diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/COPYING linux/COPYING
--- linux.orig/COPYING	2001-10-09 22:00:06.000000000 +0000
+++ linux/COPYING	2002-08-01 06:42:28.000000000 +0000
@@ -307,7 +307,7 @@
 the "copyright" line and a pointer to where the full notice is found.
 
     <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) 19yy  <name of author>
+    Copyright (C) <year>  <name of author>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -329,7 +329,7 @@
 If the program is interactive, make it output a short notice like this
 when it starts in an interactive mode:
 
-    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision version 69, Copyright (C) year name of author
     Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
     This is free software, and you are welcome to redistribute it
     under certain conditions; type `show c' for details.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/CREDITS linux/CREDITS
--- linux.orig/CREDITS	2002-02-25 19:37:50.000000000 +0000
+++ linux/CREDITS	2002-08-01 06:42:33.000000000 +0000
@@ -198,12 +198,10 @@
 S: USA
 
 N: Greg Banks
-E: gnb@linuxfan.com
+E: gnb@alphalink.com.au
 D: IDT77105 ATM network driver
-S: NEC Australia
-S: 649-655 Springvale Rd
-S: Mulgrave, Victoria 3170
-S: Australia
+D: some SuperH port work
+D: some trivial futzing with kconfig
 
 N: James Banks
 E: james@sovereign.org
@@ -586,8 +584,15 @@
 S: University of Michigan
 S: Ann Arbor, MI
 
+N: Michael Cornwell
+E: cornwell@acm.org
+D: Original designer and co-author of ATA Taskfile
+D: Kernel module SMART utilities
+S: Santa Cruz, California
+S: USA
+
 N: Kees Cook
-E: cook@cpoint.net
+E: kees@outflux.net
 W: http://outflux.net/
 P: 1024D/17063E6D 9FA3 C49C 23C9 D1BC 2E30  1975 1FFF 4BA9 1706 3E6D
 D: Minor updates to SCSI code for the Communications type
@@ -628,6 +633,11 @@
 S: NN1 3QT
 S: United Kingdom
 
+N: Stephane Dalton
+E: sdalton@videotron.ca
+D: Tieman Voyager USB Braille display driver.
+S: Québec, Canada
+
 N: Uwe Dannowski
 E: Uwe.Dannowski@ira.uka.de
 W: http://i30www.ira.uka.de/~dannowsk/
@@ -734,6 +744,11 @@
 W: http://www.fsmlabs.com/linuxppcbk.html
 D: PowerPC
 
+N: Stéphane Doyon
+E: s.doyon@videotron.ca
+D: Tieman Voyager USB Braille display driver.
+S: Québec, Canada
+
 N: Oleg Drokin
 E: green@ccssu.crimea.ua
 W: http://www.ccssu.crimea.ua/~green
@@ -1184,22 +1199,19 @@
 
 N: Andre Hedrick
 E: andre@linux-ide.org
-E: andre@aslab.com
-E: andre@suse.com
+E: andre@linuxdiskcert.org
 W: http://www.linux-ide.org/
+W: http://www.linuxdiskcert.org/
 D: Random SMP kernel hacker...
 D: Uniform Multi-Platform E-IDE driver
 D: Active-ATA-Chipset maddness..........
-D: Ultra DMA 100/66/33
-D: ATA-Disconnect
+D: Ultra DMA 133/100/66/33 w/48-bit Addressing
+D: ATA-Disconnect, ATA-TCQ
 D: ATA-Smart Kernel Daemon
+D: Serial ATA
+D: ATA Command Block and Taskfile
 S: Linux ATA Development (LAD)
 S: Concord, CA
-S: ASL, Inc. 1-877-ASL-3535
-S: 1757 Houret Court, Milpitas, CA 95035
-S: SuSE Linux, Inc.
-S: 580 Second Street, Suite 210  Oakland, CA  94607
-S: USA
 
 N: Jochen Hein
 E: jochen@jochen.org
@@ -1500,6 +1512,13 @@
 S: 602 00 Brno
 S: Czech Republic
 
+N: Jakob Kemi
+E: jakob.kemi@telia.com
+D: V4L W9966 Webcam driver
+S: Forsbyvägen 33
+S: 74143 Knivsta
+S: Sweden
+
 N: Fred N. van Kempen
 E: waltje@linux.com
 D: NET-2
@@ -1574,8 +1593,10 @@
 S: Luxembourg
 
 N: Gerd Knorr
-E: kraxel@goldbach.in-berlin.de
-D: SCSI CD-ROM driver hacking, vesafb, v4l, minor bug fixes
+W: http://bytesex.org
+E: kraxel@bytesex.org
+E: kraxel@suse.de
+D: video4linux, bttv, vesafb, some scsi, misc fixes
 
 N: Harald Koenig
 E: koenig@tat.physik.uni-tuebingen.de
@@ -1652,6 +1673,14 @@
 S: San Antonio, Texas 78269-1886
 S: USA
 
+N: Denis O. Kropp
+E: dok@directfb.org
+D: NeoMagic framebuffer driver
+D: CyberPro 32 bit support, fixes
+S: Badensche Str. 46
+S: 10715 Berlin
+S: Germany
+
 N: Andrzej M. Krzysztofowicz
 E: ankry@mif.pg.gda.pl
 D: Some 8-bit XT disk driver and devfs hacking 
@@ -1661,13 +1690,6 @@
 S: 80-283 Gdansk
 S: Poland
 
-N: Jakob Kemi
-E: jakob.kemi@telia.com
-D: V4L W9966 Webcam driver
-S: Forsbyvägen 33
-S: 74143 Knivsta
-S: Sweden
-
 N: Gero Kuhlmann
 E: gero@gkminix.han.de
 D: mounting root via NFS
@@ -1895,13 +1917,14 @@
 S: USA
 
 N: Petko Manolov
-E: petkan@dce.bg
-D: USB ethernet (pegasus) driver
-D: optimizing i[45]86 string routines
-D: i386 task swithing hacks
-S: 5, Vrah Mancho str.
-S: 1324 Sofia
-S: Bulgaria
+E: petkan@users.sourceforge.net
+D: USB ethernet pegasus/pegasus-II driver
+D: USB ethernet rtl8150 driver
+D: i[45]86 optimized string routines
+D: i386 task switching hacks
+S: 482 Shadowgraph Dr.
+S: San Jose, CA  95110
+S: USA
 
 N: Martin Mares
 E: mj@ucw.cz
@@ -2130,6 +2153,10 @@
 S: Fullarton 5063
 S: South Australia
 
+N. Wolfgang Muees
+E: wmues@nexgo.de
+D: Auerswald USB driver
+
 N: Ian A. Murdock
 E: imurdock@gnu.ai.mit.edu
 D: Creator of Debian distribution
@@ -2513,6 +2540,7 @@
 
 N: Thiago Berlitz Rondon
 E: maluco@mileniumnet.com.br
+W: http://vivaldi.linuxms.com.br/~maluco
 D: Miscellaneous kernel hacker
 S: R. Anhanguera, 1487 - Ipiranga
 S: 79080-740 - Campo Grande - Mato Grosso do Sul
@@ -2741,6 +2769,10 @@
 E: x@xman.org
 D: Tulip net driver hacker
 
+N: Mark Smith
+E: mark.smith@comdev.cc
+D: Multicast support in bonding driver
+
 N: Miquel van Smoorenburg
 E: miquels@cistron.nl
 D: Kernel and net hacker. Sysvinit, minicom. doing Debian stuff.
@@ -3265,9 +3297,10 @@
 S: USA
 
 N: Richard Zidlicky
-E: rdzidlic@geocities.com,rdzidlic@cip.informatik.uni-erlangen.de
-W: http://www.geocities.com/SiliconValley/Bay/2602/
+E: rz@linux-m68k.org, rdzidlic@geocities.com
+W: http://www.geocities.com/rdzidlic
 D: Q40 port - see arch/m68k/q40/README
+D: various m68k hacks
 S: Germany
 
 N: Werner Zimmermann
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/Changes linux/Documentation/Changes
--- linux.orig/Documentation/Changes	2001-12-21 17:41:53.000000000 +0000
+++ linux/Documentation/Changes	2002-08-01 06:42:47.000000000 +0000
@@ -31,7 +31,7 @@
 Eine deutsche Version dieser Datei finden Sie unter
 <http://www.stefan-winter.de/Changes-2.4.0.txt>.
 
-Last updated: May 9, 2001
+Last updated: February 13, 2002
 
 Chris Ricker (kaboom@gatech.edu or chris.ricker@genetics.utah.edu).
 
@@ -54,7 +54,8 @@
 o  util-linux             2.10o                   # fdformat --version
 o  modutils               2.4.2                   # insmod -V
 o  e2fsprogs              1.25                    # tune2fs
-o  reiserfsprogs          3.x.0j                  # reiserfsck 2>&1|grep reiserfsprogs
+o  jfsutils               1.0.12                  # fsck.jfs -V
+o  reiserfsprogs          3.x.1b                  # reiserfsck 2>&1|grep reiserfsprogs
 o  pcmcia-cs              3.1.21                  # cardmgr -V
 o  PPP                    2.4.0                   # pppd --version
 o  isdn4k-utils           3.1pre1                 # isdnctrl 2>&1|grep version
@@ -70,9 +71,9 @@
 necessarily to users of other CPUs. Users of other CPUs should obtain
 information about their gcc version requirements from another source.
 
-The recommended compiler for the kernel is gcc 2.95.3 or .4, and it
+The recommended compiler for the kernel is gcc 2.95.x (x >= 3), and it
 should be used when you need absolute stability. You may use gcc 3.0.x
-instead if you wish, although it may cause problems. Later  versions of gcc 
+instead if you wish, although it may cause problems. Later versions of gcc 
 have not received much testing for Linux kernel compilation, and there are 
 almost certainly bugs (mainly, but not exclusively, in the kernel) that
 will need to be fixed in order to use these compilers. In any case, using
@@ -106,14 +107,14 @@
 your kernel.  This change does, however, mean that you need a recent
 release of binutils.
 
-If you can, upgrade to the latest 2.9.5 or 2.10 binutils release.  Older
+If you can, upgrade to the latest 2.9.5 or 2.1x binutils release.  Older
 releases such as 2.8, 2.8.xx, and the FSF's 2.9.1 should be avoided if
 at all possible.  The later releases of 2.9.1.0.x (anything where x >= 22)
 can and do compile the kernel properly, but there are many benefits in
-upgrading to 2.9.5 or 2.10 if you're up to it.
+upgrading to 2.9.5 or 2.1x if you're up to it.
 
-System utils
-============
+System utilities
+================
 
 Architectural changes
 ---------------------
@@ -171,6 +172,16 @@
 The latest version of e2fsprogs fixes several bugs in fsck and
 debugfs.  Obviously, it's a good idea to upgrade.
 
+JFSutils
+--------
+
+The jfsutils package contains the utilities for the file system.
+The following utilities are available:
+o fsck.jfs - initiate replay of the transaction log, and check
+  and repair a JFS formatted partition.
+o mkfs.jfs - create a JFS formatted partition.
+o other file system utilities are also available in this package.
+
 Reiserfsprogs
 -------------
 
@@ -267,8 +278,8 @@
 Getting updated software
 ========================
 
-Compilers
-*********
+Kernel compilation
+******************
 
 egcs 1.1.2 (gcc 2.91.66)
 ------------------------
@@ -276,32 +287,22 @@
 
 gcc 2.95.3
 ----------
-o  <ftp://ftp.gnu.org/pub/gnu/gcc/gcc-2.95.3.tar.gz>
-
-Gnu Make
-********
+o  <ftp://ftp.gnu.org/gnu/gcc/gcc-2.95.3.tar.gz>
 
 Make 3.77
 ---------
 o  <ftp://ftp.gnu.org/gnu/make/make-3.77.tar.gz>
 
 Binutils
-********
-
-2.9.1 series
-------------
-o  <ftp://ftp.valinux.com/pub/support/hjl/binutils/2.9.1/binutils-2.9.1.0.25.tar.gz>
-
-2.9.5 and 2.10 series
----------------------
-o  <ftp://ftp.valinux.com/pub/support/hjl/binutils/>
+--------
+o  <ftp://ftp.kernel.org/pub/linux/devel/binutils/>
 
 System utilities
 ****************
 
 Util-linux
 ----------
-o  <ftp://ftp.kernel.org/pub/linux/utils/util-linux/util-linux-2.10o.tar.gz>
+o  <ftp://ftp.kernel.org/pub/linux/utils/util-linux/>
 
 Ksymoops
 --------
@@ -319,9 +320,13 @@
 ---------
 o  <http://prdownloads.sourceforge.net/e2fsprogs/e2fsprogs-1.25.tar.gz>
 
+JFSutils
+---------
+o  <http://oss.software.ibm.com/jfs/>
+
 Reiserfsprogs
 -------------
-o  <ftp://ftp.namesys.com/pub/reiserfsprogs/reiserfsprogs-3.x.0j.tar.gz>
+o  <ftp://ftp.namesys.com/pub/reiserfsprogs/reiserfsprogs-3.x.1b.tar.gz>
 
 LVM toolset
 -----------
@@ -345,10 +350,10 @@
 
 Powertweak
 ----------
-o  <http://powertweak.sourceforge.net>
+o  <http://powertweak.sourceforge.net/>
 
-Network
-*******
+Networking
+**********
 
 PPP
 ---
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/Configure.help linux/Documentation/Configure.help
--- linux.orig/Documentation/Configure.help	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/Configure.help	2002-08-01 06:42:47.000000000 +0000
@@ -2,7 +2,7 @@
 #	Eric S. Raymond <mailto:esr@thyrsus.com>
 #	Steven Cole <mailto:elenstev@mesatop.com>
 #
-# Merged version 2.69: current with 2.4.17-pre8/2.5.1-pre10.
+# Version 3.00: current with 2.4.19
 #
 # This version of the Linux kernel configuration help texts
 # corresponds to kernel versions 2.4.x and 2.5.x.
@@ -31,7 +31,7 @@
 #
 # Information about what a kernel is, what it does, how to patch and
 # compile it and much more is contained in the Kernel-HOWTO, available
-# at <http://www.linuxdoc.org/docs.html#howto>. Before you start
+# at <http://www.tldp.org/docs.html#howto>. Before you start
 # compiling, make sure that you have the necessary versions of all
 # programs and libraries required to compile and run this kernel; they
 # are listed in the <file:Documentation/Changes>. Make sure to read the
@@ -58,7 +58,7 @@
 #
 # Mention all the relevant READMEs and HOWTOs in the help text.
 # Make them file URLs relative to the top level of the source tree so
-# that help browsers can turn them into hotlinks.  All URLs ahould be
+# that help browsers can turn them into hotlinks.  All URLs should be
 # surrounded by <>.
 #
 # Repetitions are fine since the help texts are not meant to be read
@@ -121,7 +121,7 @@
   If you say N here, the kernel will run on single and multiprocessor
   machines, but will use only one CPU of a multiprocessor machine. If
   you say Y here, the kernel will run on many, but not all,
-  singleprocessor machines. On a singleprocessor machine, the kernel
+  single machines. On a singleprocessor machine, the kernel
   will run faster if you say N here.
 
   Note that if you say Y here and choose architecture "586" or
@@ -136,7 +136,7 @@
   See also the <file:Documentation/smp.tex>,
   <file:Documentation/smp.txt>, <file:Documentation/i386/IO-APIC.txt>,
   <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you don't know what to do here, say N.
 
@@ -277,7 +277,7 @@
 
   If you don't have a math coprocessor, you need to say Y here; if you
   say Y here even though you have a coprocessor, the coprocessor will
-  be used nevertheless. (This behavior can be changed with the kernel
+  be used nevertheless. (This behaviour can be changed with the kernel
   command line option "no387", which comes handy if your coprocessor
   is broken. Try "man bootparam" or see the documentation of your boot
   loader (lilo or loadlin) about how to pass options to the kernel at
@@ -490,6 +490,23 @@
 
   Most users will answer N here.
 
+Micro Memory MM5415 Battery Backed RAM support (EXPERIMENTAL)
+CONFIG_BLK_DEV_UMEM
+  Saying Y here will include support for the MM5415 family of
+  battery backed (Non-volatile) RAM cards.
+  http://www.umem.com/
+
+  The cards appear as block devices that can be partitioned into
+  as many as 15 partitions.
+
+  If you want to compile this driver as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want),
+  say M here and read Documentation/modules.txt. The module will be
+  called umem.o.
+
+  The umem driver has been allocated block major number 116.
+  See Documentation/devices.txt for recommended device naming.
+
 Network block device support
 CONFIG_BLK_DEV_NBD
   Saying Y here will allow your computer to be a client for network
@@ -575,7 +592,7 @@
   topics, is contained in <file:Documentation/ide.txt>. For detailed
   information about hard drives, consult the Disk-HOWTO and the
   Multi-Disk-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   To fine-tune ATA/IDE drive/interface parameters for improved
   performance, look for the hdparm package at
@@ -608,7 +625,7 @@
   If you are unsure, then just choose the Enhanced IDE/MFM/RLL driver
   instead of this one. For more detailed information, read the
   Disk-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 Use old disk-only driver on primary interface
 CONFIG_BLK_DEV_HD_IDE
@@ -723,6 +740,59 @@
   say M here and read <file:Documentation/modules.txt>.  The module
   will be called ide-floppy.o.
 
+AWARD Bios Work-Around
+CONFIG_IDEDISK_STROKE
+  Should you have a system w/ an AWARD Bios and your drives are larger
+  than 32GB and it will not boot, one is required to perform a few OEM
+  operations first.  The option is called "STROKE" because it allows
+  one to "soft clip" the drive to work around a barrier limit.  For
+  Maxtor drives it is called "jumpon.exe".  Please search Maxtor's
+  web-site for "JUMPON.EXE".  IBM has a similar tool at:
+  <http://www.storage.ibm.com/hdd/support/download.htm>.
+
+  If you are unsure, say N here.
+
+Raw Access to Media
+CONFIG_IDE_TASK_IOCTL
+  This is a direct raw access to the media.  It is a complex but
+  elegant solution to test and validate the domain of the hardware and
+  perform below the driver data recover if needed.  This is the most
+  basic form of media-forensics.
+
+  If you are unsure, say N here.
+
+Use Taskfile I/O
+CONFIG_IDE_TASKFILE_IO
+  This is the "Jewel" of the patch.  It will go away and become the new
+  driver core.  Since all the chipsets/host side hardware deal w/ their
+  exceptions in "their local code" currently, adoption of a
+  standardized data-transport is the only logical solution.
+  Additionally we packetize the requests and gain rapid performance and
+  a reduction in system latency.  Additionally by using a memory struct
+  for the commands we can redirect to a MMIO host hardware in the next
+  generation of controllers, specifically second generation Ultra133
+  and Serial ATA.
+
+  Since this is a major transition, it was deemed necessary to make the
+  driver paths buildable in separate models.  Therefore if using this
+  option fails for your arch then we need to address the needs for that
+  arch.
+
+  If you want to test this functionality, say Y here.
+
+Force DMA
+CONFIG_BLK_DEV_IDEDMA_FORCED
+  This is an old piece of lost code from Linux 2.0 Kernels.
+
+  Generally say N here.
+
+DMA Only on Disks
+CONFIG_IDEDMA_ONLYDISK
+  This is used if you know your ATAPI Devices are going to fail DMA
+  Transfers.
+
+  Generally say N here.
+
 SCSI emulation support
 CONFIG_BLK_DEV_IDESCSI
   This will provide SCSI host adapter emulation for IDE ATAPI devices,
@@ -747,6 +817,14 @@
   If both this SCSI emulation and native ATAPI support are compiled
   into the kernel, the native support will be used.
 
+Use the NOOP Elevator (WARNING)
+CONFIG_BLK_DEV_ELEVATOR_NOOP
+  If you are using a raid class top-level driver above the ATA/IDE core,
+  one may find a performance boost by preventing a merging and re-sorting
+  of the new requests.
+
+  If unsure, say N.
+
 ISA-PNP EIDE support
 CONFIG_BLK_DEV_ISAPNP
   If you have an ISA EIDE card that is PnP (Plug and Play) and
@@ -906,7 +984,7 @@
 
   It is SAFEST to say N to this question.
 
-Asyncronious DMA support (EXPERIMENTAL)
+Asynchronous DMA support (EXPERIMENTAL)
 CONFIG_BLK_DEV_ADMA
   Please read the comments at the top of
   <file:drivers/ide/ide-adma.c>.
@@ -1028,7 +1106,7 @@
 
   If unsure, say N.
 
-HPT366 chipset support
+HPT366/368/370 chipset support
 CONFIG_BLK_DEV_HPT366
   HPT366 is an Ultra DMA chipset for ATA-66.
   HPT368 is an Ultra DMA chipset for ATA-66 RAID Based.
@@ -1122,7 +1200,7 @@
 
   It was originally designed for the PDC20246/Ultra33, whose BIOS will
   only setup UDMA on the first two PDC20246 cards.  It has also been
-  used succesfully on a PDC20265/Ultra100, allowing use of UDMA modes
+  used successfully on a PDC20265/Ultra100, allowing use of UDMA modes
   when the PDC20265 BIOS has been disabled (for faster boot up).
 
   Please read the comments at the top of
@@ -1136,9 +1214,15 @@
 
 SiS5513 chipset support
 CONFIG_BLK_DEV_SIS5513
-  This driver ensures (U)DMA support for SIS5513 chipset based
-  mainboards. SiS620/530 UDMA mode 4, SiS5600/5597 UDMA mode 2, all
-  other DMA mode 2 limited chipsets are unsupported to date.
+  This driver ensures (U)DMA support for SIS5513 chipset family based
+  mainboards.
+
+  The following chipsets are supported:
+  ATA16:  SiS5511, SiS5513
+  ATA33:  SiS5591, SiS5597, SiS5598, SiS5600
+  ATA66:  SiS530, SiS540, SiS620, SiS630, SiS640
+  ATA100: SiS635, SiS645, SiS650, SiS730, SiS735, SiS740,
+          SiS745, SiS750
 
   If you say Y here, you need to say Y to "Use DMA by default when
   available" as well.
@@ -1709,7 +1793,7 @@
 
   More information about Software RAID on Linux is contained in the
   Software RAID mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. There you will also learn
+  <http://www.tldp.org/docs.html#howto>. There you will also learn
   where to get the supporting user space utilities raidtools.
 
   If unsure, say N.
@@ -1737,7 +1821,7 @@
 
   Information about Software RAID on Linux is contained in the
   Software-RAID mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. There you will also
+  <http://www.tldp.org/docs.html#howto>. There you will also
   learn where to get the supporting user space utilities raidtools.
 
   If you want to compile this as a module ( = code which can be
@@ -1759,7 +1843,7 @@
 
   Information about Software RAID on Linux is contained in the
   Software-RAID mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  There you will also
+  <http://www.tldp.org/docs.html#howto>.  There you will also
   learn where to get the supporting user space utilities raidtools.
 
   If you want to use such a RAID-1 set, say Y. This code is also
@@ -1782,7 +1866,7 @@
 
   Information about Software RAID on Linux is contained in the
   Software-RAID mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. There you will also
+  <http://www.tldp.org/docs.html#howto>. There you will also
   learn where to get the supporting user space utilities raidtools.
 
   If you want to use such a RAID-4/RAID-5 set, say Y. This code is
@@ -1809,7 +1893,7 @@
   to use its softwareraid feature.  You must also select an
   appropriate for your board low-level driver below.
 
-  Note, that Linux does not use the Raid implemetation in BIOS, and
+  Note, that Linux does not use the Raid implementation in BIOS, and
   the main purpose for this feature is to retain compatibility and
   data integrity with other OS-es, using the same disk array. Linux
   has its own Raid drivers, which you should use if you need better
@@ -1982,6 +2066,11 @@
   which allows for more memory.  Your system is most probably
   running in M-Mode, so you should say N here.
 
+Lasi Ethernet
+CONFIG_LASI_82596
+  Say Y here to support the on-board Intel 82596 ethernet controller
+  built into Hewlett-Packard PA-RISC machines.
+
 MIPS JAZZ onboard SONIC Ethernet support
 CONFIG_MIPS_JAZZ_SONIC
   This is the driver for the onboard card of MIPS Magnum 4000,
@@ -2012,7 +2101,7 @@
 
 Kernel floating-point instruction emulation
 CONFIG_MIPS_FPU_EMULATOR
-  This option enables the MIPS software floatingpoint support.  Due to
+  This option enables the MIPS software floating support.  Due to
   the way floating point works you should always enable this option
   unless you exactly know what you're doing.
 
@@ -2171,7 +2260,7 @@
 
 Discontiguous Memory Support
 CONFIG_DISCONTIGMEM
-  Say Y to upport efficient handling of discontiguous physical memory,
+  Say Y to support efficient handling of discontiguous physical memory,
   for architectures which are either NUMA (Non-Uniform Memory Access)
   or have huge holes in the physical address space for other reasons.
   See <file:Documentation/vm/numa> for more.
@@ -2180,7 +2269,7 @@
 CONFIG_MAPPED_KERNEL
   Change the way a Linux kernel is loaded unto memory on a MIPS64
   machine.  This is required in order to support text replication and
-  NUMA.  If you need to undersatand it, read the source code.
+  NUMA.  If you need to understand it, read the source code.
 
 Kernel text replication support
 CONFIG_REPLICATE_KTEXT
@@ -2250,7 +2339,7 @@
 Use power LED as a heartbeat
 CONFIG_HEARTBEAT
   Use the power-on LED on your machine as a load meter.  The exact
-  behavior is platform-dependent, but normally the flash frequency is
+  behaviour is platform-dependent, but normally the flash frequency is
   a hyperbolic function of the 5-minute load average.
 
 Networking support
@@ -2266,7 +2355,7 @@
 
   For a general introduction to Linux networking, it is highly
   recommended to read the NET-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 Socket filtering
 CONFIG_FILTER
@@ -2513,6 +2602,19 @@
   If you want to compile it as a module, say M here and read
   <file:Documentation/modules.txt>.  If unsure, say `N'.
 
+Local NAT support
+CONFIG_IP_NF_NAT_LOCAL
+  This option enables support for NAT of locally originated connections. 
+  Enable this if you need to use destination NAT on connections
+  originating from local processes on the nat box itself.
+
+  Please note that you will need a recent version (>= 1.2.6a)
+  of the iptables userspace program in order to use this feature.
+  See http://www.iptables.org/ for download instructions.
+
+  If unsure, say 'N'.
+
+
 Full NAT (Network Address Translation)
 CONFIG_IP_NF_NAT
   The Full NAT option allows masquerading, port forwarding and other
@@ -2582,7 +2684,7 @@
   associated with the packet prior to routing. This can change
   the routing method (see `Use netfilter MARK value as routing
   key') and can also be used by other subsystems to change their
-  behavior.
+  behaviour.
 
   If you want to compile it as a module, say M here and read
   <file:Documentation/modules.txt>.  If unsure, say `N'.
@@ -2628,7 +2730,7 @@
   daemon using netlink multicast sockets; unlike the LOG target
   which can only be viewed through syslog.
 
-  The apropriate userspace logging daemon (ulogd) may be obtained from
+  The appropriate userspace logging daemon (ulogd) may be obtained from
   http://www.gnumonks.org/projects/ulogd
 
   If you want to compile it as a module, say M here and read
@@ -2740,7 +2842,7 @@
   associated with the packet packet prior to routing. This can change
   the routing method (see `Use netfilter MARK value as routing
   key') and can also be used by other subsystems to change their
-  behavior.
+  behaviour.
 
   If you want to compile it as a module, say M here and read
   <file:Documentation/modules.txt>.  If unsure, say `N'.
@@ -2824,14 +2926,6 @@
 
   If unsure, say N.
 
-HCI EMU (virtual device) driver
-CONFIG_BLUEZ_HCIEMU
-  Bluetooth Virtual HCI device driver.
-  This driver is required if you want to use HCI Emulation software.
-
-  Say Y here to compile support for Virtual HCI devices into the
-  kernel or say M to compile it as module (hci_usb.o).
-
 # Choice: alphatype
 Alpha system type
 CONFIG_ALPHA_GENERIC
@@ -3104,20 +3198,12 @@
   Say Y here if you have dumb serial boards other than the four
   standard COM 1/2/3/4 ports. This may happen if you have an AST
   FourPort, Accent Async, Boca (read the Boca mini-HOWTO, available
-  from <http://www.linuxdoc.org/docs.html#howto>), or other custom
+  from <http://www.tldp.org/docs.html#howto>), or other custom
   serial port hardware which acts similar to standard serial port
   hardware. If you only use the standard COM 1/2/3/4 ports, you can
   say N here to save some memory. You can also say Y if you have an
   "intelligent" multiport card such as Cyclades, Digiboards, etc.
 
-Support for serial ports defined by ACPI tables
-CONFIG_SERIAL_ACPI
-  Legacy free machines may not have serial ports at the legacy COM1, 
-  COM2 etc addresses. Serial ports on such machines are described by
-  the ACPI tables SPCR (Serial Port Console Redirection) table and 
-  DBGP (Debug Port) table. Say Y here if you want to include support
-  for these serial ports.
-
 Support for sharing serial interrupts
 CONFIG_SERIAL_SHARE_IRQ
   Some serial boards have hardware support which allows multiple dumb
@@ -3167,6 +3253,13 @@
   via the file /proc/rtc and its behaviour is set by various ioctls on
   /dev/rtc.
 
+Indy/I2 Hardware Watchdog
+CONFIG_INDYDOG
+  Hardwaredriver for the Indy's/I2's watchdog. This is a
+  watchdog timer that will reboot the machine after a 60 second 
+  timer expired and no process has written to /dev/watchdog during
+  that time.
+
 Support the Bell Technologies HUB6 card
 CONFIG_HUB6
   Say Y here to enable support in the dumb serial driver to support
@@ -3307,6 +3400,10 @@
   You should say Y here if you use XFree86 3.3.6 or 4.x and want to
   use GLX or DRI.  If unsure, say N.
 
+CONFIG_AGP_HP_ZX1
+  This option gives you AGP GART support for the HP ZX1 chipset
+  for IA64 processors.
+
 Support for ISA-bus hardware
 CONFIG_ISA
   Find out whether you have ISA slots on your motherboard.  ISA is the
@@ -3323,7 +3420,7 @@
   VESA. If you have PCI, say Y, otherwise N.
 
   The PCI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, contains valuable
+  <http://www.tldp.org/docs.html#howto>, contains valuable
   information about which PCI hardware does work under Linux and which
   doesn't.
 
@@ -3335,7 +3432,7 @@
   VESA. If you have PCI, say Y, otherwise N.
 
   The PCI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, contains valuable
+  <http://www.tldp.org/docs.html#howto>, contains valuable
   information about which PCI hardware does work under Linux and which
   doesn't.
 
@@ -3347,7 +3444,7 @@
   VESA. If you have PCI, say Y, otherwise N.
 
   The PCI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, contains valuable
+  <http://www.tldp.org/docs.html#howto>, contains valuable
   information about which PCI hardware does work under Linux and which
   doesn't.
 
@@ -3602,7 +3699,7 @@
   To use your PC-cards, you will need supporting software from David
   Hinds' pcmcia-cs package (see the file <file:Documentation/Changes>
   for location).  Please also read the PCMCIA-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -3656,12 +3753,12 @@
   and some programs won't run unless you say Y here. In particular, if
   you want to run the DOS emulator dosemu under Linux (read the
   DOSEMU-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>), you'll need to say Y
+  <http://www.tldp.org/docs.html#howto>), you'll need to say Y
   here.
 
   You can find documentation about IPC with "info ipc" and also in
   section 6.4 of the Linux Programmer's Guide, available from
-  <http://www.linuxdoc.org/docs.html#guide>.
+  <http://www.tldp.org/docs.html#guide>.
 
 BSD Process Accounting
 CONFIG_BSD_PROCESS_ACCT
@@ -3730,7 +3827,7 @@
   want to say Y here.
 
   Information about ELF is contained in the ELF HOWTO available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you find that after upgrading from Linux kernel 1.2 and saying Y
   here, you still can't run any ELF binaries (they just crash), then
@@ -3765,6 +3862,12 @@
   because some crucial programs on your system might still be in A.OUT
   format.
 
+OSF/1 v4 readv/writev compatibility
+CONFIG_OSF4_COMPAT
+  Say Y if you are using OSF/1 binaries (like Netscape and Acrobat)
+  with v4 shared libraries freely available from Compaq. If you're
+  going to use shared libraries from Tru64 version 5.0 or later, say N.
+
 Kernel support for Linux/Intel ELF binaries
 CONFIG_BINFMT_EM86
   Say Y here if you want to be able to execute Linux/Intel ELF
@@ -3790,7 +3893,7 @@
   programs that need an interpreter to run like Java, Python or
   Emacs-Lisp. It's also useful if you often run DOS executables under
   the Linux DOS emulator DOSEMU (read the DOSEMU-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>). Once you have
+  <http://www.tldp.org/docs.html#howto>). Once you have
   registered such a binary class with the kernel, you can start one of
   those programs simply by typing in its name at a shell prompt; Linux
   will automatically feed it to the correct interpreter.
@@ -4207,6 +4310,16 @@
   This driver supports the L7200 Color LCD.
   Say Y if you want graphics support.
 
+NeoMagic display support (EXPERIMENTAL)
+CONFIG_FB_NEOMAGIC
+  This driver supports notebooks with NeoMagic PCI chips.
+  Say Y if you have such a graphics card. 
+
+  The driver is also available as a module ( = code which can be
+  inserted and removed from the running kernel whenever you want). The
+  module will be called neofb.o. If you want to compile it as a
+  module, say M here and read Documentation/modules.txt.
+
 PowerMac "control" frame buffer device support
 CONFIG_FB_CONTROL
   This driver supports a frame buffer for the graphics adapter in the
@@ -4414,7 +4527,8 @@
 CONFIG_FB_MATROX
   Say Y here if you have a Matrox Millennium, Millennium II, Mystique,
   Mystique 220, Productiva G100, Mystique G200, Millennium G200,
-  Marvel G200 video, G400, G450, or G550 card in your box.
+  Matrox G400, G450 or G550 card in your box. At this time, support for 
+  the G-series digital output is almost non-existant.
 
   This driver is also available as a module ( = code which can be
   inserted and removed from the running kernel whenever you want).
@@ -4453,6 +4567,10 @@
   "I2C support" and "I2C bit-banging support" in the character devices
   section, and then to "Matrox I2C support" and "G400 second head
   support" here in the framebuffer section.
+  
+  If you have G550, you must also compile support for G450/G550 secondary
+  head into kernel, otherwise picture will be shown only on the output you
+  are probably not using...
 
   If you need support for G450 or G550 secondary head, say Y to
   "Matrox G450/G550 second head support" below.
@@ -4503,7 +4621,8 @@
 Matrox G450 second head support
 CONFIG_FB_MATROX_G450
   Say Y or M here if you want to use a secondary head (meaning two
-  monitors in parallel) on G450 or G550.
+  monitors in parallel) on G450, or if you are using analog output
+  of G550.
 
   If you compile it as module, two modules are created,
   matroxfb_crtc2.o and matroxfb_g450.o. Both modules are needed if you
@@ -4645,6 +4764,12 @@
   The IMS Twin Turbo is a PCI-based frame buffer card bundled with
   many Macintosh and compatible computers.
 
+CONFIG_FB_TX3912
+  The TX3912 is a Toshiba RISC processor based on the MIPS 3900 core;
+  see <http://www.toshiba.com/taec/components/Generic/risc/tx3912.htm>.
+
+  Say Y here to enable kernel support for the on-board framebuffer.
+
 Virtual Frame Buffer support (ONLY FOR TESTING!)
 CONFIG_FB_VIRTUAL
   This is a `virtual' frame buffer device. It operates on a chunk of
@@ -4796,6 +4921,13 @@
   bits per pixel packed pixels on Mac. It supports variable font
   widths for low resolution screens.
 
+Permedia3 support (EXPERIMENTAL)
+CONFIG_FB_PM3
+  This is the frame buffer device driver for the 3DLabs Permedia3
+  chipset, used in Formac ProFormance III, 3DLabs Oxygen VX1 &
+  similar boards, 3DLabs Permedia3 Create!, Appian Jeronimo 2000
+  and maybe other boards.
+
 HGA monochrome support
 CONFIG_FBCON_HGA
   This is the low level frame buffer console driver for Hercules mono
@@ -4985,7 +5117,7 @@
 
   For an excellent introduction to Linux networking, please read the
   NET-3-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This option is also necessary if you want to use the full power of
   term (term is a program which gives you almost full Internet
@@ -4995,7 +5127,7 @@
 
   If you say Y here and also to "/proc file system support" and
   "Sysctl support" below, you can change various aspects of the
-  behavior of the TCP/IP code by writing to the (virtual) files in
+  behaviour of the TCP/IP code by writing to the (virtual) files in
   /proc/sys/net/ipv4/*; the options are explained in the file
   <file:Documentation/networking/ip-sysctl.txt>.
 
@@ -5307,7 +5439,7 @@
   Novell client ncpfs (available from
   <ftp://platan.vc.cvut.cz/pub/linux/ncpfs/>) or from
   within the Linux DOS emulator DOSEMU (read the DOSEMU-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>).  In order
+  available from <http://www.tldp.org/docs.html#howto>).  In order
   to do the former, you'll also have to say Y to "NCP file system
   support", below.
 
@@ -5320,7 +5452,7 @@
   <ftp://ibiblio.org/pub/Linux/system/network/daemons/> or
   mars_nwe from <ftp://www.compu-art.de/mars_nwe/>. For more
   information, read the IPX-HOWTO available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   General information about how to connect Linux, Windows machines and
   Macs is on the WWW at <http://www.eats.com/linux_mac_win.html>.
@@ -5341,7 +5473,7 @@
   same address). The way this is done is to create a virtual internal
   "network" inside your box and to assign an IPX address to this
   network. Say Y here if you want to do this; read the IPX-HOWTO at
-  <http://www.linuxdoc.org/docs.html#howto> for details.
+  <http://www.tldp.org/docs.html#howto> for details.
 
   The full internal IPX network enables you to allocate sockets on
   different virtual nodes of the internal network. This is done by
@@ -5376,7 +5508,7 @@
   space programs lwared or mars_nwe for the server side).
 
   Say Y here if you have use for SPX; read the IPX-HOWTO at
-  <http://www.linuxdoc.org/docs.html#howto> for details.
+  <http://www.tldp.org/docs.html#howto> for details.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -5434,18 +5566,19 @@
   (see ipchains(8), "-m" argument).
 
 AppleTalk interfaces support
-CONFIG_APPLETALK
-  AppleTalk is the way Apple computers speak to each other on a
-  network. If your Linux box is connected to such a network and you
-  want to join the conversation, say Y.
+CONFIG_DEV_APPLETALK
+  AppleTalk is the protocol that Apple computers can use to communicate
+  on a network.  If your Linux box is connected to such a network, and wish
+  to do IP over it, or you have a LocalTalk card and wish to use it to
+  connect to the AppleTalk network, say Y.
 
 AppleTalk protocol support
 CONFIG_ATALK
-  AppleTalk is the way Apple computers speak to each other on a
-  network.  If your Linux box is connected to such a network and you
-  want to join the conversation, say Y.  You will need to use the
-  netatalk package so that your Linux box can act as a print and file
-  server for Macs as well as access AppleTalk printers.  Check out
+  AppleTalk is the protocol that Apple computers can use to communicate
+  on a network.  If your Linux box is connected to such a network and you
+  wish to connect to it, say Y.  You will need to use the netatalk package
+  so that your Linux box can act as a print and file server for Macs as
+  well as access AppleTalk printers.  Check out
   <http://www.zettabyte.net/netatalk/> on the WWW for details.
   EtherTalk is the name used for AppleTalk over Ethernet and the
   cheaper and slower LocalTalk is AppleTalk over a proprietary Apple
@@ -5455,7 +5588,7 @@
   General information about how to connect Linux, Windows machines and
   Macs is on the WWW at <http://www.eats.com/linux_mac_win.html>.  The
   NET-3-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, contains valuable
+  <http://www.tldp.org/docs.html#howto>, contains valuable
   information as well.
 
   This driver is also available as a module ( = code which can be
@@ -5544,7 +5677,7 @@
 CONFIG_HAMRADIO
   If you want to connect your Linux box to an amateur radio, answer Y
   here. You want to read <http://www.tapr.org/tapr/html/pkthome.html> and
-  the AX25-HOWTO, available from <http://www.linuxdoc.org/docs.html#howto>.
+  the AX25-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
 
   Note that the answer to this question won't directly affect the
   kernel: saying N will just cause the configurator to skip all
@@ -5568,7 +5701,7 @@
   Information about where to get supporting software for Linux amateur
   radio as well as information about how to configure an AX.25 port is
   contained in the AX25-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. You might also want to
+  <http://www.tldp.org/docs.html#howto>. You might also want to
   check out the file <file:Documentation/networking/ax25.txt> in the
   kernel source. More information about digital amateur radio in
   general is on the WWW at
@@ -5605,7 +5738,7 @@
   A comprehensive listing of all the software for Linux amateur radio
   users as well as information about how to configure an AX.25 port is
   contained in the AX25-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. You also might want to
+  <http://www.tldp.org/docs.html#howto>. You also might want to
   check out the file <file:Documentation/networking/ax25.txt>. More
   information about digital amateur radio in general is on the WWW at
   <http://www.tapr.org/tapr/html/pkthome.html>.
@@ -5624,7 +5757,7 @@
   A comprehensive listing of all the software for Linux amateur radio
   users as well as information about how to configure an AX.25 port is
   contained in the AX25-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  You also might want to
+  <http://www.tldp.org/docs.html#howto>.  You also might want to
   check out the file <file:Documentation/networking/ax25.txt>. More
   information about digital amateur radio in general is on the WWW at
   <http://www.tapr.org/tapr/html/pkthome.html>.
@@ -5688,7 +5821,7 @@
   Currently, this driver supports Ottawa PI/PI2, Paccomm/Gracilis
   PackeTwin, and S5SCC/DMA boards. They are detected automatically.
   If you have one of these cards, say Y here and read the AX25-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   This driver can operate multiple boards simultaneously. If you
   compile it as a module (by saying M instead of Y), it will be called
@@ -5714,7 +5847,7 @@
   in order to communicate with other computers. If you want to use
   this, read <file:Documentation/networking/z8530drv.txt> and the
   AX25-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. Also make sure to say Y
+  <http://www.tldp.org/docs.html#howto>. Also make sure to say Y
   to "Amateur Radio AX.25 Level 2" support.
 
   If you want to compile this as a module ( = code which can be
@@ -6001,7 +6134,7 @@
   Note that if your box acts as a bridge, it probably contains several
   Ethernet devices, but the kernel is not able to recognize more than
   one at boot time without help; for details read the Ethernet-HOWTO,
-  available from in <http://www.linuxdoc.org/docs.html#howto>.
+  available from in <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this code as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -6099,6 +6232,19 @@
   briefly removed during revalidation. If you say Y here, packets to
   such neighbours are silently discarded instead.
 
+RFC1483/2684 Bridged protocols
+CONFIG_ATM_BR2684
+  ATM PVCs can carry ethernet PDUs according to rfc2684 (formerly 1483)
+  This device will act like an ethernet from the kernels point of view,
+  with the traffic being carried by ATM PVCs (currently 1 PVC/device).
+  This is sometimes used over DSL lines.  If in doubt, say N.
+
+Per-VC IP filter kludge
+CONFIG_ATM_BR2684_IPFILTER
+  This is an experimental mechanism for users who need to terminating a
+  large number of IP-only vcc's.  Do not enable this unless you are sure
+  you know what you are doing.
+
 LAN Emulation (LANE) support
 CONFIG_ATM_LANE
   LAN Emulation emulates services of existing LANs across an ATM
@@ -6394,6 +6540,18 @@
   boards supported by this driver, and for further information
   on the use of this driver.
 
+SCSI tape drive support for Smart Array 5xxx
+CONFIG_CISS_SCSI_TAPE
+  When enabled (Y), this option allows SCSI tape drives and SCSI medium
+  changers (tape robots) to be accessed via a Compaq 5xxx array
+  controller.  (See Documentation/cciss.txt for more details.)
+
+  "SCSI support" and "SCSI tape support" must also be enabled for this
+  option to work.
+
+  When this option is disabled (N), the SCSI portion of the driver
+  is not compiled.
+
 QuickNet Internet LineJack/PhoneJack support
 CONFIG_PHONE_IXJ
   Say M if you have a telephony card manufactured by Quicknet
@@ -6411,6 +6569,12 @@
   If you do not have any Quicknet telephony cards, you can safely
   say N here.
 
+QuickNet Internet LineJack/PhoneJack PCMCIA support
+CONFIG_PHONE_IXJ_PCMCIA
+  Say Y here to configure in PCMCIA service support for the Quicknet
+  cards manufactured by Quicknet Technologies, Inc.  This builds an
+  additional support module for the PCMCIA version of the card.
+
 FORE Systems 200E-series
 CONFIG_ATM_FORE200E_MAYBE
   This is a driver for the FORE Systems 200E-series ATM adapter
@@ -6636,7 +6800,7 @@
   If you want to use a SCSI hard disk or the SCSI or parallel port
   version of the IOMEGA ZIP drive under Linux, say Y and read the
   SCSI-HOWTO, the Disk-HOWTO and the Multi-Disk-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. This is NOT for SCSI
+  <http://www.tldp.org/docs.html#howto>. This is NOT for SCSI
   CD-ROMs.
 
   This driver is also available as a module ( = code which can be
@@ -6680,7 +6844,7 @@
 CONFIG_CHR_DEV_ST
   If you want to use a SCSI tape drive under Linux, say Y and read the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, and
+  <http://www.tldp.org/docs.html#howto>, and
   <file:drivers/scsi/README.st> in the kernel source.  This is NOT for
   SCSI CD-ROMs.
 
@@ -6700,7 +6864,7 @@
   tape drives (ADR-x0) that supports the standard SCSI-2 commands for
   tapes (QIC-157) and can be driven by the standard driver st.
   For more information, you may have a look at the SCSI-HOWTO
-  <http://www.linuxdoc.org/docs.html#howto>  and
+  <http://www.tldp.org/docs.html#howto>  and
   <file:drivers/scsi/README.osst>  in the kernel source.
   More info on the OnStream driver may be found on
   <http://linux1.onstream.nl/test/>
@@ -6717,7 +6881,7 @@
 CONFIG_BLK_DEV_SR
   If you want to use a SCSI CD-ROM under Linux, say Y and read the
   SCSI-HOWTO and the CD-ROM-HOWTO at
-  <http://www.linuxdoc.org/docs.html#howto>. Also make sure to say Y
+  <http://www.tldp.org/docs.html#howto>. Also make sure to say Y
   or M to "ISO 9660 CD-ROM file system support" later.
 
   This driver is also available as a module ( = code which can be
@@ -6840,7 +7004,7 @@
   must be manually specified in this case.
 
   It is explained in section 3.3 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. You might also want to
+  <http://www.tldp.org/docs.html#howto>. You might also want to
   read the file <file:drivers/scsi/README.aha152x>.
 
   This driver is also available as a module ( = code which can be
@@ -6852,7 +7016,7 @@
 CONFIG_SCSI_AHA1542
   This is support for a SCSI host adapter.  It is explained in section
   3.4 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Note that Trantor was
+  <http://www.tldp.org/docs.html#howto>.  Note that Trantor was
   purchased by Adaptec, and some former Trantor products are being
   sold under the Adaptec name.  If it doesn't work out of the box, you
   may have to change some settings in <file:drivers/scsi/aha1542.h>.
@@ -6866,7 +7030,7 @@
 CONFIG_SCSI_AHA1740
   This is support for a SCSI host adapter.  It is explained in section
   3.5 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If it doesn't work out
+  <http://www.tldp.org/docs.html#howto>.  If it doesn't work out
   of the box, you may have to change some settings in
   <file:drivers/scsi/aha1740.h>.
 
@@ -6903,9 +7067,9 @@
 
   This is an upper bound value for the number of tagged transactions
   to be used for any device.  The aic7xxx driver will automatically
-  vary this number based on device behavior.  For devices with a
+  vary this number based on device behaviour.  For devices with a
   fixed maximum, the driver will eventually lock to this maximum
-  and display a console message inidicating this value.
+  and display a console message indicating this value.
 
   Note: Unless you experience some type of device failure, the default
 	value, no enforced limit, should work for you.
@@ -6962,7 +7126,7 @@
   configuration options. You should read
   <file:drivers/scsi/aic7xxx_old/README.aic7xxx> at a minimum before
   contacting the maintainer with any questions.  The SCSI-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>, can also
+  available from <http://www.tldp.org/docs.html#howto>, can also
   be of great help.
 
   If you want to compile this driver as a module ( = code which can be
@@ -7056,7 +7220,7 @@
 CONFIG_SCSI_BUSLOGIC
   This is support for BusLogic MultiMaster and FlashPoint SCSI Host
   Adapters. Consult the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, and the files
+  <http://www.tldp.org/docs.html#howto>, and the files
   <file:drivers/scsi/README.BusLogic> and
   <file:drivers/scsi/README.FlashPoint> for more information. If this
   driver does not work correctly without modification, please contact
@@ -7093,7 +7257,7 @@
 CONFIG_SCSI_DTC3280
   This is support for DTC 3180/3280 SCSI Host Adapters.  Please read
   the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, and the file
+  <http://www.tldp.org/docs.html#howto>, and the file
   <file:drivers/scsi/README.dtc3x80>.
 
   This driver is also available as a module ( = code which can be
@@ -7110,7 +7274,7 @@
   Note that this driver is obsolete; if you have one of the above
   SCSI Host Adapters, you should normally say N here and Y to "EATA
   ISA/EISA/PCI support", below.  Please read the SCSI-HOWTO, available
-  from <http://www.linuxdoc.org/docs.html#howto>.
+  from <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -7124,7 +7288,7 @@
   host adapters could also use this driver but are discouraged from
   doing so, since this driver only supports hard disks and lacks
   numerous features.  You might want to have a look at the SCSI-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -7138,7 +7302,7 @@
   information about this hardware.  If the driver doesn't work out of
   the box, you may have to change some settings in
   <file: drivers/scsi/u14-34f.c>.  Read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Note that there is also
+  <http://www.tldp.org/docs.html#howto>.  Note that there is also
   another driver for the same hardware: "UltraStor SCSI support",
   below.  You should say Y to both only if you want 24F support as
   well.
@@ -7173,7 +7337,7 @@
   other adapters based on the Future Domain chipsets (Quantum
   ISA-200S, ISA-250MG; Adaptec AHA-2920A; and at least one IBM board).
   It is explained in section 3.7 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   NOTE: Newer Adaptec AHA-2920C boards use the Adaptec AIC-7850 chip
   and should use the aic7xxx driver ("Adaptec AIC7xxx chipset SCSI
@@ -7203,7 +7367,7 @@
   This is the generic NCR family of SCSI controllers, not to be
   confused with the NCR 53c7 or 8xx controllers.  It is explained in
   section 3.8 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If it doesn't work out
+  <http://www.tldp.org/docs.html#howto>.  If it doesn't work out
   of the box, you may have to change some settings in
   <file:drivers/scsi/g_NCR5380.h>.
 
@@ -7250,7 +7414,7 @@
   This is a driver for the 53c7 and 8xx NCR family of SCSI
   controllers, not to be confused with the NCR 5380 controllers.  It
   is explained in section 3.8 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If it doesn't work out
+  <http://www.tldp.org/docs.html#howto>.  If it doesn't work out
   of the box, you may have to change some settings in
   <file:drivers/scsi/53c7,8xx.h>.  Please read
   <file:drivers/scsi/README.ncr53c7xx> for the available boot time
@@ -7609,7 +7773,7 @@
 CONFIG_SCSI_INITIO
   This is support for the Initio 91XXU(W) SCSI host adapter.  Please
   read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -7620,7 +7784,7 @@
 CONFIG_SCSI_PAS16
   This is support for a SCSI host adapter.  It is explained in section
   3.10 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If it doesn't work out
+  <http://www.tldp.org/docs.html#howto>.  If it doesn't work out
   of the box, you may have to change some settings in
   <file:drivers/scsi/pas16.h>.
 
@@ -7633,7 +7797,7 @@
 CONFIG_SCSI_INIA100
   This is support for the Initio INI-A100U2W SCSI host adapter.
   Please read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -7644,7 +7808,7 @@
 CONFIG_SCSI_PCI2000
   This is support for the PCI2000I EIDE interface card which acts as a
   SCSI host adapter.  Please read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module called pci2000.o ( = code
   which can be inserted in and removed from the running kernel
@@ -7655,7 +7819,7 @@
 CONFIG_SCSI_PCI2220I
   This is support for the PCI2220i EIDE interface card which acts as a
   SCSI host adapter.  Please read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module called pci2220i.o ( = code
   which can be inserted in and removed from the running kernel
@@ -7666,7 +7830,7 @@
 CONFIG_SCSI_PSI240I
   This is support for the PSI240i EIDE interface card which acts as a
   SCSI host adapter.  Please read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module called psi240i.o ( = code
   which can be inserted in and removed from the running kernel
@@ -7686,7 +7850,7 @@
   Information about this driver is contained in
   <file:drivers/scsi/README.qlogicfas>.  You should also read the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -7704,7 +7868,7 @@
 
   Please read the file <file:drivers/scsi/README.qlogicisp>.  You
   should also read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -7720,6 +7884,12 @@
   The module will be called qlogicfc.o.  If you want to compile it as
   a module, say M here and read <file:Documentation/modules.txt>.
 
+Include loadable firmware in driver
+CONFIG_SCSI_QLOGIC_FC_FIRMWARE
+  Say Y to include ISP2100 Fabric Initiator/Target Firmware, with
+  expanded LUN addressing and FcTape (FCP-2) support, in the
+  Qlogic QLA 1280 driver. This is required on some platforms.
+
 Qlogic QLA 1280 SCSI support
 CONFIG_SCSI_QLOGIC_1280
   Say Y if you have a QLogic ISP1x80/1x160 SCSI host adapter.
@@ -7733,7 +7903,7 @@
 CONFIG_SCSI_SEAGATE
   These are 8-bit SCSI controllers; the ST-01 is also supported by
   this driver.  It is explained in section 3.9 of the SCSI-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.  If it
+  available from <http://www.tldp.org/docs.html#howto>.  If it
   doesn't work out of the box, you may have to change some settings in
   <file:drivers/scsi/seagate.h>.
 
@@ -7746,7 +7916,7 @@
 CONFIG_SCSI_T128
   This is support for a SCSI host adapter. It is explained in section
   3.11 of the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If it doesn't work out
+  <http://www.tldp.org/docs.html#howto>.  If it doesn't work out
   of the box, you may have to change some settings in
   <file:drivers/scsi/t128.h>.  Note that Trantor was purchased by
   Adaptec, and some former Trantor products are being sold under the
@@ -7762,7 +7932,7 @@
   This is support for the UltraStor 14F, 24F and 34F SCSI-2 host
   adapter family.  This driver is explained in section 3.12 of the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If it doesn't work out
+  <http://www.tldp.org/docs.html#howto>.  If it doesn't work out
   of the box, you may have to change some settings in
   <file:drivers/scsi/ultrastor.h>.
 
@@ -7804,7 +7974,7 @@
 
   You want to read the start of <file:drivers/scsi/eata.c> and the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Note that there is also another driver for the same hardware
   available: "EATA-DMA [Obsolete] (DPT, NEC, AT&T, SNI, AST, Olivetti,
@@ -7845,7 +8015,7 @@
   This is support for the NCR53c406a SCSI host adapter.  For user
   configurable parameters, check out <file:drivers/scsi/NCR53c406a.c>
   in the kernel source.  Also read the SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this driver as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -7928,7 +8098,7 @@
   This is support for the AM53/79C974 SCSI host adapters.  Please read
   <file:drivers/scsi/README.AM53C974> for details.  Also, the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, is for you.
+  <http://www.tldp.org/docs.html#howto>, is for you.
 
   Note that there is another driver for AM53C974 based adapters:
   "Tekram DC390(T) and Am53/79C974 (PCscsi) SCSI support", above.  You
@@ -7980,7 +8150,7 @@
   For more information about this driver and how to use it you should
   read the file <file:drivers/scsi/README.ppa>.  You should also read
   the SCSI-HOWTO, which is available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If you use this driver,
+  <http://www.tldp.org/docs.html#howto>.  If you use this driver,
   you will still be able to use the parallel port for other tasks,
   such as a printer; it is safe to compile both drivers into the
   kernel.
@@ -8007,7 +8177,7 @@
   For more information about this driver and how to use it you should
   read the file <file:drivers/scsi/README.ppa>.  You should also read
   the SCSI-HOWTO, which is available from
-  <http://www.linuxdoc.org/docs.html#howto>.  If you use this driver,
+  <http://www.tldp.org/docs.html#howto>.  If you use this driver,
   you will still be able to use the parallel port for other tasks,
   such as a printer; it is safe to compile both drivers into the
   kernel.
@@ -8293,7 +8463,7 @@
   telephone line with a modem either via UUCP (UUCP is a protocol to
   forward mail and news between unix hosts over telephone lines; read
   the UUCP-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>) or dialing up a shell
+  <http://www.tldp.org/docs.html#howto>) or dialing up a shell
   account or a BBS, even using term (term is a program which gives you
   almost full Internet connectivity if you have a regular dial up
   shell account on some Internet connected Unix computer. Read
@@ -8313,7 +8483,7 @@
 
   Make sure to read the NET-3-HOWTO. Eventually, you will have to read
   Olaf Kirch's excellent and free book "Network Administrator's
-  Guide", to be found in <http://www.linuxdoc.org/docs.html#guide>. If
+  Guide", to be found in <http://www.tldp.org/docs.html#guide>. If
   unsure, say Y.
 
 Dummy net driver support
@@ -8326,7 +8496,7 @@
   thing often comes in handy, the default is Y. It won't enlarge your
   kernel either. What a deal. Read about it in the Network
   Administrator's Guide, available from
-  <http://www.linuxdoc.org/docs.html#guide>.
+  <http://www.tldp.org/docs.html#guide>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -8374,7 +8544,7 @@
   allows you to use SLIP over a regular dial up shell connection. If
   you plan to use SLiRP, make sure to say Y to CSLIP, below. The
   NET-3-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, explains how to
+  <http://www.tldp.org/docs.html#howto>, explains how to
   configure SLIP. Note that you don't need this option if you just
   want to run term (term is a program which gives you almost full
   Internet connectivity if you have a regular dial up shell account on
@@ -8398,7 +8568,7 @@
   <ftp://ibiblio.org/pub/Linux/system/network/serial/>) which
   allows you to use SLIP over a regular dial up shell connection, you
   definitely want to say Y here. The NET-3-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, explains how to configure
+  <http://www.tldp.org/docs.html#howto>, explains how to configure
   CSLIP. This won't enlarge your kernel.
 
 Keepalive and linefill
@@ -8427,7 +8597,7 @@
 
   To use PPP, you need an additional program called pppd as described
   in the PPP-HOWTO, available at
-  <http://www.linuxdoc.org/docs.html#howto>.  Make sure that you have
+  <http://www.tldp.org/docs.html#howto>.  Make sure that you have
   the version of pppd recommended in <file:Documentation/Changes>.
   The PPP option enlarges your kernel by about 16 KB.
 
@@ -8530,9 +8700,9 @@
 CONFIG_PPPOE
   Support for PPP over Ethernet.
 
-  This driver requires a specially patched pppd daemon.  The patch to
-  pppd, along with binaries of a patched pppd package can be found at:
-  <http://www.shoshin.uwaterloo.ca/~mostrows/>.
+  This driver requires the current pppd from the "ppp" CVS repository
+  on cvs.samba.org.  The required support will be present in the next
+  ppp release (2.4.2).
 
 Wireless LAN (non-hamradio)
 CONFIG_NET_RADIO
@@ -8592,7 +8762,7 @@
 
   If you want to use an ISA WaveLAN card under Linux, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. Some more specific
+  <http://www.tldp.org/docs.html#howto>. Some more specific
   information is contained in
   <file:Documentation/networking/wavelan.txt> and in the source code
   <file:drivers/net/wavelan.p.h>.
@@ -8753,7 +8923,7 @@
   To use your PC-cards, you will need supporting software from David
   Hinds' pcmcia-cs package (see the file <file:Documentation/Changes>
   for location).  You also want to check out the PCMCIA-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   If unsure, say N.
 
@@ -8882,6 +9052,19 @@
   it as a module, say M here and read
   <file:Documentation/modules.txt>. If unsure, say N.
 
+Xircom CardBus support (new driver)
+CONFIG_PCMCIA_XIRCOM
+  This driver is for the Digital "Tulip" Ethernet CardBus adapters.
+  It should work with most DEC 21*4*-based chips/ethercards, as well
+  as with work-alike chips from Lite-On (PNIC) and Macronix (MXIC) and
+  ASIX.
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called xircom_cb.o.  If you want to compile
+  it as a module, say M here and read
+  <file:Documentation/modules.txt>. If unsure, say N.
+
 PCMCIA Wireless LAN
 CONFIG_NET_PCMCIA_RADIO
   Say Y here if you would like to use a PCMCIA (PC-card) device to
@@ -8891,7 +9074,7 @@
   To use your PC-cards, you will need supporting software from David
   Hinds' pcmcia-cs package (see the file <file:Documentation/Changes>
   for location). You also want to check out the PCMCIA-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
 Hermes chipset 802.11b support (Orinoco/Prism2/Symbol cards)
 CONFIG_HERMES
@@ -8925,6 +9108,14 @@
   Support for these adaptors is so far still incomplete and buggy.
   You have been warned.
 
+Prism 2.5 PCI 802.11b adaptor support
+CONFIG_PCI_HERMES
+  Enable support for PCI and mini-PCI 802.11b wireless NICs based on
+  the Prism 2.5 chipset.  These are true PCI cards, not the 802.11b
+  PCMCIA cards bundled with PCI<->PCMCIA adaptors which are also
+  common.  Some of the built-in wireless adaptors in laptops are of
+  this variety.
+
 Hermes support (Orinoco/WavelanIEEE/PrismII/Symbol 802.11b cards)
 CONFIG_PCMCIA_HERMES
   A driver for "Hermes" chipset based PCMCIA wireless adaptors, such
@@ -8937,7 +9128,7 @@
   To use your PC-cards, you will need supporting software from David
   Hinds' pcmcia-cs package (see the file <file:Documentation/Changes>
   for location).  You also want to check out the PCMCIA-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   You will also very likely also need the Wireless Tools in order to
   configure your card and that /etc/pcmcia/wireless.opts works:
@@ -8949,7 +9140,7 @@
   PCI 802.11 wireless cards.
   It supports the new 802.11b cards from Cisco (Cisco 34X, Cisco 35X
   - with or without encryption) as well as card before the Cisco
-  aquisition (Aironet 4500, Aironet 4800, Aironet 4800B).
+  acquisition (Aironet 4500, Aironet 4800, Aironet 4800B).
 
   This driver support both the standard Linux Wireless Extensions
   and Cisco proprietary API, so both the Linux Wireless Tools and the
@@ -8964,7 +9155,7 @@
   driver part of the Linux Pcmcia package.
   It supports the new 802.11b cards from Cisco (Cisco 34X, Cisco 35X
   - with or without encryption) as well as card before the Cisco
-  aquisition (Aironet 4500, Aironet 4800, Aironet 4800B). It also
+  acquisition (Aironet 4500, Aironet 4800, Aironet 4800B). It also
   supports OEM of Cisco such as the DELL TrueMobile 4800 and Xircom
   802.11b cards.
 
@@ -8975,7 +9166,7 @@
   To use your PC-cards, you will need supporting software from David
   Hinds' pcmcia-cs package (see the file <file:Documentation/Changes>
   for location).  You also want to check out the PCMCIA-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
 Aviator/Raytheon 2.4MHz wireless support
 CONFIG_PCMCIA_RAYCS
@@ -9044,7 +9235,7 @@
 
   If you want to use PLIP, say Y and read the PLIP mini-HOWTO as well
   as the NET-3-HOWTO, both available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Note that the PLIP
+  <http://www.tldp.org/docs.html#howto>.  Note that the PLIP
   protocol has been changed and this PLIP driver won't work together
   with the PLIP support in Linux versions 1.0.x.  This option enlarges
   your kernel by about 8 KB.
@@ -9069,7 +9260,7 @@
   Say Y if you want this and read
   <file:Documentation/networking/eql.txt>.  You may also want to read
   section 6.2 of the NET-3-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -9132,6 +9323,28 @@
   If you want to do that, say M here. The module will be called
   sealevel.o.
 
+TMPTX3912/PR31700 serial port support
+CONFIG_SERIAL_TX3912
+  The TX3912 is a Toshiba RISC processor based o the MIPS 3900 core;
+  see <http://www.toshiba.com/taec/components/Generic/risc/tx3912.htm>.
+  Say Y here to enable kernel support for the on-board serial port.
+
+Console on TMPTX3912/PR31700 serial port
+CONFIG_SERIAL_TX3912_CONSOLE
+  The TX3912 is a Toshiba RISC processor based o the MIPS 3900 core;
+  see <http://www.toshiba.com/taec/components/Generic/risc/tx3912.htm>.
+  Say Y here to direct console I/O to the on-board serial port.
+
+Enable Au1000 serial console
+CONFIG_AU1000_SERIAL_CONSOLE
+  If you have an Alchemy AU1000 processor (MIPS based) and you want
+  to use a console on a serial port, say Y.  Otherwise, say N.
+
+Enable Au1000 UART Support
+CONFIG_AU1000_UART
+  If you have an Alchemy AU1000 processor (MIPS based) and you want
+  to use serial ports, say Y.  Otherwise, say N.
+
 SyncLink HDLC/SYNCPPP support
 CONFIG_SYNCLINK_SYNCPPP
   Enables HDLC/SYNCPPP support for the SyncLink WAN driver.
@@ -9386,7 +9599,7 @@
 
 Diffserv field marker
 CONFIG_NET_SCH_DSMARK
-  Say Y if you want to schedule packets avccording to the
+  Say Y if you want to schedule packets according to the
   Differentiated Services architecture proposed in RFC 2475.
   Technical information on this method, with pointers to associated
   RFCs, is available at <http://www.gta.ufrj.br/diffserv/>.
@@ -9588,6 +9801,21 @@
   performance will be written to /proc/net/profile. If you don't know
   what it is about, you don't need it: say N.
 
+Network packet generator
+CONFIG_NET_PKTGEN
+  This module will inject preconfigured packets, at a configurable
+  rate, out of a given interface.  It is used for network interface
+  stress testing and performance analysis.  If you don't understand
+  what was just said, you don't need it: say N.
+
+  Documentation on how to use the packet generator can be found
+  at <file:Documentation/networking/pktgen.txt>.
+
+  This code is also available as a module called pktgen.o ( = code
+  which can be inserted in and removed from the running kernel
+  whenever you want).  If you want to compile it as a module, say M
+  here and read <file:Documentation/modules.txt>.
+
 Wan interfaces support
 CONFIG_WAN
   Wide Area Networks (WANs), such as X.25, frame relay and leased
@@ -9655,7 +9883,7 @@
   V.35 or V.36 interface) to your Linux box.
 
   LMC 1200 with on board DSU board allows you to connect your Linux
-  box dirrectly to a T1 or E1 circuit.
+  box directly to a T1 or E1 circuit.
 
   LMC 5200 board provides a HSSI interface capable of running up to
   52 mbits per second.
@@ -9772,14 +10000,14 @@
 CONFIG_WANPIPE_X25
   Say Y to this option if you are planning to connect a WANPIPE card
   to an X.25 network.  Note, this feature also includes the X.25 API
-  support used to develope custom applications over the X.25 protocol.
+  support used to develop custom applications over the X.25 protocol.
   If you say N, the X.25 support will not be included in the driver.
   The X.25 option is supported on S514-PCI and S508-ISA cards.
 
 WANPIPE Frame Relay support
 CONFIG_WANPIPE_FR
   Say Y to this option if you are planning to connect a WANPIPE card
-  to a frame relay network, or use frame relay API to develope
+  to a frame relay network, or use frame relay API to develop
   custom applications over the Frame  Relay protocol.
   This feature also contains the Ethernet Bridging over Frame Relay,
   where a WANPIPE frame relay link can be directly connected to the
@@ -9879,7 +10107,7 @@
   Hardware driver for the TCO timer built into the Intel i810 and i815
   chipset family.  The TCO (Total Cost of Ownership) timer is a
   watchdog timer that will reboot the machine after its second
-  expiration. The expiration time can be configured by commandline
+  expiration. The expiration time can be configured by command
   argument "i810_margin=<n>" where <n> is the counter initial value.
   It is decremented every 0.6 secs, the default is 50 which gives a
   timeout of 30 seconds and one minute until reset.
@@ -9893,6 +10121,20 @@
   <file:Documentation/modules.txt>.  The module will be called
   i810-tco.o.
 
+SliceCOM/PciCOM board support
+CONFIG_COMX_HW_MUNICH
+  Hardware driver for the 'SliceCOM' (channelized E1) and 'PciCOM'
+  boards (X21) from the MultiGate family.
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called comx-hw-munich.o. If you want to compile it
+  as a module, say M here and read <file:Documentation/modules.txt>.
+
+  Read linux/Documentation/networking/slicecom.txt for help on
+  configuring and using SliceCOM interfaces. Further info on these cards
+  can be found at http://www.itc.hu or <info@itc.hu>.
+
 Support for HDLC and syncPPP protocols on MultiGate boards
 CONFIG_COMX_PROTO_PPP
   Cisco-HDLC and synchronous PPP protocol driver for all MultiGate
@@ -10045,7 +10287,7 @@
   If your Linux machine will be connected to an Ethernet and you have
   an Ethernet network interface card (NIC) installed in your computer,
   say Y here and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. You will then also have
+  <http://www.tldp.org/docs.html#howto>. You will then also have
   to say Y to the driver for your particular NIC.
 
   Note that the answer to this question won't directly affect the
@@ -10056,7 +10298,7 @@
 CONFIG_NET_VENDOR_SMC
   If you have a network (Ethernet) card belonging to this class, say Y
   and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Note that the answer to this question doesn't directly affect the
   kernel: saying N will just cause the configurator to skip all
@@ -10067,7 +10309,7 @@
 CONFIG_WD80x3
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10079,7 +10321,7 @@
 CONFIG_ULTRAMCA
   If you have a network (Ethernet) card of this type and are running
   an MCA based system (PS/2), say Y and read the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10091,7 +10333,7 @@
 CONFIG_ULTRA
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Important: There have been many reports that, with some motherboards
   mixing an SMC Ultra and an Adaptec AHA154x SCSI card (or compatible,
@@ -10110,7 +10352,7 @@
 CONFIG_ULTRA32
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10125,7 +10367,7 @@
   another SMC9192/9194 based chipset.  Say Y if you want it compiled
   into the kernel, and read the file
   <file:Documentation/networking/smc9.txt> and the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10139,7 +10381,7 @@
   with ISA NE2000 cards (they have their own driver, "NE2000/NE1000
   support" below). If you have a PCI NE2000 network (Ethernet) card,
   say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver also works for the following NE2000 clone cards:
     RealTek RTL-8029  Winbond 89C940  Compex RL2000  KTI ET32P2
@@ -10156,7 +10398,7 @@
 CONFIG_NET_VENDOR_RACAL
   If you have a network (Ethernet) card belonging to this class, such
   as the NI5010, NI5210 or NI6210, say Y and read the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   Note that the answer to this question doesn't directly affect the
   kernel: saying N will just cause the configurator to skip all
@@ -10167,7 +10409,7 @@
 CONFIG_NI5010
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. Note that this is still
+  <http://www.tldp.org/docs.html#howto>. Note that this is still
   experimental code.
 
   This driver is also available as a module ( = code which can be
@@ -10180,7 +10422,7 @@
 CONFIG_NI52
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10192,7 +10434,7 @@
 CONFIG_NI65
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10205,7 +10447,7 @@
   This is a driver for the Fast Ethernet PCI network cards based on
   the RTL8139C+ chips. If you have one of those, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this driver as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10218,7 +10460,7 @@
   the RTL8139 chips. If you have one of those, say Y and read
   <file:Documentation/networking/8139too.txt> as well as the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this driver as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10252,7 +10494,7 @@
   the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in
   SiS 630 and SiS 540 chipsets.  If you have one of those, say Y and
   read the Ethernet-HOWTO, available at
-  <http://www.linuxdoc.org/docs.html#howto>.  Please read
+  <http://www.tldp.org/docs.html#howto>.  Please read
   <file:Documentation/networking/sis900.txt> and comments at the
   beginning of <file:drivers/net/sis900.c> for more information.
 
@@ -10367,6 +10609,15 @@
   Support for the Sun GEM chip, aka Sun GigabitEthernet/P 2.0.  See also
   <http://www.sun.com/products-n-solutions/hardware/docs/pdf/806-3985-10.pdf>.
 
+Broadcom Tigon3 support
+CONFIG_TIGON3
+  This driver supports Broadcom Tigon3 based gigabit Ethernet cards.
+
+  If you want to compile this driver as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want),
+  say M here and read <file:Documentation/modules.txt>.  This is
+  recommended.  The module will be called tg3.o.
+
 MyriCOM Gigabit Ethernet support
 CONFIG_MYRI_SBUS
   This driver supports MyriCOM Sbus gigabit Ethernet cards.
@@ -10392,7 +10643,7 @@
 CONFIG_LANCE
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. Some LinkSys cards are
+  <http://www.tldp.org/docs.html#howto>. Some LinkSys cards are
   of this type.
 
   If you want to compile this driver as a module ( = code which can be
@@ -10404,7 +10655,7 @@
 CONFIG_SGI_IOC3_ETH
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 National Semiconductor DP83902AV support
 CONFIG_STNIC
@@ -10419,7 +10670,7 @@
 CONFIG_NET_VENDOR_3COM
   If you have a network (Ethernet) card belonging to this class, say Y
   and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Note that the answer to this question doesn't directly affect the
   kernel: saying N will just cause the configurator to skip all
@@ -10430,7 +10681,7 @@
 CONFIG_EL1
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Also, consider buying a
+  <http://www.tldp.org/docs.html#howto>.  Also, consider buying a
   new card, since the 3c501 is slow, broken, and obsolete: you will
   have problems.  Some people suggest to ping ("man ping") a nearby
   machine every minute ("man cron") when using this card.
@@ -10445,7 +10696,7 @@
 CONFIG_EL2
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10458,7 +10709,7 @@
   Information about this network (Ethernet) card can be found in
   <file:Documentation/networking/3c505.txt>.  If you have a card of
   this type, say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10470,7 +10721,7 @@
 CONFIG_EL16
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10482,7 +10733,7 @@
 CONFIG_ELMC
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10494,7 +10745,7 @@
 CONFIG_ELMC_II
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10506,7 +10757,7 @@
 CONFIG_EL3
   If you have a network (Ethernet) card belonging to the 3Com
   EtherLinkIII series, say Y and read the Ethernet-HOWTO, available
-  from <http://www.linuxdoc.org/docs.html#howto>.
+  from <http://www.tldp.org/docs.html#howto>.
 
   If your card is not working you may need to use the DOS
   setup disk to disable Plug & Play mode, and to select the default
@@ -10522,7 +10773,7 @@
 CONFIG_3C515
   If you have a 3Com ISA EtherLink XL "Corkscrew" 3c515 Fast Ethernet
   network card, say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10542,7 +10793,7 @@
   "Hurricane" (3c555/3cSOHO)                           PCI
 
   If you have such a card, say Y and read the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>. More
+  available from <http://www.tldp.org/docs.html#howto>. More
   specific information is in
   <file:Documentation/networking/vortex.txt> and in the comments at
   the beginning of <file:drivers/net/3c59x.c>.
@@ -10558,7 +10809,7 @@
   bus system (that's the way the cards talks to the other components
   of your computer) is ISA (as opposed to EISA, VLB or PCI), say Y.
   Make sure you know the name of your card. Read the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   If unsure, say Y.
 
@@ -10579,7 +10830,7 @@
   support" below.
 
   You might also want to have a look at the Ethernet-HOWTO, available
-  from <http://www.linuxdoc.org/docs.html#howto>(even though ARCnet
+  from <http://www.tldp.org/docs.html#howto>(even though ARCnet
   is not really Ethernet).
 
   This driver is also available as a module ( = code which can be
@@ -10670,7 +10921,7 @@
 CONFIG_E2100
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10683,7 +10934,7 @@
   Support for CS89x0 chipset based Ethernet cards. If you have a
   network (Ethernet) card of this type, say Y and read the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto> as well as
+  <http://www.tldp.org/docs.html#howto> as well as
   <file:Documentation/networking/cs89x0.txt>.
 
   If you want to compile this as a module ( = code which can be
@@ -10696,7 +10947,7 @@
 CONFIG_DEPCA
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto> as well as
+  <http://www.tldp.org/docs.html#howto> as well as
   <file:drivers/net/depca.c>.
 
   If you want to compile this as a module ( = code which can be
@@ -10712,7 +10963,7 @@
   cards. If this is for you, say Y and read
   <file:Documentation/networking/ewrk3.txt> in the kernel source as
   well as the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10724,7 +10975,7 @@
 CONFIG_SEEQ8005
   This is a driver for the SEEQ 8005 network (Ethernet) card.  If this
   is for you, read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10736,7 +10987,7 @@
 CONFIG_AT1700
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10749,7 +11000,7 @@
 CONFIG_FMV18X
   If you have a Fujitsu FMV-181/182/183/184 network (Ethernet) card,
   say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you use an FMV-183 or FMV-184 and it is not working, you may need
   to disable Plug & Play mode of the card.
@@ -10766,7 +11017,7 @@
   driver supports intel i82595{FX,TX} based boards. Note however
   that the EtherExpress PRO/100 Ethernet card has its own separate
   driver.  Please read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10778,7 +11029,7 @@
 CONFIG_EEXPRESS
   If you have an EtherExpress16 network (Ethernet) card, say Y and
   read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Note that the Intel
+  <http://www.tldp.org/docs.html#howto>.  Note that the Intel
   EtherExpress16 card used to be regarded as a very poor choice
   because the driver was very unreliable. We now have a new driver
   that should do better.
@@ -10793,7 +11044,7 @@
 CONFIG_HAMACHI
   If you have a Gigabit Ethernet card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10805,7 +11056,7 @@
 CONFIG_HPLAN_PLUS
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10817,7 +11068,7 @@
 CONFIG_HPLAN
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10829,7 +11080,7 @@
 CONFIG_HP100
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10841,7 +11092,7 @@
 CONFIG_NE2000
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Many Ethernet cards
+  <http://www.tldp.org/docs.html#howto>.  Many Ethernet cards
   without a specific driver are compatible with NE2000.
 
   If you have a PCI NE2000 card however, say N here and Y to "PCI
@@ -10877,13 +11128,13 @@
 CONFIG_SK_G16
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 NE/2 (ne2000 MCA version) support
 CONFIG_NE2_MCA
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10924,7 +11175,7 @@
 CONFIG_NET_PCI
   This is another class of network cards which attach directly to the
   bus. If you have one of those, say Y and read the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   Note that the answer to this question doesn't directly affect the
   kernel: saying N will just cause the configurator to skip all
@@ -10936,7 +11187,7 @@
 CONFIG_PCNET32
   If you have a PCnet32 or PCnetPCI based network (Ethernet) card,
   answer Y here and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10948,7 +11199,7 @@
 CONFIG_AC3200
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10960,7 +11211,7 @@
 CONFIG_LNE390
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -10972,7 +11223,7 @@
 CONFIG_NE3210
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  Note that this driver
+  <http://www.tldp.org/docs.html#howto>.  Note that this driver
   will NOT WORK for NE3200 cards as they are completely different.
 
   This driver is also available as a module ( = code which can be
@@ -10985,7 +11236,7 @@
 CONFIG_APRICOT
   If you have a network (Ethernet) controller of this type, say Y and
   read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -10999,7 +11250,7 @@
   These include the DE425, DE434, DE435, DE450 and DE500 models.  If
   you have a network card of this type, say Y and read the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. More specific
+  <http://www.tldp.org/docs.html#howto>. More specific
   information is contained in
   <file:Documentation/networking/de4x5.txt>.
 
@@ -11018,7 +11269,7 @@
   (smc9332dst), you can also try the driver for "Generic DECchip"
   cards, above.  However, most people with a network card of this type
   will say Y here.) Do read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  More specific
+  <http://www.tldp.org/docs.html#howto>.  More specific
   information is contained in 
   <file:Documentation/networking/tulip.txt>.
 
@@ -11050,7 +11301,7 @@
   PCI/EISA Ethernet switch cards. These include the SE-4 and the SE-6
   models.  If you have a network card of this type, say Y and read the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.  More specific
+  <http://www.tldp.org/docs.html#howto>.  More specific
   information is contained in <file:Documentation/networking/dgrs.txt>.
 
   This driver is also available as a module ( = code which can be
@@ -11063,7 +11314,7 @@
 CONFIG_EEPRO100
   If you have an Intel EtherExpress PRO/100 PCI network (Ethernet)
   card, say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -11089,11 +11340,17 @@
   cards. Specifications and data at
   <http://www.myson.com.hk/mtd/datasheet/>.
 
+LP486E on board Ethernet
+CONFIG_LP486E
+  Say Y here to support the 82596-based on-board Ethernet controller
+  for the Panther motherboard, which is one of the two shipped in the
+  Intel Professional Workstation.
+
 ICL EtherTeam 16i/32 support
 CONFIG_ETH16I
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -11106,7 +11363,7 @@
   If you have a PCI Ethernet network card based on the ThunderLAN chip
   which is supported by this driver, say Y and read the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Devices currently supported by this driver are Compaq Netelligent,
   Compaq NetFlex and Olicom cards.  Please read the file
@@ -11159,7 +11416,7 @@
 CONFIG_ES3210
   If you have a network (Ethernet) card of this type, say Y and read
   the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -11222,7 +11479,7 @@
   (Ethernet) card, and this is the Linux driver for it. Note that the
   IBM Thinkpad 300 is compatible with the Z-Note and is also supported
   by this driver. Read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 Philips SAA9730 Ethernet support
 CONFIG_LAN_SAA9730
@@ -11236,7 +11493,7 @@
   Cute little network (Ethernet) devices which attach to the parallel
   port ("pocket adapters"), commonly used with laptops. If you have
   one of those, say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to plug a network (or some other) card into the PCMCIA
   (or PC-card) slot of your laptop instead (PCMCIA is the standard for
@@ -11256,7 +11513,7 @@
 CONFIG_ATP
   This is a network (Ethernet) device which attaches to your parallel
   port. Read <file:drivers/net/atp.c> as well as the Ethernet-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>, if you
+  available from <http://www.tldp.org/docs.html#howto>, if you
   want to use this.  If you intend to use this driver, you should have
   said N to the "Parallel printer support", because the two drivers
   don't like each other.
@@ -11271,7 +11528,7 @@
   This is a network (Ethernet) device which attaches to your parallel
   port. Read <file:Documentation/networking/DLINK.txt> as well as the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, if you want to use
+  <http://www.tldp.org/docs.html#howto>, if you want to use
   this. It is possible to have several devices share a single parallel
   port and it is safe to compile the corresponding drivers into the
   kernel.
@@ -11287,7 +11544,7 @@
   This is a network (Ethernet) device which attaches to your parallel
   port. Read <file:Documentation/networking/DLINK.txt> as well as the
   Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, if you want to use
+  <http://www.tldp.org/docs.html#howto>, if you want to use
   this. It is possible to have several devices share a single parallel
   port and it is safe to compile the corresponding drivers into the
   kernel.
@@ -11306,14 +11563,14 @@
   connected to such a Token Ring network and want to use your Token
   Ring card under Linux, say Y here and to the driver for your
   particular card below and read the Token-Ring mini-HOWTO, available
-  from <http://www.linuxdoc.org/docs.html#howto>. Most people can
+  from <http://www.tldp.org/docs.html#howto>. Most people can
   say N here.
 
 IBM Tropic chipset based adapter support
 CONFIG_IBMTR
   This is support for all IBM Token Ring cards that don't use DMA. If
   you have such a beast, say Y and read the Token-Ring mini-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   Warning: this driver will almost definitely fail if more than one
   active Token Ring card is present.
@@ -11330,7 +11587,7 @@
   Wake On Lan, and PCI 100/16/4 adapters.
 
   If you have such an adapter, say Y and read the Token-Ring
-  mini-HOWTO, available from <http://www.linuxdoc.org/docs.html#howto>.
+  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -11346,7 +11603,7 @@
   This is support for IBM Lanstreamer PCI Token Ring Cards.
 
   If you have such an adapter, say Y and read the Token-Ring
-  mini-HOWTO, available from <http://www.linuxdoc.org/docs.html#howto>.
+  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a modules ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -11366,7 +11623,7 @@
 
   If you have such an adapter and would like to use it, say Y and
   read the Token-Ring mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Also read the file <file:Documentation/networking/tms380tr.txt> or
   check <http://www.auk.cx/tms380tr/>.
@@ -11431,7 +11688,7 @@
 
   If you have such an adapter and would like to use it, say Y or M and
   read the Token-Ring mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto> and the file
+  <http://www.tldp.org/docs.html#howto> and the file
   <file:Documentation/networking/smctr.txt>.
 
   This driver is also available as a module ( = code which can be
@@ -11439,6 +11696,24 @@
   The module will be called smctr.o. If you want to compile it
   as a module, say M here and read <file:Documentation/modules.txt>.
 
+3COM 3C359 Token Link Velocity XL PCI adapter support
+CONFIG_3C359
+  This is support for the 3Com PCI Velocity XL cards, specifically
+  the 3Com 3C359, please note this is not for the 3C339 cards, you
+  should use the tms380 driver instead.
+
+  If you have such an adapter, say Y and read the Token-Ring
+  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will will be called 3c359.o. If you want to compile it
+  as a module, say M here and read Documentation/modules.txt.
+
+  Also read the file <file:Documentation/networking/3c359.txt> or check the 
+  Linux Token Ring Project site for the latest information at
+  <http://www.linuxtr.net>
+
 Sun Happy Meal 10/100baseT support
 CONFIG_HAPPYMEAL
   This driver supports the "hme" interface present on most Ultra
@@ -11615,7 +11890,7 @@
 CONFIG_CD_NO_IDESCSI
   If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y
   here, otherwise N. Read the CD-ROM-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Note that the answer to this question doesn't directly affect the
   kernel: saying N will just cause the configurator to skip all
@@ -11893,7 +12168,7 @@
   usage (also called disk quotas). Currently, it works only for the
   ext2 file system. You need additional software in order to use quota
   support; for details, read the Quota mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. Probably the quota
+  <http://www.tldp.org/docs.html#howto>. Probably the quota
   support is only useful for multi user systems. If unsure, say N.
 
 Memory Technology Device (MTD) support
@@ -12221,7 +12496,7 @@
 CONFIG_MTD_PHYSMAP_BUSWIDTH
   This is the total width of the data bus of the flash devices
   in octets. For example, if you have a data bus width of 32
-  bits, you would set the bus width octect value to 4. This is
+  bits, you would set the bus width octet value to 4. This is
   used internally by the CFI drivers.
 
 Flash chip mapping on Sun Microsystems boardsets
@@ -12376,7 +12651,7 @@
   NAND flash device internally checks only bits transitioning
   from 1 to 0. There is a rare possibility that even though the
   device thinks the write was successful, a bit could have been
-  flipped accidentaly due to device wear, gamma rays, whatever.
+  flipped accidentally due to device wear, gamma rays, whatever.
   Enable this if you are really paranoid.
 
 Support for the SPIA board
@@ -12661,18 +12936,6 @@
   of debug messages to the system log. Select this if you are having a
   problem with USB support and want to see more of what is going on.
 
-USB fetch large config
-CONFIG_USB_LARGE_CONFIG
-  This option changes the initial request for a config descriptor so
-  that some poorly designed devices will still work.  Some APC UPSes
-  need it.  Basically, the usb subsystem sends a request for a short
-  (8 byte) config, just to find out how large the real config is.
-  Incorrectly implemented devices may choke on this small config
-  request.  This option make the initial request for a quite large
-  config (1009 bytes), and things just work.
-
-  If you have an APC UPS, say Y; otherwise say N.
-
 USB long timeout for slow-responding devices (some MGE Ellipse UPSes)
 CONFIG_USB_LONG_TIMEOUT
   This option makes the standard time out a bit longer.  Basically,
@@ -12683,6 +12946,30 @@
   If you have an MGE Ellipse UPS, or you see timeouts in HID
   transactions, say Y; otherwise say N.
 
+EHCI (USB 2.0) support
+CONFIG_USB_EHCI_HCD
+  The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
+  "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
+  If your USB host controller supports USB 2.0, you will likely want to
+  configure this Host Controller Driver.  At this writing, the primary
+  implementation of EHCI is a chip from NEC, widely available in add-on
+  PCI cards, but implementations are in the works from other vendors
+  including Intel and Philips.  Motherboard support is appearing.
+
+  EHCI controllers are packaged with "companion" host controllers (OHCI
+  or UHCI) to handle USB 1.1 devices connected to root hub ports.  Ports
+  will connect to EHCI if it the device is high speed, otherwise they
+  connect to a companion controller.  If you configure EHCI, you should
+  probably configure the OHCI (for NEC and some other vendors) USB Host
+  Controller Driver too.
+
+  You may want to read <file:Documentation/usb/ehci.txt>.
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called ehci-hcd.o. If you want to compile it as a
+  module, say M here and read <file:Documentation/modules.txt>.
+
 UHCI (Intel PIIX4, VIA, ...) support
 CONFIG_USB_UHCI
   The Universal Host Controller Interface is a standard by Intel for
@@ -12744,9 +13031,13 @@
 CONFIG_USB_HID
   Say Y here if you want full HID support to connect keyboards,
   mice, joysticks, graphic tablets, or any other HID based devices
-  to your computer via USB. You can't use this driver and the
-  HIDBP (Boot Protocol) keyboard and mouse drivers at the same time.
-  More information is available: <file:Documentation/input/input.txt>.
+  to your computer via USB. You also need to select HID Input layer
+  support (below) if you want to use keyboards, mice, joysticks and
+  the like.
+
+  You can't use this driver and the HIDBP (Boot Protocol) keyboard
+  and mouse drivers at the same time. More information is available:
+  <file:Documentation/input/input.txt>.
 
   If unsure, say Y.
 
@@ -12755,6 +13046,14 @@
   The module will be called hid.o. If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
+USB HID Input layer support
+CONFIG_USB_HIDINPUT
+  Say Y here if you want to use a USB keyboard, mouse or joystick,
+  or any other HID input device. You also need Input layer support, 
+  (CONFIG_INPUT) which you select under "Input core support".
+
+  If unsure, say Y.
+
 /dev/usb/hiddev raw HID device support
 CONFIG_USB_HIDDEV
   Say Y here if you want to support HID devices (from the USB
@@ -12765,33 +13064,37 @@
   event interface on /dev/usb/hiddevX (char 180:96 to 180:111).
   This driver requires CONFIG_USB_HID.
 
-  If unsure, say N.
+  If unsure, say Y.
 
 USB HIDBP Keyboard (basic) support
 CONFIG_USB_KBD
-  Say Y here if you don't want to use the generic HID driver for your
-  USB keyboard and prefer to use the keyboard in its limited Boot
-  Protocol mode instead. This driver is much smaller than the HID one.
+  Say Y here only if you are absolutely sure that you don't want
+  to use the generic HID driver for your USB keyboard and prefer
+  to use the keyboard in its limited Boot Protocol mode instead.
+
+  This is almost certainly not what you want.
 
   This code is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
   The module will be called usbkbd.o. If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
-  If unsure, say N.
+  If even remotely unsure, say N.
 
 USB HIDBP Mouse (basic) support
 CONFIG_USB_MOUSE
-  Say Y here if you don't want to use the generic HID driver for your
-  USB mouse and prefer to use the mouse in its limited Boot Protocol
-  mode instead. This driver is much smaller than the HID one.
+  Say Y here only if you are absolutely sure that you don't want
+  to use the generic HID driver for your USB keyboard and prefer
+  to use the keyboard in its limited Boot Protocol mode instead.
+
+  This is almost certainly not what you want.
 
   This code is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
   The module will be called usbmouse.o. If you want to compile it as
   a module, say M here and read <file:Documentation/modules.txt>.
 
-  If unsure, say N.
+  If even remotely unsure, say N.
 
 Wacom Intuos/Graphire tablet support
 CONFIG_USB_WACOM
@@ -12927,6 +13230,20 @@
   The module will be called audio.o. If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
+EMI 2|6 USB Audio interface support
+CONFIG_USB_EMI26
+  This driver loads firmware to Emagic EMI 2|6 low latency USB
+  Audio interface.
+
+  After firmware load the device is handled with standard linux
+  USB Audio driver.
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called audio.o. If you want to compile it as a
+  module, say M here and read <file:Documentation/modules.txt>.
+			
+
 USB Modem (CDC ACM) support
 CONFIG_USB_ACM
   This driver supports USB modems and ISDN adapters which support the
@@ -12985,9 +13302,10 @@
 
 USB Compaq iPAQ Driver
 CONFIG_USB_SERIAL_IPAQ
-  Say Y here if you want to connect to your Compaq iPAQ running
-  Windows CE 3.0 using a USB autosync cable. For information on using
-  the driver, read <file:Documentation/usb/usb-serial.txt>.
+  Say Y here if you want to connect to your Compaq iPAQ, HP Jornada 548/568
+  or Casio EM500 running Windows CE 3.0 or PocketPC 2002 using a USB
+  cradle/cable. For information on using the driver,
+  read <file:Documentation/usb/usb-serial.txt>.
 
   This code is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -13282,6 +13600,7 @@
         * Motorola (DM100 and SB4100)
         * Broadcom Cable Modem (reference design)
         * Toshiba PCX1100U and possibly other cable modems
+        * Sharp Zaurus SL-5000D
 
   The device creates a network device (ethX, where X depends on what
   other networking devices you have in use), as for a normal PCI
@@ -13375,18 +13694,29 @@
 
 Pegasus/Pegasus II based USB-Ethernet device support
 CONFIG_USB_PEGASUS
-  Say Y here if you know you have Pegasus or Pegasus II based adapter.
+  Say Y here if you know you have Pegasus or Pegasus-II based adapter.
   If in doubt then look at linux/drivers/usb/pegasus.h for the complete
   list of supported devices.
   If your particular adapter is not in the list and you are _sure_ it
-  is Pegasus or Pegasus II based then send me (pmanolov@lnxw.com) vendor
-  and device IDs.
-
+  is Pegasus or Pegasus-II based then send me (pmanolov@users.sourceforge.net)
+  vendor and device IDs.
+  
   This code is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
   The module will be called pegasus.o. If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
+Realtek RTL8150 based USB-Ethernet device support
+CONFIG_USB_RTL8150
+  Say Y here if you have RTL8150 based usb-ethernet adapter.
+  Send me (petkan@users.sourceforge.net) any comments you may have.
+  You can also check for updates at http://pegasus2.sourceforge.net/
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called rtl8150.o. If you want to compile it as a
+  module, say M here and read <file:Documentation/modules.txt>.
+
 USB KLSI KL5USB101-based Ethernet device support
 CONFIG_USB_KAWETH
   Say Y here if you want to use one of the following 10Mbps only
@@ -13621,6 +13951,27 @@
   The module will be called rio500.o. If you want to compile it as
   a module, say M here and read <file:Documentation/modules.txt>.
 
+USB Auerswald ISDN device support
+CONFIG_USB_AUERSWALD
+  Say Y here if you want to connect an Auerswald USB ISDN Device
+  to your computer's USB port.
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called auerswald.o. If you want to compile it as
+  a module, say M here and read <file:Documentation/modules.txt>.
+
+Tieman Voyager USB Braille display support
+CONFIG_USB_BRLVOYAGER
+  Say Y here if you want to use the Voyager USB Braille display from
+  Tieman. See <file:Documentation/usb/brlvger.txt> for more
+  information.
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called brlvger.o. If you want to compile it as
+  a module, say M here and read <file:Documentation/modules.txt>.
+
 D-Link DSB-R100 FM radio support
 CONFIG_USB_DSBR
   Say Y here if you want to connect this type of radio to your
@@ -13766,7 +14117,7 @@
   kernels can talk to each other, the host, and with the host's help,
   machines on the outside world.
 
-  For more information, including explations of the networking and
+  For more information, including explanations of the networking and
   sample configurations, see
   <http://user-mode-linux.sourceforge.net/networking.html>.
 
@@ -13991,10 +14342,10 @@
   by about 44 KB.
 
   The Ext2fs-Undeletion mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, gives information about
+  <http://www.tldp.org/docs.html#howto>, gives information about
   how to retrieve deleted files on ext2fs file systems.
 
-  To change the behavior of ext2 file systems, you can use the tune2fs
+  To change the behaviour of ext2 file systems, you can use the tune2fs
   utility ("man tune2fs"). To modify attributes of files and
   directories on ext2 file systems, use chattr ("man chattr").
 
@@ -14035,7 +14386,7 @@
   system.
 
   To add a journal on an existing ext2 file system or change the
-  behavior of ext3 file systems, you can use the tune2fs utility ("man
+  behaviour of ext3 file systems, you can use the tune2fs utility ("man
   tune2fs").  To modify attributes of files and directories on ext3
   file systems, use chattr ("man chattr").  You need to be using
   e2fsprogs version 1.20 or later in order to create ext3 journals
@@ -14066,7 +14417,7 @@
 
 JBD (ext3) debugging support
 CONFIG_JBD_DEBUG
-  If you are using the ext3 journaled file system (or potentially any
+  If you are using the ext3 journalling file system (or potentially any
   other file system/device using JBD), this option allows you to
   enable debugging output while the system is running, in order to
   help track down any problems you are having.  By default the
@@ -14177,7 +14528,7 @@
   Ramfs is a file system which keeps all files in RAM. It allows
   read and write access.
 
-  It is more of an programming example than a useable file system.  If
+  It is more of an programming example than a usable file system.  If
   you need a file system which lives in RAM with limit checking use
   tmpfs.
 
@@ -14195,7 +14546,7 @@
   driver.  If you have a CD-ROM drive and want to do more with it than
   just listen to audio CDs and watch its LEDs, say Y (and read
   <file:Documentation/filesystems/isofs.txt> and the CD-ROM-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>), thereby
+  available from <http://www.tldp.org/docs.html#howto>), thereby
   enlarging your kernel by about 27 KB; otherwise say N.
 
   If you want to compile this as a module ( = code which can be
@@ -14293,7 +14644,7 @@
   they are compressed; to access compressed MSDOS partitions under
   Linux, you can either use the DOS emulator DOSEMU, described in the
   DOSEMU-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>, or try dmsdosfs in
+  <http://www.tldp.org/docs.html#howto>, or try dmsdosfs in
   <ftp://ibiblio.org/pub/Linux/system/filesystems/dosfs/>. If you
   intend to use dosemu with a non-compressed MSDOS partition, say Y
   here) and MSDOS floppies. This means that file access becomes
@@ -14402,9 +14753,16 @@
   other useful pieces of information.  Sometimes this information is
   not present or incorrect.
 
-  Unless you expect to boot on a PReP system, there is not need to
+  Unless you expect to boot on a PReP system, there is no need to
   select Y.
 
+PReP residual data available in /proc/residual
+CONFIG_PROC_PREPRESIDUAL
+  Enabling this option will create a /proc/residual file which allows
+  you to get at the residual data on PReP systems.  You will need a tool
+  (lsresidual) to parse it.  If you aren't on a PReP system, you don't
+  want this.
+
 /dev file system support
 CONFIG_DEVFS_FS
   This is support for devfs, a virtual file system (like /proc) which
@@ -14450,7 +14808,7 @@
   programs nfsd and mountd (but does not need to have NFS file system
   support enabled in its kernel). NFS is explained in the Network
   Administrator's Guide, available from
-  <http://www.linuxdoc.org/docs.html#guide>, on its man page: "man
+  <http://www.tldp.org/docs.html#guide>, on its man page: "man
   nfs", and in the NFS-HOWTO.
 
   A superior but less widely used alternative to NFS is provided by
@@ -14513,7 +14871,7 @@
   as well.
 
   Please read the NFS-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   The NFS server is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -14674,10 +15032,12 @@
 
 QNX4 file system support (read only)
 CONFIG_QNX4FS_FS
-  This is the file system used by the operating system QNX 4. Say Y if
-  you intend to mount QNX hard disks or floppies. Unless you say Y to
-  "QNX4FS read-write support" below, you will only be able to read
-  these file systems.
+  This is the file system used by the real-time operating systems
+  QNX 4 and QNX 6 (the latter is also called QNX RTP).
+  Further information is available at <http://www.qnx.com/>.
+  Say Y if you intend to mount QNX hard disks or floppies.
+  Unless you say Y to "QNX4FS read-write support" below, you will
+  only be able to read these file systems.
 
   This file system support is also available as a module ( = code
   which can be inserted in and removed from the running kernel
@@ -14692,6 +15052,9 @@
 CONFIG_QNX4FS_RW
   Say Y if you want to test write support for QNX4 file systems.
 
+  It's currently broken, so for now:
+  answer N.
+
 Kernel automounter support
 CONFIG_AUTOFS_FS
   The automounter is a tool to automatically mount remote file systems
@@ -14884,7 +15247,7 @@
 
   Windows 2000 introduced the concept of Dynamic Disks to get around
   the limitations of the PC's partitioning scheme.  The Logical Disk
-  Manager allows the user to repartion a disk and create spanned,
+  Manager allows the user to repartition a disk and create spanned,
   mirrored, striped or RAID volumes, all without the need for
   rebooting.
 
@@ -15078,7 +15441,7 @@
   works only if the Windows machines use TCP/IP as the underlying
   transport protocol, and not NetBEUI.  For details, read
   <file:Documentation/filesystems/smbfs.txt> and the SMB-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   Note: if you just want your box to act as an SMB *server* and make
   files and printing services available to Windows clients (which need
@@ -15159,7 +15522,7 @@
   to mount NetWare file server volumes and to access them just like
   any other Unix directory.  For details, please read the file
   <file:Documentation/filesystems/ncpfs.txt> in the kernel source and
-  the IPX-HOWTO from <http://www.linuxdoc.org/docs.html#howto>.
+  the IPX-HOWTO from <http://www.tldp.org/docs.html#howto>.
 
   You do not have to say Y here if you want your Linux box to act as a
   file *server* for Novell NetWare clients.
@@ -15317,8 +15680,8 @@
   say Y here if you want to include the Latin 2 codepage used by DOS
   for much of Central and Eastern Europe. It has all the required
   characters for these languages: Albanian, Croatian, Czech, English,
-  Finnish, Hungarian, Irish, German, Polish, Romanian, Serbian (Latin
-  transcription), Slovak, Slovenian, and Sorbian.
+  Finnish, Hungarian, Irish, German, Polish, Rumanian, Serbian (Latin
+  transcription), Slovak, Slovenian, and Serbian.
 
 Codepage 855 (Cyrillic)
 CONFIG_NLS_CODEPAGE_855
@@ -15728,7 +16091,7 @@
 CPM SCC Ethernet
 CONFIG_SCC_ENET
   Enable Ethernet support via the Motorola MPC8xx serial
-  commmunications controller.
+  communications controller.
 
 # Choice: scc_ethernet
 Ethernet on SCC1
@@ -15746,7 +16109,7 @@
 
 Use Big CPM Ethernet Buffers
 CONFIG_ENET_BIG_BUFFERS
-  Allocate large buffers for MPC8xx Etherenet.  Increases throughput
+  Allocate large buffers for MPC8xx Ethernet.  Increases throughput
   and decreases the likelihood of dropped packets, but costs memory.
 
 Apple Desktop Bus (ADB) support
@@ -15793,7 +16156,7 @@
 HIL keyboard support
 CONFIG_HIL
   The "Human Interface Loop" is a older, 8-channel USB-like controller
-  used in Hewlette Packard PA-RISC based machines.  There are a few
+  used in Hewlett Packard PA-RISC based machines.  There are a few
   cases where it is seen on PC/MAC architectures as well, usually also
   manufactured by HP.  This driver is based off MACH and BSD drivers,
   and implements support for a keyboard attached to the HIL port.
@@ -15844,14 +16207,14 @@
   If you want to include a driver to support Nubus or LC-PDS
   Ethernet cards using an NS8390 chipset or its equivalent, say Y
   and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 Macintosh CS89x0 based Ethernet support
 CONFIG_MAC89x0
   Support for CS89x0 chipset based Ethernet cards.  If you have a
   Nubus or LC-PDS network (Ethernet) card of this type, say Y and
   read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -15864,7 +16227,7 @@
   Support for the onboard AMD 79C940 MACE Ethernet controller used in
   the 660AV and 840AV Macintosh.  If you have one of these Macintoshes
   say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 Macintosh SONIC based Ethernet support (onboard, NuBus, LC, CS)
 CONFIG_MACSONIC
@@ -15872,7 +16235,7 @@
   the onboard Ethernet in many Quadras as well as some LC-PDS,
   a few Nubus and all known Comm Slot Ethernet cards.  If you have
   one of these say Y and read the Ethernet-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -15885,14 +16248,14 @@
   This is the NCR 5380 SCSI controller included on most of the 68030
   based Macintoshes.  If you have one of these say Y and read the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 Macintosh NCR53c9[46] SCSI support
 CONFIG_SCSI_MAC_ESP
   This is the NCR 53c9x SCSI controller found on most of the 68040
   based Macintoshes.  If you have one of these say Y and read the
   SCSI-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
@@ -16225,7 +16588,7 @@
   box (as opposed to using a serial printer; if the connector at the
   printer has 9 or 25 holes ["female"], then it's serial), say Y.
   Also read the Printing-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   It is possible to share one parallel port among several devices
   (e.g. printer and ZIP drive) and it is safe to compile the
@@ -16394,6 +16757,13 @@
   If you have a Cobalt Networks system, you should say Y here,
   unless you are absolutely sure.
 
+IT8172G Sound
+CONFIG_SOUND_IT8172
+  Say Y here to support the on-board sound generator on the Integrated
+  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+  board at <http://www.mvista.com/allies/semiconductor/ite.html>.
+
 I2C support
 CONFIG_I2C
   I2C (pronounce: I-square-C) is a slow serial bus protocol used in
@@ -16492,6 +16862,28 @@
   <file:Documentation/modules.txt>.
   The module will be called i2c-elektor.o.
 
+ITE I2C Algorithm
+CONFIG_ITE_I2C_ALGO
+  This supports the use the ITE8172 I2C interface found on some MIPS
+  systems. Say Y if you have one of these. You should also say Y for
+  the ITE I2C peripheral driver support below.
+
+  This support is also available as a module. If you want to compile
+  it as a modules, say M here and read
+  <file:Documentation/modules.txt>.
+  The module will be called i2c-algo-ite.o.
+
+ITE I2C Adapter
+CONFIG_ITE_I2C_ADAP
+  This supports the ITE8172 I2C peripheral found on some MIPS
+  systems. Say Y if you have one of these. You should also say Y for
+  the ITE I2C driver algorithm support above.
+
+  This support is also available as a module. If you want to compile
+  it as a module, say M here and read
+  <file:Documentation/modules.txt>.
+  The module will be called i2c-adap-ite.o.
+
 I2C device interface
 CONFIG_I2C_CHARDEV
   Say Y here to use i2c-* device files, usually found in the /dev
@@ -16541,7 +16933,7 @@
   MouseSystem or Microsoft mouse (made by Logitech) that plugs into a
   COM port (rectangular with 9 or 25 pins). These people say N here.
   If you have something else, read the Busmouse-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. This HOWTO contains
+  <http://www.tldp.org/docs.html#howto>. This HOWTO contains
   information about all non-serial mice, not just bus mice.
 
   If you have a laptop, you either have to check the documentation or
@@ -16558,7 +16950,7 @@
   generally a round connector with 9 pins. Note that the newer mice
   made by Logitech don't use the Logitech protocol anymore; for those,
   you don't need this option.  You want to read the Busmouse-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -16578,7 +16970,7 @@
 
   Although PS/2 mice are not technically bus mice, they are explained
   in detail in the Busmouse-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   When using a PS/2 mouse, you can get problems if you want to use the
   mouse both on the Linux console and under X. Using the "-R" option
@@ -16591,7 +16983,7 @@
   This is a certain kind of PS/2 mouse used on the TI Travelmate. If
   you are unsure, try first to say N here and come back if the mouse
   doesn't work. Read the Busmouse-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
 PC110 digitizer pad support
 CONFIG_PC110_PAD
@@ -16609,7 +17001,7 @@
   These animals (also called Inport mice) are connected to an
   expansion board using a round connector with 9 pins. If this is what
   you have, say Y and read the Busmouse-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you are unsure, say N and read the HOWTO nevertheless: it will
   tell you what you have. Also be aware that several vendors talk
@@ -16625,7 +17017,7 @@
 CONFIG_ADBMOUSE
   Say Y here if you have this type of bus mouse (4 pin connector) as
   is common on Macintoshes.  You may want to read the Busmouse-HOWTO,
-  available from <http://www.linuxdoc.org/docs.html#howto>.
+  available from <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -16639,7 +17031,7 @@
   most mice by ATI are actually Microsoft busmice; you should say Y to
   "Microsoft busmouse support" above if you have one of those.  Read
   the Busmouse-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to compile this as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want),
@@ -17188,7 +17580,7 @@
   page on the WWW at
   <http://www.cs.utexas.edu/users/kharker/linux-laptop/> and the
   Battery Powered Linux mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   Note that, even if you say N here, Linux on the x86 architecture
   will issue the hlt instruction if nothing is to be done, thereby
@@ -17305,7 +17697,7 @@
   In order to use APM, you will need supporting software. For location
   and more information, read <file:Documentation/pm.txt> and the
   Battery Powered Linux mini-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   This driver does not spin down disk drives (see the hdparm(8)
   manpage ("man 8 hdparm") for that), and it doesn't turn off
@@ -17551,6 +17943,17 @@
   module, say M here and read <file:Documentation/modules.txt>.  Most
   people will say N.
 
+ALi M7101 Watchdog Timer
+CONFIG_ALIM7101_WDT
+  This is the driver for the hardware watchdog on the ALi M7101 PMU
+  as used in the x86 Cobalt servers.
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module is called alim7101_wdt.o.  If you want to compile it as a
+  module, say M here and read <file:Documentation/modules.txt>.  Most
+  people will say N.
+
 IB700 SBC Watchdog Timer
 CONFIG_IB700_WDT
   This is the driver for the hardware watchdog on the IB700 Single
@@ -17592,6 +17995,18 @@
   The module is called machzwd.o.  If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
+CONFIG_SC1200_WDT
+  This is a driver for National Semiconductor PC87307/PC97307 hardware
+  watchdog cards as found on the SC1200. This watchdog is mainly used
+  for power management purposes and can be used to power down the device
+  during inactivity periods (includes interrupt activity monitoring).
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module is called sc1200wdt.o.  If you want to compile it as a
+  module, say M here and read <file:Documentation/modules.txt>.  Most
+  people will say N.
+
 SuperH 3/4 Watchdog
 CONFIG_SH_WDT
   This driver adds watchdog support for the integrated watchdog in the
@@ -17602,12 +18017,34 @@
   inserted in and removed from the running kernel whenever you want).
   The module is called shwdt.o. If you want to compile it as a module,
   say M here and read Documentation/modules.txt.
+
+Wafer 5823 Watchdog
+CONFIG_WAFER_WDT
+  This is a driver for the hardware watchdog on the ICP Wafer 5823
+  Single Board Computer (and probably other similar models).
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  If you want to compile it as a module, say M here and read
+  <file:Documentation/modules.txt>. The module will be called
+  wafer5823wdt.o
 	      
+Machine Check Exception
+CONFIG_X86_MCE
+  Machine Check Exception support allows the processor to notify the
+  kernel if it detects a problem (e.g. overheating, component failure).
+  The action the kernel takes depends on the severity of the problem, 
+  ranging from a warning message on the console, to halting the machine.
+  You can safely select this on machines that do not support this feature.
+
+  For pentium machines the mce support defaults to off as the mainboard
+  support is not always present. You must activate it as a boot option.
+
 Toshiba Laptop support
 CONFIG_TOSHIBA
   This adds a driver to safely access the System Management Mode of
   the CPU on Toshiba portables with a genuine Toshiba BIOS. It does
-  not work on models with a Pheonix BIOS. The System Management Mode
+  not work on models with a Phoenix BIOS. The System Management Mode
   is used to set the BIOS and power saving options on Toshiba portables.
 
   For information on utilities to make use of this driver see the
@@ -17690,6 +18127,28 @@
   CPU-1410 cards.  These are PC/104 SBCs. Spec sheets and product 
   information are at <http://www.eurotech.it/>.
 
+W83877F Watchdog Timer
+CONFIG_W83877F_WDT
+ This is the driver for the hardware watchdog on the W83877F chipset
+ as used in EMACS PC-104 motherboards (and may work on others). This
+ watchdog simply watches your kernel to make sure it doesn't freeze,
+ and if it does, it reboots your computer after a certain amount of
+ time.
+
+ You can compile this driver directly into the kernel, or use
+ it as a module.  The module will be called w83877f_wdt.o.
+
+SC520 (AMD Elan) Watchdog Timer
+CONFIG_SC520_WDT
+ This is the driver for the hardware watchdog built in to the
+ AMD "Elan" SC520 microcomputer commonly used in embedded systems.
+ This watchdog simply watches your kernel to make sure it doesn't
+ freeze, and if it does, it reboots your computer after a certain
+ amount of time.
+
+ You can compile this driver directly into the kernel, or use
+ it as a module.  The module will be called sc520_wdt.o.
+
 Enhanced Real Time Clock Support
 CONFIG_RTC
   If you say Y here and create a character special file /dev/rtc with
@@ -18142,7 +18601,7 @@
   interrupt and DMA channel), because you will be asked for it.
 
   You want to read the Sound-HOWTO, available from
-  <http://www.linuxdoc.org/docs.html#howto>. General information about
+  <http://www.tldp.org/docs.html#howto>. General information about
   the modular sound system is contained in the files
   <file:Documentation/sound/Introduction>.  The file
   <file:Documentation/sound/README.OSS> contains some slightly
@@ -18184,7 +18643,7 @@
   then you can get the persistent DMA buffer functionality by passing
   the command-line argument "dmabuf=1" to the sound.o module.
 
-  Say Y unless you have 16MB or more RAM or a PCI sound card.
+  Say Y unless you have 16MB or less RAM or a PCI sound card.
 
 Support for Aztech Sound Galaxy (non-PnP) cards
 CONFIG_SOUND_SGALAXY
@@ -18360,6 +18819,12 @@
   <file:Documentation/sound/vwsnd> for more info on this driver's
   capabilities.
 
+NEC Vrc5477 AC97 sound
+CONFIG_SOUND_VRC5477
+  Say Y here to enable sound support for the NEC Vrc5477 chip, an
+  integrated, multi-function controller chip for MIPS CPUs.  Works
+  with the AC97 codec.
+
 Ensoniq SoundScape support
 CONFIG_SOUND_SSCAPE
   Answer Y if you have a sound card based on the Ensoniq SoundScape
@@ -18636,7 +19101,7 @@
   Say Y here if you have a Sound Blaster SB32, AWE32-PnP, SB AWE64 or
   similar sound card. See <file:Documentation/sound/README.awe>,
   <file:Documentation/sound/AWE32> and the Soundblaster-AWE
-  mini-HOWTO, available from <http://www.linuxdoc.org/docs.html#howto>
+  mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>
   for more info.
 
 Gallant Audio Cards (SC-6000 and SC-6600 based)
@@ -18707,6 +19172,12 @@
   driver as a module you have to specify the MPU I/O base address with
   the parameter 'mpu_base=0xNNN'.
 
+SC-6600 CDROM Interface (4=None, 3=IDE, 1=Panasonic, 0=?Sony?)
+CONFIG_SC6600_CDROM
+  This is used to activate the CD-ROM interface of the Audio Excel
+  DSP 16 card. Enter: 0 for Sony, 1 for Panasonic, 2 for IDE, 4 for no
+  CD-ROM present.
+
 C-Media PCI (CMI8338/8378)
 CONFIG_SOUND_CMPCI
   Say Y or M if you have a PCI sound card using the CMI8338
@@ -18750,20 +19221,57 @@
   This package will among other things help you enable SPDIF 
   out/in/loop/monitor.
 
+Enable legacy FM
+CONFIG_SOUND_CMPCI_FM
+  Say Y here to enable the legacy FM (frequency-modulation) synthesis
+  support on a card using the CMI8338 or CMI8378 chipset.
+
+FM I/O 388, 3C8, 3E0, 3E8
+CONFIG_SOUND_CMPCI_FMIO
+  Set the base I/O address for FM synthesis control on a card using
+  the CMI8338 or CMI8378 chipset.
+
+Enable legacy MPU-401
+CONFIG_SOUND_CMPCI_MIDI
+  Say Y here to enable the legacy MP401 MIDI synthesis support on a
+  card using the CMI8338 or CMI8378 chipset.
+
+MPU-401 I/O 330, 320, 310, 300
+CONFIG_SOUND_CMPCI_MPUIO
+  Set the base I/O address for MP401 MIDI synthesis control on a card
+  using the CMI8338 or CMI8378 chipset.
+
+Inverse S/PDIF in for CMI8738
+CONFIG_SOUND_CMPCI_SPDIFINVERSE
+  Say Y here to have the driver invert the signal presented on SPDIF IN
+  of a card using the CMI8338 or CMI8378 chipset.
+
+Use Line-in as Read-out
+CONFIG_SOUND_CMPCI_LINE_REAR
+  Say Y here to enable using line-in jack as an output jack for a rear
+  speaker.
+
+Use Line-in as Bass
+CONFIG_SOUND_CMPCI_LINE_BASS
+  Say Y here to enable using line-in jack as an output jack for a bass
+  speaker.
+
 Creative SBLive! (EMU10K1) based PCI sound cards
 CONFIG_SOUND_EMU10K1
   Say Y or M if you have a PCI sound card using the EMU10K1 chipset,
   such as the Creative SBLive!, SB PCI512 or Emu-APS.
 
-  For more information on this driver and the degree of support for the
-  different card models please check <http://opensource.creative.com/>.
+  For more information on this driver and the degree of support for
+  the different card models please check:
+
+	<http://sourceforge.net/projects/emu10k1/>
 
   It is now possible to load dsp microcode patches into the EMU10K1
   chip.  These patches are used to implement real time sound
   processing effects which include for example: signal routing,
   bass/treble control, AC3 passthrough, ...
   Userspace tools to create new patches and load/unload them can be
-  found at <http://opensource.creative.com/dist.html>.
+  found in the emu-tools package at the above URL.
 
 Creative SBLive! (EMU10K1) MIDI
 CONFIG_MIDI_EMU10K1
@@ -18919,8 +19427,21 @@
 
 Intel ICH audio support
 CONFIG_SOUND_ICH
-  Support for integral audio in Intel's I/O Controller Hub (ICH)
-  chipset, as used on the 810/820/840 motherboards.
+  Supports the following chipsets:
+  
+  Intel ICH 82801AA
+  Intel ICH 82901AB
+  Intel 440 MX
+  Intel ICH2
+  Intel ICH3
+  SiS 7012
+  NVidia nForce
+  AMD 768
+  
+  These are audio drivers for integral audio in chipsets of motherboards.
+  
+  Intel's I/O Controller Hub (ICH) is used on 810/815/820/840/845/845D/850 motherboards.
+  SiS 7012 is used on 645/735/745 motherboards.
 
 Verbose initialization
 CONFIG_SOUND_TRACEINIT
@@ -18943,8 +19464,11 @@
 
 Yamaha YMF7xx PCI audio (native mode)
 CONFIG_SOUND_YMFPCI
-  Support for Yamaha cards including the YMF711, YMF715, YMF718,
-  YMF719, YMF724, Waveforce 192XG, and Waveforce 192 Digital.
+  Support for Yamaha cards with the following chipsets: YMF724,
+  YMF724F, YMF740, YMF740C, YMF744, and YMF754.
+
+  Two common cards that use this type of chip are Waveforce 192XG,
+  and Waveforce 192 Digital.
 
 Yamaha PCI legacy ports support
 CONFIG_SOUND_YMFPCI_LEGACY
@@ -18952,8 +19476,9 @@
 
 RME Hammerfall (RME96XX) support
 CONFIG_SOUND_RME96XX
-  Say Y or M if you have a Hammerfall, Hammerfall light or Hammerfall
-  DSP card from RME.
+  Say Y or M if you have a Hammerfall or Hammerfall light multichannel card 
+  from RME. If you want to acess advanced features of the card, read
+  Documentation/sound/rme96xx.
 
 Are you using a crosscompiler
 CONFIG_CROSSCOMPILE
@@ -18997,7 +19522,7 @@
 
 Support for Globespan IVR board
 CONFIG_MIPS_IVR
-  This is an evaluation board built by Globespan to showcase thir
+  This is an evaluation board built by Globespan to showcase their
   iVR (Internet Video Recorder) design. It utilizes a QED RM5231
   R5000 MIPS core. More information can be found out their website
   located at <http://www.globespan.net/products/product4.html>P. Say Y
@@ -19005,7 +19530,7 @@
 
 Support for Alchemy Semi PB1000 board
 CONFIG_MIPS_PB1000
-  This is an evaluation board built by Alchemy Semiconducttor to
+  This is an evaluation board built by Alchemy Semiconductor to
   showcase their Au1000 Internet Edge Processor. It is SOC design
   containing a MIPS32 core running at 266/400/500MHz with many
   integrated peripherals. Further information can be found at their
@@ -19504,6 +20029,10 @@
   This enables the PCMCIA client driver for the Sedlbauer Speed Star
   and Speed Star II cards.
 
+CONFIG_HISAX_AVM_A1_CS
+  This enables the PCMCIA client driver for the AVM A1 / Fritz!Card
+  PCMCIA cards.
+
 ST5481 USB ISDN modem
 CONFIG_HISAX_ST5481
   This enables the driver for ST5481 based USB ISDN adapters,
@@ -19854,6 +20383,11 @@
   found on many Sun machines. Note that many of the newer Ultras
   actually have pc style hardware instead.
 
+SPARC power management support
+CONFIG_SUN_PM
+  Enable power management and CPU standby features on supported 
+  SPARC platforms. 
+
 /proc/hardware support
 CONFIG_PROC_HARDWARE
   Say Y here to support the /proc/hardware file, which gives you
@@ -19870,11 +20404,12 @@
   Bluetooth can be found at <http://www.bluetooth.com/>.
 
   Linux Bluetooth subsystem consist of several layers:
-               HCI Core (device and connection manager, scheduler)
+               BlueZ Core (HCI device and connection manager, scheduler)
                HCI Device drivers (interface to the hardware)
                L2CAP Module (L2CAP protocol)
+               SCO Module (SCO links)
 
-  Say Y here to enable Linux Bluetooth support and to build HCI Core
+  Say Y here to enable Linux Bluetooth support and to build BlueZ Core
   layer.
 
   To use Linux Bluetooth subsystem, you will need several user-space
@@ -19882,7 +20417,7 @@
   Bluetooth kernel modules are provided in the BlueZ package.
   For more information, see <http://bluez.sourceforge.net/>.
 
-  If you want to compile HCI Core as module (hci.o) say M here.
+  If you want to compile BlueZ Core as module (bluez.o) say M here.
 
 L2CAP protocol support
 CONFIG_BLUEZ_L2CAP
@@ -19893,15 +20428,33 @@
   Say Y here to compile L2CAP support into the kernel or say M to
   compile it as module (l2cap.o).
 
+SCO links support
+CONFIG_BLUEZ_SCO
+  SCO link provides voice transport over Bluetooth. SCO support is
+  required for voice applications like Headset and Audio.
+
+  Say Y here to compile SCO support into the kernel or say M to
+  compile it as module (sco.o).
+
 HCI UART driver
 CONFIG_BLUEZ_HCIUART
   Bluetooth HCI UART driver.
   This driver is required if you want to use Bluetooth devices with
-  serial port interface.
+  serial port interface. You will also need this driver if you have 
+  UART based Bluetooth PCMCIA and CF devices like Xircom Credit Card 
+  adapter and BrainBoxes Bluetooth PC Card.
 
   Say Y here to compile support for Bluetooth UART devices into the
   kernel or say M to compile it as module (hci_uart.o).
 
+HCI UART (H4) protocol support 
+CONFIG_BLUEZ_HCIUART_H4
+  UART (H4) is serial protocol for communication between Bluetooth 
+  device and host. This protocol is required for most UART based 
+  Bluetooth device (including PCMCIA and CF). 
+
+  Say Y here to compile support for HCI UART (H4) protocol.
+
 HCI USB driver
 CONFIG_BLUEZ_HCIUSB
   Bluetooth HCI USB driver.
@@ -19911,7 +20464,24 @@
   Say Y here to compile support for Bluetooth USB devices into the
   kernel or say M to compile it as module (hci_usb.o).
 
-HCI VHCI virtual HCI device driver
+HCI USB firmware download support
+CONFIG_BLUEZ_USB_FW_LOAD
+  Firmware download support for Bluetooth USB devices.
+  This support is required for devices like Broadcom BCM2033.
+
+  HCI USB driver uses external firmware downloader program provided 
+  in BlueFW package.
+  For more information, see <http://bluez.sf.net/>.
+
+HCI USB zero packet support
+CONFIG_BLUEZ_USB_ZERO_PACKET
+  Support for USB zero packets. 
+  This option is provided only as a work around for buggy Bluetooth USB 
+  devices. Do _not_ enable it unless you know for sure that your device 
+  requires zero packets.
+  Most people should say N here.
+
+HCI VHCI Virtual HCI device driver
 CONFIG_BLUEZ_HCIVHCI
   Bluetooth Virtual HCI device driver.
   This driver is required if you want to use HCI Emulation software.
@@ -19919,6 +20489,16 @@
   Say Y here to compile support for virtual HCI devices into the
   kernel or say M to compile it as module (hci_vhci.o).
 
+HCI DTL1 (PC Card) device driver
+CONFIG_BLUEZ_HCIDTL1
+  Bluetooth HCI DTL1 (PC Card) driver.
+  This driver provides support for Bluetooth PCMCIA devices with
+  Nokia DTL1 interface:
+     Nokia Bluetooth PC Card, Socketcom Bluetooth CF module
+
+  Say Y here to compile support for HCI DTL1 devices into the
+  kernel or say M to compile it as module (dtl1_cs.o).
+
 # The following options are for Linux when running on the Hitachi
 # SuperH family of RISC microprocessors.
 
@@ -20027,9 +20607,13 @@
 Sun 3 support
 CONFIG_SUN3
   This option enables support for the Sun 3 series of workstations.
-  Currently, only the Sun 3/80 is supported within the Sun 3x family.
-  You will also want to enable 68030 support.  General Linux
-  information on the Sun 3x series (now discontinued) is at
+  Note that if this option is enabled, support for all other m68k 
+  platforms above must be disabled in order to produce a working 
+  kernel.
+
+  Also, you will want to enable 68020 support below, and disable 
+  all other CPU types.  General Linux information on the Sun 3x series
+  (now discontinued) is at
   <http://www.angelfire.com/ca2/tech68k/sun3.html>.
 
   If you don't want to compile a kernel for a Sun 3, say N.
@@ -20037,8 +20621,8 @@
 Sun 3X support
 CONFIG_SUN3X
   This option enables support for the Sun 3x series of workstations.
-  Be warned that this support is very experimental. You will also want
-  to say Y to 68020 support and N to the other processors below.
+  Currently, only the Sun 3/80 is supported within the Sun 3x family.
+  You will also want to enable 68030 support below  
   General Linux information on the Sun 3x series (now discontinued)
   is at <http://www.angelfire.com/ca2/tech68k/sun3.html>.
 
@@ -20049,8 +20633,7 @@
   ZS refers to a type of asynchronous serial port built in to the Sun3
   and Sun3x workstations; if you have a Sun 3, you probably have
   these.  Say 'Y' to support ZS ports directly.  This option must be
-  enabled in order to support the
-  keyboard and mouse ports.
+  enabled in order to support the keyboard and mouse ports.
 
 Sun keyboard support
 CONFIG_SUN_KEYBOARD
@@ -20189,8 +20772,8 @@
 
 Support for ST-RAM as swap space
 CONFIG_STRAM_SWAP
-  Some Atari 68k macines (including the 520STF and 1020STE) divide
-  their addressible memory into ST and TT sections.  The TT section
+  Some Atari 68k machines (including the 520STF and 1020STE) divide
+  their addressable memory into ST and TT sections.  The TT section
   (up to 512MB) is the main memory; the ST section (up to 4MB) is
   accessible to the built-in graphics board, runs slower, and is
   present mainly for backward compatibility with older machines.
@@ -20348,6 +20931,17 @@
   Hades. This increases the SCSI transfer rates at least ten times
   compared to PIO transfers.
 
+Sun3 NCR5380 OBIO SCSI
+CONFIG_SUN3_SCSI
+  This option will enable support for the OBIO (onboard io) NCR5380
+  SCSI controller found in the Sun 3/50 and 3/60.  Note that this
+  driver does not provide support for VME SCSI boards.
+
+Sun3x ESP SCSI
+CONFIG_SUN3X_ESP
+  This option will enable support for the ESP SCSI controller found
+  onboard the Sun 3/80.
+
 Ariadne support
 CONFIG_ARIADNE
   If you have a Village Tronic Ariadne Ethernet adapter, say Y.
@@ -20411,6 +21005,19 @@
   want). The module is called apne.o. If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
+Sun3/Sun3x on-board LANCE support
+CONFIG_SUN3LANCE
+  This driver enables support for the on-board LANCE ethernet adapter
+  found on the Sun 3/50, 3/60, and 3/80 workstations.  If you have 
+  one of these workstations, and would like Ethernet, say Y. 
+  Otherwise, say N.
+
+Sun3 on-board Intel 82586 support
+CONFIG_SUN3_82586
+  This driver enables support for the on-board Intel 82586 based Ethernet
+  adapter found on Sun 3/1xx and 3/2xx motherboards.  Note that this driver
+  does not support 82586-based adapters on additional VME boards.
+
 Atari Lance support
 CONFIG_ATARILANCE
   Say Y to include support for several Atari Ethernet adapters based
@@ -20801,7 +21408,7 @@
 Average high and low temp
 CONFIG_TAU_AVERAGE
   The TAU hardware can compare the temperature to an upper and lower bound.
-  The default behavior is to show both the upper and lower bound in
+  The default behaviour is to show both the upper and lower bound in
   /proc/cpuinfo. If the range is large, the temperature is either changing
   a lot, or the TAU hardware is broken (likely on some G4's). If the range
   is small (around 4 degrees), the temperature is relatively stable.
@@ -21662,6 +22269,18 @@
   Say Y here to include support for the Iomega Buz video card.  There
   is a Buz/Linux homepage at <http://www.lysator.liu.se/~gz/buz/>.
 
+Miro DC10(+) support
+CONFIG_VIDEO_ZORAN_DC10
+  Say Y to support the Pinnacle Systems Studio DC10 plus TV/Video
+  card.  Linux page at
+  <http://lhd.datapower.com/db/dispproduct.php3?DISP?1511>.  Vendor
+  page at <http://www.pinnaclesys.com/>.
+
+Linux Media Labs LML33 support
+CONFIG_VIDEO_ZORAN_LML33
+  Say Y here to support the Linux Media Labs LML33 TV/Video card.
+  Resources page is at <http://www.linuxmedialabs.com/lml33doc.html>.
+
 Zoran ZR36120/36125 Video For Linux
 CONFIG_VIDEO_ZR36120
   Support for ZR36120/ZR36125 based frame grabber/overlay boards.
@@ -22409,12 +23028,12 @@
   you are concerned with the code size or don't want to see these
   messages.
 
-Compile kernel without frame pointer
-CONFIG_NO_FRAME_POINTER
-  If you say Y here, the resulting kernel will be slightly smaller and
-  faster. However, when a problem occurs with the kernel, the
-  information that is reported is severely limited. Most people
-  should say N here.
+Compile kernel with frame pointer
+CONFIG_FRAME_POINTER
+  If you say Y here, the resulting kernel will be slightly larger and
+  slower, but it will give very useful debugging information. If you
+  don't debug the kernel, you can say N, but we may not be able to
+  solve problems without frame pointers.
 
 Verbose user fault messages
 CONFIG_DEBUG_USER
@@ -22568,7 +23187,7 @@
 MFM hard disk support
 CONFIG_BLK_DEV_MFM
   Support the MFM hard drives on the Acorn Archimedes both
-  on-board the A4x0 motherboards and via the Acorn MFM podules.
+  on-board the A4x0 motherboards and via the Acorn MFM modules.
   Drives up to 64MB are supported. If you haven't got one of these
   machines or drives just say N.
 
@@ -22641,7 +23260,7 @@
   some user-space utilities like irattach.  For more information, see
   the file <file:Documentation/networking/irda.txt>.  You also want to
   read the IR-HOWTO, available at
-  <http://www.linuxdoc.org/docs.html#howto>.
+  <http://www.tldp.org/docs.html#howto>.
 
   If you want to exchange bits of data (vCal, vCard) with a PDA, you
   will need to install some OBEX application, such as OpenObex :
@@ -22719,7 +23338,7 @@
   will also need a working PPP subsystem (driver, daemon and
   config)...
 
-  IrNET is an alternate way to tranfer TCP/IP traffic over IrDA.  It
+  IrNET is an alternate way to transfer TCP/IP traffic over IrDA.  It
   uses synchronous PPP over a set of point to point IrDA sockets.  You
   can use it between Linux machine or with W2k.
 
@@ -22767,7 +23386,7 @@
   device driver.  If you want to compile it as a module (irda-usb.o),
   say M here and read <file:Documentation/modules.txt>.  IrDA-USB
   support the various IrDA USB dongles available and most of their
-  pecularities.  Those dongles plug in the USB port of your computer,
+  peculiarities.  Those dongles plug in the USB port of your computer,
   are plug and play, and support SIR and FIR (4Mbps) speeds.  On the
   other hand, those dongles tend to be less efficient than a FIR
   chipset.
@@ -23279,7 +23898,7 @@
 
 Etrax bus waitstates
 CONFIG_ETRAX_DEF_R_WAITSTATES
-  Waitstates for SRAM, Flash and peripherials (not DRAM).  95f8 is a
+  Waitstates for SRAM, Flash and peripherals (not DRAM).  95f8 is a
   good choice for most Axis products...
 
 Etrax bus configuration
@@ -23443,13 +24062,13 @@
 
 Etrax100 RS-485 mode on PA
 CONFIG_ETRAX_RS485_ON_PA
-  Control Driver Output Enable on RS485 tranceiver using a pin on PA
+  Control Driver Output Enable on RS485 transceiver using a pin on PA
   port:
           Axis 2400/2401 uses PA 3.
 
 Etrax100 RS-485 mode on PA bit
 CONFIG_ETRAX_RS485_ON_PA_BIT
-  Control Driver Output Enable on RS485 tranceiver using a this bit
+  Control Driver Output Enable on RS485 transceiver using a this bit
   on PA port.
 
 Ser0 DTR on PB bit
@@ -24109,12 +24728,12 @@
 CONFIG_SH_GENERIC
   Select Generic if configuring for a generic SuperH system.
   The "generic" option compiles in *all* the possible hardware
-  support and relies on the sh_mv= kernel commandline option to choose
+  support and relies on the sh_mv= kernel command option to choose
   at runtime which routines to use.  "MV" stands for "machine vector";
   each of the machines below is described by a machine vector.
 
   Select SolutionEngine if configuring for a Hitachi SH7709
-  or SH7750/7750S evalutation board.
+  or SH7750/7750S evaluation board.
 
   Select Overdrive if configuring for a ST407750 Overdrive board.
   More information at
@@ -24162,12 +24781,12 @@
 SolutionEngine
 CONFIG_SH_SOLUTION_ENGINE
   Select SolutionEngine if configuring for a Hitachi SH7709
-  or SH7750 evalutation board.
+  or SH7750 evaluation board.
 
 7751 SolutionEngine
 CONFIG_SH_7751_SOLUTION_ENGINE
   Select 7751 SolutionEngine if configuring for a Hitachi SH7751
-  evalutation board.
+  evaluation board.
 
 Overdrive
 CONFIG_SH_OVERDRIVE
@@ -24382,6 +25001,285 @@
   information:  http://www.candelatech.com/~greear/vlan.html  If unsure,
   you can safely say 'N'.
 
+ARC console support
+CONFIG_ARC_CONSOLE
+  Support for the PROM-based console on MIPS machines built according
+  to the Advanced Risc Computing specification, which is now (2001)
+  dead.  These included boxes from Deskstation, Acer, Olivetti and
+  NEC.  There is a history at <http://www.openbsd.org/arc.html>.
+
+AUTCPU12
+CONFIG_ARCH_AUTCPU12
+  Say Y if you intend to run the kernel on the autronix autcpu12
+  board. This board is based on a Cirrus Logic CS89712.
+
+IT8172 IDE support
+CONFIG_BLK_DEV_IT8172
+  Say Y here to support the on-board IDE controller on the Integrated
+  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+  board at <http://www.mvista.com/allies/semiconductor/ite.html>.
+
+Use chscs for Common I/O
+CONFIG_CHSC
+  Select this option if you want the s390 common I/O layer to use information
+  obtained by channel subsystem calls. This will enable Linux to process link
+  failures and resource accessibility events. Moreover, if you have procfs
+  enabled, you'll be able to toggle chpids logically offline and online. Even
+  if you don't understand what this means, you should say "Y".
+
+Support ARM926T processor
+CONFIG_CPU_ARM926T
+  This is a variant of the ARM920.  It has slightly different
+  instruction sequences for cache and TLB operations.  Curiously,
+  there is no documentation on it at the ARM corporate website.
+
+  Say Y if you want support for the ARM926T processor.
+  Otherwise, say N.
+
+Support CPU clock change (EXPERIMENTAL)
+CONFIG_CPU_FREQ
+  CPU clock scaling allows you to change the clock speed of the
+  running CPU on the fly. This is a nice method to save battery power,
+  because the lower the clock speed, the less power the CPU
+  consumes. Note that this driver doesn't automatically change the CPU
+  clock speed, you need some userland tools (which still have to be
+  written) to implement the policy. If you don't understand what this
+  is all about, it's safe to say 'N'.
+
+Automatic activation of DIAG module
+CONFIG_DASD_AUTO_DIAG
+  Enable this option if you want your DIAG discipline module loaded
+  on DASD driver startup.
+
+Automatic activation of ECKD module
+CONFIG_DASD_AUTO_ECKD
+  Enable this option if you want your ECKD discipline module loaded
+  on DASD driver startup.
+
+Automatic activation of FBA  module
+CONFIG_DASD_AUTO_FBA
+  Enable this option if you want your FBA discipline module loaded
+  on DASD driver startup.
+
+SiS
+CONFIG_DRM_SIS
+  Choose this option if you have a SIS graphics card. AGP support is
+  required for this driver to work.
+
+Etrax Ethernet slave support (over lp0/1)
+CONFIG_ETRAX_ETHERNET_LPSLAVE
+  This option enables a slave ETRAX 100 or ETRAX 100LX, connected to a
+  master ETRAX 100 or ETRAX 100LX through par0 and par1, to act as an
+  Ethernet controller.
+
+Slave has its own LEDs
+CONFIG_ETRAX_ETHERNET_LPSLAVE_HAS_LEDS
+  Enable if the slave has it's own LEDs.
+
+ATA/IDE support
+CONFIG_ETRAX_IDE
+  Enable this to get support for ATA/IDE.  You can't use parallel
+  ports or SCSI ports at the same time.
+
+LED on when link
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK
+
+  Selecting LED_on_when_link will light the LED when there is a
+  connection and will flash off when there is activity.
+
+  Selecting LED_on_when_activity will light the LED only when
+  there is activity.
+
+  This setting will also affect the behaviour of other activity LEDs
+  e.g. Bluetooth.
+
+Power button bit on port G
+CONFIG_ETRAX_POWERBUTTON_BIT
+  Configure where power button is connected.
+
+Root device name
+CONFIG_ETRAX_ROOT_DEVICE
+  Specifies the device that should be mounted as root file system
+  when booting from flash. The axisflashmap driver adds an additional
+  mtd partition for the appended root file system image, so this option
+  should normally be the mtdblock device for the partition after the
+  last partition in the partition table.
+
+Serial port 0 enabled
+CONFIG_ETRAX_SERIAL_PORT0
+  Enables the ETRAX 100 serial driver for ser0 (ttyS0)
+  Normally you want this on, unless you use external DMA 1 that uses
+  the same DMA channels.
+
+Shutdown bit on port CSP0
+CONFIG_ETRAX_SHUTDOWN_BIT
+  Configure what pin on CSPO-port that is used for controlling power
+  supply.
+
+Software Shutdown Support
+CONFIG_ETRAX_SOFT_SHUTDOWN
+  Enable this if Etrax is used with a power-supply that can be turned
+  off and on with PS_ON signal. Gives the possibility to detect
+  powerbutton and then do a power off after unmounting disks.
+
+Disable watchdog during Oops printouts
+CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+  By enabling this you make sure that the watchdog does not bite while
+  printing oopses. Recommended for development systems but not for
+  production releases.
+
+Compaq iPAQ Handheld sleeve support
+CONFIG_H3600_SLEEVE
+  Choose this option to enable support for extension packs (sleeves)
+  for the Compaq iPAQ H3XXX series of handheld computers.  This option
+  is required for the CF, PCMCIA, Bluetooth and GSM/GPRS extension
+  packs.
+
+AVM Fritz!Card PCI/PCIv2/PnP support (EXPERIMENTAL)
+CONFIG_HISAX_FRITZ_PCIPNP
+  This enables the driver for the AVM Fritz!Card PCI, Fritz!Card PCI v2
+  and Fritz!Card PnP.
+  (the latter also needs you to select "ISA Plug and Play support"
+  from the menu "Plug and Play configuration")
+
+IBM PCI Hotplug driver
+CONFIG_HOTPLUG_PCI_IBM
+  Say Y here if you have a motherboard with a IBM PCI Hotplug
+  controller.
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called cpqphp.o. If you want to compile it
+  as a module, say M here and read Documentation/modules.txt.
+
+  When in doubt, say N.
+
+Control-Program Identification
+CONFIG_HWC_CPI
+  This option enables the hardware console interface for system
+  identification This is commonly used for workload management and
+  gives you a nice name for the system on the service element.
+  Please select this option as a module since built-in operation is
+  completely untested.
+  You should only select this option if you know what you are doing,
+  need this feature and intend to run your kernel in LPAR.
+
+Enable autotest (llsc). Option to run cache test instead of booting
+CONFIG_IA64_SGI_AUTOTEST
+  Build a kernel used for hardware validation. If you include the
+  keyword "autotest" on the boot command line, the kernel does NOT boot.
+  Instead, it starts all cpus and runs cache coherency tests instead.
+
+  If unsure, say N.
+
+IEC61883-6 (Audio transmission) support
+CONFIG_IEEE1394_AMDTP
+  This option enables the Audio & Music Data Transmission Protocol
+  (IEC61883-6) driver, which implements audio transmission over
+  IEEE1394.
+
+  The userspace interface is documented in amdtp.h.
+
+  If you want to compile this as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want),
+  say M here and read Documentation/modules.txt.  The module
+  will be called amdtp.o.
+
+IEC61883-1 Plug support
+CONFIG_IEEE1394_CMP
+  This option enables the Connection Management Procedures
+  (IEC61883-1) driver, which implements input and output plugs.
+
+  If you want to compile this as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want),
+  say M here and read Documentation/modules.txt.  The module
+  will be called amdtp.o.
+
+OHCI-DV I/O support
+CONFIG_IEEE1394_DV1394
+  This driver allows you to transmit and receive DV (digital video)
+  streams on an OHCI-1394 card using a simple frame-oriented
+  interface.
+
+  The user-space API for dv1394 is documented in dv1394.h.
+
+  If you want to compile this as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want),
+  say M here and read Documentation/modules.txt.  The module
+  will be called dv1394.o.
+
+Ethernet over 1394
+CONFIG_IEEE1394_ETH1394
+  Extremely Experimental! This driver is a Linux specific way to use your
+  IEEE1394 Host as an Ethernet type device. This is _NOT_ IP1394.
+
+Support for older IT8172 (Rev C)
+CONFIG_IT8172_REVC
+  Say Y here to support the older, Revision C version of the Integrated
+  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+  board at <http://www.mvista.com/allies/semiconductor/ite.html>.
+
+Enable Smart Card Reader 0 Support
+CONFIG_IT8172_SCR0
+  Say Y here to support smart-card reader 0 (SCR0) on the Integrated
+  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+  board at <http://www.mvista.com/allies/semiconductor/ite.html>.
+
+Enable Smart Card Reader 1 Support
+CONFIG_IT8172_SCR1
+  Say Y here to support smart-card reader 1 (SCR1) on the Integrated
+  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+  board at <http://www.mvista.com/allies/semiconductor/ite.html>.
+
+IT8172 IDE Tuning support
+CONFIG_IT8172_TUNING
+  Say Y here to support tuning the ITE8172's IDE interface.  This makes
+  it possible to set DMA channel or PIO opration and the transfer rate.
+
+Process warning machine checks
+CONFIG_MACHCHK_WARNING
+  Select this option if you want the machine check handler on IBM S/390 or
+  zSeries to process warning machine checks (e.g. on power failures).
+  If unsure, say "Y".
+
+Pseudo page fault support
+CONFIG_PFAULT
+  Select this option, if you want to use PFAULT pseudo page fault
+  handling under VM. If running native or in LPAR, this option
+  has no effect. If your VM does not support PFAULT, PAGEEX
+  pseudo page fault handling will be used.
+  Note that VM 4.2 supports PFAULT but has a bug in its
+  implementation that causes some problems.
+  Everybody who wants to run Linux under VM != VM4.2 should select
+  this option.
+
+Enable protocol mode for the L1 console
+CONFIG_SERIAL_SGI_L1_PROTOCOL
+  Uses protocol mode instead of raw mode for the level 1 console on the
+  SGI SN (Scalable NUMA) platform for IA64.  If you are compiling for
+  an SGI SN box then Y is the recommended value, otherwise say N.
+
+VM shared kernel support
+CONFIG_SHARED_KERNEL
+  Select this option, if you want to share the text segment of the
+  Linux kernel between different VM guests. This reduces memory
+  usage with lots of guests but greatly increases kernel size.
+  You should only select this option if you know what you are
+  doing and want to exploit this feature.
+
+New bus configuration (EXPERIMENTAL)  
+CONFIG_TULIP_MWI
+  This configures your Tulip card specifically for the card and
+  system cache line size type you are using.
+
+  This is experimental code, not yet tested on many boards.
+
+  If unsure, say N.
+
 #
 # A couple of things I keep forgetting:
 #   capitalize: AppleTalk, Ethernet, DOS, DMA, FAT, FTP, Internet,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/DMA-mapping.txt linux/Documentation/DMA-mapping.txt
--- linux.orig/Documentation/DMA-mapping.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/DMA-mapping.txt	2002-08-01 06:42:45.000000000 +0000
@@ -8,7 +8,7 @@
 Most of the 64bit platforms have special hardware that translates bus
 addresses (DMA addresses) into physical addresses.  This is similar to
 how page tables and/or a TLB translates virtual addresses to physical
-addresses on a cpu.  This is needed so that e.g. PCI devices can
+addresses on a CPU.  This is needed so that e.g. PCI devices can
 access with a Single Address Cycle (32bit DMA address) any page in the
 64bit physical address space.  Previously in Linux those 64bit
 platforms had to set artificial limits on the maximum RAM size in the
@@ -37,7 +37,7 @@
 			 What memory is DMA'able?
 
 The first piece of information you must know is what kernel memory can
-be used with the DMA mapping facilitites.  There has been an unwritten
+be used with the DMA mapping facilities.  There has been an unwritten
 set of rules regarding this, and this text is an attempt to finally
 write them down.
 
@@ -106,7 +106,7 @@
 3) Ignore this device and do not initialize it.
 
 It is recommended that your driver print a kernel KERN_WARNING message
-when you end up performing either #2 or #2.  In this manner, if a user
+when you end up performing either #2 or #3.  In this manner, if a user
 of your driver reports that performance is bad or that the device is not
 even detected, you can ask them for the kernel messages to find out
 exactly why.
@@ -146,7 +146,7 @@
 If your 64-bit device is going to be an enormous consumer of DMA
 mappings, this can be problematic since the DMA mappings are a
 finite resource on many platforms.  Please see the "DAC Addressing
-for Address Space Hungry Devices" setion near the end of this
+for Address Space Hungry Devices" section near the end of this
 document for how to handle this case.
 
 Finally, if your device can only drive the low 24-bits of
@@ -205,7 +205,7 @@
 
 - Consistent DMA mappings which are usually mapped at driver
   initialization, unmapped at the end and for which the hardware should
-  guarantee that the device and the cpu can access the data
+  guarantee that the device and the CPU can access the data
   in parallel and will see updates made by each other without any
   explicit software flushing.
 
@@ -222,12 +222,12 @@
 	- Device firmware microcode executed out of
 	  main memory.
 
-  The invariant these examples all require is that any cpu store
+  The invariant these examples all require is that any CPU store
   to memory is immediately visible to the device, and vice
   versa.  Consistent mappings guarantee this.
 
   IMPORTANT: Consistent DMA memory does not preclude the usage of
-             proper memory barriers.  The cpu may reorder stores to
+             proper memory barriers.  The CPU may reorder stores to
 	     consistent memory just as it may normal memory.  Example:
 	     if it is important for the device to see the first word
 	     of a descriptor updated before the second, you must do
@@ -284,7 +284,7 @@
 the pci_pool interface, described below.
 
 The consistent DMA mapping interfaces, for non-NULL dev, will always
-return a DMA address which is SAC (Single Address Cycle) addressible.
+return a DMA address which is SAC (Single Address Cycle) addressable.
 Even if the device indicates (via PCI dma mask) that it may address
 the upper 32-bits and thus perform DAC cycles, consistent allocation
 will still only return 32-bit PCI addresses for DMA.  This is true
@@ -484,7 +484,7 @@
 of sg entries it mapped them to.
 
 Then you should loop count times (note: this can be less than nents times)
-and use sg_dma_address() and sg_dma_length() macros where you previously
+and use sg_dma_address() and sg_dma_len() macros where you previously
 accessed sg->address and sg->length as shown above.
 
 To unmap a scatterlist, just call:
@@ -622,7 +622,7 @@
 Note that for streaming type mappings you must either use these
 interfaces, or the dynamic mapping interfaces above.  You may not mix
 usage of both for the same device.  Such an act is illegal and is
-guarenteed to put a banana in your tailpipe.
+guaranteed to put a banana in your tailpipe.
 
 However, consistent mappings may in fact be used in conjunction with
 these interfaces.  Remember that, as defined, consistent mappings are
@@ -637,7 +637,7 @@
 use the following interfaces if this routine fails.
 
 Next, DMA addresses using this API are kept track of using the
-dma64_addr_t type.  It is guarenteed to be big enough to hold any
+dma64_addr_t type.  It is guaranteed to be big enough to hold any
 DAC address the platform layer will give to you from the following
 routines.  If you have consistent mappings as well, you still
 use plain dma_addr_t to keep track of those.
@@ -745,7 +745,7 @@
 			 PCI_DMA_FROMDEVICE);
 
 It really should be self-explanatory.  We treat the ADDR and LEN
-seperately, because it is possible for an implementation to only
+separately, because it is possible for an implementation to only
 need the address in order to perform the unmap operation.
 
 			Platform Issues
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/DocBook/Makefile linux/Documentation/DocBook/Makefile
--- linux.orig/Documentation/DocBook/Makefile	2001-11-03 01:13:53.000000000 +0000
+++ linux/Documentation/DocBook/Makefile	2002-08-01 06:42:43.000000000 +0000
@@ -23,6 +23,8 @@
 
 html:	$(HTML)
 
+man:	kernel-api-man
+
 %.eps: %.fig
 	fig2dev -Leps $< $@
 
@@ -93,6 +95,8 @@
 		$(TOPDIR)/drivers/net/8390.c \
 		$(TOPDIR)/drivers/char/serial.c \
 		$(TOPDIR)/drivers/pci/pci.c \
+		$(TOPDIR)/drivers/hotplug/pci_hotplug_core.c \
+		$(TOPDIR)/drivers/hotplug/pci_hotplug_util.c \
 		$(TOPDIR)/drivers/block/ll_rw_blk.c \
 		$(TOPDIR)/drivers/sound/sound_core.c \
 		$(TOPDIR)/drivers/sound/sound_firmware.c \
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/DocBook/kernel-api.tmpl linux/Documentation/DocBook/kernel-api.tmpl
--- linux.orig/Documentation/DocBook/kernel-api.tmpl	2001-10-05 19:06:51.000000000 +0000
+++ linux/Documentation/DocBook/kernel-api.tmpl	2002-08-01 06:42:27.000000000 +0000
@@ -162,6 +162,10 @@
      <sect1><title>PCI Support Library</title>
 !Edrivers/pci/pci.c
      </sect1>
+     <sect1><title>PCI Hotplug Support Library</title>
+!Edrivers/hotplug/pci_hotplug_core.c
+!Edrivers/hotplug/pci_hotplug_util.c
+     </sect1>
      <sect1><title>MCA Architecture</title>
 	<sect2><title>MCA Device Functions</title>
 !Earch/i386/kernel/mca.c
@@ -268,7 +272,7 @@
 !Edrivers/video/fbcmap.c
      </sect1>
      <sect1><title>Frame Buffer Generic Functions</title>
-!Idrivers/video/fbgen.c
+!Edrivers/video/fbgen.c
      </sect1>
      <sect1><title>Frame Buffer Video Mode Database</title>
 !Idrivers/video/modedb.c
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/DocBook/kernel-hacking.tmpl linux/Documentation/DocBook/kernel-hacking.tmpl
--- linux.orig/Documentation/DocBook/kernel-hacking.tmpl	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/DocBook/kernel-hacking.tmpl	2002-08-01 06:42:45.000000000 +0000
@@ -1026,7 +1026,7 @@
     Similar to <function>EXPORT_SYMBOL()</function> except that the
     symbols exported by <function>EXPORT_SYMBOL_GPL()</function> can
     only be seen by modules with a
-    <function>MODULE_LICENCE()</function> that specifies a GPL
+    <function>MODULE_LICENSE()</function> that specifies a GPL
     compatible license.
    </para>
   </sect1>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/DocBook/kernel-locking.tmpl linux/Documentation/DocBook/kernel-locking.tmpl
--- linux.orig/Documentation/DocBook/kernel-locking.tmpl	2001-05-20 00:43:05.000000000 +0000
+++ linux/Documentation/DocBook/kernel-locking.tmpl	2002-08-01 06:42:40.000000000 +0000
@@ -788,8 +788,18 @@
     </para>
 
     <para>
-      Note that the atomic operations are defined to act as both
-      read and write barriers on all platforms.
+      Note that the atomic operations do in general not act as memory
+      barriers. Instead you can insert a memory barrier before or
+      after <function>atomic_inc()</function> or
+      <function>atomic_dec()</function> by inserting
+      <function>smp_mb__before_atomic_inc()</function>,
+      <function>smp_mb__after_atomic_inc()</function>,
+      <function>smp_mb__before_atomic_dec()</function> or
+      <function>smp_mb__after_atomic_dec()</function>
+      respectively. The advantage of using those macros instead of
+      <function>smp_mb()</function> is, that they are cheaper on some
+      platforms.    
+      <!-- Sebastian Wilhelmi <seppi@seppi.de> 2002-03-04 -->
     </para>
    </sect1>
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/DocBook/sis900.tmpl linux/Documentation/DocBook/sis900.tmpl
--- linux.orig/Documentation/DocBook/sis900.tmpl	2000-12-29 22:07:19.000000000 +0000
+++ linux/Documentation/DocBook/sis900.tmpl	2002-08-01 06:42:28.000000000 +0000
@@ -323,8 +323,8 @@
 The 1.06 revision can be found in kernel version later than 2.3.15 and pre-2.2.14, 
 and 1.07 revision can be found in kernel version 2.4.0.
 If you have no prior experience in networking under Linux, please read
-<ULink URL="http://www.linuxdoc.org/">Ethernet HOWTO</ULink> and
-<ULink URL="http://www.linuxdoc.org/">Networking HOWTO</ULink> available from
+<ULink URL="http://www.tldp.org/">Ethernet HOWTO</ULink> and
+<ULink URL="http://www.tldp.org/">Networking HOWTO</ULink> available from
 Linux Documentation Project (LDP).
 </Para>
 
@@ -435,7 +435,7 @@
 Typical values are "10baseT"(twisted-pair 10Mbps Ethernet) or "100baseT"
 (twisted-pair 100Mbps Ethernet). For more information on how to configure 
 network interface, please refer to  
-<ULink URL="http://www.linuxdoc.org/">Networking HOWTO</ULink>.
+<ULink URL="http://www.tldp.org/">Networking HOWTO</ULink>.
 </Para>
 
 <Para>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/IRQ-affinity.txt linux/Documentation/IRQ-affinity.txt
--- linux.orig/Documentation/IRQ-affinity.txt	2000-02-25 06:41:16.000000000 +0000
+++ linux/Documentation/IRQ-affinity.txt	2002-08-01 06:42:27.000000000 +0000
@@ -8,7 +8,7 @@
 affinity then the value will not change from the default 0xffffffff.
 
 Here is an example of restricting IRQ44 (eth1) to CPU0-3 then restricting
-the IRQ to CPU4-8 (this is an 8-CPU SMP box):
+the IRQ to CPU4-7 (this is an 8-CPU SMP box):
 
 [root@moon 44]# cat smp_affinity
 ffffffff
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/SubmittingDrivers linux/Documentation/SubmittingDrivers
--- linux.orig/Documentation/SubmittingDrivers	2001-08-27 15:59:16.000000000 +0000
+++ linux/Documentation/SubmittingDrivers	2002-08-01 06:42:33.000000000 +0000
@@ -3,7 +3,7 @@
 
 This document is intended to explain how to submit device drivers to the
 Linux 2.2 and 2.4 kernel trees. Note that if you are interested in video
-card drivers you should probably talk to XFree86 (http://wwww.xfree86.org) 
+card drivers you should probably talk to XFree86 (http://www.xfree86.org) 
 instead.
 
 Also read the Documentation/SubmittingPatches document.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/cachetlb.txt linux/Documentation/cachetlb.txt
--- linux.orig/Documentation/cachetlb.txt	2001-12-21 17:41:53.000000000 +0000
+++ linux/Documentation/cachetlb.txt	2002-08-01 06:42:40.000000000 +0000
@@ -339,7 +339,18 @@
 	If the icache does not snoop stores then this routine will need
 	to flush it.
 
+  void flush_icache_user_range(struct vm_area_struct *vma,
+			struct page *page, unsigned long addr, int len)
+	This is called when the kernel stores into addresses that are
+	part of the address space of a user process (which may be some
+	other process than the current process).  The addr argument
+	gives the virtual address in that process's address space,
+	page is the page which is being modified, and len indicates
+	how many bytes have been modified.  The modified region must
+	not cross a page boundary.  Currently this is only called from
+	kernel/ptrace.c.
+
   void flush_icache_page(struct vm_area_struct *vma, struct page *page)
-	All the functionality of flush_icache_page can be implemented in
-	flush_dcache_page and update_mmu_cache. In 2.5 the hope is to
-	remove this interface completely.
+	This is called when a page-cache page is about to be mapped
+	into a user process' address space.  It offers an opportunity
+	for a port to ensure d-cache/i-cache coherency if necessary.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/cciss.txt linux/Documentation/cciss.txt
--- linux.orig/Documentation/cciss.txt	2001-10-11 16:04:57.000000000 +0000
+++ linux/Documentation/cciss.txt	2002-08-01 06:42:32.000000000 +0000
@@ -100,7 +100,7 @@
 can be informed of changes to the virtual SCSI bus which the driver 
 presents to it in the usual way. For example: 
 
-	echo add-single-device 3 2 1 0 > /proc/scsi/scsi
+	echo scsi add-single-device 3 2 1 0 > /proc/scsi/scsi
  
 to add a device on controller 3, bus 2, target 1, lun 0.   Note that
 the driver makes an effort to preserve the devices positions
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/fb/README-sstfb.txt linux/Documentation/fb/README-sstfb.txt
--- linux.orig/Documentation/fb/README-sstfb.txt	2001-09-07 16:28:38.000000000 +0000
+++ linux/Documentation/fb/README-sstfb.txt	2002-08-01 06:42:35.000000000 +0000
@@ -9,12 +9,12 @@
 	combinations and it seems that it works.
 	  The main page is located at <http://sstfb.sourceforge.net>, and if
 	you want the latest version, check out the CVS, as the driver is a work
-	in progress, i feel incomfortable with releasing tarballs of something
+	in progress, I feel incomfortable with releasing tarballs of something
 	not completely working...Don't worry, it's still more than useable
 	(I eat my own dog food)
 
 	  Please read the Bug section, and report any success or failure to me
-	(Ghozlane Toumi <gtoumi@messel.emse.fr>).
+	(Ghozlane Toumi <gtoumi@laposte.net>).
 	  BTW, If you have only one monitor , and you don't feel like playing
 	with the vga passthrou cable, I can only suggest borrowing a screen
 	somewhere... 
@@ -22,8 +22,9 @@
 
 Installation 
 
-	  This driver (should) work on ix86, with any 2.2.x kernel (tested
+	  This driver (should) work on ix86, with "late" 2.2.x kernel (tested
 	with x = 19) and "recent" 2.4.x kernel, as a module or compiled in.
+	  It has been included in mainstream kernel since the infamous 2.4.10.
 	  You can apply the patches found in sstfb/kernel/*-2.{2|4}.x.patch,
 	and copy sstfb.c to linux/drivers/video/, or apply a single patch, 
 	sstfb/patch-2.{2|4}.x-sstfb-yymmdd to your linux source tree.
@@ -41,7 +42,7 @@
 	  module, the 3dfx takes control of the output, so you'll have to
 	  plug the monitor to the "normal" video board in order to issue
 	  the commands, or you can blindly use sst_dbg_vgapass
-          in the tools directory (See Tools). The latest option is pass the
+          in the tools directory (See Tools). The latest solution is pass the
 	  parameter vgapass=1 when insmodding the driver. (See Kernel/Modules
 	  Options)
 
@@ -77,36 +78,39 @@
 	in kernel :  video=sstfb:option1,option2:value2,option3 ...
 	
 	sstfb supports the folowing options :
-	module		kernel		description
 
-	vgapass=1	vgapass		enable or disable VGA passthrou cable
-	vgapass=0	vganopass	when enabled, the monitor will
-					get the signal from the VGA board
-					and not from the voodoo. default nopass
-
-	mem=x		mem:x		force frame buffer memory in MiB
-					allowed values: 1, 2, 4. default detect
-
-	inverse=1	inverse		suposed to enable inverse console.
-					doesn't work ...
-
-	clipping=1	clipping	enable or disable clipping . with
-	clipping=0	noclipping	clipping enabled, all offscreen reads
-					and writes are disgarded. default:
-					enable clipping.
-
-	gfxclk=x	gfxclk:x	force graphic clock frequency (in MHz)
-					becarefull with this option .
-					default is 50Mhz for voodoo1, 75MHz
-					for voodoo2. Be carefull, this one is
-					dangerous. default=auto
-
-	slowpci=0	slowpci		enable or disable fast PCI read/writes
-	slowpci=1	fastpci		default : fastpci
-
-	dev=x		dev:x		attach the driver to device number x
-					0 is the first compatible board (in 
-					lspci order)
+Module		Kernel		Description
+
+vgapass=0	vganopass	Enable or disable VGA passthrou cable.
+vgapass=1	vgapass		When enabled, the monitor will get the signal
+				from the VGA board and not from the voodoo.
+				Default: nopass
+
+mem=x		mem:x		Force frame buffer memory in MiB
+				allowed values: 0, 1, 2, 4.
+				Default: 0 (= autodetect)
+
+inverse=1	inverse		Supposed to enable inverse console.
+				doesn't work yet...
+
+clipping=1	clipping	Enable or disable clipping.
+clipping=0	noclipping	With clipping enabled, all offscreen
+				reads and writes are disgarded.
+				Default: enable clipping.
+
+gfxclk=x	gfxclk:x	Force graphic clock frequency (in MHz).
+				Be carefull with this option, it may be
+				DANGEROUS.
+				Default: auto 
+					50Mhz for Voodoo 1,
+					75MHz for Voodoo 2. 
+
+slowpci=1	fastpci		Enable or disable fast PCI read/writes.
+slowpci=1	slowpci		Default : fastpci
+
+dev=x		dev:x		Attach the driver to device number x.
+				0 is the first compatible board (in 
+				lspci order)
 
 Tools
 
@@ -126,8 +130,8 @@
 
 	- DO NOT use glide while the sstfb module is in, you'll most likely
 	hang your computer.
-	- if you see some artefacts (pixels not cleaning and stuff like that), 
-	try turning off clipping (clipping=0)
+	- If you see some artefacts (pixels not cleaning and stuff like that), 
+	try turning off clipping (clipping=0), and/or using slowpci
 	- the driver don't detect the 4Mb frame buffer voodoos, it seems that
 	the 2 last Mbs wrap around. looking into that .
 	- The driver is 16 bpp only, 24/32 won't work.
@@ -137,8 +141,8 @@
 	patterns at the border of your windows (the pixels loose the lowest
 	byte -> basicaly the blue component nd some of the green) . I'm unable
 	to reproduce this with XFree86-3.3, but one of the testers has this
-	problem with XFree86-4. I don't know yet if this is the drivers fault
-	or X's (most likely the driver, of course).
+	problem with XFree86-4. apparently recent Xfree86-4.x solve this
+	problem.
 	- I didn't really test changing the palette, so you may find some weird
 	things when playing with that.
 	- Sometimes the driver will not recognise the DAC , and the
@@ -147,6 +151,9 @@
 	contact me .
 	- the 24/32 is not likely to work anytime soon , knowing that the
 	hardware does ... unusual thigs in 24/32 bpp
+	- When used with anther video board, current limitations of linux
+	console subsystem can cause some troubles, specificaly, you should
+	disable software scrollback , as it can oops badly ...
 
 Todo
 
@@ -154,14 +161,14 @@
 	- Buy more coffee.
 	- test/port to other arch.
 	- try to add panning using tweeks with front and back buffer .
-	- try to implement accel en voodoo2 , this board can actualy do a 
+	- try to implement accel on voodoo2 , this board can actualy do a 
 	  lot in 2D even if it was sold as a 3D only board ...
 
 ghoz.
 
 -- 
-Ghozlane Toumi <gtoumi@messel.emse.fr>
+Ghozlane Toumi <gtoumi@laposte.net>
 
 
-$Date: 2001/08/29 00:21:11 $
+$Date: 2002/05/09 20:11:45 $
 http://sstfb.sourceforge.net/README
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/fb/matroxfb.txt linux/Documentation/fb/matroxfb.txt
--- linux.orig/Documentation/fb/matroxfb.txt	2001-09-30 19:26:08.000000000 +0000
+++ linux/Documentation/fb/matroxfb.txt	2002-08-01 06:42:36.000000000 +0000
@@ -10,7 +10,7 @@
 
  * It provides a nice large console (128 cols + 48 lines with 1024x768)
    without using tiny, unreadable fonts.
- * You can run XF68_FBDev on top of /dev/fb0
+ * You can run XF{68,86}_FBDev or XFree86 fbdev driver on top of /dev/fb0
  * Most important: boot logo :-)
 
 Disadvantages:
@@ -27,9 +27,6 @@
 
 If you want, for example, enable a resolution of 1280x1024x24bpp you should
 pass to the kernel this command line: "video=matrox:vesa:0x1BB".
-Note that the same line, if 'appended' as a lilo parameter in lilo.conf will
-read "video=matrox:vesa:443" because lilo pass integer parameters as decimal
-numbers to the kernel.
 
 You should compile in both vgacon (to boot if you remove you Matrox from
 box) and matroxfb (for graphics mode). You should not compile-in vesafb
@@ -82,13 +79,16 @@
 X11
 ===
 
-XF68_FBDev should work just fine, but it is non-accelerated. On non-intel
+XF{68,86}_FBDev should work just fine, but it is non-accelerated. On non-intel
 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
 works fine.
 
 Running another (accelerated) X-Server like XF86_SVGA works too. But (at least)
 XFree servers have big troubles in multihead configurations (even on first
-head, not even talking about second).
+head, not even talking about second). Running XFree86 4.x accelerated mga 
+driver is possible, but you must not enable DRI - if you do, resolution and
+color depth of your X desktop must match resolution and color depths of your
+virtual consoles, otherwise X will corrupt accelerator settings.
 
 
 SVGALib
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/fb/tridentfb.txt linux/Documentation/fb/tridentfb.txt
--- linux.orig/Documentation/fb/tridentfb.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/fb/tridentfb.txt	2002-08-01 06:42:32.000000000 +0000
@@ -42,8 +42,14 @@
 bpp  - bits per pixel (8,16 or 32)
 mode - a mode name like 800x600 (as described in Documentation/fb/modedb.txt)
 
+Example:
+video=trident:memsize=2048,800x600
+
 Using insane values for the above parameters will probably result in driver
 misbehaviour so take care(for instance memsize=12345678 or memdiff=23784 or
 nativex=93)
 
-Contact: jani@astechnix.ro
+If you have trouble with the driver you could check http://sf.net/projects/tridentfb
+to see if there's a newer version available.
+
+Contact: jani@iv.ro
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/filesystems/Locking linux/Documentation/filesystems/Locking
--- linux.orig/Documentation/filesystems/Locking	2001-12-21 17:41:53.000000000 +0000
+++ linux/Documentation/filesystems/Locking	2002-08-01 06:42:39.000000000 +0000
@@ -156,7 +156,7 @@
 block_flushpage() instead.
 	->releasepage() is called when the kernel is about to try to drop the
 buffers from the page in preparation for freeing it.  It returns zero to
-indicate that the buffers are (or may be) freeable.  If ->flushpage is zero,
+indicate that the buffers are (or may be) freeable.  If ->releasepage is zero,
 the kernel assumes that the fs has no private interest in the buffers.
 
 	Note: currently almost all instances of address_space methods are
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/filesystems/cramfs.txt linux/Documentation/filesystems/cramfs.txt
--- linux.orig/Documentation/filesystems/cramfs.txt	2001-07-19 23:14:53.000000000 +0000
+++ linux/Documentation/filesystems/cramfs.txt	2002-08-01 06:42:47.000000000 +0000
@@ -10,7 +10,7 @@
 
 You can't write to a cramfs filesystem (making it compressible and
 compact also makes it _very_ hard to update on-the-fly), so you have to
-create the disk image with the "mkcramfs" utility in scripts/cramfs.
+create the disk image with the "mkcramfs" utility.
 
 
 Usage Notes
@@ -19,9 +19,7 @@
 File sizes are limited to less than 16MB.
 
 Maximum filesystem size is a little over 256MB.  (The last file on the
-filesystem is allowed to extend past 256MB.)  (Comments in mkcramfs.c
-suggest that ROM sizes may be limited to 64MB, though that's not a
-limitation in cramfs code.)
+filesystem is allowed to extend past 256MB.)
 
 Only the low 8 bits of gid are stored.  The current version of
 mkcramfs simply truncates to 8 bits, which is a potential security
@@ -48,18 +46,28 @@
 
 
 For /usr/share/magic
-------------------
+--------------------
 
-0	long	0x28cd3d45	Linux cramfs
->4	long	x		size %d
->8	long	x		flags 0x%x
->12	long	x		future 0x%x
+0	ulelong	0x28cd3d45	Linux cramfs offset 0
+>4	ulelong	x		size %d
+>8	ulelong	x		flags 0x%x
+>12	ulelong	x		future 0x%x
 >16	string	>\0		signature "%.16s"
->32	long	x		fsid.crc 0x%x
->36	long	x		fsid.edition %d
->40	long	x		fsid.blocks %d
->44	long	x		fsid.files %d
+>32	ulelong	x		fsid.crc 0x%x
+>36	ulelong	x		fsid.edition %d
+>40	ulelong	x		fsid.blocks %d
+>44	ulelong	x		fsid.files %d
 >48	string	>\0		name "%.16s"
+512	ulelong	0x28cd3d45	Linux cramfs offset 512
+>516	ulelong	x		size %d
+>520	ulelong	x		flags 0x%x
+>524	ulelong	x		future 0x%x
+>528	string	>\0		signature "%.16s"
+>544	ulelong	x		fsid.crc 0x%x
+>548	ulelong	x		fsid.edition %d
+>552	ulelong	x		fsid.blocks %d
+>556	ulelong	x		fsid.files %d
+>560	string	>\0		name "%.16s"
 
 
 Hacker Notes
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/filesystems/devfs/ChangeLog linux/Documentation/filesystems/devfs/ChangeLog
--- linux.orig/Documentation/filesystems/devfs/ChangeLog	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/filesystems/devfs/ChangeLog	2002-08-01 06:42:33.000000000 +0000
@@ -1880,3 +1880,59 @@
 - Updated README from master HTML file
 
 - Fixed kdev_none macro in include/linux/kdev_t.h
+===============================================================================
+Changes for patch v199.9
+
+- Added KERN_* to remaining messages
+
+- Cleaned up declaration of <stat_read>
+
+- Updated README from master HTML file
+===============================================================================
+Changes for patch v199.10
+
+- Changed <devfs_rmdir> to allow later additions if not yet empty
+
+- Added calls to <devfs_register_partitions> in drivers/block/blkpc.c
+  <add_partition> and <del_partition>
+
+- Updated README from master HTML file
+
+- Fixed bug in <devfs_alloc_unique_number>: was clearing beyond
+  bitfield
+
+- Fixed bitfield data type for <devfs_*alloc_devnum>
+
+- Made major bitfield type and initialiser 64 bit safe
+===============================================================================
+Changes for patch v199.11
+
+- Ported to kernel 2.4.19-pre5
+
+- Updated README from master HTML file
+===============================================================================
+Changes for patch v199.12
+
+- Updated README from master HTML file
+
+- Changed fs/devfs/util.c to kdev_t compatibility macros
+===============================================================================
+Changes for patch v199.13
+
+- Updated fs/devfs/util.c to fix shift warning on 64 bit machines
+  Thanks to Anton Blanchard <anton@samba.org>
+
+- Updated README from master HTML file
+
+- Do not put miscellaneous character devices in /dev/misc if they
+  specify their own directory (i.e. contain a '/' character)
+===============================================================================
+Changes for patch v199.14
+
+- Copied macro for error messages from fs/devfs/base.c to
+  fs/devfs/util.c and made use of this macro
+
+- Added BKL to <devfs_open> because drivers still need it
+
+- Protected <scan_dir_for_removable> and <get_removable_partition>
+  from changing directory contents
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/filesystems/devfs/README linux/Documentation/filesystems/devfs/README
--- linux.orig/Documentation/filesystems/devfs/README	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/filesystems/devfs/README	2002-08-01 06:42:41.000000000 +0000
@@ -3,7 +3,7 @@
 
 Linux Devfs (Device File System) FAQ
 Richard Gooch
-20-JAN-2002
+7-APR-2002
 
 
 Document languages:
@@ -803,12 +803,19 @@
 
 add the following lines to your /etc/devfsd.conf file:
 
-REGISTER	^pt[sy]/.*	IGNORE
-CHANGE		^pt[sy]/.*	IGNORE
+REGISTER	^pt[sy]		IGNORE
+CREATE		^pt[sy]		IGNORE
+CHANGE		^pt[sy]		IGNORE
+DELETE		^pt[sy]		IGNORE
 REGISTER	.*		COPY	/dev-state/$devname $devpath
-CHANGE		.*		COPY	$devpath /dev-state/$devname
 CREATE		.*		COPY	$devpath /dev-state/$devname
+CHANGE		.*		COPY	$devpath /dev-state/$devname
+DELETE		.*		CFUNCTION GLOBAL unlink /dev-state/$devname
+RESTORE		/dev-state
 
+Note that the sample devfsd.conf file contains these lines,
+as well as other sample configurations you may find useful. See the
+devfsd distribution
 
 
 reboot.
@@ -872,7 +879,8 @@
 (for example, by starting with /etc/fstab), and then limiting the
 compatibility entries that devfsd creates.
 
-MAKE SURE YOU INSTALL DEVFSD BEFORE YOU BOOT A DEVFS-ENABLED KERNEL!
+IF YOU CONFIGURE TO MOUNT DEVFS AT BOOT, MAKE SURE YOU INSTALL DEVFSD
+BEFORE YOU BOOT A DEVFS-ENABLED KERNEL!
 
 Now that devfs has gone into the 2.3.46 kernel, I'm getting a lot of
 reports back. Many of these are because people are trying to run
@@ -1565,6 +1573,38 @@
 the existence of the entry should be relied upon.
 
 
+When I start devfsd, I see the error:
+Error opening file: ".devfsd"   No such file or directory?
+
+This means that devfs is not mounted. Make sure you have devfs mounted.
+
+
+How do I mount devfs?
+
+First make sure you have devfs compiled into your kernel (see
+above). Then you will either need to:
+
+set CONFIG_DEVFS_MOUNT=y in your kernel config
+pass devfs=mount to your boot loader
+mount devfs manually in your boot scripts with:
+mount -t none devfs /dev
+
+
+
+Mount by volume LABEL=<label> doesn't work with
+devfs
+
+Most probably you are not mounting devfs onto /dev. What
+happens is that if your kernel config has CONFIG_DEVFS_FS=y
+then the contents of /proc/partitions will have the devfs
+names (such as scsi/host0/bus0/target0/lun0/part1). The
+contents of /proc/partitions are used by mount(8) when
+mounting by volume label. If devfs is not mounted on /dev,
+then mount(8) will fail to find devices. The solution is to
+make sure that devfs is mounted on /dev. See above for how to
+do that.
+
+
 
 
 
@@ -1760,6 +1800,15 @@
 
 
 
+make sure you have enabled debugging output when configuring your
+kernel. You will need to set (at least) the following config options:
+
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+
+
+
 please make sure you have the latest devfs patches applied. The
 latest kernel version might not have the latest devfs patches applied
 yet (Linus is very busy)
@@ -1768,7 +1817,10 @@
 save a copy of your complete kernel logs (preferably by
 using the dmesg programme) for later inclusion in your bug
 report. You may need to use the -s switch to increase the
-internal buffer size so you can capture all the boot messages
+internal buffer size so you can capture all the boot messages.
+Don't edit or trim the dmesg output
+
+
 
 
 try booting with devfs=dall passed to the kernel boot
@@ -1925,11 +1977,7 @@
 
 A Korean translation by viatoris@nownuri.net is available at
 
-http://home.nownuri.net/~viatoris/devfs/devfs.html
-
-A newer version is under construcation at
-
-http://viatoris.new21.org/devfs/devfs.html
+http://your.destiny.pe.kr/devfs/devfs.html
 
 
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/i810_rng.txt linux/Documentation/i810_rng.txt
--- linux.orig/Documentation/i810_rng.txt	2001-04-19 16:34:05.000000000 +0000
+++ linux/Documentation/i810_rng.txt	2002-08-01 06:42:46.000000000 +0000
@@ -70,6 +70,14 @@
 
 Change history:
 
+	Version 0.9.8:
+	* Support other i8xx chipsets by adding 82801E detection
+	* 82801DB detection is the same as for 82801CA.
+
+	Version 0.9.7:
+	* Support other i8xx chipsets too (by adding 82801BA(M) and
+	  82801CA(M) detection)
+
 	Version 0.9.6:
 	* Internal driver cleanups, prep for 1.0.0 release.
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/ia64/IRQ-redir.txt linux/Documentation/ia64/IRQ-redir.txt
--- linux.orig/Documentation/ia64/IRQ-redir.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/ia64/IRQ-redir.txt	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,69 @@
+IRQ affinity on IA64 platforms
+------------------------------
+                           07.01.2002, Erich Focht <efocht@ess.nec.de>
+
+
+By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
+controlled. The behavior on IA64 platforms is slightly different from
+that described in Documentation/IRQ-affinity.txt for i386 systems.
+
+Because of the usage of SAPIC mode and physical destination mode the
+IRQ target is one particular CPU and cannot be a mask of several
+CPUs. Only the first non-zero bit is taken into account.
+
+
+Usage examples:
+
+The target CPU has to be specified as a hexadecimal CPU mask. The
+first non-zero bit is the selected CPU. This format has been kept for
+compatibility reasons with i386.
+
+Set the delivery mode of interrupt 41 to fixed and route the
+interrupts to CPU #3 (logical CPU number) (2^3=0x08):
+     echo "8" >/proc/irq/41/smp_affinity
+
+Set the default route for IRQ number 41 to CPU 6 in lowest priority
+delivery mode (redirectable):
+     echo "r 40" >/proc/irq/41/smp_affinity
+
+The output of the command
+     cat /proc/irq/IRQ#/smp_affinity
+gives the target CPU mask for the specified interrupt vector. If the CPU
+mask is preceeded by the character "r", the interrupt is redirectable
+(i.e. lowest priority mode routing is used), otherwise its route is
+fixed.
+
+
+
+Initialization and default behavior:
+
+If the platform features IRQ redirection (info provided by SAL) all
+IO-SAPIC interrupts are initialized with CPU#0 as their default target
+and the routing is the so called "lowest priority mode" (actually
+fixed SAPIC mode with hint). The XTP chipset registers are used as hints
+for the IRQ routing. Currently in Linux XTP registers can have three
+values:
+	- minimal for an idle task,
+	- normal if any other task runs,
+	- maximal if the CPU is going to be switched off.
+The IRQ is routed to the CPU with lowest XTP register value, the
+search begins at the default CPU. Therefore most of the interrupts
+will be handled by CPU #0.
+
+If the platform doesn't feature interrupt redirection IOSAPIC fixed
+routing is used. The target CPUs are distributed in a round robin
+manner. IRQs will be routed only to the selected target CPUs. Check
+with
+        cat /proc/interrupts
+
+
+
+Comments:
+
+On large (multi-node) systems it is recommended to route the IRQs to
+the node to which the corresponding device is connected.
+For systems like the NEC AzusA we get IRQ node-affinity for free. This
+is because usually the chipsets on each node redirect the interrupts
+only to their own CPUs (as they cannot see the XTP registers on the
+other nodes).
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/isdn/README.HiSax linux/Documentation/isdn/README.HiSax
--- linux.orig/Documentation/isdn/README.HiSax	2001-08-13 23:35:28.000000000 +0000
+++ linux/Documentation/isdn/README.HiSax	2002-08-01 06:42:33.000000000 +0000
@@ -52,6 +52,7 @@
 Sedlbauer Speed Star/Speed Star2 (PCMCIA)
 Sedlbauer ISDN-Controller PC/104
 USR Sportster internal TA (compatible Stollmann tina-pp V3)
+USR internal TA PCI
 ith Kommunikationstechnik GmbH MIC 16 ISA card
 Traverse Technologie NETjet PCI S0 card and NETspider U card
 Ovislink ISDN sc100-p card (NETjet driver)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/kernel-doc-nano-HOWTO.txt linux/Documentation/kernel-doc-nano-HOWTO.txt
--- linux.orig/Documentation/kernel-doc-nano-HOWTO.txt	2001-09-08 01:15:17.000000000 +0000
+++ linux/Documentation/kernel-doc-nano-HOWTO.txt	2002-08-01 06:42:43.000000000 +0000
@@ -73,10 +73,10 @@
 mkdir $ARGV[0],0777;
 $state = 0;
 while (<STDIN>) {
-    if (/^\.TH \"[^\"]*\" 4 \"([^\"]*)\"/) {
+    if (/^\.TH \"[^\"]*\" (\d) \"([^\"]*)\"/) {
 	if ($state == 1) { close OUT }
 	$state = 1;
-	$fn = "$ARGV[0]/$1.4";
+	$fn = "$ARGV[0]/$2.$1";
 	print STDERR "Creating $fn\n";
 	open OUT, ">$fn" or die "can't open $fn: $!\n";
 	print OUT $_;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/kernel-docs.txt linux/Documentation/kernel-docs.txt
--- linux.orig/Documentation/kernel-docs.txt	2001-06-28 21:45:07.000000000 +0000
+++ linux/Documentation/kernel-docs.txt	2002-08-01 06:42:46.000000000 +0000
@@ -41,7 +41,7 @@
        
      * Title: "The Linux Kernel"
        Author: David A. Rusling.
-       URL: http://www.linuxdoc.org/LDP/tlk/tlk.html
+       URL: http://www.tldp.org/LDP/tlk/tlk.html
        Keywords: everything!, book.
        Description: On line, 200 pages book describing most aspects of
        the Linux Kernel. Probably, the first reference for beginners.
@@ -57,7 +57,7 @@
        
      * Title: "The Linux Kernel Hackers' Guide"
        Author: Michael K.Johnson and others.
-       URL: http://www.linuxdoc.org/LDP/khg/HyperNews/get/khg.html
+       URL: http://www.tldp.org/LDP/khg/HyperNews/get/khg.html
        Keywords: everything!
        Description: No more Postscript book-like version. Only HTML now.
        Many people have contributed. The interface is similar to web
@@ -277,7 +277,7 @@
        
      * Title: "Linux Kernel Module Programming Guide"
        Author: Ori Pomerantz.
-       URL: http://www.linuxdoc.org/LDP/lkmpg/mpg.html
+       URL: http://www.tldp.org/LDP/lkmpg/mpg.html
        Keywords: modules, GPL book, /proc, ioctls, system calls,
        interrupt handlers .
        Description: Very nice 92 pages GPL book on the topic of modules
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/kernel-parameters.txt linux/Documentation/kernel-parameters.txt
--- linux.orig/Documentation/kernel-parameters.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/kernel-parameters.txt	2002-08-01 06:42:45.000000000 +0000
@@ -68,6 +68,8 @@
 	53c7xx=		[HW,SCSI] Amiga SCSI controllers.
 
 	acpi=		[HW,ACPI] Advanced Configuration and Power Interface 
+
+	acpismp=force	[IA-32] Early setup parse and use ACPI SMP table.
  
 	ad1816=		[HW,SOUND]
 
@@ -379,6 +381,8 @@
  
 	no-hlt		[BUGS=ix86]
 
+	noht		[SMP,IA-32] Disables P4 Xeon(tm) HyperThreading.
+
 	noisapnp	[ISAPNP] Disables ISA PnP code.
 
 	noinitrd	[RAM] Tells the kernel not to load any configured
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/nbd.txt linux/Documentation/nbd.txt
--- linux.orig/Documentation/nbd.txt	1999-08-05 21:34:01.000000000 +0000
+++ linux/Documentation/nbd.txt	2002-08-01 06:42:47.000000000 +0000
@@ -54,4 +54,4 @@
   ...                 in case of read operation with no error,
                       this is immediately followed len bytes of data
 
-   For more information, look at http://atrey.karlin.mff.cuni.cz/~pavel.
+   For more information, look at http://nbd.sf.net/.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/3c359.txt linux/Documentation/networking/3c359.txt
--- linux.orig/Documentation/networking/3c359.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/3c359.txt	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,58 @@
+
+3COM PCI TOKEN LINK VELOCITY XL TOKEN RING CARDS README
+
+Release 0.9.0 - Release   
+	Jul 17th 2000 Mike Phillips 
+
+	1.2.0 - Final
+	Feb 17th 2002 Mike Phillips 
+	Updated for submission to the 2.4.x kernel.
+
+Thanks:
+	Terry Murphy from 3Com for tech docs and support,
+	Adam D. Ligas for testing the driver.
+ 
+Note:
+	This driver will NOT work with the 3C339 Token Ring cards, you need
+to use the tms380 driver instead.
+
+Options:
+
+The driver accepts three options: ringspeed, pkt_buf_sz and message_level.
+
+These options can be specified differently for each card found. 
+
+ringspeed:  Has one of three settings 0 (default), 4 or 16.  0 will 
+make the card autosense the ringspeed and join at the appropriate speed, 
+this will be the default option for most people.  4 or 16 allow you to 
+explicitly force the card to operate at a certain speed.  The card will fail 
+if you try to insert it at the wrong speed. (Although some hubs will allow 
+this so be *very* careful).  The main purpose for explicitly setting the ring
+speed is for when the card is first on the ring.  In autosense mode, if the card
+cannot detect any active monitors on the ring it will open at the same speed as
+its last opening. This can be hazardous if this speed does not match the speed
+you want the ring to operate at.  
+
+pkt_buf_sz:  This is this initial receive buffer allocation size.  This will
+default to 4096 if no value is entered. You may increase performance of the 
+driver by setting this to a value larger than the network packet size, although
+the driver now re-sizes buffers based on MTU settings as well. 
+
+message_level: Controls level of messages created by the driver. Defaults to 0:
+which only displays start-up and critical messages.  Presently any non-zero 
+value will display all soft messages as well.  NB This does not turn 
+debuging messages on, that must be done by modified the source code.
+
+Variable MTU size:
+
+The driver can handle a MTU size upto either 4500 or 18000 depending upon 
+ring speed.  The driver also changes the size of the receive buffers as part
+of the mtu re-sizing, so if you set mtu = 18000, you will need to be able
+to allocate 16 * (sk_buff with 18000 buffer size) call it 18500 bytes per ring 
+position = 296,000 bytes of memory space, plus of course anything 
+necessary for the tx sk_buff's.  Remember this is per card, so if you are
+building routers, gateway's etc, you could start to use a lot of memory
+real fast.
+
+2/17/02 Mike Phillips
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/3c509.txt linux/Documentation/networking/3c509.txt
--- linux.orig/Documentation/networking/3c509.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/3c509.txt	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,210 @@
+Linux and the 3Com EtherLink III Series Ethercards (driver v1.18c and higher)
+----------------------------------------------------------------------------
+
+This file contains the instructions and caveats for v1.18c and higher versions
+of the 3c509 driver. You should not use the driver without reading this file.
+
+release 1.0
+28 February 2002
+Current maintainer (corrections to):
+  David Ruggiero <jdr@farfalle.com>
+
+----------------------------------------------------------------------------
+
+(0) Introduction
+
+The following are notes and information on using the 3Com EtherLink III series
+ethercards in Linux. These cards are commonly known by the most widely-used
+card's 3Com model number, 3c509. They are all 10mb/s ISA-bus cards and shouldn't
+be (but sometimes are) confused with the similarly-numbered PCI-bus "3c905"
+(aka "Vortex" or "Boomerang") series.  Kernel support for the 3c509 family is
+provided by the module 3c509.c, which has code to support all of the following
+models:
+
+  3c509 (original ISA card)
+  3c509B (later revision of the ISA card; supports full-duplex)
+  3c589 (PCMCIA)
+  3c589B (later revision of the 3c589; supports full-duplex)
+  3c529 (MCA)
+  3c579 (EISA)
+
+Large portions of this documentation were heavily borrowed from the guide
+written the original author of the 3c509 driver, Donald Becker. The master
+copy of that document, which contains notes on older versions of the driver,
+currently resides on Scyld web server: http://www.scyld.com/network/3c509.html.
+
+
+(1) Special Driver Features
+
+Overriding card settings
+
+The driver allows boot- or load-time overriding of the card's detected IOADDR,
+IRQ, and transceiver settings, although this capability shouldn't generally be
+needed except to enable full-duplex mode (see below). An example of the syntax
+for LILO parameters for doing this:
+
+    ether=10,0x310,3,0x3c509,eth0 
+
+This configures the first found 3c509 card for IRQ 10, base I/O 0x310, and
+transceiver type 3 (10base2). The flag "0x3c509" must be set to avoid conflicts
+with other card types when overriding the I/O address. When the driver is
+loaded as a module, only the IRQ and transceiver setting may be overridden.
+For example, setting two cards to 10base2/IRQ10 and AUI/IRQ11 is done by using
+the xcvr and irq module options:
+
+   options 3c509 xcvr=3,3 irq=10,11
+
+
+(2) Full-duplex mode
+
+The v1.18c driver added support for the 3c509B's full-duplex capabilities.
+In order to enable and successfully use full-duplex mode, three conditions
+must be met: 
+
+(a) You must have a Etherlink III card model whose hardware supports full-
+duplex operations. Currently, the only members of the 3c509 family that are
+positively known to support full-duplex are the 3c509B (ISA bus) and 3c589B
+(PCMCIA) cards. Cards without the "B" model designation do *not* support
+full-duplex mode; these include the original 3c509 (no "B"), the original
+3c589, the 3c529 (MCA bus), and the 3c579 (EISA bus).
+
+(b) You must be using your card's 10baseT transceiver (i.e., the RJ-45
+connector), not its AUI (thick-net) or 10base2 (thin-net/coax) interfaces.
+AUI and 10base2 network cabling is physically incapable of full-duplex
+operation.
+
+(c) Most importantly, your 3c509B must be connected to a link partner that is
+itself full-duplex capable. This is almost certainly one of two things: a full-
+duplex-capable  Ethernet switch (*not* a hub), or a full-duplex-capable NIC on
+another system that's connected directly to the 3c509B via a crossover cable.
+ 
+/////Extremely important caution concerning full-duplex mode/////
+Understand that the 3c509B's hardware's full-duplex support is much more
+limited than that provide by more modern network interface cards. Although
+at the physical layer of the network it fully supports full-duplex operation,
+the card was designed before the current Ethernet auto-negotiation (N-way)
+spec was written. This means that the 3c509B family ***cannot and will not
+auto-negotiate a full-duplex connection with its link partner under any
+circumstances, no matter how it is initialized***. If the full-duplex mode
+of the 3c509B is enabled, its link partner will very likely need to be
+independently _forced_ into full-duplex mode as well; otherwise various nasty
+failures will occur - at the very least, you'll see massive numbers of packet
+collisions. This is one of very rare circumstances where disabling auto-
+negotiation and forcing the duplex mode of a network interface card or switch
+would ever be necessary or desirable.
+
+
+(3) Available Transceiver Types
+
+For versions of the driver v1.18c and above, the available transceiver types are:
+ 
+0  transceiver type from EEPROM config (normally 10baseT); force half-duplex
+1  AUI (thick-net / DB15 connector)
+2  (undefined)
+3  10base2 (thin-net == coax / BNC connector)
+4  10baseT (RJ-45 connector); force half-duplex mode
+8  transceiver type and duplex mode taken from card's EEPROM config settings
+12 10baseT (RJ-45 connector); force full-duplex mode
+
+Prior to driver version 1.18c, only tranceiver codes 0-4 were supported. Note
+that the new transceiver codes 8 and 12 are the *only* ones that will enable
+full-duplex mode, no matter what the card's detected EEPROM settings might be.
+This insured that merely upgrading the driver from an earlier version would
+never automatically enable full-duplex mode in an existing installation;
+it must always be explicitly enabled via one of these code in order to be
+activated.
+  
+
+(4a) Interpretation of error messages and common problems
+
+Error Messages
+
+eth0: Infinite loop in interrupt, status 2011. 
+These are "mostly harmless" message indicating that the driver had too much
+work during that interrupt cycle. With a status of 0x2011 you are receiving
+packets faster than they can be removed from the card. This should be rare
+or impossible in normal operation. Possible causes of this error report are:
+ 
+   - a "green" mode enabled that slows the processor down when there is no
+     keyboard activitiy. 
+
+   - some other device or device driver hogging the bus or disabling interrupts.
+     Check /proc/interrupts for excessive interrupt counts. The timer tick
+     interrupt should always be incrementing faster than the others. 
+
+No received packets 
+If a 3c509, 3c562 or 3c589 can successfully transmit packets, but never
+receives packets (as reported by /proc/net/dev or 'ifconfig') you likely
+have an interrupt line problem. Check /proc/interrupts to verify that the
+card is actually generating interrupts. If the interrupt count is not
+increasing you likely have a physical conflict with two devices trying to
+use the same ISA IRQ line. The common conflict is with a sound card on IRQ10
+or IRQ5, and the easiest solution is to move the 3c509 to a different
+interrupt line. If the device is receiving packets but 'ping' doesn't work,
+you have a routing problem.
+
+Tx Carrier Errors Reported in /proc/net/dev 
+If an EtherLink III appears to transmit packets, but the "Tx carrier errors"
+field in /proc/net/dev increments as quickly as the Tx packet count, you
+likely have an unterminated network or the incorrect media tranceiver selected. 
+
+3c509B card is not detected on machines with an ISA PnP BIOS. 
+While the updated driver works with most PnP BIOS programs, it does not work
+with all. This can be fixed by disabling PnP support using the 3Com-supplied
+setup program. 
+
+3c509 card is not detected on overclocked machines 
+Increase the delay time in id_read_eeprom() from the current value, 500,
+to an absurdly high value, such as 5000. 
+
+
+(4b) Decoding Status and Error Messages
+
+The bits in the main status register are: 
+
+value 	description
+0x01 	Interrupt latch
+0x02 	Tx overrun, or Rx underrun
+0x04 	Tx complete
+0x08 	Tx FIFO room available
+0x10 	A complete Rx packet has arrived
+0x20 	A Rx packet has started to arrive
+0x40 	The driver has requested an interrupt
+0x80 	Statistics counter nearly full
+
+The bits in the transmit (Tx) status word are: 
+
+value 	description
+0x02 	Out-of-window collision.
+0x04 	Status stack overflow (normally impossible).
+0x08 	16 collisions.
+0x10 	Tx underrun (not enough PCI bus bandwidth).
+0x20 	Tx jabber.
+0x40 	Tx interrupt requested.
+0x80 	Status is valid (this should always be set).
+
+
+When a transmit error occurs the driver produces a status message such as 
+
+   eth0: Transmit error, Tx status register 82
+
+The two values typically seen here are:
+
+0x82 
+Out of window collision. This typically occurs when some other Ethernet
+host is incorrectly set to full duplex on a half duplex network. 
+
+0x88 
+16 collisions. This typically occurs when the network is exceptionally busy
+or when another host doesn't correctly back off after a collision. If this
+error is mixed with 0x82 errors it is the result of a host incorrectly set
+to full duplex (see above).
+
+Both of these errors are the result of network problems that should be
+corrected. They do not represent driver malfunction.
+
+
+(5) Revision history (this file)
+
+28Feb02 v1.0  DR   New; major portions based on Becker original 3c509 docs
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/8139too.txt linux/Documentation/networking/8139too.txt
--- linux.orig/Documentation/networking/8139too.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/networking/8139too.txt	2002-08-01 06:42:29.000000000 +0000
@@ -98,6 +98,7 @@
 Lantech FastNet TX
 Ovislink Fast Ethernet
 Planet ENW-9504 (V.4) 10/100
+SDT Jeoun Fast PCI-TX
 SMC EZNET 10/100
 UNEX NexNIC ND012C
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/arcnet-hardware.txt linux/Documentation/networking/arcnet-hardware.txt
--- linux.orig/Documentation/networking/arcnet-hardware.txt	2000-08-22 22:21:54.000000000 +0000
+++ linux/Documentation/networking/arcnet-hardware.txt	2002-08-01 06:42:43.000000000 +0000
@@ -2256,7 +2256,7 @@
 When I got my two cards, one of them had this switch set to "enhanced". That
 card didn't work at all, it wasn't even recognized by the driver. The other
 card had this switch set to "compatible" and it behaved absolutely normally. I
-guess that the switch on one of the cards, must have been changed accidently
+guess that the switch on one of the cards, must have been changed accidentally
 when the card was taken out of its former host. The question remains
 unanswered, what is the purpose of the "enhanced" position?
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/bonding.txt linux/Documentation/networking/bonding.txt
--- linux.orig/Documentation/networking/bonding.txt	2001-11-07 22:39:36.000000000 +0000
+++ linux/Documentation/networking/bonding.txt	2002-08-01 06:42:37.000000000 +0000
@@ -271,7 +271,7 @@
 	
 	If you wish to change the MAC address, you can set it with ifconfig:
 
-	  # ifconfig bond0 ha ether 00:11:22:33:44:55
+	  # ifconfig bond0 hw ether 00:11:22:33:44:55
 
 	The MAC address can be also changed by bringing down/up the device
 	and then changing its slaves (or their order):
@@ -503,7 +503,7 @@
 Resources and links
 ===================
 
-Current developement on this driver is posted to:
+Current development on this driver is posted to:
  - http://www.sourceforge.net/projects/bonding/
 
 Donald Becker's Ethernet Drivers and diag programs may be found at :
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/comx.txt linux/Documentation/networking/comx.txt
--- linux.orig/Documentation/networking/comx.txt	2001-04-06 17:42:48.000000000 +0000
+++ linux/Documentation/networking/comx.txt	2002-08-01 06:42:41.000000000 +0000
@@ -24,6 +24,8 @@
 LoCOMX (1x512 kbps passive board)
 MixCOM (1x512 or 2x512kbps passive board with a hardware watchdog an
 	optional BRI interface and optional flashROM (1-32M))
+SliceCOM	(1x2Mbps channelized E1 board)
+PciCOM	(X21)
 
 At the moment of writing this document, the (Cisco)-HDLC, LAPB, SyncPPP and
 Frame Relay (DTE, rfc1294 IP encapsulation with partially implemented Q933a 
@@ -72,7 +74,7 @@
 To create the interface 'comx0' which is the first channel of a COMX card:
 
 insmod comx 
-# insmod comx-hw-comx ; insmod comx-proto-hdlc  (these are usually
+# insmod comx-hw-comx ; insmod comx-proto-ppp  (these are usually
 autoloaded if you use the kernel module loader)
 
 mkdir /proc/comx/comx0
@@ -141,47 +143,45 @@
 The MixCOM board doesn't require firmware, the driver communicates with
 it through I/O ports. You can have three of these cards in one machine.
 
-THE HDLC LINE PROTOCOL DRIVER
+THE SLICECOM DRIVER
+
+The SliceCOM board doesn't require firmware. You can have 4 of these cards
+in one machine. The driver doesn't (yet) support shared interrupts, so
+you will need a separate IRQ line for every board.
+Read linux/Documentation/networking/slicecom.txt for help on configuring
+this adapter.
+
+THE HDLC/PPP LINE PROTOCOL DRIVER
+
+The HDLC/SyncPPP line protocol driver uses the kernel's built-in syncppp
+driver (syncppp.o). You don't have to manually select syncppp.o when building
+the kernel, the dependencies compile it in automatically.
 
-There's only one configurable parameter with this protocol: the 'keepalive'
-value. You can set this in seconds or set to 'off'. Agree with the administrator
-of your peer router on this setting. The default is 10 (seconds).
 
-EXAMPLE
 
+
+EXAMPLE
 (setting up hw parameters, see above)
+
+# using HDLC:
 echo hdlc >/proc/comx/comx0/protocol
 echo 10 >/proc/comx/comx0/keepalive	<- not necessary, 10 is the default
 ifconfig comx0 1.2.3.4 pointopoint 5.6.7.8 netmask 255.255.255.255
 
-
-THE PPP LINE PROTOCOL DRIVER
-
-To use this driver, you have to have ppp-2.3.4, and have a modified version of
-pppd (this pppd will work as async pppd to, the modifiactions merely relax 
-some restricions in order to be able to use non-async lines too.
-If configured, this driver can use Van Jacobson TCP header compression (you'll
-need the slhc.o module for this).
-Additionally to use this protocol, enable async ppp in your kernel config, and
-create the comx device special files in /dev. They're character special files
-with major 88, and their names must be the same as their network interface
-counterparts (i.e /dev/comx0 with minor 0 corresponds interface comx0 and so
-on).
-
-EXAMPLE
-
 (setting up hw parameters, see above)
+
+# using PPP:
 echo ppp >/proc/comx/comx0/protocol
 ifconfig comx0 up
-pppd comx0 1.2.3.4:5.6.7.8 persist	<- with this option pppd won't exit
-					   when the line goes down
+ifconfig comx0 1.2.3.4 pointopoint 5.6.7.8 netmask 255.255.255.255
+
 
 THE LAPB LINE PROTOCOL DRIVER
 
 For this, you'll need to configure LAPB support (See 'LAPB Data Link Driver' in
 'Network options' section) into your kernel (thanks to Jonathan Naylor for his 
 excellent implementation). 
-comxlapb.o provides the following files in the appropriate directory
+comx-proto-lapb.o provides the following files in the appropriate directory
 (the default values in parens): t1 (5), t2 (1), n2 (20), mode (DTE, STD) and
 window (7). Agree with the administrator of your peer router on these
 settings (most people use defaults, but you have to know if you are DTE or
@@ -221,7 +221,7 @@
 
 boardtype:
 Type of the hardware. Valid values are:
- 'comx', 'hicomx', 'locomx', 'cmx'.
+ 'comx', 'hicomx', 'locomx', 'cmx', 'slicecom'.
 
 protocol:
 Data-link protocol on this channel. Can be: HDLC, LAPB, PPP, FRAD
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/cs89x0.txt linux/Documentation/networking/cs89x0.txt
--- linux.orig/Documentation/networking/cs89x0.txt	2001-03-26 02:24:31.000000000 +0000
+++ linux/Documentation/networking/cs89x0.txt	2002-08-01 06:42:28.000000000 +0000
@@ -51,7 +51,7 @@
     6.2 Information Required Before Contacting Technical Support
     6.3 Obtaining the Latest Driver Version
     6.4 Current maintainer
-
+    6.5 Kernel boot parameters
 
 
 1.0 CIRRUS LOGIC LAN CS8900/CS8920 ETHERNET ADAPTERS
@@ -690,4 +690,14 @@
 6.4 Current maintainer
 
 In February 2000 the maintenance of this driver was assumed by Andrew
-Morton <andrewm@uow.edu.au>
+Morton <akpm@zip.com.au>
+
+6.5 Kernel module parameters
+
+For use in embedded environments with no cs89x0 EEPROM, the kernel boot
+parameter `cs89x0_media=' has been implemented.  Usage is:
+
+	cs89x0_media=rj45    or
+	cs89x0_media=aui     or
+	cs89x0_media=bnc
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/dl2k.txt linux/Documentation/networking/dl2k.txt
--- linux.orig/Documentation/networking/dl2k.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/networking/dl2k.txt	2002-08-01 06:42:32.000000000 +0000
@@ -1,7 +1,7 @@
 
     D-Link DL2000-based Gigabit Ethernet Adapter Installation
     for Linux
-    Jan 02, 2002
+    Jan 29, 2002
 
 Contents
 ========
@@ -199,8 +199,8 @@
 				  6          	1000Mbps full duplex.
 
 				  By default, the NIC operates at autosense.
-				  Note that only 1000mbps_fd and 1000mbps_hd
-				  types are available for fiber adapter.
+				  1000mbps_fd and 1000mbps_hd types are only
+				  available for fiber adapter.
 
 vlan=[0|1]			- Specifies the VLAN ID. If vlan=0, the
 				  Virtual Local Area Network (VLAN) function is
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/driver.txt linux/Documentation/networking/driver.txt
--- linux.orig/Documentation/networking/driver.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/driver.txt	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,84 @@
+Documents about softnet driver issues in general can be found
+at:
+
+	http://www.firstfloor.org/~andi/softnet/
+
+Transmit path guidelines:
+
+1) The hard_start_xmit method must never return '1' under any
+   normal circumstances.  It is considered a hard error unless
+   there is no way your device can tell ahead of time when it's
+   transmit function will become busy.
+
+   Instead it must maintain the queue properly.  For example,
+   for a driver implementing scatter-gather this means:
+
+	static int drv_hard_start_xmit(struct sk_buff *skb,
+		   		       struct net_device *dev)
+	{
+		struct drv *dp = dev->priv;
+
+		lock_tx(dp);
+		...
+		/* This is a hard error log it. */
+		if (TX_BUFFS_AVAIL(dp) <= (skb_shinfo(skb)->nr_frags + 1)) {
+			netif_stop_queue(dev);
+			unlock_tx(dp);
+			printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
+			       dev->name);
+			return 1;
+		}
+
+		... queue packet to card ...
+		... update tx consumer index ...
+
+		if (TX_BUFFS_AVAIL(dp) <= (MAX_SKB_FRAGS + 1))
+			netif_stop_queue(dev);
+
+		...
+		unlock_tx(dp);
+		...
+	}
+
+   And then at the end of your TX reclaimation event handling:
+
+	if (netif_queue_stopped(dp->dev) &&
+            TX_BUFFS_AVAIL(dp) > (MAX_SKB_FRAGS + 1))
+		netif_wake_queue(dp->dev);
+
+   For a non-scatter-gather supporting card, the three tests simply become:
+
+		/* This is a hard error log it. */
+		if (TX_BUFFS_AVAIL(dp) <= 0)
+
+   and:
+
+		if (TX_BUFFS_AVAIL(dp) == 0)
+
+   and:
+
+	if (netif_queue_stopped(dp->dev) &&
+            TX_BUFFS_AVAIL(dp) > 0)
+		netif_wake_queue(dp->dev);
+
+2) Do not forget to update netdev->trans_start to jiffies after
+   each new tx packet is given to the hardware.
+
+3) Do not forget that once you return 0 from your hard_start_xmit
+   method, it is your driver's responsibility to free up the SKB
+   and in some finite amount of time.
+
+   For example, this means that it is not allowed for your TX
+   mitigation scheme to let TX packets "hang out" in the TX
+   ring unreclaimed forever if no new TX packets are sent.
+   This error can deadlock sockets waiting for send buffer room
+   to be freed up.
+
+   If you return 1 from the hard_start_xmit method, you must not keep
+   any reference to that SKB and you must not attempt to free it up.
+
+Probing guidelines:
+
+1) Any hardware layer address you obtain for your device should
+   be verified.  For example, for ethernet check it with
+   linux/etherdevice.h:is_valid_ether_addr()
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/ifenslave.c linux/Documentation/networking/ifenslave.c
--- linux.orig/Documentation/networking/ifenslave.c	2001-11-07 22:39:36.000000000 +0000
+++ linux/Documentation/networking/ifenslave.c	2002-08-01 06:42:34.000000000 +0000
@@ -38,6 +38,9 @@
  *         take care of this itself
  *       - Try the SIOC*** versions of the bonding ioctls before using the
  *         old versions
+ *    - 2002/02/18 Erik Habbinga <erik_habbinga @ hp dot com> :
+ *       - ifr2.ifr_flags was not initialized in the hwaddr_notset case,
+ *         SIOCGIFFLAGS now called before hwaddr_notset test
  */
 
 static char *version =
@@ -288,19 +291,19 @@
 			     hwaddr from it's first slave.
 			   - if !hwaddr_notset, assign the master's hwaddr to each slave
 			*/
-	
+
+			strncpy(ifr2.ifr_name, slave_ifname, IFNAMSIZ);
+			if (ioctl(skfd, SIOCGIFFLAGS, &ifr2) < 0) {
+				int saved_errno = errno;
+				fprintf(stderr, "SIOCGIFFLAGS on %s failed: %s\n", slave_ifname,
+						strerror(saved_errno));
+				return 1;
+			}
+
 			if (hwaddr_notset) { /* we do nothing */
 
 			}
 			else {  /* we'll assign master's hwaddr to this slave */
-				strncpy(ifr2.ifr_name, slave_ifname, IFNAMSIZ);
-				if (ioctl(skfd, SIOCGIFFLAGS, &ifr2) < 0) {
-					int saved_errno = errno;
-					fprintf(stderr, "SIOCGIFFLAGS on %s failed: %s\n", slave_ifname,
-							strerror(saved_errno));
-					return 1;
-				}
-	
 				if (ifr2.ifr_flags & IFF_UP) {
 					ifr2.ifr_flags &= ~IFF_UP;
 					if (ioctl(skfd, SIOCSIFFLAGS, &ifr2) < 0) {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/ip-sysctl.txt linux/Documentation/networking/ip-sysctl.txt
--- linux.orig/Documentation/networking/ip-sysctl.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/networking/ip-sysctl.txt	2002-08-01 06:42:42.000000000 +0000
@@ -43,23 +43,23 @@
 	Minimum time-to-live of entries.  Should be enough to cover fragment
 	time-to-live on the reassembling side.  This minimum time-to-live  is
 	guaranteed if the pool size is less than inet_peer_threshold.
-	Measured in jiffies.
+	Measured in jiffies(1).
 
 inet_peer_maxttl - INTEGER
 	Maximum time-to-live of entries.  Unused entries will expire after
 	this period of time if there is no memory pressure on the pool (i.e.
 	when the number of entries in the pool is very small).
-	Measured in jiffies.
+	Measured in jiffies(1).
 
 inet_peer_gc_mintime - INTEGER
 	Minimum interval between garbage collection passes.  This interval is
 	in effect under high memory pressure on the pool.
-	Measured in jiffies.
+	Measured in jiffies(1).
 
 inet_peer_gc_maxtime - INTEGER
 	Minimum interval between garbage collection passes.  This interval is
 	in effect under low (or absent) memory pressure on the pool.
-	Measured in jiffies.
+	Measured in jiffies(1).
 
 TCP variables: 
 
@@ -81,7 +81,7 @@
 	How many keepalive probes TCP sends out, until it decides that the
 	connection is broken. Default value: 9.
 
-tcp_keepalive_interval - INTEGER
+tcp_keepalive_intvl - INTEGER
 	How frequently the probes are send out. Multiplied by
 	tcp_keepalive_probes it is time to kill not responding connection,
 	after probes started. Default value: 75sec i.e. connection
@@ -126,7 +126,13 @@
 	if network conditions require more than default value.
 
 tcp_tw_recycle - BOOLEAN
-	Enable fast recycling TIME-WAIT sockets. Default value is 1.
+	Enable fast recycling TIME-WAIT sockets. Default value is 0.
+	It should not be changed without advice/request of technical
+	experts.
+
+tcp_tw_reuse - BOOLEAN
+	Allow to reuse TIME-WAIT sockets for new connections when it is
+	safe from protocol viewpoint. Default value is 0.
 	It should not be changed without advice/request of technical
 	experts.
 
@@ -182,10 +188,7 @@
 	still did not receive an acknowledgement from connecting client.
 	Default value is 1024 for systems with more than 128Mb of memory,
 	and 128 for low memory machines. If server suffers of overload,
-	try to increase this number. Warning! If you make it greater
-	than 1024, it would be better to change TCP_SYNQ_HSIZE in
-	include/net/tcp.h to keep TCP_SYNQ_HSIZE*16<=tcp_max_syn_backlog
-	and to recompile kernel.
+	try to increase this number.
 
 tcp_window_scaling - BOOLEAN
 	Enable window scaling as defined in RFC1323.
@@ -313,28 +316,37 @@
 	Limit the maximal rates for sending ICMP packets whose type matches
 	icmp_ratemask (see below) to specific targets.
 	0 to disable any limiting, otherwise the maximal rate in jiffies(1)
-	Default: 1
+	Default: 100
 
 icmp_ratemask - INTEGER
 	Mask made of ICMP types for which rates are being limited.
-	Default: 6168
-	Note: 6168 = 0x1818 = 1<<ICMP_DEST_UNREACH + 1<<ICMP_SOURCE_QUENCH +
-	      1<<ICMP_TIME_EXCEEDED + 1<<ICMP_PARAMETERPROB, which means
-	      dest unreachable (3), source quench (4), time exceeded (11)
-	      and parameter problem (12) ICMP packets are rate limited
-	      (check values in icmp.h)
+	Significant bits: IHGFEDCBA9876543210
+	Default mask:     0000001100000011000 (6168)
+
+	Bit definitions (see include/linux/icmp.h):
+		0 Echo Reply
+		3 Destination Unreachable *
+		4 Source Quench *
+		5 Redirect
+		8 Echo Request
+		B Time Exceeded *
+		C Parameter Problem *
+		D Timestamp Request
+		E Timestamp Reply
+		F Info Request
+		G Info Reply
+		H Address Mask Request
+		I Address Mask Reply
+
+	* These are rate limited by default (see default mask above)
 
 icmp_ignore_bogus_error_responses - BOOLEAN
-	Some routers violate RFC 1122 by sending bogus responses to broadcast
+	Some routers violate RFC1122 by sending bogus responses to broadcast
 	frames.  Such violations are normally logged via a kernel warning.
 	If this is set to TRUE, the kernel will not give such warnings, which
 	will avoid log file clutter.
 	Default: FALSE
 
-(1) Jiffie: internal timeunit for the kernel. On the i386 1/100s, on the
-Alpha 1/1024s. See the HZ define in /usr/include/asm/param.h for the exact
-value on your system. 
-
 igmp_max_memberships - INTEGER
 	Change the maximum number of multicast groups we can subscribe to.
 	Default: 20
@@ -358,6 +370,17 @@
 	Do multicast routing. The kernel needs to be compiled with CONFIG_MROUTE
 	and a multicast routing daemon is required.
 
+medium_id - INTEGER
+	Integer value used to differentiate the devices by the medium they
+	are attached to. Two devices can have different id values when
+	the broadcast packets are received only on one of them.
+	The default value 0 means that the device is the only interface
+	to its medium, value of -1 means that medium is not known.
+	
+	Currently, it is used to change the proxy_arp behavior:
+	the proxy_arp feature is enabled for packets forwarded between
+	two devices attached to different media.
+
 proxy_arp - BOOLEAN
 	Do proxy arp.
 
@@ -397,7 +420,30 @@
 	0 - No source validation. 
 
 	Default value is 0. Note that some distributions enable it
-	in startip scripts.
+	in startup scripts.
+
+arp_filter - BOOLEAN
+	1 - Allows you to have multiple network interfaces on the same
+	subnet, and have the ARPs for each interface be answered
+	based on whether or not the kernel would route a packet from
+	the ARP'd IP out that interface (therefore you must use source
+	based routing for this to work). In other words it allows control
+	of which cards (usually 1) will respond to an arp request.
+
+	0 - (default) The kernel can respond to arp requests with addresses
+	from other interfaces. This may seem wrong but it usually makes
+	sense, because it increases the chance of successful communication.
+	IP addresses are owned by the complete host on Linux, not by
+	particular interfaces. Only for more complex setups like load-
+	balancing, does this behaviour cause problems.
+
+tag - INTEGER
+	Allows you to write a number, which can be used as required.
+	Default value is 0.
+
+(1) Jiffie: internal timeunit for the kernel. On the i386 1/100s, on the
+Alpha 1/1024s. See the HZ define in /usr/include/asm/param.h for the exact
+value on your system. 
 
 Alexey Kuznetsov.
 kuznet@ms2.inr.ac.ru
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/pktgen.txt linux/Documentation/networking/pktgen.txt
--- linux.orig/Documentation/networking/pktgen.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/pktgen.txt	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,50 @@
+How to use the Linux packet generator module.
+
+1. Enable CONFIG_NET_PKTGEN to compile and build pktgen.o, install it
+   in the place where insmod may find it.
+2. Cut script "ipg" (see below).
+3. Edit script to set preferred device and destination IP address.
+4. Run in shell: ". ipg"
+5. After this two commands are defined:
+   A. "pg" to start generator and to get results.
+   B. "pgset" to change generator parameters. F.e.
+      pgset "multiskb 1"      use multiple SKBs for packet generation
+      pgset "multiskb 0"      use single SKB for all transmits
+      pgset "pkt_size 9014"   sets packet size to 9014
+      pgset "frags 5"         packet will consist of 5 fragments
+      pgset "count 200000"    sets number of packets to send
+      pgset "ipg 5000"        sets artificial gap inserted between packets
+                              to 5000 nanoseconds
+      pgset "dst 10.0.0.1"    sets IP destination address
+                              (BEWARE! This generator is very aggressive!)
+      pgset "dstmac 00:00:00:00:00:00"    sets MAC destination address
+      pgset stop    	      aborts injection
+      
+  Also, ^C aborts generator.
+
+---- cut here
+
+#! /bin/sh
+
+modprobe pktgen.o
+
+function pgset() {
+    local result
+
+    echo $1 > /proc/net/pg
+
+    result=`cat /proc/net/pg | fgrep "Result: OK:"`
+    if [ "$result" = "" ]; then
+         cat /proc/net/pg | fgrep Result:
+    fi
+}
+
+function pg() {
+    echo inject > /proc/net/pg
+    cat /proc/net/pg
+}
+
+pgset "odev eth0"
+pgset "dst 0.0.0.0"
+
+---- cut here
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/ppp_generic.txt linux/Documentation/networking/ppp_generic.txt
--- linux.orig/Documentation/networking/ppp_generic.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/ppp_generic.txt	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,432 @@
+		PPP Generic Driver and Channel Interface
+		----------------------------------------
+
+			    Paul Mackerras
+			   paulus@samba.org
+			      7 Feb 2002
+
+The generic PPP driver in linux-2.4 provides an implementation of the
+functionality which is of use in any PPP implementation, including:
+
+* the network interface unit (ppp0 etc.)
+* the interface to the networking code
+* PPP multilink: splitting datagrams between multiple links, and
+  ordering and combining received fragments
+* the interface to pppd, via a /dev/ppp character device
+* packet compression and decompression
+* TCP/IP header compression and decompression
+* detecting network traffic for demand dialling and for idle timeouts
+* simple packet filtering
+
+For sending and receiving PPP frames, the generic PPP driver calls on
+the services of PPP `channels'.  A PPP channel encapsulates a
+mechanism for transporting PPP frames from one machine to another.  A
+PPP channel implementation can be arbitrarily complex internally but
+has a very simple interface with the generic PPP code: it merely has
+to be able to send PPP frames, receive PPP frames, and optionally
+handle ioctl requests.  Currently there are PPP channel
+implementations for asynchronous serial ports, synchronous serial
+ports, and for PPP over ethernet.
+
+This architecture makes it possible to implement PPP multilink in a
+natural and straightforward way, by allowing more than one channel to
+be linked to each ppp network interface unit.  The generic layer is
+responsible for splitting datagrams on transmit and recombining them
+on receive.
+
+
+PPP channel API
+---------------
+
+See include/linux/ppp_channel.h for the declaration of the types and
+functions used to communicate between the generic PPP layer and PPP
+channels.
+
+Each channel has to provide two functions to the generic PPP layer,
+via the ppp_channel.ops pointer:
+
+* start_xmit() is called by the generic layer when it has a frame to
+  send.  The channel has the option of rejecting the frame for
+  flow-control reasons.  In this case, start_xmit() should return 0
+  and the channel should call the ppp_output_wakeup() function at a
+  later time when it can accept frames again, and the generic layer
+  will then attempt to retransmit the rejected frame(s).  If the frame
+  is accepted, the start_xmit() function should return 1.
+
+* ioctl() provides an interface which can be used by a user-space
+  program to control aspects of the channel's behaviour.  This
+  procedure will be called when a user-space program does an ioctl
+  system call on an instance of /dev/ppp which is bound to the
+  channel.  (Usually it would only be pppd which would do this.)
+
+The generic PPP layer provides seven functions to channels:
+
+* ppp_register_channel() is called when a channel has been created, to
+  notify the PPP generic layer of its presence.  For example, setting
+  a serial port to the PPPDISC line discipline causes the ppp_async
+  channel code to call this function.
+
+* ppp_unregister_channel() is called when a channel is to be
+  destroyed.  For example, the ppp_async channel code calls this when
+  a hangup is detected on the serial port.
+
+* ppp_output_wakeup() is called by a channel when it has previously
+  rejected a call to its start_xmit function, and can now accept more
+  packets.
+
+* ppp_input() is called by a channel when it has received a complete
+  PPP frame.
+
+* ppp_input_error() is called by a channel when it has detected that a
+  frame has been lost or dropped (for example, because of a FCS (frame
+  check sequence) error).
+
+* ppp_channel_index() returns the channel index assigned by the PPP
+  generic layer to this channel.  The channel should provide some way
+  (e.g. an ioctl) to transmit this back to user-space, as user-space
+  will need it to attach an instance of /dev/ppp to this channel.
+
+* ppp_unit_number() returns the unit number of the ppp network
+  interface to which this channel is connected, or -1 if the channel
+  is not connected.
+
+Connecting a channel to the ppp generic layer is initiated from the
+channel code, rather than from the generic layer.  The channel is
+expected to have some way for a user-level process to control it
+independently of the ppp generic layer.  For example, with the
+ppp_async channel, this is provided by the file descriptor to the
+serial port.
+
+Generally a user-level process will initialize the underlying
+communications medium and prepare it to do PPP.  For example, with an
+async tty, this can involve setting the tty speed and modes, issuing
+modem commands, and then going through some sort of dialog with the
+remote system to invoke PPP service there.  We refer to this process
+as `discovery'.  Then the user-level process tells the medium to
+become a PPP channel and register itself with the generic PPP layer.
+The channel then has to report the channel number assigned to it back
+to the user-level process.  From that point, the PPP negotiation code
+in the PPP daemon (pppd) can take over and perform the PPP
+negotiation, accessing the channel through the /dev/ppp interface.
+
+At the interface to the PPP generic layer, PPP frames are stored in
+skbuff structures and start with the two-byte PPP protocol number.
+The frame does *not* include the 0xff `address' byte or the 0x03
+`control' byte that are optionally used in async PPP.  Nor is there
+any escaping of control characters, nor are there any FCS or framing
+characters included.  That is all the responsibility of the channel
+code, if it is needed for the particular medium.  That is, the skbuffs
+presented to the start_xmit() function contain only the 2-byte
+protocol number and the data, and the skbuffs presented to ppp_input()
+must be in the same format.
+
+The channel must provide an instance of a ppp_channel struct to
+represent the channel.  The channel is free to use the `private' field
+however it wishes.  The channel should initialize the `mtu' and
+`hdrlen' fields before calling ppp_register_channel() and not change
+them until after ppp_unregister_channel() returns.  The `mtu' field
+represents the maximum size of the data part of the PPP frames, that
+is, it does not include the 2-byte protocol number.
+
+If the channel needs some headroom in the skbuffs presented to it for
+transmission (i.e., some space free in the skbuff data area before the
+start of the PPP frame), it should set the `hdrlen' field of the
+ppp_channel struct to the amount of headroom required.  The generic
+PPP layer will attempt to provide that much headroom but the channel
+should still check if there is sufficient headroom and copy the skbuff
+if there isn't.
+
+On the input side, channels should ideally provide at least 2 bytes of
+headroom in the skbuffs presented to ppp_input().  The generic PPP
+code does not require this but will be more efficient if this is done.
+
+
+Buffering and flow control
+--------------------------
+
+The generic PPP layer has been designed to minimize the amount of data
+that it buffers in the transmit direction.  It maintains a queue of
+transmit packets for the PPP unit (network interface device) plus a
+queue of transmit packets for each attached channel.  Normally the
+transmit queue for the unit will contain at most one packet; the
+exceptions are when pppd sends packets by writing to /dev/ppp, and
+when the core networking code calls the generic layer's start_xmit()
+function with the queue stopped, i.e. when the generic layer has
+called netif_stop_queue(), which only happens on a transmit timeout.
+The start_xmit function always accepts and queues the packet which it
+is asked to transmit.
+
+Transmit packets are dequeued from the PPP unit transmit queue and
+then subjected to TCP/IP header compression and packet compression
+(Deflate or BSD-Compress compression), as appropriate.  After this
+point the packets can no longer be reordered, as the decompression
+algorithms rely on receiving compressed packets in the same order that
+they were generated.
+
+If multilink is not in use, this packet is then passed to the attached
+channel's start_xmit() function.  If the channel refuses to take
+the packet, the generic layer saves it for later transmission.  The
+generic layer will call the channel's start_xmit() function again
+when the channel calls  ppp_output_wakeup() or when the core
+networking code calls the generic layer's start_xmit() function
+again.  The generic layer contains no timeout and retransmission
+logic; it relies on the core networking code for that.
+
+If multilink is in use, the generic layer divides the packet into one
+or more fragments and puts a multilink header on each fragment.  It
+decides how many fragments to use based on the length of the packet
+and the number of channels which are potentially able to accept a
+fragment at the moment.  A channel is potentially able to accept a
+fragment if it doesn't have any fragments currently queued up for it
+to transmit.  The channel may still refuse a fragment; in this case
+the fragment is queued up for the channel to transmit later.  This
+scheme has the effect that more fragments are given to higher-
+bandwidth channels.  It also means that under light load, the generic
+layer will tend to fragment large packets across all the channels,
+thus reducing latency, while under heavy load, packets will tend to be
+transmitted as single fragments, thus reducing the overhead of
+fragmentation.
+
+
+SMP safety
+----------
+
+The PPP generic layer has been designed to be SMP-safe.  Locks are
+used around accesses to the internal data structures where necessary
+to ensure their integrity.  As part of this, the generic layer
+requires that the channels adhere to certain requirements and in turn
+provides certain guarantees to the channels.  Essentially the channels
+are required to provide the appropriate locking on the ppp_channel
+structures that form the basis of the communication between the
+channel and the generic layer.  This is because the channel provides
+the storage for the ppp_channel structure, and so the channel is
+required to provide the guarantee that this storage exists and is
+valid at the appropriate times.
+
+The generic layer requires these guarantees from the channel:
+
+* The ppp_channel object must exist from the time that
+  ppp_register_channel() is called until after the call to
+  ppp_unregister_channel() returns.
+
+* No thread may be in a call to any of ppp_input(), ppp_input_error(),
+  ppp_output_wakeup(), ppp_channel_index() or ppp_unit_number() for a
+  channel at the time that ppp_unregister_channel() is called for that
+  channel.
+
+* ppp_register_channel() and ppp_unregister_channel() must be called
+  from process context, not interrupt or softirq/BH context.
+
+* The remaining generic layer functions may be called at softirq/BH
+  level but must not be called from a hardware interrupt handler.
+
+* The generic layer may call the channel start_xmit() function at
+  softirq/BH level but will not call it at interrupt level.  Thus the
+  start_xmit() function may not block.
+
+* The generic layer will only call the channel ioctl() function in
+  process context.
+
+The generic layer provides these guarantees to the channels:
+
+* The generic layer will not call the start_xmit() function for a
+  channel while any thread is already executing in that function for
+  that channel.
+
+* The generic layer will not call the ioctl() function for a channel
+  while any thread is already executing in that function for that
+  channel.
+
+* By the time a call to ppp_unregister_channel() returns, no thread
+  will be executing in a call from the generic layer to that channel's
+  start_xmit() or ioctl() function, and the generic layer will not
+  call either of those functions subsequently.
+
+
+Interface to pppd
+-----------------
+
+The PPP generic layer exports a character device interface called
+/dev/ppp.  This is used by pppd to control PPP interface units and
+channels.  Although there is only one /dev/ppp, each open instance of
+/dev/ppp acts independently and can be attached either to a PPP unit
+or a PPP channel.  This is achieved using the file->private_data field
+to point to a separate object for each open instance of /dev/ppp.  In
+this way an effect similar to Solaris' clone open is obtained,
+allowing us to control an arbitrary number of PPP interfaces and
+channels without having to fill up /dev with hundreds of device names.
+
+When /dev/ppp is opened, a new instance is created which is initially
+unattached.  Using an ioctl call, it can then be attached to an
+existing unit, attached to a newly-created unit, or attached to an
+existing channel.  An instance attached to a unit can be used to send
+and receive PPP control frames, using the read() and write() system
+calls, along with poll() if necessary.  Similarly, an instance
+attached to a channel can be used to send and receive PPP frames on
+that channel.
+
+In multilink terms, the unit represents the bundle, while the channels
+represent the individual physical links.  Thus, a PPP frame sent by a
+write to the unit (i.e., to an instance of /dev/ppp attached to the
+unit) will be subject to bundle-level compression and to fragmentation
+across the individual links (if multilink is in use).  In contrast, a
+PPP frame sent by a write to the channel will be sent as-is on that
+channel, without any multilink header.
+
+A channel is not initially attached to any unit.  In this state it can
+be used for PPP negotiation but not for the transfer of data packets.
+It can then be connected to a PPP unit with an ioctl call, which
+makes it available to send and receive data packets for that unit.
+
+The ioctl calls which are available on an instance of /dev/ppp depend
+on whether it is unattached, attached to a PPP interface, or attached
+to a PPP channel.  The ioctl calls which are available on an
+unattached instance are:
+
+* PPPIOCNEWUNIT creates a new PPP interface and makes this /dev/ppp
+  instance the "owner" of the interface.  The argument should point to
+  an int which is the desired unit number if >= 0, or -1 to assign the
+  lowest unused unit number.  Being the owner of the interface means
+  that the interface will be shut down if this instance of /dev/ppp is
+  closed.
+
+* PPPIOCATTACH attaches this instance to an existing PPP interface.
+  The argument should point to an int containing the unit number.
+  This does not make this instance the owner of the PPP interface.
+
+* PPPIOCATTCHAN attaches this instance to an existing PPP channel.
+  The argument should point to an int containing the channel number.
+
+The ioctl calls available on an instance of /dev/ppp attached to a
+channel are:
+
+* PPPIOCDETACH detaches the instance from the channel.  This ioctl is
+  deprecated since the same effect can be achieved by closing the
+  instance.  In order to prevent possible races this ioctl will fail
+  with an EINVAL error if more than one file descriptor refers to this
+  instance (i.e. as a result of dup(), dup2() or fork()).
+
+* PPPIOCCONNECT connects this channel to a PPP interface.  The
+  argument should point to an int containing the interface unit
+  number.  It will return an EINVAL error if the channel is already
+  connected to an interface, or ENXIO if the requested interface does
+  not exist.
+
+* PPPIOCDISCONN disconnects this channel from the PPP interface that
+  it is connected to.  It will return an EINVAL error if the channel
+  is not connected to an interface.
+
+* All other ioctl commands are passed to the channel ioctl() function.
+
+The ioctl calls that are available on an instance that is attached to
+an interface unit are:
+
+* PPPIOCSMRU sets the MRU (maximum receive unit) for the interface.
+  The argument should point to an int containing the new MRU value.
+
+* PPPIOCSFLAGS sets flags which control the operation of the
+  interface.  The argument should be a pointer to an int containing
+  the new flags value.  The bits in the flags value that can be set
+  are:
+	SC_COMP_TCP		enable transmit TCP header compression
+	SC_NO_TCP_CCID		disable connection-id compression for
+				TCP header compression
+	SC_REJ_COMP_TCP		disable receive TCP header decompression
+	SC_CCP_OPEN		Compression Control Protocol (CCP) is
+				open, so inspect CCP packets
+	SC_CCP_UP		CCP is up, may (de)compress packets
+	SC_LOOP_TRAFFIC		send IP traffic to pppd
+	SC_MULTILINK		enable PPP multilink fragmentation on
+				transmitted packets
+	SC_MP_SHORTSEQ		expect short multilink sequence
+				numbers on received multilink fragments
+	SC_MP_XSHORTSEQ		transmit short multilink sequence nos.
+
+  The values of these flags are defined in <linux/if_ppp.h>.  Note
+  that the values of the SC_MULTILINK, SC_MP_SHORTSEQ and
+  SC_MP_XSHORTSEQ bits are ignored if the CONFIG_PPP_MULTILINK option
+  is not selected.
+
+* PPPIOCGFLAGS returns the value of the status/control flags for the
+  interface unit.  The argument should point to an int where the ioctl
+  will store the flags value.  As well as the values listed above for
+  PPPIOCSFLAGS, the following bits may be set in the returned value:
+	SC_COMP_RUN		CCP compressor is running
+	SC_DECOMP_RUN		CCP decompressor is running
+	SC_DC_ERROR		CCP decompressor detected non-fatal error
+	SC_DC_FERROR		CCP decompressor detected fatal error
+
+* PPPIOCSCOMPRESS sets the parameters for packet compression or
+  decompression.  The argument should point to a ppp_option_data
+  structure (defined in <linux/if_ppp.h>), which contains a
+  pointer/length pair which should describe a block of memory
+  containing a CCP option specifying a compression method and its
+  parameters.  The ppp_option_data struct also contains a `transmit'
+  field.  If this is 0, the ioctl will affect the receive path,
+  otherwise the transmit path.
+
+* PPPIOCGUNIT returns, in the int pointed to by the argument, the unit
+  number of this interface unit.
+
+* PPPIOCSDEBUG sets the debug flags for the interface to the value in
+  the int pointed to by the argument.  Only the least significant bit
+  is used; if this is 1 the generic layer will print some debug
+  messages during its operation.  This is only intended for debugging
+  the generic PPP layer code; it is generally not helpful for working
+  out why a PPP connection is failing.
+
+* PPPIOCGDEBUG returns the debug flags for the interface in the int
+  pointed to by the argument.
+
+* PPPIOCGIDLE returns the time, in seconds, since the last data
+  packets were sent and received.  The argument should point to a
+  ppp_idle structure (defined in <linux/ppp_defs.h>).  If the
+  CONFIG_PPP_FILTER option is enabled, the set of packets which reset
+  the transmit and receive idle timers is restricted to those which
+  pass the `active' packet filter.
+
+* PPPIOCSMAXCID sets the maximum connection-ID parameter (and thus the
+  number of connection slots) for the TCP header compressor and
+  decompressor.  The lower 16 bits of the int pointed to by the
+  argument specify the maximum connection-ID for the compressor.  If
+  the upper 16 bits of that int are non-zero, they specify the maximum
+  connection-ID for the decompressor, otherwise the decompressor's
+  maximum connection-ID is set to 15.
+
+* PPPIOCSNPMODE sets the network-protocol mode for a given network
+  protocol.  The argument should point to an npioctl struct (defined
+  in <linux/if_ppp.h>).  The `protocol' field gives the PPP protocol
+  number for the protocol to be affected, and the `mode' field
+  specifies what to do with packets for that protocol:
+
+	NPMODE_PASS	normal operation, transmit and receive packets
+	NPMODE_DROP	silently drop packets for this protocol
+	NPMODE_ERROR	drop packets and return an error on transmit
+	NPMODE_QUEUE	queue up packets for transmit, drop received
+			packets
+
+  At present NPMODE_ERROR and NPMODE_QUEUE have the same effect as
+  NPMODE_DROP.
+
+* PPPIOCGNPMODE returns the network-protocol mode for a given
+  protocol.  The argument should point to an npioctl struct with the
+  `protocol' field set to the PPP protocol number for the protocol of
+  interest.  On return the `mode' field will be set to the network-
+  protocol mode for that protocol.
+
+* PPPIOCSPASS and PPPIOCSACTIVE set the `pass' and `active' packet
+  filters.  These ioctls are only available if the CONFIG_PPP_FILTER
+  option is selected.  The argument should point to a sock_fprog
+  structure (defined in <linux/filter.h>) containing the compiled BPF
+  instructions for the filter.  Packets are dropped if they fail the
+  `pass' filter; otherwise, if they fail the `active' filter they are
+  passed but they do not reset the transmit or receive idle timer.
+
+* PPPIOCSMRRU enables or disables multilink processing for received
+  packets and sets the multilink MRRU (maximum reconstructed receive
+  unit).  The argument should point to an int containing the new MRRU
+  value.  If the MRRU value is 0, processing of received multilink
+  fragments is disabled.  This ioctl is only available if the
+  CONFIG_PPP_MULTILINK option is selected.
+
+Last modified: 7-feb-2002
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/skfp.txt linux/Documentation/networking/skfp.txt
--- linux.orig/Documentation/networking/skfp.txt	2000-05-12 18:43:26.000000000 +0000
+++ linux/Documentation/networking/skfp.txt	2002-08-01 06:42:27.000000000 +0000
@@ -143,6 +143,10 @@
 (6) HISTORY
 ===========
 
+v2.07 (20020506) (In-Kernel version)
+    Fix: Transmit Descriptor struct
+    Fix: Receive Descriptor struct
+
 v2.06 (20000511) (In-Kernel version)
     New features:
 	- 64 bit support
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/slicecom.hun linux/Documentation/networking/slicecom.hun
--- linux.orig/Documentation/networking/slicecom.hun	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/slicecom.hun	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,371 @@
+
+SliceCOM adapter felhasznaloi dokumentacioja - 0.51 verziohoz
+
+Bartók István <bartoki@itc.hu>
+Utolso modositas: Wed Aug 29 17:26:58 CEST 2001
+
+-----------------------------------------------------------------
+
+Hasznalata:
+
+Forditas:
+
+Code maturity level options
+	[*] Prompt for development and/or incomplete code/drivers
+
+Network device support
+	Wan interfaces
+		<M> MultiGate (COMX) synchronous
+			<M> Support for MUNICH based boards: SliceCOM, PCICOM (NEW)
+			<M> Support for HDLC and syncPPP...
+
+
+A modulok betoltese:
+
+modprobe comx
+
+modprobe comx-proto-ppp		# a Cisco-HDLC es a SyncPPP protokollt is
+				# ez a modul adja
+
+modprobe comx-hw-munich		# a modul betoltodeskor azonnal jelent a
+				# syslogba a detektalt kartyakrol
+
+
+Konfiguralas:
+
+# Ezen az interfeszen Cisco-HDLC vonali protokoll fog futni
+# Az interfeszhez rendelt idoszeletek: 1,2 (128 kbit/sec-es vonal)
+# (a G.703 keretben az elso adatot vivo idoszelet az 1-es)
+#
+mkdir /proc/comx/comx0.1/
+echo slicecom	>/proc/comx/comx0.1/boardtype
+echo hdlc	>/proc/comx/comx0.1/protocol
+echo 1 2	>/proc/comx/comx0.1/timeslots
+
+
+# Ezen az interfeszen SyncPPP vonali protokoll fog futni
+# Az interfeszhez rendelt idoszelet: 3 (64 kbit/sec-es vonal)
+#
+mkdir /proc/comx/comx0.2/
+echo slicecom	>/proc/comx/comx0.2/boardtype
+echo ppp	>/proc/comx/comx0.2/protocol
+echo 3		>/proc/comx/comx0.2/timeslots
+
+...
+
+ifconfig comx0.1 up
+ifconfig comx0.2 up
+
+-----------------------------------------------------------------
+
+A COMX driverek default 20 csomagnyi transmit queue-t rendelnek a halozati
+interfeszekhez. WAN halozatokban ennel hosszabbat is szokas hasznalni
+(20 es 100 kozott), hogy a vonal kihasznaltsaga nagy terheles eseten jobb
+legyen (bar ezzel megno a varhato kesleltetes a csomagok sorban allasa miatt):
+
+# ifconfig comx0 txqueuelen 50
+
+Ezt a beallitasi lehetoseget csak az ujabb disztribuciok ifconfig parancsa
+tamogatja (amik mar a 2.2 kernelekhez keszultek, mint a RedHat 6.1 vagy a
+Debian 2.2).
+
+A 2.1-es Debian disztribuciohoz a http://www.debian.org/~rcw/2.2/netbase/
+cimrol toltheto le ujabb netbase csomag, ami mar ilyet tamogato ifconfig
+parancsot tartalmaz. Bovebben a 2.2 kernel hasznalatarol Debian 2.1 alatt:
+http://www.debian.org/releases/stable/running-kernel-2.2
+
+-----------------------------------------------------------------
+
+A kartya LED-jeinek jelentese:
+
+piros	- eg, ha Remote Alarm-ot kuld a tuloldal
+zold	- eg, ha a vett jelben megtalalja a keretszinkront
+
+Reszletesebben:
+
+piros:	zold:	jelentes:
+
+-	-	nincs keretszinkron (nincs jel, vagy rossz a jel)
+-	eg	"minden rendben"
+eg	eg	a vetel OK, de a tuloldal Remote Alarm-ot kuld
+eg	-	ez nincs ertelmezve, egyelore funkcio nelkul
+
+-----------------------------------------------------------------
+
+Reszletesebb leiras a hardver beallitasi lehetosegeirol:
+
+Az altalanos,- es a protokoll-retegek beallitasi lehetosegeirol a 'comx.txt'
+fajlban leirtak SliceCOM kartyanal is ervenyesek, itt csak a hardver-specifikus
+beallitasi lehetosegek vannak osszefoglalva:
+
+Konfiguralasi interfesz a /proc/comx/ alatt:
+
+Minden timeslot-csoportnak kulon comx* interfeszt kell letrehozni mkdir-rel:
+comx0, comx1, .. stb. Itt beallithato, hogy az adott interfesz hanyadik kartya
+melyik timeslotja(i)bol alljon ossze. A Cisco-fele serial3:1 elnevezesek
+(serial3:1 = a 3. kartyaban az 1-es idoszelet-csoport) Linuxon aliasing-ot
+jelentenenek, ezert mi nem tudunk ilyen elnevezest hasznalni.
+
+Tobb kartya eseten a comx0.1, comx0.2, ... vagy slice0.1, slice0.2 nevek
+hasznalhatoak.
+
+Tobb SliceCOM kartya is lehet egy gepben, de sajat interrupt kell mindegyiknek,
+nem tud meg megosztott interruptot kezelni.
+
+Az egesz kartyat erinto beallitasok:
+
+Az ioport es irq beallitas nincs: amit a PCI BIOS kioszt a rendszernek,
+azt hasznalja a driver.
+
+
+comx0/boardnum	- hanyadik SliceCOM kartya a gepben (a 'termeszetes' PCI
+		sorrendben ertve: ahogyan a /proc/pci-ban vagy az 'lspci'
+		kimeneteben megjelenik, altalaban az alaplapi PCI meghajto
+		aramkorokhoz kozelebb eso kartyak a kisebb sorszamuak)
+
+		Default: 0 (0-tol kezdodik a szamolas)
+
+
+Bar a kovetkezoket csak egy-egy interfeszen allitjuk at, megis az egesz kartya
+mukodeset egyszerre allitjak. A megkotes hogy csak UP-ban levo interfeszen
+hasznalhatoak, azert van, mert kulonben nem vart eredmenyekre vezetne egy ilyen
+paranccsorozat:
+
+	echo 0        >boardnum
+	echo internal >clock_source
+	echo 1        >boardnum
+
+- Ez a 0-s board clock_source-at allitana at.
+
+Ezek a beallitasok megmaradnak az osszes interfesz torlesekor, de torlodnek
+a driver modul ki/betoltesekor.
+
+
+comx0/clock_source - A Tx orajelforrasa, a Cisco-val hasonlatosra keszult.
+	Hasznalata:
+
+	papaya:# echo line     >/proc/comx/comx0/clock_source
+	papaya:# echo internal >/proc/comx/comx0/clock_source
+
+	line     - A Tx orajelet a vett adatfolyambol dekodolja, igyekszik
+		igazodni hozza. Ha nem lat orajelet az inputon, akkor
+		atall a sajat orajelgeneratorara.
+	internal - A Tx orajelet a sajat orajelgeneratora szolgaltatja.
+
+	Default: line
+
+	Normal osszeallitas eseten a tavkozlesi szolgaltato eszkoze
+	(pl. HDSL modem) adja az orajelet, ezert ez a default.
+
+
+comx0/framing	- A CRC4 ki/be kapcsolasa
+
+	A CRC4: 16 PCM keretet (A PCM keret az, amibe a 32 darab 64
+	kilobites csatorna van bemultiplexalva. Nem osszetevesztendo a HDLC
+	kerettel.) 2x8 -as csoportokra osztanak, es azokhoz 4-4 bites CRC-t
+	szamolnak. Elsosorban a vonal minosegenek a monitorozasara szolgal.
+
+	papaya:~# echo crc4	>/proc/comx/comx0/framing
+	papaya:~# echo no-crc4	>/proc/comx/comx0/framing
+
+	Default a 'crc4', a MATAV vonalak altalaban igy futnak. De ha nem
+	egyforma is a beallitas a vonal ket vegen, attol a forgalom altalaban
+	at tud menni.
+
+
+comx0/linecode	- A vonali kodolas beallitasa
+
+	papaya:~# echo hdb3	>/proc/comx/comx0/linecode
+	papaya:~# echo ami	>/proc/comx/comx0/linecode
+
+	Default a 'hdb3', a MATAV vonalak igy futnak.
+	
+	(az AMI kodolas igen ritka E1-es vonalaknal). Ha ez a beallitas nem
+	egyezik a vonal ket vegen, akkor elofordulhat hogy a keretszinkron
+	osszejon, de CRC4-hibak es a vonalakon atvitt adatokban is hibak
+	keletkeznek (amit a HDLC/SyncPPP szinten CRC-hibaval jelez)
+
+
+comx0/reg	- a kartya aramkoreinek, a MUNICH (reg) es a FALC (lbireg)
+comx0/lbireg	regisztereinek kozvetlen elerese. Hasznalata:
+
+		echo >reg 0x04 0x0	- a 4-es regiszterbe 0-t ir
+		echo >reg 0x104		- printk()-val kiirja a 4-es regiszter
+					tartalmat a syslogba.
+
+		WARNING: ezek csak a fejleszteshez keszultek, sok galibat
+		lehet veluk okozni!
+
+
+comx0/loopback - A kartya G.703 jelenek a visszahurkolasara is van lehetoseg:
+
+	papaya:# echo none   >/proc/comx/comx0/loopback
+	papaya:# echo local  >/proc/comx/comx0/loopback
+	papaya:# echo remote >/proc/comx/comx0/loopback
+
+	none   - nincs visszahurkolas, normal mukodes
+	local  - a kartya a sajat maga altal adott jelet kapja vissza
+	remote - a kartya a kivulrol vett jelet adja kifele
+
+	Default: none
+
+-----------------------------------------------------------------
+
+Az interfeszhez (Cisco terminologiaban 'channel-group') kapcsolodo beallitasok:
+
+comx0/timeslots	- mely timeslotok (idoszeletek) tartoznak az adott interfeszhez.
+
+	papaya:~# cat /proc/comx/comx0/timeslots
+	1 3 4 5 6
+	papaya:~#
+
+	Egy timeslot megkeresese (hanyas interfeszbe tartozik nalunk):
+
+	papaya:~# grep ' 4' /proc/comx/comx*/timeslots
+	/proc/comx/comx0/timeslots:1 3 4 5 6
+	papaya:~#
+
+	Beallitasa:
+	papaya:~# echo '1 5 2 6 7 8' >/proc/comx/comx0/timeslots
+	
+	A timeslotok sorrendje nem szamit, '1 3 2' ugyanaz mint az '1 2 3'.
+
+	Beallitashoz az adott interfesznek DOWN-ban kell lennie
+	(ifconfig comx0 down), de ugyanannak a kartyanak a tobbi interfesze
+	uzemelhet kozben.
+
+	Beallitaskor leellenorzi, hogy az uj timeslotok nem utkoznek-e egy
+	masik interfesz timeslotjaival. Ha utkoznek, akkor nem allitja at.
+
+	Mindig 10-es szamrendszerben tortenik a timeslotok ertelmezese, nehogy
+	a 08, 09 alaku felirast rosszul ertelmezze.
+
+-----------------------------------------------------------------
+
+Az interfeszek es a kartya allapotanak lekerdezese:
+
+- A ' '-szel kezdodo sorok az eredeti kimenetet, a //-rel kezdodo sorok a
+magyarazatot jelzik.
+
+ papaya:~$ cat /proc/comx/comx1/status
+ Interface administrative status is UP, modem status is UP, protocol is UP
+ Modem status changes: 0, Transmitter status is IDLE, tbusy: 0
+ Interface load (input): 978376 / 947808 / 951024 bits/s (5s/5m/15m)
+               (output): 978376 / 947848 / 951024 bits/s (5s/5m/15m)
+ Debug flags: none
+ RX errors: len: 22, overrun: 1, crc: 0, aborts: 0
+            buffer overrun: 0, pbuffer overrun: 0
+ TX errors: underrun: 0
+ Line keepalive (value: 10) status UP [0]
+
+// Itt kezdodik a hardver-specifikus resz:
+ Controller status:
+         No alarms
+
+// Alarm: hibajelzes:
+//
+// No alarms - minden rendben
+//
+// LOS  - Loss Of Signal - nem erzekel jelet a bemeneten.
+// AIS  - Alarm Indication Signal - csak egymas utani 1-esek jonnek
+//	a bemeneten, a tuloldal igy is jelezheti hogy meghibasodott vagy
+//	nincs inicializalva.
+// AUXP - Auxiliary Pattern Indication - 01010101.. sorozat jon a bemeneten.
+// LFA  - Loss of Frame Alignment - nincs keretszinkron
+// RRA  - Receive Remote Alarm - a tuloldal el, de hibat jelez.
+// LMFA - Loss of CRC4 Multiframe Alignment - nincs CRC4-multikeret-szinkron
+// NMF  - No Multiframe alignment Found after 400 msec - ilyen alarm a no-crc4
+//	es crc4 keretezesek eseten nincs, lasd lentebb
+//
+// Egyeb lehetseges hibajelzesek:
+//
+// Transmit Line Short - a kartya ugy erzi hogy az adasi kimenete rovidre
+//	van zarva, ezert kikapcsolta az adast. (nem feltetlenul veszi eszre
+//	a kulso rovidzarat)
+
+// A veteli oldal csomagjainak lancolt listai, debug celokra:
+
+ Rx ring:
+         rafutott: 0
+         lastcheck: 50845731, jiffies: 51314281
+         base: 017b1858
+         rx_desc_ptr: 0
+         rx_desc_ptr: 017b1858
+         hw_curr_ptr: 017b1858
+         06040000 017b1868 017b1898 c016ff00
+         06040000 017b1878 017b1e9c c016ff00
+         46040000 017b1888 017b24a0 c016ff00
+         06040000 017b1858 017b2aa4 c016ff00
+
+// A kartyat hasznalo tobbi interfesz: a 0-s channel-group a comx1 interfesz,
+// es az 1,2,...,16 timeslotok tartoznak hozza:
+
+ Interfaces using this board: (channel-group, interface, timeslots)
+          0 comx1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+          1 comx2: 17
+          2 comx3: 18
+          3 comx4: 19
+          4 comx5: 20
+          5 comx6: 21
+          6 comx7: 22
+          7 comx8: 23
+          8 comx9: 24
+          9 comx10: 25
+         10 comx11: 26
+         11 comx12: 27
+         12 comx13: 28
+         13 comx14: 29
+         14 comx15: 30
+         15 comx16: 31
+
+// Hany esemenyt kezelt le a driver egy-egy hardver-interrupt kiszolgalasanal:
+
+ Interrupt work histogram:
+ hist[ 0]:        0 hist[ 1]:        2 hist[ 2]:    18574 hist[ 3]:       79
+ hist[ 4]:       14 hist[ 5]:        1 hist[ 6]:        0 hist[ 7]:        1
+ hist[ 8]:        0 hist[ 9]:        7
+
+// Hany kikuldendo csomag volt mar a Tx-ringben amikor ujabb lett irva bele:
+
+ Tx ring histogram:
+ hist[ 0]:     2329 hist[ 1]:        0 hist[ 2]:        0 hist[ 3]:        0
+
+// Az E1-interfesz hiba-szamlaloi, az rfc2495-nek megfeleloen:
+// (kb. a Cisco routerek "show controllers e1" formatumaban: http://www.cisco.com/univercd/cc/td/doc/product/software/ios11/rbook/rinterfc.htm#xtocid25669126)
+
+Data in current interval (91 seconds elapsed):
+   9516 Line Code Violations, 65 Path Code Violations, 2 E-Bit Errors
+   0 Slip Secs, 2 Fr Loss Secs, 2 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 11 Unavail Secs
+Data in Interval 1 (15 minutes):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 4 intervals (1 hour):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 96 intervals (24 hours):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+
+-----------------------------------------------------------------
+
+Nehany kulonlegesebb beallitasi lehetoseg (idovel beepulhetnek majd a driverbe):
+Ezekkel sok galibat lehet okozni, nagyon ovatosan kell oket hasznalni!
+
+	modified CRC-4, for improved interworking of CRC-4 and non-CRC-4
+	devices: (lasd page 107 es g706 Annex B)
+		lbireg[ 0x1b ] |= 0x08
+		lbireg[ 0x1c ] |= 0xc0
+	- ilyenkor ertelmezett az NMF - 'No Multiframe alignment Found after
+	400 msec' alarm.
+
+	FALC - a vonali meghajto IC
+	local loop - a sajat adasomat halljam vissza
+	remote loop - a kivulrol jovo adast adom vissza
+
+	Egy hibakeresesre hasznalhato dolog:
+		- 1-es timeslot local loop a FALC-ban:	echo >lbireg 0x1d 0x21
+		- local loop kikapcsolasa:		echo >lbireg 0x1d 0x00
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/slicecom.txt linux/Documentation/networking/slicecom.txt
--- linux.orig/Documentation/networking/slicecom.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/networking/slicecom.txt	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,369 @@
+
+SliceCOM adapter user's documentation - for the 0.51 driver version
+
+Written by Bartók István <bartoki@itc.hu>
+
+English translation: Lakatos György <gyuri@itc.hu>
+Mon Dec 11 15:28:42 CET 2000
+
+Last modified: Wed Aug 29 17:25:37 CEST 2001
+
+-----------------------------------------------------------------
+
+Usage:
+
+Compiling the kernel:
+
+Code maturity level options
+	[*] Prompt for development and/or incomplete code/drivers
+
+Network device support
+	Wan interfaces
+		<M> MultiGate (COMX) synchronous
+			<M> Support for MUNICH based boards: SliceCOM, PCICOM (NEW)
+			<M> Support for HDLC and syncPPP...
+
+
+Loading the modules:
+
+modprobe comx
+
+modprobe comx-proto-ppp		# module for  Cisco-HDLC and SyncPPP protocols
+
+modprobe comx-hw-munich		# the module logs information by the kernel
+				# about the detected boards
+
+
+Configuring the board:
+
+# This interface will use the Cisco-HDLC line protocol,
+# the timeslices assigned are 1,2 (128 KiBit line speed)
+# (the first data timeslice in the G.703 frame is no. 1)
+#
+mkdir /proc/comx/comx0.1/
+echo slicecom	>/proc/comx/comx0.1/boardtype
+echo hdlc	>/proc/comx/comx0.1/protocol
+echo 1 2	>/proc/comx/comx0.1/timeslots
+
+
+# This interface uses SyncPPP line protocol, the assigned 
+# is no. 3 (64 KiBit line speed)
+#
+mkdir /proc/comx/comx0.2/
+echo slicecom	>/proc/comx/comx0.2/boardtype
+echo ppp	>/proc/comx/comx0.2/protocol
+echo 3		>/proc/comx/comx0.2/timeslots
+
+...
+
+ifconfig comx0.1 up
+ifconfig comx0.2 up
+
+-----------------------------------------------------------------
+
+The COMX interfaces use a 10 packet transmit queue by default, however WAN
+networks sometimes use bigger values (20 to 100), to utilize the line better
+by large traffic (though the line delay increases because of more packets
+join the queue).
+
+# ifconfig comx0 txqueuelen 50
+
+This option is only supported by the ifconfig command of the later 
+distributions, which came with 2.2 kernels, such as RedHat 6.1 or Debian 2.2.
+
+You can download a newer netbase packet from 
+http://www.debian.org/~rcw/2.2/netbase/ for Debian 2.1, which has a new
+ifconfig. You can get further information about using 2.2 kernel with
+Debian 2.1 from http://www.debian.org/releases/stable/running-kernel-2.2
+
+-----------------------------------------------------------------
+
+The SliceCom LEDs:
+
+red	- on, if the interface is unconfigured, or it gets Remote Alarm-s
+green	- on, if the board finds frame-sync in the received signal 	
+
+A bit more detailed:
+
+red:	green:	meaning:
+
+-	-	no frame-sync, no signal received, or signal SNAFU.
+-	on	"Everything is OK"
+on	on	Recepion is ok, but the remote end sends Remote Alarm
+on	-	The interface is unconfigured
+
+-----------------------------------------------------------------
+
+A more detailed description of the hardware setting options:
+
+The general and the protocol layer options described in the 'comx.txt' file
+apply to the SliceCom as well, I only summarize the SliceCom hardware specific
+settings below.
+
+The '/proc/comx' configuring interface:
+
+An interface directory should be created for every timeslot group with
+'mkdir', e,g: 'comx0', 'comx1' etc. The timeslots can be assigned here to the
+specific interface. The Cisco-like naming convention (serial3:1 - first
+timeslot group of the 3rd. board) can't be used here, because these mean IP
+aliasing in Linux.
+
+You can give any meaningful name to keep the configuration clear; 
+e.g: 'comx0.1', 'comx0.2', 'comx1.1', comx1.2', if you have two boards
+with two interfaces each.
+
+Settings, which apply to the board:
+
+Neither 'io' nor 'irq' settings required, the driver uses the resources
+given by the PCI BIOS.
+
+comx0/boardnum	- board number of the SliceCom in the PC (using the 'natural'
+		PCI order) as listed in '/proc/pci' or the output of the
+	 	'lspci' command, generally the slots nearer to the motherboard
+		PCI driver chips have the lower numbers.
+		
+		Default: 0 (the counting starts with 0)
+
+Though the options below are to be set on a single interface, they apply to the
+whole board. The restriction, to use them on 'UP' interfaces, is because the 
+command sequence below could lead to unpredicable results.
+
+	# echo 0        >boardnum
+	# echo internal >clock_source
+	# echo 1        >boardnum
+
+The sequence would set the clock source of board 0.
+
+These settings will persist after all the interfaces are cleared, but are
+cleared when the driver module is unloaded and loaded again.
+
+comx0/clock_source - source of the transmit clock
+	Usage:
+
+	# echo line     >/proc/comx/comx0/clock_source
+	# echo internal >/proc/comx/comx0/clock_source
+
+	line	- The Tx clock is being decoded if the input data stream,
+		if no clock seen on the input, then the board will use it's
+		own clock generator.
+
+	internal - The Tx clock is supplied by the builtin clock generator. 	
+
+	Default: line
+
+	Normally, the telecommunication company's end device (the HDSL
+	modem) provides the Tx clock, that's why 'line' is the default.
+
+comx0/framing	- Switching CRC4 off/on
+
+	CRC4: 16 PCM frames (The 32 64Kibit channels are multiplexed into a
+	PCM frame, nothing to do with HDLC frames) are divided into 2x8
+	groups, each group has a 4 bit CRC.
+
+	# echo crc4	>/proc/comx/comx0/framing
+	# echo no-crc4	>/proc/comx/comx0/framing
+
+	Default is 'crc4', the Hungarian MATAV lines behave like this. 
+	The traffic generally passes if this setting on both ends don't match.
+
+comx0/linecode	- Setting the line coding
+
+	# echo hdb3	>/proc/comx/comx0/linecode
+	# echo ami	>/proc/comx/comx0/linecode
+
+	Default a 'hdb3', MATAV lines use this.
+	
+	(AMI coding is rarely used with E1 lines). Frame sync may occur, if
+	this setting doesn't match the other end's, but CRC4 and data errors
+	will come, which will result in CRC errors on HDLC/SyncPPP level. 
+
+comx0/reg	- direct access to the board's MUNICH (reg) and FALC (lbireg)
+comx0/lbireg	circuit's registers  
+
+	# echo >reg 0x04 0x0	- write 0 to register 4
+	# echo >reg 0x104	- write the contents of register 4 with
+				printk() to syslog
+
+WARNING! These are only for development purposes, messing with this will
+	result much trouble!
+
+comx0/loopback - Places a loop to the board's G.703 signals
+
+	# echo none   >/proc/comx/comx0/loopback
+	# echo local  >/proc/comx/comx0/loopback
+	# echo remote >/proc/comx/comx0/loopback
+
+	none   - normal operation, no loop
+	local  - the board receives it's own output
+	remote - the board sends the received data to the remote side
+
+	Default: none
+
+-----------------------------------------------------------------
+
+Interface (channel group in Cisco terms) settings: 
+
+comx0/timeslots	- which timeslots belong to the given interface
+
+	Setting:
+
+	# echo '1 5 2 6 7 8' >/proc/comx/comx0/timeslots
+
+	# cat /proc/comx/comx0/timeslots
+	1 2 5 6 7 8 
+	#
+
+	Finding a timeslot: 
+
+	# grep ' 4' /proc/comx/comx*/timeslots
+	/proc/comx/comx0/timeslots:1 3 4 5 6
+	#
+
+	The timeslots can be in any order, '1 2 3' is the same as '1 3 2'.
+
+	The interface has to be DOWN during the setting ('ifconfig comx0
+	down'), but the other interfaces could operate normally.
+
+	The driver checks if the assigned timeslots are vacant, if not, then
+	the setting won't be applied.
+
+	The timeslot values are treated as decimal numbers, not to misunderstand
+	values of 08, 09 form.
+
+-----------------------------------------------------------------
+
+Checking the interface and board status:
+
+- Lines beginning with ' ' (space) belong to the original output, the lines
+which begin with '//' are the comments.
+
+ papaya:~$ cat /proc/comx/comx1/status
+ Interface administrative status is UP, modem status is UP, protocol is UP
+ Modem status changes: 0, Transmitter status is IDLE, tbusy: 0
+ Interface load (input): 978376 / 947808 / 951024 bits/s (5s/5m/15m)
+               (output): 978376 / 947848 / 951024 bits/s (5s/5m/15m)
+ Debug flags: none
+ RX errors: len: 22, overrun: 1, crc: 0, aborts: 0
+            buffer overrun: 0, pbuffer overrun: 0
+ TX errors: underrun: 0
+ Line keepalive (value: 10) status UP [0]
+
+// The hardware specific part starts here:
+ Controller status:
+         No alarms
+
+// Alarm: 
+//
+// No alarms - Everything OK
+//
+// LOS  - Loss Of Signal - No signal sensed on the input
+// AIS  - Alarm Indication Signal - The remot side sends '11111111'-s, 
+//	it tells, that there's an error condition, or it's not
+//	initialised.
+// AUXP - Auxiliary Pattern Indication - 01010101.. received.
+// LFA  - Loss of Frame Alignment - no frame sync received.
+// RRA  - Receive Remote Alarm - the remote end's OK, but singnals error cond.
+// LMFA - Loss of CRC4 Multiframe Alignment - no CRC4 multiframe sync.
+// NMF  - No Multiframe alignment Found after 400 msec - no such alarm using
+//	no-crc4 or crc4 framing, see below.
+//
+// Other possible error messages:
+//
+// Transmit Line Short - the board felt, that it's output is short-circuited,
+// 	so it switched the transmission off. (The board can't definitely tell,
+//	that it's output is short-circuited.)
+
+// Chained list of the received packets, for debug purposes:
+
+ Rx ring:
+         rafutott: 0
+         lastcheck: 50845731, jiffies: 51314281
+         base: 017b1858
+         rx_desc_ptr: 0
+         rx_desc_ptr: 017b1858
+         hw_curr_ptr: 017b1858
+         06040000 017b1868 017b1898 c016ff00
+         06040000 017b1878 017b1e9c c016ff00
+         46040000 017b1888 017b24a0 c016ff00
+         06040000 017b1858 017b2aa4 c016ff00
+
+// All the interfaces using the board: comx1, using the 1,2,...16 timeslots,
+// comx2, using timeslot 17, etc.
+
+ Interfaces using this board: (channel-group, interface, timeslots)
+          0 comx1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+          1 comx2: 17
+          2 comx3: 18
+          3 comx4: 19
+          4 comx5: 20
+          5 comx6: 21
+          6 comx7: 22
+          7 comx8: 23
+          8 comx9: 24
+          9 comx10: 25
+         10 comx11: 26
+         11 comx12: 27
+         12 comx13: 28
+         13 comx14: 29
+         14 comx15: 30
+         15 comx16: 31
+
+// The number of events handled by the driver during an interrupt cycle:
+
+ Interrupt work histogram:
+ hist[ 0]:        0 hist[ 1]:        2 hist[ 2]:    18574 hist[ 3]:       79
+ hist[ 4]:       14 hist[ 5]:        1 hist[ 6]:        0 hist[ 7]:        1
+ hist[ 8]:        0 hist[ 9]:        7
+
+// The number of packets to send in the Tx ring, when a new one arrived:
+
+ Tx ring histogram:
+ hist[ 0]:     2329 hist[ 1]:        0 hist[ 2]:        0 hist[ 3]:        0
+
+// The error counters of the E1 interface, according to the RFC2495,
+// (similar to the Cisco "show controllers e1" command's output:
+// http://www.cisco.com/univercd/cc/td/doc/product/software/ios11/rbook/rinterfc.htm#xtocid25669126)
+
+Data in current interval (91 seconds elapsed):
+   9516 Line Code Violations, 65 Path Code Violations, 2 E-Bit Errors
+   0 Slip Secs, 2 Fr Loss Secs, 2 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 11 Unavail Secs
+Data in Interval 1 (15 minutes):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 4 intervals (1 hour):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 96 intervals (24 hours):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+
+-----------------------------------------------------------------
+
+Some unique options, (may get into the driver later):
+Treat them very carefully, these can cause much trouble!
+
+	modified CRC-4, for improved interworking of CRC-4 and non-CRC-4
+	devices: (see page 107 and g706 Annex B)
+		lbireg[ 0x1b ] |= 0x08
+		lbireg[ 0x1c ] |= 0xc0
+
+	- The NMF - 'No Multiframe alignment Found after 400 msec' alarm 
+	comes into account.
+
+	FALC - the line driver chip.
+	local loop - I hear my transmission back.
+	remote loop - I echo the remote transmission back.
+
+	Something useful for finding errors:
+	
+		- local loop for timeslot 1 in the FALC chip:
+
+	# echo >lbireg 0x1d 0x21
+
+		- Swithing the loop off:
+
+	# echo >lbireg 0x1d 0x00
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/networking/vortex.txt linux/Documentation/networking/vortex.txt
--- linux.orig/Documentation/networking/vortex.txt	2001-08-12 19:27:36.000000000 +0000
+++ linux/Documentation/networking/vortex.txt	2002-08-01 06:42:35.000000000 +0000
@@ -117,6 +117,12 @@
   will force full-duplex 100base-TX, rather than allowing the usual
   autonegotiation.
 
+global_options=N
+
+  Sets the `options' parameter for all 3c59x NICs in the machine. 
+  Entries in the `options' array above will override any setting of
+  this.
+
 full_duplex=N1,N2,N3...
 
   Similar to bit 9 of 'options'.  Forces the corresponding card into
@@ -126,6 +132,11 @@
   In fact, please don't use this at all! You're better off getting
   autonegotiation working properly.
 
+global_full_duplex=N1
+
+  Sets full duplex mode for all 3c59x NICs in the machine.  Entries
+  in the `full_duplex' array above will override any setting of this.
+
 flow_ctrl=N1,N2,N3...
 
   Use 802.3x MAC-layer flow control.  The 3com cards only support the
@@ -211,6 +222,12 @@
   Becker's `ether-wake' application may be used to wake suspended
   machines.
 
+  Also enables the NIC's power management support.
+
+global_enable_wol=N
+
+  Sets enable_wol mode for all 3c59x NICs in the machine.  Entries in
+  the `enable_wol' array above will override any setting of this.
 
 Media selection
 ---------------
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/pci.txt linux/Documentation/pci.txt
--- linux.orig/Documentation/pci.txt	2001-12-21 17:41:53.000000000 +0000
+++ linux/Documentation/pci.txt	2002-08-01 06:42:43.000000000 +0000
@@ -156,6 +156,11 @@
 which enables the bus master bit in PCI_COMMAND register and also fixes
 the latency timer value if it's set to something bogus by the BIOS.
 
+   If you want to use the PCI Memory-Write-Invalidate transaction,
+call pci_set_mwi().  This enables bit PCI_COMMAND bit for Mem-Wr-Inval
+and also ensures that the cache line size register is set correctly.
+Make sure to check the return value of pci_set_mwi(), not all architectures
+may support Memory-Write-Invalidate.
 
 4. How to access PCI config space
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -202,6 +207,8 @@
 pci_resource_len()		Returns the byte length of a PCI region
 pci_set_drvdata()		Set private driver data pointer for a pci_dev
 pci_get_drvdata()		Return private driver data pointer for a pci_dev
+pci_set_mwi()			Enable Memory-Write-Invalidate transactions.
+pci_clear_mwi()			Disable Memory-Write-Invalidate transactions.
 
 
 7. Miscellaneous hints
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/power/pci.txt linux/Documentation/power/pci.txt
--- linux.orig/Documentation/power/pci.txt	2001-06-28 21:58:05.000000000 +0000
+++ linux/Documentation/power/pci.txt	2002-08-01 06:42:37.000000000 +0000
@@ -63,7 +63,7 @@
 callbacks. This currently takes place only during APM state transitions.
 
 Upon going to sleep, the PCI subsystem walks its device tree twice. Both times, it does
-a depth first walk of the device tree. The first walk saves  each of the device's state 
+a depth first walk of the device tree. The first walk saves each of the device's state 
 and checks for devices that will prevent the system from entering a global power state. 
 The next walk then places the devices in a low power state.
 
@@ -104,7 +104,7 @@
 -----------------
 
 Usage:
-	pci_restore_state(dev,buffer);
+	pci_restore_state(dev, buffer);
 
 Description:
 	Restore previously saved config space. (First 64 bytes only);
@@ -117,7 +117,7 @@
 -------------------
 
 Usage:
-	pci_set_power_state(dev,state);
+	pci_set_power_state(dev, state);
 
 Description:
 	Transition device to low power state using PCI PM Capabilities registers.
@@ -132,7 +132,7 @@
 ---------------
 
 Usage:
-	pci_enable_wake(dev,state,enable);
+	pci_enable_wake(dev, state, enable);
 
 Description:
 	Enable device to generate PME# during low power state using PCI PM 
@@ -155,7 +155,7 @@
 struct pci_driver:
 
         int  (*save_state) (struct pci_dev *dev, u32 state);
-        int  (*suspend)(struct pci_dev *dev, u32 state);
+        int  (*suspend) (struct pci_dev *dev, u32 state);
         int  (*resume) (struct pci_dev *dev);
         int  (*enable_wake) (struct pci_dev *dev, u32 state, int enable);
 
@@ -178,7 +178,7 @@
 
 The driver can also interpret this function as a notification that it may be entering
 a sleep state in the near future. If it knows that the device cannot enter the 
-requested state, either because of lack of support for it, or because the devices is 
+requested state, either because of lack of support for it, or because the device is 
 middle of some critical operation, then it should fail.
 
 This function should not be used to set any state in the device or the driver because
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/scsi-generic.txt linux/Documentation/scsi-generic.txt
--- linux.orig/Documentation/scsi-generic.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/scsi-generic.txt	2002-08-01 06:42:31.000000000 +0000
@@ -30,7 +30,7 @@
 =======================
 The most recent documentation of the sg driver is kept at the Linux
 Documentation Project's (LDP) site: 
-http://www.linuxdoc.org/HOWTO/SCSI-Generic-HOWTO
+http://www.tldp.org/HOWTO/SCSI-Generic-HOWTO
 This describes the sg version 3 driver found in the lk 2.4 series.
 The LDP renders documents in single and multiple page HTML, postscript
 and pdf. This document can also be found at:
@@ -51,7 +51,7 @@
 can be found at the top of the /usr/src/linux/drivers/scsi/sg.c file.
 
 A more general description of the Linux SCSI subsystem of which sg is a 
-part can be found at http://www.linuxdoc.org/HOWTO/SCSI-2.4-HOWTO .
+part can be found at http://www.tldp.org/HOWTO/SCSI-2.4-HOWTO .
 
 
 Example code and utilities
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/scsi.txt linux/Documentation/scsi.txt
--- linux.orig/Documentation/scsi.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/scsi.txt	2002-08-01 06:42:31.000000000 +0000
@@ -2,7 +2,7 @@
 ============================
 The Linux Documentation Project (LDP) maintains a document describing
 the SCSI subsystem in the Linux kernel (lk) 2.4 series. See:
-http://www.linuxdoc.org/HOWTO/SCSI-2.4-HOWTO . The LDP has single
+http://www.tldp.org/HOWTO/SCSI-2.4-HOWTO . The LDP has single
 and multiple page HTML renderings as well as postscript and pdf.
 It can also be found at http://www.torque.net/scsi/SCSI-2.4-HOWTO .
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sonypi.txt linux/Documentation/sonypi.txt
--- linux.orig/Documentation/sonypi.txt	2002-02-25 19:37:51.000000000 +0000
+++ linux/Documentation/sonypi.txt	2002-08-01 06:42:29.000000000 +0000
@@ -36,14 +36,14 @@
 driver and the ACPI BIOS, because Sony doesn't agree to release any programming
 specs for its laptops. If someone convinces them to do so, drop me a note.
 
-Module options:
+Driver options:
 ---------------
 
 Several options can be passed to the sonypi driver, either by adding them
 to /etc/modules.conf file, when the driver is compiled as a module or by
 adding the following to the kernel command line (in your bootloader):
 
-	sonypi=minor[[[[,camera],fnkeyinit],verbose],compat]
+	sonypi=minor[,verbose[,fnkeyinit[,camera[,compat[,nojogdial]]]]]
 
 where:
 
@@ -71,6 +71,9 @@
 			(prior to version 1.5) and does not work anymore,
 			add this option and report to the author.
 
+	nojogdial:	gives more accurate PKEY events on those Vaio models
+			which don't have a jogdial (like the FX series).
+
 Module use:
 -----------
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sound/OPL3-SA2 linux/Documentation/sound/OPL3-SA2
--- linux.orig/Documentation/sound/OPL3-SA2	2001-07-18 14:14:01.000000000 +0000
+++ linux/Documentation/sound/OPL3-SA2	2002-08-01 06:42:31.000000000 +0000
@@ -65,7 +65,7 @@
 ------------
 
 In previous kernels (2.2.x), some configuration was required to
-get the driver to talk to the card.  Being the new millenium and
+get the driver to talk to the card.  Being the new millennium and
 all, the 2.4.x kernels now support auto-configuration if ISA PnP
 support is configured in.  Theoretically, the driver even supports
 having more than one card in this case.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sound/PAS16 linux/Documentation/sound/PAS16
--- linux.orig/Documentation/sound/PAS16	2001-04-12 02:02:27.000000000 +0000
+++ linux/Documentation/sound/PAS16	2002-08-01 06:42:48.000000000 +0000
@@ -71,7 +71,7 @@
   interrupt and DMA channel), because you will be asked for it.
 
   You want to read the Sound-HOWTO, available from
-  http://www.linuxdoc.org/docs.html#howto . General information
+  http://www.tldp.org/docs.html#howto . General information
   about the modular sound system is contained in the files
   Documentation/sound/Introduction. The file
   Documentation/sound/README.OSS contains some slightly outdated but
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sound/README.OSS linux/Documentation/sound/README.OSS
--- linux.orig/Documentation/sound/README.OSS	2001-06-12 17:56:11.000000000 +0000
+++ linux/Documentation/sound/README.OSS	2002-08-01 06:42:29.000000000 +0000
@@ -542,7 +542,7 @@
 
 	SoftOSS keeps the samples loaded on the system's RAM so much RAM is
 	required. SoftOSS should never be used on machines with less than 16 MB
-	of RAM since this is potentially dangerous (you may accidently run out
+	of RAM since this is potentially dangerous (you may accidentally run out
 	of memory which probably crashes the machine). 
 
 	SoftOSS implements the wave table API originally designed for GUS. For
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sound/rme96xx linux/Documentation/sound/rme96xx
--- linux.orig/Documentation/sound/rme96xx	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/sound/rme96xx	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,767 @@
+Beta release of the rme96xx (driver for RME 96XX cards like the 
+"Hammerfall" and the "Hammerfall light") 
+
+Important: The driver module has to be installed on a freshly rebooted system, 
+otherwise the driver might not be able to acquire its buffers.
+
+features:
+
+ - OSS programming interface (i.e. runs with standard OSS soundsoftware) 
+ - OSS/Multichannel interface (OSS multichannel is done by just aquiring
+   more than 2 channels). The driver does not use more than one device 
+   ( yet .. this feature may be implemented later ) 
+ - more than one RME card supported
+
+The driver uses a specific multichannel interface, which I will document
+when the driver gets stable. (take a look at the defines in rme96xx.h,
+which adds blocked multichannel formats i.e instead of 
+lrlrlrlr --> llllrrrr  etc.
+
+Use the "rmectrl" programm to look at the status of the card .. 
+or use xrmectrl, a GUI interface for the ctrl program.
+
+What you can do with the rmectrl program is to set the stereo device for
+OSS emulation (e.g. if you use SPDIF out).
+
+You do:
+
+./ctrl offset 24 24
+
+which makes the stereo device use channels 25 and 26.
+
+Guenter Geiger <geiger@epy.co.at> 
+               
+copy the first part of the attached source code into rmectrl.c
+and the  second part into xrmectrl (or get the program from
+http://gige.xdv.org/pages/soft/pages/rme)
+
+to compile: gcc -o rmectrl rmectrl.c
+------------------------------ snip ------------------------------------
+ 
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+#include <linux/soundcard.h>
+#include <math.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include "rme96xx.h"
+
+/*
+  remctrl.c
+  (C) 2000 Guenter Geiger <geiger@debian.org>
+  HP20020201 - Heiko Purnhagen <purnhage@tnt.uni-hannover.de>
+*/
+
+/* # define DEVICE_NAME "/dev/mixer" */
+# define DEVICE_NAME "/dev/mixer1"
+
+
+void usage(void)
+{
+     fprintf(stderr,"usage: rmectrl [/dev/mixer<n>] [command [options]]\n\n");
+     fprintf(stderr,"where command is one of:\n");
+     fprintf(stderr,"  help                       show this help\n");
+     fprintf(stderr,"  status                     show status bits\n");
+     fprintf(stderr,"  control                    show control bits\n");
+     fprintf(stderr,"  mix                        show mixer/offset status\n");
+     fprintf(stderr,"  master <n>                 set sync master\n");
+     fprintf(stderr,"  pro <n>                    set spdif out pro\n");
+     fprintf(stderr,"  emphasis <n>               set spdif out emphasis\n");
+     fprintf(stderr,"  dolby <n>                  set spdif out no audio\n");
+     fprintf(stderr,"  optout <n>                 set spdif out optical\n");
+     fprintf(stderr,"  wordclock <n>              set sync wordclock\n");
+     fprintf(stderr,"  spdifin <n>                set spdif in (0=optical,1=coax,2=intern)\n");
+     fprintf(stderr,"  syncref <n>                set sync source (0=ADAT1,1=ADAT2,2=ADAT3,3=SPDIF)\n");
+     fprintf(stderr,"  adat1cd <n>                set ADAT1 on internal CD\n");
+     fprintf(stderr,"  offset <devnr> <in> <out>  set dev (0..3) offset (0..25)\n");
+     exit(-1);
+}
+
+
+int main(int argc, char* argv[])
+{
+     int cards;
+     int ret;
+     int i;
+     double ft;
+     int fd, fdwr;
+     int param,orig;
+     rme_status_t stat;
+     rme_ctrl_t ctrl;
+     char *device;
+     int argidx;
+
+     if (argc < 2)
+	  usage();
+
+     if (*argv[1]=='/') {
+	  device = argv[1];
+	  argidx = 2;
+     }
+     else {
+	  device = DEVICE_NAME;
+	  argidx = 1;
+     }
+
+     fprintf(stdout,"mixer device %s\n",device);
+     if ((fd = open(device,O_RDONLY)) < 0) {
+	  fprintf(stdout,"opening device failed\n");
+	  exit(-1);
+     }
+
+     if ((fdwr = open(device,O_WRONLY)) < 0) {
+	  fprintf(stdout,"opening device failed\n");
+	  exit(-1);
+     }
+
+     if (argc < argidx+1)
+	  usage();
+	  
+     if (!strcmp(argv[argidx],"help")) 
+        usage();
+     if (!strcmp(argv[argidx],"-h")) 
+        usage();
+     if (!strcmp(argv[argidx],"--help")) 
+        usage();
+
+     if (!strcmp(argv[argidx],"status")) {
+	  ioctl(fd,SOUND_MIXER_PRIVATE2,&stat);
+	  fprintf(stdout,"stat.irq %d\n",stat.irq);
+	  fprintf(stdout,"stat.lockmask %d\n",stat.lockmask);
+	  fprintf(stdout,"stat.sr48 %d\n",stat.sr48);
+	  fprintf(stdout,"stat.wclock %d\n",stat.wclock);
+	  fprintf(stdout,"stat.bufpoint %d\n",stat.bufpoint);
+	  fprintf(stdout,"stat.syncmask %d\n",stat.syncmask);
+	  fprintf(stdout,"stat.doublespeed %d\n",stat.doublespeed);
+	  fprintf(stdout,"stat.tc_busy %d\n",stat.tc_busy);
+	  fprintf(stdout,"stat.tc_out %d\n",stat.tc_out);
+	  fprintf(stdout,"stat.crystalrate %d (0=64k 3=96k 4=88.2k 5=48k 6=44.1k 7=32k)\n",stat.crystalrate);
+	  fprintf(stdout,"stat.spdif_error %d\n",stat.spdif_error);
+	  fprintf(stdout,"stat.bufid %d\n",stat.bufid);
+	  fprintf(stdout,"stat.tc_valid %d\n",stat.tc_valid);
+	  exit (0);
+     }
+	 
+     if (!strcmp(argv[argidx],"control")) {
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  fprintf(stdout,"ctrl.start %d\n",ctrl.start);
+	  fprintf(stdout,"ctrl.latency %d (0=64 .. 7=8192)\n",ctrl.latency);
+	  fprintf(stdout,"ctrl.master %d\n",ctrl.master);
+	  fprintf(stdout,"ctrl.ie %d\n",ctrl.ie);
+	  fprintf(stdout,"ctrl.sr48 %d\n",ctrl.sr48);
+	  fprintf(stdout,"ctrl.spare %d\n",ctrl.spare);
+	  fprintf(stdout,"ctrl.doublespeed %d\n",ctrl.doublespeed);
+	  fprintf(stdout,"ctrl.pro %d\n",ctrl.pro);
+	  fprintf(stdout,"ctrl.emphasis %d\n",ctrl.emphasis);
+	  fprintf(stdout,"ctrl.dolby %d\n",ctrl.dolby);
+	  fprintf(stdout,"ctrl.opt_out %d\n",ctrl.opt_out);
+	  fprintf(stdout,"ctrl.wordclock %d\n",ctrl.wordclock);
+	  fprintf(stdout,"ctrl.spdif_in %d (0=optical,1=coax,2=intern)\n",ctrl.spdif_in);
+	  fprintf(stdout,"ctrl.sync_ref %d (0=ADAT1,1=ADAT2,2=ADAT3,3=SPDIF)\n",ctrl.sync_ref);
+	  fprintf(stdout,"ctrl.spdif_reset %d\n",ctrl.spdif_reset);
+	  fprintf(stdout,"ctrl.spdif_select %d\n",ctrl.spdif_select);
+	  fprintf(stdout,"ctrl.spdif_clock %d\n",ctrl.spdif_clock);
+	  fprintf(stdout,"ctrl.spdif_write %d\n",ctrl.spdif_write);
+	  fprintf(stdout,"ctrl.adat1_cd %d\n",ctrl.adat1_cd);
+	  exit (0);
+     }
+     
+     if (!strcmp(argv[argidx],"mix")) {
+	  rme_mixer mix;
+	  int i;
+	  
+	  for (i=0; i<4; i++) {
+	       mix.devnr = i;
+	       ioctl(fd,SOUND_MIXER_PRIVATE1,&mix);
+	       if (mix.devnr == i) {
+		    fprintf(stdout,"devnr %d\n",mix.devnr);
+		    fprintf(stdout,"mix.i_offset %2d (0-25)\n",mix.i_offset);
+		    fprintf(stdout,"mix.o_offset %2d (0-25)\n",mix.o_offset);
+	       }
+	  }
+	  exit (0);
+     }
+
+/* the control flags */
+
+     if (argc < argidx+2)
+	  usage();
+	  
+     if (!strcmp(argv[argidx],"master")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("master = %d\n",val);
+	  ctrl.master = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"pro")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("pro = %d\n",val);
+	  ctrl.pro = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"emphasis")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("emphasis = %d\n",val);
+	  ctrl.emphasis = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"dolby")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("dolby = %d\n",val);
+	  ctrl.dolby = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"optout")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("optout = %d\n",val);
+	  ctrl.opt_out = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"wordclock")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("wordclock = %d\n",val);
+	  ctrl.wordclock = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"spdifin")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("spdifin = %d\n",val);
+	  ctrl.spdif_in = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+
+     if (!strcmp(argv[argidx],"syncref")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("syncref = %d\n",val);
+	  ctrl.sync_ref = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+ 
+     if (!strcmp(argv[argidx],"adat1cd")) {
+	  int val = atoi(argv[argidx+1]);
+	  ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+	  printf("adat1cd = %d\n",val);
+	  ctrl.adat1_cd = val;
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+	  exit (0);
+     }
+ 
+/* setting offset */
+
+     if (argc < argidx+4)
+	  usage();
+	  
+     if (!strcmp(argv[argidx],"offset")) {
+	  rme_mixer mix;
+
+	  mix.devnr = atoi(argv[argidx+1]);
+	  
+	  mix.i_offset = atoi(argv[argidx+2]);
+	  mix.o_offset = atoi(argv[argidx+3]);
+	  ioctl(fdwr,SOUND_MIXER_PRIVATE1,&mix);
+	  fprintf(stdout,"devnr %d\n",mix.devnr);
+	  fprintf(stdout,"mix.i_offset to %d\n",mix.i_offset);
+	  fprintf(stdout,"mix.o_offset to %d\n",mix.o_offset);
+	  exit (0);
+     }	 
+
+     usage();
+     exit (0); /* to avoid warning */
+}
+
+
+---------------------------- <snip> --------------------------------
+#!/usr/bin/wish
+
+# xrmectrl
+# (C) 2000 Guenter Geiger <geiger@debian.org>
+# HP20020201 - Heiko Purnhagen <purnhage@tnt.uni-hannover.de>
+
+#set defaults "-relief ridged"
+set CTRLPROG "./rmectrl"
+if {$argc} {
+    set CTRLPROG "$CTRLPROG $argv"
+}
+puts "CTRLPROG $CTRLPROG"
+
+frame .butts
+button .butts.exit -text "Exit" -command "exit" -relief ridge
+#button .butts.state -text "State" -command "get_all" 
+
+pack .butts.exit -side left 
+pack .butts -side bottom 
+
+
+#
+# STATUS 
+#
+
+frame .status
+
+# Sampling Rate
+
+frame .status.sr
+label .status.sr.text -text "Sampling Rate" -justify left
+radiobutton .status.sr.441 -selectcolor red -text "44.1 kHz" -width 10 -anchor nw -variable srate -value 44100 -font times
+radiobutton .status.sr.480 -selectcolor red -text "48 kHz" -width 10 -anchor nw -variable srate -value 48000 -font times
+radiobutton .status.sr.882 -selectcolor red -text "88.2 kHz" -width 10 -anchor nw -variable srate -value 88200 -font times
+radiobutton .status.sr.960 -selectcolor red -text "96 kHz" -width 10 -anchor nw  -variable srate -value 96000 -font times
+
+pack .status.sr.text .status.sr.441 .status.sr.480 .status.sr.882 .status.sr.960 -side top -padx 3
+
+# Lock
+
+frame .status.lock
+label .status.lock.text -text "Lock" -justify left
+checkbutton .status.lock.adat1 -selectcolor red -text "ADAT1" -anchor nw -width 10 -variable adatlock1 -font times
+checkbutton .status.lock.adat2 -selectcolor red -text "ADAT2" -anchor nw -width 10 -variable adatlock2 -font times
+checkbutton .status.lock.adat3 -selectcolor red -text "ADAT3" -anchor nw -width 10 -variable adatlock3 -font times
+
+pack .status.lock.text .status.lock.adat1 .status.lock.adat2 .status.lock.adat3 -side top -padx 3 
+
+# Sync
+
+frame .status.sync
+label .status.sync.text -text "Sync" -justify left
+checkbutton .status.sync.adat1 -selectcolor red -text "ADAT1" -anchor nw -width 10 -variable adatsync1 -font times
+checkbutton .status.sync.adat2 -selectcolor red -text "ADAT2" -anchor nw -width 10 -variable adatsync2 -font times
+checkbutton .status.sync.adat3 -selectcolor red -text "ADAT3" -anchor nw -width 10 -variable adatsync3 -font times
+
+pack .status.sync.text .status.sync.adat1 .status.sync.adat2 .status.sync.adat3 -side top -padx 3 
+
+# Timecode
+
+frame .status.tc
+label .status.tc.text -text "Timecode" -justify left
+checkbutton .status.tc.busy -selectcolor red -text "busy" -anchor nw -width 10 -variable tcbusy -font times
+checkbutton .status.tc.out -selectcolor red -text "out" -anchor nw -width 10 -variable tcout -font times
+checkbutton .status.tc.valid -selectcolor red -text "valid" -anchor nw -width 10 -variable tcvalid -font times
+
+pack .status.tc.text .status.tc.busy .status.tc.out .status.tc.valid -side top -padx 3 
+
+# SPDIF In
+
+frame .status.spdif
+label .status.spdif.text -text "SPDIF In" -justify left
+label .status.spdif.sr -text "--.- kHz" -anchor n -width 10 -font times
+checkbutton .status.spdif.error -selectcolor red -text "Input Lock" -anchor nw -width 10 -variable spdiferr -font times
+
+pack .status.spdif.text .status.spdif.sr .status.spdif.error -side top -padx 3 
+
+pack .status.sr .status.lock .status.sync .status.tc .status.spdif -side left -fill x -anchor n -expand 1
+
+
+#
+# CONTROL 
+#
+
+proc setprof {} {
+    global CTRLPROG
+    global spprof
+    exec $CTRLPROG pro $spprof
+}
+
+proc setemph {} {
+    global CTRLPROG
+    global spemph
+    exec $CTRLPROG emphasis $spemph
+}
+
+proc setnoaud {} {
+    global CTRLPROG
+    global spnoaud
+    exec $CTRLPROG dolby $spnoaud
+}
+
+proc setoptical {} {
+    global CTRLPROG
+    global spoptical
+    exec $CTRLPROG optout $spoptical
+}
+
+proc setspdifin {} {
+    global CTRLPROG
+    global spdifin
+    exec $CTRLPROG spdifin [expr $spdifin - 1]
+}
+
+proc setsyncsource {} {
+    global CTRLPROG
+    global syncsource
+    exec $CTRLPROG syncref [expr $syncsource -1]
+}
+
+
+proc setmaster {} {
+    global CTRLPROG
+    global master
+    exec $CTRLPROG master $master
+}
+
+proc setwordclock {} {
+    global CTRLPROG
+    global wordclock
+    exec $CTRLPROG wordclock $wordclock
+}
+
+proc setadat1cd {} {
+    global CTRLPROG
+    global adat1cd
+    exec $CTRLPROG adat1cd $adat1cd
+}
+
+
+frame .control
+
+# SPDIF In & SPDIF Out
+
+
+frame .control.spdif
+
+frame .control.spdif.in
+label .control.spdif.in.text -text "SPDIF In" -justify left
+radiobutton .control.spdif.in.input1 -text "Optical" -anchor nw -width 13 -variable spdifin -value 1 -command setspdifin -selectcolor blue -font times
+radiobutton .control.spdif.in.input2 -text "Coaxial" -anchor nw -width 13 -variable spdifin -value 2 -command setspdifin -selectcolor blue -font times
+radiobutton .control.spdif.in.input3 -text "Intern " -anchor nw -width 13 -variable spdifin -command setspdifin -value 3 -selectcolor blue -font times
+
+checkbutton .control.spdif.in.adat1cd -text "ADAT1 Intern" -anchor nw -width 13 -variable adat1cd -command setadat1cd -selectcolor blue -font times
+
+pack .control.spdif.in.text .control.spdif.in.input1 .control.spdif.in.input2 .control.spdif.in.input3 .control.spdif.in.adat1cd
+
+label .control.spdif.space
+
+frame .control.spdif.out
+label .control.spdif.out.text -text "SPDIF Out" -justify left
+checkbutton .control.spdif.out.pro -text "Professional" -anchor nw -width 13 -variable spprof -command setprof -selectcolor blue -font times
+checkbutton .control.spdif.out.emphasis -text "Emphasis" -anchor nw -width 13 -variable spemph -command setemph -selectcolor blue -font times
+checkbutton .control.spdif.out.dolby -text "NoAudio" -anchor nw -width 13 -variable spnoaud -command setnoaud -selectcolor blue -font times
+checkbutton .control.spdif.out.optout -text "Optical Out" -anchor nw -width 13 -variable spoptical -command setoptical -selectcolor blue -font times
+
+pack .control.spdif.out.optout .control.spdif.out.dolby .control.spdif.out.emphasis .control.spdif.out.pro .control.spdif.out.text -side bottom
+
+pack .control.spdif.in .control.spdif.space .control.spdif.out -side top -fill y -padx 3 -expand 1
+
+# Sync Mode & Sync Source
+
+frame .control.sync
+frame .control.sync.mode
+label .control.sync.mode.text -text "Sync Mode" -justify left
+checkbutton .control.sync.mode.master -text "Master" -anchor nw -width 13 -variable master -command setmaster -selectcolor blue -font times
+checkbutton .control.sync.mode.wc -text "Wordclock" -anchor nw -width 13 -variable wordclock -command setwordclock -selectcolor blue -font times
+
+pack .control.sync.mode.text .control.sync.mode.master .control.sync.mode.wc
+
+label .control.sync.space
+
+frame .control.sync.src
+label .control.sync.src.text -text "Sync Source" -justify left
+radiobutton .control.sync.src.input1 -text "ADAT1" -anchor nw -width 13 -variable syncsource -value 1 -command setsyncsource -selectcolor blue -font times
+radiobutton .control.sync.src.input2 -text "ADAT2" -anchor nw -width 13 -variable syncsource -value 2 -command setsyncsource -selectcolor blue -font times
+radiobutton .control.sync.src.input3 -text "ADAT3" -anchor nw -width 13 -variable syncsource -command setsyncsource -value 3 -selectcolor blue -font times
+radiobutton .control.sync.src.input4 -text "SPDIF" -anchor nw -width 13 -variable syncsource -command setsyncsource -value 4 -selectcolor blue -font times
+
+pack .control.sync.src.input4 .control.sync.src.input3 .control.sync.src.input2 .control.sync.src.input1 .control.sync.src.text -side bottom
+
+pack .control.sync.mode .control.sync.space .control.sync.src -side top -fill y -padx 3 -expand 1
+
+label .control.space -text "" -width 10
+
+# Buffer Size
+
+frame .control.buf
+label .control.buf.text -text "Buffer Size (Latency)" -justify left
+radiobutton .control.buf.b1 -selectcolor red -text "64 (1.5 ms)" -width 13 -anchor nw -variable ssrate -value 1 -font times
+radiobutton .control.buf.b2 -selectcolor red -text "128 (3 ms)" -width 13 -anchor nw -variable ssrate -value 2 -font times
+radiobutton .control.buf.b3 -selectcolor red -text "256 (6 ms)" -width 13 -anchor nw -variable ssrate -value 3 -font times
+radiobutton .control.buf.b4 -selectcolor red -text "512 (12 ms)" -width 13 -anchor nw -variable ssrate -value 4 -font times
+radiobutton .control.buf.b5 -selectcolor red -text "1024 (23 ms)" -width 13 -anchor nw -variable ssrate -value 5 -font times
+radiobutton .control.buf.b6 -selectcolor red -text "2048 (46 ms)" -width 13 -anchor nw -variable ssrate -value 6 -font times
+radiobutton .control.buf.b7 -selectcolor red -text "4096 (93 ms)" -width 13 -anchor nw -variable ssrate -value 7 -font times
+radiobutton .control.buf.b8 -selectcolor red -text "8192 (186 ms)" -width 13 -anchor nw -variable ssrate -value 8 -font times
+
+pack .control.buf.text .control.buf.b1 .control.buf.b2 .control.buf.b3 .control.buf.b4 .control.buf.b5 .control.buf.b6 .control.buf.b7 .control.buf.b8 -side top -padx 3 
+
+# Offset
+
+frame .control.offset
+
+frame .control.offset.in
+label .control.offset.in.text -text "Offset In" -justify left
+label .control.offset.in.off0 -text "dev\#0: -" -anchor nw -width 10 -font times
+label .control.offset.in.off1 -text "dev\#1: -" -anchor nw -width 10 -font times
+label .control.offset.in.off2 -text "dev\#2: -" -anchor nw -width 10 -font times
+label .control.offset.in.off3 -text "dev\#3: -" -anchor nw -width 10 -font times
+
+pack .control.offset.in.text .control.offset.in.off0 .control.offset.in.off1 .control.offset.in.off2 .control.offset.in.off3
+
+label .control.offset.space
+
+frame .control.offset.out
+label .control.offset.out.text -text "Offset Out" -justify left
+label .control.offset.out.off0 -text "dev\#0: -" -anchor nw -width 10 -font times
+label .control.offset.out.off1 -text "dev\#1: -" -anchor nw -width 10 -font times
+label .control.offset.out.off2 -text "dev\#2: -" -anchor nw -width 10 -font times
+label .control.offset.out.off3 -text "dev\#3: -" -anchor nw -width 10 -font times
+
+pack .control.offset.out.off3 .control.offset.out.off2 .control.offset.out.off1 .control.offset.out.off0 .control.offset.out.text -side bottom
+
+pack .control.offset.in .control.offset.space .control.offset.out -side top -fill y -padx 3 -expand 1
+
+
+pack .control.spdif .control.sync .control.space .control.buf .control.offset -side left -fill both -anchor n -expand 1
+
+
+label .statustext -text Status -justify center -relief ridge
+label .controltext -text Control -justify center -relief ridge
+
+label .statusspace
+label .controlspace
+
+pack .statustext .status .statusspace .controltext .control .controlspace -side top -anchor nw -fill both -expand 1
+
+
+proc get_bit {output sstr} {
+    set idx1 [string last [concat $sstr 1] $output]
+    set idx1 [expr $idx1 != -1]
+    return $idx1
+}
+
+proc get_val {output sstr} {
+    set val [string wordend $output [string last $sstr $output]] 
+    set val [string range $output $val [expr $val+1]]
+    return $val
+}
+
+proc get_val2 {output sstr} {
+    set val [string wordend $output [string first $sstr $output]] 
+    set val [string range $output $val [expr $val+2]]
+    return $val
+}
+
+proc get_control {} {
+    global spprof
+    global spemph
+    global spnoaud
+    global spoptical
+    global spdifin
+    global ssrate
+    global master
+    global wordclock
+    global syncsource
+    global CTRLPROG
+
+    set f [open "| $CTRLPROG control" r+]
+    set ooo [read $f 1000]
+    close $f
+#    puts $ooo
+
+    set spprof [ get_bit $ooo "pro"]
+    set spemph [ get_bit $ooo "emphasis"]
+    set spnoaud [ get_bit $ooo "dolby"]
+    set spoptical [ get_bit $ooo "opt_out"]
+    set spdifin [ expr [ get_val $ooo "spdif_in"] + 1]
+    set ssrate [ expr [ get_val $ooo "latency"] + 1]
+    set master [ expr [ get_val $ooo "master"]]
+    set wordclock [ expr [ get_val $ooo "wordclock"]]
+    set syncsource [ expr [ get_val $ooo "sync_ref"] + 1]
+}
+
+proc get_status {} {
+    global srate
+    global ctrlcom
+    
+    global adatlock1
+    global adatlock2
+    global adatlock3
+
+    global adatsync1
+    global adatsync2
+    global adatsync3
+
+    global tcbusy
+    global tcout
+    global tcvalid
+
+    global spdiferr
+    global crystal
+    global .status.spdif.text
+    global CTRLPROG
+
+
+    set f [open "| $CTRLPROG status" r+]
+    set ooo [read $f 1000]
+    close $f
+#    puts $ooo
+ 
+# samplerate
+
+    set idx1 [string last "sr48 1" $ooo]
+    set idx2 [string last "doublespeed 1" $ooo]
+    if {$idx1 >= 0} {
+	set fact1 48000
+    } else {
+	set fact1 44100
+    }
+    
+    if {$idx2 >= 0} {
+	set fact2 2 
+    } else {
+	set fact2 1 
+    }
+    set srate [expr $fact1 * $fact2]
+#   ADAT lock 
+
+    set val [get_val $ooo lockmask]
+    set adatlock1 0
+    set adatlock2 0
+    set adatlock3 0
+    if {[expr $val & 1]} {
+       set adatlock3 1
+    } 
+    if {[expr $val & 2]} {
+       set adatlock2 1
+    } 
+    if {[expr $val & 4]} {
+       set adatlock1 1
+    } 
+
+#  ADAT sync
+    set val [get_val $ooo syncmask]
+    set adatsync1 0
+    set adatsync2 0
+    set adatsync3 0
+
+    if {[expr $val & 1]} {
+       set adatsync3 1
+    } 
+    if {[expr $val & 2]} {
+       set adatsync2 1
+    } 
+    if {[expr $val & 4]} {
+       set adatsync1 1
+    } 
+
+# TC busy
+
+    set tcbusy [get_bit $ooo "busy"]
+    set tcout [get_bit $ooo "out"]
+    set tcvalid [get_bit $ooo "valid"]
+    set spdiferr [expr [get_bit $ooo "spdif_error"] == 0]
+
+#  000=64kHz, 100=88.2kHz, 011=96kHz  
+#  111=32kHz, 110=44.1kHz, 101=48kHz
+
+    set val [get_val $ooo crystalrate] 
+
+    set crystal "--.- kHz"
+    if {$val == 0} {
+        set crystal "64 kHz"
+    }
+    if {$val == 4} {
+        set crystal "88.2 kHz"
+    }
+    if {$val == 3} {
+        set crystal "96 kHz"
+    }
+    if {$val == 7} {
+        set crystal "32 kHz"
+    }
+    if {$val == 6} {
+        set crystal "44.1 kHz"
+    }
+    if {$val == 5} {
+        set crystal "48 kHz"
+    }
+    .status.spdif.sr configure -text $crystal
+}
+
+proc get_offset {} {
+    global inoffset
+    global outoffset
+    global CTRLPROG
+
+    set f [open "| $CTRLPROG mix" r+]
+    set ooo [read $f 1000]
+    close $f
+#    puts $ooo
+
+    if { [string match "*devnr*" $ooo] } {
+	set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+	set val [get_val2 $ooo i_offset] 
+	.control.offset.in.off0 configure -text "dev\#0: $val"
+	set val [get_val2 $ooo o_offset] 
+	.control.offset.out.off0 configure -text "dev\#0: $val"
+    } else {
+	.control.offset.in.off0 configure -text "dev\#0: -"
+	.control.offset.out.off0 configure -text "dev\#0: -"
+    }
+    if { [string match "*devnr*" $ooo] } {
+	set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+	set val [get_val2 $ooo i_offset] 
+	.control.offset.in.off1 configure -text "dev\#1: $val"
+	set val [get_val2 $ooo o_offset] 
+	.control.offset.out.off1 configure -text "dev\#1: $val"
+    } else {
+	.control.offset.in.off1 configure -text "dev\#1: -"
+	.control.offset.out.off1 configure -text "dev\#1: -"
+    }
+    if { [string match "*devnr*" $ooo] } {
+	set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+	set val [get_val2 $ooo i_offset] 
+	.control.offset.in.off2 configure -text "dev\#2: $val"
+	set val [get_val2 $ooo o_offset] 
+	.control.offset.out.off2 configure -text "dev\#2: $val"
+    } else {
+	.control.offset.in.off2 configure -text "dev\#2: -"
+	.control.offset.out.off2 configure -text "dev\#2: -"
+    }
+    if { [string match "*devnr*" $ooo] } {
+	set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+	set val [get_val2 $ooo i_offset] 
+	.control.offset.in.off3 configure -text "dev\#3: $val"
+	set val [get_val2 $ooo o_offset] 
+	.control.offset.out.off3 configure -text "dev\#3: $val"
+    } else {
+	.control.offset.in.off3 configure -text "dev\#3: -"
+	.control.offset.out.off3 configure -text "dev\#3: -"
+    }
+}
+
+
+proc get_all {} {
+get_status
+get_control
+get_offset
+}
+
+# main
+while {1} {
+  after 200 
+  get_all
+  update
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sysctl/vm.txt linux/Documentation/sysctl/vm.txt
--- linux.orig/Documentation/sysctl/vm.txt	2001-09-10 21:36:25.000000000 +0000
+++ linux/Documentation/sysctl/vm.txt	2002-08-01 06:42:46.000000000 +0000
@@ -21,6 +21,7 @@
 - buffermem
 - freepages
 - kswapd
+- max_map_count
 - overcommit_memory
 - page-cluster
 - pagecache
@@ -170,6 +171,19 @@
 
 ==============================================================
 
+max_map_count:
+
+This file contains the maximum number of memory map areas a
+process may have. Memory map areas are used as a side-effect
+of calling malloc, directly by mmap and mprotect, and also
+when loading shared libraries.
+
+While most applications need less than a thousand maps,
+certain programs, particularly malloc debuggers, may consume 
+lots of them, e.g. up to one or two maps per allocation.
+
+==============================================================
+
 page-cluster:
 
 The Linux VM subsystem avoids excessive disk seeks by reading
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/sysrq.txt linux/Documentation/sysrq.txt
--- linux.orig/Documentation/sysrq.txt	2001-09-18 05:52:35.000000000 +0000
+++ linux/Documentation/sysrq.txt	2002-08-01 06:42:44.000000000 +0000
@@ -153,7 +153,7 @@
 and 4 functions are exported for interface to it: __sysrq_lock_table,
 __sysrq_unlock_table, __sysrq_get_key_op, and __sysrq_put_key_op. The
 functions __sysrq_swap_key_ops and __sysrq_swap_key_ops_nolock are defined
-in the header itself, and the REGISTER and UNREGISTER macros are built fromi
+in the header itself, and the REGISTER and UNREGISTER macros are built from
 these. More complex (and dangerous!) manipulations of the table are possible
 using these functions, but you must be careful to always lock the table before
 you read or write from it, and to unlock it again when you are done. (And of
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/usb/auerswald.txt linux/Documentation/usb/auerswald.txt
--- linux.orig/Documentation/usb/auerswald.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/usb/auerswald.txt	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,30 @@
+		Auerswald USB kernel driver
+		===========================
+
+What is it? What can I do with it?
+==================================
+The auerswald USB kernel driver connects your linux 2.4.x
+system to the auerswald usb-enabled devices.
+
+There are two types of auerswald usb devices:
+a) small PBX systems (ISDN)
+b) COMfort system telephones (ISDN)
+
+The driver installation creates the devices
+/dev/usb/auer0..15. These devices carry a vendor-
+specific protocol. You may run all auerswald java
+software on it. The java software needs a native
+library "libAuerUsbJNINative.so" installed on
+your system. This library is available from
+auerswald and shipped as part of the java software.
+
+You may create the devices with:
+	mknod -m 666 /dev/usb/auer0 c 180 112
+	...
+	mknod -m 666 /dev/usb/auer15 c 180 127
+
+Future plans
+============
+- Connection to ISDN4LINUX (the hisax interface)
+
+The maintainer of this driver is wmues@nexgo.de
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/usb/brlvger.txt linux/Documentation/usb/brlvger.txt
--- linux.orig/Documentation/usb/brlvger.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/usb/brlvger.txt	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,36 @@
+Kernel Driver for the Tieman Voyager Braille Display (USB)
+
+Authors:
+Stéphane Dalton <sdalton@videotron.ca>
+Stéphane Doyon  <s.doyon@videotron.ca>
+
+Version 0.8, April 2002
+
+The brlvger driver supports a Braille display (aka Braille terminal)
+model Voyager from Tieman.
+
+The driver has been in heavy use for about six months now (as of April
+2002) by a very few users (about 3-4), who say it has worked very well
+for them.
+
+We have tested it with a Voyager 44, but it should also support
+the Voyager 70.
+
+This driver implements a character device which allows userspace programs
+access to the braille displays raw functions. You still need a userspace
+program to perform the screen-review functions and control the
+display. Get BRLTTY from http://mielke.cc/brltty/ (version 2.99.8 or
+later). It has a Voyager driver which interfaces with this kernel driver.
+
+The interface is through a character device, major 180, minor 128, called
+"brlvger" under devfs.
+
+Many thanks to the Tieman people: Corand van Strien, Ivar Illing, Daphne
+Vogelaar and Ingrid Vogel. They provided us with a Braille display (as
+well as programming information) so that we could write this driver. They
+replaced the display when it broke and they answered our technical
+questions. It is very motivating when companies take an interest in such
+projects and are so supportive.
+
+Thanks to Andor Demarteau <ademarte@students.cs.uu.nl> who got this whole
+project started and beta-tested all our early buggy attempts.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/usb/ehci.txt linux/Documentation/usb/ehci.txt
--- linux.orig/Documentation/usb/ehci.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/usb/ehci.txt	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,171 @@
+26-Apr-2002
+
+The EHCI driver is used to talk to high speed USB 2.0 devices using
+USB 2.0-capable host controller hardware.  The USB 2.0 standard is
+compatible with the USB 1.1 standard. It defines three transfer speeds:
+
+    - "High Speed" 480 Mbit/sec (60 MByte/sec)
+    - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
+    - "Low Speed" 1.5 Mbit/sec
+
+USB 1.1 only addressed full speed and low speed.  High speed devices
+can be used on USB 1.1 systems, but they slow down to USB 1.1 speeds. 
+
+USB 1.1 devices may also be used on USB 2.0 systems.  When plugged
+into an EHCI controller, they are given to a USB 1.1 "companion"
+controller, which is a OHCI or UHCI controller as normally used with
+such devices.  When USB 1.1 devices plug into USB 2.0 hubs, they
+interact with the EHCI controller through a "Transaction Translator"
+(TT) in the hub, which turns low or full speed transactions into
+high speed "split transactions" that don't waste transfer bandwidth.
+
+At this writing, this driver has been seen to work with implementations
+of EHCI from (in alphabetical order):  Intel, NEC, Philips, and VIA.
+
+At this writing, high speed devices are finally beginning to appear.
+While usb-storage devices have been available for some time (working
+quite speedily on the 2.4 version of this driver), hubs have only
+very recently become available.
+
+Note that USB 2.0 support involves more than just EHCI.  It requires
+other changes to the Linux-USB core APIs, including the hub driver,
+but those changes haven't needed to really change the basic "usbcore"
+APIs exposed to USB device drivers.
+
+- David Brownell
+  <dbrownell@users.sourceforge.net>
+
+
+FUNCTIONALITY
+
+This driver is regularly tested on x86 hardware, and has also been
+used on PPC hardware so big/little endianness issues should be gone.
+It's believed to do all the right PCI magic so that I/O works even on
+systems with interesting DMA mapping issues.
+
+At this writing the driver should comfortably handle all control and bulk
+transfers, including requests to USB 1.1 devices through transaction
+translators (TTs) in USB 2.0 hubs.  However, there some situations where
+the hub driver needs to clear TT error state, which it doesn't yet do.
+
+Interrupt transfer support is newly functional and not yet as robust as
+control and bulk traffic.  As yet there is no support for split transaction
+scheduling for interrupt transfers, which means among other things that
+connecting USB 1.1 hubs, keyboards, and mice to USB 2.0 hubs won't work.
+Connect them to USB 1.1 hubs, or to a root hub.
+
+Isochronous (ISO) transfer support is also newly functional.  No production
+high speed devices are available which would need it (though high quality
+webcams are in the works!).  Note that split transaction support for ISO
+transfers can't share much code with the code for high speed ISO transfers,
+since EHCI represents these with a different data structure.  So for now,
+most USB audio and video devices have the same restrictions as hubs, mice,
+and keyboards:  don't connect them using high speed USB hubs.
+
+The EHCI root hub code should hand off USB 1.1 devices to its companion
+controller.  This driver doesn't need to know anything about those
+drivers; a OHCI or UHCI driver that works already doesn't need to change
+just because the EHCI driver is also present.
+
+There are some issues with power management; suspend/resume doesn't
+behave quite right at the moment.
+
+
+USE BY
+
+Assuming you have an EHCI controller (on a PCI card or motherboard)
+and have compiled this driver as a module, load this like:
+
+    # modprobe ehci-hcd
+
+and remove it by:
+
+    # rmmod ehci-hcd
+
+You should also have a driver for a "companion controller", such as
+"ohci-hcd", "usb-ohci", "usb-uhci", or "uhci".  In case of any trouble
+with the EHCI driver, remove its module and then the driver for that
+companion controller will take over (at lower speed) all the devices
+that were previously handled by the EHCI driver.
+
+Module parameters (pass to "modprobe") include:
+
+    log2_irq_thresh (default 0):
+	Log2 of default interrupt delay, in microframes.  The default
+	value is 0, indicating 1 microframe (125 usec).  Maximum value
+	is 6, indicating 2^6 = 64 microframes.  This controls how often
+	the EHCI controller can issue interrupts.
+
+The EHCI interrupt handler just acknowledges interrupts and schedules
+a tasklet to handle whatever needs handling.  That keeps latencies low,
+no matter how often interrupts are issued.
+
+Device drivers shouldn't care whether they're running over EHCI or not,
+but they may want to check for "usb_device->speed == USB_SPEED_HIGH".
+High speed devices can do things that full speed (or low speed) ones
+can't, such as "high bandwidth" periodic (interrupt or ISO) transfers.
+Also, some values in device descriptors (such as polling intervals for
+periodic transfers) use different encodings when operating at high speed.
+
+
+PERFORMANCE
+
+USB 2.0 throughput is gated by two main factors:  how fast the host
+controller can process requests, and how fast devices can respond to
+them.  The 480 Mbit/sec "raw transfer rate" is obeyed by all devices,
+but aggregate throughput is also affected by issues like delays between
+individual high speed packets, driver intelligence, and of course the
+overall system load.  Latency is also a performance concern.
+
+Bulk transfers are most often used where throughput is an issue.  It's
+good to keep in mind that bulk transfers are always in 512 byte packets,
+and at most 13 of those fit into one USB 2.0 microframe.  Eight USB 2.0
+microframes fit in a USB 1.1 frame; a microframe is 1 msec/8 = 125 usec.
+
+Hardware Performance
+
+At this writing, individual USB 2.0 devices tend to max out at around
+20 MByte/sec transfer rates.  This is of course subject to change;
+and some devices now go faster, while others go slower.
+
+The NEC implementation of EHCI seems to have a hardware bottleneck
+at around 28 MByte/sec aggregate transfer rate.  While this is clearly
+enough for a single device at 20 MByte/sec, putting three such devices
+onto one bus does not get you 60 MByte/sec.  The issue appears to be
+that the controller hardware won't do concurrent USB and PCI access,
+so that it's only trying six (or maybe seven) USB transactions each
+microframe rather than thirteen.  (Seems like a reasonable trade off
+for a product that beat all the others to market by over a year!)
+It's expected that newer implementations will better this, throwing
+more silicon real estate at the problem so that new motherboard chip
+sets will get closer to that 60 MByte/sec target.
+
+There's a minimum latency of one microframe (125 usec) for the host
+to receive interrupts from the EHCI controller indicating completion
+of requests.  That latency is tunable; there's a module option.  By
+default ehci-hcd driver uses the minimum latency, which means that if
+you issue a control or bulk request you can often expect to learn that
+it completed in less than 250 usec (depending on transfer size).
+
+Software Performance
+
+To get even 20 MByte/sec transfer rates, Linux-USB device drivers will
+need to keep the EHCI queue full.  That means issuing large requests,
+or using bulk queuing if a series of small requests needs to be issued.
+When drivers don't do that, their performance results will show it.
+
+In typical situations, a usb_bulk_msg() loop writing out 4 KB chunks is
+going to waste more than half the USB 2.0 bandwidth.  Delays between the
+I/O completion and the driver issuing the next request will take longer
+than the I/O.  If that same loop used 16 KB chunks, it'd be better; a
+sequence of 128 KB chunks would waste a lot less.
+
+But rather than depending on such large I/O buffers to make synchronous
+I/O be efficient, it's better to just queue all several (bulk) requests
+to the HC, and wait for them all to complete (or be canceled on error).
+Such URB queuing should work with all the USB 1.1 HC drivers too.
+
+TBD:  Interrupt and ISO transfer performance issues.  Those periodic
+transfers are fully scheduled, so the main issue is likely to be how
+to trigger "high bandwidth" modes.
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/usb/ibmcam.txt linux/Documentation/usb/ibmcam.txt
--- linux.orig/Documentation/usb/ibmcam.txt	2000-04-02 22:19:56.000000000 +0000
+++ linux/Documentation/usb/ibmcam.txt	2002-08-01 06:42:48.000000000 +0000
@@ -25,12 +25,19 @@
 
 SUPPORTED CAMERAS:
 
-IBM "C-It" camera, also known as "Xirlink PC Camera"
+Xirlink "C-It" camera, also known as "IBM PC Camera".
 The device uses proprietary ASIC (and compression method);
 it is manufactured by Xirlink. See http://www.xirlink.com/
 http://www.ibmpccamera.com or http://www.c-itnow.com/ for
 details and pictures.
 
+This very chipset ("X Chip", as marked at the factory)
+is used in several other cameras, and they are supported
+as well:
+
+- IBM NetCamera
+- Veo Stingray
+
 The Linux driver was developed with camera with following
 model number (or FCC ID): KSX-XVP510. This camera has three
 interfaces, each with one endpoint (control, iso, iso). This
@@ -50,12 +57,30 @@
 Such type of cameras is referred to as "model 2". They are supported
 (with exception of 352x288 native mode).
 
+Some IBM NetCameras (Model 4) are made to generate only compressed
+video streams. This is great for performance, but unfortunately
+nobody knows how to decompress the stream :-( Therefore, these
+cameras are *unsupported* and if you try to use one of those, all
+you get is random colored horizontal streaks, not the image!
+If you have one of those cameras, you probably should return it
+to the store and get something that is supported.
+
+Tell me more about all that "model" business
+--------------------------------------------
+
+I just invented model numbers to uniquely identify flavors of the
+hardware/firmware that were sold. It was very confusing to use
+brand names or some other internal numbering schemes. So I found
+by experimentation that all Xirlink chipsets fall into four big
+classes, and I called them "models". Each model is programmed in
+its own way, and each model sends back the video in its own way.
+
 Quirks of Model 2 cameras:
 -------------------------
 
 Model 2 does not have hardware contrast control. Corresponding V4L
-control is not used at the moment. It may be possible to implement
-contrast control in software, at cost of extra processor cycles.
+control is implemented in software, which is not very nice to your
+CPU, but at least it works.
 
 This driver provides 352x288 mode by switching the camera into
 quasi-352x288 RGB mode (800 Kbits per frame) essentially limiting
@@ -67,17 +92,24 @@
 the frame rate at slowest setting, but I had to move it pretty much down
 the scale (so that framerate option barely matters). I also noticed that
 camera after first powering up produces frames slightly faster than during
-consecutive uses. All this means that if you use videosize=2 (which is
+consecutive uses. All this means that if you use 352x288 (which is
 default), be warned - you may encounter broken picture on first connect;
 try to adjust brightness - brighter image is slower, so USB will be able
 to send all data. However if you regularly use Model 2 cameras you may
-prefer videosize=1 which makes perfectly good I420, with no scaling and
+prefer 176x144 which makes perfectly good I420, with no scaling and
 lesser demands on USB (300 Kbits per second, or 26 frames per second).
 
+Another strange effect of 352x288 mode is the fine vertical grid visible
+on some colored surfaces. I am sure it is caused by me not understanding
+what the camera is trying to say. Blame trade secrets for that.
+
 The camera that I had also has a hardware quirk: if disconnected,
 it needs few minutes to "relax" before it can be plugged in again
 (poorly designed USB processor reset circuit?)
 
+[Veo Stingray with Product ID 0x800C is also Model 2, but I haven't
+observed this particular flaw in it.]
+
 Model 2 camera can be programmed for very high sensitivity (even starlight
 may be enough), this makes it convenient for tinkering with. The driver
 code has enough comments to help a programmer to tweak the camera
@@ -98,12 +130,14 @@
 precompile all modules, so you can go directly to the next
 section "HOW TO USE THE DRIVER".
 
-The driver consists of two files in usb/ directory:
-ibmcam.c and ibmcam.h These files are included into the
-Linux kernel build process if you configure the kernel
-for CONFIG_USB_IBMCAM. Run "make xconfig" and in USB section
-you will find the IBM camera driver. Select it, save the
-configuration and recompile.
+The ibmcam driver uses usbvideo helper library (module),
+so if you are studying the ibmcam code you will be led there.
+
+The driver itself consists of only one file in usb/ directory:
+ibmcam.c. This file is included into the Linux kernel build
+process if you configure the kernel for CONFIG_USB_IBMCAM.
+Run "make xconfig" and in USB section you will find the IBM
+camera driver. Select it, save the configuration and recompile.
 
 HOW TO USE THE DRIVER:
 
@@ -112,6 +146,13 @@
 settings than V4L can operate, so some settings are done using
 module options.
 
+To begin with, on most modern Linux distributions the driver
+will be automatically loaded whenever you plug the supported
+camera in. Therefore, you don't need to do anything. However
+if you want to experiment with some module parameters then
+you can load and unload the driver manually, with camera
+plugged in or unplugged.
+
 Typically module is installed with command 'modprobe', like this:
 
 # modprobe ibmcam framerate=1
@@ -138,7 +179,7 @@
 init_hue        Integer         0-255 [128]     init_hue=115
 lighting        Integer         0-2* [1]        lighting=2
 sharpness       Integer         0-6* [4]        sharpness=3
-videosize       Integer         0-2* [2]        videosize=1
+size            Integer         0-2* [2]        size=1
 
 Options for Model 2 only:
 
@@ -181,6 +222,11 @@
                                            this is a little faster but may
                                            produce flicker if frame rate is
                                            too high and Isoc data gets lost.
+                FLAGS_NO_DECODING      128 This flag turns the video stream
+                                           decoder off, and dumps the raw
+                                           Isoc data from the camera into
+                                           the reading process. Useful to
+                                           developers, but not to users.
 
 framerate       This setting controls frame rate of the camera. This is
                 an approximate setting (in terms of "worst" ... "best")
@@ -227,35 +273,38 @@
                 be greeted with "snowy" image. Default is 4. Model 2
                 cameras do not support this feature.
 
-videosize       This setting chooses one if three image sizes that are
-                supported by this driver. Camera supports more, but
+size            This setting chooses one of several image sizes that are
+                supported by this driver. Cameras may support more, but
                 it's difficult to reverse-engineer all formats.
                 Following video sizes are supported:
 
-                videosize=0     128x96  (Model 1 only)
-                videosize=1     176x144
-                videosize=2     352x288
-                videosize=3     320x240 (Model 2 only)
-                videosize=4     352x240 (Model 2 only)
+                size=0     128x96  (Model 1 only)
+                size=1     160x120
+                size=2     176x144
+                size=3     320x240 (Model 2 only)
+                size=4     352x240 (Model 2 only)
+                size=5     352x288
+                size=6     640x480 (Model 3 only)
 
-                The last one (352x288) is the native size of the sensor
-                array, so it's the best resolution camera (Model 1) can
+                The 352x288 is the native size of the Model 1 sensor
+                array, so it's the best resolution the camera can
                 yield. The best resolution of Model 2 is 176x144, and
                 larger images are produced by stretching the bitmap.
+                Model 3 has sensor with 640x480 grid, and it works too,
+                but the frame rate will be exceptionally low (1-2 FPS);
+                it may be still OK for some applications, like security.
                 Choose the image size you need. The smaller image can
                 support faster frame rate. Default is 352x288.
 
+For more information and the Troubleshooting FAQ visit this URL:
+
+                http://www.linux-usb.org/ibmcam/
+
 WHAT NEEDS TO BE DONE:
 
-- The box freezes if camera is unplugged after being used (OHCI).
-  Workaround: remove usb-ohci module first.
-- On occasion camera (model 1) does not start properly (xawtv reports
-  errors), or camera produces negative image (funny colors.)
-  Workaround: reload the driver module. Reason: [1].
 - The button on the camera is not used. I don't know how to get to it.
   I know now how to read button on Model 2, but what to do with it?
 
-[1]
 - Camera reports its status back to the driver; however I don't know
   what returned data means. If camera fails at some initialization
   stage then something should be done, and I don't do that because
@@ -263,26 +312,13 @@
   concern because Model 2 uses different commands which do not return
   status (and seem to complete successfully every time).
 
-VIDEO SIZE AND IMAGE SIZE
-
-Camera produces picture X by Y pixels. This is camera-specific and can be
-altered by programming the camera accordingly. This image is placed onto
-larger (or equal) area W by H, this is V4L image. At this time the driver
-uses V4L image size (W by H) 352x288 pixels because many programs (such
-as xawtv) expect quite specific sizes and don't want to deal with arbitrary,
-camera-specific sizes. However this approach "hides" real image size, and
-application always sees the camera as producing only 352x288 image. It is
-possible to change the V4L image size to 128x96, and then if camera is
-switched to 128x96 mode then xawtv will correctly accept this image size. But
-many other popular sizes (such as 176x144) will not be welcomed. This is the
-reason why all camera images are at this time placed onto 352x288 "canvas",
-and size of that canvas (V4L) is reported to applications. It will be easy
-to add options to control the canvas size, but it will be application-
-specific because not all applications are ready to work with variety of
-camera-specific sizes.
+- Some flavors of Model 4 NetCameras produce only compressed video
+  streams, and I don't know how to decode them.
 
 CREDITS:
 
 The code is based in no small part on the CPiA driver by Johannes Erdfelt,
 Randy Dunlap, and others. Big thanks to them for their pioneering work on that
 and the USB stack.
+
+I also thank John Lightsey for his donation of the Veo Stingray camera.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/usb/proc_usb_info.txt linux/Documentation/usb/proc_usb_info.txt
--- linux.orig/Documentation/usb/proc_usb_info.txt	2000-08-22 16:06:31.000000000 +0000
+++ linux/Documentation/usb/proc_usb_info.txt	2002-08-01 06:42:31.000000000 +0000
@@ -1,32 +1,99 @@
 /proc/bus/usb filesystem output
 ===============================
-(version 2000.08.15)
+(version 2002.03.18)
 
 
-The /proc filesystem for USB devices generates
-/proc/bus/usb/drivers and /proc/bus/usb/devices.
+The /proc filesystem for USB devices provides /proc/bus/usb/drivers
+and /proc/bus/usb/devices, as well as /proc/bus/usb/BBB/DDD files.
 
-/proc/bus/usb/drivers lists the registered drivers,
-one per line, with each driver's USB minor dev node
-number range if applicable.
 
-**NOTE**: If /proc/bus/usb appears empty, you need
-          to mount the filesystem, issue the command (as root):
+**NOTE**: If /proc/bus/usb appears empty, and a host controller
+	  driver has been linked, then you need to mount the
+	  filesystem.  Issue the command (as root):
 
-      mount -t usbdevfs none /proc/bus/usb
+      mount -t usbfs none /proc/bus/usb
 
 	  An alternative and more permanent method would be to add
 
-      none  /proc/bus/usb  usbdevfs  defaults  0  0
+      none  /proc/bus/usb  usbfs  defaults  0  0
 
-	  to /etc/fstab.  This will mount usbdevfs at each reboot.
+	  to /etc/fstab.  This will mount usbfs at each reboot.
 	  You can then issue `cat /proc/bus/usb/devices` to extract
-	  USB device information.
+	  USB device information, and user mode drivers can use usbfs 
+	  to interact with USB devices.
 
-For more information on mounting the usbdevfs file system, see the
+	  There are a number of mount options supported by usbfs.
+	  Consult the source code (linux/drivers/usb/inode.c) for
+	  information about those options.
+
+**NOTE**: The filesystem has been renamed from "usbdevfs" to
+	  "usbfs", to reduce confusion with "devfs".  You may
+	  still see references to the older "usbdevfs" name.
+
+For more information on mounting the usbfs file system, see the
 "USB Device Filesystem" section of the USB Guide. The latest copy 
 of the USB Guide can be found at http://www.linux-usb.org/
 
+
+THE /proc/bus/usb/BBB/DDD FILES:
+--------------------------------
+Each connected USB device has one file.  The BBB indicates the bus
+number.  The DDD indicates the device address on that bus.  Both
+of these numbers are assigned sequentially, and can be reused, so
+you can't rely on them for stable access to devices.  For example,
+it's relatively common for devices to re-enumerate while they are
+still connected (perhaps someone jostled their power supply, hub,
+or USB cable), so a device might be 002/027 when you first connect
+it and 002/048 sometime later.
+
+These files can be read as binary data.  The binary data consists
+of first the device descriptor, then the descriptors for each
+configuration of the device.  That information is also shown in
+text form by the /proc/bus/usb/devices file, described later.
+
+These files may also be used to write user-level drivers for the USB
+devices.  You would open the /proc/bus/usb/BBB/DDD file read/write,
+read its descriptors to make sure it's the device you expect, and then
+bind to an interface (or perhaps several) using an ioctl call.  You
+would issue more ioctls to the device to communicate to it using
+control, bulk, or other kinds of USB transfers.  The IOCTLs are
+listed in the <linux/usbdevice_fs.h> file, and at this writing the
+source code (linux/drivers/usb/devio.c) is the primary reference
+for how to access devices through those files.
+
+Note that since by default these BBB/DDD files are writable only by
+root, only root can write such user mode drivers.  You can selectively
+grant read/write permissions to other users by using "chmod".  Also,
+usbfs mount options such as "devmode=0666" may be helpful.
+
+
+
+THE /proc/bus/usb/drivers FILE:
+-------------------------------
+Each of the USB device drivers linked into your kernel (statically,
+or dynamically using "modprobe") is listed in the "drivers" file.
+Here's an example from one system:
+
+         usbdevfs
+         hub
+  0- 15: usblp
+         usbnet
+         serial
+         usb-storage
+         pegasus
+
+If you see this file, "usbdevfs" and "hub" will always be listed,
+since those are part of the "usbcore" framework.
+
+Drivers that use the USB major number (180) to provide character devices
+will include a range of minor numbers, as shown above for the "usblp"
+(actually "printer.o") module.  USB device drivers can of course use any
+major number, but it's easy to use the USB range since there's explicit
+support for subdividing it in the USB device driver framework.
+
+
+THE /proc/bus/usb/devices FILE:
+-------------------------------
 In /proc/bus/usb/devices, each device's output has multiple
 lines of ASCII output.
 I made it ASCII instead of binary on purpose, so that someone
@@ -34,8 +101,6 @@
 auxiliary program.  However, with an auxiliary program, the numbers
 in the first 4 columns of each "T:" line (topology info:
 Lev, Prnt, Port, Cnt) can be used to build a USB topology diagram.
-(I think.  I haven't proved this, but I have tested it with 3
-different topo/connections and it looked possible.)
 
 Each line is tagged with a one-character ID for that line:
 
@@ -73,14 +138,30 @@
 |   |__Bus number
 |__Topology info tag
 
+    Speed may be:
+    	1.5	Mbit/s for low speed USB
+	12	Mbit/s for full speed USB
+	480	Mbit/s for high speed USB (added for USB 2.0)
+
 
 Bandwidth info:
 B:  Alloc=ddd/ddd us (xx%), #Int=ddd, #Iso=ddd
-|   |                       |         |__Number if isochronous requests
+|   |                       |         |__Number of isochronous requests
 |   |                       |__Number of interrupt requests
 |   |__Total Bandwidth allocated to this bus
 |__Bandwidth info tag
 
+    Bandwidth allocation is an approximation of how much of one frame
+    (millisecond) is in use.  It reflects only periodic transfers, which
+    are the only transfers that reserve bandwidth.  Control and bulk
+    transfers use all other bandwidth, including reserved bandwidth that
+    is not used for transfers (such as for short packets).
+    
+    The percentage is how much of the "reserved" bandwidth is scheduled by
+    those transfers.  For a low or full speed bus (loosely, "USB 1.1"),
+    90% of the bus bandwidth is reserved.  For a high speed bus (loosely,
+    "USB 2.0") 80% is reserved.
+
 
 Device descriptor info & Product ID info:
 
@@ -109,37 +190,55 @@
 
 S:  Manufacturer=ssss
 |   |__Manufacturer of this device as read from the device.
+|      For USB host controller drivers (virtual root hubs) this may
+|      be omitted, or (for newer drivers) will identify the kernel
+|      version and the driver which provides this hub emulation.
 |__String info tag
 
 S:  Product=ssss
-|   |__Product description of this device as read from the device,
-|      except that it is a generated string for USB host controllers
-|      (virtual root hubs), in the form "USB *HCI Root Hub".
+|   |__Product description of this device as read from the device.
+|      For older USB host controller drivers (virtual root hubs) this
+|      indicates the driver; for newer ones, it's a product (and vendor)
+|      description that often comes from the kernel's PCI ID database.
 |__String info tag
 
 S:  SerialNumber=ssss
-|   |__Serial Number of this device as read from the device,
-|      except that it is a generated string for USB host controllers
-|      (virtual root hubs), and represents the host controller's
-|      unique identification in the system (currently I/O or
-|      memory-mapped base address).
+|   |__Serial Number of this device as read from the device.
+|      For USB host controller drivers (virtual root hubs) this is
+|      some unique ID, normally a bus ID (address or slot name) that
+|      can't be shared with any other device.
 |__String info tag
 
 
+
 Configuration descriptor info:
 
-C:  #Ifs=dd Cfg#=dd Atr=xx MPwr=dddmA
-|   |       |       |      |__MaxPower in mA
-|   |       |       |__Attributes
-|   |       |__ConfiguratioNumber
-|   |__NumberOfInterfaces
+C:* #Ifs=dd Cfg#=dd Atr=xx MPwr=dddmA
+| | |       |       |      |__MaxPower in mA
+| | |       |       |__Attributes
+| | |       |__ConfiguratioNumber
+| | |__NumberOfInterfaces
+| |__ "*" indicates the active configuration (others are " ")
 |__Config info tag
+    
+    USB devices may have multiple configurations, each of which act
+    rather differently.  For example, a bus-powered configuration
+    might be much less capable than one that is self-powered.  Only
+    one device configuration can be active at a time; most devices
+    have only one configuration.
+
+    Each configuration consists of one or more interfaces.  Each
+    interface serves a distinct "function", which is typically bound
+    to a different USB device driver.  One common example is a USB
+    speaker with an audio interface for playback, and a HID interface
+    for use with software volume control.
 
 
 Interface descriptor info (can be multiple per Config):
 
 I:  If#=dd Alt=dd #EPs=dd Cls=xx(sssss) Sub=xx Prot=xx Driver=ssss
 |   |      |      |       |             |      |       |__Driver name
+|   |      |      |       |             |      |          or "(none)"
 |   |      |      |       |             |      |__InterfaceProtocol
 |   |      |      |       |             |__InterfaceSubClass
 |   |      |      |       |__InterfaceClass
@@ -148,17 +247,39 @@
 |   |__InterfaceNumber
 |__Interface info tag
 
+    A given interface may have one or more "alternate" settings.
+    For example, default settings may not use more than a small
+    amount of periodic bandwidth.  To use significant fractions
+    of bus bandwidth, drivers must select a non-default altsetting.
+    
+    Only one setting for an interface may be active at a time, and
+    only one driver may bind to an interface at a time.  Most devices
+    have only one alternate setting per interface.
+
 
 Endpoint descriptor info (can be multiple per Interface):
 
 E:  Ad=xx(s) Atr=xx(ssss) MxPS=dddd Ivl=dddms
-E:  Ad=xx(s) Atr=xx(ssss) MxPS=dddd Ivl=dddms
-|   |        |            |         |__Interval
+|   |        |            |         |__Interval (max) between transfers
 |   |        |            |__EndpointMaxPacketSize
 |   |        |__Attributes(EndpointType)
 |   |__EndpointAddress(I=In,O=Out)
 |__Endpoint info tag
 
+    The interval is nonzero for all periodic (interrupt or isochronous)
+    endpoints.  For high speed endpoints the transfer interval may be
+    measured in microseconds rather than milliseconds.
+
+    For high speed periodic endpoints, the "MaxPacketSize" reflects
+    the per-microframe data transfer size.  For "high bandwidth"
+    endpoints, that can reflect two or three packets (for up to
+    3KBytes every 125 usec) per endpoint.
+
+    With the Linux-USB stack, periodic bandwidth reservations use the
+    transfer intervals and sizes provided by URBs, which can be less
+    than those found in endpoint descriptor.
+
+
 =======================================================================
 
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/usb/usb-serial.txt linux/Documentation/usb/usb-serial.txt
--- linux.orig/Documentation/usb/usb-serial.txt	2002-02-25 19:37:52.000000000 +0000
+++ linux/Documentation/usb/usb-serial.txt	2002-08-01 06:42:31.000000000 +0000
@@ -95,12 +95,13 @@
   Kroah-Hartman at greg@kroah.com
 
 
-Compaq iPAQ driver
+Compaq iPAQ, HP Jornada and Casio EM500 driver
 
-  This driver can be used to connect to Compaq iPAQ PDAs running
-  Windows CE 3.0 using a USB autosync cable. It has been tested only on
-  the Compaq H3135. It should work with the H3600 and later models too.
-  It may work with other CE based handhelds as well.
+  This driver can be used to connect to Compaq iPAQ, HP Jornada and Casio EM500
+  PDAs running Windows CE 3.0 or PocketPC 2002 using a USB cable/cradle. It
+  has been tested only on the Compaq H3135, but is rumoured to work on
+  with the H3600 and later models as well as the Jornada 548 and 568.
+  With minor modifications, it may work for other CE based handhelds too.
 
   The driver presents a serial interface (usually on /dev/ttyUSB0) over
   which one may run ppp and establish a TCP/IP link to the iPAQ. Once this
@@ -109,11 +110,14 @@
   kbytes/sec for download/upload to the iPAQ.
 
   The driver works intermittently with the usb-uhci driver but quite
-  reliably with the uhci driver. Make sure you have the right driver
-  loaded - usb-uhci is often the default.
+  reliably with the uhci driver. However, performance is much better
+  with usb-uhci. It does not seem to work with ohci at all.
 
   You must setup hotplug to invoke pppd as soon as the iPAQ is connected.
-  A ppp script like the one below may be used:
+  A ppp script like the one below should be kept in the file
+  /etc/hotplug/usb/ipaq Remember to chmod +x. Make sure there are no
+  options in /etc/ppp/options or ~/.ppprc which conflict with the ones
+  given below.
 
 	#!/bin/bash
 
@@ -133,7 +137,7 @@
   On connecting the cable, you should see the usual "Device Connected",
   "User Authenticated" messages flash by on your iPAQ. Once connected,
   you can use Win CE programs like ftpView, Pocket Outlook from the iPAQ
-  and other synce utilities from the Linux side. Remember to enable IP
+  and xcerdisp, synce utilities from the Linux side. Remember to enable IP
   forwarding. 
 
   To use Pocket IE, follow the instructions given at
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/API.html linux/Documentation/video4linux/API.html
--- linux.orig/Documentation/video4linux/API.html	2000-01-06 22:46:18.000000000 +0000
+++ linux/Documentation/video4linux/API.html	2002-08-01 06:42:41.000000000 +0000
@@ -105,7 +105,7 @@
 <TR><TD><b>height</b><TD>The height of the image capture.</TD>
 <TR><TD><b>chromakey</b><TD>A host order RGB32 value for the chroma key.</TD>
 <TR><TD><b>flags</b><TD>Additional capture flags.</TD>
-<TR><TD><b>clips</b><TD>A list of clipping rectangles. <em>(Set only)</em)</TD>
+<TR><TD><b>clips</b><TD>A list of clipping rectangles. <em>(Set only)</em></TD>
 <TR><TD><b>clipcount</b><TD>The number of clipping rectangles. <em>(Set only)</em></TD>
 </TABLE>
 <P>
@@ -120,6 +120,7 @@
 </TABLE>
 <P>
 Merely setting the window does not enable capturing. Overlay capturing
+(i.e. PCI-PCI transfer to the frame buffer of the video card)
 is activated by passing the <b>VIDIOCCAPTURE</b> ioctl a value of 1, and
 disabled by passing it a value of 0. 
 <P>
@@ -310,9 +311,10 @@
 </TABLE>
 <P>
 <H3>Reading Images</H3>
-Each call to the <b>read</b> syscall returns the next available image from
-the device. It is up to the caller to set the format and then to pass a 
-suitable size buffer and length to the function. Not all devices will support
+Each call to the <b>read</b> syscall returns the next available image
+from the device. It is up to the caller to set format and size (using
+the VIDIOCSPICT and VIDIOCSWIN ioctls) and then to pass a suitable
+size buffer and length to the function. Not all devices will support
 read operations.
 <P>
 A second way to handle image capture is via the mmap interface if supported.
@@ -329,16 +331,39 @@
 <TR><TD><b>offsets</b><TD>The offset of each frame</TD>
 </TABLE>
 <P>
-Once the mmap has been made the VIDIOCMCAPTURE ioctl sets the image size
-you wish to use (which should match or be below the initial query size).
-Having done so it will begin capturing to the memory mapped buffer. Whenever
-a buffer is "used" by the program it should called VIDIOCSYNC to free this
-frame up and continue. <em>to add:</em>VIDIOCSYNC takes the frame number
-you are freeing as its argument. When the buffer is unmapped or all the
-buffers are full capture ceases. While capturing to memory the driver will
-make a "best effort" attempt to capture to screen as well if requested. This
-normally means all frames that "miss" memory mapped capture will go to the
-display.
+Once the mmap has been made the VIDIOCMCAPTURE ioctl starts the
+capture to a frame using the format and image size specified in the
+video_mmap (which should match or be below the initial query size).
+When the VIDIOCMCAPTURE ioctl returns the frame is <em>not</em>
+captured yet, the driver just instructed the hardware to start the
+capture.  The application has to use the VIDIOCSYNC ioctl to wait
+until the capture of a frame is finished.  VIDIOCSYNC takes the frame
+number you want to wait for as argument.
+<p>
+It is allowed to call VIDIOCMCAPTURE multiple times (with different
+frame numbers in video_mmap->frame of course) and thus have multiple
+outstanding capture requests.  A simple way do to double-buffering
+using this feature looks like this:
+<pre>
+/* setup everything */
+VIDIOCMCAPTURE(0)
+while (whatever) {
+   VIDIOCMCAPTURE(1)
+   VIDIOCSYNC(0)
+   /* process frame 0 while the hardware captures frame 1 */
+   VIDIOCMCAPTURE(0)
+   VIDIOCSYNC(1)
+   /* process frame 1 while the hardware captures frame 0 */
+}
+</pre>
+Note that you are <em>not</em> limited to only two frames.  The API
+allows up to 32 frames, the VIDIOCGMBUF ioctl returns the number of
+frames the driver granted.  Thus it is possible to build deeper queues
+to avoid loosing frames on load peaks.
+<p>
+While capturing to memory the driver will make a "best effort" attempt
+to capture to screen as well if requested. This normally means all
+frames that "miss" memory mapped capture will go to the display.
 <P>
 A final ioctl exists to allow a device to obtain related devices if a
 driver has multiple components (for example video0 may not be associated
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/bttv/CARDLIST linux/Documentation/video4linux/bttv/CARDLIST
--- linux.orig/Documentation/video4linux/bttv/CARDLIST	2001-10-17 21:19:20.000000000 +0000
+++ linux/Documentation/video4linux/bttv/CARDLIST	2002-08-01 06:42:32.000000000 +0000
@@ -7,13 +7,13 @@
   card=5 - Diamond DTV2000
   card=6 - AVerMedia TVPhone
   card=7 - MATRIX-Vision MV-Delta
-  card=8 - Fly Video II (Bt848)
-  card=9 - TurboTV
+  card=8 - FlyVideo II (Bt848) LR26
+  card=9 - IXMicro TurboTV
   card=10 - Hauppauge (bt878)
   card=11 - MIRO PCTV pro
   card=12 - ADS Technologies Channel Surfer TV
   card=13 - AVerMedia TVCapture 98
-  card=14 - Aimslab VHX
+  card=14 - Aimslab Video Highway Xtreme (VHX)
   card=15 - Zoltrix TV-Max
   card=16 - Pixelview PlayTV (bt878)
   card=17 - Leadtek WinView 601
@@ -21,7 +21,7 @@
   card=19 - LifeView FlyKit w/o Tuner
   card=20 - CEI Raffles Card
   card=21 - Lucky Star Image World ConferenceTV
-  card=22 - Phoebe Tv Master + FM
+  card=22 - Phoebe Tv Master + FM (CPH050)
   card=23 - Modular Technology MM205 PCTV, bt878
   card=24 - [many vendors] CPH05X/06X (bt878)
   card=25 - Terratec/Vobis TV-Boostar
@@ -54,12 +54,12 @@
   card=52 - Pinnacle PCTV Studio Pro
   card=53 - Typhoon TView RDS + FM Stereo / KNC1 TV Station RDS
   card=54 - Lifetec LT 9415 TV (LR90 Rev.F)
-  card=55 - BESTBUY Easy TV
+  card=55 - BESTBUY Easy TV (CPH031)
   card=56 - FlyVideo '98/FM
-  card=57 - GrandTec 'Grand Video Capture'
-  card=58 - Phoebe TV Master Only (No FM)
-  card=59 - TV Capturer
-  card=60 - MM100PCTV
+  card=57 - GrandTec 'Grand Video Capture' (Bt848)
+  card=58 - Phoebe TV Master Only (No FM) CPH060
+  card=59 - TV Capturer (CPH03X)
+  card=60 - Modular Technology MM100PCTV
   card=61 - AG Electronics GMV1
   card=62 - BESTBUY Easy TV (bt878)
   card=63 - ATI TV-Wonder
@@ -72,6 +72,12 @@
   card=70 - PV-BT878P+
   card=71 - Flyvideo 98EZ (capture only)
   card=72 - Prolink PV-BT878P+9B (PlayTV Pro rev.9B FM+NICAM)
+  card=73 - Sensoray 311
+  card=74 - RemoteVision MX (RV605)
+  card=75 - Powercolor MTV878/ MTV878R/ MTV878F
+  card=76 - Canopus WinDVR PCI (COMPAQ Presario 3524JP, 5112JP)
+  card=77 - GrandTec Multi Capture Card (Bt878)
+  card=78 - AOPEN VA1000
 
 tuner.o
   type=0 - Temic PAL (4002 FH5)
@@ -94,7 +100,7 @@
   type=17 - Philips NTSC_M (MK2)
   type=18 - Temic PAL_I (4066 FY5)
   type=19 - Temic PAL* auto (4006 FN5)
-  type=20 - Temic PAL (4009 FR5)
+  type=20 - Temic PAL_BG (4009 FR5) or PAL_I (4069 FR5)
   type=21 - Temic NTSC (4039 FR5)
   type=22 - Temic PAL/SECAM multi (4046 FM5)
   type=23 - Philips PAL_DK
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/bttv/Cards linux/Documentation/video4linux/bttv/Cards
--- linux.orig/Documentation/video4linux/bttv/Cards	2001-10-17 21:19:20.000000000 +0000
+++ linux/Documentation/video4linux/bttv/Cards	2002-08-01 06:42:35.000000000 +0000
@@ -15,6 +15,10 @@
 All other cards only differ by additional components as tuners, sound decoders,
 EEPROMs, teletext decoders ...
 
+Unsupported Cards: 
+------------------
+Cards with Zoran (ZR) or Philips (SAA) or ISA are not supported by this driver. 
+
 
 MATRIX Vision
 -------------
@@ -137,20 +141,37 @@
       1851:1850 = Flyvideo 98
       1851:1851 = Flyvideo 98 EZ (capture only)
   2) There is a print on the PCB:
-      LR25       = Flyvideo (Zoran)
-      LR37 Rev.C = Capture only (ZR36120 + SAA7110)
+      LR25       = Flyvideo (Zoran ZR36120, SAA7110A)
+      LR26 Rev.N = Flyvideo II (Bt848)
+           Rev.O = Flyvideo II (Bt878)
+      LR37 Rev.C = Flyvideo EZ (Capture only, ZR36120 + SAA7110)
+      LR38 Rev.A1= Flyvideo II EZ (Bt848 capture only)
       LR50 Rev.Q = Flyvideo 98 (w/eeprom and PCI subsystem ID)
-      LR50 Rev.W = Flyvideo 98 (no eeprom)
+           Rev.W = Flyvideo 98 (no eeprom)
       LR51 Rev.E = Flyvideo 98 EZ (capture only)
       LR90       = Flyvideo 2000 series
-      LR90 Rev.F = Lifetec/Medion LT 9815
+      LR91       = Stereo daughter card for LR90
       LR97       = Flyvideo DVBS
+      LR138 Rev.C= Flyvideo 2000 (SAA7130)
+	        or Flyvideo 3000 (SAA7134) w/Stereo TV
+		   These exist in variations w/FM and w/Remote sometimes denoted
+		   by suffixes "FM" and "R".
+
+      Lifeview.com.tw states (Feb. 2002):
+      "The FlyVideo2000 and FlyVideo2000s product name have renamed to FlyVideo98."
+      Their Bt8x8 cards are listed as discontinued.
+      Flyvideo 2000S was probably sold as Flyvideo 3000 in some contries(Europe?).
+      The new Flyvideo 2000/3000 are SAA7130/SAA7134 based. 
+      Flyvideo 2100/3100 are half-sized cards (for system integrators etc.)
 
   "Flyvideo II" had been the name for the 848 cards, nowadays (in Germany)
   this name is re-used for LR50 Rev.W.
-  The Lifeview website has even more names: Flyvideo III,2100,3000,3100.
+  The Lifeview website mentioned Flyvideo III at some time, but such a card
+  has never been seen. 
   These cards are sold by many OEMs too.
 
+  FlyVideo A2 = LR90 Rev.F (w/Remote, w/o FM, stereo TV by tda9821)
+
 
 Typhoon TV card series:
 -----------------------
@@ -176,6 +197,7 @@
 
 Guillemot
 ---------
+  Maxi-TV PCI (ZR36120)
   Maxi TV Video 2 = LR50 Rev.Q (FI1216MF, PAL BG+SECAM)
   Maxi TV Video 3 = CPH064 (PAL BG + SECAM)
 
@@ -208,3 +230,163 @@
 Genius/Kye
 ----------
    Video Wonder/Genius Internet Video Kit = LR37 Rev.C
+   Video Wonder Pro II (848 or 878) = LR26
+
+Tekram
+------
+   VideoCap C205 (Bt848)
+   VideoCap C210 (Zoran ZR36120 +Philips)
+   CaptureTV M200 (ISA)
+   CaptureTV M205 (Bt848)
+
+Lucky Star
+----------
+   Image World Conference TV = LR50 Rev. Q
+
+Leadtek
+-------
+   WinView 601 (Bt848)
+   WinView 610 (Zoran)
+   WinFast2000
+
+KNC One
+-------
+   TV-Station
+   TV-Station SE (+Software Bundle)
+   TV-Station pro (+TV stereo)
+   TV-Station FM (+Radio)
+   TV-Station RDS (+RDS)
+
+PV951 cards:
+------------
+  These are sold as:
+   Boeder TV-FM Video Capture Card
+   Titanmedia Supervision TV-2400
+   Provideo PV951 TF
+   3DeMon PV951
+   MediaForte TV-Vision PV951
+   Yoko PV951
+
+Highscreen
+----------
+   TV Karte = LR50 Rev.S
+   TV-Boostar = Terratec Terra TV+ Version 1.0 (Bt848, TDA9821) "ceb105.pcb"
+
+Zoltrix
+-------
+   Face To Face TV MAX (Bt848) (PCB "VP-8482 Rev1.3")
+   Genie TV (Bt878) (PCB "VP-8790 Rev 2.1")
+
+AVerMedia
+---------
+   AVer FunTV Lite (ISA, AV3001 chipset)  "M101.C"
+   AVerTV
+   AVerTV Stereo
+   AVerTV Studio (w/FM)
+   AVerMedia TV98 with Remote 
+   AVerMedia TV/FM98 Stereo
+   AVerMedia TVCAM98
+   TVCapture (Bt848)
+   TVPhone (Bt848)
+   TVCapture98 (="AVerMedia TV98" in USA) (Bt878)
+   TVPhone98 (Bt878, w/FM)
+
+   PCB      PCI-ID      Model-Name      Eeprom  Tuner  Sound    Country
+   --------------------------------------------------------------------
+   M1A8-A      --       AVer TV-Phone           FM1216  --
+   M168-T   1461:0003   AVerTV Studio   48:17   FM1216 TDA9840T  D    (1) w/FM w/Remote
+   M168-U   1461:0004   TVCapture98     40:11   FI1216   --      D    w/Remote
+   M168II-B 1461:0003   Medion MD9592   48:16   FM1216 TDA9873H  D    w/FM
+
+   (1) Daughterboard MB68-A with TDA9820T and TDA9840T
+
+Aimslab
+-------
+   Video Highway Xtreme (aka "VHX") (Bt848, FM w/ TEA5757)
+
+IXMicro
+-------
+   IXTV BT848
+   IXTV BT878
+   TurboTV (Bt848)
+
+Lifetec/Medion/Tevion/Aldi
+-------
+   LT9415/MD9415 = LR90 Rev. F
+          MD9592 = Avermedia TVphone98 (PCI_ID=1461:0003), PCB-Rev=M168II-B (w/TDA9873H)
+
+Modular Technologies (www.modulartech.com) UK
+--------------------
+   MM100 PCTV (Bt848)
+   MM205 PCTV (Bt878)
+   MM210 PCTV (Bt878) (Galaxy TV)
+
+Terratec
+--------
+   Terra TV+ Version 1.0 (Bt848), "ceb105.PCB" printed on the PCB, TDA9821
+   Terra TV+ Version 1.1 (Bt878), "LR74 Rev.E" printed on the PCB, TDA9821
+   Terra TValueRadio,             "LR102 Rev.C" printed on the PCB
+   Terra TV/Radio+ Version 1.0,   "80-CP2830100-0" TTTV3 printed on the PCB, i
+				     "CPH010-E83" on the back, SAA6588T, TDA9873H
+   Terra TValue Version BT878,    "80-CP2830110-0 TTTV4" printed on the PCB, 
+				     "CPH011-D83" on back
+   Terra TValue Version 1.0       "ceb105.PCB" (really identical to Terra TV+ Version 1.0)
+
+   LR74 is a newer PCB revision of ceb105 (both incl. connector for Active Radio Upgrade)
+
+
+Technisat
+---------
+   Mediafocus I (ZR36120/ZR36125)
+   Mediafocus II (SAA7146)
+
+Siemens
+-------
+   Multimedia eXtension Board (MXB) (SAA7146, SAA7111)
+
+Stradis
+-------
+   SDM275,SDM250,SDM026,SDM025 (SAA7146, IBMMPEG2): MPEG2 decoder only
+
+Powercolor
+----------
+   MTV878
+   MTV878R w/Remote Control
+   MTV878F w/Remote Control w/FM radio
+
+Pinnacle
+--------
+   Mirovideo PCTV (Bt848)
+   Mirovideo PCTV SE (Bt848)
+   Mirovideo PCTV Pro (Bt848 + Daughterboard)
+   Studio PCTV Rave (Bt878 w/o infrared)
+   Studio PCTV
+   Studio PCTV Pro (Bt878 stereo w/ FM)
+
+   DC1+ (ISA)
+   DC10  (zr36057 + zr36060 + saa7110 + adv7176)
+   DC10+ (zr36067 + zr36060 + saa7110 + adv7176)
+   DC20
+   DC30
+   DC30+ (zr36067 + zr36050 + zr36016 + vpx3220 + adv7176)
+
+Lenco
+-----
+   MXR-9565 (=Technisat Mediafocus?)
+   MXR-9571 (Bt848)
+   MXR-9575
+   MXR-9477 (Bt878)
+   MXTV-9578CP (= Prolink PV-BT878P+4E)
+
+Iomega
+------
+   Buz (Zoran zr36067 + zr36060 + SAA7111 + SAA7185)
+
+LML
+---
+   LML33 (zr36067 + zr36060 + bt819+ bt856)
+
+Grandtec
+--------
+   Grand Video Capture (Bt848)
+   Multi Capture Card  (Bt878)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/bttv/Insmod-options linux/Documentation/video4linux/bttv/Insmod-options
--- linux.orig/Documentation/video4linux/bttv/Insmod-options	2001-10-17 21:19:20.000000000 +0000
+++ linux/Documentation/video4linux/bttv/Insmod-options	2002-08-01 06:42:33.000000000 +0000
@@ -28,7 +28,7 @@
 				default is 0 (off).
 		irq_debug=0/1	irq handler debug messages.
 				default is 0 (off).
-		gbuffers=2-64	number of capture buffers for mmap'ed capture.
+		gbuffers=2-32	number of capture buffers for mmap'ed capture.
 				default is 2.
 		gbufsize=	size of capture buffers. default and
 				maximum value is 0x208000 (~2MB)
@@ -38,6 +38,13 @@
 				push used by bttv.  bttv will disable overlay
 				by default on this hardware to avoid crashes.
 				With this insmod option you can override this.
+		automute=0/1	Automatically mutes the sound if there is
+				no TV signal, on by default.  You might try
+				to disable this if you have bad input signal
+				quality which leading to unwanted sound
+				dropouts.
+		chroma_agc=0/1	AGC of chroma signal, off by default.
+		adc_crush=0/1	Luminance ADC crush, on by default.
 
 		bttv_gpio=0/1
 		gpiomask=
@@ -89,6 +96,8 @@
 	insmod args for tda9874a:
 		tda9874a_SIF=1/2	select sound IF input pin (1 or 2)
 					(default is pin 1)
+		tda9874a_AMSEL=0/1	auto-mute select for NICAM (default=0)
+					Please read note 3 below!
 		tda9874a_STD=n		select TV sound standard (0..8):
 					0 - A2, B/G
 					1 - A2, M (Korea)
@@ -100,11 +109,20 @@
 					7 - NICAM, D/K (default)
 					8 - NICAM, L
 
-	Note: tda9874a is very similar to tda9874 (without 'A'-suffix), but
-	this driver will not work for the latter device (will not load).
-	Note: tda9874a and tda9875 (which is supported separately by
+	Note 1: tda9874a supports both tda9874h (old) and tda9874a (new) chips.
+	Note 2: tda9874h/a and tda9875 (which is supported separately by
 	tda9875.o) use the same i2c address so both modules should not be
 	used at the same time.
+	Note 3: Using tda9874a_AMSEL option depends on your TV card design!
+		AMSEL=0: auto-mute will switch between NICAM sound
+			 and the sound on 1st carrier (i.e. FM mono or AM).
+		AMSEL=1: auto-mute will switch between NICAM sound
+			 and the analog mono input (MONOIN pin).
+	If tda9874a decoder on your card has MONOIN pin not connected, then
+	use only tda9874_AMSEL=0 or don't specify this option at all.
+	For example:
+	  card=65 (FlyVideo 2000S) - set AMSEL=1 or AMSEL=0
+	  card=72 (Prolink PV-BT878P rev.9B) - set AMSEL=0 only
 
 msp3400.o
 	The driver for the msp34xx sound processor chips. If you have a
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/bttv/README.freeze linux/Documentation/video4linux/bttv/README.freeze
--- linux.orig/Documentation/video4linux/bttv/README.freeze	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/video4linux/bttv/README.freeze	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,65 @@
+
+If the box freezes hard with bttv ...
+=====================================
+
+It might be a bttv driver bug.  It also might be bad hardware.  It also
+might be something else ...
+
+Just mailing me "bttv freezes" isn't going to help much.  This README
+has a few hints how you can help to pin down the problem.
+
+
+bttv bugs
+---------
+
+If some version works and another doesn't it is likely to be a driver
+bug.  It is very helpful if you can tell where exactly it broke
+(i.e. the last working and the first broken version).
+
+With a hard freeze you probably doesn't find anything in the logfiles.
+The only way to capture any kernel messages is to hook up a serial
+console and let some terminal application log the messages.  /me uses
+screen.  See Documentation/serial-console.txt for details on setting
+up a serial console.
+
+Read Documentation/oops-tracing.txt to learn how to get any useful
+information out of a register+stack dump printed by the kernel on
+protection faults (so-called "kernel oops").
+
+If you run into some kind of deadlock, you can try to dump a call trace
+for each process using sysrq-t (see Documentation/sysrq.txt).  ksymoops
+will translate these dumps into kernel symbols too.  This way it is
+possible to figure where *exactly* some process in "D" state is stuck.
+
+I've seen reports that bttv 0.7.x crashes whereas 0.8.x works rock solid
+for some people.  Thus probably a small buglet left somewhere in bttv
+0.7.x.  I have no idea where exactly, it works stable for me and alot of
+other people.  But in case you have problems with the 0.7.x versions you
+can give 0.8.x a try ...
+
+
+hardware bugs
+-------------
+
+Some hardware can't deal with PCI-PCI transfers (i.e. grabber => vga).
+Sometimes problems show up with bttv just because of the high load on
+the PCI bus. The bt848/878 chips have a few workarounds for known
+incompatibilities, see README.quirks.
+
+Some mainboard have problems to deal correctly with multiple devices
+doing DMA at the same time.  bttv + ide seems to cause this sometimes,
+if this is the case you likely see freezes only with video and hard disk
+access at the same time.  Updating the IDE driver to get the latest and
+greatest workarounds for hardware bugs might fix these problems.
+
+
+other
+-----
+
+IRQ sharing is known to cause problems in some cases.  It works just
+fine in theory and many configurations.  Neverless it might be worth a
+try to shuffle around the PCI cards to give bttv another IRQ or make
+it share the IRQ with some other piece of hardware.  IRQ sharing with
+VGA cards seems to cause trouble sometimes.  I've also seen funny
+effects with bttv sharing the IRQ with the ACPI bridge (and
+apci-enabled kernel).
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/bttv/Sound-FAQ linux/Documentation/video4linux/bttv/Sound-FAQ
--- linux.orig/Documentation/video4linux/bttv/Sound-FAQ	2001-10-17 21:19:20.000000000 +0000
+++ linux/Documentation/video4linux/bttv/Sound-FAQ	2002-08-01 06:42:45.000000000 +0000
@@ -62,7 +62,7 @@
 {
 	[ ... ]
         u32 gpiomask;
-        u32 audiomux[5];  /* audio mux: tuner, radio, external, internal, mute */
+        u32 audiomux[6]; /* Tuner, Radio, external, internal, mute, stereo */
 };
 
 gpiomask specifies which pins are used to control the audio mux chip.
@@ -127,6 +127,9 @@
 *_modulename    - hint whenever some card needs this or that audio
                   module loaded to work properly.
 has_radio	- whenever this TV card has a radio tuner.
+no_msp34xx	- "1" disables loading of msp3400.o module
+no_tda9875	- "1" disables loading of tda9875.o module 
+needs_tvaudio	- set to "1" to load tvaudio.o module 
 
 If some config item is specified both from the tvcards array and as
 insmod option, the insmod option takes precedence.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/video4linux/meye.txt linux/Documentation/video4linux/meye.txt
--- linux.orig/Documentation/video4linux/meye.txt	2001-10-11 16:04:57.000000000 +0000
+++ linux/Documentation/video4linux/meye.txt	2002-08-01 06:42:35.000000000 +0000
@@ -15,9 +15,17 @@
 
 MJPEG hardware grabbing is supported via a private API (see below).
 
-Module options:
+Driver options:
 ---------------
 
+Several options can be passed to the meye driver, either by adding them
+to /etc/modules.conf file, when the driver is compiled as a module, or
+by adding the following to the kernel command line (in your bootloader):
+
+	meye=gbuffers[,gbufsize[,video_nr]]
+
+where:
+
 	gbuffers:	number of capture buffers, default is 2 (32 max)
 
 	gbufsize:	size of each capture buffer, default is 614400
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Documentation/watchdog-api.txt linux/Documentation/watchdog-api.txt
--- linux.orig/Documentation/watchdog-api.txt	1970-01-01 00:00:00.000000000 +0000
+++ linux/Documentation/watchdog-api.txt	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,390 @@
+The Linux Watchdog driver API.
+
+Copyright 2002 Christer Weingel <wingel@nano-system.com>
+
+Some parts of this document are copied verbatim from the sbc60xxwdt
+driver which is (c) Copyright 2000 Jakob Oestergaard <jakob@ostenfeld.dk>
+
+This document describes the state of the Linux 2.4.18 kernel.
+
+Introduction:
+
+A Watchdog Timer (WDT) is a hardware circuit that can reset the
+computer system in case of a software fault.  You probably knew that
+already.
+
+Usually a userspace daemon will notify the kernel watchdog driver via the
+/dev/watchdog special device file that userspace is still alive, at
+regular intervals.  When such a notification occurs, the driver will
+usually tell the hardware watchdog that everything is in order, and
+that the watchdog should wait for yet another little while to reset
+the system.  If userspace fails (RAM error, kernel bug, whatever), the
+notifications cease to occur, and the hardware watchdog will reset the
+system (causing a reboot) after the timeout occurs.
+
+The Linux watchdog API is a rather AD hoc construction and different
+drivers implement different, and sometimes incompatible, parts of it.
+This file is an attempt to document the existing usage and allow
+future driver writers to use it as a reference.
+
+The simplest API:
+
+All drivers support the basic mode of operation, where the watchdog
+activates as soon as /dev/watchdog is opened and will reboot unless
+the watchdog is pinged within a certain time, this time is called the
+timeout or margin.  The simplest way to ping the watchdog is to write
+some data to the device.  So a very simple watchdog daemon would look
+like this:
+
+int main(int argc, const char *argv[]) {
+	int fd=open("/dev/watchdog",O_WRONLY);
+	if (fd==-1) {
+		perror("watchdog");
+		exit(1);
+	}
+	while(1) {
+		write(fd, "\0", 1);
+		sleep(10);
+	}
+}
+
+A more advanced driver could for example check that a HTTP server is
+still responding before doing the write call to ping the watchdog.
+
+When the device is closed, the watchdog is disabled.  This is not
+always such a good idea, since if there is a bug in the watchdog
+daemon and it crashes the system will not reboot.  Because of this,
+some of the drivers support the configuration option "Disable watchdog
+shutdown on close", CONFIG_WATCHDOG_NOWAYOUT.  If it is set to Y when
+compiling the kernel, there is no way of disabling the watchdog once
+it has been started.  So, if the watchdog dameon crashes, the system
+will reboot after the timeout has passed.
+
+Some other drivers will not disable the watchdog, unless a specific
+magic character 'V' has been sent /dev/watchdog just before closing
+the file.  If the userspace daemon closes the file without sending
+this special character, the driver will assume that the daemon (and
+userspace in general) died, and will stop pinging the watchdog without
+disabling it first.  This will then cause a reboot.
+
+The ioctl API:
+
+All conforming drivers also support an ioctl API.
+
+Pinging the watchdog using an ioctl:
+
+All drivers that have an ioctl interface support at least one ioctl,
+KEEPALIVE.  This ioctl does exactly the same thing as a write to the
+watchdog device, so the main loop in the above program could be
+replaced with:
+
+	while (1) {
+		ioctl(fd, WDIOC_KEEPALIVE, 0);
+		sleep(10);
+	}
+
+the argument to the ioctl is ignored.
+
+Setting and getting the timeout:
+
+For some drivers it is possible to modify the watchdog timeout on the
+fly with the SETTIMEOUT ioctl, those drivers have the WDIOF_SETTIMEOUT
+flag set in their option field.  The argument is an integer
+representing the timeout in seconds.  The driver returns the real
+timeout used in the same variable, and this timeout might differ from
+the requested one due to limitation of the hardware.
+
+    int timeout = 45;
+    ioctl(fd, WDIOC_SETTIMEOUT, &timeout);
+    printf("The timeout was set to %d seconds\n", timeout);
+
+This example might actually print "The timeout was set to 60 seconds"
+if the device has a granularity of minutes for its timeout.
+
+Starting with the Linux 2.4.18 kernel, it is possible to query the
+current timeout using the GETTIMEOUT ioctl.
+
+    ioctl(fd, WDIOC_GETTIMEOUT, &timeout);
+    printf("The timeout was is %d seconds\n", timeout);
+
+Envinronmental monitoring:
+
+All watchdog drivers are required return more information about the system,
+some do temperature, fan and power level monitoring, some can tell you
+the reason for the last reboot of the system.  The GETSUPPORT ioctl is
+available to ask what the device can do:
+
+	struct watchdog_info ident;
+	ioctl(fd, WDIOC_GETSUPPORT, &ident);
+
+the fields returned in the ident struct are:
+
+        identity		a string identifying the watchdog driver
+	firmware_version	the firmware version of the card if available
+	options			a flags describing what the device supports
+
+the options field can have the following bits set, and describes what
+kind of information that the GET_STATUS and GET_BOOT_STATUS ioctls can
+return.   [FIXME -- Is this correct?]
+
+	WDIOF_OVERHEAT		Reset due to CPU overheat
+
+The machine was last rebooted by the watchdog because the thermal limit was
+exceeded
+
+	WDIOF_FANFAULT		Fan failed
+
+A system fan monitored by the watchdog card has failed
+
+	WDIOF_EXTERN1		External relay 1
+
+External monitoring relay/source 1 was triggered. Controllers intended for
+real world applications include external monitoring pins that will trigger
+a reset.
+
+	WDIOF_EXTERN2		External relay 2
+
+External monitoring relay/source 2 was triggered
+
+	WDIOF_POWERUNDER	Power bad/power fault
+
+The machine is showing an undervoltage status
+
+	WDIOF_CARDRESET		Card previously reset the CPU
+
+The last reboot was caused by the watchdog card
+
+	WDIOF_POWEROVER		Power over voltage
+
+The machine is showing an overvoltage status. Note that if one level is
+under and one over both bits will be set - this may seem odd but makes
+sense.
+
+	WDIOF_KEEPALIVEPING	Keep alive ping reply
+
+The watchdog saw a keepalive ping since it was last queried.
+
+	WDIOF_SETTIMEOUT	Can set/get the timeout
+
+
+For those drivers that return any bits set in the option field, the
+GETSTATUS and GETBOOTSTATUS ioctls can be used to ask for the current
+status, and the status at the last reboot, respectively.  
+
+    int flags;
+    ioctl(fd, WDIOC_GETSTATUS, &flags);
+
+    or
+
+    ioctl(fd, WDIOC_GETBOOTSTATUS, &flags);
+
+Note that not all devices support these two calls, and some only
+support the GETBOOTSTATUS call.
+
+Some drivers can measure the temperature using the GETTEMP ioctl.  The
+returned value is the temperature in degrees farenheit.
+
+    int temperature;
+    ioctl(fd, WDIOC_GETTEMP, &temperature);
+
+Finally the SETOPTIONS ioctl can be used to control some aspects of
+the cards operation; right now the pcwd driver is the only one
+supporting thiss ioctl.
+
+    int options = 0;
+    ioctl(fd, WDIOC_SETOPTIONS, options);
+
+The following options are available:
+
+	WDIOS_DISABLECARD	Turn off the watchdog timer
+	WDIOS_ENABLECARD	Turn on the watchdog timer
+	WDIOS_TEMPPANIC		Kernel panic on temperature trip
+
+[FIXME -- better explanations]
+
+Implementations in the current drivers in the kernel tree:
+
+Here I have tried to summarize what the different drivers support and
+where they do strange things compared to the other drivers.
+
+acquirewdt.c -- Acquire Single Board Computer
+
+	This driver has a hardcoded timeout of 1 minute
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns KEEPALIVEPING.  GETSTATUS will return 1 if
+	the device is open, 0 if not.  [FIXME -- isn't this rather
+	silly?  To be able to use the ioctl, the device must be open
+	and so GETSTATUS will always return 1].
+
+advantechwdt.c -- Advantech Single Board Computer
+
+	Timeout that defaults to 60 seconds, supports SETTIMEOUT.
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns WDIOF_KEEPALIVEPING and WDIOF_SETTIMEOUT.
+	The GETSTATUS call returns if the device is open or not.
+	[FIXME -- silliness again?]
+	
+eurotechwdt.c -- Eurotech CPU-1220/1410
+
+	The timeout can be set using the SETTIMEOUT ioctl and defaults
+	to 60 seconds.
+
+	Also has a module parameter "ev", event type which controls
+	what should happen on a timeout, the string "int" or anything
+	else that causes a reboot.  [FIXME -- better description]
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns CARDRESET and WDIOF_SETTIMEOUT but
+	GETSTATUS is not supported and GETBOOTSTATUS just returns 0.
+
+i810-tco.c -- Intel 810 chipset
+
+	Also has support for a lot of other i8x0 stuff, but the
+	watchdog is one of the things.
+
+	The timeout is set using the module parameter "i810_margin",
+	which is in steps of 0.6 seconds where 2<i810_margin<64.  The
+	driver supports the SETTIMEOUT ioctl.
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT.
+
+	GETSUPPORT returns WDIOF_SETTIMEOUT.  The GETSTATUS call
+	returns some kind of timer value which ist not compatible with
+	the other drivers.  GETBOOT status returns some kind of
+	hardware specific boot status.  [FIXME -- describe this]
+
+ib700wdt.c -- IB700 Single Board Computer
+
+	Default timeout of 30 seconds and the timeout is settable
+	using the SETTIMEOUT ioctl.  Note that only a few timeout
+	values are supported.
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns WDIOF_KEEPALIVEPING and WDIOF_SETTIMEOUT.
+	The GETSTATUS call returns if the device is open or not.
+	[FIXME -- silliness again?]
+
+machzwd.c -- MachZ ZF-Logic
+
+	Hardcoded timeout of 10 seconds
+
+	Has a module parameter "action" that controls what happens
+	when the timeout runs out which can be 0 = RESET (default), 
+	1 = SMI, 2 = NMI, 3 = SCI.
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT and the the magic character
+	'V' close handling.
+
+	GETSUPPORT returns WDIOF_KEEPALIVEPING, and the GETSTATUS call
+	returns if the device is open or not.  [FIXME -- silliness
+	again?]
+
+mixcomwd.c -- MixCom Watchdog
+
+	[FIXME -- I'm unable to tell what the timeout is]
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns WDIOF_KEEPALIVEPING, GETSTATUS returns if
+	the device is opened or not [FIXME -- I'm not really sure how
+	this works, there seems to be some magic connected to
+	CONFIG_WATCHDOG_NOWAYOUT]
+
+pcwd.c -- Berkshire PC Watchdog
+
+	Hardcoded timeout of 1.5 seconds
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns WDIOF_OVERHEAT|WDIOF_CARDRESET and both
+	GETSTATUS and GETBOOTSTATUS return something useful.
+
+	The SETOPTIONS call can be used to enable and disable the card
+	and to ask the driver to call panic if the system overheats.
+
+sbc60xxwdt.c -- 60xx Single Board Computer
+
+	Hardcoded timeout of 10 seconds
+
+	Does not support CONFIG_WATCHDOG_NOWAYOUT, but has the magic
+	character 'V' close handling.
+
+	No bits set in GETSUPPORT
+
+scx200.c -- National SCx200 CPUs
+
+	Not in the kernel yet.
+
+	The timeout is set using a module parameter "margin" which
+	defaults to 60 seconds.  The timeout can also be set using
+	SETTIMEOUT and read using GETTIMEOUT.
+
+	Supports a module parameter "nowayout" that is initialized
+	with the value of CONFIG_WATCHDOG_NOWAYOUT.  Also supports the
+	magic character 'V' handling.
+
+shwdt.c -- SuperH 3/4 processors
+
+	[FIXME -- I'm unable to tell what the timeout is]
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns WDIOF_KEEPALIVEPING, and the GETSTATUS call
+	returns if the device is open or not.  [FIXME -- silliness
+	again?]
+
+softdog.c -- Software watchdog
+
+	The timeout is set with the module parameter "soft_margin"
+	which defaults to 60 seconds, the timeout is also settable
+	using the SETTIMEOUT ioctl.
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	WDIOF_SETTIMEOUT bit set in GETSUPPORT
+
+w83877f_wdt.c -- W83877F Computer
+
+	Hardcoded timeout of 30 seconds
+
+	Does not support CONFIG_WATCHDOG_NOWAYOUT, but has the magic
+	character 'V' close handling.
+
+	No bits set in GETSUPPORT
+
+wdt.c -- ICS WDT500/501 ISA and
+wdt_pci.c -- ICS WDT500/501 PCI
+
+	Default timeout of 60 seconds.  The timeout is also settable
+        using the SETTIMEOUT ioctl.
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	GETSUPPORT returns with bits set depending on the actual
+	card. The WDT501 supports a lot of external monitoring, the
+	WDT500 much less.
+
+wdt285.c -- Footbridge watchdog
+
+	The timeout is set with the module parameter "soft_margin"
+	which defaults to 60 seconds.  The timeout is also settable
+	using the SETTIMEOUT ioctl.
+
+	Does not support CONFIG_WATCHDOG_NOWAYOUT
+
+	WDIOF_SETTIMEOUT bit set in GETSUPPORT
+
+wdt977.c -- Netwinder W83977AF chip
+
+	Hardcoded timeout of 3 minutes
+
+	Supports CONFIG_WATCHDOG_NOWAYOUT
+
+	Does not support any ioctls at all.
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/MAINTAINERS linux/MAINTAINERS
--- linux.orig/MAINTAINERS	2002-02-25 19:37:52.000000000 +0000
+++ linux/MAINTAINERS	2002-08-01 06:42:30.000000000 +0000
@@ -69,6 +69,14 @@
 			it has been replaced by a better system and you
 			should be using that.
 
+3C359 NETWORK DRIVER
+P:	Mike Phillips
+M:	mikep@linuxtr.net
+L:	linux-net@vger.rutgers.edu
+L:	linux-tr@linuxtr.net
+W:	http://www.linuxtr.net
+S:	Maintained
+
 3C501 NETWORK DRIVER
 P:	Alan Cox
 M:	alan@the.3c501.cabal.tm
@@ -260,9 +268,9 @@
 
 BTTV VIDEO4LINUX DRIVER
 P:	Gerd Knorr
-M:	kraxel@goldbach.in-berlin.de
+M:	kraxel@bytesex.org
 L:	video4linux-list@redhat.com
-W:	http://me.in-berlin.de/~kraxel/bttv.html
+W:	http://bytesex.org/bttv/
 S:	Maintained
 
 BUSLOGIC SCSI DRIVER
@@ -544,14 +552,12 @@
 S:      Maintained
 
 EXT2 FILE SYSTEM
-P:	Remy Card
-M:	Remy.Card@linux.org
-L:	linux-kernel@vger.kernel.org
+L:	ext2-devel@lists.sourceforge.net
 S:	Maintained
 
 EXT3 FILE SYSTEM
-P:	Remy Card, Stephen Tweedie
-M:	sct@redhat.com, akpm@zip.com.au, adilger@turbolinux.com
+P:	Stephen Tweedie, Andrew Morton
+M:	sct@redhat.com, akpm@zip.com.au, adilger@clusterfs.com
 L:	ext3-users@redhat.com
 S:	Maintained
 
@@ -667,7 +673,7 @@
 
 i386 BOOT CODE
 P:	Riley H. Williams
-M:	rhw@memalpha.cx
+M:	Riley@Williams.Name
 L:	Linux-Kernel@vger.kernel.org
 S:	Maintained
 
@@ -706,12 +712,12 @@
 IDE DRIVER [GENERAL]
 P:	Andre Hedrick
 M:	andre@linux-ide.org
-M:	andre@aslab.com
-M:	andre@suse.com
+M:	andre@linuxdiskcert.org
 L:	linux-kernel@vger.kernel.org
 W:	http://www.kernel.org/pub/linux/kernel/people/hedrick/
 W:	http://www.linux-ide.org/
-S:	Supported
+W:	http://www.linuxdiskcert.org/
+S:	Maintained
 
 IDE/ATAPI CDROM DRIVER
 P:	Jens Axboe
@@ -734,16 +740,12 @@
 S:	Maintained
 
 IEEE 1394 SUBSYSTEM
-P:	Andreas Bombe
-M:	andreas.bombe@munich.netsurf.de
+P:	Ben Collins
+M:	bcollins@debian.org
 L:	linux1394-devel@lists.sourceforge.net
 W:	http://linux1394.sourceforge.net/
 S:	Maintained
 
-IEEE 1394 AIC5800 DRIVER
-L:	linux1394-devel@lists.sourceforge.net
-S:	Orphan
-
 IEEE 1394 OHCI DRIVER
 P:	Ben Collins
 M:	bcollins@debian.org
@@ -791,6 +793,12 @@
 L:      intermezzo-discuss@lists.sourceforge.net
 S:      Maintained
 
+IOC3 DRIVER
+P:	Ralf Baechle
+M:	ralf@oss.sgi.com
+L:	linux-mips@oss.sgi.com
+S:	Maintained
+
 IP MASQUERADING:
 P:	Juanjo Ciarlante
 M:	jjciarla@raiz.uncu.edu.ar
@@ -849,7 +857,7 @@
 M:	vojtech@suse.cz
 L:	linux-joystick@atrey.karlin.mff.cuni.cz
 W:	http://www.suse.cz/development/joystick/
-S:	Supported
+S:	Maintained
 
 KERNEL AUTOMOUNTER (AUTOFS)
 P:	H. Peter Anvin
@@ -918,6 +926,13 @@
 L:	linuxppc-dev@lists.linuxppc.org
 S:	Maintained
 
+LINUX FOR 64BIT POWERPC
+P:	David Engebretsen
+M:	engebret@us.ibm.com
+W:	http://linuxppc64.org
+L:	linuxppc64-dev@lists.linuxppc.org
+S:	Supported
+
 LOGICAL DISK MANAGER SUPPORT (LDM, Windows 2000/XP Dynamic Disks)
 P:	Richard Russon (FlatCap)
 M:	ldm@flatcap.org
@@ -1156,6 +1171,12 @@
 L:	linux-sound@vger.kernel.org
 S:	Maintained
 
+ORINOCO DRIVER
+P:	David Gibson
+M:	hermes@gibson.dropbear.id.au
+W:	http://www.ozlabs.org/people/dgibson/dldwd
+S:	Maintained
+
 PARALLEL PORT SUPPORT
 P:	Phil Blundell
 M:	Philip.Blundell@pobox.com
@@ -1183,8 +1204,10 @@
 S:	Maintained
 
 PCI ID DATABASE
-P:	Jens Maurer
-M:	jmaurer@cck.uni-kl.de
+P:	Martin Mares
+M:	mj@ucw.cz
+L:	pciids-devel@lists.sourceforge.net
+W:	http://pciids.sourceforge.net/
 S:	Maintained
 
 PCI SOUND DRIVERS (ES1370, ES1371 and SONICVIBES)
@@ -1224,6 +1247,20 @@
 L:	linux-net@vger.kernel.org
 S:	Maintained
 
+PERMEDIA 3 FRAMEBUFFER DRIVER
+P:	Romain Dolbeau
+M:	dolbeau@irisa.fr
+L:	linux-fbdev-devel@lists.sourceforge.net
+W:	http://www.irisa.fr/prive/dolbeau/pm3fb/pm3fb.html
+S:	Maintained
+
+PHILIPS NINO PALM PC
+P:	Steven Hill
+M:	sjhill@realitydiluted.com
+L:	linux-mips@oss.sgi.com
+W:	http://www.realitydiluted.com/projects/nino
+S:	Maintained
+
 PNP SUPPORT
 P:	Tom Lees
 M:	tom@lpsg.demon.co.uk
@@ -1254,6 +1291,17 @@
 W:	http://www.pnd-pc.demon.co.uk/promise/
 S:	Maintained
 
+PROMISE PDC202XX IDE CONTROLLER DRIVER
+P:	Hank Yang
+M:	support@promise.com.tw [TAIWAN]
+P:	Jordan Rhody
+M:	support@promise.com [U.S.A]
+P:	Jack Hu
+M:	support-china@promise.com [CHINA]
+W:	http://www.promise.com/support/linux_eng.asp
+W:	http://www.promise.com.tw/support/linux_eng.asp
+S:	Maintained
+
 QNX4 FILESYSTEM
 P:	Anders Larsen
 M:	al@alarsen.net
@@ -1304,6 +1352,12 @@
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 
+RME96XX MULTICHANNEL SOUND DRIVER
+P:      Guenter Geiger
+M:      geiger@epy.co.at  
+L:      linux-kernel@vger.kernel.org
+S:      Maintained
+
 RTLINUX  REALTIME  LINUX
 P:	Victor Yodaiken
 M:	yodaiken@fsmlabs.com
@@ -1331,6 +1385,11 @@
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 
+SC1200 WDT DRIVER
+P:      Zwane Mwaikambo
+M:      zwane@commfireservices.com
+S:      Maintained
+
 SCSI CDROM DRIVER
 P:	Jens Axboe
 M:	axboe@suse.de
@@ -1362,6 +1421,13 @@
 M:	mingo@redhat.com
 S:	Maintained
 
+SIS 5513 IDE CONTROLLER DRIVER
+P:      Lionel Bouton
+M:      Lionel.Bouton@inet6.fr
+W:      http://inet6.dyn.dhs.org/sponsoring/sis5513/index.html
+W:      http://gyver.homeip.net/sis5513/index.html
+S:      Maintained
+
 SIS 900/7016 FAST ETHERNET DRIVER
 P:	Ollie Lho
 M:	ollie@sis.com.tw
@@ -1412,8 +1478,6 @@
 M:	anton@samba.org
 L:	sparclinux@vger.kernel.org
 L:	ultralinux@vger.kernel.org
-W:	http://ultra.linux.cz
-W:	http://www.geog.ubc.ca/s_linux.html
 S:	Maintained
 
 SPECIALIX IO8+ MULTIPORT SERIAL CARD DRIVER
@@ -1477,13 +1541,18 @@
 M:	hch@infradead.org
 S:	Maintained
 
+TIEMAN VOYAGER USB BRAILLE DISPLAY DRIVER
+P:	Stephane Dalton
+M:	sdalton@videotron.ca
+P:	Stéphane Doyon
+M:	s.doyon@videotron.ca
+S:	Maintained
+
 TLAN NETWORK DRIVER
-P:	Torben Mathiasen
-M:	torben.mathiasen@compaq.com
-M:	torben@kernel.dk
-L:	tlan@vuser.vu.union.edu
-L:	linux-net@vger.kernel.org
-W:	http://tlan.kernel.dk
+P:	Samuel Chessman
+M:	chessman@tux.org
+L:	tlan-devel@lists.sourceforge.net
+W:	http://sourceforge.net/projects/tlan/
 S:	Maintained
 
 TOKEN-RING NETWORK DRIVER
@@ -1562,7 +1631,14 @@
 M:	vojtech@suse.cz
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
-S:	Supported
+S:	Maintained
+
+USB AUERSWALD DRIVER
+P:	Wolfgang Muees
+M:	wmues@nexgo.de
+L:	linux-usb-users@lists.sourceforge.net
+L:	linux-usb-devel@lists.sourceforge.net
+S:	Maintained
 
 USB BLUETOOTH DRIVER
 P:	Greg Kroah-Hartman
@@ -1579,13 +1655,19 @@
 L:	linux-usb-devel@lists.sourceforge.net
 S:	Maintained
 
+USB EHCI DRIVER
+P:	David Brownell
+M:	dbrownell@users.sourceforge.net
+L:	linux-usb-devel@lists.sourceforge.net
+S:	Maintained
+
 USB HID/HIDBP/INPUT DRIVERS
 P:	Vojtech Pavlik
 M:	vojtech@suse.cz
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
 W:	http://www.suse.cz/development/input/
-S:	Supported
+S:	Maintained
 
 USB HUB
 P:	Johannes Erdfelt
@@ -1595,8 +1677,8 @@
 S:	Maintained
 
 USB KAWASAKI LSI DRIVER
-P:	Brad Hards
-M:	bradh@frogmouth.net
+P:	Oliver Neukum
+M:	drivers@neukum.org
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
 S:	Maintained
@@ -1626,7 +1708,7 @@
 
 USB PEGASUS DRIVER
 P:	Petko Manolov
-M:	petkan@dce.bg
+M:	petkan@users.sourceforge.net
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
 S:	Maintained
@@ -1636,7 +1718,14 @@
 M:	vojtech@suse.cz
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
-S:	Supported
+S:	Maintained
+
+USB RTL8150 DRIVER
+P:	Petko Manolov
+M:	petkan@users.sourceforge.net
+L:	linux-usb-users@lists.sourceforge.net
+L:	linux-usb-devel@lists.sourceforge.net
+S:	Maintained
 
 USB SE401 DRIVER
 P:	Jeroen Vreeken
@@ -1684,12 +1773,12 @@
 S:	Maintained
 
 USB SERIAL KEYSPAN DRIVER
-P:	Hugh Blemings
-M:	hugh@misc.nu
+P:	Greg Kroah-Hartman
+M:	greg@kroah.com
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
+W:	http://www.kroah.com/linux/
 S:	Maintained
-W:	http://misc.nu/hugh/keyspan/
 
 USB SUBSYSTEM
 P:	Greg Kroah-Hartman
@@ -1707,6 +1796,12 @@
 W:	http://usb.in.tum.de
 S:	Maintained
 	
+USB "USBNET" DRIVER
+P:	David Brownell
+M:	dbrownell@users.sourceforge.net
+L:	linux-usb-devel@lists.sourceforge.net
+S:	Maintained
+
 VFAT FILESYSTEM:
 P:	Gordon Chaffee
 M:	chaffee@cs.berkeley.edu
@@ -1727,10 +1822,9 @@
 S:	Maintained
 
 VIDEO FOR LINUX
-P:	Alan Cox
-M:	Alan.Cox@linux.org
-W:	http://roadrunner.swansea.linux.org.uk/v4l.shtml
-S:	Maintained for 2.2 only
+P:	Gerd Knorr
+M:	kraxel@bytesex.org
+S:	Maintained
 
 WAN ROUTER & SANGOMA WANPIPE DRIVERS & API (X.25, FRAME RELAY, PPP, CISCO HDLC)
 P:     Nenad Corbic
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Makefile linux/Makefile
--- linux.orig/Makefile	2002-02-25 19:37:52.000000000 +0000
+++ linux/Makefile	2002-08-01 06:42:32.000000000 +0000
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 4
-SUBLEVEL = 18
-EXTRAVERSION =
+SUBLEVEL = 19
+EXTRAVERSION = -rc5
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
@@ -14,7 +14,7 @@
 TOPDIR	:= $(shell /bin/pwd)
 
 HPATH   	= $(TOPDIR)/include
-FINDHPATH	= $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net
+FINDHPATH	= $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net $(HPATH)/math-emu
 
 HOSTCC  	= gcc
 HOSTCFLAGS	= -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
@@ -89,7 +89,10 @@
 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
 
 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
-	  -fomit-frame-pointer -fno-strict-aliasing -fno-common
+	  -fno-strict-aliasing -fno-common
+ifndef CONFIG_FRAME_POINTER
+CFLAGS += -fomit-frame-pointer
+endif
 AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS)
 
 #
@@ -140,9 +143,8 @@
 DRIVERS-$(CONFIG_DRM_NEW) += drivers/char/drm/drm.o
 DRIVERS-$(CONFIG_DRM_OLD) += drivers/char/drm-4.0/drm.o
 DRIVERS-$(CONFIG_NUBUS) += drivers/nubus/nubus.a
-DRIVERS-$(CONFIG_ISDN) += drivers/isdn/isdn.a
 DRIVERS-$(CONFIG_NET_FC) += drivers/net/fc/fc.o
-DRIVERS-$(CONFIG_APPLETALK) += drivers/net/appletalk/appletalk.o
+DRIVERS-$(CONFIG_DEV_APPLETALK) += drivers/net/appletalk/appletalk.o
 DRIVERS-$(CONFIG_TR) += drivers/net/tokenring/tr.o
 DRIVERS-$(CONFIG_WAN) += drivers/net/wan/wan.o
 DRIVERS-$(CONFIG_ARCNET) += drivers/net/arcnet/arcnetdrv.o
@@ -168,7 +170,7 @@
 DRIVERS-$(CONFIG_SBUS) += drivers/sbus/sbus_all.o
 DRIVERS-$(CONFIG_ZORRO) += drivers/zorro/driver.o
 DRIVERS-$(CONFIG_FC4) += drivers/fc4/fc4.a
-DRIVERS-$(CONFIG_ALL_PPC) += drivers/macintosh/macintosh.o
+DRIVERS-$(CONFIG_PPC) += drivers/macintosh/macintosh.o
 DRIVERS-$(CONFIG_MAC) += drivers/macintosh/macintosh.o
 DRIVERS-$(CONFIG_ISAPNP) += drivers/pnp/pnp.o
 DRIVERS-$(CONFIG_SGI_IP22) += drivers/sgi/sgi.a
@@ -185,6 +187,7 @@
 DRIVERS-$(CONFIG_MD) += drivers/md/mddev.o
 DRIVERS-$(CONFIG_BLUEZ) += drivers/bluetooth/bluetooth.o
 DRIVERS-$(CONFIG_HOTPLUG_PCI) += drivers/hotplug/vmlinux-obj.o
+DRIVERS-$(CONFIG_ISDN_BOOL) += drivers/isdn/vmlinux-obj.o
 
 DRIVERS := $(DRIVERS-y)
 
@@ -201,10 +204,15 @@
 	drivers/zorro/devlist.h drivers/zorro/gen-devlist \
 	drivers/sound/bin2hex drivers/sound/hex2hex \
 	drivers/atm/fore200e_mkfirm drivers/atm/{pca,sba}*{.bin,.bin1,.bin2} \
+	drivers/scsi/aic7xxx/aicasm/aicasm \
 	drivers/scsi/aic7xxx/aicasm/aicasm_gram.c \
+	drivers/scsi/aic7xxx/aicasm/aicasm_gram.h \
+	drivers/scsi/aic7xxx/aicasm/aicasm_macro_gram.c \
+	drivers/scsi/aic7xxx/aicasm/aicasm_macro_gram.h \
+	drivers/scsi/aic7xxx/aicasm/aicasm_macro_scan.c \
 	drivers/scsi/aic7xxx/aicasm/aicasm_scan.c \
+	drivers/scsi/aic7xxx/aicasm/aicdb.h \
 	drivers/scsi/aic7xxx/aicasm/y.tab.h \
-	drivers/scsi/aic7xxx/aicasm/aicasm \
 	drivers/scsi/53c700_d.h \
 	net/khttpd/make_times_h \
 	net/khttpd/times.h \
@@ -243,6 +251,16 @@
 
 include arch/$(ARCH)/Makefile
 
+# Extra cflags for kbuild 2.4.  The default is to forbid includes by kernel code
+# from user space headers.  Some UML code requires user space headers, in the
+# UML Makefiles add 'kbuild_2_4_nostdinc :=' before include Rules.make.  No
+# other kernel code should include user space headers, if you need
+# 'kbuild_2_4_nostdinc :=' or -I/usr/include for kernel code and you are not UML
+# then your code is broken!  KAO.
+
+kbuild_2_4_nostdinc	:= -nostdinc $(shell $(CC) -print-search-dirs | sed -ne 's/install: \(.*\)/-I \1include/gp')
+export kbuild_2_4_nostdinc
+
 export	CPPFLAGS CFLAGS CFLAGS_KERNEL AFLAGS AFLAGS_KERNEL
 
 export	NETWORKS DRIVERS LIBS HEAD LDFLAGS LINKFLAGS MAKEBOOT ASFLAGS
@@ -258,8 +276,8 @@
 boot: vmlinux
 	@$(MAKE) CFLAGS="$(CFLAGS) $(CFLAGS_KERNEL)" -C arch/$(ARCH)/boot
 
-vmlinux: include/linux/version.h $(CONFIGURATION) init/main.o init/version.o linuxsubdirs
-	$(LD) $(LINKFLAGS) $(HEAD) init/main.o init/version.o \
+vmlinux: include/linux/version.h $(CONFIGURATION) init/main.o init/version.o init/do_mounts.o linuxsubdirs
+	$(LD) $(LINKFLAGS) $(HEAD) init/main.o init/version.o init/do_mounts.o \
 		--start-group \
 		$(CORE_FILES) \
 		$(DRIVERS) \
@@ -306,25 +324,29 @@
 	. scripts/mkversion > .tmpversion
 	@mv -f .tmpversion .version
 
+uts_len		:= 64
+uts_truncate	:= sed -e 's/\(.\{1,$(uts_len)\}\).*/\1/'
+
 include/linux/compile.h: $(CONFIGURATION) include/linux/version.h newversion
-	@echo -n \#define UTS_VERSION \"\#`cat .version` > .ver
-	@if [ -n "$(CONFIG_SMP)" ] ; then echo -n " SMP" >> .ver; fi
-	@if [ -f .name ]; then  echo -n \-`cat .name` >> .ver; fi
-	@echo ' '`date`'"' >> .ver
-	@echo \#define LINUX_COMPILE_TIME \"`date +%T`\" >> .ver
+	@echo -n \#`cat .version` > .ver1
+	@if [ -n "$(CONFIG_SMP)" ] ; then echo -n " SMP" >> .ver1; fi
+	@if [ -f .name ]; then  echo -n \-`cat .name` >> .ver1; fi
+	@LANG=C echo ' '`date` >> .ver1
+	@echo \#define UTS_VERSION \"`cat .ver1 | $(uts_truncate)`\" > .ver
+	@LANG=C echo \#define LINUX_COMPILE_TIME \"`date +%T`\" >> .ver
 	@echo \#define LINUX_COMPILE_BY \"`whoami`\" >> .ver
-	@echo \#define LINUX_COMPILE_HOST \"`hostname`\" >> .ver
-	@if [ -x /bin/dnsdomainname ]; then \
-	   echo \#define LINUX_COMPILE_DOMAIN \"`dnsdomainname`\"; \
-	 elif [ -x /bin/domainname ]; then \
-	   echo \#define LINUX_COMPILE_DOMAIN \"`domainname`\"; \
-	 else \
-	   echo \#define LINUX_COMPILE_DOMAIN ; \
-	 fi >> .ver
+	@echo \#define LINUX_COMPILE_HOST \"`hostname | $(uts_truncate)`\" >> .ver
+	@([ -x /bin/dnsdomainname ] && /bin/dnsdomainname > .ver1) || \
+	 ([ -x /bin/domainname ] && /bin/domainname > .ver1) || \
+	 echo > .ver1
+	@echo \#define LINUX_COMPILE_DOMAIN \"`cat .ver1 | $(uts_truncate)`\" >> .ver
 	@echo \#define LINUX_COMPILER \"`$(CC) $(CFLAGS) -v 2>&1 | tail -1`\" >> .ver
 	@mv -f .ver $@
+	@rm -f .ver1
 
 include/linux/version.h: ./Makefile
+	@expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
+	  (echo KERNELRELEASE \"$(KERNELRELEASE)\" exceeds $(uts_len) characters >&2; false)
 	@echo \#define UTS_RELEASE \"$(KERNELRELEASE)\" > .ver
 	@echo \#define LINUX_VERSION_CODE `expr $(VERSION) \\* 65536 + $(PATCHLEVEL) \\* 256 + $(SUBLEVEL)` >> .ver
 	@echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))' >>.ver
@@ -336,15 +358,18 @@
 	$(CC) $(CFLAGS) $(CFLAGS_KERNEL) -DUTS_MACHINE='"$(ARCH)"' -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) -c -o init/version.o init/version.c
 
 init/main.o: init/main.c include/config/MARKER
-	$(CC) $(CFLAGS) $(CFLAGS_KERNEL) $(PROFILING) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) -c -o $*.o $<
+	$(CC) $(CFLAGS) $(CFLAGS_KERNEL) $(PROFILING) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) -c -o $@ $<
+
+init/do_mounts.o: init/do_mounts.c include/config/MARKER
+	$(CC) $(CFLAGS) $(CFLAGS_KERNEL) $(PROFILING) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) -c -o $@ $<
 
 fs lib mm ipc kernel drivers net: dummy
 	$(MAKE) CFLAGS="$(CFLAGS) $(CFLAGS_KERNEL)" $(subst $@, _dir_$@, $@)
 
 TAGS: dummy
-	etags `find include/asm-$(ARCH) -name '*.h'`
-	find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print | xargs etags -a
-	find $(SUBDIRS) init -name '*.[ch]' | xargs etags -a
+	{ find include/asm-${ARCH} -name '*.h' -print ; \
+	find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print ; \
+	find $(SUBDIRS) init arch/${ARCH} -name '*.[chS]' ; } | grep -v SCCS | etags -
 
 # Exuberant ctags works better with -I
 tags: dummy
@@ -452,6 +477,11 @@
 htmldocs: sgmldocs
 	$(MAKE) -C Documentation/DocBook html
 
+mandocs:
+	chmod 755 $(TOPDIR)/scripts/kernel-doc
+	chmod 755 $(TOPDIR)/scripts/split-man
+	$(MAKE) -C Documentation/DocBook man
+
 sums:
 	find . -type f -print | sort | xargs sum > .SUMS
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/README linux/README
--- linux.orig/README	2001-10-05 19:10:00.000000000 +0000
+++ linux/README	2002-08-01 06:42:39.000000000 +0000
@@ -150,13 +150,12 @@
 
 COMPILING the kernel:
 
- - Make sure you have gcc-2.91.66 (egcs-1.1.2) available.  gcc 2.95.2 may
+ - Make sure you have gcc 2.95.3 available.  gcc 2.91.66 (egcs-1.1.2) may
    also work but is not as safe, and *gcc 2.7.2.3 is no longer supported*.
    Also remember to upgrade your binutils package (for as/ld/nm and company)
    if necessary. For more information, refer to ./Documentation/Changes.
 
-   Please note that you can still run a.out user programs with this
-   kernel.
+   Please note that you can still run a.out user programs with this kernel.
 
  - Do a "make bzImage" to create a compressed kernel image.  If you want
    to make a boot disk (without root filesystem or LILO), insert a floppy
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/Rules.make linux/Rules.make
--- linux.orig/Rules.make	2002-02-25 19:37:52.000000000 +0000
+++ linux/Rules.make	2002-08-01 06:42:40.000000000 +0000
@@ -32,6 +32,7 @@
 unexport subdir-
 
 comma	:= ,
+EXTRA_CFLAGS_nostdinc := $(EXTRA_CFLAGS) $(kbuild_2_4_nostdinc)
 
 #
 # Get things started.
@@ -50,15 +51,15 @@
 #
 
 %.s: %.c
-	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$@) -S $< -o $@
+	$(CC) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_$@) -S $< -o $@
 
 %.i: %.c
-	$(CPP) $(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$@) $< > $@
+	$(CPP) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_$@) $< > $@
 
 %.o: %.c
-	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_$@) -c -o $@ $<
+	$(CC) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_$@) -c -o $@ $<
 	@ ( \
-	    echo 'ifeq ($(strip $(subst $(comma),:,$(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$@))),$$(strip $$(subst $$(comma),:,$$(CFLAGS) $$(EXTRA_CFLAGS) $$(CFLAGS_$@))))' ; \
+	    echo 'ifeq ($(strip $(subst $(comma),:,$(CFLAGS) $(EXTRA_CFLAGS_nostdinc) $(CFLAGS_$@))),$$(strip $$(subst $$(comma),:,$$(CFLAGS) $$(EXTRA_CFLAGS_nostdinc) $$(CFLAGS_$@))))' ; \
 	    echo 'FILES_FLAGS_UP_TO_DATE += $@' ; \
 	    echo 'endif' \
 	) > $(dir $@)/.$(notdir $@).flags
@@ -81,7 +82,7 @@
 endif
 
 %.lst: %.c
-	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$@) -g -c -o $*.o $<
+	$(CC) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) $(CFLAGS_$@) -g -c -o $*.o $<
 	$(TOPDIR)/scripts/makelst $* $(TOPDIR) $(OBJDUMP)
 #
 #
@@ -125,7 +126,7 @@
 # This make dependencies quickly
 #
 fastdep: dummy
-	$(TOPDIR)/scripts/mkdep $(CFLAGS) $(EXTRA_CFLAGS) -- $(wildcard *.[chS]) > .depend
+	$(TOPDIR)/scripts/mkdep $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -- $(wildcard *.[chS]) > .depend
 ifdef ALL_SUB_DIRS
 	$(MAKE) $(patsubst %,_sfdep_%,$(ALL_SUB_DIRS)) _FASTDEP_ALL_SUB_DIRS="$(ALL_SUB_DIRS)"
 endif
@@ -175,7 +176,7 @@
 _modinst__: dummy
 ifneq "$(strip $(ALL_MOBJS))" ""
 	mkdir -p $(MODLIB)/kernel/$(MOD_DESTDIR)
-	cp $(ALL_MOBJS) $(MODLIB)/kernel/$(MOD_DESTDIR)$(MOD_TARGET)
+	cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
 endif
 
 .PHONY: modules_install
@@ -224,9 +225,9 @@
 
 $(MODINCL)/%.ver: %.c
 	@if [ ! -r $(MODINCL)/$*.stamp -o $(MODINCL)/$*.stamp -ot $< ]; then \
-		echo '$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -D__GENKSYMS__ $<'; \
+		echo '$(CC) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -E -D__GENKSYMS__ $<'; \
 		echo '| $(GENKSYMS) $(genksyms_smp_prefix) -k $(VERSION).$(PATCHLEVEL).$(SUBLEVEL) > $@.tmp'; \
-		$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -D__GENKSYMS__ $< \
+		$(CC) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -E -D__GENKSYMS__ $< \
 		| $(GENKSYMS) $(genksyms_smp_prefix) -k $(VERSION).$(PATCHLEVEL).$(SUBLEVEL) > $@.tmp; \
 		if [ -r $@ ] && cmp -s $@ $@.tmp; then echo $@ is unchanged; rm -f $@.tmp; \
 		else echo mv $@.tmp $@; mv -f $@.tmp $@; fi; \
@@ -272,9 +273,9 @@
 
 ifneq "$(strip $(export-objs))" ""
 $(export-objs): $(export-objs:.o=.c) $(TOPDIR)/include/linux/modversions.h
-	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_$@) -DEXPORT_SYMTAB -c $(@:.o=.c)
+	$(CC) $(CFLAGS) $(EXTRA_CFLAGS_nostdinc) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_$@) -DEXPORT_SYMTAB -c $(@:.o=.c)
 	@ ( \
-	    echo 'ifeq ($(strip $(subst $(comma),:,$(CFLAGS) $(EXTRA_CFLAGS) $(CFLAGS_$@) -DEXPORT_SYMTAB)),$$(strip $$(subst $$(comma),:,$$(CFLAGS) $$(EXTRA_CFLAGS) $$(CFLAGS_$@) -DEXPORT_SYMTAB)))' ; \
+	    echo 'ifeq ($(strip $(subst $(comma),:,$(CFLAGS) $(EXTRA_CFLAGS_nostdinc) $(CFLAGS_$@) -DEXPORT_SYMTAB)),$$(strip $$(subst $$(comma),:,$$(CFLAGS) $$(EXTRA_CFLAGS_nostdinc) $$(CFLAGS_$@) -DEXPORT_SYMTAB)))' ; \
 	    echo 'FILES_FLAGS_UP_TO_DATE += $@' ; \
 	    echo 'endif' \
 	) > $(dir $@)/.$(notdir $@).flags
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/Makefile linux/arch/alpha/Makefile
--- linux.orig/arch/alpha/Makefile	2000-12-04 01:45:20.000000000 +0000
+++ linux/arch/alpha/Makefile	2002-08-01 06:42:31.000000000 +0000
@@ -40,22 +40,22 @@
     CFLAGS := $(CFLAGS) -mcpu=pca56
     mcpu_done := y
   endif
-  ifeq ($(mcpu_done)$(CONFIG_ALPHA_PYXIS),ny)
-    CFLAGS := $(CFLAGS) -mcpu=ev56
-    mcpu_done := y
-  endif
-  ifeq ($(mcpu_done)$(CONFIG_ALPHA_POLARIS),ny)
-    ifeq ($(have_mcpu_pca56),y)
-      CFLAGS := $(CFLAGS) -mcpu=pca56
-    else
-      CFLAGS := $(CFLAGS) -mcpu=ev56
-    endif
+  ifeq ($(mcpu_done)$(CONFIG_ALPHA_POLARIS)$(have_mcpu_pca56),nyy)
+    CFLAGS := $(CFLAGS) -mcpu=pca56
     mcpu_done := y
   endif
   ifeq ($(mcpu_done)$(CONFIG_ALPHA_EV4),ny)
     CFLAGS := $(CFLAGS) -mcpu=ev4
     mcpu_done := y
   endif
+  ifeq ($(mcpu_done)$(CONFIG_ALPHA_EV56),ny)
+    CFLAGS := $(CFLAGS) -mcpu=ev56
+    mcpu_done := y
+  endif
+  ifeq ($(mcpu_done)$(CONFIG_ALPHA_EV5),ny)
+    CFLAGS := $(CFLAGS) -mcpu=ev5
+    mcpu_done := y
+  endif
   ifeq ($(mcpu_done)$(CONFIG_ALPHA_EV67)$(have_mcpu_ev67),nyy)
     CFLAGS := $(CFLAGS) -mcpu=ev67
     mcpu_done := y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/config.in linux/arch/alpha/config.in
--- linux.orig/arch/alpha/config.in	2001-11-20 23:49:31.000000000 +0000
+++ linux/arch/alpha/config.in	2002-08-01 06:42:35.000000000 +0000
@@ -102,19 +102,44 @@
 then
 	define_bool CONFIG_ALPHA_EB64P y
 fi
-if [ "$CONFIG_ALPHA_EB164" = "y" -o "$CONFIG_ALPHA_PC164" = "y" \
-	-o "$CONFIG_ALPHA_ALCOR" = "y" -o "$CONFIG_ALPHA_TAKARA" = "y" ]
+if [ "$CONFIG_ALPHA_ALCOR" = "y" ]
 then
 	define_bool CONFIG_ALPHA_EV5 y
 	define_bool CONFIG_ALPHA_CIA y
+	bool 'EV56 CPU (speed >= 366MHz)?' CONFIG_ALPHA_EV56
 fi
-if [ "$CONFIG_ALPHA_MIKASA" = "y" -o "$CONFIG_ALPHA_NORITAKE" = "y" ]
+if [ "$CONFIG_ALPHA_EB164" = "y" ]
+then
+	define_bool CONFIG_ALPHA_EV5 y
+	define_bool CONFIG_ALPHA_CIA y
+fi
+if [ "$CONFIG_ALPHA_PC164" = "y" -o "$CONFIG_ALPHA_TAKARA" = "y" ]
+then
+	define_bool CONFIG_ALPHA_EV5 y
+	define_bool CONFIG_ALPHA_EV56 y
+	define_bool CONFIG_ALPHA_CIA y
+fi
+if [ "$CONFIG_ALPHA_MIKASA" = "y" ]
 then
 	bool 'EV5 CPU daughtercard (model 5/xxx)?' CONFIG_ALPHA_PRIMO
 	if [ "$CONFIG_ALPHA_PRIMO" = "y" ]
 	then
 		define_bool CONFIG_ALPHA_EV5 y
 		define_bool CONFIG_ALPHA_CIA y
+		bool 'EV56 CPU (speed >= 333MHz)?' CONFIG_ALPHA_EV56
+	else
+		define_bool CONFIG_ALPHA_EV4 y
+		define_bool CONFIG_ALPHA_APECS y
+	fi
+fi
+if [ "$CONFIG_ALPHA_NORITAKE" = "y" ]
+then
+	bool 'EV5 CPU (model 5/xxx)?' CONFIG_ALPHA_PRIMO
+	if [ "$CONFIG_ALPHA_PRIMO" = "y" ]
+	then
+		define_bool CONFIG_ALPHA_EV5 y
+		define_bool CONFIG_ALPHA_CIA y
+		bool 'EV56 CPU (speed >= 333MHz)?' CONFIG_ALPHA_EV56
 	else
 		define_bool CONFIG_ALPHA_EV4 y
 		define_bool CONFIG_ALPHA_APECS y
@@ -135,6 +160,7 @@
 	-o "$CONFIG_ALPHA_SX164" = "y" -o "$CONFIG_ALPHA_RUFFIAN" = "y" ]
 then
 	define_bool CONFIG_ALPHA_EV5 y
+	define_bool CONFIG_ALPHA_EV56 y
 	define_bool CONFIG_ALPHA_CIA y
 	define_bool CONFIG_ALPHA_PYXIS y
 fi
@@ -159,10 +185,12 @@
 then
 	define_bool CONFIG_ALPHA_EV5 y
 	define_bool CONFIG_ALPHA_MCPCIA y
+	bool 'EV56 CPU (speed >= 400MHz)?' CONFIG_ALPHA_EV56
 fi
 if [ "$CONFIG_ALPHA_RX164" = "y" ]
 then
 	define_bool CONFIG_ALPHA_EV5 y
+	define_bool CONFIG_ALPHA_EV56 y
 	define_bool CONFIG_ALPHA_POLARIS y
 fi
 if [ "$CONFIG_ALPHA_JENSEN" = "y" ]
@@ -250,11 +278,15 @@
 	"ELF		CONFIG_KCORE_ELF	\
 	 A.OUT		CONFIG_KCORE_AOUT" ELF
 fi
-if [ "$CONFIG_PROC_FS" != "n" -a "$CONFIG_ALPHA_SRM" = "y" ]; then
+if [ "$CONFIG_PROC_FS" != "n" ]; then
    tristate 'SRM environment through procfs' CONFIG_SRM_ENV
 fi
  
 tristate 'Kernel support for a.out (ECOFF) binaries' CONFIG_BINFMT_AOUT
+if [ "$CONFIG_BINFMT_AOUT" != "n" ]; then
+	bool '  OSF/1 v4 readv/writev compatibility' CONFIG_OSF4_COMPAT
+fi
+
 tristate 'Kernel support for ELF binaries' CONFIG_BINFMT_ELF
 tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
 tristate 'Kernel support for Linux/Intel ELF binaries' CONFIG_BINFMT_EM86
@@ -371,9 +403,7 @@
 source drivers/usb/Config.in
 source drivers/input/Config.in
 
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
-   source net/bluetooth/Config.in
-fi
+source net/bluetooth/Config.in
 
 mainmenu_option next_comment
 comment 'Kernel hacking'
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/alpha_ksyms.c linux/arch/alpha/kernel/alpha_ksyms.c
--- linux.orig/arch/alpha/kernel/alpha_ksyms.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/alpha/kernel/alpha_ksyms.c	2002-08-01 06:42:31.000000000 +0000
@@ -58,11 +58,12 @@
 EXPORT_SYMBOL(probe_irq_mask);
 EXPORT_SYMBOL(screen_info);
 EXPORT_SYMBOL(perf_irq);
-#ifdef CONFIG_ALPHA_SRM
 EXPORT_SYMBOL(callback_getenv);
 EXPORT_SYMBOL(callback_setenv);
 EXPORT_SYMBOL(callback_save_env);
-#endif /* CONFIG_ALPHA_SRM */
+#ifdef CONFIG_ALPHA_GENERIC
+EXPORT_SYMBOL(alpha_using_srm);
+#endif /* CNFIG_ALPHA_GENERIC */
 
 /* platform dependent support */
 EXPORT_SYMBOL(_inb);
@@ -214,6 +215,7 @@
 EXPORT_SYMBOL(smp_imb);
 EXPORT_SYMBOL(cpu_data);
 EXPORT_SYMBOL(__cpu_number_map);
+EXPORT_SYMBOL(__cpu_logical_map);
 EXPORT_SYMBOL(smp_num_cpus);
 EXPORT_SYMBOL(smp_call_function);
 EXPORT_SYMBOL(smp_call_function_on_cpu);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/entry.S linux/arch/alpha/kernel/entry.S
--- linux.orig/arch/alpha/kernel/entry.S	2001-11-09 21:45:35.000000000 +0000
+++ linux/arch/alpha/kernel/entry.S	2002-08-01 06:42:27.000000000 +0000
@@ -10,7 +10,7 @@
 
 #define SIGCHLD 20
 
-#define NR_SYSCALLS 378
+#define NR_SYSCALLS 382
 
 /*
  * These offsets must match with alpha_mv in <asm/machvec.h>.
@@ -886,8 +886,13 @@
 	.quad osf_getrusage
 	.quad sys_getsockopt
 	.quad alpha_ni_syscall
+#ifdef CONFIG_OSF4_COMPAT
+	.quad osf_readv				/* 120 */
+	.quad osf_writev
+#else
 	.quad sys_readv				/* 120 */
 	.quad sys_writev
+#endif
 	.quad osf_settimeofday
 	.quad sys_fchown
 	.quad sys_fchmod
@@ -1148,3 +1153,9 @@
 	.quad sys_gettid
 	.quad sys_readahead
 	.quad sys_ni_syscall			/* 380, sys_security */
+	.quad sys_tkill
+
+/* Remember to update everything, kids.  */
+.ifne (. - sys_call_table) - (NR_SYSCALLS * 8)
+.err
+.endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/osf_sys.c linux/arch/alpha/kernel/osf_sys.c
--- linux.orig/arch/alpha/kernel/osf_sys.c	2001-11-03 01:39:20.000000000 +0000
+++ linux/arch/alpha/kernel/osf_sys.c	2002-08-01 06:42:27.000000000 +0000
@@ -219,8 +219,8 @@
 	 * isn't actually going to matter, as if the parent happens
 	 * to change we can happily return either of the pids.
 	 */
-	(&regs)->r20 = tsk->p_opptr->pid;
-	return tsk->pid;
+	(&regs)->r20 = tsk->p_opptr->tgid;
+	return tsk->tgid;
 }
 
 asmlinkage unsigned long osf_mmap(unsigned long addr, unsigned long len,
@@ -1384,3 +1384,44 @@
 
 	return addr;
 }
+
+#ifdef CONFIG_OSF4_COMPAT
+extern ssize_t sys_readv(unsigned long, const struct iovec *, unsigned long);
+extern ssize_t sys_writev(unsigned long, const struct iovec *, unsigned long);
+
+/* Clear top 32 bits of iov_len in the user's buffer for
+   compatibility with old versions of OSF/1 where iov_len
+   was defined as int. */
+static int
+osf_fix_iov_len(const struct iovec *iov, unsigned long count)
+{
+	unsigned long i;
+
+	for (i = 0 ; i < count ; i++) {
+		int *iov_len_high = (int *)&iov[i].iov_len + 1;
+
+		if (put_user(0, iov_len_high))
+			return -EFAULT;
+	}
+	return 0;
+}
+
+asmlinkage ssize_t
+osf_readv(unsigned long fd, const struct iovec * vector, unsigned long count)
+{
+	if (unlikely(personality(current->personality) == PER_OSF4))
+		if (osf_fix_iov_len(vector, count))
+			return -EFAULT;
+	return sys_readv(fd, vector, count);
+}
+
+asmlinkage ssize_t
+osf_writev(unsigned long fd, const struct iovec * vector, unsigned long count)
+{
+	if (unlikely(personality(current->personality) == PER_OSF4))
+		if (osf_fix_iov_len(vector, count))
+			return -EFAULT;
+	return sys_writev(fd, vector, count);
+}
+
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/pci_iommu.c linux/arch/alpha/kernel/pci_iommu.c
--- linux.orig/arch/alpha/kernel/pci_iommu.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/alpha/kernel/pci_iommu.c	2002-08-01 06:42:48.000000000 +0000
@@ -217,9 +217,14 @@
 	}
 
 	/* If the machine doesn't define a pci_tbi routine, we have to
-	   assume it doesn't support sg mapping.  */
+	   assume it doesn't support sg mapping, and, since we tried to
+	   use direct_map above, it now must be considered an error. */
 	if (! alpha_mv.mv_pci_tbi) {
-		printk(KERN_WARNING "pci_map_single failed: no hw sg\n");
+		static int been_here = 0; /* Only print the message once. */
+		if (!been_here) {
+		    printk(KERN_WARNING "pci_map_single: no HW sg\n");
+		    been_here = 1;
+		}
 		return 0;
 	}
 		
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/setup.c linux/arch/alpha/kernel/setup.c
--- linux.orig/arch/alpha/kernel/setup.c	2001-11-17 02:38:39.000000000 +0000
+++ linux/arch/alpha/kernel/setup.c	2002-08-01 06:42:34.000000000 +0000
@@ -440,12 +440,6 @@
         return MKDEV(TTY_MAJOR, 64 + c->index);
 }
 
-static int srm_console_wait_key(struct console *co)
-{
-  /* Huh? */
-	return 1;
-}
-
 static int __init srm_console_setup(struct console *co, char *options)
 {
 	return 1;
@@ -455,7 +449,6 @@
 	name:		"srm0",
 	write:		srm_console_write,
 	device:		srm_console_device,
-	wait_key:	srm_console_wait_key,
 	setup:		srm_console_setup,
 	flags:		CON_PRINTBUFFER | CON_ENABLED, /* fake it out */
 	index:		-1,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/signal.c linux/arch/alpha/kernel/signal.c
--- linux.orig/arch/alpha/kernel/signal.c	2001-11-09 21:45:35.000000000 +0000
+++ linux/arch/alpha/kernel/signal.c	2002-08-01 06:42:43.000000000 +0000
@@ -717,9 +717,7 @@
 
 			default:
 				lock_kernel();
-				sigaddset(&current->pending.signal, signr);
-				current->flags |= PF_SIGNALED;
-				do_exit(exit_code);
+				sig_exit(signr, exit_code, &info);
 				/* NOTREACHED */
 			}
 			continue;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/smp.c linux/arch/alpha/kernel/smp.c
--- linux.orig/arch/alpha/kernel/smp.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/alpha/kernel/smp.c	2002-08-01 06:42:37.000000000 +0000
@@ -184,9 +184,23 @@
 	 */
 	wait_boot_cpu_to_stop(cpuid);
 	mb();
+ try_again:
 	calibrate_delay();
 
 	smp_store_cpu_info(cpuid);
+
+	{
+#define LPJ(c) ((long)cpu_data[c].loops_per_jiffy)
+	  static int tries = 3;
+	  long diff = LPJ(boot_cpuid) - LPJ(cpuid);
+	  if (diff < 0) diff = -diff;
+				
+	  if (diff > LPJ(boot_cpuid)/10 && --tries) {
+	    printk("Bogus BogoMIPS for cpu %d - retrying...\n", cpuid);
+	    goto try_again;
+	  }
+	}
+
 	/*
 	 * Allow master to continue only after we written
 	 * the loops_per_jiffy.
@@ -1065,7 +1079,8 @@
 }
 
 void
-flush_icache_page(struct vm_area_struct *vma, struct page *page)
+flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+			unsigned long addr, int len)
 {
 	struct mm_struct *mm = vma->vm_mm;
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/kernel/srm_env.c linux/arch/alpha/kernel/srm_env.c
--- linux.orig/arch/alpha/kernel/srm_env.c	2001-10-21 17:20:57.000000000 +0000
+++ linux/arch/alpha/kernel/srm_env.c	2002-08-01 06:42:33.000000000 +0000
@@ -1,27 +1,20 @@
 /*
- * srm_env.c - Access to SRC environment variables through
- *             the linux procfs
+ * srm_env.c - Access to SRM environment
+ *             variables through linux' procfs
  *
- * (C)2001, Jan-Benedict Glaw <jbglaw@lug-owl.de>
+ * Copyright (C) 2001-2002 Jan-Benedict Glaw <jbglaw@lug-owl.de>
  *
  * This driver is at all a modified version of Erik Mouw's
- * ./linux/Documentation/DocBook/procfs_example.c, so: thanky
+ * ./linux/Documentation/DocBook/procfs_example.c, so: thank
  * you, Erik! He can be reached via email at
  * <J.A.K.Mouw@its.tudelft.nl>. It is based on an idea
- * provided by DEC^WCompaq's "Jumpstart" CD. They included
- * a patch like this as well. Thanks for idea!
- *
- *
- * This software has been developed while working on the LART
- * computing board (http://www.lart.tudelft.nl/). The
- * development has been sponsored by the Mobile Multi-media
- * Communications (http://www.mmc.tudelft.nl/) and Ubiquitous
- * Communications (http://www.ubicom.tudelft.nl/) projects.
+ * provided by DEC^WCompaq^WIntel's "Jumpstart" CD. They
+ * included a patch like this as well. Thanks for idea!
  *
  * This program is free software; you can redistribute
  * it and/or modify it under the terms of the GNU General
- * Public License as published by the Free Software
- * Foundation version 2.
+ * Public License version 2 as published by the Free Software
+ * Foundation.
  *
  * This program is distributed in the hope that it will be
  * useful, but WITHOUT ANY WARRANTY; without even the implied
@@ -36,6 +29,24 @@
  *
  */
 
+/*
+ * Changelog
+ * ~~~~~~~~~
+ *
+ * Wed, 22 May 2002 00:11:21 +0200
+ * 	- Fix typo on comment (SRC -> SRM)
+ * 	- Call this "Version 0.0.4"
+ *
+ * Tue,  9 Apr 2002 18:44:40 +0200
+ * 	- Implement access by variable name and additionally
+ * 	  by number. This is done by creating two subdirectories
+ * 	  where one holds all names (like the old directory
+ * 	  did) and the other holding 256 files named like "0",
+ * 	  "1" and so on.
+ * 	- Call this "Version 0.0.3"
+ *
+ */
+
 #include <linux/kernel.h>
 #include <linux/config.h>
 #include <linux/module.h>
@@ -43,11 +54,13 @@
 #include <linux/proc_fs.h>
 #include <asm/console.h>
 #include <asm/uaccess.h>
+#include <asm/machvec.h>
 
-#define DIRNAME		"srm_environment"	/* Subdir in /proc/	*/
-#define VERSION		"0.0.2"			/* Module version	*/
-#define NAME		"srm_env"		/* Module name		*/
-#define DEBUG
+#define BASE_DIR	"srm_environment"	/* Subdir in /proc/		*/
+#define NAMED_DIR	"named_variables"	/* Subdir for known variables	*/
+#define NUMBERED_DIR	"numbered_variables"	/* Subdir for all variables	*/
+#define VERSION		"0.0.4"			/* Module version		*/
+#define NAME		"srm_env"		/* Module name			*/
 
 MODULE_AUTHOR("Jan-Benedict Glaw <jbglaw@lug-owl.de>");
 MODULE_DESCRIPTION("Accessing Alpha SRM environment through procfs interface");
@@ -60,8 +73,12 @@
 	struct proc_dir_entry	*proc_entry;
 } srm_env_t;
 
-static struct proc_dir_entry	*directory;
-static srm_env_t	srm_entries[] = {
+static struct proc_dir_entry	*base_dir;
+static struct proc_dir_entry	*named_dir;
+static struct proc_dir_entry	*numbered_dir;
+static char			number[256][4];
+
+static srm_env_t	srm_named_entries[] = {
 	{ "auto_action",	ENV_AUTO_ACTION		},
 	{ "boot_dev",		ENV_BOOT_DEV		},
 	{ "bootdef_dev",	ENV_BOOTDEF_DEV		},
@@ -79,10 +96,11 @@
 	{ "tty_dev",		ENV_TTY_DEV		},
 	{ NULL,			0			},
 };
+static srm_env_t	srm_numbered_entries[256];
 
-static int srm_env_read(char *page, char **start, off_t off, int count,
-		int *eof, void *data)
-{
+static int
+srm_env_read(char *page, char **start, off_t off, int count, int *eof,
+		void *data) {
 	int		nbytes;
 	unsigned long	ret;
 	srm_env_t	*entry;
@@ -107,10 +125,9 @@
 	return nbytes;
 }
 
-
-static int srm_env_write(struct file *file, const char *buffer,
-		unsigned long count, void *data)
-{
+static int
+srm_env_write(struct file *file, const char *buffer, unsigned long count,
+		void *data) {
 #define BUFLEN	512
 	int		nbytes;
 	srm_env_t	*entry;
@@ -126,8 +143,8 @@
 		MOD_DEC_USE_COUNT;
 		return -ENOMEM;
 	}
-		
-	//memcpy(aligned_buffer, buffer, nbytes)
+
+	/* memcpy(aligned_buffer, buffer, nbytes) */
 
 	if(copy_from_user(buf, buffer, count)) {
 		MOD_DEC_USE_COUNT;
@@ -149,55 +166,142 @@
 	return nbytes;
 }
 
-static void srm_env_cleanup(void)
-{
+static void
+srm_env_cleanup(void) {
 	srm_env_t	*entry;
+	unsigned long	var_num;
 
-	if(directory) {
-		entry = srm_entries;
-		while(entry->name != NULL && entry->id != 0) {
-			if(entry->proc_entry) {
-				remove_proc_entry(entry->name, directory);
-				entry->proc_entry = NULL;
+	if(base_dir) {
+		/*
+		 * Remove named entries
+		 */
+		if(named_dir) {
+			entry = srm_named_entries;
+			while(entry->name != NULL && entry->id != 0) {
+				if(entry->proc_entry) {
+					remove_proc_entry(entry->name,
+							named_dir);
+					entry->proc_entry = NULL;
+				}
+				entry++;
 			}
-			entry++;
+			remove_proc_entry(NAMED_DIR, base_dir);
 		}
-		remove_proc_entry(DIRNAME, NULL);
+
+		/*
+		 * Remove numbered entries
+		 */
+		if(numbered_dir) {
+			for(var_num = 0; var_num <= 255; var_num++) {
+				entry =	&srm_numbered_entries[var_num];
+
+				if(entry->proc_entry) {
+					remove_proc_entry(entry->name,
+							numbered_dir);
+					entry->proc_entry	= NULL;
+					entry->name		= NULL;
+				}
+			}
+			remove_proc_entry(NUMBERED_DIR, base_dir);
+		}
+
+		remove_proc_entry(BASE_DIR, NULL);
 	}
 
 	return;
 }
 
-static int __init srm_env_init(void)
-{
+static int __init
+srm_env_init(void) {
 	srm_env_t	*entry;
-	
+	unsigned long	var_num;
+
+	/*
+	 * Check system
+	 */
 	if(!alpha_using_srm) {
 		printk(KERN_INFO "%s: This Alpha system doesn't "
 				"know about SRM...\n", __FUNCTION__);
 		return -ENODEV;
 	}
 
-	directory = proc_mkdir(DIRNAME, NULL);
-	if(directory == NULL)
-		return -ENOMEM;
-	
-	directory->owner = THIS_MODULE;
-	
-	/* Now create all the nodes... */
-	entry = srm_entries;
+	/*
+	 * Init numbers
+	 */
+	for(var_num = 0; var_num <= 255; var_num++)
+		sprintf(number[var_num], "%ld", var_num);
+
+	/*
+	 * Create base directory
+	 */
+	base_dir = proc_mkdir(BASE_DIR, NULL);
+	if(base_dir == NULL) {
+		printk(KERN_ERR "Couldn't create base dir /proc/%s\n",
+				BASE_DIR);
+		goto cleanup;
+	}
+	base_dir->owner = THIS_MODULE;
+
+	/*
+	 * Create per-name subdirectory
+	 */
+	named_dir = proc_mkdir(NAMED_DIR, base_dir);
+	if(named_dir == NULL) {
+		printk(KERN_ERR "Couldn't create dir /proc/%s/%s\n",
+				BASE_DIR, NAMED_DIR);
+		goto cleanup;
+	}
+	named_dir->owner = THIS_MODULE;
+
+	/*
+	 * Create per-number subdirectory
+	 */
+	numbered_dir = proc_mkdir(NUMBERED_DIR, base_dir);
+	if(numbered_dir == NULL) {
+		printk(KERN_ERR "Couldn't create dir /proc/%s/%s\n",
+				BASE_DIR, NUMBERED_DIR);
+		goto cleanup;
+
+	}
+	numbered_dir->owner = THIS_MODULE;
+
+	/*
+	 * Create all named nodes
+	 */
+	entry = srm_named_entries;
 	while(entry->name != NULL && entry->id != 0) {
-		entry->proc_entry = create_proc_entry(entry->name, 0644,
-				directory);
+		entry->proc_entry = create_proc_entry(entry->name,
+				0644, named_dir);
 		if(entry->proc_entry == NULL)
 			goto cleanup;
-		entry->proc_entry->data		= entry;
+
+		entry->proc_entry->data		= (void *)entry;
+		entry->proc_entry->owner	= THIS_MODULE;
 		entry->proc_entry->read_proc	= srm_env_read;
 		entry->proc_entry->write_proc	= srm_env_write;
-		entry->proc_entry->owner	= THIS_MODULE;
+
 		entry++;
 	}
-	
+
+	/*
+	 * Create all numbered nodes
+	 */
+	for(var_num = 0; var_num <= 255; var_num++) {
+		entry = &srm_numbered_entries[var_num];
+		entry->name = number[var_num];
+
+		entry->proc_entry = create_proc_entry(entry->name,
+				0644, numbered_dir);
+		if(entry->proc_entry == NULL)
+			goto cleanup;
+
+		entry->id			= var_num;
+		entry->proc_entry->data		= (void *)entry;
+		entry->proc_entry->owner	= THIS_MODULE;
+		entry->proc_entry->read_proc	= srm_env_read;
+		entry->proc_entry->write_proc	= srm_env_write;
+	}
+
 	printk(KERN_INFO "%s: version %s loaded successfully\n", NAME,
 			VERSION);
 	return 0;
@@ -207,9 +311,8 @@
 	return -ENOMEM;
 }
 
-
-static void __exit srm_env_exit(void)
-{
+static void __exit
+srm_env_exit(void) {
 	srm_env_cleanup();
 	printk(KERN_INFO "%s: unloaded successfully\n", NAME);
 	return;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/lib/ev6-memset.S linux/arch/alpha/lib/ev6-memset.S
--- linux.orig/arch/alpha/lib/ev6-memset.S	2000-12-11 21:46:26.000000000 +0000
+++ linux/arch/alpha/lib/ev6-memset.S	2002-08-01 06:42:31.000000000 +0000
@@ -236,7 +236,7 @@
 	 * entry point.
 	 */
 .align 4
-	.ent __memset
+	.ent __constant_c_memset
 __constant_c_memset:
 	.frame $30,0,$26,0
 	.prologue 0
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/math-emu/math.c linux/arch/alpha/math-emu/math.c
--- linux.orig/arch/alpha/math-emu/math.c	2000-09-22 20:54:09.000000000 +0000
+++ linux/arch/alpha/math-emu/math.c	2002-08-01 06:42:48.000000000 +0000
@@ -220,12 +220,12 @@
 				FP_CONV(S,D,1,1,SR,DB);
 				goto pack_s;
 			} else {
-				/* CVTST need do nothing else but copy the
-				   bits and repack.  */
+				vb = alpha_read_fp_reg_s(fb);
+				FP_UNPACK_SP(SB, &vb);
 				DR_c = DB_c;
 				DR_s = DB_s;
 				DR_e = DB_e;
-				DR_f = DB_f;
+				DR_f = SB_f << (52 - 23);
 				goto pack_d;
 			}
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/mm/init.c linux/arch/alpha/mm/init.c
--- linux.orig/arch/alpha/mm/init.c	2001-09-21 03:02:03.000000000 +0000
+++ linux/arch/alpha/mm/init.c	2002-08-01 06:42:40.000000000 +0000
@@ -380,7 +380,7 @@
 		free_page(addr);
 		totalram_pages++;
 	}
-	printk ("Freeing unused kernel memory: %ldk freed\n",
+	printk (KERN_INFO "Freeing unused kernel memory: %ldk freed\n",
 		(&__init_end - &__init_begin) >> 10);
 }
 
@@ -395,7 +395,7 @@
 		free_page(start);
 		totalram_pages++;
 	}
-	printk ("Freeing initrd memory: %ldk freed\n", (end - __start) >> 10);
+	printk (KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - __start) >> 10);
 }
 #endif
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/alpha/mm/numa.c linux/arch/alpha/mm/numa.c
--- linux.orig/arch/alpha/mm/numa.c	2001-08-12 17:38:48.000000000 +0000
+++ linux/arch/alpha/mm/numa.c	2002-08-01 06:42:29.000000000 +0000
@@ -312,7 +312,7 @@
 		printk(".");				\
 } while(0)
 
-#define clobber(p, size) memset((p)->virtual, 0xaa, (size))
+#define clobber(p, size) memset(page_address(p), 0xaa, (size))
 
 void __init mem_stress(void)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/Makefile linux/arch/arm/Makefile
--- linux.orig/arch/arm/Makefile	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/arm/Makefile	2002-08-01 06:42:40.000000000 +0000
@@ -11,10 +11,6 @@
 GZFLAGS		:=-9
 CFLAGS		+=-fno-common -pipe
 
-ifneq ($(CONFIG_NO_FRAME_POINTER),y)
-CFLAGS		:=$(CFLAGS:-fomit-frame-pointer=)
-endif
-
 ifeq ($(CONFIG_DEBUG_INFO),y)
 CFLAGS		+=-g
 endif
@@ -39,10 +35,12 @@
 tune-$(CONFIG_CPU_ARM710)	:=-mtune=arm710
 tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM922T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_SA110)	:=-mtune=strongarm110
 tune-$(CONFIG_CPU_SA1100)	:=-mtune=strongarm1100
 
+CFLAGS_BOOT	:=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float
 CFLAGS		+=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float
 AFLAGS		+=$(apcs-y) $(arch-y) -mno-fpu -msoft-float
 
@@ -74,6 +72,8 @@
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 MACHINE		 = ebsa110
+CFLAGS_3c589_cs	:=-DISA_SIXTEEN_BIT_PERIPHERAL
+export CFLAGS_3c589_cs
 endif
 
 ifeq ($(CONFIG_ARCH_CLPS7500),y)
@@ -121,6 +121,10 @@
 MACHINE		 = integrator
 endif
 
+ifeq ($(CONFIG_ARCH_MX1ADS),y)
+MACHINE		 = mx1ads
+endif
+
 ifeq ($(CONFIG_ARCH_CAMELOT),y)
 MACHINE          = epxa10db
 endif
@@ -130,11 +134,15 @@
 MACHINE		 = clps711x
 endif
 
+ifeq ($(CONFIG_ARCH_FORTUNET),y)
+TEXTADDR	 = 0xc0008000
+endif
+
 ifeq ($(CONFIG_ARCH_ANAKIN),y)
 MACHINE		 = anakin
 endif
 
-export	MACHINE PROCESSOR TEXTADDR GZFLAGS
+export	MACHINE PROCESSOR TEXTADDR GZFLAGS CFLAGS_BOOT
 
 # Only set INCDIR if its not already defined above
 # Grr, ?= doesn't work as all the other assignment operators do.  Make bug?
@@ -207,6 +215,7 @@
 	arch/arm/vmlinux.lds
 
 MRPROPER_FILES	+= \
+	arch/arm/tools/constants.h* \
 	include/asm-arm/arch \
 	include/asm-arm/proc \
 	include/asm-arm/constants.h* \
@@ -254,7 +263,7 @@
 	@( \
 	CFG=$(@:_config=); \
 	if [ -f arch/arm/def-configs/$$CFG ]; then \
-	  [ -f .config ] && $(MV) .config .config.old; \
+	  [ -f .config ] && mv -f .config .config.old; \
 	  cp arch/arm/def-configs/$$CFG .config; \
 	  echo "*** Default configuration for $$CFG installed"; \
 	  echo "*** Next, you may run 'make oldconfig'"; \
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/Makefile linux/arch/arm/boot/Makefile
--- linux.orig/arch/arm/boot/Makefile	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/boot/Makefile	2002-08-01 06:42:32.000000000 +0000
@@ -54,6 +54,14 @@
 INITRD_VIRT	 = 0xc0800000
 endif
 
+ifeq ($(CONFIG_ARCH_MX1ADS),y)
+ZTEXTADDR	 = 0x08008000
+endif
+
+ifeq ($(CONFIG_ARCH_CAMELOT),y)
+ZTEXTADDR	 = 0x00008000
+endif
+
 ifeq ($(CONFIG_ARCH_NEXUSPCI),y)
 ZTEXTADDR	 = 0x40008000
 endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/Makefile linux/arch/arm/boot/compressed/Makefile
--- linux.orig/arch/arm/boot/compressed/Makefile	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/boot/compressed/Makefile	2002-08-01 06:42:33.000000000 +0000
@@ -9,7 +9,7 @@
 
 HEAD		 = head.o
 OBJS		 = misc.o
-CFLAGS		 = $(CPPFLAGS) -O2 -DSTDC_HEADERS $(CFLAGS_PROC) -msoft-float
+CFLAGS		 = $(CPPFLAGS) -O2 -DSTDC_HEADERS $(CFLAGS_BOOT)
 FONTC		 = $(TOPDIR)/drivers/video/font_acorn_8x8.c
 ZLDFLAGS	 = -p -X -T vmlinux.lds
 
@@ -33,6 +33,14 @@
 OBJS		+= head-integrator.o
 endif
 
+ifeq ($(CONFIG_ARCH_MX1ADS),y)
+OBJS		+= head-mx1ads.o
+endif
+
+ifeq ($(CONFIG_ARCH_CAMELOT),y)
+OBJS		+= head-epxa10db.o
+endif
+
 ifeq ($(CONFIG_ARCH_FTVPCI),y)
 OBJS		+= head-ftvpci.o
 endif
@@ -84,12 +92,12 @@
 font.o:		$(FONTC)
 		$(CC) $(CFLAGS) -Dstatic= -c -o $@ $(FONTC)
 
-vmlinux.lds:	vmlinux.lds.in
+vmlinux.lds:	vmlinux.lds.in Makefile $(TOPDIR)/arch/$(ARCH)/boot/Makefile $(TOPDIR)/.config
 		@sed "$(SEDFLAGS)" < vmlinux.lds.in > $@
 
 clean:;		rm -f vmlinux core piggy* vmlinux.lds
 
-.PHONY:	vmlinux.lds clean
+.PHONY:	clean
 
 misc.o: misc.c $(TOPDIR)/include/asm/arch/uncompress.h $(TOPDIR)/lib/inflate.c
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/head-epxa10db.S linux/arch/arm/boot/compressed/head-epxa10db.S
--- linux.orig/arch/arm/boot/compressed/head-epxa10db.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/boot/compressed/head-epxa10db.S	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,5 @@
+#include <asm/mach-types.h>
+#include <asm/arch/excalibur.h>
+
+		.section	".start", #alloc, #execinstr
+		mov	r7, #MACH_TYPE_CAMELOT
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/head-mx1ads.S linux/arch/arm/boot/compressed/head-mx1ads.S
--- linux.orig/arch/arm/boot/compressed/head-mx1ads.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/boot/compressed/head-mx1ads.S	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,4 @@
+#include <asm/mach-types.h>
+
+		.section	".start", #alloc, #execinstr
+		mov	r7, #MACH_TYPE_MX1ADS
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/head-shark.S linux/arch/arm/boot/compressed/head-shark.S
--- linux.orig/arch/arm/boot/compressed/head-shark.S	2001-04-12 19:03:50.000000000 +0000
+++ linux/arch/arm/boot/compressed/head-shark.S	2002-08-01 06:42:37.000000000 +0000
@@ -1,5 +1,5 @@
 /* The head-file for the Shark
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
  *
  * Does the following:
  * - get the memory layout from firmware. This can only be done as long as the mmu
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/head.S linux/arch/arm/boot/compressed/head.S
--- linux.orig/arch/arm/boot/compressed/head.S	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/boot/compressed/head.S	2002-08-01 06:42:47.000000000 +0000
@@ -18,14 +18,14 @@
  * Please select one of the following when turning on debugging.
  */
 #ifdef DEBUG
-#if 0 /* DC21285-type */
+#if defined(CONFIG_DEBUG_DC21285_PORT)
 		.macro	loadsp,	rb
 		mov	\rb, #0x7c000000
 		.endm
 		.macro	writeb,	rb
 		strb	\rb, [r3, #0x3f8]
 		.endm
-#elif 0 /* RiscPC-type */
+#elif defined(CONFIG_ARCH_RPC)
 		.macro	loadsp,	rb
 		mov	\rb, #0x03000000
 		orr	\rb, \rb, #0x00010000
@@ -33,13 +33,25 @@
 		.macro	writeb,	rb
 		strb	\rb, [r3, #0x3f8 << 2]
 		.endm
-#elif 0 /* integrator-type */
+#elif defined(CONFIG_ARCH_INTEGRATOR)
 		.macro	loadsp, rb
 		mov	\rb, #0x16000000
 		.endm
 		.macro	writeb, rb
 		strb	\rb, [r3, #0]
 		.endm
+#elif defined(CONFIG_ARCH_SA1100)
+		.macro	loadsp, rb
+		mov	\rb, #0x80000000	@ physical base address
+#  if defined(CONFIG_DEBUG_LL_SER3)
+		add	\rb, \rb, #0x00050000	@ Ser3
+#  else
+		add	\rb, \rb, #0x00010000	@ Ser1
+#  endif
+		.endm
+		.macro	writeb, rb
+		str	\rb, [r3, #0x14]	@ UTDR
+		.endm
 #else
 #error no serial architecture defined
 #endif
@@ -64,7 +76,7 @@
 		kphex	r7, 8		/* architecture id */
 		kputc	#':'
 		mrc	p15, 0, r0, c1, c0
-		kphex	r0, 8		/* control reg
+		kphex	r0, 8		/* control reg */
 		kputc	#'\n'
 		kphex	r5, 8		/* decompressed kernel start */
 		kputc	#'-'
@@ -218,7 +230,8 @@
 		ldr     r1, proc_sa1110_type
 		eor	r1, r1, r6
 		movs	r1, r1, lsr #4
-		movne	pc, lr
+@		movne	pc, lr
+		bne	cache_off
 1:
 		sub	r3, r4, #16384		@ Page directory size
 		bic	r3, r3, #0xff		@ Align the pointer
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/misc.c linux/arch/arm/boot/compressed/misc.c
--- linux.orig/arch/arm/boot/compressed/misc.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/boot/compressed/misc.c	2002-08-01 06:42:33.000000000 +0000
@@ -18,6 +18,8 @@
 
 unsigned int __machine_arch_type;
 
+#include <linux/kernel.h>
+
 #include <asm/uaccess.h>
 #include <asm/arch/uncompress.h>
 #include <asm/proc/uncompress.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/boot/compressed/ofw-shark.c linux/arch/arm/boot/compressed/ofw-shark.c
--- linux.orig/arch/arm/boot/compressed/ofw-shark.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/boot/compressed/ofw-shark.c	2002-08-01 06:42:44.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/boot/compressed/ofw-shark.c
  *
- * by Alexander Schulz <aschulz@netwinder.org>
+ * by Alexander Schulz
  *
  * This file is used to get some basic information
  * about the memory layout of the shark we are running
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/config.in linux/arch/arm/config.in
--- linux.orig/arch/arm/config.in	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/arm/config.in	2002-08-01 06:42:34.000000000 +0000
@@ -43,6 +43,7 @@
 	 FootBridge		CONFIG_ARCH_FOOTBRIDGE \
 	 Integrator		CONFIG_ARCH_INTEGRATOR \
 	 LinkUp-L7200		CONFIG_ARCH_L7200 \
+	 Motorola-MX1ADS        CONFIG_ARCH_MX1ADS \
 	 RiscPC			CONFIG_ARCH_RPC \
  	 SA1100-based		CONFIG_ARCH_SA1100 \
 	 Shark			CONFIG_ARCH_SHARK" RiscPC
@@ -85,7 +86,14 @@
          32MB   CONFIG_SA1100_CERF_FLASH_32MB" CerfFlash
    bool 'Cerf w/CPLD support (CerfPDA)' CONFIG_SA1100_CERF_CPLD
 fi
-dep_bool '  Compaq iPAQ H3600' CONFIG_SA1100_H3600 $CONFIG_ARCH_SA1100
+dep_bool '  Compaq iPAQ H3100' CONFIG_SA1100_H3100 $CONFIG_ARCH_SA1100
+dep_bool '  Compaq iPAQ H3600/H3700' CONFIG_SA1100_H3600 $CONFIG_ARCH_SA1100
+dep_bool '  Compaq iPAQ H3800' CONFIG_SA1100_H3800 $CONFIG_ARCH_SA1100
+if [ "$CONFIG_SA1100_H3100" = "y" -o "$CONFIG_SA1100_H3600" = "y" -o "$CONFIG_SA1100_H3800" = "y" ]; then
+  define_bool CONFIG_SA1100_H3XXX y
+else
+  define_bool CONFIG_SA1100_H3XXX n
+fi
 #dep_bool '  Empeg' CONFIG_SA1100_EMPEG $CONFIG_ARCH_SA1100
 dep_bool '  Extenex HandHeld Theater (Squashtail)' CONFIG_SA1100_EXTENEX1 $CONFIG_ARCH_SA1100
 if [ "$CONFIG_SA1100_EXTENEX1" = "y" ]; then
@@ -93,8 +101,10 @@
 fi
 dep_bool '  FlexaNet' CONFIG_SA1100_FLEXANET $CONFIG_ARCH_SA1100
 dep_bool '  FreeBird-v1.1' CONFIG_SA1100_FREEBIRD $CONFIG_ARCH_SA1100
+dep_bool '  Frodo' CONFIG_SA1100_FRODO $CONFIG_ARCH_SA1100
 dep_bool '  GraphicsClient Plus' CONFIG_SA1100_GRAPHICSCLIENT $CONFIG_ARCH_SA1100
 dep_bool '  GraphicsMaster' CONFIG_SA1100_GRAPHICSMASTER $CONFIG_ARCH_SA1100
+dep_bool '  HP Labs BadgePAD 4' CONFIG_SA1100_BADGE4 $CONFIG_ARCH_SA1100
 dep_bool '  HP Jornada 720' CONFIG_SA1100_JORNADA720 $CONFIG_ARCH_SA1100
 dep_bool '  HuW WebPanel' CONFIG_SA1100_HUW_WEBPANEL $CONFIG_ARCH_SA1100
 dep_bool '  Itsy' CONFIG_SA1100_ITSY $CONFIG_ARCH_SA1100
@@ -103,6 +113,8 @@
 dep_bool '  OmniMeter' CONFIG_SA1100_OMNIMETER $CONFIG_ARCH_SA1100
 dep_bool '  Pangolin' CONFIG_SA1100_PANGOLIN $CONFIG_ARCH_SA1100
 dep_bool '  PLEB' CONFIG_SA1100_PLEB $CONFIG_ARCH_SA1100
+dep_bool '  PT System 3' CONFIG_SA1100_PT_SYSTEM3 $CONFIG_ARCH_SA1100
+dep_bool '  Shannon' CONFIG_SA1100_SHANNON $CONFIG_ARCH_SA1100
 dep_bool '  Sherman' CONFIG_SA1100_SHERMAN $CONFIG_ARCH_SA1100
 dep_bool '  Simpad' CONFIG_SA1100_SIMPAD $CONFIG_ARCH_SA1100
 dep_bool '  Tulsa' CONFIG_SA1100_PFS168 $CONFIG_ARCH_SA1100
@@ -116,18 +128,28 @@
      "$CONFIG_SA1100_PFS168" = "y" -o \
      "$CONFIG_SA1100_XP860" = "y" -o \
      "$CONFIG_SA1100_GRAPHICSMASTER" = "y" -o \
-     "$CONFIG_SA1100_ADSBITSY" = "y" ]; then
+     "$CONFIG_SA1100_PT_SYSTEM3" = "y" -o \
+     "$CONFIG_SA1100_ADSBITSY" = "y" -o \
+     "$CONFIG_SA1100_BADGE4" = "y" ]; then
    define_bool CONFIG_SA1111 y
    define_int CONFIG_FORCE_MAX_ZONEORDER 9
 fi
+
+#dep_tristate 'SA1100 USB function support' CONFIG_SA1100_USB $CONFIG_ARCH_SA1100
+#dep_tristate '  Support for SA11x0 USB network link function' CONFIG_SA1100_USB_NETLINK $CONFIG_SA1100_USB
+#dep_tristate '  Support for SA11x0 USB character device emulation' CONFIG_SA1100_USB_CHAR $CONFIG_SA1100_USB
+
+dep_tristate 'Compaq iPAQ Handheld sleeve support' CONFIG_H3600_SLEEVE $CONFIG_SA1100_H3600
 endmenu
 
 mainmenu_option next_comment
 comment 'CLPS711X/EP721X Implementations'
+dep_bool '  AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X
 dep_bool '  CDB89712' CONFIG_ARCH_CDB89712 $CONFIG_ARCH_CLPS711X
 dep_bool '  CLEP7312' CONFIG_ARCH_CLEP7312 $CONFIG_ARCH_CLPS711X
 dep_bool '  EDB7211' CONFIG_ARCH_EDB7211 $CONFIG_ARCH_CLPS711X
 dep_bool '  P720T' CONFIG_ARCH_P720T $CONFIG_ARCH_CLPS711X
+dep_bool '  FORTUNET' CONFIG_ARCH_FORTUNET $CONFIG_ARCH_CLPS711X
 
 # XXX Maybe these should indicate register compatibility
 # instead of being mutually exclusive.
@@ -205,7 +227,7 @@
      "$CONFIG_ARCH_NEXUSPCI"   = "y" -o "$CONFIG_ARCH_CLPS711X" = "y" -o \
      "$CONFIG_ARCH_INTEGRATOR" = "y" -o "$CONFIG_ARCH_SA1100"   = "y" -o \
      "$CONFIG_ARCH_L7200"      = "y" -o "$CONFIG_ARCH_ANAKIN"	= "y" -o \
-     "$CONFIG_ARCH_CAMELOT"    = "y" ]; then
+     "$CONFIG_ARCH_CAMELOT"    = "y" -o "$CONFIG_ARCH_MX1ADS"   = "y" ]; then
    define_bool CONFIG_CPU_32v4 y
 else
    define_bool CONFIG_CPU_32v4 n
@@ -247,11 +269,17 @@
 fi
 
 # ARM920T
-if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
-   bool 'Support ARM920T processor' CONFIG_CPU_ARM920T
+if [ "$CONFIG_ARCH_MX1ADS" = "y" ]; then
+   define_bool CONFIG_CPU_ARM920T y
 else
-   define_bool CONFIG_CPU_ARM920T n
+   if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
+      bool 'Support ARM920T processor' CONFIG_CPU_ARM920T
+   else
+      define_bool CONFIG_CPU_ARM920T n
+   fi
 fi
+
+
 if [ "$CONFIG_CPU_ARM920T" = "y" ]; then
    bool '  ARM920T CPU idle' CONFIG_CPU_ARM920_CPU_IDLE
    bool '  ARM920T I-Cache on' CONFIG_CPU_ARM920_I_CACHE_ON
@@ -261,6 +289,21 @@
    fi
 fi
 
+# ARM922T
+if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then
+         define_bool CONFIG_CPU_ARM922T y
+else
+         define_bool CONFIG_CPU_ARM922T n
+fi
+if [ "$CONFIG_CPU_ARM922T" = "y" ]; then
+   bool '  ARM922T CPU idle' CONFIG_CPU_ARM922_CPU_IDLE
+   bool '  ARM922T I-Cache on' CONFIG_CPU_ARM922_I_CACHE_ON
+   bool '  ARM922T D-Cache on' CONFIG_CPU_ARM922_D_CACHE_ON
+   if [ "$CONFIG_CPU_ARM922_D_CACHE_ON" = "y" ] ; then
+      bool '  Force write through caches on ARM922T' CONFIG_CPU_ARM922_WRITETHROUGH
+   fi
+fi
+
 # ARM926T
 if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
    bool 'Support ARM926T processor' CONFIG_CPU_ARM926T
@@ -404,7 +447,8 @@
      "$CONFIG_ARCH_P720T" = "y" -o	     \
      "$CONFIG_ARCH_CDB89712" = "y" -o	     \
      "$CONFIG_ARCH_CAMELOT" = "y" -o	     \
-     "$CONFIG_ARCH_ANAKIN" = "y" ]; then
+     "$CONFIG_ARCH_ANAKIN" = "y"  -o         \
+     "$CONFIG_ARCH_MX1ADS" = "y" ]; then
    string 'Default kernel command string' CONFIG_CMDLINE ""
 fi
 if [ "$CONFIG_ARCH_NETWINDER" = "y" -o  \
@@ -554,7 +598,8 @@
         "$CONFIG_ARCH_TBOX" = "y" -o       \
         "$CONFIG_ARCH_CLPS7500" = "y" -o   \
         "$CONFIG_ARCH_P720T" = "y" -o      \
-        "$CONFIG_ARCH_ANAKIN" = "y" ]; then
+        "$CONFIG_ARCH_ANAKIN" = "y" -o      \
+	"$CONFIG_ARCH_MX1ADS" = "y" ]; then
       define_bool CONFIG_PC_KEYMAP y
    fi
    if [ "$CONFIG_ARCH_ACORN" != "y" -a "$CONFIG_ARCH_EBSA110" != "y" ]; then
@@ -584,25 +629,29 @@
 
 source drivers/usb/Config.in
 
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
-   source net/bluetooth/Config.in
-fi
+source net/bluetooth/Config.in
 
 mainmenu_option next_comment
 comment 'Kernel hacking'
 
-# Always compile kernel with framepointer (until 2.4 real comes out)
-# Bug reports aren't much use without this.
-bool 'Compile kernel without frame pointer' CONFIG_NO_FRAME_POINTER
-bool 'Verbose kernel error messages' CONFIG_DEBUG_ERRORS
+# RMK wants arm kernels compiled with frame pointers so hardwire this to y.  If
+# you know what you are doing and are willing to live without stack traces, you
+# can get a slightly smaller kernel by setting this option to n, but then RMK
+# will have to kill you ;).
+define_bool CONFIG_FRAME_POINTER y
 bool 'Verbose user fault messages' CONFIG_DEBUG_USER
 bool 'Include debugging information in kernel binary' CONFIG_DEBUG_INFO
-bool 'Debug memory allocations' CONFIG_DEBUG_SLAB
-bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ
-bool 'Spinlock debugging' CONFIG_DEBUG_SPINLOCK
 dep_bool 'Disable pgtable cache' CONFIG_NO_PGT_CACHE $CONFIG_CPU_26
+
+bool 'Kernel debugging' CONFIG_DEBUG_KERNEL
+dep_bool '  Debug memory allocations' CONFIG_DEBUG_SLAB $CONFIG_DEBUG_KERNEL
+dep_bool '  Magic SysRq key' CONFIG_MAGIC_SYSRQ $CONFIG_DEBUG_KERNEL
+dep_bool '  Spinlock debugging' CONFIG_DEBUG_SPINLOCK $CONFIG_DEBUG_KERNEL
+dep_bool '  Wait queue debugging' CONFIG_DEBUG_WAITQ $CONFIG_DEBUG_KERNEL
+dep_bool '  Verbose BUG() reporting (adds 70K)' CONFIG_DEBUG_BUGVERBOSE $CONFIG_DEBUG_KERNEL
+dep_bool '  Verbose kernel error messages' CONFIG_DEBUG_ERRORS $CONFIG_DEBUG_KERNEL
 # These options are only for real kernel hackers who want to get their hands dirty. 
-dep_bool 'Kernel low-level debugging functions' CONFIG_DEBUG_LL $CONFIG_EXPERIMENTAL
-dep_bool '  Kernel low-level debugging messages via footbridge serial port' CONFIG_DEBUG_DC21285_PORT $CONFIG_DEBUG_LL $CONFIG_FOOTBRIDGE
-dep_bool '  kernel low-level debugging messages via UART2' CONFIG_DEBUG_CLPS711X_UART2 $CONFIG_DEBUG_LL $CONFIG_ARCH_CLPS711X
+dep_bool '  Kernel low-level debugging functions' CONFIG_DEBUG_LL $CONFIG_DEBUG_KERNEL
+dep_bool '    Kernel low-level debugging messages via footbridge serial port' CONFIG_DEBUG_DC21285_PORT $CONFIG_DEBUG_LL $CONFIG_FOOTBRIDGE
+dep_bool '    Kernel low-level debugging messages via UART2' CONFIG_DEBUG_CLPS711X_UART2 $CONFIG_DEBUG_LL $CONFIG_ARCH_CLPS711X
 endmenu
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/adsbitsy linux/arch/arm/def-configs/adsbitsy
--- linux.orig/arch/arm/def-configs/adsbitsy	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/adsbitsy	2002-08-01 06:42:33.000000000 +0000
@@ -663,7 +663,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/anakin linux/arch/arm/def-configs/anakin
--- linux.orig/arch/arm/def-configs/anakin	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/anakin	2002-08-01 06:42:31.000000000 +0000
@@ -454,7 +454,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/assabet linux/arch/arm/def-configs/assabet
--- linux.orig/arch/arm/def-configs/assabet	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/assabet	2002-08-01 06:42:39.000000000 +0000
@@ -956,7 +956,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/badge4 linux/arch/arm/def-configs/badge4
--- linux.orig/arch/arm/def-configs/badge4	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/def-configs/badge4	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODVERSIONS=y
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+CONFIG_SA1100_BADGE4=y
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_PT_SYSTEM3 is not set
+# CONFIG_SA1100_SHANNON is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1111=y
+CONFIG_FORCE_MAX_ZONEORDER=9
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+# CONFIG_H3600_SLEEVE is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_FORTUNET is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+CONFIG_ISA=y
+# CONFIG_ISA_DMA is not set
+CONFIG_CPU_FREQ=y
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_PROBE=y
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_FASTFPE=m
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+# CONFIG_PM is not set
+CONFIG_ARTHUR=m
+CONFIG_CMDLINE="init=/linuxrc root=/dev/mtdblock3"
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+CONFIG_PARPORT=m
+# CONFIG_PARPORT_PC is not set
+# CONFIG_PARPORT_AMIGA is not set
+# CONFIG_PARPORT_MFC3 is not set
+# CONFIG_PARPORT_ATARI is not set
+# CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_SUNBPP is not set
+# CONFIG_PARPORT_OTHER is not set
+# CONFIG_PARPORT_1284 is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+CONFIG_MTD_CFI_B2=y
+# CONFIG_MTD_CFI_B4 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+# CONFIG_MTD_FORTUNET is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+# CONFIG_NET_ETHERNET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+CONFIG_NET_RADIO=y
+# CONFIG_STRIP is not set
+# CONFIG_WAVELAN is not set
+# CONFIG_ARLAN is not set
+# CONFIG_AIRONET4500 is not set
+# CONFIG_AIRONET4500_NONCS is not set
+# CONFIG_AIRONET4500_PROC is not set
+# CONFIG_AIRO is not set
+CONFIG_HERMES=y
+
+#
+# Wireless Pcmcia cards support
+#
+CONFIG_PCMCIA_HERMES=y
+CONFIG_AIRO_CS=m
+CONFIG_NET_WIRELESS=y
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+CONFIG_PCMCIA_3C589=y
+CONFIG_PCMCIA_3C574=m
+CONFIG_PCMCIA_FMVJ18X=m
+CONFIG_PCMCIA_PCNET=y
+CONFIG_PCMCIA_AXNET=m
+CONFIG_PCMCIA_NMCLAN=m
+CONFIG_PCMCIA_SMC91C92=m
+CONFIG_PCMCIA_XIRC2PS=m
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+CONFIG_NET_PCMCIA_RADIO=y
+CONFIG_PCMCIA_RAYCS=m
+CONFIG_PCMCIA_NETWAVE=m
+CONFIG_PCMCIA_WAVELAN=m
+# CONFIG_AIRONET4500_CS is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=y
+# CONFIG_IRNET is not set
+CONFIG_IRCOMM=y
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_NSC_FIR is not set
+# CONFIG_WINBOND_FIR is not set
+# CONFIG_TOSHIBA_FIR is not set
+# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
+CONFIG_SA1100_FIR=y
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=m
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=m
+CONFIG_BLK_DEV_IDESCSI=m
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+CONFIG_CHR_DEV_ST=m
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_SR_EXTRA_DEVS=2
+CONFIG_CHR_DEV_SG=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_SCSI_PCMCIA is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=115200
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_PRINTER is not set
+# CONFIG_PPDEV is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=m
+CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_PHILIPSPAR is not set
+CONFIG_I2C_ELV=m
+CONFIG_I2C_VELLEMAN=m
+# CONFIG_I2C_BIT_SA1100_GPIO is not set
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ELEKTOR=m
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_PROC=m
+
+#
+# L3 serial bus support
+#
+CONFIG_L3=y
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+
+#
+# Other L3 adapters
+#
+CONFIG_L3_SA1111=y
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_21285_WATCHDOG is not set
+# CONFIG_977_WATCHDOG is not set
+CONFIG_SA1100_WATCHDOG=m
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_I810_TCO is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=m
+CONFIG_SA1100_RTC=m
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+
+#
+# Video For Linux
+#
+CONFIG_VIDEO_PROC_FS=y
+# CONFIG_I2C_PARPORT is not set
+
+#
+# Video Adapters
+#
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_BWQCAM is not set
+# CONFIG_VIDEO_CQCAM is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_VIDEO_STRADIS is not set
+# CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIDEO_ZORAN_BUZ is not set
+# CONFIG_VIDEO_ZORAN_DC10 is not set
+# CONFIG_VIDEO_ZORAN_LML33 is not set
+# CONFIG_VIDEO_ZR36120 is not set
+# CONFIG_VIDEO_MEYE is not set
+# CONFIG_VIDEO_CYBERPRO is not set
+
+#
+# Radio Adapters
+#
+# CONFIG_RADIO_CADET is not set
+# CONFIG_RADIO_RTRACK is not set
+# CONFIG_RADIO_RTRACK2 is not set
+# CONFIG_RADIO_AZTECH is not set
+# CONFIG_RADIO_GEMTEK is not set
+# CONFIG_RADIO_GEMTEK_PCI is not set
+# CONFIG_RADIO_MAXIRADIO is not set
+# CONFIG_RADIO_MAESTRO is not set
+# CONFIG_RADIO_MIROPCM20 is not set
+# CONFIG_RADIO_MIROPCM20_RDS is not set
+# CONFIG_RADIO_SF16FMI is not set
+# CONFIG_RADIO_TERRATEC is not set
+# CONFIG_RADIO_TRUST is not set
+# CONFIG_RADIO_TYPHOON is not set
+# CONFIG_RADIO_ZOLTRIX is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=m
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_CRAMFS=m
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=m
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=m
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+CONFIG_ZLIB_FS_INFLATE=m
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+CONFIG_SMB_NLS=y
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_SA1100=y
+CONFIG_SOUND_UDA1341=y
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+CONFIG_SOUND_SA1111_UDA1341=y
+# CONFIG_SOUND_SA1100SSP is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
+# CONFIG_SOUND_TVMIXER is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+CONFIG_MCP=y
+CONFIG_MCP_SA1100=y
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_LONG_TIMEOUT is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+CONFIG_USB_OHCI_SA1111=y
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_AUDIO=y
+CONFIG_USB_BLUETOOTH=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DEBUG=y
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+CONFIG_USB_DC2XX=m
+CONFIG_USB_MDC800=m
+CONFIG_USB_SCANNER=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USB_HPUSBSCSI=m
+
+#
+# USB Multimedia devices
+#
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_OV511=m
+CONFIG_USB_PWC=m
+CONFIG_USB_SE401=m
+# CONFIG_USB_STV680 is not set
+CONFIG_USB_VICAM=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_DABUSB=m
+
+#
+# USB Network adaptors
+#
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_CATC=m
+CONFIG_USB_CDCETHER=m
+CONFIG_USB_USBNET=m
+
+#
+# USB port drivers
+#
+CONFIG_USB_USS720=m
+
+#
+# USB Serial Converter support
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_VISOR=m
+# CONFIG_USB_SERIAL_IPAQ is not set
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_KLSI is not set
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OMNINET=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_RIO500=m
+
+#
+# Bluetooth support
+#
+CONFIG_BLUEZ=m
+CONFIG_BLUEZ_L2CAP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BLUEZ_HCIUSB=m
+CONFIG_BLUEZ_HCIUART=m
+CONFIG_BLUEZ_HCIVHCI=m
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/cerfcube linux/arch/arm/def-configs/cerfcube
--- linux.orig/arch/arm/def-configs/cerfcube	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/cerfcube	2002-08-01 06:42:28.000000000 +0000
@@ -876,7 +876,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/cerfpda linux/arch/arm/def-configs/cerfpda
--- linux.orig/arch/arm/def-configs/cerfpda	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/cerfpda	2002-08-01 06:42:34.000000000 +0000
@@ -970,7 +970,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/cerfpod linux/arch/arm/def-configs/cerfpod
--- linux.orig/arch/arm/def-configs/cerfpod	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/cerfpod	2002-08-01 06:42:43.000000000 +0000
@@ -897,7 +897,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/clps7500 linux/arch/arm/def-configs/clps7500
--- linux.orig/arch/arm/def-configs/clps7500	2001-05-20 00:43:05.000000000 +0000
+++ linux/arch/arm/def-configs/clps7500	2002-08-01 06:42:28.000000000 +0000
@@ -511,7 +511,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/ebsa110 linux/arch/arm/def-configs/ebsa110
--- linux.orig/arch/arm/def-configs/ebsa110	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/ebsa110	2002-08-01 06:42:29.000000000 +0000
@@ -594,7 +594,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/epxa10db linux/arch/arm/def-configs/epxa10db
--- linux.orig/arch/arm/def-configs/epxa10db	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/epxa10db	2002-08-01 06:42:37.000000000 +0000
@@ -651,7 +651,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_INFO=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/flexanet linux/arch/arm/def-configs/flexanet
--- linux.orig/arch/arm/def-configs/flexanet	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/flexanet	2002-08-01 06:42:41.000000000 +0000
@@ -8,6 +8,8 @@
 CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
 
 #
 # Code maturity level options
@@ -25,17 +27,19 @@
 #
 # System Type
 #
+# CONFIG_ARCH_ANAKIN is not set
 # CONFIG_ARCH_ARCA5K is not set
 # CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_SHARK is not set
 
 #
 # Archimedes/A5000 Implementations
@@ -44,22 +48,32 @@
 #
 # Archimedes/A5000 Implementations (select only ONE)
 #
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
 
 #
 # Footbridge Implementations
 #
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
 
 #
 # SA11x0 Implementations
 #
 # CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
 # CONFIG_SA1100_BRUTUS is not set
 # CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3600 is not set
 # CONFIG_SA1100_EXTENEX1 is not set
 CONFIG_SA1100_FLEXANET=y
 # CONFIG_SA1100_FREEBIRD is not set
 # CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HUW_WEBPANEL is not set
 # CONFIG_SA1100_ITSY is not set
@@ -68,7 +82,9 @@
 # CONFIG_SA1100_OMNIMETER is not set
 # CONFIG_SA1100_PANGOLIN is not set
 # CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHANNON is not set
 # CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
 # CONFIG_SA1100_PFS168 is not set
 # CONFIG_SA1100_VICTOR is not set
 # CONFIG_SA1100_XP860 is not set
@@ -76,11 +92,17 @@
 CONFIG_SA1100_USB=y
 CONFIG_SA1100_USB_NETLINK=y
 # CONFIG_SA1100_USB_CHAR is not set
-# CONFIG_SA1100_FREQUENCY_SCALE is not set
 
 #
 # CLPS711X/EP721X Implementations
 #
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
 # CONFIG_ARCH_ACORN is not set
 # CONFIG_FOOTBRIDGE is not set
 # CONFIG_FOOTBRIDGE_HOST is not set
@@ -97,32 +119,40 @@
 # CONFIG_CPU_ARM710 is not set
 # CONFIG_CPU_ARM720T is not set
 # CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
 # CONFIG_CPU_ARM1020 is not set
 # CONFIG_CPU_SA110 is not set
 CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
 CONFIG_DISCONTIGMEM=y
-# CONFIG_CPU_BIG_ENDIAN is not set
 
 #
 # General setup
 #
 # CONFIG_PCI is not set
-# CONFIG_ISA is not set
+CONFIG_ISA=y
 # CONFIG_ISA_DMA is not set
-# CONFIG_CPU_CLOCK is not set
+CONFIG_CPU_FREQ=y
 CONFIG_HOTPLUG=y
 
 #
 # PCMCIA/CardBus support
 #
 CONFIG_PCMCIA=y
+# CONFIG_I82092 is not set
 # CONFIG_I82365 is not set
 # CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
 CONFIG_PCMCIA_SA1100=y
 CONFIG_NET=y
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
 CONFIG_FPE_NWFPE=y
 CONFIG_FPE_FASTFPE=y
 CONFIG_KCORE_ELF=y
@@ -130,7 +160,7 @@
 # CONFIG_BINFMT_AOUT is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
-# CONFIG_PM is not set
+CONFIG_PM=y
 # CONFIG_ARTHUR is not set
 CONFIG_CMDLINE=""
 CONFIG_LEDS=y
@@ -149,7 +179,7 @@
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_REDBOOT_PARTS=y
 # CONFIG_MTD_BOOTLDR_PARTS is not set
 # CONFIG_MTD_AFS_PARTS is not set
 
@@ -165,43 +195,42 @@
 # RAM/ROM/Flash chip drivers
 #
 CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_VIRTUAL_ER is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_NOSWAP=y
 # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
 # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LART_BIT_SWAP is not set
 # CONFIG_MTD_CFI_GEOMETRY is not set
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_AMDSTD is not set
-# CONFIG_MTD_SHARP is not set
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
 # CONFIG_MTD_JEDEC is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_SUN_UFLASH is not set
 # CONFIG_MTD_NORA is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_NETSC520 is not set
-# CONFIG_MTD_SBC_GXX is not set
-# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
 CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
 # CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_CFI_FLAGADM is not set
-# CONFIG_MTD_ARMFLASH is not set
+# CONFIG_MTD_PCI is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_PMC551 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
 
 #
 # Disk-On-Chip Device Drivers
@@ -220,11 +249,17 @@
 # Plug and Play configuration
 #
 # CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
 
 #
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
@@ -235,6 +270,13 @@
 # Multi-device support (RAID and LVM)
 #
 # CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
 
 #
 # Networking options
@@ -258,6 +300,7 @@
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #
@@ -293,42 +336,75 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
 
 #
 # Ethernet (10 or 100Mbit)
 #
 CONFIG_NET_ETHERNET=y
+# CONFIG_ARM_AM79C961A is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
 CONFIG_NET_VENDOR_SMC=y
 # CONFIG_WD80x3 is not set
+# CONFIG_ULTRAMCA is not set
 # CONFIG_ULTRA is not set
+# CONFIG_ULTRA32 is not set
 CONFIG_SMC9194=y
 # CONFIG_NET_VENDOR_RACAL is not set
 # CONFIG_AT1700 is not set
 # CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_NET_POCKET is not set
 
 #
 # Ethernet (1000 Mbit)
 #
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 
 #
 # Wireless LAN (non-hamradio)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_NET_RADIO=y
+# CONFIG_STRIP is not set
+# CONFIG_WAVELAN is not set
+# CONFIG_ARLAN is not set
+# CONFIG_AIRONET4500 is not set
+# CONFIG_AIRONET4500_NONCS is not set
+# CONFIG_AIRONET4500_PROC is not set
+# CONFIG_AIRO is not set
+CONFIG_HERMES=m
+
+#
+# Wireless Pcmcia cards support
+#
+CONFIG_PCMCIA_HERMES=m
+# CONFIG_AIRO_CS is not set
+CONFIG_NET_WIRELESS=y
 
 #
 # Token Ring devices
 #
 # CONFIG_TR is not set
 # CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
 # CONFIG_SHAPER is not set
 
 #
@@ -347,8 +423,10 @@
 # CONFIG_PCMCIA_NMCLAN is not set
 # CONFIG_PCMCIA_SMC91C92 is not set
 # CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
 # CONFIG_NET_PCMCIA_RADIO is not set
-CONFIG_PCMCIA_NETCARD=y
 
 #
 # Amateur Radio support
@@ -378,20 +456,33 @@
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 # CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
 # CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
 CONFIG_BLK_DEV_IDECS=y
 # CONFIG_BLK_DEV_IDECD is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
 
 #
 # IDE chipset support/bugfixes
 #
 # CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
 # CONFIG_IDE_CHIPSETS is not set
 # CONFIG_IDEDMA_AUTO is not set
 # CONFIG_DMA_NONPCI is not set
 # CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
 
 #
 # SCSI support
@@ -402,6 +493,10 @@
 # I2O device support
 #
 # CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
 
 #
 # ISDN subsystem
@@ -412,6 +507,10 @@
 # Input core support
 #
 # CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
 
 #
 # Character devices
@@ -419,21 +518,38 @@
 CONFIG_VT=y
 # CONFIG_VT_CONSOLE is not set
 # CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
 CONFIG_SERIAL_SA1100=y
-# CONFIG_SERIAL_SA1100_OLD is not set
 CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SA1100_DEFAULT_BAUDRATE=57600
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_UNIX98_PTY_COUNT=32
-CONFIG_UCB1200=y
-CONFIG_TOUCHSCREEN_UCB1200=y
-CONFIG_AUDIO_UCB1200=y
-CONFIG_ADC_UCB1200=y
-# CONFIG_TOUCHSCREEN_BITSY is not set
-# CONFIG_PROFILER is not set
 
 #
 # I2C support
@@ -441,37 +557,35 @@
 # CONFIG_I2C is not set
 
 #
-# Mice
+# L3 serial bus support
 #
-# CONFIG_BUSMOUSE is not set
-# CONFIG_MOUSE is not set
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
 
 #
-# Joysticks
+# Other L3 adapters
 #
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
 
 #
-# Game port support
-#
-
-#
-# Gameport joysticks
-#
-
-#
-# Serial port support
+# Mice
 #
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
 
 #
-# Serial port joysticks
+# Joysticks
 #
+# CONFIG_INPUT_GAMEPORT is not set
 
 #
-# Parallel port joysticks
+# Input core support is needed for gameports
 #
 
 #
-#   Parport support is needed for parallel port joysticks
+# Input core support is needed for joysticks
 #
 # CONFIG_QIC02_TAPE is not set
 
@@ -479,6 +593,7 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
 CONFIG_SA1100_RTC=y
@@ -509,44 +624,74 @@
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
 # CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_JFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
 CONFIG_RAMFS=y
 # CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
 CONFIG_PROC_FS=y
 # CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
 CONFIG_DEVPTS_FS=y
 # CONFIG_QNX4FS_FS is not set
-CONFIG_ROMFS_FS=y
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
 
 #
 # Network File Systems
 #
 # CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 CONFIG_ROOT_NFS=y
 # CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
 CONFIG_SUNRPC=y
 CONFIG_LOCKD=y
 # CONFIG_SMB_FS is not set
 # CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -562,6 +707,7 @@
 # CONFIG_MINIX_SUBPARTITION is not set
 # CONFIG_SOLARIS_X86_PARTITION is not set
 # CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
 # CONFIG_SGI_PARTITION is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_SUN_PARTITION is not set
@@ -573,15 +719,17 @@
 #
 CONFIG_PC_KEYMAP=y
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
 
 #
 # Frame-buffer support
 #
 CONFIG_FB=y
 CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
 CONFIG_FB_SA1100=y
-# CONFIG_FB_E1355 is not set
+# CONFIG_FB_CYBER2000 is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FBCON_ADVANCED is not set
 CONFIG_FBCON_CFB2=y
@@ -597,28 +745,49 @@
 # Sound
 #
 CONFIG_SOUND=y
-# CONFIG_SOUND_SA1100_SSP is not set
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
 # CONFIG_SOUND_FUSION is not set
 # CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
 # CONFIG_SOUND_ESSSOLO1 is not set
 # CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
 # CONFIG_SOUND_SONICVIBES is not set
 # CONFIG_SOUND_TRIDENT is not set
 # CONFIG_SOUND_MSNDCLAS is not set
 # CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_SA1100 is not set
+# CONFIG_SOUND_UDA1341 is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
 # CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
+# CONFIG_SOUND_TVMIXER is not set
 
 #
-# USB support
+# Multimedia Capabilities Port drivers
 #
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
 
 #
-# Miscellaneous USB options
+# USB support
 #
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB is not set
 
 #
 # USB Controllers
@@ -626,15 +795,22 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 # CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_AUDIO is not set
 # CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 
@@ -652,40 +828,83 @@
 # CONFIG_USB_DC2XX is not set
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
 
 #
 # USB Multimedia devices
 #
-# CONFIG_USB_DABUSB is not set
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
 
 #
 # USB Network adaptors
 #
-# CONFIG_USB_PLUSB is not set
 # CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_NET1080 is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
 # CONFIG_USB_USBNET is not set
 
 #
 # USB port drivers
 #
+# CONFIG_USB_USS720 is not set
 
 #
 # USB Serial Converter support
 #
 # CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
 
 #
-# USB misc drivers
+# USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
 
 #
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
-CONFIG_DEBUG_ERRORS=y
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
-CONFIG_MAGIC_SYSRQ=y
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/fortunet linux/arch/arm/def-configs/fortunet
--- linux.orig/arch/arm/def-configs/fortunet	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/def-configs/fortunet	2002-08-01 06:42:30.000000000 +0000
@@ -0,0 +1,593 @@
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+CONFIG_ARCH_CLPS711X=y
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHANNON is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+# CONFIG_H3600_SLEEVE is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+CONFIG_ARCH_FORTUNET=y
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+CONFIG_CPU_ARM720T=y
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+# CONFIG_CPU_SA1100 is not set
+# CONFIG_ARM_THUMB is not set
+# CONFIG_DISCONTIGMEM is not set
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_ISA_DMA is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FPE_FASTFPE=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_PARTITIONS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+# CONFIG_MTD_SA1100 is not set
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+CONFIG_MTD_FORTUNET=y
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+# CONFIG_INET is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET_AUNUDP is not set
+# CONFIG_ECONET_NATIVE is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+# CONFIG_NETDEVICES is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Synchronous Serial Interface
+#
+# CONFIG_SSI is not set
+# CONFIG_SSI_CLPS711X is not set
+# CONFIG_SSI_JUNO is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+CONFIG_SERIAL_CLPS711X=y
+CONFIG_SERIAL_CLPS711X_CONSOLE=y
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
+# CONFIG_SERIAL_SA1100 is not set
+# CONFIG_SERIAL_SA1100_CONSOLE is not set
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+# CONFIG_JFFS_PROC_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_NO_PGT_CACHE is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
+# CONFIG_DEBUG_LL_SER3 is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/freebird linux/arch/arm/def-configs/freebird
--- linux.orig/arch/arm/def-configs/freebird	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/freebird	2002-08-01 06:42:34.000000000 +0000
@@ -614,7 +614,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/freebird_new linux/arch/arm/def-configs/freebird_new
--- linux.orig/arch/arm/def-configs/freebird_new	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/freebird_new	2002-08-01 06:42:30.000000000 +0000
@@ -634,7 +634,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/frodo linux/arch/arm/def-configs/frodo
--- linux.orig/arch/arm/def-configs/frodo	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/def-configs/frodo	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,618 @@
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_BADGE4 is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_PT_SYSTEM3 is not set
+# CONFIG_SA1100_SHANNON is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1100_FRODO=y
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+# CONFIG_H3600_SLEEVE is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_FORTUNET is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+CONFIG_ISA=y
+# CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FPE_FASTFPE=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttySA0,9600 ramdisk_size=4096 root=/dev/ram idebus=33"
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+# CONFIG_NETDEVICES is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=9600
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=16
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_SA1100_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+CONFIG_ROMFS_FS=y
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
+CONFIG_FB_SA1100=y
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_WAITQ=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/graphicsclient linux/arch/arm/def-configs/graphicsclient
--- linux.orig/arch/arm/def-configs/graphicsclient	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/graphicsclient	2002-08-01 06:42:44.000000000 +0000
@@ -731,7 +731,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/graphicsmaster linux/arch/arm/def-configs/graphicsmaster
--- linux.orig/arch/arm/def-configs/graphicsmaster	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/graphicsmaster	2002-08-01 06:42:27.000000000 +0000
@@ -744,7 +744,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/h3600 linux/arch/arm/def-configs/h3600
--- linux.orig/arch/arm/def-configs/h3600	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/h3600	2002-08-01 06:42:36.000000000 +0000
@@ -948,7 +948,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/integrator linux/arch/arm/def-configs/integrator
--- linux.orig/arch/arm/def-configs/integrator	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/integrator	2002-08-01 06:42:31.000000000 +0000
@@ -652,7 +652,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/jornada720 linux/arch/arm/def-configs/jornada720
--- linux.orig/arch/arm/def-configs/jornada720	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/jornada720	2002-08-01 06:42:36.000000000 +0000
@@ -1,11 +1,15 @@
 #
-# Automatically generated make config: don't edit
+# Automatically generated by make menuconfig: don't edit
 #
 CONFIG_ARM=y
 # CONFIG_EISA is not set
 # CONFIG_SBUS is not set
 # CONFIG_MCA is not set
 CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
 
 #
 # Code maturity level options
@@ -23,24 +27,23 @@
 #
 # System Type
 #
+# CONFIG_ARCH_ANAKIN is not set
 # CONFIG_ARCH_ARCA5K is not set
 # CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
-# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_SHARK is not set
 
 #
 # Archimedes/A5000 Implementations
 #
-
-#
-# Archimedes/A5000 Implementations (select only ONE)
-#
 # CONFIG_ARCH_ARC is not set
 # CONFIG_ARCH_A5K is not set
 
@@ -58,12 +61,18 @@
 #
 # CONFIG_SA1100_ASSABET is not set
 # CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
 # CONFIG_SA1100_BRUTUS is not set
 # CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
 # CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
 # CONFIG_SA1100_FREEBIRD is not set
 # CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
 CONFIG_SA1100_JORNADA720=y
 # CONFIG_SA1100_HUW_WEBPANEL is not set
 # CONFIG_SA1100_ITSY is not set
@@ -72,70 +81,75 @@
 # CONFIG_SA1100_OMNIMETER is not set
 # CONFIG_SA1100_PANGOLIN is not set
 # CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHANNON is not set
 # CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
 # CONFIG_SA1100_PFS168 is not set
 # CONFIG_SA1100_VICTOR is not set
 # CONFIG_SA1100_XP860 is not set
 # CONFIG_SA1100_YOPY is not set
 CONFIG_SA1111=y
+CONFIG_FORCE_MAX_ZONEORDER=9
 # CONFIG_SA1100_USB is not set
 # CONFIG_SA1100_USB_NETLINK is not set
 # CONFIG_SA1100_USB_CHAR is not set
-# CONFIG_SA1100_FREQUENCY_SCALE is not set
-# CONFIG_SA1100_VOLTAGE_SCALE is not set
+# CONFIG_REGISTERS is not set
 
 #
 # CLPS711X/EP721X Implementations
 #
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
 # CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
 # CONFIG_ARCH_ACORN is not set
 # CONFIG_FOOTBRIDGE is not set
 # CONFIG_FOOTBRIDGE_HOST is not set
 # CONFIG_FOOTBRIDGE_ADDIN is not set
 CONFIG_CPU_32=y
 # CONFIG_CPU_26 is not set
-
-#
-# Processor Type
-#
 # CONFIG_CPU_32v3 is not set
 CONFIG_CPU_32v4=y
 # CONFIG_CPU_ARM610 is not set
 # CONFIG_CPU_ARM710 is not set
 # CONFIG_CPU_ARM720T is not set
 # CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
 # CONFIG_CPU_ARM1020 is not set
 # CONFIG_CPU_SA110 is not set
 CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
 CONFIG_DISCONTIGMEM=y
 
 #
 # General setup
 #
-
-#
-# Please ensure that you have read the help on the next option
-#
-# CONFIG_ANGELBOOT is not set
 # CONFIG_PCI is not set
-# CONFIG_ISA is not set
+CONFIG_ISA=y
 # CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
 CONFIG_HOTPLUG=y
 
 #
 # PCMCIA/CardBus support
 #
 CONFIG_PCMCIA=y
+# CONFIG_I82092 is not set
 # CONFIG_I82365 is not set
 # CONFIG_TCIC is not set
 # CONFIG_PCMCIA_CLPS6700 is not set
 CONFIG_PCMCIA_SA1100=y
+# CONFIG_MERCURY_BACKPAQ is not set
 CONFIG_NET=y
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_FASTFPE is not set
+CONFIG_FPE_FASTFPE=y
 CONFIG_KCORE_ELF=y
 # CONFIG_KCORE_AOUT is not set
 CONFIG_BINFMT_AOUT=m
@@ -145,10 +159,8 @@
 # CONFIG_APM is not set
 # CONFIG_ARTHUR is not set
 CONFIG_CMDLINE="keepinitrd"
-# CONFIG_PFS168_CMDLINE is not set
 # CONFIG_LEDS is not set
-# CONFIG_ALIGNMENT_TRAP is not set
-# CONFIG_UCB1200 is not set
+CONFIG_ALIGNMENT_TRAP=y
 
 #
 # Parallel port support
@@ -159,63 +171,72 @@
 # Memory Technology Devices (MTD)
 #
 CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC1000 is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOCPROBE is not set
-
-#
-# RAM/ROM Device Drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_BOOTLDR_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
 
 #
-# Linearly Mapped Flash Device Drivers
+# RAM/ROM/Flash chip drivers
 #
 CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+CONFIG_MTD_CFI_B2=y
+CONFIG_MTD_CFI_B4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
 # CONFIG_MTD_AMDSTD is not set
 # CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
 # CONFIG_MTD_PHYSMAP is not set
 # CONFIG_MTD_NORA is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_SBC_MEDIAGX is not set
-# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
 CONFIG_MTD_SA1100=y
+# CONFIG_MTD_H3600_BACKPAQ is not set
 # CONFIG_MTD_DC21285 is not set
 # CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_CSTM_CFI_JEDEC is not set
-# CONFIG_MTD_JEDEC is not set
-# CONFIG_MTD_MIXMEM is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_VMAX is not set
 
 #
-# NAND Flash Device Drivers
+# Self-contained MTD device drivers
 #
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_NAND_SPIA is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
 
 #
-# User Modules And Translation Layers
+# NAND Flash Device Drivers
 #
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
+# CONFIG_MTD_NAND is not set
 
 #
 # Plug and Play configuration
@@ -246,6 +267,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -258,7 +280,7 @@
 # CONFIG_NETLINK_DEV is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
-# CONFIG_FILTER is not set
+CONFIG_FILTER=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
@@ -282,10 +304,7 @@
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
-
-#
-#
-#
+# CONFIG_VLAN_8021Q is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
 # CONFIG_DECNET is not set
@@ -318,7 +337,6 @@
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_ETHERTAP is not set
-# CONFIG_NET_SB1000 is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -329,18 +347,44 @@
 # Ethernet (1000 Mbit)
 #
 # CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPPOE is not set
 # CONFIG_SLIP is not set
 
 #
 # Wireless LAN (non-hamradio)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_NET_RADIO=y
+# CONFIG_STRIP is not set
+CONFIG_WAVELAN=m
+CONFIG_ARLAN=m
+CONFIG_AIRONET4500=m
+CONFIG_AIRONET4500_NONCS=m
+# CONFIG_AIRONET4500_PNP is not set
+# CONFIG_AIRONET4500_PCI is not set
+# CONFIG_AIRONET4500_ISA is not set
+# CONFIG_AIRONET4500_I365 is not set
+# CONFIG_AIRONET4500_PROC is not set
+# CONFIG_AIRO is not set
+CONFIG_HERMES=m
+CONFIG_PCMCIA_HERMES=m
+CONFIG_AIRO_CS=m
+CONFIG_NET_WIRELESS=y
 
 #
 # Token Ring devices
@@ -366,11 +410,11 @@
 CONFIG_PCMCIA_NMCLAN=m
 CONFIG_PCMCIA_SMC91C92=m
 CONFIG_PCMCIA_XIRC2PS=m
+# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_ARCNET_COM20020_CS is not set
 # CONFIG_PCMCIA_IBMTR is not set
 CONFIG_NET_PCMCIA_RADIO=y
 # CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_PCMCIA_HERMES is not set
 # CONFIG_PCMCIA_NETWAVE is not set
 CONFIG_PCMCIA_WAVELAN=m
 CONFIG_AIRONET4500_CS=m
@@ -384,10 +428,6 @@
 # IrDA (infrared) support
 #
 CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
 CONFIG_IRLAN=m
 # CONFIG_IRNET is not set
 CONFIG_IRCOMM=m
@@ -397,28 +437,19 @@
 #
 # Infrared-port device drivers
 #
-
-#
-# SIR device drivers
-#
 # CONFIG_IRTTY_SIR is not set
 # CONFIG_IRPORT_SIR is not set
-
-#
-# FIR device drivers
-#
+# CONFIG_DONGLE is not set
+# CONFIG_USB_IRDA is not set
 # CONFIG_NSC_FIR is not set
 # CONFIG_WINBOND_FIR is not set
 # CONFIG_TOSHIBA_FIR is not set
 # CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
 CONFIG_SA1100_FIR=m
 
 #
-# Dongle support
-#
-# CONFIG_DONGLE is not set
-
-#
 # ATA/IDE/MFM/RLL support
 #
 CONFIG_IDE=m
@@ -427,10 +458,6 @@
 # IDE, ATA and ATAPI Block devices
 #
 CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
 # CONFIG_BLK_DEV_HD_IDE is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_BLK_DEV_IDEDISK=m
@@ -445,14 +472,10 @@
 # CONFIG_BLK_DEV_COMMERIAL is not set
 # CONFIG_BLK_DEV_TIVO is not set
 CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_IDECD is not set
+CONFIG_BLK_DEV_IDECD=m
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_BLK_DEV_IDESCSI is not set
-
-#
-# IDE chipset support/bugfixes
-#
 # CONFIG_BLK_DEV_CMD640 is not set
 # CONFIG_BLK_DEV_CMD640_ENHANCED is not set
 # CONFIG_BLK_DEV_ISAPNP is not set
@@ -460,6 +483,9 @@
 # CONFIG_IDEDMA_AUTO is not set
 # CONFIG_DMA_NONPCI is not set
 # CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
 
 #
 # SCSI support
@@ -483,7 +509,13 @@
 #
 # Input core support
 #
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
+# CONFIG_INPUT_KEYBDEV is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
 
 #
 # Character devices
@@ -493,19 +525,37 @@
 CONFIG_SERIAL=m
 # CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
 CONFIG_SERIAL_SA1100=y
 CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SA1100_DEFAULT_BAUDRATE=115200
-# CONFIG_TOUCHSCREEN_UCB1200 is not set
-# CONFIG_TOUCHSCREEN_BITSY is not set
-CONFIG_PROFILER=m
-# CONFIG_PFS168_SPI is not set
-# CONFIG_PFS168_DTMF is not set
-# CONFIG_PFS168_MISC is not set
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_UNIX98_PTY_COUNT=32
+# CONFIG_NEWTONKBD is not set
 
 #
 # I2C support
@@ -513,6 +563,15 @@
 # CONFIG_I2C is not set
 
 #
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
 # Mice
 #
 # CONFIG_BUSMOUSE is not set
@@ -524,11 +583,33 @@
 #
 # Joysticks
 #
-# CONFIG_JOYSTICK is not set
-
-#
-# Input core support is needed for joysticks
-#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
 # CONFIG_QIC02_TAPE is not set
 
 #
@@ -553,12 +634,13 @@
 #
 # PCMCIA character devices
 #
-CONFIG_PCMCIA_SERIAL_CS=m
+# CONFIG_PCMCIA_SERIAL_CS is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_V4L2_DEV is not set
 
 #
 # File systems
@@ -568,37 +650,45 @@
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
 # CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
 # CONFIG_UMSDOS_FS is not set
-CONFIG_VFAT_FS=m
+# CONFIG_VFAT_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_JFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=2
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
 CONFIG_RAMFS=y
-# CONFIG_ISO9660_FS is not set
+CONFIG_ISO9660_FS=m
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
 CONFIG_PROC_FS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVFS_MOUNT is not set
-# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+# CONFIG_DRIVERFS_FS is not set
 CONFIG_DEVPTS_FS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_QNX4FS_RW is not set
 # CONFIG_ROMFS_FS is not set
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
-# CONFIG_SYSV_FS_WRITE is not set
 # CONFIG_UDF_FS is not set
 # CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
@@ -608,6 +698,7 @@
 # Network File Systems
 #
 # CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_ROOT_NFS is not set
@@ -616,8 +707,7 @@
 CONFIG_SUNRPC=m
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_NCPFS_PACKET_SIGNING is not set
 # CONFIG_NCPFS_IOCTL_LOCKING is not set
@@ -627,59 +717,22 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-CONFIG_SMB_NLS=y
-CONFIG_NLS=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_UTF8 is not set
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
 
 #
 # Console drivers
 #
 CONFIG_PC_KEYMAP=y
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
 
 #
 # Frame-buffer support
@@ -687,16 +740,17 @@
 CONFIG_FB=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
 # CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_SA1100 is not set
 CONFIG_FB_EPSON1356=y
 # CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_SA1100 is not set
 # CONFIG_FB_VIRTUAL is not set
 CONFIG_FBCON_ADVANCED=y
 # CONFIG_FBCON_MFB is not set
 # CONFIG_FBCON_CFB2 is not set
 # CONFIG_FBCON_CFB4 is not set
-CONFIG_FBCON_CFB8=y
+# CONFIG_FBCON_CFB8 is not set
 CONFIG_FBCON_CFB16=y
 # CONFIG_FBCON_CFB24 is not set
 # CONFIG_FBCON_CFB32 is not set
@@ -721,10 +775,10 @@
 # Sound
 #
 CONFIG_SOUND=m
-CONFIG_SOUND_UDA1341=m
-# CONFIG_SOUND_SA1100_SSP is not set
+# CONFIG_SOUND_BT878 is not set
 # CONFIG_SOUND_CMPCI is not set
 # CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
 # CONFIG_SOUND_FUSION is not set
 # CONFIG_SOUND_CS4281 is not set
 # CONFIG_SOUND_ES1370 is not set
@@ -733,28 +787,121 @@
 # CONFIG_SOUND_MAESTRO is not set
 # CONFIG_SOUND_MAESTRO3 is not set
 # CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
 # CONFIG_SOUND_SONICVIBES is not set
 # CONFIG_SOUND_TRIDENT is not set
 # CONFIG_SOUND_MSNDCLAS is not set
 # CONFIG_SOUND_MSNDPIN is not set
 # CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_SA1100=m
+# CONFIG_SOUND_UDA1341 is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
 # CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
 # CONFIG_SOUND_TVMIXER is not set
 
 #
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
+#
 # USB support
 #
 # CONFIG_USB is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_HID is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
 
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
-CONFIG_DEBUG_ERRORS=y
+CONFIG_FRAME_POINTER=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_DC21285_PORT is not set
 # CONFIG_DEBUG_CLPS711X_UART2 is not set
+# CONFIG_DEBUG_LL_SER3 is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/lart linux/arch/arm/def-configs/lart
--- linux.orig/arch/arm/def-configs/lart	2001-10-25 20:53:44.000000000 +0000
+++ linux/arch/arm/def-configs/lart	2002-08-01 06:42:41.000000000 +0000
@@ -892,7 +892,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/neponset linux/arch/arm/def-configs/neponset
--- linux.orig/arch/arm/def-configs/neponset	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/def-configs/neponset	2002-08-01 06:42:39.000000000 +0000
@@ -950,7 +950,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/pangolin linux/arch/arm/def-configs/pangolin
--- linux.orig/arch/arm/def-configs/pangolin	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/def-configs/pangolin	2002-08-01 06:42:45.000000000 +0000
@@ -741,7 +741,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_INFO=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/pfs168_mqtft linux/arch/arm/def-configs/pfs168_mqtft
--- linux.orig/arch/arm/def-configs/pfs168_mqtft	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/pfs168_mqtft	2002-08-01 06:42:44.000000000 +0000
@@ -783,7 +783,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_INFO=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/pfs168_mqvga linux/arch/arm/def-configs/pfs168_mqvga
--- linux.orig/arch/arm/def-configs/pfs168_mqvga	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/pfs168_mqvga	2002-08-01 06:42:28.000000000 +0000
@@ -783,7 +783,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_INFO=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/pfs168_sastn linux/arch/arm/def-configs/pfs168_sastn
--- linux.orig/arch/arm/def-configs/pfs168_sastn	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/pfs168_sastn	2002-08-01 06:42:30.000000000 +0000
@@ -774,7 +774,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_INFO=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/pfs168_satft linux/arch/arm/def-configs/pfs168_satft
--- linux.orig/arch/arm/def-configs/pfs168_satft	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/pfs168_satft	2002-08-01 06:42:28.000000000 +0000
@@ -783,7 +783,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_INFO=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/pleb linux/arch/arm/def-configs/pleb
--- linux.orig/arch/arm/def-configs/pleb	2001-08-13 00:36:24.000000000 +0000
+++ linux/arch/arm/def-configs/pleb	2002-08-01 06:42:34.000000000 +0000
@@ -524,7 +524,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/rpc linux/arch/arm/def-configs/rpc
--- linux.orig/arch/arm/def-configs/rpc	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/def-configs/rpc	2002-08-01 06:42:27.000000000 +0000
@@ -839,7 +839,7 @@
 #
 # Kernel hacking
 #
-# CONFIG_NO_FRAME_POINTER is not set
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/shannon linux/arch/arm/def-configs/shannon
--- linux.orig/arch/arm/def-configs/shannon	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/def-configs/shannon	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,737 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_OBSOLETE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+
+#
+# Footbridge Implementations
+#
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+CONFIG_SA1100_SHANNON=y
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+# CONFIG_SA1100_USB is not set
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+CONFIG_ISA=y
+# CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_SA1100=y
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttySA0,9600 console=tty1 root=/dev/mtdblock2 init=/linuxrc"
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_BOOTLDR_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_IQ80310 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=y
+# CONFIG_PCMCIA_NMCLAN is not set
+CONFIG_PCMCIA_SMC91C92=y
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=m
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=9600
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_SERIO is not set
+
+#
+# Joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+CONFIG_SA1100_WATCHDOG=y
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_I810_TCO is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_SA1100_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_CMS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_FREEVXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_EXT2_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFSD is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FB_SA1100=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+CONFIG_SOUND_SA1100=y
+# CONFIG_SOUND_SA1100SSP is not set
+# CONFIG_SOUND_OSS is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+CONFIG_MCP=y
+CONFIG_MCP_SA1100=y
+CONFIG_MCP_UCB1200=y
+CONFIG_MCP_UCB1200_AUDIO=y
+CONFIG_MCP_UCB1200_TS=y
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+
+#
+# USB Device Class drivers
+#
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+# USB Imaging devices
+#
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+
+#
+# USB Miscellaneous drivers
+#
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_LL=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/shark linux/arch/arm/def-configs/shark
--- linux.orig/arch/arm/def-configs/shark	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/def-configs/shark	2002-08-01 06:42:32.000000000 +0000
@@ -956,7 +956,7 @@
 #
 # Kernel hacking
 #
-CONFIG_NO_FRAME_POINTER=y
+CONFIG_FRAME_POINTER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_INFO is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/def-configs/system3 linux/arch/arm/def-configs/system3
--- linux.orig/arch/arm/def-configs/system3	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/def-configs/system3	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,977 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+# CONFIG_EISA is not set
+# CONFIG_SBUS is not set
+# CONFIG_MCA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_OBSOLETE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_ARCA5K is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+CONFIG_ARCH_SA1100=y
+# CONFIG_ARCH_SHARK is not set
+
+#
+# Archimedes/A5000 Implementations
+#
+
+#
+# Archimedes/A5000 Implementations (select only ONE)
+#
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
+
+#
+# Footbridge Implementations
+#
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
+
+#
+# SA11x0 Implementations
+#
+# CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
+# CONFIG_SA1100_BRUTUS is not set
+# CONFIG_SA1100_CERF is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
+# CONFIG_SA1100_FREEBIRD is not set
+# CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
+# CONFIG_SA1100_JORNADA720 is not set
+# CONFIG_SA1100_HUW_WEBPANEL is not set
+# CONFIG_SA1100_ITSY is not set
+# CONFIG_SA1100_LART is not set
+# CONFIG_SA1100_NANOENGINE is not set
+# CONFIG_SA1100_OMNIMETER is not set
+# CONFIG_SA1100_PANGOLIN is not set
+# CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHANNON is not set
+# CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
+# CONFIG_SA1100_PFS168 is not set
+# CONFIG_SA1100_VICTOR is not set
+# CONFIG_SA1100_XP860 is not set
+# CONFIG_SA1100_YOPY is not set
+CONFIG_SA1100_PT_SYSTEM3=y
+CONFIG_SA1111=y
+CONFIG_FORCE_MAX_ZONEORDER=9
+CONFIG_SA1100_USB=m
+CONFIG_SA1100_USB_NETLINK=m
+CONFIG_SA1100_USB_CHAR=m
+
+#
+# CLPS711X/EP721X Implementations
+#
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
+# CONFIG_ARCH_ACORN is not set
+# CONFIG_FOOTBRIDGE is not set
+# CONFIG_FOOTBRIDGE_HOST is not set
+# CONFIG_FOOTBRIDGE_ADDIN is not set
+CONFIG_CPU_32=y
+# CONFIG_CPU_26 is not set
+
+#
+# Processor Type
+#
+# CONFIG_CPU_32v3 is not set
+CONFIG_CPU_32v4=y
+# CONFIG_CPU_ARM610 is not set
+# CONFIG_CPU_ARM710 is not set
+# CONFIG_CPU_ARM720T is not set
+# CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM1020 is not set
+# CONFIG_CPU_SA110 is not set
+CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_DISCONTIGMEM=y
+
+#
+# General setup
+#
+# CONFIG_PCI is not set
+CONFIG_ISA=y
+# CONFIG_ISA_DMA is not set
+CONFIG_CPU_FREQ=y
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=m
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
+CONFIG_PCMCIA_SA1100=m
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_PM=y
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="noinitrd root=/dev/mtdblock3"
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_BOOTLDR_PARTS=m
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_NORA is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
+CONFIG_MTD_SA1100=y
+# CONFIG_MTD_DC21285 is not set
+# CONFIG_MTD_IQ80310 is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_ARM_AM79C961A is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+CONFIG_NET_VENDOR_SMC=y
+# CONFIG_WD80x3 is not set
+# CONFIG_ULTRAMCA is not set
+# CONFIG_ULTRA is not set
+# CONFIG_ULTRA32 is not set
+CONFIG_SMC9194=m
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=m
+# CONFIG_PCMCIA_NMCLAN is not set
+CONFIG_PCMCIA_SMC91C92=m
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+# CONFIG_IRNET is not set
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+# CONFIG_IRDA_OPTIONS is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+CONFIG_IRPORT_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_NSC_FIR is not set
+# CONFIG_WINBOND_FIR is not set
+# CONFIG_TOSHIBA_FIR is not set
+# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
+CONFIG_SA1100_FIR=m
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
+CONFIG_SERIAL_SA1100=y
+CONFIG_SERIAL_SA1100_CONSOLE=y
+CONFIG_SA1100_DEFAULT_BAUDRATE=38400
+CONFIG_SERIAL_8250=m
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=32
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+
+#
+# Other L3 adapters
+#
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_SA1100_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+CONFIG_PCMCIA_SERIAL_CS=m
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_PC_KEYMAP=y
+# CONFIG_VGA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
+# CONFIG_FB_CLPS711X is not set
+CONFIG_FB_SA1100=y
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FBCON_ADVANCED is not set
+CONFIG_FBCON_CFB2=y
+CONFIG_FBCON_CFB4=y
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+CONFIG_FBCON_FONTWIDTH8_ONLY=y
+CONFIG_FBCON_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
+#
+# USB support
+#
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_LONG_TIMEOUT is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+CONFIG_USB_OHCI_SA1111=m
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=m
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=m
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+# CONFIG_USB_WACOM is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+CONFIG_USB_USBNET=m
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_WAITQ=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/Makefile linux/arch/arm/kernel/Makefile
--- linux.orig/arch/arm/kernel/Makefile	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/kernel/Makefile	2002-08-01 06:42:47.000000000 +0000
@@ -42,7 +42,8 @@
 
 no-irq-arch	:= $(CONFIG_ARCH_INTEGRATOR) $(CONFIG_ARCH_CLPS711X) \
 		   $(CONFIG_FOOTBRIDGE) $(CONFIG_ARCH_EBSA110) \
-		   $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT)
+		   $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT) \
+		   $(CONFIG_ARCH_MX1ADS)
 
 ifneq ($(findstring y,$(no-irq-arch)),y)
   obj-y		+= irq-arch.o
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/armksyms.c linux/arch/arm/kernel/armksyms.c
--- linux.orig/arch/arm/kernel/armksyms.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/armksyms.c	2002-08-01 06:42:39.000000000 +0000
@@ -77,12 +77,12 @@
 extern void __do_softirq(void);
 
 #define EXPORT_SYMBOL_ALIAS(sym,orig)		\
- const char __kstrtab_##sym##[]			\
+ const char __kstrtab_##sym[]			\
   __attribute__((section(".kstrtab"))) =	\
     __MODULE_STRING(sym);			\
  const struct module_symbol __ksymtab_##sym	\
   __attribute__((section("__ksymtab"))) =	\
-    { (unsigned long)&##orig, __kstrtab_##sym };
+    { (unsigned long)&orig, __kstrtab_##sym };
 
 /*
  * floating point math emulator support.
@@ -115,7 +115,9 @@
 EXPORT_SYMBOL(system_rev);
 EXPORT_SYMBOL(system_serial_low);
 EXPORT_SYMBOL(system_serial_high);
+#ifdef CONFIG_DEBUG_BUGVERBOSE
 EXPORT_SYMBOL(__bug);
+#endif
 EXPORT_SYMBOL(__bad_xchg);
 EXPORT_SYMBOL(__readwrite_bug);
 EXPORT_SYMBOL(enable_irq);
@@ -229,6 +231,7 @@
 EXPORT_SYMBOL_NOVERS(__udivmoddi4);
 EXPORT_SYMBOL_NOVERS(__udivsi3);
 EXPORT_SYMBOL_NOVERS(__umodsi3);
+EXPORT_SYMBOL_NOVERS(abort);
 
 	/* bitops */
 EXPORT_SYMBOL(set_bit);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/bios32.c linux/arch/arm/kernel/bios32.c
--- linux.orig/arch/arm/kernel/bios32.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/bios32.c	2002-08-01 06:42:41.000000000 +0000
@@ -153,8 +153,7 @@
 }
 
 /*
- * PCI IDE controllers use non-standard I/O port
- * decoding, respect it.
+ * PCI IDE controllers use non-standard I/O port decoding, respect it.
  */
 static void __init pci_fixup_ide_bases(struct pci_dev *dev)
 {
@@ -181,9 +180,82 @@
 	pci_write_config_dword(dev, 0x40, 0x80000000);
 }
 
+/*
+ * The CY82C693 needs some rather major fixups to ensure that it does
+ * the right thing.  Idea from the Alpha people, with a few additions.
+ *
+ * We ensure that the IDE base registers are set to 1f0/3f4 for the
+ * primary bus, and 170/374 for the secondary bus.  Also, hide them
+ * from the PCI subsystem view as well so we won't try to perform
+ * our own auto-configuration on them.
+ *
+ * In addition, we ensure that the PCI IDE interrupts are routed to
+ * IRQ 14 and IRQ 15 respectively.
+ *
+ * The above gets us to a point where the IDE on this device is
+ * functional.  However, The CY82C693U _does not work_ in bus
+ * master mode without locking the PCI bus solid.
+ */
+static void __init pci_fixup_cy82c693(struct pci_dev *dev)
+{
+	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
+		u32 base0, base1;
+
+		if (dev->class & 0x80) {	/* primary */
+			base0 = 0x1f0;
+			base1 = 0x3f4;
+		} else {			/* secondary */
+			base0 = 0x170;
+			base1 = 0x374;
+		}
+
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
+				       base0 | PCI_BASE_ADDRESS_SPACE_IO);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
+				       base1 | PCI_BASE_ADDRESS_SPACE_IO);
+
+		dev->resource[0].start = 0;
+		dev->resource[0].end   = 0;
+		dev->resource[0].flags = 0;
+
+		dev->resource[1].start = 0;
+		dev->resource[1].end   = 0;
+		dev->resource[1].flags = 0;
+	} else if (PCI_FUNC(dev->devfn) == 0) {
+		/*
+		 * Setup IDE IRQ routing.
+		 */
+		pci_write_config_byte(dev, 0x4b, 14);
+		pci_write_config_byte(dev, 0x4c, 15);
+
+		/*
+		 * Disable FREQACK handshake, enable USB.
+		 */
+		pci_write_config_byte(dev, 0x4d, 0x41);
+
+		/*
+		 * Enable PCI retry, and PCI post-write buffer.
+		 */
+		pci_write_config_byte(dev, 0x44, 0x17);
+
+		/*
+		 * Enable ISA master and DMA post write buffering.
+		 */
+		pci_write_config_byte(dev, 0x45, 0x03);
+	}
+}
+
 struct pci_fixup pcibios_fixups[] = {
 	{
 		PCI_FIXUP_HEADER,
+		PCI_VENDOR_ID_CONTAQ,	PCI_DEVICE_ID_CONTAQ_82C693,
+		pci_fixup_cy82c693
+	}, {
+		PCI_FIXUP_HEADER,
+		PCI_VENDOR_ID_DEC,	PCI_DEVICE_ID_DEC_21142,
+		pci_fixup_dec21142
+	}, {
+		PCI_FIXUP_HEADER,
 		PCI_VENDOR_ID_DEC,	PCI_DEVICE_ID_DEC_21285,
 		pci_fixup_dec21285
 	}, {
@@ -198,10 +270,6 @@
 		PCI_FIXUP_HEADER,
 		PCI_ANY_ID,		PCI_ANY_ID,
 		pci_fixup_ide_bases
-	}, {
-		PCI_FIXUP_HEADER,
-		PCI_VENDOR_ID_DEC,	PCI_DEVICE_ID_DEC_21142,
-		pci_fixup_dec21142
 	}, { 0 }
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/calls.S linux/arch/arm/kernel/calls.S
--- linux.orig/arch/arm/kernel/calls.S	2001-10-08 17:39:18.000000000 +0000
+++ linux/arch/arm/kernel/calls.S	2002-08-01 06:42:44.000000000 +0000
@@ -236,6 +236,27 @@
 		.long	SYMBOL_NAME(sys_mincore)
 /* 220 */	.long	SYMBOL_NAME(sys_madvise)
 		.long	SYMBOL_NAME(sys_fcntl64)
+		.long	SYMBOL_NAME(sys_ni_syscall) /* TUX */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* Security */
+		.long	SYMBOL_NAME(sys_gettid)
+/* 225 */	.long	SYMBOL_NAME(sys_readahead)
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_setxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_lsetxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_fsetxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_getxattr */
+/* 230 */	.long	SYMBOL_NAME(sys_ni_syscall) /* sys_lgetxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_fgetxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_listxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_llistxattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_flistxattr */
+/* 235 */	.long	SYMBOL_NAME(sys_ni_syscall) /* sys_removexattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_lremovexattr */
+		.long	SYMBOL_NAME(sys_ni_syscall) /* sys_fremovexattr */
+		.long	SYMBOL_NAME(sys_tkill)
+		/*
+		 * Please check 2.5 _before_ adding calls here,
+		 * and copy changes to rmk@arm.linux.org.uk.  Thanks.
+		 */
 __syscall_end:
 
 		.rept	NR_syscalls - (__syscall_end - __syscall_start) / 4
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/compat.c linux/arch/arm/kernel/compat.c
--- linux.orig/arch/arm/kernel/compat.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/compat.c	2002-08-01 06:42:29.000000000 +0000
@@ -89,10 +89,12 @@
 	}
 
 #ifdef CONFIG_FOOTBRIDGE
-	tag = tag_next(tag);
-	tag->hdr.tag = ATAG_MEMCLK;
-	tag->hdr.size = tag_size(tag_memclk);
-	tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285;
+	if (params->u1.s.mem_fclk_21285) {
+		tag = tag_next(tag);
+		tag->hdr.tag = ATAG_MEMCLK;
+		tag->hdr.size = tag_size(tag_memclk);
+		tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285;
+	}
 #endif
 
 #ifdef CONFIG_ARCH_ACORN
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/debug-armv.S linux/arch/arm/kernel/debug-armv.S
--- linux.orig/arch/arm/kernel/debug-armv.S	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/kernel/debug-armv.S	2002-08-01 06:42:39.000000000 +0000
@@ -164,28 +164,49 @@
 		.endm
 
 #elif defined(CONFIG_ARCH_SA1100)
+
 		.macro	addruart,rx
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ MMU enabled?
 		moveq	\rx, #0x80000000	@ physical base address
 		movne	\rx, #0xf8000000	@ virtual address
-		@add	\rx, \rx, #0x00050000	@ Ser3
-		add	\rx, \rx, #0x00010000	@ Ser1
+
+		@ We probe for the active serial port here, coherently with
+		@ the comment in include/asm-arm/arch-sa1100/uncompress.h.
+		@ We assume r1 can be clobbered.
+
+		@ see if Ser3 is active
+		add	\rx, \rx, #0x00050000
+		ldr	r1, [\rx, #UTCR3]
+		tst	r1, #UTCR3_TXE
+
+		@ if Ser3 is inactive, then try Ser1
+		addeq	\rx, \rx, #(0x00010000 - 0x00050000)
+		ldreq	r1, [\rx, #UTCR3]
+		tsteq	r1, #UTCR3_TXE
+
+		@ if Ser1 is inactive, then try Ser2
+		addeq	\rx, \rx, #(0x00030000 - 0x00010000)
+		ldreq	r1, [\rx, #UTCR3]
+		tsteq	r1, #UTCR3_TXE
+
+		@ if all ports are inactive, then there is nothing we can do
+		moveq	pc, lr
 		.endm
 
 		.macro	senduart,rd,rx
-		str	\rd, [\rx, #0x14]	@ UTDR
+		str	\rd, [\rx, #UTDR]
 		.endm
 
 		.macro	waituart,rd,rx
-1001:		ldr	\rd, [\rx, #0x20]	@ UTSR1
-		tst	\rd, #1 << 2		@ UTSR1_TNF
+1001:		ldr	\rd, [\rx, #UTSR1]
+		tst	\rd, #UTSR1_TNF
 		beq	1001b
 		.endm
 
 		.macro	busyuart,rd,rx
-1001:		ldr	\rd, [\rx, #0x20]	@ UTSR1
-		tst	\rd, #1 << 0		@ UTSR1_TBY
+1001:		ldr	\rd, [\rx, #UTSR1]
+		tst	\rd, #UTSR1_TBY
 		bne	1001b
 		.endm
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/dma-arc.c linux/arch/arm/kernel/dma-arc.c
--- linux.orig/arch/arm/kernel/dma-arc.c	2001-07-04 21:56:44.000000000 +0000
+++ linux/arch/arm/kernel/dma-arc.c	2002-08-01 06:42:46.000000000 +0000
@@ -96,7 +96,7 @@
 	/* 10/1/1999 DAG - Presume whether there is an outstanding command? */
 	extern unsigned int fdc1772_fdc_int_done;
 
-	* Explicit! If the int done is 0 then 1 int to go */
+	/* Explicit! If the int done is 0 then 1 int to go */
 	return (fdc1772_fdc_int_done==0)?1:0;
 }
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/dma.c linux/arch/arm/kernel/dma.c
--- linux.orig/arch/arm/kernel/dma.c	2001-02-09 19:29:44.000000000 +0000
+++ linux/arch/arm/kernel/dma.c	2002-08-01 06:42:46.000000000 +0000
@@ -275,6 +275,8 @@
 
 #endif
 
+EXPORT_SYMBOL(request_dma);
+EXPORT_SYMBOL(free_dma);
 EXPORT_SYMBOL(enable_dma);
 EXPORT_SYMBOL(disable_dma);
 EXPORT_SYMBOL(set_dma_addr);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/entry-armv.S linux/arch/arm/kernel/entry-armv.S
--- linux.orig/arch/arm/kernel/entry-armv.S	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/kernel/entry-armv.S	2002-08-01 06:42:38.000000000 +0000
@@ -454,6 +454,31 @@
 		.macro	irq_prio_table
 		.endm
 
+#elif defined(CONFIG_ARCH_MX1ADS)
+
+		.macro	disable_fiq
+		.endm
+#define AITC_NIVECSR   0x40
+		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+		ldr	\irqstat, =IO_ADDRESS(MX1ADS_AITC_BASE)
+		@ Load offset & priority of the highest priority
+		@ interrupt pending.
+		ldr	\irqnr, [\irqstat, #AITC_NIVECSR]
+		@ Shift off the priority leaving the offset or
+		@ "interrupt number"
+		mov	\irqnr, \irqnr, lsr #16
+ 		ldr	\irqstat, =1	@ dummy compare
+		ldr	\base, =0xFFFF		// invalid interrupt
+		cmp	\irqnr, \base
+		bne	1001f
+		ldr	\irqstat, =0
+1001:
+		tst	\irqstat, #1	@ to make the condition code = TRUE
+		.endm
+
+		.macro	irq_prio_table
+		.endm
+
 #elif defined(CONFIG_ARCH_CLPS711X)
 
 #include <asm/hardware/clps7111.h>
@@ -643,14 +668,14 @@
 		mrs	r9, cpsr			@ Enable interrupts if they were
 		tst	r3, #I_BIT
 		biceq	r9, r9, #I_BIT			@ previously
-		mov	r0, r2
+		mov	r0, r2				@ *** remove once everyones in sync
 /*
  * This routine must not corrupt r9
  */
 #ifdef MULTI_CPU
-		ldr	r2, .LCprocfns			@ pass r0, r3 to
+		ldr	r4, .LCprocfns			@ pass r0, r3 to
 		mov	lr, pc				@ processor code
-		ldr	pc, [r2]			@ call processor specific code
+		ldr	pc, [r4]			@ call processor specific code
 #else
 		bl	cpu_data_abort
 #endif
@@ -747,15 +772,16 @@
 		stmia	sp, {r0 - r12}			@ save r0 - r12
 		ldr	r7, .LCabt
 		add	r5, sp, #S_PC
-		ldmia	r7, {r0, r3, r4}		@ Get USR pc, cpsr
-		stmia	r5, {r0, r3, r4}		@ Save USR pc, cpsr, old_r0
+		ldmia	r7, {r2 - r4}			@ Get USR pc, cpsr
+		stmia	r5, {r2 - r4}			@ Save USR pc, cpsr, old_r0
 		stmdb	r5, {sp, lr}^
 		alignment_trap r7, r7, __temp_abt
 		zero_fp
+		mov	r0, r2				@ remove once everyones in sync
 #ifdef MULTI_CPU
-		ldr	r2, .LCprocfns			@ pass r0, r3 to
+		ldr	r4, .LCprocfns			@ pass r0, r3 to
 		mov	lr, pc				@ processor code
-		ldr	pc, [r2]			@ call processor specific code
+		ldr	pc, [r4]			@ call processor specific code
 #else
 		bl	cpu_data_abort
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/entry-header.S linux/arch/arm/kernel/entry-header.S
--- linux.orig/arch/arm/kernel/entry-header.S	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/entry-header.S	2002-08-01 06:42:42.000000000 +0000
@@ -13,7 +13,7 @@
 #endif
 
 		.macro	zero_fp
-#ifndef CONFIG_NO_FRAME_POINTER
+#ifdef CONFIG_FRAME_POINTER
 		mov	fp, #0
 #endif
 		.endm
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/init_task.c linux/arch/arm/kernel/init_task.c
--- linux.orig/arch/arm/kernel/init_task.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/init_task.c	2002-08-01 06:42:40.000000000 +0000
@@ -9,7 +9,6 @@
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 
-static struct vm_area_struct init_mmap = INIT_MMAP;
 static struct fs_struct init_fs = INIT_FS;
 static struct files_struct init_files = INIT_FILES;
 static struct signal_struct init_signals = INIT_SIGNALS;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/process.c linux/arch/arm/kernel/process.c
--- linux.orig/arch/arm/kernel/process.c	2001-09-30 19:26:08.000000000 +0000
+++ linux/arch/arm/kernel/process.c	2002-08-01 06:42:40.000000000 +0000
@@ -24,9 +24,8 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 
-#include <asm/system.h>
-#include <asm/io.h>
 #include <asm/leds.h>
+#include <asm/system.h>
 #include <asm/uaccess.h>
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/semaphore.c linux/arch/arm/kernel/semaphore.c
--- linux.orig/arch/arm/kernel/semaphore.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/arm/kernel/semaphore.c	2002-08-01 06:42:41.000000000 +0000
@@ -210,7 +210,6 @@
 	mov	r0, ip
 	bl	__up
 	ldmfd	sp!, {r0 - r3, pc}^
-
 	");
 
 #else
@@ -248,7 +247,6 @@
 	mov	r0, ip
 	bl	__up
 	ldmfd	sp!, {r0 - r3, pc}
-
 	");
 
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/signal.c linux/arch/arm/kernel/signal.c
--- linux.orig/arch/arm/kernel/signal.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/signal.c	2002-08-01 06:42:29.000000000 +0000
@@ -344,7 +344,7 @@
 	/*
 	 * This is the X/Open sanctioned signal stack switching.
 	 */
-	if ((ka->sa.sa_flags & SA_ONSTACK) && sas_ss_flags(sp))
+	if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp))
 		sp = current->sas_ss_sp + current->sas_ss_size;
 
 	/*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/traps.c linux/arch/arm/kernel/traps.c
--- linux.orig/arch/arm/kernel/traps.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/kernel/traps.c	2002-08-01 06:42:42.000000000 +0000
@@ -25,8 +25,6 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 
-#include <asm/atomic.h>
-#include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
@@ -53,7 +51,7 @@
  */
 static int verify_stack(unsigned long sp)
 {
-	if (sp < PAGE_OFFSET || sp > (unsigned long)high_memory)
+	if (sp < PAGE_OFFSET || (sp > (unsigned long)high_memory && high_memory != 0))
 		return -EFAULT;
 
 	return 0;
@@ -62,13 +60,15 @@
 /*
  * Dump out the contents of some memory nicely...
  */
-void dump_mem(unsigned long bottom, unsigned long top)
+static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
 {
 	unsigned long p = bottom & ~31;
 	int i;
 
+	printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
+
 	for (p = bottom & ~31; p < top;) {
-		printk("%08lx: ", p);
+		printk("%04lx: ", p & 0xffff);
 
 		for (i = 0; i < 8; i++, p += 4) {
 			unsigned int val;
@@ -79,21 +79,11 @@
 				__get_user(val, (unsigned long *)p);
 				printk("%08x ", val);
 			}
-			if (i == 3)
-				printk(" ");
 		}
 		printk ("\n");
 	}
 }
 
-/*
- * These constants are for searching for possible module text
- * segments.  VMALLOC_OFFSET comes from mm/vmalloc.c; MODULE_RANGE is
- * a guess of how much space is likely to be vmalloced.
- */
-#define VMALLOC_OFFSET (8*1024*1024)
-#define MODULE_RANGE (8*1024*1024)
-
 static void dump_instr(struct pt_regs *regs)
 {
 	unsigned long addr = instruction_pointer(regs);
@@ -102,7 +92,7 @@
 	int i;
 
 	printk("Code: ");
-	for (i = -2; i < 3; i++) {
+	for (i = -4; i < 1; i++) {
 		unsigned int val, bad;
 
 		if (thumb)
@@ -122,8 +112,7 @@
 
 static void dump_stack(struct task_struct *tsk, unsigned long sp)
 {
-	printk("Stack:\n");
-	dump_mem(sp - 16, 8192+(unsigned long)tsk);
+	dump_mem("Stack: ", sp - 16, 8192+(unsigned long)tsk);
 }
 
 static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
@@ -289,10 +278,9 @@
 		handler[reason], processor_modes[proc_mode]);
 
 	/*
-	 * We need to switch to kernel mode so that we can
-	 * use __get_user to safely read from kernel space.
-	 * Note that we now dump the code first, just in case
-	 * the backtrace kills us.
+	 * We need to switch to kernel mode so that we can use __get_user
+	 * to safely read from kernel space.  Note that we now dump the
+	 * code first, just in case the backtrace kills us.
 	 */
 	fs = get_fs();
 	set_fs(KERNEL_DS);
@@ -301,10 +289,8 @@
 	 * Dump out the vectors and stub routines.  Maybe a better solution
 	 * would be to dump them out only if we detect that they are corrupted.
 	 */
-	printk(KERN_CRIT "Vectors:\n");
-	dump_mem(vectors, 0x40);
-	printk(KERN_CRIT "Stubs:\n");
-	dump_mem(vectors + 0x200, 0x4b8);
+	dump_mem(KERN_CRIT "Vectors: ", vectors, vectors + 0x40);
+	dump_mem(KERN_CRIT "Stubs: ", vectors + 0x200, vectors + 0x4b8);
 
 	set_fs(fs);
 
@@ -528,11 +514,6 @@
 
 void abort(void)
 {
-	void *lr = __builtin_return_address(0);
-
-	printk(KERN_CRIT "abort() called from %p!  (Please "
-	       "report to rmk@arm.linux.org.uk)\n", lr);
-
 	BUG();
 
 	/* if that doesn't kill us, halt */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/kernel/via82c505.c linux/arch/arm/kernel/via82c505.c
--- linux.orig/arch/arm/kernel/via82c505.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/kernel/via82c505.c	2002-08-01 06:42:28.000000000 +0000
@@ -157,8 +157,15 @@
 	struct pci_bus *bus;
 
 	printk(KERN_DEBUG "PCI: VIA 82c505\n");
-	request_region(0xA8,2,"via config");
-	request_region(0xCF8,8,"pci config");
+	if (!request_region(0xA8,2,"via config")) {
+		printk(KERN_WARNING"VIA 82c505: Unable to request region 0xA8\n");
+		return;
+	}
+	if (!request_region(0xCF8,8,"pci config")) {
+		printk(KERN_WARNING"VIA 82c505: Unable to request region 0xCF8\n");
+		release_region(0xA8, 2);
+		return;
+	}
 
 	/* Enable compatible Mode */
 	outb(0x96,0xA8);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/lib/backtrace.S linux/arch/arm/lib/backtrace.S
--- linux.orig/arch/arm/lib/backtrace.S	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/lib/backtrace.S	2002-08-01 06:42:33.000000000 +0000
@@ -26,7 +26,7 @@
 
 ENTRY(c_backtrace)
 
-#ifdef CONFIG_NO_FRAME_POINTER
+#ifndef CONFIG_FRAME_POINTER
 		mov	pc, lr
 #else
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/lib/ecard.S linux/arch/arm/lib/ecard.S
--- linux.orig/arch/arm/lib/ecard.S	2000-11-28 01:07:59.000000000 +0000
+++ linux/arch/arm/lib/ecard.S	2002-08-01 06:42:38.000000000 +0000
@@ -12,7 +12,7 @@
 #include <asm/assembler.h>
 #include <asm/hardware.h>
 
-#if defined(CONFIG_CPU_26)
+#ifdef CONFIG_CPU_26
 #define CPSR2SPSR(rt)
 #else
 #define CPSR2SPSR(rt) \
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/lib/getuser.S linux/arch/arm/lib/getuser.S
--- linux.orig/arch/arm/lib/getuser.S	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/lib/getuser.S	2002-08-01 06:42:44.000000000 +0000
@@ -80,8 +80,9 @@
 
 	/* fall through */
 
-__get_user_bad:
+__get_user_bad_8:
 	mov	r2, #0
+__get_user_bad:
 	mov	r1, #0
 	mov	r0, #-14
 	mov	pc, lr
@@ -91,6 +92,6 @@
 	.long	2b, __get_user_bad
 	.long	3b, __get_user_bad
 	.long	4b, __get_user_bad
-	.long	5b, __get_user_bad
-	.long	6b, __get_user_bad
+	.long	5b, __get_user_bad_8
+	.long	6b, __get_user_bad_8
 .previous
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/lib/io-acorn.S linux/arch/arm/lib/io-acorn.S
--- linux.orig/arch/arm/lib/io-acorn.S	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/lib/io-acorn.S	2002-08-01 06:42:33.000000000 +0000
@@ -58,7 +58,7 @@
 @ Proto  : void memc_write(int register, int value);
 @ Returns: nothing
 
-#if defined(CONFIG_CPU_26)
+#ifdef CONFIG_CPU_26
 ENTRY(memc_write)
 		cmp	r0, #7
 		RETINSTR(movgt,pc,lr)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/lib/io-shark.c linux/arch/arm/lib/io-shark.c
--- linux.orig/arch/arm/lib/io-shark.c	2001-04-12 19:20:31.000000000 +0000
+++ linux/arch/arm/lib/io-shark.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/lib/io-shark.c
  *
- *  by Alexander Schulz <aschulz@netwinder.org>
+ *  by Alexander Schulz
  *
  * derived from:
  * linux/arch/arm/lib/io-ebsa.S
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/lib/strrchr.S linux/arch/arm/lib/strrchr.S
--- linux.orig/arch/arm/lib/strrchr.S	2000-09-18 22:15:25.000000000 +0000
+++ linux/arch/arm/lib/strrchr.S	2002-08-01 06:42:45.000000000 +0000
@@ -18,7 +18,7 @@
 		mov	r3, #0
 1:		ldrb	r2, [r0], #1
 		teq	r2, r1
-		moveq	r3, r0
+		subeq	r3, r0, #1
 		teq	r2, #0
 		bne	1b
 		mov	r0, r3
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/Makefile linux/arch/arm/mach-clps711x/Makefile
--- linux.orig/arch/arm/mach-clps711x/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/Makefile	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,30 @@
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET		:= clps711x.o
+
+# Object file lists.
+
+obj-y			:= irq.o mm.o time.o
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+export-objs		:= leds-p720t.o
+
+obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
+obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
+obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
+obj-$(CONFIG_ARCH_EDB7211) += edb7211-arch.o edb7211-mm.o
+obj-$(CONFIG_ARCH_P720T) += p720t.o
+obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
+leds-$(CONFIG_ARCH_P720T) += p720t-leds.o
+obj-$(CONFIG_LEDS)	+= $(leds-y)
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/autcpu12.c linux/arch/arm/mach-clps711x/autcpu12.c
--- linux.orig/arch/arm/mach-clps711x/autcpu12.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/autcpu12.c	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,72 @@
+/*
+ *  linux/arch/arm/mach-clps711x/autcpu12.c
+ *
+ * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/blk.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/hardware.h>
+#include <asm/sizes.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/arch/autcpu12.h>
+
+extern void clps711x_map_io(void);
+extern void clps711x_init_irq(void);
+
+/*
+ * The on-chip registers are given a size of 1MB so that a section can
+ * be used to map them; this saves a page table.  This is the place to
+ * add mappings for ROM, expansion memory, PCMCIA, etc.  (if static
+ * mappings are chosen for those areas).
+ *
+*/
+
+static struct map_desc autcpu12_io_desc[] __initdata = {
+ /* virtual, physical, length, domain, r, w, c, b */
+ /* memory-mapped extra io and CS8900A Ethernet chip */
+ /* ethernet chip */
+ 	{ AUTCPU12_VIRT_CS8900A, AUTCPU12_PHYS_CS8900A, SZ_1M, DOMAIN_IO, 1, 1, 0, 0 },
+	
+ 	LAST_DESC
+};
+
+void __init autcpu12_map_io(void)
+{
+        clps711x_map_io();
+        iotable_init(autcpu12_io_desc);
+}
+
+MACHINE_START(AUTCPU12, "autronix autcpu12")
+	MAINTAINER("Thomas Gleixner")
+        BOOT_MEM(0xc0000000, 0x80000000, 0xff000000)
+	BOOT_PARAMS(0xc0020000)
+	MAPIO(autcpu12_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/cdb89712.c linux/arch/arm/mach-clps711x/cdb89712.c
--- linux.orig/arch/arm/mach-clps711x/cdb89712.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/cdb89712.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/mach-clps711x/cdb89712.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+extern void clps711x_init_irq(void);
+extern void clps711x_map_io(void);
+
+/*
+ * Map the CS89712 Ethernet port.  That should be moved to the
+ * ethernet driver, perhaps.
+ */
+static struct map_desc cdb89712_io_desc[] __initdata = {
+	{ ETHER_BASE, ETHER_START, ETHER_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
+	LAST_DESC
+};
+
+static void __init
+fixup_cdb89712(struct machine_desc *desc, struct param_struct *params,
+	    char **cmdline, struct meminfo *mi)
+{
+}
+
+static void __init cdb89712_map_io(void)
+{
+	clps711x_map_io();
+	iotable_init(cdb89712_io_desc);
+}
+
+MACHINE_START(CDB89712, "Cirrus-CDB89712")
+	MAINTAINER("Ray Lehtiniemi")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xff000000)
+	BOOT_PARAMS(0xc0000100)
+	FIXUP(fixup_cdb89712)
+	MAPIO(cdb89712_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END
+
+static int cdb89712_hw_init(void)
+{
+	return 0;
+}
+
+__initcall(cdb89712_hw_init);
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/clep7312.c linux/arch/arm/mach-clps711x/clep7312.c
--- linux.orig/arch/arm/mach-clps711x/clep7312.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/clep7312.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,49 @@
+/*
+ *  linux/arch/arm/mach-clps711x/clep7312.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+extern void clps711x_init_irq(void);
+extern void clps711x_map_io(void); 
+
+static void __init
+fixup_clep7312(struct machine_desc *desc, struct param_struct *params,
+	    char **cmdline, struct meminfo *mi)
+{
+	mi->nr_banks=1;
+	mi->end = 0xc0FFFFFF;
+	mi->bank[0].start = 0xc0000000;
+	mi->bank[0].size = 0x01000000;
+	mi->bank[0].node = 0;
+}
+
+
+MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
+	MAINTAINER("Nobody")
+        BOOT_MEM(0xc0000000, 0x80000000, 0xff000000)
+	BOOT_PARAMS(0xc0000100)
+	FIXUP(fixup_clep7312)
+	MAPIO(clps711x_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/dma.c linux/arch/arm/mach-clps711x/dma.c
--- linux.orig/arch/arm/mach-clps711x/dma.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/dma.c	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,35 @@
+/*
+ *  linux/arch/arm/mach-clps711x/dma.c
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/mman.h>
+#include <linux/init.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+
+#include <asm/mach/dma.h>
+
+void __init arch_dma_init(dma_t *dma)
+{
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/edb7211-arch.c linux/arch/arm/mach-clps711x/edb7211-arch.c
--- linux.orig/arch/arm/mach-clps711x/edb7211-arch.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/edb7211-arch.c	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,59 @@
+/*
+ *  linux/arch/arm/mach-clps711x/arch-edb7211.c
+ *
+ *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+extern void clps711x_init_irq(void);
+extern void edb7211_map_io(void);
+
+static void __init
+fixup_edb7211(struct machine_desc *desc, struct param_struct *params,
+	      char **cmdline, struct meminfo *mi)
+{
+	/*
+	 * Bank start addresses are not present in the information
+	 * passed in from the boot loader.  We could potentially
+	 * detect them, but instead we hard-code them.
+	 *
+	 * Banks sizes _are_ present in the param block, but we're
+	 * not using that information yet.
+	 */
+	mi->bank[0].start = 0xc0000000;
+	mi->bank[0].size = 8*1024*1024;
+	mi->bank[0].node = 0;
+	mi->bank[1].start = 0xc1000000;
+	mi->bank[1].size = 8*1024*1024;
+	mi->bank[1].node = 1;
+	mi->nr_banks = 2;
+}
+
+MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
+	MAINTAINER("Jon McClintock")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xff000000)
+	BOOT_PARAMS(0xc0020100)	/* 0xc0000000 - 0xc001ffff can be video RAM */
+	FIXUP(fixup_edb7211)
+	MAPIO(edb7211_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/edb7211-mm.c linux/arch/arm/mach-clps711x/edb7211-mm.c
--- linux.orig/arch/arm/mach-clps711x/edb7211-mm.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/edb7211-mm.c	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/mach-clps711x/mm.c
+ *
+ *  Extra MM routines for the EDB7211 board
+ *
+ *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+ 
+#include <asm/mach/map.h>
+
+#define MB1 1048576	/* one megabyte == size of an MMU section */
+
+extern void clps711x_map_io(void);
+
+/*
+ * The on-chip registers are given a size of 1MB so that a section can
+ * be used to map them; this saves a page table.  This is the place to
+ * add mappings for ROM, expansion memory, PCMCIA, etc.  (if static
+ * mappings are chosen for those areas).
+ *
+ * Here is a physical memory map (to be fleshed out later):
+ *
+ * Physical Address  Size  Description
+ * ----------------- ----- ---------------------------------
+ * c0000000-c001ffff 128KB reserved for video RAM [1]
+ * c0020000-c0023fff  16KB parameters (see Documentation/arm/Setup)
+ * c0024000-c0027fff  16KB swapper_pg_dir (task 0 page directory)
+ * c0028000-...            kernel image (TEXTADDR)
+ *
+ * [1] Unused pages should be given back to the VM; they are not yet.
+ *     The parameter block should also be released (not sure if this
+ *     happens).
+ */
+static struct map_desc edb7211_io_desc[] __initdata = {
+ /* virtual, physical, length, domain, r, w, c, b */
+
+ /* memory-mapped extra keyboard row and CS8900A Ethernet chip */
+ { EP7211_VIRT_EXTKBD, EP7211_PHYS_EXTKBD, MB1, DOMAIN_IO, 1, 1, 0, 0 }, 
+ { EP7211_VIRT_CS8900A, EP7211_PHYS_CS8900A, MB1, DOMAIN_IO, 1, 1, 0, 0 },
+
+ /* flash banks */
+ { EP7211_VIRT_FLASH1, EP7211_PHYS_FLASH1, MB1 * 8, DOMAIN_KERNEL, 1, 1, 0, 0 },
+ { EP7211_VIRT_FLASH2, EP7211_PHYS_FLASH2, MB1 * 8, DOMAIN_KERNEL, 1, 1, 0, 0 },
+
+ LAST_DESC
+};
+
+void __init edb7211_map_io(void)
+{
+        clps711x_map_io();
+        iotable_init(edb7211_io_desc);
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/fortunet.c linux/arch/arm/mach-clps711x/fortunet.c
--- linux.orig/arch/arm/mach-clps711x/fortunet.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/fortunet.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,81 @@
+/*
+ *  linux/arch/arm/mach-clps711x/fortunet.c
+ *
+ *  Derived from linux/arch/arm/mach-integrator/arch.c
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/blk.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/amba_kmi.h>
+
+extern void clps711x_map_io(void);
+extern void clps711x_init_irq(void);
+
+struct meminfo memmap = { 1, 0xC1000000, {{0xC0000000,0x01000000,0}}};
+
+typedef struct tag_IMAGE_PARAMS
+{
+	int	ramdisk_ok;
+	int	ramdisk_address;
+	int	ramdisk_size;
+	int	ram_size;
+	int	extra_param_type;
+	int	extra_param_ptr;
+	int	command_line;
+} IMAGE_PARAMS;
+
+#define IMAGE_PARAMS_PHYS	0xC01F0000
+
+static void __init
+fortunet_fixup(struct machine_desc *desc, struct param_struct *params,
+		 char **cmdline, struct meminfo *mi)
+{
+	IMAGE_PARAMS *ip;
+	ip = (IMAGE_PARAMS *)__phys_to_virt(IMAGE_PARAMS_PHYS);
+	*cmdline = (char *)__phys_to_virt(ip->command_line);
+#ifdef CONFIG_BLK_DEV_INITRD
+	if(ip->ramdisk_ok)
+	{
+		initrd_start = __phys_to_virt(ip->ramdisk_address);
+		initrd_end = initrd_start + ip->ramdisk_size;
+	}
+#endif
+	memmap.bank[0].size = ip->ram_size;
+	memmap.end = ip->ram_size+0xC0000000;
+	*mi = memmap;
+}
+
+MACHINE_START(FORTUNET, "ARM-FortuNet")
+	MAINTAINER("FortuNet Inc.")
+        BOOT_MEM(0xc0000000, 0x80000000, 0xf0000000)
+	BOOT_PARAMS(0x00000000)
+	FIXUP(fortunet_fixup)
+	MAPIO(clps711x_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/irq.c linux/arch/arm/mach-clps711x/irq.c
--- linux.orig/arch/arm/mach-clps711x/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/irq.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,138 @@
+/*
+ *  linux/arch/arm/mach-clps711x/irq.c
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+
+#include <asm/mach/irq.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/hardware/clps7111.h>
+
+static void mask_irq_int1(unsigned int irq)
+{
+	u32 intmr1;
+
+	intmr1 = clps_readl(INTMR1);
+	intmr1 &= ~(1 << irq);
+	clps_writel(intmr1, INTMR1);
+}
+
+static void mask_ack_irq_int1(unsigned int irq)
+{
+	u32 intmr1;
+
+	intmr1 = clps_readl(INTMR1);
+	intmr1 &= ~(1 << irq);
+	clps_writel(intmr1, INTMR1);
+
+	switch (irq) {
+	case IRQ_CSINT:  clps_writel(0, COEOI);  break;
+	case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
+	case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
+	case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
+	case IRQ_TINT:   clps_writel(0, TEOI);   break;
+	case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
+	}
+}
+
+static void unmask_irq_int1(unsigned int irq)
+{
+	u32 intmr1;
+
+	intmr1 = clps_readl(INTMR1);
+	intmr1 |= 1 << irq;
+	clps_writel(intmr1, INTMR1);
+}
+
+static void mask_irq_int2(unsigned int irq)
+{
+	u32 intmr2;
+
+	intmr2 = clps_readl(INTMR2);
+	intmr2 &= ~(1 << (irq - 16));
+	clps_writel(intmr2, INTMR2);
+}
+
+static void mask_ack_irq_int2(unsigned int irq)
+{
+	u32 intmr2;
+
+	intmr2 = clps_readl(INTMR2);
+	intmr2 &= ~(1 << (irq - 16));
+	clps_writel(intmr2, INTMR2);
+
+	switch (irq) {
+	case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
+	}
+}
+
+static void unmask_irq_int2(unsigned int irq)
+{
+	u32 intmr2;
+
+	intmr2 = clps_readl(INTMR2);
+	intmr2 |= 1 << (irq - 16);
+	clps_writel(intmr2, INTMR2);
+}
+
+void __init clps711x_init_irq(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < NR_IRQS; i++) {
+	        if (INT1_IRQS & (1 << i)) {
+		        irq_desc[i].valid	= 1;
+			irq_desc[i].probe_ok	= 1;
+			irq_desc[i].mask_ack	= (INT1_ACK_IRQS & (1 << i)) ?
+						   mask_ack_irq_int1 :
+						   mask_irq_int1;
+			irq_desc[i].mask	= mask_irq_int1;
+			irq_desc[i].unmask	= unmask_irq_int1;
+		}
+		if (INT2_IRQS & (1 << i)) {
+		        irq_desc[i].valid	= 1;
+			irq_desc[i].probe_ok	= 1;
+			irq_desc[i].mask_ack	= (INT2_ACK_IRQS & (1 << i)) ?
+						   mask_ack_irq_int2 :
+						   mask_irq_int2;
+			irq_desc[i].mask	= mask_irq_int2;
+			irq_desc[i].unmask	= unmask_irq_int2;
+		}			
+	}
+
+	/*
+	 * Disable interrupts
+	 */
+	clps_writel(0, INTMR1);
+	clps_writel(0, INTMR2);
+
+	/*
+	 * Clear down any pending interrupts
+	 */
+	clps_writel(0, COEOI);
+	clps_writel(0, TC1EOI);
+	clps_writel(0, TC2EOI);
+	clps_writel(0, RTCEOI);
+	clps_writel(0, TEOI);
+	clps_writel(0, UMSEOI);
+	clps_writel(0, SYNCIO);
+	clps_writel(0, KBDEOI);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/mm.c linux/arch/arm/mach-clps711x/mm.c
--- linux.orig/arch/arm/mach-clps711x/mm.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/mm.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,70 @@
+/*
+ *  linux/arch/arm/mach-clps711x/mm.c
+ *
+ *  Generic MM setup for the CLPS711x-based machines.
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/config.h>
+#include <linux/bootmem.h>
+
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/clps7111.h>
+
+#if 0 //def CONFIG_DISCONTIGMEM
+  
+/*
+ * The assumption of maximum 4 discontiguous memory banks is present
+ * in several places in the ARM kernel, including the parameter block
+ * (this affects boot loaders, too).  Banks do not necessarily
+ * correspond 1:1 with NUMA nodes, although they usually will,
+ * especially if they are widely discontiguous.
+ *
+ *  - note that the parameter block is depreciated for new implementations
+ *  - also note that discontig_node_data is actually used
+ *    -- rmk 
+ */
+
+static bootmem_data_t node_bootmem_data[4];
+
+pg_data_t clps711x_node_data[4] = {
+        { bdata: &node_bootmem_data[0] },
+        { bdata: &node_bootmem_data[1] },
+        { bdata: &node_bootmem_data[2] },
+        { bdata: &node_bootmem_data[3] },
+};
+
+#endif
+
+/*
+ * This maps the generic CLPS711x registers
+ */
+static struct map_desc clps711x_io_desc[] __initdata = {
+ { CLPS7111_VIRT_BASE,	CLPS7111_PHYS_BASE,	1048576, DOMAIN_IO, 0, 1 },
+ LAST_DESC
+};
+
+void __init clps711x_map_io(void)
+{
+	iotable_init(clps711x_io_desc);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/p720t-leds.c linux/arch/arm/mach-clps711x/p720t-leds.c
--- linux.orig/arch/arm/mach-clps711x/p720t-leds.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/p720t-leds.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,67 @@
+/*
+ *  linux/arch/arm/mach-clps711x/leds.c
+ *
+ *  Integrator LED control routines
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+#include <asm/mach-types.h>
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+
+static void p720t_leds_event(led_event_t ledevt)
+{
+	unsigned long flags;
+	u32 pddr;
+
+	local_irq_save(flags);
+	switch(ledevt) {
+	case led_idle_start:
+		break;
+
+	case led_idle_end:
+		break;
+
+	case led_timer:
+		pddr = clps_readb(PDDR);
+		clps_writeb(pddr ^ 1, PDDR);
+		break;
+
+	default:
+		break;
+	}
+
+	local_irq_restore(flags);
+}
+
+static int __init leds_init(void)
+{
+	if (machine_is_p720t())
+		leds_event = p720t_leds_event;
+
+	return 0;
+}
+
+__initcall(leds_init);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/p720t.c linux/arch/arm/mach-clps711x/p720t.c
--- linux.orig/arch/arm/mach-clps711x/p720t.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/p720t.c	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,118 @@
+/*
+ *  linux/arch/arm/mach-clps711x/p720t.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/syspld.h>
+
+extern void clps711x_init_irq(void);
+extern void clps711x_map_io(void);
+
+/*
+ * Map the P720T system PLD.  It occupies two address spaces:
+ *  SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
+ * We map both here.
+ */
+static struct map_desc p720t_io_desc[] __initdata = {
+	{ SYSPLD_VIRT_BASE,	SYSPLD_PHYS_BASE, 1048576, DOMAIN_IO, 0, 1 },
+	{ 0xfe400000,		0x10400000,	  1048576, DOMAIN_IO, 0, 1 },
+	LAST_DESC
+};
+
+static void __init
+fixup_p720t(struct machine_desc *desc, struct param_struct *params,
+	    char **cmdline, struct meminfo *mi)
+{
+	struct tag *tag = (struct tag *)params;
+
+	/*
+	 * Our bootloader doesn't setup any tags (yet).
+	 */
+	if (tag->hdr.tag != ATAG_CORE) {
+		tag->hdr.tag = ATAG_CORE;
+		tag->hdr.size = tag_size(tag_core);
+		tag->u.core.flags = 0;
+		tag->u.core.pagesize = PAGE_SIZE;
+		tag->u.core.rootdev = 0x0100;
+
+		tag = tag_next(tag);
+		tag->hdr.tag = ATAG_MEM;
+		tag->hdr.size = tag_size(tag_mem32);
+		tag->u.mem.size = 4096;
+		tag->u.mem.start = PHYS_OFFSET;
+
+		tag = tag_next(tag);
+		tag->hdr.tag = ATAG_NONE;
+		tag->hdr.size = 0;
+	}
+}
+
+static void __init p720t_map_io(void)
+{
+	clps711x_map_io();
+	iotable_init(p720t_io_desc);
+}
+
+MACHINE_START(P720T, "ARM-Prospector720T")
+	MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xff000000)
+	BOOT_PARAMS(0xc0000100)
+	FIXUP(fixup_p720t)
+	MAPIO(p720t_map_io)
+	INITIRQ(clps711x_init_irq)
+MACHINE_END
+
+static int p720t_hw_init(void)
+{
+	/*
+	 * Power down as much as possible in case we don't
+	 * have the drivers loaded.
+	 */
+	PLD_LCDEN = 0;
+	PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
+
+	PLD_KBD   = 0;
+	PLD_IO    = 0;
+	PLD_IRDA  = 0;
+	PLD_CODEC = 0;
+	PLD_TCH   = 0;
+	PLD_SPI   = 0;
+#ifndef CONFIG_DEBUG_LL
+	PLD_COM2  = 0;
+	PLD_COM1  = 0;
+#endif
+
+	return 0;
+}
+
+__initcall(p720t_hw_init);
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-clps711x/time.c linux/arch/arm/mach-clps711x/time.c
--- linux.orig/arch/arm/mach-clps711x/time.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-clps711x/time.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,54 @@
+/*
+ *  linux/arch/arm/mach-clps711x/time.c
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/hardware/clps7111.h>
+
+extern unsigned long (*gettimeoffset)(void);
+
+/*
+ * gettimeoffset() returns time since last timer tick, in usecs.
+ *
+ * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * 'tick' is usecs per jiffy.
+ */
+static unsigned long clps711x_gettimeoffset(void)
+{
+	unsigned long hwticks;
+	hwticks = LATCH - (clps_readl(TC2D) & 0xffff);	/* since last underflow */
+	return (hwticks * tick) / LATCH;
+}
+
+void __init clps711x_setup_timer(void)
+{
+	unsigned int syscon;
+
+	gettimeoffset = clps711x_gettimeoffset;
+
+	syscon = clps_readl(SYSCON1);
+	syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
+	clps_writel(syscon, SYSCON1);
+
+	clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+
+	xtime.tv_sec = clps_readl(RTCDR);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-ebsa110/io.c linux/arch/arm/mach-ebsa110/io.c
--- linux.orig/arch/arm/mach-ebsa110/io.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-ebsa110/io.c	2002-08-01 06:42:39.000000000 +0000
@@ -139,7 +139,11 @@
 	 ((p) >> 3) == (0x2f8 >> 3) || \
 	 ((p) >> 3) == (0x378 >> 3))
 
-u8 __inb(int port)
+/*
+ * We're addressing an 8 or 16-bit peripheral which tranfers
+ * odd addresses on the low ISA byte lane.
+ */
+u8 __inb8(unsigned int port)
 {
 	u32 ret;
 
@@ -162,7 +166,11 @@
 	return ret;
 }
 
-u16 __inw(int port)
+/*
+ * We're addressing a 16-bit peripheral which transfers odd
+ * addresses on the high ISA byte lane.
+ */
+u8 __inb16(unsigned int port)
 {
 	u32 ret;
 
@@ -170,13 +178,33 @@
 	 * The SuperIO registers use sane addressing techniques...
 	 */
 	if (SUPERIO_PORT(port))
-		ret = __arch_getw(ISAIO_BASE + (port << 2));
+		ret = __arch_getb(ISAIO_BASE + (port << 2));
 	else {
 		u32 a = ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
 		 */
+		ret = __arch_getb(a + (port & 1));
+	}
+	return ret;
+}
+
+u16 __inw(unsigned int port)
+{
+	u32 ret;
+
+	/*
+	 * The SuperIO registers use sane addressing techniques...
+	 */
+	if (SUPERIO_PORT(port) || port & 1)
+		ret = __arch_getw(ISAIO_BASE + (port << 2));
+	else {
+		u32 a = ISAIO_BASE + (port << 1);
+
+		/*
+		 * Shame nothing else does
+		 */
 		if (port & 1)
 			BUG();
 
@@ -185,17 +213,27 @@
 	return ret;
 }
 
-u32 __inl(int port)
+/*
+ * Fake a 32-bit read with two 16-bit reads.  Needed for 3c589.
+ */
+u32 __inl(unsigned int port)
 {
-	BUG();
-	return 0;
+	u32 a;
+
+	if (SUPERIO_PORT(port) || port & 3)
+		BUG();
+
+	a = ISAIO_BASE + (port << 1);
+
+	return __arch_getw(a) | __arch_getw(a + 4) << 16;
 }
 
-EXPORT_SYMBOL(__inb);
+EXPORT_SYMBOL(__inb8);
+EXPORT_SYMBOL(__inb16);
 EXPORT_SYMBOL(__inw);
 EXPORT_SYMBOL(__inl);
 
-void __outb(u8 val, int port)
+void __outb8(u8 val, unsigned int port)
 {
 	/*
 	 * The SuperIO registers use sane addressing techniques...
@@ -215,7 +253,24 @@
 	}
 }
 
-void __outw(u16 val, int port)
+void __outb16(u8 val, unsigned int port)
+{
+	/*
+	 * The SuperIO registers use sane addressing techniques...
+	 */
+	if (SUPERIO_PORT(port))
+		__arch_putb(val, ISAIO_BASE + (port << 2));
+	else {
+		u32 a = ISAIO_BASE + ((port & ~1) << 1);
+
+		/*
+		 * Shame nothing else does
+		 */
+		__arch_putb(val, a + (port & 1));
+	}
+}
+
+void __outw(u16 val, unsigned int port)
 {
 	u32 off;
 
@@ -225,7 +280,7 @@
 	if (SUPERIO_PORT(port))
 		off = port << 2;
 	else {
-		off = (port & ~1) << 1;
+		off = port << 1;
 		if (port & 1)
 			BUG();
 
@@ -233,12 +288,13 @@
 	__arch_putw(val, ISAIO_BASE + off);
 }
 
-void __outl(u32 val, int port)
+void __outl(u32 val, unsigned int port)
 {
 	BUG();
 }
 
-EXPORT_SYMBOL(__outb);
+EXPORT_SYMBOL(__outb8);
+EXPORT_SYMBOL(__outb16);
 EXPORT_SYMBOL(__outw);
 EXPORT_SYMBOL(__outl);
 
@@ -315,12 +371,29 @@
 EXPORT_SYMBOL(outsw);
 EXPORT_SYMBOL(insw);
 
+/*
+ * We implement these as 16-bit insw/outsw, mainly for
+ * 3c589 cards.
+ */
 void outsl(unsigned int port, const void *from, int len)
 {
-	panic("outsl not supported on this architecture");
+	u32 off = port << 1;
+
+	if (SUPERIO_PORT(port) || port & 3)
+		BUG();
+
+	__raw_writesw(ISAIO_BASE + off, from, len << 1);
 }
 
 void insl(unsigned int port, void *from, int len)
 {
-	panic("insl not supported on this architecture");
+	u32 off = port << 1;
+
+	if (SUPERIO_PORT(port) || port & 3)
+		BUG();
+
+	__raw_readsw(ISAIO_BASE + off, from, len << 1);
 }
+
+EXPORT_SYMBOL(outsl);
+EXPORT_SYMBOL(insl);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-epxa10db/arch.c linux/arch/arm/mach-epxa10db/arch.c
--- linux.orig/arch/arm/mach-epxa10db/arch.c	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/mach-epxa10db/arch.c	2002-08-01 06:42:45.000000000 +0000
@@ -18,7 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-epxa10db/mm.c linux/arch/arm/mach-epxa10db/mm.c
--- linux.orig/arch/arm/mach-epxa10db/mm.c	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/mach-epxa10db/mm.c	2002-08-01 06:42:46.000000000 +0000
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/sizes.h>
  
 #include <asm/mach/map.h>
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-integrator/pci_v3.c linux/arch/arm/mach-integrator/pci_v3.c
--- linux.orig/arch/arm/mach-integrator/pci_v3.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-integrator/pci_v3.c	2002-08-01 06:42:34.000000000 +0000
@@ -20,6 +20,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+#include <linux/config.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
@@ -411,12 +412,19 @@
 	flags:	IORESOURCE_MEM | IORESOURCE_PREFETCH,
 };
 
-void __init pci_v3_setup_resources(struct resource **resource)
+int __init pci_v3_setup_resources(struct resource **resource)
 {
-	if (request_resource(&iomem_resource, &non_mem))
-		printk("PCI: unable to allocate non-prefetchable memory region\n");
-	if (request_resource(&iomem_resource, &pre_mem))
-		printk("PCI: unable to allocate prefetchable memory region\n");
+	if (request_resource(&iomem_resource, &non_mem)) {
+		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
+		       "memory region\n");
+		return -EBUSY;
+	}
+	if (request_resource(&iomem_resource, &pre_mem)) {
+		release_resource(&non_mem);
+		printk(KERN_ERR "PCI: unable to allocate prefetchable "
+		       "memory region\n");
+		return -EBUSY;
+	}
 
 	/*
 	 * bus->resource[0] is the IO resource for this bus
@@ -426,6 +434,8 @@
 	resource[0] = &ioport_resource;
 	resource[1] = &non_mem;
 	resource[2] = &pre_mem;
+
+	return 1;
 }
 
 /*
@@ -433,18 +443,23 @@
  * means I can't get additional information on the reason for the pm2fb
  * problems.  I suppose I'll just have to mind-meld with the machine. ;)
  */
-#define SC_PCI     (IO_ADDRESS(INTEGRATOR_SC_PCIENABLE))
-#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE+0x20))
-#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE+0x24))
+#define SC_PCI     (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET)
+#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20)
+#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24)
 
 static int v3_fault(unsigned long addr, struct pt_regs *regs)
 {
 	unsigned long pc = instruction_pointer(regs);
 	unsigned long instr = *(unsigned long *)pc;
+#if 0
+	char buf[128];
 
-	printk("V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
+	sprintf(buf, "V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
 		addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
 		v3_readb(V3_LB_ISTAT));
+	printk(KERN_DEBUG "%s", buf);
+	printascii(buf);
+#endif
 
 	v3_writeb(V3_LB_ISTAT, 0);
 	__raw_writel(3, SC_PCI);
@@ -467,11 +482,20 @@
 		return 0;
 	}
 
+	if ((instr & 0x0e100090) == 0x00100090) {
+		int reg = (instr >> 12) & 15;
+
+		regs->uregs[reg] = -1;
+		regs->ARM_pc += 4;
+		return 0;
+	}
+
 	return 1;
 }
 
 static void v3_irq(int irq, void *devid, struct pt_regs *regs)
 {
+#ifdef CONFIG_DEBUG_LL
 	unsigned long pc = instruction_pointer(regs);
 	unsigned long instr = *(unsigned long *)pc;
 	char buf[128];
@@ -480,10 +504,13 @@
 		pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
 		v3_readb(V3_LB_ISTAT));
 	printascii(buf);
+#endif
 
+	v3_writew(V3_PCI_STAT, 0xf000);
 	v3_writeb(V3_LB_ISTAT, 0);
 	__raw_writel(3, SC_PCI);
 
+#ifdef CONFIG_DEBUG_LL
 	/*
 	 * If the instruction being executed was a read,
 	 * make it look like it read all-ones.
@@ -493,17 +520,9 @@
 		sprintf(buf, "   reg%d = %08lx\n", reg, regs->uregs[reg]);
 		printascii(buf);
 	}
+#endif
 }
 
-static struct irqaction v3_int = {
-	name: "V3",
-	handler: v3_irq,
-};
-static struct irqaction v3_int2 = {
-	name: "V3TM",
-	handler: v3_irq,
-};
-
 extern int (*external_fault)(unsigned long addr, struct pt_regs *regs);
 
 /*
@@ -514,6 +533,8 @@
 {
 	unsigned int pci_cmd;
 	unsigned long flags;
+	unsigned int temp;
+	int ret;
 
 	/*
 	 * Hook in our fault handler for PCI errors
@@ -523,6 +544,12 @@
 	spin_lock_irqsave(&v3_lock, flags);
 
 	/*
+	 * Unlock V3 registers, but only if they were previously locked.
+	 */
+	if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
+		v3_writew(V3_SYSTEM, 0xa05f);
+
+	/*
 	 * Setup window 0 - PCI non-prefetchable memory
 	 *  Local: 0x40000000 Bus: 0x00000000 Size: 256MB
 	 */
@@ -548,6 +575,45 @@
 			V3_LB_BASE_ENABLE);
 	v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
 
+	/*
+	 * Disable PCI to host IO cycles
+	 */
+	temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
+	temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
+	v3_writew(V3_PCI_CFG, temp);
+
+	printk(KERN_DEBUG "FIFO_CFG: %04x  FIFO_PRIO: %04x\n",
+		v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
+
+	/*
+	 * Set the V3 FIFO such that writes have higher priority than
+	 * reads, and local bus write causes local bus read fifo flush.
+	 * Same for PCI.
+	 */
+	v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
+
+	/*
+	 * Re-lock the system register.
+	 */
+	temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
+	v3_writew(V3_SYSTEM, temp);
+
+	/*
+	 * Clear any error conditions, and enable write errors.
+	 */
+	v3_writeb(V3_LB_ISTAT, 0);
+	v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
+	v3_writeb(V3_LB_IMASK, 0x28);
+	__raw_writel(3, SC_PCI);
+
+	/*
+	 * Grab the PCI error interrupt.
+	 */
+	ret = request_irq(IRQ_V3INT, v3_irq, 0, "V3 error", NULL);
+	if (ret)
+		printk(KERN_ERR "PCI: unable to grab PCI error "
+		       "interrupt: %d\n", ret);
+
 	spin_unlock_irqrestore(&v3_lock, flags);
 
 	pci_scan_bus(0, &pci_v3_ops, sysdata);
@@ -557,18 +623,13 @@
 
 	v3_writew(V3_PCI_CMD, pci_cmd);
 
-	/*
-	 * Clear any error conditions.
-	 */
-	__raw_writel(3, SC_PCI);
-	v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
-	v3_writeb(V3_LB_ISTAT, 0);
+	v3_writeb(V3_LB_ISTAT, ~0x40);
 	v3_writeb(V3_LB_IMASK, 0x68);
 
-	printk("LB_CFG: %04x LB_ISTAT: %02x LB_IMASK: %02x\n",
-		v3_readw(V3_LB_CFG),
-		v3_readb(V3_LB_ISTAT),
-		v3_readb(V3_LB_IMASK));
-	setup_arm_irq(IRQ_V3INT, &v3_int);
-//	setup_arm_irq(IRQ_LBUSTIMEOUT, &v3_int2);
+#if 0
+	ret = request_irq(IRQ_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
+	if (ret)
+		printk(KERN_ERR "PCI: unable to grab local bus timeout ".
+		       "interrupt: %d\n", ret);
+#endif
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-mx1ads/Makefile linux/arch/arm/mach-mx1ads/Makefile
--- linux.orig/arch/arm/mach-mx1ads/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-mx1ads/Makefile	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,20 @@
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET		:= mx1ads.o
+
+# Object file lists.
+
+obj-y			:= arch.o cpu.o irq.o mm.o time.o
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-mx1ads/arch.c linux/arch/arm/mach-mx1ads/arch.c
--- linux.orig/arch/arm/mach-mx1ads/arch.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-mx1ads/arch.c	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,59 @@
+/*
+ *  linux/arch/arm/mach-mx1ads/arch.c
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/amba_kmi.h>
+
+extern void mx1ads_map_io(void);
+extern void mx1ads_init_irq(void);
+
+
+static void __init
+mx1ads_fixup(struct machine_desc *desc, struct param_struct *unused,
+		 char **cmdline, struct meminfo *mi)
+{
+}
+
+MACHINE_START(MX1ADS, "Motorola MX1ADS")
+	MAINTAINER("Shane Nay")
+#ifdef CONFIG_ARCH_MX1ADS_SRAM
+	BOOT_MEM(0x12000000, 0x00200000, 0xf0200000)
+#else
+	BOOT_MEM(0x08000000, 0x00200000, 0xf0200000)
+#endif
+	FIXUP(mx1ads_fixup)
+	MAPIO(mx1ads_map_io)
+	INITIRQ(mx1ads_init_irq)
+MACHINE_END
+
+#if 0
+
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-mx1ads/cpu.c linux/arch/arm/mach-mx1ads/cpu.c
--- linux.orig/arch/arm/mach-mx1ads/cpu.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-mx1ads/cpu.c	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,34 @@
+/*
+ *  linux/arch/arm/mach-mx1ads/cpu.c
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ *  $Id: cpu.c,v 1.2 2001/09/22 12:11:17 rmk Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * CPU support functions
+ */
+
+/*  FIXME-
+ *  Add support for clock change on the fly.  (Power)
+ *
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/cpufreq.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+
+static int __init cpu_init(void)
+{
+	return 0;
+}
+
+__initcall(cpu_init);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-mx1ads/irq.c linux/arch/arm/mach-mx1ads/irq.c
--- linux.orig/arch/arm/mach-mx1ads/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-mx1ads/irq.c	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,73 @@
+/*
+ *  linux/arch/arm/mach-mx1ads/irq.c
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/irq.h>
+
+/*
+ *
+ * We simply use the ENABLE DISABLE registers inside of the MX1
+ * to turn on/off specific interrupts.  FIXME- We should
+ * also add support for the accelerated interrupt controller
+ * by putting offets to irq jump code in the appropriate
+ * places.
+ *
+ */
+
+#define INTENNUM_OFF              0x8
+#define INTDISNUM_OFF             0xC
+
+#define VA_AITC_BASE              IO_ADDRESS(MX1ADS_AITC_BASE)
+#define MX1ADS_AITC_INTDISNUM     (VA_AITC_BASE + INTDISNUM_OFF)
+#define MX1ADS_AITC_INTENNUM      (VA_AITC_BASE + INTENNUM_OFF)
+
+static void
+mx1ads_mask_irq(unsigned int irq)
+{
+	__raw_writel(irq, MX1ADS_AITC_INTDISNUM);
+}
+
+static void
+mx1ads_unmask_irq(unsigned int irq)
+{
+	__raw_writel(irq, MX1ADS_AITC_INTENNUM);
+}
+
+void __init
+mx1ads_init_irq(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < NR_IRQS; i++) {
+		irq_desc[i].valid = 1;
+		irq_desc[i].probe_ok = 1;
+		irq_desc[i].mask_ack = mx1ads_mask_irq;
+		irq_desc[i].mask = mx1ads_mask_irq;
+		irq_desc[i].unmask = mx1ads_unmask_irq;
+	}
+
+	/* Disable all interrupts initially. */
+	/* In MX1 this is done in the bootloader. */
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-mx1ads/mm.c linux/arch/arm/mach-mx1ads/mm.c
--- linux.orig/arch/arm/mach-mx1ads/mm.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-mx1ads/mm.c	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/mach-mx1ads/mm.c
+ *
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+
+
+
+static struct map_desc mx1ads_io_desc[] __initdata = {
+
+  { IO_ADDRESS(MX1ADS_SRAM_BASE),     MX1ADS_SRAM_BASE,      SZ_128K   , DOMAIN_IO, 0, 1},
+  { IO_ADDRESS(MX1ADS_IO_BASE),       MX1ADS_IO_BASE,        SZ_256K   , DOMAIN_IO, 0, 1},
+  LAST_DESC
+};
+
+void __init mx1ads_map_io(void)
+{
+	iotable_init(mx1ads_io_desc);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-mx1ads/time.c linux/arch/arm/mach-mx1ads/time.c
--- linux.orig/arch/arm/mach-mx1ads/time.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-mx1ads/time.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/mach-mx1ads/time.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+
+extern int (*set_rtc)(void);
+
+/* FIXME-
+ * When we have an external RTC part,
+ * put the mapping in for that part.
+ *
+ * The internal RTC within the MX1 is not sufficient
+ * for tracking time other than time of day, or
+ * date over very short periods of time.
+ *
+ */
+
+static int mx1ads_set_rtc(void)
+{
+	return 0;
+}
+
+static int mx1ads_rtc_init(void)
+{
+	xtime.tv_sec = 0;
+
+	set_rtc = mx1ads_set_rtc;
+
+	return 0;
+}
+
+__initcall(mx1ads_rtc_init);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/Makefile linux/arch/arm/mach-sa1100/Makefile
--- linux.orig/arch/arm/mach-sa1100/Makefile	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/mach-sa1100/Makefile	2002-08-01 06:42:48.000000000 +0000
@@ -9,20 +9,19 @@
 
 O_TARGET		:= sa1100.o
 
-obj-y :=
+# Common support (must be linked before board specific support)
+obj-y := generic.o irq.o dma-sa1100.o
 obj-m :=
 obj-n :=
 obj-  :=
 
-export-objs :=	assabet.o dma-sa1100.o dma-sa1111.o freebird.o generic.o \
-		h3600.o huw_webpanel.o irq.o pcipool.o sa1111-pcibuf.o   \
-		yopy.o
+export-objs :=	assabet.o dma-sa1100.o dma-sa1111.o \
+		flexanet.o freebird.o generic.o h3600.o \
+		huw_webpanel.o irq.o pcipool.o sa1111.o sa1111-pcibuf.o \
+		system3.o yopy.o usb_ctl.o usb_recv.o usb_send.o
 
 # These aren't present yet, and prevents a plain -ac kernel building.
-# hwtimer.o usb_ctl.o usb_recv.o usb_send.o
-
-# Common support (must be linked before board specific support)
-obj-y += generic.o irq.o dma-sa1100.o
+# hwtimer.o
 
 # This needs to be cleaned up.  We probably need to have SA1100
 # and SA1110 config symbols.
@@ -31,6 +30,7 @@
 ifeq ($(CONFIG_CPU_FREQ),y)
 obj-$(CONFIG_SA1100_ASSABET) += cpu-sa1110.o
 obj-$(CONFIG_SA1100_CERF) += cpu-sa1110.o
+obj-$(CONFIG_SA1100_PT_SYSTEM3) += cpu-sa1110.o
 obj-$(CONFIG_SA1100_LART) += cpu-sa1100.o
 endif
 
@@ -42,11 +42,13 @@
 obj-$(CONFIG_SA1100_ADSBITSY) += adsbitsy.o
 obj-$(CONFIG_SA1100_ASSABET) += assabet.o
 obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o
+obj-$(CONFIG_SA1100_BADGE4) +=  badge4.o
 obj-$(CONFIG_SA1100_BRUTUS) += brutus.o
 obj-$(CONFIG_SA1100_CERF) += cerf.o
 obj-$(CONFIG_SA1100_EMPEG) += empeg.o
 obj-$(CONFIG_SA1100_FLEXANET) += flexanet.o
 obj-$(CONFIG_SA1100_FREEBIRD) += freebird.o
+obj-$(CONFIG_SA1100_FRODO) += frodo.o
 obj-$(CONFIG_SA1100_GRAPHICSCLIENT) += graphicsclient.o
 obj-$(CONFIG_SA1100_GRAPHICSMASTER) += graphicsmaster.o
 obj-$(CONFIG_SA1100_H3600) += h3600.o
@@ -59,6 +61,8 @@
 obj-$(CONFIG_SA1100_PANGOLIN) += pangolin.o
 obj-$(CONFIG_SA1100_PFS168) += pfs168.o
 obj-$(CONFIG_SA1100_PLEB) += pleb.o
+obj-$(CONFIG_SA1100_PT_SYSTEM3) += system3.o
+obj-$(CONFIG_SA1100_SHANNON) += shannon.o
 obj-$(CONFIG_SA1100_SHERMAN) += sherman.o
 obj-$(CONFIG_SA1100_SIMPAD) += simpad.o
 obj-$(CONFIG_SA1100_VICTOR) += victor.o
@@ -72,14 +76,27 @@
 leds-$(CONFIG_SA1100_BRUTUS) += leds-brutus.o
 leds-$(CONFIG_SA1100_CERF) += leds-cerf.o
 leds-$(CONFIG_SA1100_FLEXANET) += leds-flexanet.o
+leds-$(CONFIG_SA1100_FRODO) += leds-frodo.o
 leds-$(CONFIG_SA1100_GRAPHICSCLIENT) += leds-graphicsclient.o
 leds-$(CONFIG_SA1100_GRAPHICSMASTER) += leds-graphicsmaster.o
 leds-$(CONFIG_SA1100_LART) += leds-lart.o
 leds-$(CONFIG_SA1100_PFS168) += leds-pfs168.o
 leds-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o  
+leds-$(CONFIG_SA1100_PT_SYSTEM3) += leds-system3.o
 obj-$(CONFIG_LEDS) += $(leds-y)
 
+# SA1110 USB client support
+list-multi += sa1100usb_core.o
+sa1100usb_core-objs := usb_ctl.o usb_ep0.o usb_recv.o usb_send.o
+obj-$(CONFIG_SA1100_USB) += sa1100usb_core.o
+obj-$(CONFIG_SA1100_USB_NETLINK) += usb-eth.o
+obj-$(CONFIG_SA1100_USB_CHAR) += usb-char.o
+
 # Miscelaneous functions
 obj-$(CONFIG_PM) += pm.o sleep.o
 
 include $(TOPDIR)/Rules.make
+
+sa1100usb_core.o: $(sa1100usb_core-objs)
+	$(LD) -r -o $@ $(sa1100usb_core-objs)
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/adsbitsy.c linux/arch/arm/mach-sa1100/adsbitsy.c
--- linux.orig/arch/arm/mach-sa1100/adsbitsy.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/adsbitsy.c	2002-08-01 06:42:28.000000000 +0000
@@ -53,7 +53,7 @@
 	/*
 	 * Probe for SA1111.
 	 */
-	ret = sa1111_probe();
+	ret = sa1111_probe(ADSBITSY_SA1111_BASE);
 	if (ret < 0)
 		return ret;
 
@@ -94,7 +94,7 @@
 	sa1110_mb_enable();
 
 	set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_RISING_EDGE);
-	sa1111_init_irq(SA1100_GPIO_TO_IRQ(0));
+	sa1111_init_irq(IRQ_GPIO0);
 
 	return 0;
 }
@@ -126,8 +126,8 @@
 
 static struct map_desc adsbitsy_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x08000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 1 */
-  { 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA1111 */
+  { 0xe8000000, 0x08000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 1 */
+  { 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA1111 */
   LAST_DESC
 };
 
@@ -135,24 +135,15 @@
 {
 	if (port->mapbase == _Ser1UTCR0) {
 		Ser1SDCR0 |= SDCR0_UART;
-		// Set RTS Output and High (should be done in the set_mctrl fn)
-		GPDR |= GPIO_GPIO15;
-		GPCR |= GPIO_GPIO15;
-		// Set CTS Input
-		GPDR &= ~GPIO_GPIO14;
+#error Fixme	// Set RTS High (should be done in the set_mctrl fn)
+		GPCR = GPIO_GPIO15;
 	} else if (port->mapbase == _Ser2UTCR0) {
 		Ser2UTCR4 = Ser2HSCR0 = 0;
-		// Set RTS Output and High (should be done in the set_mctrl fn)
-		GPDR |= GPIO_GPIO17;
-		GPCR |= GPIO_GPIO17;
-		// Set CTS Input
-		GPDR &= ~GPIO_GPIO16;
+#error Fixme	// Set RTS High (should be done in the set_mctrl fn)
+		GPCR = GPIO_GPIO17;
 	} else if (port->mapbase == _Ser2UTCR0) {
-		// Set RTS Output and High (should be done in the set_mctrl fn)
-		GPDR |= GPIO_GPIO19;
-		GPCR |= GPIO_GPIO19;
-		// Set CTS Input
-		GPDR &= ~GPIO_GPIO18;
+#error Fixme	// Set RTS High (should be done in the set_mctrl fn)
+		GPCR = GPIO_GPIO19;
 	}
 	return 0;
 }
@@ -166,10 +157,12 @@
 	sa1100_map_io();
 	iotable_init(adsbitsy_io_desc);
 
-	sa1110_register_uart_fns(&adsbitsy_port_fns);
+	sa1100_register_uart_fns(&adsbitsy_port_fns);
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1);
 	sa1100_register_uart(2, 2);
+	GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19;
+	GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18);
 }
 
 MACHINE_START(ADSBITSY, "ADS Bitsy")
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/assabet.c linux/arch/arm/mach-sa1100/assabet.c
--- linux.orig/arch/arm/mach-sa1100/assabet.c	2001-10-25 20:53:45.000000000 +0000
+++ linux/arch/arm/mach-sa1100/assabet.c	2002-08-01 06:42:28.000000000 +0000
@@ -31,16 +31,48 @@
 
 #include "generic.h"
 
+#define ASSABET_BCR_DB1110 \
+	(ASSABET_BCR_SPK_OFF    | ASSABET_BCR_QMUTE     | \
+	 ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
+	 ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
+	 ASSABET_BCR_IRDA_MD0)
+
+#define ASSABET_BCR_DB1111 \
+	(ASSABET_BCR_SPK_OFF    | ASSABET_BCR_QMUTE     | \
+	 ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
+	 ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
+	 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
+	 ASSABET_BCR_IRDA_MD0   | ASSABET_BCR_CF_RST)
 
-unsigned long BCR_value = ASSABET_BCR_DB1110;
 unsigned long SCR_value = ASSABET_SCR_INIT;
-EXPORT_SYMBOL(BCR_value);
 EXPORT_SYMBOL(SCR_value);
 
+static unsigned long BCR_value = ASSABET_BCR_DB1110;
+
+void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	BCR_value = (BCR_value & ~mask) | val;
+	ASSABET_BCR = BCR_value;
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ASSABET_BCR_frob);
+
 
 static int __init assabet_init(void)
 {
-	if (machine_is_assabet() && machine_has_neponset()) {
+	if (!machine_is_assabet())
+		return -EINVAL;
+
+	/*
+	 * Set the IRQ edges
+	 */
+	set_GPIO_IRQ_edge(GPIO_GPIO23, GPIO_RISING_EDGE);	/* UCB1300 */
+
+	if (machine_has_neponset()) {
 		/*
 		 * Angel sets this, but other bootloaders may not.
 		 *
@@ -55,6 +87,7 @@
 			"hasn't been configured in the kernel\n" );
 #endif
 	}
+
 	return 0;
 }
 
@@ -87,18 +120,18 @@
  * repeat it here because the kernel may not be loaded as a zImage, and
  * also because it's a hassle to communicate the SCR value to the kernel
  * from the decompressor.
+ *
+ * Note that IRQs are guaranteed to be disabled.
  */
 static void __init get_assabet_scr(void)
 {
-	unsigned long flags, scr, i;
+	unsigned long scr, i;
 
-	local_irq_save(flags);
 	GPDR |= 0x3fc;			/* Configure GPIO 9:2 as outputs */
 	GPSR = 0x3fc;			/* Write 0xFF to GPIO 9:2 */
 	GPDR &= ~(0x3fc);		/* Configure GPIO 9:2 as inputs */
 	for(i = 100; i--; scr = GPLR);	/* Read GPIO 9:2 */
 	GPDR |= 0x3fc;			/*  restore correct pin direction */
-	local_irq_restore(flags);
 	scr &= 0x3fc;			/* save as system configuration byte. */
 	SCR_value = scr;
 }
@@ -174,9 +207,9 @@
 
 static struct map_desc assabet_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf1000000, 0x12000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Board Control Register */
-  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf1000000, 0x12000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Board Control Register */
+  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
   /*  f3000000 - neponset system registers */
   /*  f4000000 - neponset SA1111 registers */
   LAST_DESC
@@ -186,19 +219,18 @@
 {
 	if (port->mapbase == _Ser1UTCR0) {
 		if (state)
-			ASSABET_BCR_clear(ASSABET_BCR_RS232EN);
+			ASSABET_BCR_clear(ASSABET_BCR_RS232EN |
+					  ASSABET_BCR_COM_RTS |
+					  ASSABET_BCR_COM_DTR);
 		else
-			ASSABET_BCR_set(ASSABET_BCR_RS232EN);
+			ASSABET_BCR_set(ASSABET_BCR_RS232EN |
+					ASSABET_BCR_COM_RTS |
+					ASSABET_BCR_COM_DTR);
 	}
 }
 
 /*
- * Note! this can be called from IRQ context.
- * FIXME: You _need_ to handle ASSABET_BCR carefully, which doesn't
- * happen at the moment.  Suggest putting interrupt save/restore
- * in ASSABET_BCR_set/clear.
- *
- * NB: Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
+ * Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
  * and UART3 (radio module).  We only handle them for UART1 here.
  */
 static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
@@ -207,21 +239,21 @@
 		u_int set = 0, clear = 0;
 
 		if (mctrl & TIOCM_RTS)
-			set |= ASSABET_BCR_COM_RTS;
-		else
 			clear |= ASSABET_BCR_COM_RTS;
+		else
+			set |= ASSABET_BCR_COM_RTS;
 
 		if (mctrl & TIOCM_DTR)
-			set |= ASSABET_BCR_COM_DTR;
-		else
 			clear |= ASSABET_BCR_COM_DTR;
+		else
+			set |= ASSABET_BCR_COM_DTR;
 
 		ASSABET_BCR_clear(clear);
 		ASSABET_BCR_set(set);
 	}
 }
 
-static int assabet_get_mctrl(struct uart_port *port)
+static u_int assabet_get_mctrl(struct uart_port *port)
 {
 	u_int ret = 0;
 	u_int bsr = ASSABET_BSR;
@@ -312,11 +344,7 @@
 	PWER = PWER_GPIO0;
 	PGSR = 0;
 	PCFR = 0;
-
-	/*
-	 * Clear all possible wakeup reasons.
-	 */
-	RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
+	PSDR = 0;
 }
 
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/badge4.c linux/arch/arm/mach-sa1100/badge4.c
--- linux.orig/arch/arm/mach-sa1100/badge4.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-sa1100/badge4.c	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,213 @@
+/*
+ * linux/arch/arm/mach-sa1100/badge4.c
+ *
+ * BadgePAD 4 specific initialization
+ *
+ *   Tim Connors <connors@hpl.hp.com>
+ *   Christopher Hoover <ch@hpl.hp.com>
+ *
+ * Copyright (C) 2002 Hewlett-Packard Company
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/tty.h>
+#include <linux/errno.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/arch/irqs.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/sa1111.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include "generic.h"
+#include "sa1111.h"
+
+static int __init badge4_sa1111_init(void)
+{
+	int ret;
+
+	/*
+	 * Ensure that the memory bus request/grant signals are setup,
+	 * and the grant is held in its inactive state
+	 */
+	sa1110_mb_disable();
+
+	/*
+	 * Probe for SA1111.
+	 */
+	ret = sa1111_probe(BADGE4_SA1111_BASE);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * We found it.  Wake the chip up.
+	 */
+	sa1111_wake();
+
+	/*
+	 * The SDRAM configuration of the SA1110 and the SA1111 must
+	 * match.  This is very important to ensure that SA1111 accesses
+	 * don't corrupt the SDRAM.  Note that this ungates the SA1111's
+	 * MBGNT signal, so we must have called sa1110_mb_disable()
+	 * beforehand.
+	 */
+	sa1111_configure_smc(1,
+			     FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
+			     FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
+
+	/*
+	 * We only need to turn on DCLK whenever we want to use the
+	 * DMA.  It can otherwise be held firmly in the off position.
+	 */
+	SKPCR |= SKPCR_DCLKEN;
+
+	/*
+	 * Enable the SA1110 memory bus request and grant signals.
+	 */
+	sa1110_mb_enable();
+
+	set_GPIO_IRQ_edge(BADGE4_GPIO_INT_1111, GPIO_RISING_EDGE);
+	sa1111_init_irq(BADGE4_IRQ_GPIO_SA1111);
+
+	return 0;
+}
+
+static int __init badge4_init(void)
+{
+	int ret;
+
+	if (!machine_is_badge4())
+		return -ENODEV;
+
+	ret = badge4_sa1111_init();
+	if (ret < 0)
+		printk(KERN_ERR __FUNCTION__
+		       ": SA-1111 initialization failed (%d)\n", ret);
+
+	/* N.B, according to rmk this is the singular place that GPDR
+           should be set */
+
+	/* Video expansion */
+	GPCR  = (BADGE4_GPIO_INT_VID | BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 |
+		 BADGE4_GPIO_LGP4 | BADGE4_GPIO_LGP5 | BADGE4_GPIO_LGP6 |
+		 BADGE4_GPIO_LGP7 | BADGE4_GPIO_LGP8 | BADGE4_GPIO_LGP9 |
+		 BADGE4_GPIO_GPA_VID | BADGE4_GPIO_GPB_VID |
+		 BADGE4_GPIO_GPC_VID);
+	GPDR |= (BADGE4_GPIO_INT_VID | BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 |
+		 BADGE4_GPIO_LGP4 | BADGE4_GPIO_LGP5 | BADGE4_GPIO_LGP6 |
+		 BADGE4_GPIO_LGP7 | BADGE4_GPIO_LGP8 | BADGE4_GPIO_LGP9 |
+		 BADGE4_GPIO_GPA_VID | BADGE4_GPIO_GPB_VID |
+		 BADGE4_GPIO_GPC_VID);
+
+	/* SDRAM SPD i2c */
+	GPCR  = (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL);
+	GPDR |= (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL);
+
+	/* uart */
+	GPCR  = (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2);
+	GPDR |= (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2);
+
+	/* drives CPLD muxsel0 input */
+	GPCR  = BADGE4_GPIO_MUXSEL0;
+	GPDR |= BADGE4_GPIO_MUXSEL0;
+
+	/* test points */
+	GPCR  = (BADGE4_GPIO_TESTPT_J7 | BADGE4_GPIO_TESTPT_J6 |
+		 BADGE4_GPIO_TESTPT_J5);
+	GPDR |= (BADGE4_GPIO_TESTPT_J7 | BADGE4_GPIO_TESTPT_J6 |
+		 BADGE4_GPIO_TESTPT_J5);
+
+	/* drives CPLD sdram type inputs; this shouldn't be needed;
+           bootloader left it this way. */
+	GPDR |= (BADGE4_GPIO_SDTYP0 | BADGE4_GPIO_SDTYP1);
+
+  	/* 5V supply rail. */
+  	GPCR  = BADGE4_GPIO_PCMEN5V;		/* initially off */
+   	GPDR |= BADGE4_GPIO_PCMEN5V;
+
+	/* drives SA1111 reset pin; this shouldn't be needed;
+           bootloader left it this way. */
+	GPSR  = BADGE4_GPIO_SA1111_NRST;
+	GPDR |= BADGE4_GPIO_SA1111_NRST;
+
+	return 0;
+}
+
+__initcall(badge4_init);
+
+
+static unsigned badge4_5V_bitmap = 0;
+
+void badge4_set_5V(unsigned subsystem, int on)
+{
+	unsigned long flags;
+	unsigned old_5V_bitmap;
+
+	local_irq_save(flags);
+
+	old_5V_bitmap = badge4_5V_bitmap;
+
+	if (on) {
+		badge4_5V_bitmap |= subsystem;
+	} else {
+		badge4_5V_bitmap &= ~subsystem;
+	}
+
+	/* detect on->off and off->on transitions */
+	if ((!old_5V_bitmap) && (badge4_5V_bitmap)) {
+		/* was off, now on */
+		printk(KERN_INFO __FUNCTION__ ": enabling 5V supply rail\n");
+		GPSR = BADGE4_GPIO_PCMEN5V;
+	} else if ((old_5V_bitmap) && (!badge4_5V_bitmap)) {
+		/* was on, now off */
+		printk(KERN_INFO __FUNCTION__ ": disabling 5V supply rail\n");
+		GPCR = BADGE4_GPIO_PCMEN5V;
+	}
+
+	local_irq_restore(flags);
+}
+EXPORT_SYMBOL(badge4_set_5V);
+
+
+static void __init
+fixup_badge4(struct machine_desc *desc, struct param_struct *params,
+	    char **cmdline, struct meminfo *mi)
+{
+	/* nothing needed here */
+}
+
+static struct map_desc badge4_io_desc[] __initdata = {
+  /*  virtual    physical    length      domain   r w c b		   */
+  {0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0,1,0,0},/* Flash bank 0 */
+  {0xf1000000, 0x08000000, 0x00100000, DOMAIN_IO, 0,1,0,0},/* SRAM  bank 1 */
+  {0xf2000000, 0x10000000, 0x00100000, DOMAIN_IO, 0,1,0,0},/* SRAM  bank 2 */
+  {0xf4000000, 0x48000000, 0x00100000, DOMAIN_IO, 0,1,0,0},/* SA-1111      */
+  LAST_DESC
+};
+
+static void __init badge4_map_io(void)
+{
+	sa1100_map_io();
+	iotable_init(badge4_io_desc);
+
+	sa1100_register_uart(0, 3);
+	sa1100_register_uart(1, 1);
+}
+
+MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	BOOT_PARAMS(0xc0000100)
+	FIXUP(fixup_badge4)
+	MAPIO(badge4_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/cerf.c linux/arch/arm/mach-sa1100/cerf.c
--- linux.orig/arch/arm/mach-sa1100/cerf.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/cerf.c	2002-08-01 06:42:42.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-sa1100/cerf.c
  */
-
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
@@ -16,20 +16,22 @@
 #include "generic.h"
 
 
-static void __init cerf_init_irq (void)
+static void __init cerf_init_irq(void)
 {
-  sa1100_init_irq();
+	sa1100_init_irq();
 
-  /* Need to register these as rising edge interrupts
-   * For standard 16550 serial driver support
-   * Basically - I copied it from pfs168.c :)
-   */
+	/* Need to register these as rising edge interrupts
+	 * For standard 16550 serial driver support
+	 * Basically - I copied it from pfs168.c :)
+	 */
 #ifdef CONFIG_SA1100_CERF_CPLD
-  set_GPIO_IRQ_edge(GPIO_GPIO(3), GPIO_RISING_EDGE); /* PDA Full serial port */
-  set_GPIO_IRQ_edge(GPIO_GPIO(2), GPIO_RISING_EDGE); /* PDA Bluetooth */
-  GPDR &= ~(GPIO_GPIO(3)); /* Set the direction of serial port GPIO pin to in */
-  GPDR &= ~(GPIO_GPIO(2)); /* Set the direction of bluetooth GPIO pin to in */
+	/* PDA Full serial port */
+	set_GPIO_IRQ_edge(GPIO_GPIO3, GPIO_RISING_EDGE);
+	/* PDA Bluetooth */
+	set_GPIO_IRQ_edge(GPIO_GPIO2, GPIO_RISING_EDGE);
 #endif /* CONFIG_SA1100_CERF_CPLD */
+
+	set_GPIO_IRQ_edge(GPIO_UCB1200_IRQ, GPIO_RISING_EDGE);
 }
 
 static void __init
@@ -37,22 +39,20 @@
 	   char **cmdline, struct meminfo *mi)
 {
 #if defined(CONFIG_SA1100_CERF_64MB)
-        // 64MB RAM
-        SET_BANK( 0, 0xc0000000, 64*1024*1024 );
-        mi->nr_banks = 1;
-#elif defined(CONFIG_SA1100_CERF_32MB)	// 32MB RAM
+	SET_BANK( 0, 0xc0000000, 64*1024*1024 );
+	mi->nr_banks = 1;
+#elif defined(CONFIG_SA1100_CERF_32MB)
 	SET_BANK( 0, 0xc0000000, 32*1024*1024 );
 	mi->nr_banks = 1;
-#elif defined(CONFIG_SA1100_CERF_16MB)	// 16Meg Ram.
+#elif defined(CONFIG_SA1100_CERF_16MB)
 	SET_BANK( 0, 0xc0000000, 8*1024*1024 );
 	SET_BANK( 1, 0xc8000000, 8*1024*1024 );
 	mi->nr_banks = 2;
 #elif defined(CONFIG_SA1100_CERF_8MB)
-        // 8Meg Ram.
-        SET_BANK( 0, 0xc0000000, 8*1024*1024 );
-        mi->nr_banks = 1;
+	SET_BANK( 0, 0xc0000000, 8*1024*1024 );
+	mi->nr_banks = 1;
 #else
-       #error "Undefined memory size for Cerfboard."
+#error "Undefined memory size for Cerfboard."
 #endif
 
 //	ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
@@ -62,13 +62,13 @@
 }
 
 static struct map_desc cerf_io_desc[] __initdata = {
-  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Crystal Ethernet Chip */
+  /* virtual	 physical    length	 domain     r  w  c  b */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Crystal Ethernet Chip */
 #ifdef CONFIG_SA1100_CERF_CPLD
-  { 0xf1000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CPLD Chip */
-  { 0xf2000000, 0x10000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CerfPDA Bluetooth */
-  { 0xf3000000, 0x18000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CerfPDA Serial */
+  { 0xf1000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD Chip */
+  { 0xf2000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CerfPDA Bluetooth */
+  { 0xf3000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CerfPDA Serial */
 #endif
   LAST_DESC
 };
@@ -78,13 +78,19 @@
 	sa1100_map_io();
 	iotable_init(cerf_io_desc);
 
-        sa1100_register_uart(0, 3);
+	sa1100_register_uart(0, 3);
 #ifdef CONFIG_SA1100_CERF_IRDA_ENABLED
 	sa1100_register_uart(1, 1);
 #else
 	sa1100_register_uart(1, 2);
 	sa1100_register_uart(2, 1);
 #endif
+
+	/* set some GPDR bits here while it's safe */
+	GPDR |= GPIO_CF_RESET;
+#ifdef CONFIG_SA1100_CERF_CPLD
+	GPDR |= GPIO_PWR_SHUTDOWN;
+#endif
 }
 
 MACHINE_START(CERF, "Intrinsyc's Cerf Family of Products")
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/cpu-sa1100.c linux/arch/arm/mach-sa1100/cpu-sa1100.c
--- linux.orig/arch/arm/mach-sa1100/cpu-sa1100.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/cpu-sa1100.c	2002-08-01 06:42:31.000000000 +0000
@@ -90,7 +90,8 @@
 
 #include <asm/hardware.h>
 
-
+extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz);
+extern unsigned int sa11x0_validatespeed(unsigned int khz);
 
 
 typedef struct {
@@ -219,14 +220,22 @@
 };
 
 
-
+static void sa1100_setspeed(unsigned int khz)
+{
+	PPCR = sa11x0_freq_to_ppcr(khz);
+}
 
 static int __init sa1100_dram_init(void)
 {
-	return cpufreq_register_notifier(&sa1100_dram_block);
-}
+	int ret = -ENODEV;
 
+	if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID) {
+		ret = cpufreq_register_notifier(&sa1100_dram_block);
 
+		cpufreq_setfunctions(sa11x0_validatespeed, sa1100_setspeed);
+	}
 
+	return ret;
+}
 
 __initcall(sa1100_dram_init);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/cpu-sa1110.c linux/arch/arm/mach-sa1100/cpu-sa1110.c
--- linux.orig/arch/arm/mach-sa1100/cpu-sa1110.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/cpu-sa1110.c	2002-08-01 06:42:29.000000000 +0000
@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 2001 Russell King
  *
- *  $Id: cpu-sa1110.c,v 1.5 2001/09/10 13:25:58 rmk Exp $
+ *  $Id: cpu-sa1110.c,v 1.6 2001/10/22 11:53:47 rmk Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -29,14 +29,8 @@
 
 #undef DEBUG
 
-extern u_int processor_id;
-
-#define CPU_REVISION	(processor_id & 15)
-#define CPU_SA1110_A0	(0)
-#define CPU_SA1110_B0	(4)
-#define CPU_SA1110_B1	(5)
-#define CPU_SA1110_B2	(6)
-#define CPU_SA1110_B4	(8)
+extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz);
+extern unsigned int sa11x0_validatespeed(unsigned int khz);
 
 struct sdram_params {
 	u_char  rows;		/* bits				 */
@@ -48,6 +42,12 @@
 	u_short refresh;	/* refresh time for array (us)	 */
 };
 
+struct sdram_info {
+	u_int	mdcnfg;
+	u_int	mdrefr;
+	u_int	mdcas[3];
+};
+
 static struct sdram_params tc59sm716_cl2_params __initdata = {
 	rows:		    12,
 	tck:		    10,
@@ -68,6 +68,16 @@
 	cas_latency:	     3,
 };
 
+static struct sdram_params samsung_k4s641632d_tc75 __initdata = {
+	rows:		    14,
+	tck:		     9,
+	trcd:		    27,
+	trp:		    20,
+	twr:		     9,
+	refresh:	 64000,
+	cas_latency:	     3,
+};
+
 static struct sdram_params sdram_params;
 
 /*
@@ -95,10 +105,11 @@
 	mdcas[1]  = mdcas[2] = 0x55555555 << (shift & 1);
 }
 
-static void sdram_update_timing(u_int cpu_khz, struct sdram_params *sdram)
+static void
+sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
+		       struct sdram_params *sdram)
 {
-	u_int mdcnfg, mdrefr, mdcas[3], mem_khz, sd_khz, trp, twr;
-	unsigned long flags;
+	u_int mem_khz, sd_khz, trp, twr;
 
 	mem_khz = cpu_khz / 2;
 	sd_khz = mem_khz;
@@ -114,7 +125,7 @@
 	    (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
 		sd_khz /= 2;
 
-	mdcnfg = MDCNFG & 0x007f007f;
+	sd->mdcnfg = MDCNFG & 0x007f007f;
 
 	twr = ns_to_cycles(sdram->twr, mem_khz);
 
@@ -123,53 +134,26 @@
 	if (trp < 1)
 		trp = 1;
 
-	mdcnfg |= trp << 8;
-	mdcnfg |= trp << 24;
-	mdcnfg |= sdram->cas_latency << 12;
-	mdcnfg |= sdram->cas_latency << 28;
-	mdcnfg |= twr << 14;
-	mdcnfg |= twr << 30;
+	sd->mdcnfg |= trp << 8;
+	sd->mdcnfg |= trp << 24;
+	sd->mdcnfg |= sdram->cas_latency << 12;
+	sd->mdcnfg |= sdram->cas_latency << 28;
+	sd->mdcnfg |= twr << 14;
+	sd->mdcnfg |= twr << 30;
 
-	mdrefr = MDREFR & 0xffbffff0;
-	mdrefr |= 7;
+	sd->mdrefr = MDREFR & 0xffbffff0;
+	sd->mdrefr |= 7;
 
 	if (sd_khz != mem_khz)
-		mdrefr |= MDREFR_K1DB2;
+		sd->mdrefr |= MDREFR_K1DB2;
 
 	/* initial number of '1's in MDCAS + 1 */
-	set_mdcas(mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
+	set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
 
 #ifdef DEBUG
-	mdelay(250);
 	printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
-		mdcnfg, mdrefr, mdcas[0], mdcas[1], mdcas[2]);
+		sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
 #endif
-
-	/*
-	 * Reprogram the DRAM timings with interrupts disabled, and
-	 * ensure that we are doing this within a complete cache line.
-	 * This means that we won't access SDRAM for the duration of
-	 * the programming.
-	 */
-	local_irq_save(flags);
-	asm("mcr p15, 0, %0, c10, c4" : : "r" (0));
-	udelay(10);
-	__asm__("
-		b	1f
-		.align	5
-1:		str	%3, [%1, #28]		@ MDREFR
-		str	%4, [%1, #4]		@ MDCAS0
-		str	%5, [%1, #8]		@ MDCAS1
-		str	%6, [%1, #12]		@ MDCAS2
-		str	%2, [%1, #0]		@ MDCNFG
-		ldr	%0, [%1, #0]
-		nop
-		nop"
-		: "=&r" (mdcnfg)
-		: "r" (io_p2v(_MDCNFG)),
-		  "0" (mdcnfg), "r" (mdrefr),
-		  "r" (mdcas[0]), "r" (mdcas[1]), "r" (mdcas[2]));
-	local_irq_restore(flags);
 }
 
 /*
@@ -203,65 +187,92 @@
 	sdram_set_refresh(dri);
 }
 
-static int
-sdram_notifier(struct notifier_block *nb, unsigned long val, void *data)
+/*
+ * Ok, set the CPU frequency.  Since we've done the validation
+ * above, we can match for an exact frequency.  If we don't find
+ * an exact match, we will to set the lowest frequency to be safe.
+ */
+static void sa1110_setspeed(unsigned int khz)
 {
-	struct cpufreq_info *ci = data;
 	struct sdram_params *sdram = &sdram_params;
+	struct sdram_info sd;
+	unsigned long flags;
+	unsigned int ppcr, unused;
 
-	/* were we initialised? */
-	if (sdram->cas_latency == 0) {
-		struct cpufreq_minmax *m = data;
-		m->min_freq = m->max_freq = m->cur_freq;
-		return 0;
-	}
+	ppcr = sa11x0_freq_to_ppcr(khz);
+	sdram_calculate_timing(&sd, khz, sdram);
 
-	switch (val) {
-	case CPUFREQ_MINMAX:
-		/*
-		 * until we work out why the assabet
-		 * crashes below 147.5MHz...
-		 */
-		cpufreq_updateminmax(data, 147500, -1);
-		break;
-
-	case CPUFREQ_PRECHANGE:
-		/*
-		 * The clock could be going away for some time.
-		 * Set the SDRAMs to refresh rapidly (every 64
-		 * memory clock cycles).  To get through the
-		 * whole array, we need to wait 262144 mclk cycles.
-		 * We wait 20ms to be safe.
-		 */
-		sdram_set_refresh(2);
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(20 * HZ / 1000);
-
-		if (ci->old_freq < ci->new_freq)
-			sdram_update_timing(ci->new_freq, sdram);
-		break;
-
-	case CPUFREQ_POSTCHANGE:
-		if (ci->old_freq > ci->new_freq)
-			sdram_update_timing(ci->new_freq, sdram);
-		sdram_update_refresh(ci->new_freq, sdram);
-		break;
+#if 0
+	/*
+	 * These values are wrong according to the SA1110 documentation
+	 * and errata, but they seem to work.  Need to get a storage
+	 * scope on to the SDRAM signals to work out why.
+	 */
+	if (khz < 147500) {
+		sd.mdrefr |= MDREFR_K1DB2;
+		sd.mdcas[0] = 0xaaaaaa7f;
+	} else {
+		sd.mdrefr &= ~MDREFR_K1DB2;
+		sd.mdcas[0] = 0xaaaaaa9f;
 	}
-	return 0;
-}
+	sd.mdcas[1] = 0xaaaaaaaa;
+	sd.mdcas[2] = 0xaaaaaaaa;
+#endif
+	/*
+	 * The clock could be going away for some time.  Set the SDRAMs
+	 * to refresh rapidly (every 64 memory clock cycles).  To get
+	 * through the whole array, we need to wait 262144 mclk cycles.
+	 * We wait 20ms to be safe.
+	 */
+	sdram_set_refresh(2);
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(20 * HZ / 1000);
 
-static struct notifier_block sa1110_clkchg_block = {
-	notifier_call:	sdram_notifier,
-};
+	/*
+	 * Reprogram the DRAM timings with interrupts disabled, and
+	 * ensure that we are doing this within a complete cache line.
+	 * This means that we won't access SDRAM for the duration of
+	 * the programming.
+	 */
+	local_irq_save(flags);
+	asm("mcr p15, 0, %0, c10, c4" : : "r" (0));
+	udelay(10);
+	__asm__ __volatile__("
+		b	2f
+		.align	5
+1:		str	%3, [%1, #0]		@ MDCNFG
+		str	%4, [%1, #28]		@ MDREFR
+		str	%5, [%1, #4]		@ MDCAS0
+		str	%6, [%1, #8]		@ MDCAS1
+		str	%7, [%1, #12]		@ MDCAS2
+		str	%8, [%2, #0]		@ PPCR
+		ldr	%0, [%1, #0]
+		b	3f
+2:		b	1b
+3:		nop
+		nop"
+		: "=&r" (unused)
+		: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
+		  "r" (sd.mdrefr), "r" (sd.mdcas[0]),
+		  "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
+	local_irq_restore(flags);
 
-static int __init sa1110_sdram_init(void)
+	/*
+	 * Now, return the SDRAM refresh back to normal.
+	 */
+	sdram_update_refresh(khz, sdram);
+}
+
+static int __init sa1110_clk_init(void)
 {
 	struct sdram_params *sdram = NULL;
-	unsigned int cur_freq = cpufreq_get(smp_processor_id());
 
 	if (machine_is_assabet())
 		sdram = &tc59sm716_cl3_params;
 
+	if (machine_is_pt_system3())
+		sdram = &samsung_k4s641632d_tc75;
+
 	if (sdram) {
 		printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
 			" twr: %d refresh: %d cas_latency: %d\n",
@@ -270,11 +281,11 @@
 
 		memcpy(&sdram_params, sdram, sizeof(sdram_params));
 
-		sdram_update_timing(cur_freq, &sdram_params);
-		sdram_update_refresh(cur_freq, &sdram_params);
+		sa1110_setspeed(cpufreq_get(0));
+		cpufreq_setfunctions(sa11x0_validatespeed, sa1110_setspeed);
 	}
 
-	return cpufreq_register_notifier(&sa1110_clkchg_block);
+	return 0;
 }
 
-__initcall(sa1110_sdram_init);
+__initcall(sa1110_clk_init);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/dma-sa1100.c linux/arch/arm/mach-sa1100/dma-sa1100.c
--- linux.orig/arch/arm/mach-sa1100/dma-sa1100.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/dma-sa1100.c	2002-08-01 06:42:33.000000000 +0000
@@ -147,6 +147,19 @@
 		}
 
 		/*
+		 * This improves latency if there are some active spinning
+		 * buffers.  We kill them altogether.
+		 */
+		if (dma->spin_ref > 0) {
+			if (channel_is_sa1111_sac(dma - dma_chan))
+				sa1111_reset_sac_dma(dma - dma_chan);
+			else
+				dma->regs->ClrDCSR =
+				    DCSR_STRTA|DCSR_STRTB|DCSR_DONEA|DCSR_DONEB;
+			dma->spin_ref = 0;
+		}
+
+		/*
 		 * Let's try to start DMA on the current buffer.
 		 * If DMA is busy then we break here.
 		 */
@@ -188,8 +201,7 @@
 			 */
 			DPRINTK("IRQ: buf done\n");
 			dma->curr = buf->next;
-			if (dma->curr == NULL)
-				dma->spin_ref = -dma->spin_ref;
+			dma->spin_ref = -dma->spin_ref;
 			if (dma->head == buf)
 				dma->head = NULL;
 			if (dma->callback) {
@@ -468,7 +480,6 @@
 		int flags;
 		save_flags_cli(flags);
 		dma->stopped = 0;
-		dma->spin_ref = 0;
 		process_dma(dma);
 		restore_flags(flags);
 	}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/dma-sa1111.c linux/arch/arm/mach-sa1100/dma-sa1111.c
--- linux.orig/arch/arm/mach-sa1100/dma-sa1111.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/dma-sa1111.c	2002-08-01 06:42:33.000000000 +0000
@@ -22,6 +22,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/dma.h>
+#include <asm/hardware/sa1111.h>
 
 // #define DEBUG
 #ifdef DEBUG
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/empeg.c linux/arch/arm/mach-sa1100/empeg.c
--- linux.orig/arch/arm/mach-sa1100/empeg.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/empeg.c	2002-08-01 06:42:33.000000000 +0000
@@ -31,7 +31,7 @@
 
 static struct map_desc empeg_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { EMPEG_FLASHBASE, 0x00000000, 0x00200000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash */
+  { EMPEG_FLASHBASE, 0x00000000, 0x00200000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/flexanet.c linux/arch/arm/mach-sa1100/flexanet.c
--- linux.orig/arch/arm/mach-sa1100/flexanet.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/flexanet.c	2002-08-01 06:42:41.000000000 +0000
@@ -9,8 +9,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
-#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -27,22 +25,140 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
+#include <linux/serial_core.h>
 
 #include "generic.h"
 
 
-unsigned long BCR_value         = BCR_POWERUP;
-unsigned long flexanet_GUI_type = 0x0000000F;
+unsigned long flexanet_BCR = FHH_BCR_POWERUP;
+
+EXPORT_SYMBOL(flexanet_BCR);
+
+/* physical addresses */
+#define _RCNR        0x90010004
+#define _GPLR        0x90040000
+#define _Ser4SSCR0   0x80070060
+
+/*
+ * Get the modem-control register of the UARTs
+ *
+ */
+static int flexanet_get_mctrl(struct uart_port *port)
+{
+	int            stat = 0;
+	unsigned long  bsr;
+
+	/* only DSR and CTS are implemented in UART1 & 3 */
+	if (port->membase == (void *)&Ser1UTCR0)
+	{
+		bsr = FHH_BSR;
+
+		if ((bsr & FHH_BSR_DSR1) != 0)
+			stat |= TIOCM_DSR;
+		if ((bsr & FHH_BSR_CTS1) != 0)
+			stat |= TIOCM_CTS;
+	}
+	else if (port->membase == (void *)&Ser3UTCR0)
+	{
+		bsr = FHH_BSR;
+
+		if ((bsr & FHH_BSR_DSR3) != 0)
+			stat |= TIOCM_DSR;
+		if ((bsr & FHH_BSR_CTS3) != 0)
+			stat |= TIOCM_CTS;
+	}
 
-EXPORT_SYMBOL(BCR_value);
-EXPORT_SYMBOL(flexanet_GUI_type);
+	return stat;
+}
+
+/*
+ * Set the modem-control register of the UARTs
+ *
+ */
+static void flexanet_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+	unsigned long	flags;
+
+	/* only the RTS signal is implemented in UART1 & 3 */
+	if (port->membase == (void *)&Ser1UTCR0)
+	{
+		local_irq_save(flags);
+
+		if (mctrl & TIOCM_RTS)
+			flexanet_BCR |= FHH_BCR_RTS1;
+		else
+			flexanet_BCR &= ~FHH_BCR_RTS1;
+
+		FHH_BCR = flexanet_BCR;
+		local_irq_restore(flags);
+	}
+	else if (port->membase == (void *)&Ser3UTCR0)
+	{
+		local_irq_save(flags);
+
+		if (mctrl & TIOCM_RTS)
+			flexanet_BCR |= FHH_BCR_RTS3;
+		else
+			flexanet_BCR &= ~FHH_BCR_RTS3;
+
+		FHH_BCR = flexanet_BCR;
+		local_irq_restore(flags);
+	}
+}
+
+/*
+ * machine-specific serial port functions
+ *
+ * get_mctrl : set state of modem control lines
+ * set_mctrl : set the modem control lines
+ * pm        : power-management. Turn device on/off.
+ *
+ */
+static struct sa1100_port_fns	flexanet_port_fns __initdata =
+{
+	set_mctrl : flexanet_set_mctrl,
+	get_mctrl : flexanet_get_mctrl,
+	pm        : NULL,
+};
+
+
+/*
+ * Initialization and serial port mapping
+ *
+ */
+
+static int flexanet_serial_init(void)
+{
+	/* register low-level functions */
+	sa1100_register_uart_fns(&flexanet_port_fns);
+
+	/* UART port number mapping */
+	sa1100_register_uart(0, 1); /* RS232 */
+	sa1100_register_uart(1, 3); /* Radio */
+
+	/* Select UART function in Serial port 1 */
+	Ser1SDCR0 |= SDCR0_UART;
+
+	return 0;
+}
+
+
+static int __init flexanet_init(void)
+{
+	return 0;
+}
+
+__initcall(flexanet_init);
 
-static unsigned long probe_gui_board (void);
 
 static void __init
 fixup_flexanet(struct machine_desc *desc, struct param_struct *params,
 	      char **cmdline, struct meminfo *mi)
 {
+	int				status;
+	unsigned long	now;
+
+
 	/* fixed RAM size, by now (64MB) */
 	SET_BANK( 0, 0xc0000000, 64*1024*1024 );
 	mi->nr_banks = 1;
@@ -56,8 +172,11 @@
 
 static struct map_desc flexanet_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* Board Control Register */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Board Control Register */
+  { 0xf1000000, 0x18000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Ethernet controller */
+  { 0xD0000000, 0x40000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Instrument boards */
+  { 0xD8000000, 0x48000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* External peripherals */
   LAST_DESC
 };
 
@@ -65,9 +184,27 @@
 {
 	sa1100_map_io();
 	iotable_init(flexanet_io_desc);
+	flexanet_serial_init();
 
-	sa1100_register_uart(0, 1);
-	Ser1SDCR0 |= SDCR0_UART;
+	/* wakeup source is GPIO-0 only */
+	PWER = PWER_GPIO0;
+
+	/* GPIOs set to zero during sleep */
+	PGSR = 0;
+
+	/*
+	 * stop the 3.68 MHz oscillator and float control busses
+	 * during sleep, since peripherals are powered off.
+	 */
+	PCFR = PCFR_OPDE | PCFR_FP | PCFR_FS;
+
+	/* deassert the GUI reset */
+	FLEXANET_BCR_set(FHH_BCR_GUI_NRST);
+
+	/*
+	 * Set IRQ edges
+	 */
+	set_GPIO_IRQ_edge(GPIO_GUI_IRQ, GPIO_RISING_EDGE);
 }
 
 
@@ -78,3 +215,4 @@
 	MAPIO(flexanet_map_io)
 	INITIRQ(sa1100_init_irq)
 MACHINE_END
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/freebird.c linux/arch/arm/mach-sa1100/freebird.c
--- linux.orig/arch/arm/mach-sa1100/freebird.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/freebird.c	2002-08-01 06:42:34.000000000 +0000
@@ -37,9 +37,9 @@
 
 static struct map_desc freebird_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x12000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Board Control Register */
-  { 0xf2000000, 0x19000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0},
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x12000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Board Control Register */
+  { 0xf2000000, 0x19000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0},
    LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/frodo.c linux/arch/arm/mach-sa1100/frodo.c
--- linux.orig/arch/arm/mach-sa1100/frodo.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-sa1100/frodo.c	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,61 @@
+
+/*
+ * linux/arch/arm/mach-sa1100/frodo.c
+ *
+ * Author: Abraham van der Merwe <abraham@2d3d.co.za>
+ *
+ * This file contains the 2d3D, Inc. SA-1110 Development Board tweaks.
+ *
+ * This source code is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * History:
+ *
+ *   2002/01/31   Initial version
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/tty.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include "generic.h"
+
+static struct map_desc frodo_io_desc[] __initdata =
+{
+  /* virtual     physical    length      domain     r  w  c  b */
+   { 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 1, 1, 0, 0 },	/* flash memory */
+   { 0xf0000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 },	/* 16-bit on-board devices (including CPLDs) */
+   { 0xf1000000, 0x18000000, 0x04000000, DOMAIN_IO, 1, 1, 0, 0 },	/* 32-bit daughter card */
+   LAST_DESC
+};
+
+static void __init frodo_map_io (void)
+{
+   sa1100_map_io ();
+   iotable_init (frodo_io_desc);
+
+   sa1100_register_uart (0,2);	/* UART2 (serial console) */
+   sa1100_register_uart (1,1);	/* UART1 (big kahuna flow control serial port) */
+
+   /*
+	* Set SUS bit in SDCR0 so serial port 1 acts as a UART.
+	* See Intel SA-1110 Developers Manual Section 11.9.2.1 (GPCLK/UART Select)
+	*/
+   Ser1SDCR0 |= SDCR0_SUS;
+}
+
+MACHINE_START (FRODO,"2d3D, Inc. SA-1110 Development Board")
+	BOOT_MEM (0xc0000000,0x80000000,0xf8000000)
+	BOOT_PARAMS (0xc0000100)
+	MAPIO (frodo_map_io)
+	INITIRQ (sa1100_init_irq)
+MACHINE_END
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/generic.c linux/arch/arm/mach-sa1100/generic.c
--- linux.orig/arch/arm/mach-sa1100/generic.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/generic.c	2002-08-01 06:42:37.000000000 +0000
@@ -56,20 +56,13 @@
 /*
  * Return the current CPU clock frequency in units of 100kHz
  */
-unsigned short get_cclk_frequency(void)
+static inline unsigned short get_cclk_frequency(void)
 {
 	return cclk_frequency_100khz[PPCR & 0xf];
 }
 
-EXPORT_SYMBOL(get_cclk_frequency);
-
 #ifdef CONFIG_CPU_FREQ
-
-/*
- * Validate the speed in khz.  If we can't generate the precise
- * frequency requested, round it down (to be on the safe side).
- */
-unsigned int sa1100_validatespeed(unsigned int khz)
+unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
 {
 	int i;
 
@@ -79,35 +72,34 @@
 		if (cclk_frequency_100khz[i] <= khz)
 			break;
 
-	return cclk_frequency_100khz[i] * 100;
+	return i;
 }
 
 /*
- * Ok, set the CPU frequency.  Since we've done the validation
- * above, we can match for an exact frequency.  If we don't find
- * an exact match, we will to set the lowest frequency to be safe.
+ * Validate the speed in khz.  If we can't generate the precise
+ * frequency requested, round it down (to be on the safe side).
  */
-void sa1100_setspeed(unsigned int khz)
+unsigned int sa11x0_validatespeed(unsigned int khz)
 {
-	int i;
-
-	khz /= 100;
-
-	for (i = NR_FREQS - 1; i > 0; i--)
-		if (cclk_frequency_100khz[i] == khz)
-			break;
-//printk("setting ppcr to %d\n", i);
-	PPCR = i;
+	return cclk_frequency_100khz[sa11x0_freq_to_ppcr(khz)] * 100;
 }
 
-static int __init sa1100_init_clock(void)
+static int __init sa11x0_init_clock(void)
 {
-	cpufreq_init(get_cclk_frequency() * 100);
-	cpufreq_setfunctions(sa1100_validatespeed, sa1100_setspeed);
+	cpufreq_init(cclk_frequency_100khz[PPCR & 0xf] * 100);
 	return 0;
 }
 
-__initcall(sa1100_init_clock);
+__initcall(sa11x0_init_clock);
+#else
+/*
+ * We still need to provide this so building without cpufreq works.
+ */ 
+unsigned int cpufreq_get(int cpu)
+{
+	return cclk_frequency_100khz[PPCR & 0xf] * 100;
+}
+EXPORT_SYMBOL(cpufreq_get);
 #endif
 
 /*
@@ -130,13 +122,13 @@
 	PMCR = PMCR_SF;
 }
 
-static int __init sa1100_set_poweroff(void)
+static int __init sa1100_init(void)
 {
 	pm_power_off = sa1100_power_off;
 	return 0;
 }
 
-__initcall(sa1100_set_poweroff);
+__initcall(sa1100_init);
 
 
 /*
@@ -149,7 +141,8 @@
  * 0xf0000000-0xf3ffffff:	miscellaneous stuff (CPLDs, etc.)
  * 0xf4000000-0xf4ffffff:	SA-1111
  * 0xf5000000-0xf5ffffff:	reserved (used by cache flushing area)
- * 0xf6000000-0xffffffff:	reserved (internal SA1100 IO defined above)
+ * 0xf6000000-0xfffeffff:	reserved (internal SA1100 IO defined above)
+ * 0xffff0000-0xffff0fff:	SA1100 exception vectors
  *
  * Below 0xe8000000 is reserved for vm allocation.
  *
@@ -159,8 +152,8 @@
 
 static struct map_desc standard_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xf6000000, 0x20000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* PCMCIA0 IO */
-  { 0xf7000000, 0x30000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* PCMCIA1 IO */
+  { 0xf6000000, 0x20000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA0 IO */
+  { 0xf7000000, 0x30000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA1 IO */
   { 0xf8000000, 0x80000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCM */
   { 0xfa000000, 0x90000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SCM */
   { 0xfc000000, 0xa0000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* MER */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/graphicsclient.c linux/arch/arm/mach-sa1100/graphicsclient.c
--- linux.orig/arch/arm/mach-sa1100/graphicsclient.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/graphicsclient.c	2002-08-01 06:42:48.000000000 +0000
@@ -113,7 +113,6 @@
 		irq_desc[irq].mask	= ADS_mask_irq1;
 		irq_desc[irq].unmask	= ADS_unmask_irq1;
 	}
-	GPDR &= ~GPIO_GPIO0;
 	set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE);
 	setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq );
 }
@@ -138,7 +137,7 @@
 
 static struct map_desc graphicsclient_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x08000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 1 */
+  { 0xe8000000, 0x08000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 1 */
   { 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
   { 0xf1000000, 0x18000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CAN */
   LAST_DESC
@@ -193,12 +192,8 @@
 	if (port->mapbase == _Ser1UTCR0) {
 		Ser1SDCR0 |= SDCR0_UART;
 		/* Set RTS Output */
-		GPDR |= GPIO_GC_UART0_RTS;
 		GPSR  = GPIO_GC_UART0_RTS;
 
-		/* Set CTS Input */
-		GPDR &= ~GPIO_GC_UART0_CTS;
-
 		gc_uart_ctrl_data[0].cts_prev_state = 0;
 		gc_uart_ctrl_data[0].info = info;
 		gc_uart_ctrl_data[0].port = port;
@@ -210,12 +205,8 @@
 	} else if (port->mapbase == _Ser2UTCR0) {
 		Ser2UTCR4 = Ser2HSCR0 = 0;
 		/* Set RTS Output */
-		GPDR |= GPIO_GC_UART1_RTS;
 		GPSR  = GPIO_GC_UART1_RTS;
 
-		/* Set CTS Input */
-		GPDR &= ~GPIO_GC_UART1_RTS;
-
 		gc_uart_ctrl_data[1].cts_prev_state = 0;
 		gc_uart_ctrl_data[1].info = info;
 		gc_uart_ctrl_data[1].port = port;
@@ -226,12 +217,8 @@
 							&gc_uart_ctrl_data[1]);
 	} else if (port->mapbase == _Ser3UTCR0) {
 		/* Set RTS Output */
-		GPDR |= GPIO_GC_UART2_RTS;
 		GPSR =	GPIO_GC_UART2_RTS;
 
-		/* Set CTS Input */
-		GPDR &= ~GPIO_GC_UART2_RTS;
-
 		gc_uart_ctrl_data[2].cts_prev_state = 0;
 		gc_uart_ctrl_data[2].info = info;
 		gc_uart_ctrl_data[2].port = port;
@@ -258,9 +245,9 @@
 	return 0;
 }
 
-static int graphicsclient_get_mctrl(struct uart_port *port)
+static u_int graphicsclient_get_mctrl(struct uart_port *port)
 {
-	int result = TIOCM_CD | TIOCM_DSR;
+	u_int result = TIOCM_CD | TIOCM_DSR;
 
 	if (port->mapbase == _Ser1UTCR0) {
 		if (!(GPLR & GPIO_GC_UART0_CTS))
@@ -326,6 +313,8 @@
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1);
 	sa1100_register_uart(2, 2);
+	GPDR |= GPIO_GC_UART0_RTS | GPIO_GC_UART1_RTS | GPIO_GC_UART2_RTS;
+	GPDR &= ~(GPIO_GC_UART0_CTS | GPIO_GC_UART1_RTS | GPIO_GC_UART2_RTS);
 }
 
 MACHINE_START(GRAPHICSCLIENT, "ADS GraphicsClient")
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/graphicsmaster.c linux/arch/arm/mach-sa1100/graphicsmaster.c
--- linux.orig/arch/arm/mach-sa1100/graphicsmaster.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/graphicsmaster.c	2002-08-01 06:42:41.000000000 +0000
@@ -43,7 +43,7 @@
 	/*
 	 * Probe for SA1111.
 	 */
-	ret = sa1111_probe();
+	ret = sa1111_probe(ADS_SA1111_BASE);
 	if (ret < 0)
 		return ret;
 
@@ -174,7 +174,6 @@
 		irq_desc[irq].mask	= ADS_mask_irq1;
 		irq_desc[irq].unmask	= ADS_unmask_irq1;
 	}
-	GPDR &= ~GPIO_GPIO0;
 	set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE);
 	setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq );
 }
@@ -200,10 +199,10 @@
 
 static struct map_desc graphicsmaster_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x08000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 1 */
-  { 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* CPLD */
-  { 0xf1000000, 0x40000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* CAN */
-  { 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */
+  { 0xe8000000, 0x08000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 1 */
+  { 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
+  { 0xf1000000, 0x40000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CAN */
+  { 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
   LAST_DESC
 };
 
@@ -215,31 +214,22 @@
 		Ser1SDCR0 |= SDCR0_UART;
 		/* Set RTS Output */
 		GPSR = GPIO_GPIO15;
-		GPDR |= GPIO_GPIO15;
-		/* Set CTS Input */
-		GPDR &= ~GPIO_GPIO14;
 	}
 	else if (port->mapbase == _Ser2UTCR0) {
 		Ser2UTCR4 = Ser2HSCR0 = 0;
 		/* Set RTS Output */
 		GPSR = GPIO_GPIO17;
-		GPDR |= GPIO_GPIO17;
-		/* Set CTS Input */
-		GPDR &= ~GPIO_GPIO16;
 	}
 	else if (port->mapbase == _Ser3UTCR0) {
 	        /* Set RTS Output */
 		GPSR = GPIO_GPIO19;
-		GPDR |= GPIO_GPIO19;
-		/* Set CTS Input */
-		GPDR &= ~GPIO_GPIO18;
 	}
 	return ret;
 }
 
-static int graphicsmaster_get_mctrl(struct uart_port *port)
+static u_int graphicsmaster_get_mctrl(struct uart_port *port)
 {
-	int result = TIOCM_CD | TIOCM_DSR;
+	u_int result = TIOCM_CD | TIOCM_DSR;
 
 	if (port->mapbase == _Ser1UTCR0) {
 		if (!(GPLR & GPIO_GPIO14))
@@ -304,6 +294,10 @@
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1);
 	sa1100_register_uart(2, 2);
+
+	/* set GPDR now */
+	GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19;
+       	GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18);
 }
 
 MACHINE_START(GRAPHICSMASTER, "ADS GraphicsMaster")
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/h3600.c linux/arch/arm/mach-sa1100/h3600.c
--- linux.orig/arch/arm/mach-sa1100/h3600.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/h3600.c	2002-08-01 06:42:35.000000000 +0000
@@ -1,8 +1,24 @@
 /*
- * linux/arch/arm/mach-sa1100/h3600.c
+ * Hardware definitions for Compaq iPAQ H3xxx Handheld Computers
+ *
+ * Copyright 2000,1 Compaq Computer Corporation.
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks.
+ *
+ * History:
+ *
+ * 2001-10-??	Andrew Christian   Added support for iPAQ H3800
+ *				   and abstracted EGPIO interface.
+ *
  */
-
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -17,84 +33,338 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 #include <linux/serial_core.h>
+#include <asm/arch/h3600_gpio.h>
 
 #include "generic.h"
 
-
 /*
- * Bitsy has extended, write-only memory-mapped GPIO's
+ * H3600 has extended, write-only memory-mapped GPIO's
+ * H3100 has 1/2 extended, write-only GPIO and 1/2 on
+ *	 regular GPIO lines.
+ * H3800 has memory-mapped GPIO through ASIC1 & 2
  */
 
-static int h3600_egpio = EGPIO_H3600_RS232_ON;
+#define H3600_EGPIO	(*(volatile unsigned int *)H3600_EGPIO_VIRT)
+
+static unsigned int h3600_egpio;
+
+/************************* H3100 *************************/
+
+#define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON	  \
+			  | GPIO_H3100_GPIO3	  \
+			  | GPIO_H3100_QMUTE	  \
+			  | GPIO_H3100_LCD_3V_ON  \
+			  | GPIO_H3100_AUD_ON	  \
+			  | GPIO_H3100_AUD_PWR_ON \
+			  | GPIO_H3100_IR_ON	  \
+			  | GPIO_H3100_IR_FSEL)
+
+static void h3100_init_egpio( void )
+{
+	GPDR |= H3100_DIRECT_EGPIO;
+	GPCR = H3100_DIRECT_EGPIO;   /* Initially all off */
+
+	/* Older bootldrs put GPIO2-9 in alternate mode on the
+	   assumption that they are used for video */
+	GAFR &= ~H3100_DIRECT_EGPIO;
+
+	h3600_egpio = EGPIO_H3600_RS232_ON;
+	H3600_EGPIO = h3600_egpio;
+}
+
+static void h3100_control_egpio( enum ipaq_egpio_type x, int setp )
+{
+	unsigned int egpio = 0;
+	long	     gpio = 0;
+	unsigned long flags;
+
+	switch (x) {
+	case IPAQ_EGPIO_LCD_ON:
+		egpio |= EGPIO_H3600_LCD_ON;
+		gpio  |= GPIO_H3100_LCD_3V_ON;
+		break;
+	case IPAQ_EGPIO_CODEC_NRESET:
+		egpio |= EGPIO_H3600_CODEC_NRESET;
+		break;
+	case IPAQ_EGPIO_AUDIO_ON:
+		gpio |= GPIO_H3100_AUD_PWR_ON
+			| GPIO_H3100_AUD_ON;
+		break;
+	case IPAQ_EGPIO_QMUTE:
+		gpio |= GPIO_H3100_QMUTE;
+		break;
+	case IPAQ_EGPIO_OPT_NVRAM_ON:
+		egpio |= EGPIO_H3600_OPT_NVRAM_ON;
+		break;
+	case IPAQ_EGPIO_OPT_ON:
+		egpio |= EGPIO_H3600_OPT_ON;
+		break;
+	case IPAQ_EGPIO_CARD_RESET:
+		egpio |= EGPIO_H3600_CARD_RESET;
+		break;
+	case IPAQ_EGPIO_OPT_RESET:
+		egpio |= EGPIO_H3600_OPT_RESET;
+		break;
+	case IPAQ_EGPIO_IR_ON:
+		gpio |= GPIO_H3100_IR_ON;
+		break;
+	case IPAQ_EGPIO_IR_FSEL:
+		gpio |= GPIO_H3100_IR_FSEL;
+		break;
+	case IPAQ_EGPIO_RS232_ON:
+		egpio |= EGPIO_H3600_RS232_ON;
+		break;
+	case IPAQ_EGPIO_VPP_ON:
+		egpio |= EGPIO_H3600_VPP_ON;
+		break;
+	}
+
+	local_irq_save(flags);
+	if ( setp ) {
+		h3600_egpio |= egpio;
+		GPSR = gpio;
+	} else {
+		h3600_egpio &= ~egpio;
+		GPCR = gpio;
+	}
+	H3600_EGPIO = h3600_egpio;
+	local_irq_restore(flags);
+
+	/*
+	if ( x != IPAQ_EGPIO_VPP_ON ) {
+		printk(__FUNCTION__ " : type=%d (%s) gpio=0x%x (0x%x) egpio=0x%x (0x%x) setp=%d\n",
+		       x, egpio_names[x], GPLR, gpio, h3600_egpio, egpio, setp );
+	}
+	*/
+}
+
+static unsigned long h3100_read_egpio( void )
+{
+	return h3600_egpio;
+}
+
+static struct ipaq_model_ops h3100_model_ops __initdata = {
+	model	     : IPAQ_H3100,
+	generic_name : "3100",
+	initialize   : h3100_init_egpio,
+	control      : h3100_control_egpio,
+	read	     : h3100_read_egpio
+};
+
+
+/************************* H3600 *************************/
 
-void init_h3600_egpio(void)
+static void h3600_init_egpio( void )
 {
-#ifdef CONFIG_IPAQ_H3100
-	int h3100_controls = (GPIO_H3100_BT_ON
-			      | GPIO_H3100_QMUTE
-			      | GPIO_H3100_LCD_3V_ON 
-			      | GPIO_H3100_AUD_ON
-			      | GPIO_H3100_AUD_PWR_ON
-			      | GPIO_H3100_IR_ON
-			      | GPIO_H3100_IR_FSEL);
-	GPDR |= h3100_controls;
-	GPCR = h3100_controls;
-	GAFR = GPIO_SSP_CLK;
-#endif
-}
-
-void clr_h3600_egpio(unsigned long x)
-{
-#ifdef CONFIG_IPAQ_H3100
-	unsigned long gpcr = 0;
-	if (x&EGPIO_H3600_QMUTE)
-		gpcr |= GPIO_H3100_QMUTE;
-	if (x&EGPIO_H3600_LCD_ON)
-		gpcr |= GPIO_H3100_LCD_3V_ON;
-	if (x&EGPIO_H3600_AUD_AMP_ON)
-		gpcr |= GPIO_H3100_AUD_ON;
-	if (x&EGPIO_H3600_AUD_PWR_ON)
-		gpcr |= GPIO_H3100_AUD_PWR_ON;
-	if (x&EGPIO_H3600_IR_ON)
-		gpcr |= GPIO_H3100_IR_ON;
-	if (x&EGPIO_H3600_IR_FSEL)
-		gpcr |= GPIO_H3100_IR_FSEL;
-	GPCR = gpcr;
-#endif
-	h3600_egpio &= ~x;
+	h3600_egpio = EGPIO_H3600_RS232_ON;
 	H3600_EGPIO = h3600_egpio;
 }
 
-void set_h3600_egpio(unsigned long x)
+static void h3600_control_egpio( enum ipaq_egpio_type x, int setp )
 {
-#ifdef CONFIG_IPAQ_H3100
-	unsigned long gpsr = 0;
-	if (x&EGPIO_H3600_QMUTE)
-		gpsr |= GPIO_H3100_QMUTE;
-	if (x&EGPIO_H3600_LCD_ON)
-		gpsr |= GPIO_H3100_LCD_3V_ON;
-	if (x&EGPIO_H3600_AUD_AMP_ON)
-		gpsr |= GPIO_H3100_AUD_ON;
-	if (x&EGPIO_H3600_AUD_PWR_ON)
-		gpsr |= GPIO_H3100_AUD_PWR_ON;
-	if (x&EGPIO_H3600_IR_ON)
-		gpsr |= GPIO_H3100_IR_ON;
-	if (x&EGPIO_H3600_IR_FSEL)
-		gpsr |= GPIO_H3100_IR_FSEL;
-	GPSR = gpsr;
-#endif
-	h3600_egpio |= x;
+	unsigned int egpio = 0;
+	unsigned long flags;
+
+	switch (x) {
+	case IPAQ_EGPIO_LCD_ON:
+		egpio |= EGPIO_H3600_LCD_ON |
+			 EGPIO_H3600_LCD_PCI |
+			 EGPIO_H3600_LCD_5V_ON |
+			 EGPIO_H3600_LVDD_ON;
+		break;
+	case IPAQ_EGPIO_CODEC_NRESET:
+		egpio |= EGPIO_H3600_CODEC_NRESET;
+		break;
+	case IPAQ_EGPIO_AUDIO_ON:
+		egpio |= EGPIO_H3600_AUD_AMP_ON |
+			EGPIO_H3600_AUD_PWR_ON;
+		break;
+	case IPAQ_EGPIO_QMUTE:
+		egpio |= EGPIO_H3600_QMUTE;
+		break;
+	case IPAQ_EGPIO_OPT_NVRAM_ON:
+		egpio |= EGPIO_H3600_OPT_NVRAM_ON;
+		break;
+	case IPAQ_EGPIO_OPT_ON:
+		egpio |= EGPIO_H3600_OPT_ON;
+		break;
+	case IPAQ_EGPIO_CARD_RESET:
+		egpio |= EGPIO_H3600_CARD_RESET;
+		break;
+	case IPAQ_EGPIO_OPT_RESET:
+		egpio |= EGPIO_H3600_OPT_RESET;
+		break;
+	case IPAQ_EGPIO_IR_ON:
+		egpio |= EGPIO_H3600_IR_ON;
+		break;
+	case IPAQ_EGPIO_IR_FSEL:
+		egpio |= EGPIO_H3600_IR_FSEL;
+		break;
+	case IPAQ_EGPIO_RS232_ON:
+		egpio |= EGPIO_H3600_RS232_ON;
+		break;
+	case IPAQ_EGPIO_VPP_ON:
+		egpio |= EGPIO_H3600_VPP_ON;
+		break;
+	}
+
+	local_irq_save(flags);
+	if ( setp )
+		h3600_egpio |= egpio;
+	else
+		h3600_egpio &= ~egpio;
 	H3600_EGPIO = h3600_egpio;
+	local_irq_restore(flags);
+}
+
+static unsigned long h3600_read_egpio( void )
+{
+	return h3600_egpio;
+}
+
+static struct ipaq_model_ops h3600_model_ops __initdata = {
+	model	     : IPAQ_H3600,
+	generic_name : "3600",
+	initialize   : h3600_init_egpio,
+	control      : h3600_control_egpio,
+	read	     : h3600_read_egpio
+};
+
+/************************* H3800 *************************/
+
+#define ASIC1_OUTPUTS	 0x7fff   /* First 15 bits are used */
+
+static unsigned int h3800_asic1_gpio;
+static unsigned int h3800_asic2_gpio;
+
+static void h3800_init_egpio(void)
+{
+	/* Set up ASIC #1 */
+	H3800_ASIC1_GPIO_Direction    = ASIC1_OUTPUTS;		  /* All outputs */
+	H3800_ASIC1_GPIO_Mask	      = ASIC1_OUTPUTS;		  /* No interrupts */
+	H3800_ASIC1_GPIO_SleepMask    = ASIC1_OUTPUTS;
+	H3800_ASIC1_GPIO_SleepDir     = ASIC1_OUTPUTS;
+	H3800_ASIC1_GPIO_SleepOut     = GPIO_H3800_ASIC1_EAR_ON_N;
+	H3800_ASIC1_GPIO_BattFaultDir = ASIC1_OUTPUTS;
+	H3800_ASIC1_GPIO_BattFaultOut = GPIO_H3800_ASIC1_EAR_ON_N;
+
+	h3800_asic1_gpio = GPIO_H3800_ASIC1_IR_ON_N   /* TODO: Check IR level */
+		| GPIO_H3800_ASIC1_RS232_ON
+		| GPIO_H3800_ASIC1_EAR_ON_N;
+
+	H3800_ASIC1_GPIO_Out = h3800_asic1_gpio;
+
+	/* Set up ASIC #2 */
+	H3800_ASIC2_GPIO_Direction = GPIO_H3800_ASIC2_PEN_IRQ
+		| GPIO_H3800_ASIC2_SD_DETECT
+		| GPIO_H3800_ASIC2_EAR_IN_N
+		| GPIO_H3800_ASIC2_USB_DETECT_N
+		| GPIO_H3800_ASIC2_SD_CON_SLT;
+
+	h3800_asic2_gpio = GPIO_H3800_ASIC2_IN_Y1_N | GPIO_H3800_ASIC2_IN_X1_N;
+	H3800_ASIC2_GPIO_Data	      = h3800_asic2_gpio;
+	H3800_ASIC2_GPIO_BattFaultOut = h3800_asic2_gpio;
+
+	/* TODO : Set sleep states & battery fault states */
+
+	/* Clear VPP Enable */
+	H3800_ASIC1_FlashWP_VPP_ON = 0;
+}
+
+static void h3800_control_egpio( enum ipaq_egpio_type x, int setp )
+{
+	unsigned int set_asic1_egpio = 0;
+	unsigned int clear_asic1_egpio = 0;
+	unsigned long flags;
+
+	switch (x) {
+	case IPAQ_EGPIO_LCD_ON:
+		set_asic1_egpio |= GPIO_H3800_ASIC1_LCD_5V_ON
+			| GPIO_H3800_ASIC1_LCD_ON
+			| GPIO_H3800_ASIC1_LCD_PCI
+			| GPIO_H3800_ASIC1_VGH_ON
+			| GPIO_H3800_ASIC1_VGL_ON;
+		break;
+	case IPAQ_EGPIO_CODEC_NRESET:
+		break;
+	case IPAQ_EGPIO_AUDIO_ON:
+		break;
+	case IPAQ_EGPIO_QMUTE:
+		break;
+	case IPAQ_EGPIO_OPT_NVRAM_ON:
+		break;
+	case IPAQ_EGPIO_OPT_ON:
+		break;
+	case IPAQ_EGPIO_CARD_RESET:
+		break;
+	case IPAQ_EGPIO_OPT_RESET:
+		break;
+	case IPAQ_EGPIO_IR_ON:
+		clear_asic1_egpio |= GPIO_H3800_ASIC1_IR_ON_N;	 /* TODO : This is backwards? */
+		break;
+	case IPAQ_EGPIO_IR_FSEL:
+		break;
+	case IPAQ_EGPIO_RS232_ON:
+		set_asic1_egpio |= GPIO_H3800_ASIC1_RS232_ON;
+		break;
+	case IPAQ_EGPIO_VPP_ON:
+		H3800_ASIC1_FlashWP_VPP_ON = setp;
+		break;
+	}
+
+	local_irq_save(flags);
+	if ( setp ) {
+		h3800_asic1_gpio |= set_asic1_egpio;
+		h3800_asic1_gpio &= ~clear_asic1_egpio;
+	}
+	else {
+		h3800_asic1_gpio &= ~set_asic1_egpio;
+		h3800_asic1_gpio |= clear_asic1_egpio;
+	}
+	H3800_ASIC1_GPIO_Out = h3800_asic1_gpio;
+	local_irq_restore(flags);
+}
+
+static unsigned long h3800_read_egpio( void )
+{
+	return h3800_asic1_gpio | (h3800_asic2_gpio << 16);
 }
 
-EXPORT_SYMBOL(clr_h3600_egpio);
-EXPORT_SYMBOL(set_h3600_egpio);
+static struct ipaq_model_ops h3800_model_ops __initdata = {
+	model	     : IPAQ_H3800,
+	generic_name : "3800",
+	initialize   : h3800_init_egpio,
+	control      : h3800_control_egpio,
+	read	     : h3800_read_egpio
+};
 
 
 /*
- * Low-level UART features.
- *
- * Note that RTS, CTS and DCD are all active low.
+ * Use command line argument to choose between ipaq handheld model numbers
+ */
+
+struct ipaq_model_ops ipaq_model_ops;
+EXPORT_SYMBOL(ipaq_model_ops);
+
+static int __init h3600_init_model_ops(void)
+{
+	if (machine_is_h3xxx()) {
+		if (machine_is_h3100()) {
+			ipaq_model_ops = h3100_model_ops;
+		} else if (machine_is_h3600()) {
+			ipaq_model_ops = h3600_model_ops;
+		} else if (machine_is_h3800()) {
+			ipaq_model_ops = h3800_model_ops;
+		}
+		init_h3600_egpio();
+	}
+	return 0;
+}
+
+__initcall(h3600_init_model_ops);
+
+/*
+ * low-level UART features
  */
 
 static void h3600_uart_set_mctrl(struct uart_port *port, u_int mctrl)
@@ -107,9 +377,9 @@
 	}
 }
 
-static int h3600_uart_get_mctrl(struct uart_port *port)
+static u_int h3600_uart_get_mctrl(struct uart_port *port)
 {
-	int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
+	u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
 
 	if (port->mapbase == _Ser3UTCR0) {
 		int gplr = GPLR;
@@ -139,18 +409,28 @@
 static void h3600_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
 {
 	if (port->mapbase == _Ser2UTCR0) {
-		if (state == 0) {
-			set_h3600_egpio(EGPIO_H3600_IR_ON);
-		} else {
-			clr_h3600_egpio(EGPIO_H3600_IR_ON);
-		}
+		assign_h3600_egpio( IPAQ_EGPIO_IR_ON, !state );
 	} else if (port->mapbase == _Ser3UTCR0) {
-		if (state == 0) {
-			set_h3600_egpio(EGPIO_H3600_RS232_ON);
-		} else {
-			clr_h3600_egpio(EGPIO_H3600_RS232_ON);
-		}
+		assign_h3600_egpio( IPAQ_EGPIO_RS232_ON, !state );
+	}
+}
+
+/*
+ * Enable/Disable wake up events for this serial port.
+ * Obviously, we only support this on the normal COM port.
+ */
+static int h3600_uart_set_wake(struct uart_port *port, u_int enable)
+{
+	int err = -EINVAL;
+
+	if (port->mapbase == _Ser3UTCR0) {
+		if (enable)
+			PWER |= PWER_GPIO23 | PWER_GPIO25 ; /* DCD and CTS */
+		else
+			PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
+		err = 0;
 	}
+	return err;
 }
 
 static int h3600_uart_open(struct uart_port *port, struct uart_info *info)
@@ -163,8 +443,6 @@
 		Ser2HSSR0 = HSSR0_EIF | HSSR0_TUR |
 			    HSSR0_RAB | HSSR0_FRE;
 	} else if (port->mapbase == _Ser3UTCR0) {
-		GPDR &= ~(GPIO_H3600_COM_DCD|GPIO_H3600_COM_CTS);
-		GPDR |= GPIO_H3600_COM_RTS;
 		set_GPIO_IRQ_edge(GPIO_H3600_COM_DCD|GPIO_H3600_COM_CTS,
 				  GPIO_BOTH_EDGES);
 
@@ -193,16 +471,17 @@
 	set_mctrl:	h3600_uart_set_mctrl,
 	get_mctrl:	h3600_uart_get_mctrl,
 	pm:		h3600_uart_pm,
+	set_wake:	h3600_uart_set_wake,
 	open:		h3600_uart_open,
 	close:		h3600_uart_close,
 };
 
 static struct map_desc h3600_io_desc[] __initdata = {
- /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x49000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 */
-  { 0xf1000000, 0x10000000, 0x02800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 2 */
-  { 0xf3800000, 0x40000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 4 */
+ /* virtual	       physical    length      domain	  r  w	c  b */
+  { 0xe8000000,        0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 	 CS#0 */
+  { H3600_EGPIO_VIRT,  0x49000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0		 CS#5 */
+  { H3600_BANK_2_VIRT, 0x10000000, 0x02800000, DOMAIN_IO, 0, 1, 0, 0 }, /* static memory bank 2  CS#2 */
+  { H3600_BANK_4_VIRT, 0x40000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* static memory bank 4  CS#4 */
   LAST_DESC
 };
 
@@ -214,13 +493,19 @@
 	sa1100_register_uart_fns(&h3600_port_fns);
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1); /* isn't this one driven elsewhere? */
-	init_h3600_egpio();
 
 	/*
-	 * Default GPIO settings.
+	 * Default GPIO settings.  Should be set by machine
 	 */
 	GPCR = 0x0fffffff;
-	GPDR = 0x0401f3fc;
+//	GPDR = 0x0401f3fc;
+	GPDR = GPIO_H3600_COM_RTS  | GPIO_H3600_L3_CLOCK |
+	       GPIO_H3600_L3_MODE  | GPIO_H3600_L3_DATA  |
+	       GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 |
+	       GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
+	       GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9  | GPIO_LDD8;
+
+	init_h3600_egpio();
 
 	/*
 	 * Ensure those pins are outputs and driving low.
@@ -230,11 +515,24 @@
 
 	/* Configure suspend conditions */
 	PGSR = 0;
-	PWER = 0x1 | (1 << 31);
-	PCFR = PCFR_OPDE | PCFR_FP | PCFR_FS;
+	PWER = PWER_GPIO0 | PWER_RTC;
+	PCFR = PCFR_OPDE;
+	PSDR = 0;
 }
 
-MACHINE_START(H3600, "Compaq iPAQ")
+MACHINE_START(H3600, "Compaq iPAQ H3600")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	BOOT_PARAMS(0xc0000100)
+	MAPIO(h3600_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END
+MACHINE_START(H3100, "Compaq iPAQ H3100")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	BOOT_PARAMS(0xc0000100)
+	MAPIO(h3600_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END
+MACHINE_START(H3800, "Compaq iPAQ H3800")
 	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
 	BOOT_PARAMS(0xc0000100)
 	MAPIO(h3600_map_io)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/huw_webpanel.c linux/arch/arm/mach-sa1100/huw_webpanel.c
--- linux.orig/arch/arm/mach-sa1100/huw_webpanel.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/huw_webpanel.c	2002-08-01 06:42:42.000000000 +0000
@@ -2,8 +2,6 @@
  * linux/arch/arm/mach-sa1100/huw_webpanel.c
  *
  */
-
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -55,8 +53,8 @@
 **/
 static struct map_desc huw_webpanel_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0, neccessary for mtd */
-  { 0xf0000000, 0xc1fb8000, 0x00048000, DOMAIN_IO, 1, 1, 0, 0 }, /* Parameter */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0, neccessary for mtd */
+  { 0xf0000000, 0xc1fb8000, 0x00048000, DOMAIN_IO, 0, 1, 0, 0 }, /* Parameter */
   { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */
   LAST_DESC
 };
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/irq.c linux/arch/arm/mach-sa1100/irq.c
--- linux.orig/arch/arm/mach-sa1100/irq.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/irq.c	2002-08-01 06:42:48.000000000 +0000
@@ -9,12 +9,11 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
-#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/ptrace.h>
 
 #include <asm/hardware.h>
@@ -35,8 +34,13 @@
 static int GPIO_IRQ_rising_edge;
 static int GPIO_IRQ_falling_edge;
 
-void set_GPIO_IRQ_edge( int gpio_mask, int edge )
+void set_GPIO_IRQ_edge(int gpio_mask, int edge)
 {
+	long flags;
+	int irq = 0;
+
+	gpio_mask &= 0x0fffffff;
+	local_irq_save(flags);
 	if (edge & GPIO_FALLING_EDGE)
 		GPIO_IRQ_falling_edge |= gpio_mask;
 	else
@@ -45,6 +49,17 @@
 		GPIO_IRQ_rising_edge |= gpio_mask;
 	else
 		GPIO_IRQ_rising_edge &= ~gpio_mask;
+	GPDR &= ~gpio_mask;
+	GAFR &= ~gpio_mask;
+	while (gpio_mask) {
+		if (irq == 11)
+			irq = IRQ_GPIO11;
+		if (gpio_mask & 1)
+			irq_desc[irq].valid = 1;
+		irq++;
+		gpio_mask >>= 1;
+	}
+	local_irq_restore(flags);
 }
 
 EXPORT_SYMBOL(set_GPIO_IRQ_edge);
@@ -121,7 +136,7 @@
 
 		for (i = 11; i <= 27; ++i) {
 			if (irq & (1<<i)) {
-				do_IRQ (IRQ_GPIO_11_27(i), regs);
+				do_IRQ(IRQ_GPIO11 + i - 11, regs);
 			}
 		}
 	}
@@ -175,11 +190,18 @@
 	GFER = (GFER & ~mask) | (GPIO_IRQ_falling_edge & mask);
 }
 
+static struct resource irq_resource = {
+	name:	"irqs",
+	start:	0x90050000,
+	end:	0x9005ffff,
+};
 
 void __init sa1100_init_irq(void)
 {
 	int irq;
 
+	request_resource(&iomem_resource, &irq_resource);
+
 	/* disable all IRQs */
 	ICMR = 0;
 
@@ -197,8 +219,13 @@
 	 */
 	ICCR = 1;
 
+	/*
+	 * Note: GPIO IRQs are initially invalid until at least one call
+	 * to set_GPIO_IRQ_edge() is performed.
+	 */
+
 	for (irq = 0; irq <= 10; irq++) {
-		irq_desc[irq].valid	= 1;
+		irq_desc[irq].valid	= 0;
 		irq_desc[irq].probe_ok	= 1;
 		irq_desc[irq].mask_ack	= sa1100_mask_and_ack_GPIO0_10_irq;
 		irq_desc[irq].mask	= sa1100_mask_GPIO0_10_irq;
@@ -214,7 +241,7 @@
 	}
 
 	for (irq = 32; irq <= 48; irq++) {
-		irq_desc[irq].valid	= 1;
+		irq_desc[irq].valid	= 0;
 		irq_desc[irq].probe_ok	= 1;
 		irq_desc[irq].mask_ack	= sa1100_mask_and_ack_GPIO11_27_irq;
 		irq_desc[irq].mask	= sa1100_mask_GPIO11_27_irq;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/itsy.c linux/arch/arm/mach-sa1100/itsy.c
--- linux.orig/arch/arm/mach-sa1100/itsy.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/itsy.c	2002-08-01 06:42:37.000000000 +0000
@@ -31,8 +31,8 @@
    likely wrong. */
 static struct map_desc itsy_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x49000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* EGPIO 0 */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x49000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/jornada720.c linux/arch/arm/mach-sa1100/jornada720.c
--- linux.orig/arch/arm/mach-sa1100/jornada720.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/jornada720.c	2002-08-01 06:42:44.000000000 +0000
@@ -37,20 +37,17 @@
 	SKCR = JORSKCR_INIT;	/* Turn on the PLL, enable Ready and enable nOE assertion from DC */
 	mdelay(100);
 
-	SKCR = JORSKCR_RCLK;	/* turn on the RCLOCK */
-	SMCR = 0x35;	/* initialize the SMC (debug SA-1111 reset */
-	PCCR = 0;	/* initialize the S2MC (debug SA-1111 reset) */
+	SBI_SKCR = JORSKCR_RCLK;/* turn on the RCLOCK */
+	SBI_SMCR = 0x35;	/* initialize the SMC (debug SA-1111 reset */
+	PCCR = 0;		/* initialize the S2MC (debug SA-1111 reset) */
 
 	/* LDD4 is speaker, LDD3 is microphone */
 	PPSR &= ~(PPC_LDD3 | PPC_LDD4);
 	PPDR |= PPC_LDD3 | PPC_LDD4;
 
 	/* initialize extra IRQs */
-	set_GPIO_IRQ_edge(GPIO_GPIO(1), GPIO_RISING_EDGE);
-	sa1111_init_irq(SA1100_GPIO_TO_IRQ(1));	/* chained on GPIO 1 */
-
-	sa1100_register_uart(0, 3);
-	sa1100_register_uart(1, 1);
+	set_GPIO_IRQ_edge(GPIO_GPIO1, GPIO_RISING_EDGE);
+	sa1111_init_irq(IRQ_GPIO1);	/* chained on GPIO 1 */
 
 	return 0;
 }
@@ -68,10 +65,10 @@
 
 static struct map_desc jornada720_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x48000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Epson registers */
-  { 0xf1000000, 0x48200000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Epson frame buffer */
-  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x48000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Epson registers */
+  { 0xf1000000, 0x48200000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Epson frame buffer */
+  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
   LAST_DESC
 };
 
@@ -79,6 +76,9 @@
 {
 	sa1100_map_io();
 	iotable_init(jornada720_io_desc);
+	
+	sa1100_register_uart(0, 3);
+	sa1100_register_uart(1, 1);
 }
 
 MACHINE_START(JORNADA720, "HP Jornada 720")
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/lart.c linux/arch/arm/mach-sa1100/lart.c
--- linux.orig/arch/arm/mach-sa1100/lart.c	2001-08-13 00:36:24.000000000 +0000
+++ linux/arch/arm/mach-sa1100/lart.c	2002-08-01 06:42:43.000000000 +0000
@@ -18,8 +18,8 @@
 
 static struct map_desc lart_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* main flash memory */
-  { 0xec000000, 0x08000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* main flash, alternative location */
+  { 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash memory */
+  { 0xec000000, 0x08000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash, alternative location */
   LAST_DESC
 };
 
@@ -31,6 +31,7 @@
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1);
 	sa1100_register_uart(2, 2);
+
 	GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
 	GPDR |= GPIO_UART_TXD;
 	GPDR &= ~GPIO_UART_RXD;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/leds-assabet.c linux/arch/arm/mach-sa1100/leds-assabet.c
--- linux.orig/arch/arm/mach-sa1100/leds-assabet.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/leds-assabet.c	2002-08-01 06:42:41.000000000 +0000
@@ -42,6 +42,8 @@
 
 	case led_stop:
 		led_state &= ~LED_STATE_ENABLED;
+		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
+		ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
 		break;
 
 	case led_claim:
@@ -107,8 +109,7 @@
 	}
 
 	if  (led_state & LED_STATE_ENABLED)
-		ASSABET_BCR = BCR_value = (BCR_value & ~ASSABET_BCR_LED_MASK) |
-			hw_led_state;
+		ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
 
 	local_irq_restore(flags);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/leds-flexanet.c linux/arch/arm/mach-sa1100/leds-flexanet.c
--- linux.orig/arch/arm/mach-sa1100/leds-flexanet.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/leds-flexanet.c	2002-08-01 06:42:30.000000000 +0000
@@ -35,7 +35,7 @@
 	switch (evt) {
 	case led_start:
 		/* start using LEDs and enable its hardware */
-		hw_led_bcr = BCR_LED_GREEN;
+		hw_led_bcr = FHH_BCR_LED_GREEN;
 		hw_led_gpio = GPIO_LED_RED;
 		led_state = LED_STATE_ENABLED;
 		break;
@@ -71,13 +71,13 @@
 	case led_idle_start:
 		/* turn off CPU load LED */
 		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_bcr &= ~BCR_LED_GREEN;
+			hw_led_bcr &= ~FHH_BCR_LED_GREEN;
 		break;
 
 	case led_idle_end:
 		/* turn on CPU load LED */
 		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_bcr |= BCR_LED_GREEN;
+			hw_led_bcr |= FHH_BCR_LED_GREEN;
 		break;
 #endif
 
@@ -88,12 +88,12 @@
 	/* direct LED access (must be previously claimed) */
 	case led_green_on:
 		if (led_state & LED_STATE_CLAIMED)
-			hw_led_bcr |= BCR_LED_GREEN;
+			hw_led_bcr |= FHH_BCR_LED_GREEN;
 		break;
 
 	case led_green_off:
 		if (led_state & LED_STATE_CLAIMED)
-			hw_led_bcr &= ~BCR_LED_GREEN;
+			hw_led_bcr &= ~FHH_BCR_LED_GREEN;
 		break;
 
 	case led_amber_on:
@@ -119,7 +119,7 @@
 	if  (led_state & LED_STATE_ENABLED)
 	{
 		/* update LEDs */
-		BCR = BCR_value = (BCR_value & ~BCR_LED_GREEN) | hw_led_bcr;
+		FHH_BCR = flexanet_BCR = (flexanet_BCR & ~FHH_BCR_LED_GREEN) | hw_led_bcr;
 		GPSR = hw_led_gpio;
 		GPCR = hw_led_gpio ^ GPIO_LED_RED;
 	}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/leds-frodo.c linux/arch/arm/mach-sa1100/leds-frodo.c
--- linux.orig/arch/arm/mach-sa1100/leds-frodo.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-sa1100/leds-frodo.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,121 @@
+
+/*
+ * linux/arch/arm/mach-sa1100/leds-frodo.c
+ *
+ * Author: Abraham van der Merwe <abraham@2d3d.co.za>
+ *
+ * This file contains the 2d3D, Inc. SA-1110 Development Board LED
+ * event handler.
+ *
+ * Frodo LEDs
+ *
+ *   - led6 - toggles state every 50 timer interrupts (Heartbeat)
+ *   - led7 - on if system is not idle (CPU load)
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include "leds.h"
+
+#define led6_on() FRODO_CPLD_GENERAL |= FRODO_LED2
+#define led6_off() FRODO_CPLD_GENERAL &= ~FRODO_LED2
+#define led6_invert() do {						\
+		if ((FRODO_CPLD_GENERAL & FRODO_LED2))	\
+			led6_off ();						\
+		else									\
+			led6_on ();							\
+	} while (0)
+
+#define led7_on() FRODO_CPLD_GENERAL |= FRODO_LED1
+#define led7_off() FRODO_CPLD_GENERAL &= ~FRODO_LED1
+#define led7_invert() do {						\
+		if ((FRODO_CPLD_GENERAL & FRODO_LED1))	\
+			led7_off ();						\
+		else									\
+			led7_on ();							\
+	} while (0)
+
+static int claimed;
+
+void frodo_leds_event (led_event_t evt)
+{
+   unsigned long flags;
+
+   local_irq_save (flags);
+
+   switch (evt)
+	 {
+#ifdef CONFIG_LEDS_CPU
+		/* turn off CPU load LED */
+	  case led_idle_start:
+		if (!claimed) led7_off ();
+		break;
+
+		/* turn on CPU load LED */
+	  case led_idle_end:
+		if (!claimed) led7_on ();
+		break;
+#endif
+
+#ifdef CONFIG_LEDS_TIMER
+		/* toggle heartbeat LED */
+	  case led_timer:
+		if (!claimed) led6_invert ();
+		break;
+#endif
+
+		/* start: turn on LEDs and set claimed to 0 */
+	  case led_start:
+		led6_on ();
+		led7_on ();
+		claimed = 0;
+		break;
+
+		/* stop: turn off LEDs */
+	  case led_stop:
+		led6_off ();
+		led7_off ();
+		break;
+
+		/* override CPU load & timer LEDs */
+	  case led_claim:
+		claimed = 1;
+		break;
+
+		/* restore CPU load & timer LEDs */
+	  case led_release:
+		claimed = 0;
+		break;
+
+		/* direct LED access (must be previously claimed) */
+
+		/* led7 */
+	  case led_green_on:
+		if (claimed) led7_on ();
+		break;
+
+	  case led_green_off:
+		if (claimed) led7_off ();
+		break;
+
+		/* led6 -- at the moment this is actually also green */
+	  case led_red_on:
+		if (claimed) led6_on ();
+		break;
+
+	  case led_red_off:
+		if (claimed) led6_off ();
+		break;
+
+	  default:
+		break;
+	}
+
+   local_irq_restore (flags);
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/leds-system3.c linux/arch/arm/mach-sa1100/leds-system3.c
--- linux.orig/arch/arm/mach-sa1100/leds-system3.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-sa1100/leds-system3.c	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * linux/arch/arm/mach-sa1100/leds-system3.c
+ *
+ * Copyright (C) 2001 Stefan Eletzhofer <stefan.eletzhofer@gmx.de>
+ *
+ * Original (leds-footbridge.c) by Russell King
+ *
+ * $Id: leds-system3.c,v 1.1.6.1 2001/12/04 15:19:26 seletz Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Log: leds-system3.c,v $
+ * Revision 1.1.6.1  2001/12/04 15:19:26  seletz
+ * - merged from linux_2_4_13_ac5_rmk2
+ *
+ * Revision 1.1.4.2  2001/11/19 17:58:53  seletz
+ * - cleanup
+ *
+ * Revision 1.1.4.1  2001/11/16 13:49:54  seletz
+ * - dummy LED support for PT Digital Board
+ *
+ * Revision 1.1.2.1  2001/10/15 16:03:39  seletz
+ * - dummy function
+ *
+ *
+ */
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include "leds.h"
+
+
+#define LED_STATE_ENABLED	1
+#define LED_STATE_CLAIMED	2
+
+static unsigned int led_state;
+static unsigned int hw_led_state;
+
+void system3_leds_event(led_event_t evt)
+{
+	/* TODO: support LEDs */
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/leds.c linux/arch/arm/mach-sa1100/leds.c
--- linux.orig/arch/arm/mach-sa1100/leds.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/leds.c	2002-08-01 06:42:34.000000000 +0000
@@ -5,7 +5,6 @@
  * 
  * Copyright (C) 2001 Nicolas Pitre
  */
-#include <linux/config.h>
 #include <linux/init.h>
 
 #include <asm/leds.h>
@@ -16,24 +15,30 @@
 static int __init
 sa1100_leds_init(void)
 {
+	if (machine_is_adsbitsy())
+		leds_event = adsbitsy_leds_event;
 	if (machine_is_assabet())
 		leds_event = assabet_leds_event;
+ 	if (machine_is_consus())
+ 	        leds_event = consus_leds_event;
 	if (machine_is_brutus())
 		leds_event = brutus_leds_event;
 	if (machine_is_cerf())
 		leds_event = cerf_leds_event;
 	if (machine_is_flexanet())
 		leds_event = flexanet_leds_event;
+	if (machine_is_frodo())
+		leds_event = frodo_leds_event;
 	if (machine_is_graphicsclient())
 		leds_event = graphicsclient_leds_event;
+	if (machine_is_graphicsmaster())
+		leds_event = graphicsmaster_leds_event;
 	if (machine_is_lart())
 		leds_event = lart_leds_event;
 	if (machine_is_pfs168())
 		leds_event = pfs168_leds_event;
-	if (machine_is_graphicsmaster())
-		leds_event = graphicsmaster_leds_event;
-	if (machine_is_adsbitsy())
-		leds_event = adsbitsy_leds_event;
+	if (machine_is_pt_system3())
+		leds_event = system3_leds_event;
 
 	leds_event(led_start);
 	return 0;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/leds.h linux/arch/arm/mach-sa1100/leds.h
--- linux.orig/arch/arm/mach-sa1100/leds.h	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/leds.h	2002-08-01 06:42:35.000000000 +0000
@@ -1,4 +1,5 @@
 extern void assabet_leds_event(led_event_t evt);
+extern void consus_leds_event(led_event_t evt);
 extern void brutus_leds_event(led_event_t evt);
 extern void cerf_leds_event(led_event_t evt);
 extern void flexanet_leds_event(led_event_t evt);
@@ -7,3 +8,5 @@
 extern void pfs168_leds_event(led_event_t evt);
 extern void graphicsmaster_leds_event(led_event_t evt);
 extern void adsbitsy_leds_event(led_event_t evt);
+extern void system3_leds_event(led_event_t evt);
+extern void frodo_leds_event(led_event_t evt);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/nanoengine.c linux/arch/arm/mach-sa1100/nanoengine.c
--- linux.orig/arch/arm/mach-sa1100/nanoengine.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/nanoengine.c	2002-08-01 06:42:28.000000000 +0000
@@ -34,9 +34,9 @@
 
 static struct map_desc nanoengine_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x10000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* System Registers */
-  { 0xf1000000, 0x18A00000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Internal PCI Config Space */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
+  { 0xf1000000, 0x18A00000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Internal PCI Config Space */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/neponset.c linux/arch/arm/mach-sa1100/neponset.c
--- linux.orig/arch/arm/mach-sa1100/neponset.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/neponset.c	2002-08-01 06:42:43.000000000 +0000
@@ -7,6 +7,8 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
+#include <linux/tty.h>
+#include <linux/ioport.h>
 #include <linux/serial_core.h>
 
 #include <asm/hardware.h>
@@ -16,6 +18,7 @@
 #include <asm/arch/irq.h>
 #include <asm/mach/serial_sa1100.h>
 #include <asm/arch/assabet.h>
+#include <asm/hardware/sa1111.h>
 
 #include "sa1111.h"
 
@@ -40,10 +43,10 @@
 		if (!irr) break;
 
 		if( irr & IRR_ETHERNET )
-			do_IRQ(NEPONSET_ETHERNET_IRQ, regs);
+			do_IRQ(IRQ_NEPONSET_SMC9196, regs);
 
 		if( irr & IRR_USAR )
-			do_IRQ(NEPONSET_USAR_IRQ, regs);
+			do_IRQ(IRQ_NEPONSET_USAR, regs);
 
 		if( irr & IRR_SA1111 )
 			sa1111_IRQ_demux(irq, dev_id, regs);
@@ -58,19 +61,16 @@
 
 static void __init neponset_init_irq(void)
 {
-	int irq;
-
 	sa1111_init_irq(-1);	/* SA1111 IRQ not routed to a GPIO */
 
 	/* setup extra Neponset IRQs */
-	irq = NEPONSET_ETHERNET_IRQ;
-	irq_desc[irq].valid	= 1;
-	irq_desc[irq].probe_ok	= 1;
-	irq = NEPONSET_USAR_IRQ;
-	irq_desc[irq].valid	= 1;
-	irq_desc[irq].probe_ok	= 1;
-	set_GPIO_IRQ_edge(ASSABET_GPIO_NEP_IRQ, GPIO_RISING_EDGE);
-	setup_arm_irq(ASSABET_IRQ_GPIO_NEP_IRQ, &neponset_irq);
+	irq_desc[IRQ_NEPONSET_SMC9196].valid	= 1;
+	irq_desc[IRQ_NEPONSET_SMC9196].probe_ok	= 1;
+	irq_desc[IRQ_NEPONSET_USAR].valid	= 1;
+	irq_desc[IRQ_NEPONSET_USAR].probe_ok	= 1;
+
+	set_GPIO_IRQ_edge(GPIO_GPIO25, GPIO_RISING_EDGE);
+	setup_arm_irq(IRQ_GPIO25, &neponset_irq);
 }
 
 static int __init neponset_init(void)
@@ -102,6 +102,11 @@
 	}
 
 	/*
+	 * Disable GPIO 0/1 drivers so the buttons work on the module.
+	 */
+	NCR_0 |= NCR_GP01_OFF;
+
+	/*
 	 * Neponset has SA1111 connected to CS4.  We know that after
 	 * reset the chip will be configured for variable latency IO.
 	 */
@@ -110,7 +115,7 @@
 	/*
 	 * Probe for a SA1111.
 	 */
-	ret = sa1111_probe();
+	ret = sa1111_probe(NEPONSET_SA1111_BASE);
 	if (ret < 0)
 		return ret;
 
@@ -150,8 +155,8 @@
 
 static struct map_desc neponset_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xf3000000, 0x10000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* System Registers */
-  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */
+  { 0xf3000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
+  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
   LAST_DESC
 };
 
@@ -184,7 +189,7 @@
 	MDM_CTL_0 = mdm_ctl0;
 }
 
-static int neponset_get_mctrl(struct uart_port *port)
+static u_int neponset_get_mctrl(struct uart_port *port)
 {
 	u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
 	u_int mdm_ctl1 = MDM_CTL_1;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/omnimeter.c linux/arch/arm/mach-sa1100/omnimeter.c
--- linux.orig/arch/arm/mach-sa1100/omnimeter.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/omnimeter.c	2002-08-01 06:42:27.000000000 +0000
@@ -30,7 +30,7 @@
 
 static struct map_desc omnimeter_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xd2000000, 0x10000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* TS */
+  { 0xd2000000, 0x10000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* TS */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/pangolin.c linux/arch/arm/mach-sa1100/pangolin.c
--- linux.orig/arch/arm/mach-sa1100/pangolin.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/pangolin.c	2002-08-01 06:42:47.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-sa1100/pangolin.c
  */
-
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
@@ -30,8 +30,8 @@
 
 static struct map_desc pangolin_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */
+  { 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
   LAST_DESC
 };
 
@@ -43,6 +43,12 @@
 	sa1100_register_uart(0, 1);
 	sa1100_register_uart(1, 3);
 	Ser1SDCR0 |= SDCR0_UART;
+
+	/* set some GPDR bits while it's safe */
+	GPDR |= GPIO_PCMCIA_RESET;
+#ifndef CONFIG_SA1100_PANGOLIN_PCMCIA_IDE
+	GPDR |= GPIO_PCMCIA_BUS_ON;
+#endif
 }
 
 MACHINE_START(PANGOLIN, "Dialogue-Pangolin")
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/pfs168.c linux/arch/arm/mach-sa1100/pfs168.c
--- linux.orig/arch/arm/mach-sa1100/pfs168.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/pfs168.c	2002-08-01 06:42:27.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-sa1100/pfs168.c
  */
-
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
@@ -34,7 +34,7 @@
 	/*
 	 * Probe for SA1111.
 	 */
-	ret = sa1111_probe();
+	ret = sa1111_probe(PFS168_SA1111_BASE);
 	if (ret < 0)
 		return ret;
 
@@ -65,8 +65,7 @@
 	 */
 	sa1110_mb_enable();
 
-	set_GPIO_IRQ_edge(GPIO_GPIO(25), GPIO_RISING_EDGE);
-	sa1111_init_irq(SA1100_GPIO_TO_IRQ(25));	/* SA1111 IRQ on GPIO 25 */
+	sa1111_init_irq(IRQ_GPIO25);	/* SA1111 IRQ on GPIO 25 */
 
 	return 0;
 }
@@ -84,6 +83,8 @@
 	 */
 	set_GPIO_IRQ_edge(GPIO_GPIO(19), GPIO_RISING_EDGE);
 	set_GPIO_IRQ_edge(GPIO_GPIO(20), GPIO_RISING_EDGE);
+	set_GPIO_IRQ_edge(GPIO_GPIO(25), GPIO_RISING_EDGE);
+	set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ, GPIO_RISING_EDGE);
 }
 
 
@@ -101,20 +102,20 @@
 
 static struct map_desc pfs168_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* 16C752 DUART port A (COM5) */
-  { 0xf0001000, 0x10800000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* 16C752 DUART port B (COM6) */
-  { 0xf0002000, 0x11000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* COM1 RTS control (SYSC1RTS) */
-  { 0xf0003000, 0x11400000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* Status LED control (SYSLED) */
-  { 0xf0004000, 0x11800000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* DTMF code read (SYSDTMF) */
-  { 0xf0005000, 0x11c00000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* LCD configure, enable (SYSLCDDE) */
-  { 0xf0006000, 0x12000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* COM1 DSR and motion sense (SYSC1DSR) */
-  { 0xf0007000, 0x12800000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* COM3 xmit enable (SYSC3TEN) */
-  { 0xf0008000, 0x13000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* Control register A (SYSCTLA) */
-  { 0xf0009000, 0x13800000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* Control register B (SYSCTLB) */
-  { 0xf000a000, 0x18000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* SMC91C96 */
-  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */
-  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* 16C752 DUART port A (COM5) */
+  { 0xf0001000, 0x10800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* 16C752 DUART port B (COM6) */
+  { 0xf0002000, 0x11000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* COM1 RTS control (SYSC1RTS) */
+  { 0xf0003000, 0x11400000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Status LED control (SYSLED) */
+  { 0xf0004000, 0x11800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* DTMF code read (SYSDTMF) */
+  { 0xf0005000, 0x11c00000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD configure, enable (SYSLCDDE) */
+  { 0xf0006000, 0x12000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* COM1 DSR and motion sense (SYSC1DSR) */
+  { 0xf0007000, 0x12800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* COM3 xmit enable (SYSC3TEN) */
+  { 0xf0008000, 0x13000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Control register A (SYSCTLA) */
+  { 0xf0009000, 0x13800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Control register B (SYSCTLB) */
+  { 0xf000a000, 0x18000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* SMC91C96 */
+  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
+  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/pleb.c linux/arch/arm/mach-sa1100/pleb.c
--- linux.orig/arch/arm/mach-sa1100/pleb.c	2001-08-13 00:36:24.000000000 +0000
+++ linux/arch/arm/mach-sa1100/pleb.c	2002-08-01 06:42:37.000000000 +0000
@@ -35,8 +35,8 @@
 
 static struct map_desc pleb_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* main flash memory */
-  { 0xe8400000, 0x08000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* main flash, alternative location */
+  { 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash memory */
+  { 0xe8400000, 0x08000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash, alternative location */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/pm.c linux/arch/arm/mach-sa1100/pm.c
--- linux.orig/arch/arm/mach-sa1100/pm.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/pm.c	2002-08-01 06:42:35.000000000 +0000
@@ -19,30 +19,27 @@
  * 			Cleaned up, pushed platform dependent stuff
  * 			in the platform specific files.
  */
-
-/*
- * Debug macros
- */
-#define DEBUG 1
-#ifdef DEBUG
-#  define DPRINTK(fmt, args...)	printk("%s: " fmt, __FUNCTION__ , ## args)
-#else
-#  define DPRINTK(fmt, args...)
-#endif
-
-
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/pm.h>
 #include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
 #include <linux/sysctl.h>
-#include <linux/acpi.h>
+#include <linux/errno.h>
 
 #include <asm/hardware.h>
 #include <asm/memory.h>
 #include <asm/system.h>
+#include <asm/leds.h>
 
 #include "sleep.h"
 
+/*
+ * Debug macros
+ */
+#undef DEBUG
+
 extern void sa1100_cpu_suspend(void);
 extern void sa1100_cpu_resume(void);
 
@@ -54,22 +51,17 @@
 
 int pm_do_suspend(void)
 {
-	int retval;
-
 	/* set up pointer to sleep parameters */
-	sleep_save = kmalloc (SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC);
+	sleep_save = kmalloc(SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC);
 	if (!sleep_save)
 		return -ENOMEM;
-	sleep_save_p = virt_to_phys(sleep_save);
 
-	retval = pm_send_all(PM_SUSPEND, (void *)2);
-	if (retval) {
-		kfree(sleep_save);
-		return retval;
-	}
+	sleep_save_p = virt_to_phys(sleep_save);
 
 	cli();
 
+	leds_event(led_stop);
+
 	/* preserve current time */
 	RCNR = xtime.tv_sec;
 
@@ -112,7 +104,9 @@
 	/* ensure not to come back here if it wasn't intended */
 	PSPR = 0;
 
-	DPRINTK("*** made it back from resume\n");
+#ifdef DEBUG
+	printk(KERN_DEBUG "*** made it back from resume\n");
+#endif
 
 	/* restore registers */
 	RESTORE(GPDR);
@@ -146,21 +140,55 @@
 	/* restore current time */
 	xtime.tv_sec = RCNR;
 
+	leds_event(led_start);
+
 	sti();
 
 	kfree (sleep_save);
 
-	retval = pm_send_all(PM_RESUME, (void *)0);
-	if (retval)
-		return retval;
+	/*
+	 * Restore the CPU frequency settings.
+	 */
+#ifdef CONFIG_CPU_FREQ
+	cpufreq_restore();
+#endif
 
 	return 0;
 }
 
+#ifdef CONFIG_SYSCTL
+/*
+ * ARGH!  ACPI people defined CTL_ACPI in linux/acpi.h rather than
+ * linux/sysctl.h.
+ *
+ * This means our interface here won't survive long - it needs a new
+ * interface.  Quick hack to get this working - use sysctl id 9999.
+ */
+#warning ACPI broke the kernel, this interface needs to be fixed up.
+#define CTL_ACPI 9999
+#define ACPI_S1_SLP_TYP 19
+
+/*
+ * Send us to sleep.
+ */
+static int sysctl_pm_do_suspend(void)
+{
+	int retval;
+
+	retval = pm_send_all(PM_SUSPEND, (void *)3);
+
+	if (retval == 0) {
+		retval = pm_do_suspend();
+
+		pm_send_all(PM_RESUME, (void *)0);
+	}
+
+	return retval;
+}
 
 static struct ctl_table pm_table[] =
 {
-	{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&pm_do_suspend},
+	{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
 	{0}
 };
 
@@ -181,3 +209,4 @@
 
 __initcall(pm_init);
 
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/sa1111-pcibuf.c linux/arch/arm/mach-sa1100/sa1111-pcibuf.c
--- linux.orig/arch/arm/mach-sa1100/sa1111-pcibuf.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/sa1111-pcibuf.c	2002-08-01 06:42:27.000000000 +0000
@@ -13,7 +13,6 @@
  *
  *  06/13/2001 - created.
  */
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/sa1111.c linux/arch/arm/mach-sa1100/sa1111.c
--- linux.orig/arch/arm/mach-sa1100/sa1111.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/sa1111.c	2002-08-01 06:42:40.000000000 +0000
@@ -15,6 +15,7 @@
  * All initialization functions provided here are intended to be called
  * from machine specific code with proper arguments when required.
  */
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
@@ -22,57 +23,80 @@
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
 #include <linux/errno.h>
+#include <linux/ioport.h>
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/arch/irq.h>
 
+#include <asm/hardware/sa1111.h>
+
 #include "sa1111.h"
 
+struct resource sa1111_resource = {
+	name:	"SA1111",
+};
+
+EXPORT_SYMBOL(sa1111_resource);
+
 /*
- * SA1111  Interrupt support
+ * SA1111 interrupt support
  */
-
-void sa1111_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs )
+void sa1111_IRQ_demux(int irq, void *dev_id, struct pt_regs *regs)
 {
-	int i;
 	unsigned long stat0, stat1;
 
-	for(;;) {
-		stat0 = INTSTATCLR0, stat1 = INTSTATCLR1;
-		if( !stat0 && !stat1 ) break;
-		if( stat0 )
-			for( i = 0; i < 32; i++ )
-				if( stat0 & (1<<i) )
-					do_IRQ( SA1111_IRQ(i), regs );
-
-		if( stat1 )
-			for( i = 32; i < 55; i++ )
-				if( stat1 & (1<<(i-32)) )
-					do_IRQ( SA1111_IRQ(i), regs );
+	while (1) {
+		int i;
+
+		stat0 = INTSTATCLR0;
+		stat1 = INTSTATCLR1;
+
+		if (stat0 == 0 && stat1 == 0)
+			break;
+
+		for (i = IRQ_SA1111_START; stat0; i++, stat0 >>= 1)
+			if (stat0 & 1)
+				do_IRQ(i, regs);
+
+		for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1)
+			if (stat1 & 1)
+				do_IRQ(i, regs);
 	}
 }
 
-static struct irqaction sa1111_irq = {
-	name:		"SA1111",
-	handler:	sa1111_IRQ_demux,
-	flags:		SA_INTERRUPT
-};
+#define SA1111_IRQMASK_LO(x)	(1 << (x - IRQ_SA1111_START))
+#define SA1111_IRQMASK_HI(x)	(1 << (x - IRQ_SA1111_START - 32))
 
+/*
+ * A note about masking IRQs:
+ *
+ * The GPIO IRQ edge detection only functions while the IRQ itself is
+ * enabled; edges are not detected while the IRQ is disabled.
+ *
+ * This is especially important for the PCMCIA signals, where we must
+ * pick up every transition.  We therefore do not disable the IRQs
+ * while processing them.
+ *
+ * However, since we are changed to a GPIO on the host processor,
+ * all SA1111 IRQs will be disabled while we're processing any SA1111
+ * IRQ.
+ *
+ * Note also that changing INTPOL while an IRQ is enabled will itself
+ * trigger an IRQ.
+ */
 static void sa1111_mask_and_ack_lowirq(unsigned int irq)
 {
-	unsigned int mask = 1 << (irq - SA1111_IRQ(0));
+	unsigned int mask = SA1111_IRQMASK_LO(irq);
 
-	// broken hardware: interrupt events are lost if they occur
-	// while the interrupts are disabled.
 	//INTEN0 &= ~mask;
 	INTSTATCLR0 = mask;
 }
 
 static void sa1111_mask_and_ack_highirq(unsigned int irq)
 {
-	unsigned int mask = 1 << (irq - SA1111_IRQ(32));
+	unsigned int mask = SA1111_IRQMASK_HI(irq);
 
 	//INTEN1 &= ~mask;
 	INTSTATCLR1 = mask;
@@ -80,27 +104,29 @@
 
 static void sa1111_mask_lowirq(unsigned int irq)
 {
-	//INTEN0 &= ~(1 << (irq - SA1111_IRQ(0)));
+	INTEN0 &= ~SA1111_IRQMASK_LO(irq);
 }
 
 static void sa1111_mask_highirq(unsigned int irq)
 {
-	//INTEN1 &= ~(1 << (irq - SA1111_IRQ(32)));
+	INTEN1 &= ~SA1111_IRQMASK_HI(irq);
 }
 
 static void sa1111_unmask_lowirq(unsigned int irq)
 {
-	INTEN0 |= 1 << (irq - SA1111_IRQ(0));
+	INTEN0 |= SA1111_IRQMASK_LO(irq);
 }
 
 static void sa1111_unmask_highirq(unsigned int irq)
 {
-	INTEN1 |= 1 << ((irq - SA1111_IRQ(32)));
+	INTEN1 |= SA1111_IRQMASK_HI(irq);
 }
 
 void __init sa1111_init_irq(int irq_nr)
 {
-	int irq;
+	int irq, ret;
+
+	request_mem_region(_INTTEST0, 512, "irqs");
 
 	/* disable all IRQs */
 	INTEN0 = 0;
@@ -111,21 +137,21 @@
 	 * specifies that S0ReadyInt and S1ReadyInt should be '1'.
 	 */
 	INTPOL0 = 0;
-	INTPOL1 = 1 << (S0_READY_NINT - SA1111_IRQ(32)) |
-		  1 << (S1_READY_NINT - SA1111_IRQ(32));
+	INTPOL1 = SA1111_IRQMASK_HI(S0_READY_NINT) |
+		  SA1111_IRQMASK_HI(S1_READY_NINT);
 
 	/* clear all IRQs */
 	INTSTATCLR0 = -1;
 	INTSTATCLR1 = -1;
 
-	for (irq = SA1111_IRQ(0); irq <= SA1111_IRQ(26); irq++) {
+	for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
 		irq_desc[irq].valid	= 1;
 		irq_desc[irq].probe_ok	= 0;
 		irq_desc[irq].mask_ack	= sa1111_mask_and_ack_lowirq;
 		irq_desc[irq].mask	= sa1111_mask_lowirq;
 		irq_desc[irq].unmask	= sa1111_unmask_lowirq;
 	}
-	for (irq = SA1111_IRQ(32); irq <= SA1111_IRQ(54); irq++) {
+	for (irq = AUDXMTDMADONEA; irq <= S1_BVD1_STSCHG; irq++) {
 		irq_desc[irq].valid	= 1;
 		irq_desc[irq].probe_ok	= 0;
 		irq_desc[irq].mask_ack	= sa1111_mask_and_ack_highirq;
@@ -134,28 +160,60 @@
 	}
 
 	/* Register SA1111 interrupt */
-	if (irq_nr >= 0)
-		setup_arm_irq(irq_nr, &sa1111_irq);
+	if (irq_nr < 0)
+		return;
+
+	ret = request_irq(irq_nr, sa1111_IRQ_demux, SA_INTERRUPT,
+			  "SA1111", NULL);
+	if (ret < 0)
+		printk(KERN_ERR "SA1111: unable to claim IRQ%d: %d\n",
+		       irq_nr, ret);
 }
 
-/*
- * Probe for a SA1111 chip.
+/**
+ *	sa1111_probe - probe for a single SA1111 chip.
+ *	@phys_addr: physical address of device.
+ *
+ *	Probe for a SA1111 chip.  This must be called
+ *	before any other SA1111-specific code.
+ *
+ *	Returns:
+ *	%-ENODEV	device not found.
+ *	%-EBUSY		physical address already marked in-use.
+ *	%0		successful.
  */
-
-int __init sa1111_probe(void)
+int __init sa1111_probe(unsigned long phys_addr)
 {
-	unsigned long id = SBI_SKID;
+	unsigned long id;
 	int ret = -ENODEV;
 
-	if ((id & SKID_ID_MASK) == SKID_SA1111_ID) {
-		printk(KERN_INFO "SA-1111 Microprocessor Companion Chip: "
-			"silicon revision %lx, metal revision %lx\n",
-			(id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK));
-		ret = 0;
-	} else {
-		printk(KERN_DEBUG "SA-1111 not detected: ID = %08lx\n", id);
+	sa1111_resource.start = phys_addr;
+	sa1111_resource.end = phys_addr + 0x2000;
+
+	if (request_resource(&iomem_resource, &sa1111_resource)) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	/*
+	 * Probe for the chip.  Only touch the SBI registers.
+	 */
+	id = SBI_SKID;
+	if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
+		printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
+		ret = -ENODEV;
+		goto release;
 	}
 
+	printk(KERN_INFO "SA1111 Microprocessor Companion Chip: "
+		"silicon revision %lx, metal revision %lx\n",
+		(id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK));
+
+	return 0;
+
+ release:
+	release_resource(&sa1111_resource);
+ out:
 	return ret;
 }
 
@@ -175,6 +233,10 @@
  */
 void sa1111_wake(void)
 {
+	unsigned long flags;
+
+	local_irq_save(flags);
+
 	/*
 	 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
 	 * (SA-1110 Developer's Manual, section 9.1.2.1)
@@ -210,6 +272,8 @@
 	 * Ensure all clocks are initially off.
 	 */
 	SKPCR = 0;
+
+	local_irq_restore(flags);
 }
 
 void sa1111_doze(void)
@@ -242,12 +306,17 @@
  */
 void __init sa1110_mb_disable(void)
 {
+	unsigned long flags;
+
+	local_irq_save(flags);
+	
 	PGSR &= ~GPIO_MBGNT;
 	GPCR = GPIO_MBGNT;
 	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 
 	GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
 
+	local_irq_restore(flags);
 }
 
 /*
@@ -256,10 +325,19 @@
  */
 void __init sa1110_mb_enable(void)
 {
+	unsigned long flags;
+
+	local_irq_save(flags);
+
 	PGSR &= ~GPIO_MBGNT;
 	GPCR = GPIO_MBGNT;
 	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 
 	GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
 	TUCR |= TUCR_MR;
+
+	local_irq_restore(flags);
 }
+
+EXPORT_SYMBOL(sa1111_wake);
+EXPORT_SYMBOL(sa1111_doze);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/sa1111.h linux/arch/arm/mach-sa1100/sa1111.h
--- linux.orig/arch/arm/mach-sa1100/sa1111.h	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/sa1111.h	2002-08-01 06:42:44.000000000 +0000
@@ -11,7 +11,7 @@
 /*
  * Probe for a SA1111 chip.
  */
-extern int sa1111_probe(void);
+extern int sa1111_probe(unsigned long phys);
 
 /*
  * Wake up a SA1111 chip.
@@ -30,5 +30,5 @@
 
 
 extern void sa1111_init_irq(int irq_nr);
-extern void sa1111_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs );
+extern void sa1111_IRQ_demux(int irq, void *dev_id, struct pt_regs *regs);
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/shannon.c linux/arch/arm/mach-sa1100/shannon.c
--- linux.orig/arch/arm/mach-sa1100/shannon.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-sa1100/shannon.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * linux/arch/arm/mach-sa1100/shannon.c
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/tty.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include "generic.h"
+
+
+static struct map_desc shannon_io_desc[] __initdata = {
+ /* virtual     physical    length      domain     r  w  c  b */
+  { 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash memory */
+  LAST_DESC
+};
+
+static void __init shannon_map_io(void)
+{
+	sa1100_map_io();
+	iotable_init(shannon_io_desc);
+
+	sa1100_register_uart(0, 3);
+	sa1100_register_uart(1, 1);
+	Ser1SDCR0 |= SDCR0_SUS;
+	GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
+	GPDR |= GPIO_UART_TXD;
+	GPDR &= ~GPIO_UART_RXD;
+	PPAR |= PPAR_UPR;
+
+	set_GPIO_IRQ_edge(SHANNON_GPIO_IRQ_CODEC);
+}
+
+MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	BOOT_PARAMS(0xc0000100)
+	MAPIO(shannon_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/sherman.c linux/arch/arm/mach-sa1100/sherman.c
--- linux.orig/arch/arm/mach-sa1100/sherman.c	2001-08-13 00:36:24.000000000 +0000
+++ linux/arch/arm/mach-sa1100/sherman.c	2002-08-01 06:42:28.000000000 +0000
@@ -31,7 +31,7 @@
 
 static struct map_desc sherman_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash*/
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash*/
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/simpad.c linux/arch/arm/mach-sa1100/simpad.c
--- linux.orig/arch/arm/mach-sa1100/simpad.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mach-sa1100/simpad.c	2002-08-01 06:42:31.000000000 +0000
@@ -23,18 +23,6 @@
 
 long cs3_shadow;
 
-static int __init simpad_init(void)
-{
-	PSPR = 0xc0008000;
-	GPDR &= ~GPIO_GPIO0;
-	cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON | 
-		      ENABLE_5V | RESET_SIMCARD);
-	*(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
-	return 0;
-}
-
-__initcall(simpad_init);
-
 long get_cs3_shadow()
 {
 	return cs3_shadow;
@@ -70,8 +58,8 @@
 
 static struct map_desc simpad_io_desc[] __initdata = {
   /* virtual	physical    length	domain	   r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, 
-  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */  
+  { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, 
+  { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */  
   { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */
   LAST_DESC
 };
@@ -96,11 +84,17 @@
 	sa1100_map_io();
 	iotable_init(simpad_io_desc);
 
-#ifndef CONFIG_SERIAL_SA1100_OLD
+	PSPR = 0xc0008000;
+	GPDR &= ~GPIO_GPIO0;
+	cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON | 
+		      ENABLE_5V | RESET_SIMCARD);
+	*(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
+
 	//It is only possible to register 3 UART in serial_sa1100.c
 	sa1100_register_uart(0, 3);
 	sa1100_register_uart(1, 1);
-#endif
+
+	set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ, GPIO_RISING_EDGE);
 }
 
 #ifdef CONFIG_PROC_FS
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/system3.c linux/arch/arm/mach-sa1100/system3.c
--- linux.orig/arch/arm/mach-sa1100/system3.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mach-sa1100/system3.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,379 @@
+/*
+ * linux/arch/arm/mach-sa1100/system3.c
+ *
+ * Copyright (C) 2001 Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
+ *
+ * $Id: system3.c,v 1.1.6.1 2001/12/04 17:28:06 seletz Exp $
+ *
+ * This file contains all PT Sytsem 3 tweaks. Based on original work from
+ * Nicolas Pitre's assabet fixes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Log: system3.c,v $
+ * Revision 1.1.6.1  2001/12/04 17:28:06  seletz
+ * - merged from previous branch
+ *
+ * Revision 1.1.4.3  2001/12/04 15:16:31  seletz
+ * - merged from linux_2_4_13_ac5_rmk2
+ *
+ * Revision 1.1.4.2  2001/11/19 17:18:57  seletz
+ * - more code cleanups
+ *
+ * Revision 1.1.4.1  2001/11/16 13:52:05  seletz
+ * - PT Digital Board Support Code
+ *
+ * Revision 1.1.2.2  2001/11/05 16:46:18  seletz
+ * - cleanups
+ *
+ * Revision 1.1.2.1  2001/10/15 16:00:43  seletz
+ * - first revision working with new board
+ *
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include <asm/arch/irq.h>
+
+#include <linux/serial_core.h>
+
+#include "generic.h"
+#include "sa1111.h"
+
+#define DEBUG 1
+
+#ifdef DEBUG
+#	define DPRINTK( x, args... )	printk( "%s: line %d: "x, __FUNCTION__, __LINE__, ## args  );
+#else
+#	define DPRINTK( x, args... )	/* nix */
+#endif
+
+/**********************************************************************
+ *  prototypes
+ */
+
+/* init funcs */
+static void __init fixup_system3(struct machine_desc *desc,
+		struct param_struct *params, char **cmdline, struct meminfo *mi);
+static void __init get_system3_scr(void);
+static int __init system3_init(void);
+static void __init system3_init_irq(void);
+static void __init system3_map_io(void);
+
+static void system3_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs );
+static int system3_get_mctrl(struct uart_port *port);
+static void system3_set_mctrl(struct uart_port *port, u_int mctrl);
+static void system3_uart_pm(struct uart_port *port, u_int state, u_int oldstate);
+static int sdram_notifier(struct notifier_block *nb, unsigned long event, void *data);
+
+extern void convert_to_tag_list(struct param_struct *params, int mem_init);
+
+
+/**********************************************************************
+ *  global data
+ */
+
+/**********************************************************************
+ *  static data
+ */
+
+static struct map_desc system3_io_desc[] __initdata = {
+ /* virtual     physical    length      domain     r  w  c  b */
+  { 0xe8000000, 0x00000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
+  { 0xf3000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
+  { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
+  LAST_DESC
+};
+
+static struct sa1100_port_fns system3_port_fns __initdata = {
+	set_mctrl:	system3_set_mctrl,
+	get_mctrl:	system3_get_mctrl,
+	pm:		system3_uart_pm,
+};
+
+static struct irqaction system3_irq = {
+	name:		"PT Digital Board SA1111 IRQ",
+	handler:	system3_IRQ_demux,
+	flags:		SA_INTERRUPT
+};
+
+static struct notifier_block system3_clkchg_block = {
+	notifier_call:	sdram_notifier,
+};
+
+/**********************************************************************
+ *  Static functions
+ */
+
+static void __init system3_map_io(void)
+{
+	DPRINTK( "%s\n", "START" );
+	sa1100_map_io();
+	iotable_init(system3_io_desc);
+
+	sa1100_register_uart_fns(&system3_port_fns);
+	sa1100_register_uart(0, 1);	/* com port */
+	sa1100_register_uart(1, 2);
+	sa1100_register_uart(2, 3);	/* radio module */
+
+	Ser1SDCR0 |= SDCR0_SUS;
+}
+
+
+/*********************************************************************
+ * Install IRQ handler
+ */
+static void system3_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs )
+{
+	u_char irr;
+
+	for(;;){
+		//irr = PTCPLD_REG_IRQSR & (PT_IRQ_LAN | PT_IRQ_USAR | PT_IRQ_SA1111);
+		irr = PT_IRQSR & (PT_IRQ_LAN | PT_IRQ_SA1111);
+
+		irr ^= (PT_IRQ_LAN);
+		if (!irr) break;
+
+		if( irr & PT_IRQ_LAN )
+			do_IRQ(IRQ_SYSTEM3_SMC9196, regs);
+
+#if 0
+		/* Highspeed Serial Bus not yet used */
+		if( irr & PT_IRQ_USAR )
+			do_IRQ(PT_USAR_IRQ, regs);
+#endif
+
+		if( irr & PT_IRQ_SA1111 )
+			sa1111_IRQ_demux(irq, dev_id, regs);
+	}
+}
+
+
+static void __init system3_init_irq(void)
+{
+	int irq;
+
+	DPRINTK( "%s\n", "START" );
+
+	/* SA1111 IRQ not routed to a GPIO. */
+	sa1111_init_irq(-1);
+
+	/* setup extra IRQs */
+	irq = IRQ_SYSTEM3_SMC9196;
+	irq_desc[irq].valid	= 1;
+	irq_desc[irq].probe_ok	= 1;
+
+#if 0
+	/* Highspeed Serial Bus not yet used */
+	irq = PT_USAR_IRQ;
+	irq_desc[irq].valid	= 1;
+	irq_desc[irq].probe_ok	= 1;
+#endif
+
+	/* IRQ by CPLD */
+	set_GPIO_IRQ_edge( GPIO_GPIO(25), GPIO_RISING_EDGE );
+	setup_arm_irq( IRQ_GPIO25, &system3_irq );
+}
+
+/**********************************************************************
+ * On system 3 limit cpu frequency to 206 Mhz
+ */
+static int sdram_notifier(struct notifier_block *nb, unsigned long event,
+		void *data)
+{
+	switch (event) {
+		case CPUFREQ_MINMAX:
+			cpufreq_updateminmax(data, 147500, 206000);
+			break;
+
+	}
+	return 0;
+}
+
+/**
+ *	fixup_system3 - fixup function for system 3 board
+ *	@desc:		machine description
+ *	@param:		kernel params
+ *	@cmdline:	kernel cmdline
+ *	@mi:		memory info struct
+ *
+ */
+static void __init fixup_system3(struct machine_desc *desc,
+		struct param_struct *params, char **cmdline, struct meminfo *mi)
+{
+	DPRINTK( "%s\n", "START" );
+
+	ROOT_DEV = MKDEV(RAMDISK_MAJOR,0);
+	setup_ramdisk( 1, 0, 0, 8192 );
+	setup_initrd( 0xc0800000, 8*1024*1024 );
+}
+
+
+/**
+ *	system3_uart_pm - powermgmt callback function for system 3 UART
+ *	@port: uart port structure
+ *	@state: pm state
+ *	@oldstate: old pm state
+ *
+ */
+static void system3_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+	/* TODO: switch on/off uart in powersave mode */
+}
+
+/*
+ * Note! this can be called from IRQ context.
+ * FIXME: Handle PT Digital Board CTRL regs irq-safe.
+ *
+ * NB: system3 uses COM_RTS and COM_DTR for both UART1 (com port)
+ * and UART3 (radio module).  We only handle them for UART1 here.
+ */
+static void system3_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+	if (port->mapbase == _Ser1UTCR0) {
+		u_int set = 0, clear = 0;
+
+		if (mctrl & TIOCM_RTS)
+			set |= PT_CTRL2_RS1_RTS;
+		else
+			clear |= PT_CTRL2_RS1_RTS;
+
+		if (mctrl & TIOCM_DTR)
+			set |= PT_CTRL2_RS1_DTR;
+		else
+			clear |= PT_CTRL2_RS1_DTR;
+
+		PTCTRL2_clear(clear);
+		PTCTRL2_set(set);
+	}
+}
+
+static int system3_get_mctrl(struct uart_port *port)
+{
+	u_int ret = 0;
+	u_int irqsr = PT_IRQSR;
+
+	/* need 2 reads to read current value */
+	irqsr = PT_IRQSR;
+
+	/* TODO: check IRQ source register for modem/com
+	 status lines and set them correctly. */
+
+	ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
+
+	return ret;
+}
+
+static int __init system3_init(void)
+{
+	int ret = 0;
+	DPRINTK( "%s\n", "START" );
+
+	if ( !machine_is_pt_system3() ) {
+		ret = -EINVAL;
+		goto DONE;
+	}
+
+	/* init control register */
+	PT_CTRL0 = PT_CTRL0_INIT;
+	PT_CTRL1 = 0x02;
+	PT_CTRL2 = 0x00;
+	DPRINTK( "CTRL[0]=0x%02x\n", PT_CTRL0 );
+	DPRINTK( "CTRL[1]=0x%02x\n", PT_CTRL1 );
+	DPRINTK( "CTRL[2]=0x%02x\n", PT_CTRL2 );
+
+	/*
+	 * Ensure that the memory bus request/grant signals are setup,
+	 * and the grant is held in its inactive state.
+	 */
+	sa1110_mb_disable();
+
+	/*
+	 * Probe for a SA1111.
+	 */
+	ret = sa1111_probe(PT_SA1111_BASE);
+	if (ret < 0) {
+		printk( KERN_WARNING"PT Digital Board: no SA1111 found!\n" );
+		goto DONE;
+	}
+
+	/*
+	 * We found it.  Wake the chip up.
+	 */
+	sa1111_wake();
+
+	/*
+	 * The SDRAM configuration of the SA1110 and the SA1111 must
+	 * match.  This is very important to ensure that SA1111 accesses
+	 * don't corrupt the SDRAM.  Note that this ungates the SA1111's
+	 * MBGNT signal, so we must have called sa1110_mb_disable()
+	 * beforehand.
+	 */
+	sa1111_configure_smc(1,
+			     FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
+			     FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
+
+	/*
+	 * We only need to turn on DCLK whenever we want to use the
+	 * DMA.  It can otherwise be held firmly in the off position.
+	 */
+	SKPCR |= SKPCR_DCLKEN;
+
+	/*
+	 * Enable the SA1110 memory bus request and grant signals.
+	 */
+	sa1110_mb_enable();
+
+	system3_init_irq();
+
+#if defined( CONFIG_CPU_FREQ )
+	ret = cpufreq_register_notifier(&system3_clkchg_block);
+	if ( ret != 0 ) {
+		printk( KERN_WARNING"PT Digital Board: could not register clock scale callback\n" );
+		goto DONE;
+	}
+#endif
+
+	ret = 0;
+DONE:
+	DPRINTK( "ret=%d\n", ret );
+	return ret;
+}
+
+/**********************************************************************
+ *  Exported Functions
+ */
+
+/**********************************************************************
+ *  kernel magic macros
+ */
+__initcall(system3_init);
+
+MACHINE_START(PT_SYSTEM3, "PT System 3")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	BOOT_PARAMS(0xc0000100)
+	FIXUP(fixup_system3)
+	MAPIO(system3_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/victor.c linux/arch/arm/mach-sa1100/victor.c
--- linux.orig/arch/arm/mach-sa1100/victor.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/victor.c	2002-08-01 06:42:29.000000000 +0000
@@ -60,7 +60,7 @@
 
 static struct map_desc victor_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x00200000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash */
+  { 0xe8000000, 0x00000000, 0x00200000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/xp860.c linux/arch/arm/mach-sa1100/xp860.c
--- linux.orig/arch/arm/mach-sa1100/xp860.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mach-sa1100/xp860.c	2002-08-01 06:42:44.000000000 +0000
@@ -21,6 +21,7 @@
 
 static void xp860_power_off(void)
 {
+	cli();
 	GPDR |= GPIO_GPIO20;
 	GPSR = GPIO_GPIO20;
 	mdelay(1000);
@@ -40,7 +41,7 @@
 	/*
 	 * Probe for SA1111.
 	 */
-	ret = sa1111_probe();
+	ret = sa1111_probe(0x40000000);
 	if (ret < 0)
 		return ret;
 
@@ -65,9 +66,9 @@
 
 static struct map_desc xp860_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xf0000000, 0x10000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* SCSI */
-  { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* LAN */
-  { 0xf4000000, 0x40000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */
+  { 0xf0000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SCSI */
+  { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN */
+  { 0xf4000000, 0x40000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
   LAST_DESC
 };
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mach-sa1100/yopy.c linux/arch/arm/mach-sa1100/yopy.c
--- linux.orig/arch/arm/mach-sa1100/yopy.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/mach-sa1100/yopy.c	2002-08-01 06:42:32.000000000 +0000
@@ -1,8 +1,6 @@
 /*
  * linux/arch/arm/mach-sa1100/yopy.c
  */
-
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -52,14 +50,16 @@
 
 static int __init yopy_hw_init(void)
 {
-	YOPY_EGPIO = yopy_egpio;
+	if (machine_is_yopy()) {
+		YOPY_EGPIO = yopy_egpio;
 
-	/* Enable Output */
-	PPDR |= PPC_L_BIAS;
-	PSDR &= ~PPC_L_BIAS;
-	PPSR |= PPC_L_BIAS;
+		/* Enable Output */
+		PPDR |= PPC_L_BIAS;
+		PSDR &= ~PPC_L_BIAS;
+		PPSR |= PPC_L_BIAS;
 
-	YOPY_EGPIO = yopy_egpio;
+		YOPY_EGPIO = yopy_egpio;
+	}
 
 	return 0;
 }
@@ -69,9 +69,9 @@
 
 static struct map_desc yopy_io_desc[] __initdata = {
  /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash 0 */
-  { 0xec000000, 0x08000000, 0x04000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash 1 */
-  { 0xf0000000, 0x48000000, 0x00300000, DOMAIN_IO, 1, 1, 0, 0 }, /* LCD */
+  { 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash 0 */
+  { 0xec000000, 0x08000000, 0x04000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash 1 */
+  { 0xf0000000, 0x48000000, 0x00300000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD */
   { 0xf1000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO */
   LAST_DESC
 };
@@ -82,6 +82,8 @@
 	iotable_init(yopy_io_desc);
 
 	sa1100_register_uart(0, 3);
+
+	set_GPIO_IRQ_edge(GPIO_UCB1200_IRQ, GPIO_RISING_EDGE);
 }
 
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/Makefile linux/arch/arm/mm/Makefile
--- linux.orig/arch/arm/mm/Makefile	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/arm/mm/Makefile	2002-08-01 06:42:45.000000000 +0000
@@ -13,19 +13,20 @@
 
 # Object file lists.
 
-obj-y		:= init.o
+obj-y		:= init.o extable.o fault-common.o
 obj-m		:=
 obj-n		:=
 obj-		:=
 export-objs	:= proc-syms.o discontig.o
 
-cpu32-y		:= consistent.o fault-armv.o ioremap.o mm-armv.o
-cpu32-$(CONFIG_MODULES) += proc-syms.o
+ifeq ($(CONFIG_CPU_32),y)
+obj-y		+= consistent.o fault-armv.o ioremap.o mm-armv.o
+obj-$(CONFIG_MODULES) += proc-syms.o
+endif
 
-obj-y		+= extable.o fault-common.o
 obj-$(CONFIG_CPU_26) += fault-armo.o mm-armo.o small_page.o
-obj-$(CONFIG_CPU_32) += $(cpu32-y)
 
+obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
 obj-$(CONFIG_DISCONTIGMEM) += discontig.o
 
 # Select the processor-specific files
@@ -34,6 +35,7 @@
 p-$(CONFIG_CPU_ARM710)	+= proc-arm6,7.o
 p-$(CONFIG_CPU_ARM720T)	+= proc-arm720.o
 p-$(CONFIG_CPU_ARM920T)	+= proc-arm920.o
+p-$(CONFIG_CPU_ARM922T)	+= proc-arm922.o
 p-$(CONFIG_CPU_ARM926T)	+= proc-arm926.o
 p-$(CONFIG_CPU_ARM1020)	+= proc-arm1020.o
 p-$(CONFIG_CPU_SA110)	+= proc-sa110.o
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/alignment.c linux/arch/arm/mm/alignment.c
--- linux.orig/arch/arm/mm/alignment.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mm/alignment.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,609 @@
+/*
+ *  linux/arch/arm/mm/alignment.c
+ *
+ *  Copyright (C) 1995  Linus Torvalds
+ *  Modifications for ARM processor (c) 1995-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/bitops.h>
+#include <linux/init.h>
+
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
+#include <asm/unaligned.h>
+
+extern void
+do_bad_area(struct task_struct *tsk, struct mm_struct *mm, unsigned long addr,
+	    int error_code, struct pt_regs *regs);
+
+/*
+ * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
+ * /proc/sys/debug/alignment, modified and integrated into
+ * Linux 2.1 by Russell King
+ *
+ * Speed optimisations and better fault handling by Russell King.
+ *
+ * *** NOTE ***
+ * This code is not portable to processors with late data abort handling.
+ */
+#define CODING_BITS(i)	(i & 0x0e000000)
+
+#define LDST_I_BIT(i)	(i & (1 << 26))		/* Immediate constant	*/
+#define LDST_P_BIT(i)	(i & (1 << 24))		/* Preindex		*/
+#define LDST_U_BIT(i)	(i & (1 << 23))		/* Add offset		*/
+#define LDST_W_BIT(i)	(i & (1 << 21))		/* Writeback		*/
+#define LDST_L_BIT(i)	(i & (1 << 20))		/* Load			*/
+
+#define LDST_P_EQ_U(i)	((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
+
+#define LDSTH_I_BIT(i)	(i & (1 << 22))		/* half-word immed	*/
+#define LDM_S_BIT(i)	(i & (1 << 22))		/* write CPSR from SPSR	*/
+
+#define RN_BITS(i)	((i >> 16) & 15)	/* Rn			*/
+#define RD_BITS(i)	((i >> 12) & 15)	/* Rd			*/
+#define RM_BITS(i)	(i & 15)		/* Rm			*/
+
+#define REGMASK_BITS(i)	(i & 0xffff)
+#define OFFSET_BITS(i)	(i & 0x0fff)
+
+#define IS_SHIFT(i)	(i & 0x0ff0)
+#define SHIFT_BITS(i)	((i >> 7) & 0x1f)
+#define SHIFT_TYPE(i)	(i & 0x60)
+#define SHIFT_LSL	0x00
+#define SHIFT_LSR	0x20
+#define SHIFT_ASR	0x40
+#define SHIFT_RORRRX	0x60
+
+static unsigned long ai_user;
+static unsigned long ai_sys;
+static unsigned long ai_skipped;
+static unsigned long ai_half;
+static unsigned long ai_word;
+static unsigned long ai_multi;
+static int ai_usermode;
+
+#ifdef CONFIG_PROC_FS
+static const char *usermode_action[] = {
+	"ignored",
+	"warn",
+	"fixup",
+	"fixup+warn",
+	"signal",
+	"signal+warn"
+};
+
+static int
+proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
+		    void *data)
+{
+	char *p = page;
+	int len;
+
+	p += sprintf(p, "User:\t\t%lu\n", ai_user);
+	p += sprintf(p, "System:\t\t%lu\n", ai_sys);
+	p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
+	p += sprintf(p, "Half:\t\t%lu\n", ai_half);
+	p += sprintf(p, "Word:\t\t%lu\n", ai_word);
+	p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
+	p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
+			usermode_action[ai_usermode]);
+
+	len = (p - page) - off;
+	if (len < 0)
+		len = 0;
+
+	*eof = (len <= count) ? 1 : 0;
+	*start = page + off;
+
+	return len;
+}
+
+static int proc_alignment_write(struct file *file, const char *buffer,
+			       unsigned long count, void *data)
+{
+	int mode;
+
+	if (count > 0) {
+		if (get_user(mode, buffer))
+			return -EFAULT;
+		if (mode >= '0' && mode <= '5')
+			   ai_usermode = mode - '0';
+	}
+	return count;
+}
+
+/*
+ * This needs to be done after sysctl_init, otherwise sys/ will be
+ * overwritten.  Actually, this shouldn't be in sys/ at all since
+ * it isn't a sysctl, and it doesn't contain sysctl information.
+ * We now locate it in /proc/cpu/alignment instead.
+ */
+static int __init alignment_init(void)
+{
+	struct proc_dir_entry *res;
+
+	res = proc_mkdir("cpu", NULL);
+	if (!res)
+		return -ENOMEM;
+
+	res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
+	if (!res)
+		return -ENOMEM;
+
+	res->read_proc = proc_alignment_read;
+	res->write_proc = proc_alignment_write;
+
+	return 0;
+}
+
+__initcall(alignment_init);
+#endif /* CONFIG_PROC_FS */
+
+union offset_union {
+	unsigned long un;
+	  signed long sn;
+};
+
+#define TYPE_ERROR	0
+#define TYPE_FAULT	1
+#define TYPE_LDST	2
+#define TYPE_DONE	3
+
+#define __get8_unaligned_check(ins,val,addr,err)	\
+	__asm__(					\
+	"1:	"ins"	%1, [%2], #1\n"			\
+	"2:\n"						\
+	"	.section .fixup,\"ax\"\n"		\
+	"	.align	2\n"				\
+	"3:	mov	%0, #1\n"			\
+	"	b	2b\n"				\
+	"	.previous\n"				\
+	"	.section __ex_table,\"a\"\n"		\
+	"	.align	3\n"				\
+	"	.long	1b, 3b\n"			\
+	"	.previous\n"				\
+	: "=r" (err), "=&r" (val), "=r" (addr)		\
+	: "0" (err), "2" (addr))
+
+#define __get16_unaligned_check(ins,val,addr)			\
+	do {							\
+		unsigned int err = 0, v, a = addr;		\
+		__get8_unaligned_check(ins,val,a,err);		\
+		__get8_unaligned_check(ins,v,a,err);		\
+		val |= v << 8;					\
+		if (err)					\
+			goto fault;				\
+	} while (0)
+
+#define get16_unaligned_check(val,addr) \
+	__get16_unaligned_check("ldrb",val,addr)
+
+#define get16t_unaligned_check(val,addr) \
+	__get16_unaligned_check("ldrbt",val,addr)
+
+#define __get32_unaligned_check(ins,val,addr)			\
+	do {							\
+		unsigned int err = 0, v, a = addr;		\
+		__get8_unaligned_check(ins,val,a,err);		\
+		__get8_unaligned_check(ins,v,a,err);		\
+		val |= v << 8;					\
+		__get8_unaligned_check(ins,v,a,err);		\
+		val |= v << 16;					\
+		__get8_unaligned_check(ins,v,a,err);		\
+		val |= v << 24;					\
+		if (err)					\
+			goto fault;				\
+	} while (0)
+
+#define get32_unaligned_check(val,addr) \
+	__get32_unaligned_check("ldrb",val,addr)
+
+#define get32t_unaligned_check(val,addr) \
+	__get32_unaligned_check("ldrbt",val,addr)
+
+#define __put16_unaligned_check(ins,val,addr)			\
+	do {							\
+		unsigned int err = 0, v = val, a = addr;	\
+		__asm__(					\
+		"1:	"ins"	%1, [%2], #1\n"			\
+		"	mov	%1, %1, lsr #8\n"		\
+		"2:	"ins"	%1, [%2]\n"			\
+		"3:\n"						\
+		"	.section .fixup,\"ax\"\n"		\
+		"	.align	2\n"				\
+		"4:	mov	%0, #1\n"			\
+		"	b	3b\n"				\
+		"	.previous\n"				\
+		"	.section __ex_table,\"a\"\n"		\
+		"	.align	3\n"				\
+		"	.long	1b, 4b\n"			\
+		"	.long	2b, 4b\n"			\
+		"	.previous\n"				\
+		: "=r" (err), "=&r" (v), "=&r" (a)		\
+		: "0" (err), "1" (v), "2" (a));			\
+		if (err)					\
+			goto fault;				\
+	} while (0)
+
+#define put16_unaligned_check(val,addr)  \
+	__put16_unaligned_check("strb",val,addr)
+
+#define put16t_unaligned_check(val,addr) \
+	__put16_unaligned_check("strbt",val,addr)
+
+#define __put32_unaligned_check(ins,val,addr)			\
+	do {							\
+		unsigned int err = 0, v = val, a = addr;	\
+		__asm__(					\
+		"1:	"ins"	%1, [%2], #1\n"			\
+		"	mov	%1, %1, lsr #8\n"		\
+		"2:	"ins"	%1, [%2], #1\n"			\
+		"	mov	%1, %1, lsr #8\n"		\
+		"3:	"ins"	%1, [%2], #1\n"			\
+		"	mov	%1, %1, lsr #8\n"		\
+		"4:	"ins"	%1, [%2]\n"			\
+		"5:\n"						\
+		"	.section .fixup,\"ax\"\n"		\
+		"	.align	2\n"				\
+		"6:	mov	%0, #1\n"			\
+		"	b	5b\n"				\
+		"	.previous\n"				\
+		"	.section __ex_table,\"a\"\n"		\
+		"	.align	3\n"				\
+		"	.long	1b, 6b\n"			\
+		"	.long	2b, 6b\n"			\
+		"	.long	3b, 6b\n"			\
+		"	.long	4b, 6b\n"			\
+		"	.previous\n"				\
+		: "=r" (err), "=&r" (v), "=&r" (a)		\
+		: "0" (err), "1" (v), "2" (a));			\
+		if (err)					\
+			goto fault;				\
+	} while (0)
+
+#define put32_unaligned_check(val,addr)	 \
+	__put32_unaligned_check("strb", val, addr)
+
+#define put32t_unaligned_check(val,addr) \
+	__put32_unaligned_check("strbt", val, addr)
+
+static void
+do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
+{
+	if (!LDST_U_BIT(instr))
+		offset.un = -offset.un;
+
+	if (!LDST_P_BIT(instr))
+		addr += offset.un;
+
+	if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
+		regs->uregs[RN_BITS(instr)] = addr;
+}
+
+static int
+do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
+{
+	unsigned int rd = RD_BITS(instr);
+
+	if ((instr & 0x01f00ff0) == 0x01000090)
+		goto swp;
+
+	if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0)
+		goto bad;
+
+	ai_half += 1;
+
+	if (user_mode(regs))
+		goto user;
+
+	if (LDST_L_BIT(instr)) {
+		unsigned long val;
+		get16_unaligned_check(val, addr);
+
+		/* signed half-word? */
+		if (instr & 0x40)
+			val = (signed long)((signed short) val);
+
+		regs->uregs[rd] = val;
+	} else
+		put16_unaligned_check(regs->uregs[rd], addr);
+
+	return TYPE_LDST;
+
+ user:
+ 	if (LDST_L_BIT(instr)) {
+ 		unsigned long val;
+ 		get16t_unaligned_check(val, addr);
+
+ 		/* signed half-word? */
+ 		if (instr & 0x40)
+ 			val = (signed long)((signed short) val);
+
+ 		regs->uregs[rd] = val;
+ 	} else
+ 		put16t_unaligned_check(regs->uregs[rd], addr);
+
+ 	return TYPE_LDST;
+
+ swp:
+	printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
+ bad:
+	return TYPE_ERROR;
+
+ fault:
+	return TYPE_FAULT;
+}
+
+static int
+do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
+{
+	unsigned int rd = RD_BITS(instr);
+
+	ai_word += 1;
+
+	if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
+		goto trans;
+
+	if (LDST_L_BIT(instr)) {
+		unsigned int val;
+		get32_unaligned_check(val, addr);
+		regs->uregs[rd] = val;
+	} else
+		put32_unaligned_check(regs->uregs[rd], addr);
+	return TYPE_LDST;
+
+ trans:
+	if (LDST_L_BIT(instr)) {
+		unsigned int val;
+		get32t_unaligned_check(val, addr);
+		regs->uregs[rd] = val;
+	} else
+		put32t_unaligned_check(regs->uregs[rd], addr);
+	return TYPE_LDST;
+
+ fault:
+	return TYPE_FAULT;
+}
+
+/*
+ * LDM/STM alignment handler.
+ *
+ * There are 4 variants of this instruction:
+ *
+ * B = rn pointer before instruction, A = rn pointer after instruction
+ *              ------ increasing address ----->
+ *	        |    | r0 | r1 | ... | rx |    |
+ * PU = 01             B                    A
+ * PU = 11        B                    A
+ * PU = 00        A                    B
+ * PU = 10             A                    B
+ */
+static int
+do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
+{
+	unsigned int rd, rn, correction, nr_regs, regbits;
+	unsigned long eaddr, newaddr;
+
+	if (LDM_S_BIT(instr))
+		goto bad;
+
+	correction = 4; /* processor implementation defined */
+	regs->ARM_pc += correction;
+
+	ai_multi += 1;
+
+	/* count the number of registers in the mask to be transferred */
+	nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
+
+	rn = RN_BITS(instr);
+	newaddr = eaddr = regs->uregs[rn];
+
+	if (!LDST_U_BIT(instr))
+		nr_regs = -nr_regs;
+	newaddr += nr_regs;
+	if (!LDST_U_BIT(instr))
+		eaddr = newaddr;
+
+	if (LDST_P_EQ_U(instr))	/* U = P */
+		eaddr += 4;
+
+	/* 
+	 * For alignment faults on the ARM922T the MMU  makes 
+	 * the FSR (and hence addr) equal to the updated base address
+	 * of the multiple access rather than the restored value.
+	 * Switch this messsage off if we've got a ARM922, otherwise
+	 * [ls]dm alignment faults are noisy!
+	 */
+#if !(defined CONFIG_CPU_ARM922T)  
+	/*
+	 * This is a "hint" - we already have eaddr worked out by the
+	 * processor for us.
+	 */
+	if (addr != eaddr) {
+		printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
+			"addr = %08lx, eaddr = %08lx\n",
+			 instruction_pointer(regs), instr, addr, eaddr);
+		show_regs(regs);
+	}
+#endif
+
+	if (user_mode(regs)) {
+		for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
+		     regbits >>= 1, rd += 1)
+			if (regbits & 1) {
+				if (LDST_L_BIT(instr)) {
+					unsigned int val;
+					get32t_unaligned_check(val, eaddr);
+					regs->uregs[rd] = val;
+				} else
+					put32t_unaligned_check(regs->uregs[rd], eaddr);
+				eaddr += 4;
+			}
+	} else {
+		for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
+		     regbits >>= 1, rd += 1)
+			if (regbits & 1) {
+				if (LDST_L_BIT(instr)) {
+					unsigned int val;
+					get32_unaligned_check(val, eaddr);
+					regs->uregs[rd] = val;
+				} else
+					put32_unaligned_check(regs->uregs[rd], eaddr);
+				eaddr += 4;
+			}
+	}
+
+	if (LDST_W_BIT(instr))
+		regs->uregs[rn] = newaddr;
+	if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
+		regs->ARM_pc -= correction;
+	return TYPE_DONE;
+
+fault:
+	regs->ARM_pc -= correction;
+	return TYPE_FAULT;
+
+bad:
+	printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
+	return TYPE_ERROR;
+}
+
+int do_alignment(unsigned long addr, int error_code, struct pt_regs *regs)
+{
+	union offset_union offset;
+	unsigned long instr, instrptr;
+	int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
+	unsigned int type;
+
+	instrptr = instruction_pointer(regs);
+	instr = *(unsigned long *)instrptr;
+
+	if (user_mode(regs))
+		goto user;
+
+	ai_sys += 1;
+
+ fixup:
+
+	regs->ARM_pc += 4;
+
+	switch (CODING_BITS(instr)) {
+	case 0x00000000:	/* ldrh or strh */
+		if (LDSTH_I_BIT(instr))
+			offset.un = (instr & 0xf00) >> 4 | (instr & 15);
+		else
+			offset.un = regs->uregs[RM_BITS(instr)];
+		handler = do_alignment_ldrhstrh;
+		break;
+
+	case 0x04000000:	/* ldr or str immediate */
+		offset.un = OFFSET_BITS(instr);
+		handler = do_alignment_ldrstr;
+		break;
+
+	case 0x06000000:	/* ldr or str register */
+		offset.un = regs->uregs[RM_BITS(instr)];
+
+		if (IS_SHIFT(instr)) {
+			unsigned int shiftval = SHIFT_BITS(instr);
+
+			switch(SHIFT_TYPE(instr)) {
+			case SHIFT_LSL:
+				offset.un <<= shiftval;
+				break;
+
+			case SHIFT_LSR:
+				offset.un >>= shiftval;
+				break;
+
+			case SHIFT_ASR:
+				offset.sn >>= shiftval;
+				break;
+
+			case SHIFT_RORRRX:
+				if (shiftval == 0) {
+					offset.un >>= 1;
+					if (regs->ARM_cpsr & CC_C_BIT)
+						offset.un |= 1 << 31;
+				} else
+					offset.un = offset.un >> shiftval |
+							  offset.un << (32 - shiftval);
+				break;
+			}
+		}
+		handler = do_alignment_ldrstr;
+		break;
+
+	case 0x08000000:	/* ldm or stm */
+		handler = do_alignment_ldmstm;
+		break;
+
+	default:
+		goto bad;
+	}
+
+	type = handler(addr, instr, regs);
+
+	if (type == TYPE_ERROR || type == TYPE_FAULT)
+		goto bad_or_fault;
+
+	if (type == TYPE_LDST)
+		do_alignment_finish_ldst(addr, instr, regs, offset);
+
+	return 0;
+
+ bad_or_fault:
+	if (type == TYPE_ERROR)
+		goto bad;
+	regs->ARM_pc -= 4;
+	/*
+	 * We got a fault - fix it up, or die.
+	 */
+	do_bad_area(current, current->mm, addr, error_code, regs);
+	return 0;
+
+ bad:
+	/*
+	 * Oops, we didn't handle the instruction.
+	 */
+	printk(KERN_ERR "Alignment trap: not handling instruction "
+		"%08lx at [<%08lx>]\n", instr, instrptr);
+	ai_skipped += 1;
+	return 1;
+
+ user:
+	ai_user += 1;
+
+	if (ai_usermode & 1)
+		printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%08lx "
+		       "Address=0x%08lx Code 0x%02x\n", current->comm,
+			current->pid, instrptr, instr, addr, error_code);
+
+	if (ai_usermode & 2)
+		goto fixup;
+
+	if (ai_usermode & 4)
+		force_sig(SIGBUS, current);
+	else
+		set_cr(cr_no_alignment);
+
+	return 0;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/fault-armv.c linux/arch/arm/mm/fault-armv.c
--- linux.orig/arch/arm/mm/fault-armv.c	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mm/fault-armv.c	2002-08-01 06:42:35.000000000 +0000
@@ -27,7 +27,6 @@
 #include <asm/uaccess.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
-#include <asm/unaligned.h>
 
 extern void die_if_kernel(const char *str, struct pt_regs *regs, int err);
 extern void show_pte(struct mm_struct *mm, unsigned long addr);
@@ -40,499 +39,15 @@
 			struct pt_regs *regs);
 
 #ifdef CONFIG_ALIGNMENT_TRAP
-/*
- * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
- * /proc/sys/debug/alignment, modified and integrated into
- * Linux 2.1 by Russell King
- *
- * Speed optimisations and better fault handling by Russell King.
- *
- * *** NOTE ***
- * This code is not portable to processors with late data abort handling.
- */
-#define CODING_BITS(i)	(i & 0x0e000000)
-
-#define LDST_I_BIT(i)	(i & (1 << 26))		/* Immediate constant	*/
-#define LDST_P_BIT(i)	(i & (1 << 24))		/* Preindex		*/
-#define LDST_U_BIT(i)	(i & (1 << 23))		/* Add offset		*/
-#define LDST_W_BIT(i)	(i & (1 << 21))		/* Writeback		*/
-#define LDST_L_BIT(i)	(i & (1 << 20))		/* Load			*/
-
-#define LDST_P_EQ_U(i)	((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
-
-#define LDSTH_I_BIT(i)	(i & (1 << 22))		/* half-word immed	*/
-#define LDM_S_BIT(i)	(i & (1 << 22))		/* write CPSR from SPSR	*/
-
-#define RN_BITS(i)	((i >> 16) & 15)	/* Rn			*/
-#define RD_BITS(i)	((i >> 12) & 15)	/* Rd			*/
-#define RM_BITS(i)	(i & 15)		/* Rm			*/
-
-#define REGMASK_BITS(i)	(i & 0xffff)
-#define OFFSET_BITS(i)	(i & 0x0fff)
-
-#define IS_SHIFT(i)	(i & 0x0ff0)
-#define SHIFT_BITS(i)	((i >> 7) & 0x1f)
-#define SHIFT_TYPE(i)	(i & 0x60)
-#define SHIFT_LSL	0x00
-#define SHIFT_LSR	0x20
-#define SHIFT_ASR	0x40
-#define SHIFT_RORRRX	0x60
-
-static unsigned long ai_user;
-static unsigned long ai_sys;
-static unsigned long ai_skipped;
-static unsigned long ai_half;
-static unsigned long ai_word;
-static unsigned long ai_multi;
-
-#ifdef CONFIG_SYSCTL
-static int proc_alignment_read(char *page, char **start, off_t off,
-			       int count, int *eof, void *data)
-{
-	char *p = page;
-	int len;
-
-	p += sprintf(p, "User:\t\t%li\n", ai_user);
-	p += sprintf(p, "System:\t\t%li\n", ai_sys);
-	p += sprintf(p, "Skipped:\t%li\n", ai_skipped);
-	p += sprintf(p, "Half:\t\t%li\n", ai_half);
-	p += sprintf(p, "Word:\t\t%li\n", ai_word);
-	p += sprintf(p, "Multi:\t\t%li\n", ai_multi);
-
-	len = (p - page) - off;
-	if (len < 0)
-		len = 0;
-
-	*eof = (len <= count) ? 1 : 0;
-	*start = page + off;
-
-	return len;
-}
-
-/*
- * This needs to be done after sysctl_init, otherwise sys/
- * will be overwritten.
- */
-static int __init alignment_init(void)
-{
-	create_proc_read_entry("sys/debug/alignment", 0, NULL,
-				proc_alignment_read, NULL);
-	return 0;
-}
-
-__initcall(alignment_init);
-#endif /* CONFIG_SYSCTL */
-
-union offset_union {
-	unsigned long un;
-	  signed long sn;
-};
-
-#define TYPE_ERROR	0
-#define TYPE_FAULT	1
-#define TYPE_LDST	2
-#define TYPE_DONE	3
-
-#define get8_unaligned_check(val,addr,err)		\
-	__asm__(					\
-	"1:	ldrb	%1, [%2], #1\n"			\
-	"2:\n"						\
-	"	.section .fixup,\"ax\"\n"		\
-	"	.align	2\n"				\
-	"3:	mov	%0, #1\n"			\
-	"	b	2b\n"				\
-	"	.previous\n"				\
-	"	.section __ex_table,\"a\"\n"		\
-	"	.align	3\n"				\
-	"	.long	1b, 3b\n"			\
-	"	.previous\n"				\
-	: "=r" (err), "=&r" (val), "=r" (addr)		\
-	: "0" (err), "2" (addr))
-
-#define get8t_unaligned_check(val,addr,err)		\
-	__asm__(					\
-	"1:	ldrbt	%1, [%2], #1\n"			\
-	"2:\n"						\
-	"	.section .fixup,\"ax\"\n"		\
-	"	.align	2\n"				\
-	"3:	mov	%0, #1\n"			\
-	"	b	2b\n"				\
-	"	.previous\n"				\
-	"	.section __ex_table,\"a\"\n"		\
-	"	.align	3\n"				\
-	"	.long	1b, 3b\n"			\
-	"	.previous\n"				\
-	: "=r" (err), "=&r" (val), "=r" (addr)		\
-	: "0" (err), "2" (addr))
-
-#define get16_unaligned_check(val,addr)				\
-	do {							\
-		unsigned int err = 0, v, a = addr;		\
-		get8_unaligned_check(val,a,err);		\
-		get8_unaligned_check(v,a,err);			\
-		val |= v << 8;					\
-		if (err)					\
-			goto fault;				\
-	} while (0)
-
-#define put16_unaligned_check(val,addr)				\
-	do {							\
-		unsigned int err = 0, v = val, a = addr;	\
-		__asm__(					\
-		"1:	strb	%1, [%2], #1\n"			\
-		"	mov	%1, %1, lsr #8\n"		\
-		"2:	strb	%1, [%2]\n"			\
-		"3:\n"						\
-		"	.section .fixup,\"ax\"\n"		\
-		"	.align	2\n"				\
-		"4:	mov	%0, #1\n"			\
-		"	b	3b\n"				\
-		"	.previous\n"				\
-		"	.section __ex_table,\"a\"\n"		\
-		"	.align	3\n"				\
-		"	.long	1b, 4b\n"			\
-		"	.long	2b, 4b\n"			\
-		"	.previous\n"				\
-		: "=r" (err), "=&r" (v), "=&r" (a)		\
-		: "0" (err), "1" (v), "2" (a));			\
-		if (err)					\
-			goto fault;				\
-	} while (0)
-
-#define __put32_unaligned_check(ins,val,addr)			\
-	do {							\
-		unsigned int err = 0, v = val, a = addr;	\
-		__asm__(					\
-		"1:	"ins"	%1, [%2], #1\n"			\
-		"	mov	%1, %1, lsr #8\n"		\
-		"2:	"ins"	%1, [%2], #1\n"			\
-		"	mov	%1, %1, lsr #8\n"		\
-		"3:	"ins"	%1, [%2], #1\n"			\
-		"	mov	%1, %1, lsr #8\n"		\
-		"4:	"ins"	%1, [%2]\n"			\
-		"5:\n"						\
-		"	.section .fixup,\"ax\"\n"		\
-		"	.align	2\n"				\
-		"6:	mov	%0, #1\n"			\
-		"	b	5b\n"				\
-		"	.previous\n"				\
-		"	.section __ex_table,\"a\"\n"		\
-		"	.align	3\n"				\
-		"	.long	1b, 6b\n"			\
-		"	.long	2b, 6b\n"			\
-		"	.long	3b, 6b\n"			\
-		"	.long	4b, 6b\n"			\
-		"	.previous\n"				\
-		: "=r" (err), "=&r" (v), "=&r" (a)		\
-		: "0" (err), "1" (v), "2" (a));			\
-		if (err)					\
-			goto fault;				\
-	} while (0)
-
-#define get32_unaligned_check(val,addr)				\
-	do {							\
-		unsigned int err = 0, v, a = addr;		\
-		get8_unaligned_check(val,a,err);		\
-		get8_unaligned_check(v,a,err);			\
-		val |= v << 8;					\
-		get8_unaligned_check(v,a,err);			\
-		val |= v << 16;					\
-		get8_unaligned_check(v,a,err);			\
-		val |= v << 24;					\
-		if (err)					\
-			goto fault;				\
-	} while (0)
-
-#define put32_unaligned_check(val,addr)	 \
-	__put32_unaligned_check("strb", val, addr)
-
-#define get32t_unaligned_check(val,addr)			\
-	do {							\
-		unsigned int err = 0, v, a = addr;		\
-		get8t_unaligned_check(val,a,err);		\
-		get8t_unaligned_check(v,a,err);			\
-		val |= v << 8;					\
-		get8t_unaligned_check(v,a,err);			\
-		val |= v << 16;					\
-		get8t_unaligned_check(v,a,err);			\
-		val |= v << 24;					\
-		if (err)					\
-			goto fault;				\
-	} while (0)
-
-#define put32t_unaligned_check(val,addr) \
-	__put32_unaligned_check("strbt", val, addr)
-
-static void
-do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
-{
-	if (!LDST_U_BIT(instr))
-		offset.un = -offset.un;
-
-	if (!LDST_P_BIT(instr))
-		addr += offset.un;
-
-	if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
-		regs->uregs[RN_BITS(instr)] = addr;
-}
-
-static int
-do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
-{
-	unsigned int rd = RD_BITS(instr);
-
-	if ((instr & 0x01f00ff0) == 0x01000090)
-		goto swp;
-
-	if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0)
-		goto bad;
-
-	ai_half += 1;
-
-	if (LDST_L_BIT(instr)) {
-		unsigned long val;
-		get16_unaligned_check(val, addr);
-
-		/* signed half-word? */
-		if (instr & 0x40)
-			val = (signed long)((signed short) val);
-
-		regs->uregs[rd] = val;
-	} else
-		put16_unaligned_check(regs->uregs[rd], addr);
-
-	return TYPE_LDST;
-
-swp:
-	printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
-bad:
-	return TYPE_ERROR;
-
-fault:
-	return TYPE_FAULT;
-}
-
-static int
-do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
-{
-	unsigned int rd = RD_BITS(instr);
-
-	ai_word += 1;
-
-	if (!LDST_P_BIT(instr) && LDST_W_BIT(instr))
-		goto trans;
-
-	if (LDST_L_BIT(instr))
-		get32_unaligned_check(regs->uregs[rd], addr);
-	else
-		put32_unaligned_check(regs->uregs[rd], addr);
-	return TYPE_LDST;
-
-trans:
-	if (LDST_L_BIT(instr))
-		get32t_unaligned_check(regs->uregs[rd], addr);
-	else
-		put32t_unaligned_check(regs->uregs[rd], addr);
-	return TYPE_LDST;
-
-fault:
-	return TYPE_FAULT;
-}
-
-/*
- * LDM/STM alignment handler.
- *
- * There are 4 variants of this instruction:
- *
- * B = rn pointer before instruction, A = rn pointer after instruction
- *              ------ increasing address ----->
- *	        |    | r0 | r1 | ... | rx |    |
- * PU = 01             B                    A
- * PU = 11        B                    A
- * PU = 00        A                    B
- * PU = 10             A                    B
- */
-static int
-do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
-{
-	unsigned int rd, rn, correction, nr_regs, regbits;
-	unsigned long eaddr, newaddr;
-
-	if (LDM_S_BIT(instr))
-		goto bad;
-
-	correction = 4; /* processor implementation defined */
-	regs->ARM_pc += correction;
-
-	ai_multi += 1;
-
-	/* count the number of registers in the mask to be transferred */
-	nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
-
-	rn = RN_BITS(instr);
-	newaddr = eaddr = regs->uregs[rn];
-
-	if (!LDST_U_BIT(instr))
-		nr_regs = -nr_regs;
-	newaddr += nr_regs;
-	if (!LDST_U_BIT(instr))
-		eaddr = newaddr;
-
-	if (LDST_P_EQ_U(instr))	/* U = P */
-		eaddr += 4;
-
-	/*
-	 * This is a "hint" - we already have eaddr worked out by the
-	 * processor for us.
-	 */
-	if (addr != eaddr) {
-		printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
-			"addr = %08lx, eaddr = %08lx\n",
-			 instruction_pointer(regs), instr, addr, eaddr);
-		show_regs(regs);
-	}
-
-	for (regbits = REGMASK_BITS(instr), rd = 0; regbits; regbits >>= 1, rd += 1)
-		if (regbits & 1) {
-			if (LDST_L_BIT(instr))
-				get32_unaligned_check(regs->uregs[rd], eaddr);
-			else
-				put32_unaligned_check(regs->uregs[rd], eaddr);
-			eaddr += 4;
-		}
-
-	if (LDST_W_BIT(instr))
-		regs->uregs[rn] = newaddr;
-	if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
-		regs->ARM_pc -= correction;
-	return TYPE_DONE;
-
-fault:
-	regs->ARM_pc -= correction;
-	return TYPE_FAULT;
-
-bad:
-	printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
-	return TYPE_ERROR;
-}
-
-static int
-do_alignment(unsigned long addr, int error_code, struct pt_regs *regs)
-{
-	union offset_union offset;
-	unsigned long instr, instrptr;
-	int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
-	unsigned int type;
-
-	if (user_mode(regs))
-		goto user;
-
-	ai_sys += 1;
-
-	instrptr = instruction_pointer(regs);
-	instr = *(unsigned long *)instrptr;
-
-	regs->ARM_pc += 4;
-
-	switch (CODING_BITS(instr)) {
-	case 0x00000000:	/* ldrh or strh */
-		if (LDSTH_I_BIT(instr))
-			offset.un = (instr & 0xf00) >> 4 | (instr & 15);
-		else
-			offset.un = regs->uregs[RM_BITS(instr)];
-		handler = do_alignment_ldrhstrh;
-		break;
-
-	case 0x04000000:	/* ldr or str immediate */
-		offset.un = OFFSET_BITS(instr);
-		handler = do_alignment_ldrstr;
-		break;
-
-	case 0x06000000:	/* ldr or str register */
-		offset.un = regs->uregs[RM_BITS(instr)];
-
-		if (IS_SHIFT(instr)) {
-			unsigned int shiftval = SHIFT_BITS(instr);
-
-			switch(SHIFT_TYPE(instr)) {
-			case SHIFT_LSL:
-				offset.un <<= shiftval;
-				break;
-
-			case SHIFT_LSR:
-				offset.un >>= shiftval;
-				break;
-
-			case SHIFT_ASR:
-				offset.sn >>= shiftval;
-				break;
-
-			case SHIFT_RORRRX:
-				if (shiftval == 0) {
-					offset.un >>= 1;
-					if (regs->ARM_cpsr & CC_C_BIT)
-						offset.un |= 1 << 31;
-				} else
-					offset.un = offset.un >> shiftval |
-							  offset.un << (32 - shiftval);
-				break;
-			}
-		}
-		handler = do_alignment_ldrstr;
-		break;
-
-	case 0x08000000:	/* ldm or stm */
-		handler = do_alignment_ldmstm;
-		break;
-
-	default:
-		goto bad;
-	}
-
-	type = handler(addr, instr, regs);
-
-	if (type == TYPE_ERROR || type == TYPE_FAULT)
-		goto bad_or_fault;
-
-	if (type == TYPE_LDST)
-		do_alignment_finish_ldst(addr, instr, regs, offset);
-
-	return 0;
-
-bad_or_fault:
-	if (type == TYPE_ERROR)
-		goto bad;
-	regs->ARM_pc -= 4;
-	/*
-	 * We got a fault - fix it up, or die.
-	 */
-	do_bad_area(current, current->mm, addr, error_code, regs);
-	return 0;
-
-bad:
-	/*
-	 * Oops, we didn't handle the instruction.
-	 */
-	printk(KERN_ERR "Alignment trap: not handling instruction "
-		"%08lx at [<%08lx>]\n", instr, instrptr);
-	ai_skipped += 1;
-	return 1;
-
-user:
-	set_cr(cr_no_alignment);
-	ai_user += 1;
-	return 0;
-}
-
+extern int do_alignment(unsigned long addr, int error_code, struct pt_regs *regs);
 #else
-
-#define do_alignment NULL
-
+#define do_alignment do_bad
 #endif
 
+
 /*
- * Some section permission faults need to be handled gracefully, for
- * instance, when they happen due to a __{get,put}_user during an oops).
+ * Some section permission faults need to be handled gracefully.
+ * They can happen due to a __{get,put}_user during an oops.
  */
 static int
 do_sect_fault(unsigned long addr, int error_code, struct pt_regs *regs)
@@ -557,73 +72,54 @@
 	return 1;
 }
 
+/*
+ * This abort handler always returns "fault".
+ */
+static int
+do_bad(unsigned long addr, int error_code, struct pt_regs *regs)
+{
+	return 1;
+}
+
 static const struct fsr_info {
 	int	(*fn)(unsigned long addr, int error_code, struct pt_regs *regs);
 	int	sig;
-	char	*name;
+	const char *name;
 } fsr_info[] = {
-	{ NULL,			SIGSEGV, "vector exception"		   },
+	{ do_bad,		SIGSEGV, "vector exception"		   },
 	{ do_alignment,		SIGILL,	 "alignment exception"		   },
-	{ NULL,			SIGKILL, "terminal exception"		   },
+	{ do_bad,		SIGKILL, "terminal exception"		   },
 	{ do_alignment,		SIGILL,	 "alignment exception"		   },
 	{ do_external_fault,	SIGBUS,	 "external abort on linefetch"	   },
 	{ do_translation_fault,	SIGSEGV, "section translation fault"	   },
 	{ do_external_fault,	SIGBUS,	 "external abort on linefetch"	   },
 	{ do_page_fault,	SIGSEGV, "page translation fault"	   },
 	{ do_external_fault,	SIGBUS,	 "external abort on non-linefetch" },
-	{ NULL,			SIGSEGV, "section domain fault"		   },
+	{ do_bad,		SIGSEGV, "section domain fault"		   },
 	{ do_external_fault,	SIGBUS,	 "external abort on non-linefetch" },
-	{ NULL,			SIGSEGV, "page domain fault"		   },
-	{ NULL,			SIGBUS,	 "external abort on translation"   },
+	{ do_bad,		SIGSEGV, "page domain fault"		   },
+	{ do_bad,		SIGBUS,	 "external abort on translation"   },
 	{ do_sect_fault,	SIGSEGV, "section permission fault"	   },
-	{ NULL,			SIGBUS,	 "external abort on translation"   },
+	{ do_bad,		SIGBUS,	 "external abort on translation"   },
 	{ do_page_fault,	SIGSEGV, "page permission fault"	   }
 };
 
 /*
- * Currently dropped down to debug level
+ * Dispatch a data abort to the relevant handler.
  */
 asmlinkage void
 do_DataAbort(unsigned long addr, int error_code, struct pt_regs *regs, int fsr)
 {
 	const struct fsr_info *inf = fsr_info + (fsr & 15);
 
-#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) || defined(CONFIG_DEBUG_ERRORS)
-	if (addr == regs->ARM_pc)
-		goto sa1_weirdness;
-#endif
-
-	if (!inf->fn)
-		goto bad;
-
 	if (!inf->fn(addr, error_code, regs))
 		return;
-bad:
-	printk(KERN_ALERT "Unhandled fault: %s (%X) at 0x%08lx\n",
+
+	printk(KERN_ALERT "Unhandled fault: %s (0x%03x) at 0x%08lx\n",
 		inf->name, fsr, addr);
-	show_pte(current->mm, addr);
 	force_sig(inf->sig, current);
+	show_pte(current->mm, addr);
 	die_if_kernel("Oops", regs, 0);
-	return;
-
-#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) || defined(CONFIG_DEBUG_ERRORS)
-sa1_weirdness:
-	if (user_mode(regs)) {
-		static int first = 1;
-		if (first) {
-			printk(KERN_DEBUG "Fixing up bad data abort at %08lx\n", addr);
-#ifdef CONFIG_DEBUG_ERRORS
-			show_pte(current->mm, addr);
-#endif
-		}
-		first = 0;
-		return;
-	}
-
-	if (!inf->fn || inf->fn(addr, error_code, regs))
-		goto bad;
-	return;
-#endif
 }
 
 asmlinkage void
@@ -680,38 +176,13 @@
 	return;
 }
 
-/*
- * Take care of architecture specific things when placing a new PTE into
- * a page table, or changing an existing PTE.  Basically, there are two
- * things that we need to take care of:
- *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
- *     that any cache entries for the kernels virtual memory
- *     range are written back to the page.
- *  2. If we have multiple shared mappings of the same space in
- *     an object, we need to deal with the cache aliasing issues.
- *
- * Note that the page_table_lock will be held.
- */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+static void
+make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page)
 {
-	struct page *page = pte_page(pte);
 	struct vm_area_struct *mpnt;
-	struct mm_struct *mm;
-	unsigned long pgoff;
-	int aliases;
-
-	if (!VALID_PAGE(page) || !page->mapping)
-		return;
-
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) {
-		unsigned long kvirt = (unsigned long)page_address(page);
-		cpu_cache_clean_invalidate_range(kvirt, kvirt + PAGE_SIZE, 0);
-	}
-
-	mm = vma->vm_mm;
-	pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
-	aliases = 0;
+	struct mm_struct *mm = vma->vm_mm;
+	unsigned long pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
+	int aliases = 0;
 
 	/*
 	 * If we have any shared mappings that are in the same mm
@@ -727,7 +198,7 @@
 		 * Note that we intentionally don't mask out the VMA
 		 * that we are fixing up.
 		 */
-		if (mpnt->vm_mm != mm && mpnt != vma)
+		if (mpnt->vm_mm != mm || mpnt == vma)
 			continue;
 
 		/*
@@ -749,3 +220,30 @@
 	if (aliases)
 		adjust_pte(vma, addr);
 }
+
+/*
+ * Take care of architecture specific things when placing a new PTE into
+ * a page table, or changing an existing PTE.  Basically, there are two
+ * things that we need to take care of:
+ *
+ *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *     that any cache entries for the kernels virtual memory
+ *     range are written back to the page.
+ *  2. If we have multiple shared mappings of the same space in
+ *     an object, we need to deal with the cache aliasing issues.
+ *
+ * Note that the page_table_lock will be held.
+ */
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+	struct page *page = pte_page(pte);
+
+	if (VALID_PAGE(page) && page->mapping) {
+		if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) {
+			unsigned long kvirt = (unsigned long)page_address(page);
+			cpu_cache_clean_invalidate_range(kvirt, kvirt + PAGE_SIZE, 0);
+		}
+
+		make_coherent(vma, addr, page);
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/fault-common.c linux/arch/arm/mm/fault-common.c
--- linux.orig/arch/arm/mm/fault-common.c	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mm/fault-common.c	2002-08-01 06:42:29.000000000 +0000
@@ -141,6 +141,7 @@
 	printk(KERN_DEBUG "%s: unhandled page fault at pc=0x%08lx, "
 	       "lr=0x%08lx (bad address=0x%08lx, code %d)\n",
 	       tsk->comm, regs->ARM_pc, regs->ARM_lr, addr, error_code);
+	show_regs(regs);
 #endif
 
 	tsk->thread.address = addr;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/mm-armv.c linux/arch/arm/mm/mm-armv.c
--- linux.orig/arch/arm/mm/mm-armv.c	2001-06-27 21:12:04.000000000 +0000
+++ linux/arch/arm/mm/mm-armv.c	2002-08-01 06:42:31.000000000 +0000
@@ -14,10 +14,10 @@
 #include <linux/init.h>
 #include <linux/bootmem.h>
 
+#include <asm/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/page.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 
 #include <asm/mach/map.h>
@@ -225,6 +225,19 @@
 	int prot_sect, prot_pte;
 	long off;
 
+	if (md->prot_read && md->prot_write &&
+	    !md->cacheable && !md->bufferable) {
+		printk(KERN_WARNING "Security risk: creating user "
+		       "accessible mapping for 0x%08lx at 0x%08lx\n",
+		       md->physical, md->virtual);
+	}
+
+	if (md->virtual != vectors_base() && md->virtual < PAGE_OFFSET) {
+		printk(KERN_WARNING "MM: not creating mapping for "
+		       "0x%08lx at 0x%08lx in user region\n",
+		       md->physical, md->virtual);
+	}
+
 	prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 		   (md->prot_read  ? L_PTE_USER       : 0) |
 		   (md->prot_write ? L_PTE_WRITE      : 0) |
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/proc-arm1020.S linux/arch/arm/mm/proc-arm1020.S
--- linux.orig/arch/arm/mm/proc-arm1020.S	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/arm/mm/proc-arm1020.S	2002-08-01 06:42:30.000000000 +0000
@@ -56,22 +56,27 @@
  * cpu_arm1020_data_abort()
  *
  * obtain information about current aborted instruction
+ * Note: we read user space.  This means we might cause a data
+ * abort here if the I-TLB and D-TLB aren't seeing the same
+ * picture.  Unfortunately, this does happen.  We live with it.
  *
- * r0 = address of aborted instruction
+ *  r2 = address of aborted instruction
+ *  r3 = cpsr
  *
  * Returns:
  *  r0 = address of abort
  *  r1 != 0 if writing
  *  r3 = FSR
+ *  r4 = corrupted
  */
 	.align	5
 ENTRY(cpu_arm1020_data_abort)
-	ldr	r1, [r0]			@ read aborted instruction
+	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	ldr	r1, [r2]			@ read aborted instruction
+	and	r3, r3, #255
 	tst	r1, r1, lsr #21 		@ C = bit 20
-	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 	sbc	r1, r1, r1			@ r1 = C - 1
-	and	r3, r3, #255
 	mov	pc, lr
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/proc-arm720.S linux/arch/arm/mm/proc-arm720.S
--- linux.orig/arch/arm/mm/proc-arm720.S	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/mm/proc-arm720.S	2002-08-01 06:42:31.000000000 +0000
@@ -111,6 +111,9 @@
  *         : r3 = saved SPSR
  *
  * Purpose : obtain information about current aborted instruction
+ * Note: we read user space.  This means we might cause a data
+ * abort here if the I-TLB and D-TLB aren't seeing the same
+ * picture.  Unfortunately, this does happen.  We live with it.
  *
  * Returns : r0 = address of abort
  *	   : r1 != 0 if writing
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/proc-arm920.S linux/arch/arm/mm/proc-arm920.S
--- linux.orig/arch/arm/mm/proc-arm920.S	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mm/proc-arm920.S	2002-08-01 06:42:29.000000000 +0000
@@ -56,22 +56,27 @@
  * cpu_arm920_data_abort()
  *
  * obtain information about current aborted instruction
+ * Note: we read user space.  This means we might cause a data
+ * abort here if the I-TLB and D-TLB aren't seeing the same
+ * picture.  Unfortunately, this does happen.  We live with it.
  *
- * r0 = address of aborted instruction
+ *  r2 = address of aborted instruction
+ *  r3 = cpsr
  *
  * Returns:
  *  r0 = address of abort
  *  r1 != 0 if writing
  *  r3 = FSR
+ *  r4 = corrupted
  */
 	.align	5
 ENTRY(cpu_arm920_data_abort)
-	ldr	r1, [r0]			@ read aborted instruction
+	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	ldr	r1, [r2]			@ read aborted instruction
+	and	r3, r3, #255
 	tst	r1, r1, lsr #21			@ C = bit 20
-	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 	sbc	r1, r1, r1			@ r1 = C - 1
-	and	r3, r3, #255
 	mov	pc, lr
 	
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/proc-arm922.S linux/arch/arm/mm/proc-arm922.S
--- linux.orig/arch/arm/mm/proc-arm922.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/arm/mm/proc-arm922.S	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,657 @@
+/*
+ *  linux/arch/arm/mm/arm922.S: MMU functions for ARM922
+ *
+ *  Copyright (C) 1999,2000 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *
+ * These are the low level assembler for performing cache and TLB
+ * functions on the arm922.
+ */
+#include <linux/linkage.h>
+#include <linux/config.h>
+#include <asm/assembler.h>
+#include <asm/constants.h>
+#include <asm/procinfo.h>
+#include <asm/hardware.h>
+
+/*
+ * This is the maximum size of an area which will be invalidated
+ * using the single invalidate entry instructions.  Anything larger
+ * than this, and we go for the whole cache.
+ *
+ * This value should be chosen such that we choose the cheapest
+ * alternative.
+ */
+#define MAX_AREA_SIZE	8192
+
+/*
+ * the cache line size of the I and D cache
+ */
+#define DCACHELINESIZE	32
+#define ICACHELINESIZE	32
+
+/*
+ * and the page size
+ */
+#define PAGESIZE	4096
+
+	.text
+
+/*
+ * cpu_arm922_data_abort()
+ *
+ * obtain information about current aborted instruction
+ *
+ * r0 = address of aborted instruction
+ *
+ * Returns:
+ *  r0 = address of abort
+ *  r1 != 0 if writing
+ *  r3 = FSR
+ */
+	.align	5
+ENTRY(cpu_arm922_data_abort)
+	ldr	r1, [r0]			@ read aborted instruction
+	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	tst	r1, r1, lsr #21			@ C = bit 20
+	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
+	sbc	r1, r1, r1			@ r1 = C - 1
+	and	r3, r3, #255
+	mov	pc, lr
+	
+/*
+ * cpu_arm922_check_bugs()
+ */
+ENTRY(cpu_arm922_check_bugs)
+	mrs	ip, cpsr
+	bic	ip, ip, #F_BIT
+	msr	cpsr, ip
+	mov	pc, lr
+
+/*
+ * cpu_arm922_proc_init()
+ */
+ENTRY(cpu_arm922_proc_init)
+	mov	pc, lr
+
+/*
+ * cpu_arm922_proc_fin()
+ */
+ENTRY(cpu_arm922_proc_fin)
+	stmfd	sp!, {lr}
+	mov	ip, #F_BIT | I_BIT | SVC_MODE
+	msr	cpsr_c, ip
+	bl	cpu_arm922_cache_clean_invalidate_all
+	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
+	bic	r0, r0, #0x1000			@ ...i............
+	bic	r0, r0, #0x000e			@ ............wca.
+	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
+	ldmfd	sp!, {pc}
+
+/*
+ * cpu_arm922_reset(loc)
+ *
+ * Perform a soft reset of the system.  Put the CPU into the
+ * same state as it would be if it had been reset, and branch
+ * to what would be the reset vector.
+ *
+ * loc: location to jump to for soft reset
+ */
+	.align	5
+ENTRY(cpu_arm922_reset)
+	mov	ip, #0
+	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
+	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
+	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
+	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
+	bic	ip, ip, #0x000f			@ ............wcam
+	bic	ip, ip, #0x1100			@ ...i...s........
+	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
+	mov	pc, r0
+
+/*
+ * cpu_arm922_do_idle()
+ */
+	.align	5
+ENTRY(cpu_arm922_do_idle)
+#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
+	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
+#endif
+	mov	pc, lr
+
+/* ================================= CACHE ================================ */
+
+
+/*
+ * cpu_arm922_cache_clean_invalidate_all()
+ *
+ * clean and invalidate all cache lines
+ *
+ * Note:
+ *  1. we should preserve r0 at all times
+ */
+	.align	5
+ENTRY(cpu_arm922_cache_clean_invalidate_all)
+	mov	r2, #1
+cpu_arm922_cache_clean_invalidate_all_r2:
+	mov	ip, #0
+#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
+#else
+/*
+ * 'Clean & Invalidate whole DCache'
+ * Re-written to use Index Ops.
+ * Uses registers r1, r3 and ip
+ */
+	mov	r1, #3 << 5			@ 4 segments
+1:	orr	r3, r1, #63 << 26		@ 64 entries
+2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
+	subs	r3, r3, #1 << 26
+	bcs	2b				@ entries 63 to 0
+	subs	r1, r1, #1 << 5
+	bcs	1b				@ segments 7 to 0
+#endif
+	teq	r2, #0
+	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
+	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm922_cache_clean_invalidate_range(start, end, flags)
+ *
+ * clean and invalidate all cache lines associated with this area of memory
+ *
+ * start: Area start address
+ * end:   Area end address
+ * flags: nonzero for I cache as well
+ */
+		.align	5
+ENTRY(cpu_arm922_cache_clean_invalidate_range)
+	bic	r0, r0, #DCACHELINESIZE - 1	@ && added by PGM
+	bic	r1, r1, #DCACHELINESIZE - 1     @ && added by DHM
+	sub	r3, r1, r0
+	cmp	r3, #MAX_AREA_SIZE
+	bgt	cpu_arm922_cache_clean_invalidate_all_r2
+1:	teq	r2, #0
+#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+#else
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+#endif
+	cmp	r0, r1
+	blt	1b
+
+	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm922_flush_ram_page(page)
+ *
+ * clean and invalidate all cache lines associated with this area of memory
+ *
+ * page: page to clean and invalidate
+ */
+	.align	5
+ENTRY(cpu_arm922_flush_ram_page)
+	mov	r1, #PAGESIZE
+#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+#else
+1:	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+#endif
+	subs	r1, r1, #2 * DCACHELINESIZE
+	bne	1b
+	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/* ================================ D-CACHE =============================== */
+
+/*
+ * cpu_arm922_dcache_invalidate_range(start, end)
+ *
+ * throw away all D-cached data in specified region without an obligation
+ * to write them back.  Note however that we must clean the D-cached entries
+ * around the boundaries if the start and/or end address are not cache
+ * aligned.
+ *
+ * start: virtual start address
+ * end:   virtual end address
+ */
+	.align	5
+ENTRY(cpu_arm922_dcache_invalidate_range)
+#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
+	tst	r0, #DCACHELINESIZE - 1
+	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
+	tst	r1, #DCACHELINESIZE - 1
+	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
+#endif		@ clean D entry
+	bic	r0, r0, #DCACHELINESIZE - 1
+	bic	r1, r1, #DCACHELINESIZE - 1
+1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	cmp	r0, r1
+	blt	1b
+	mov	pc, lr
+
+/*
+ * cpu_arm922_dcache_clean_range(start, end)
+ *
+ * For the specified virtual address range, ensure that all caches contain
+ * clean data, such that peripheral accesses to the physical RAM fetch
+ * correct data.
+ *
+ * start: virtual start address
+ * end:   virtual end address
+ */
+	.align	5
+ENTRY(cpu_arm922_dcache_clean_range)
+#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
+	bic	r0, r0, #DCACHELINESIZE - 1
+	sub	r1, r1, r0
+	cmp	r1, #MAX_AREA_SIZE
+	mov	r2, #0
+	bgt	cpu_arm922_cache_clean_invalidate_all_r2
+
+	bic	r1, r1, #DCACHELINESIZE -1
+	add	r1, r1, #DCACHELINESIZE
+
+1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	add	r0, r0, #DCACHELINESIZE
+	subs	r1, r1, #DCACHELINESIZE
+	bpl	1b
+#endif
+	mcr	p15, 0, r2, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm922_dcache_clean_page(page)
+ *
+ * Cleans a single page of dcache so that if we have any future aliased
+ * mappings, they will be consistent at the time that they are created.
+ *
+ * page: virtual address of page to clean from dcache
+ *
+ * Note:
+ *  1. we don't need to flush the write buffer in this case.
+ *  2. we don't invalidate the entries since when we write the page
+ *     out to disk, the entries may get reloaded into the cache.
+ */
+	.align	5
+ENTRY(cpu_arm922_dcache_clean_page)
+#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
+	mov	r1, #PAGESIZE
+1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	add	r0, r0, #DCACHELINESIZE
+	subs	r1, r1, #2 * DCACHELINESIZE
+	bne	1b
+#endif
+	mov	pc, lr
+
+/*
+ * cpu_arm922_dcache_clean_entry(addr)
+ *
+ * Clean the specified entry of any caches such that the MMU
+ * translation fetches will obtain correct data.
+ *
+ * addr: cache-unaligned virtual address
+ */
+	.align	5
+ENTRY(cpu_arm922_dcache_clean_entry)
+#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+#endif
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/* ================================ I-CACHE =============================== */
+
+/*
+ * cpu_arm922_icache_invalidate_range(start, end)
+ *
+ * invalidate a range of virtual addresses from the Icache
+ *
+ * This is a little misleading, it is not intended to clean out
+ * the i-cache but to make sure that any data written to the
+ * range is made consistant.  This means that when we execute code
+ * in that region, everything works as we expect.
+ *
+ * This generally means writing back data in the Dcache and
+ * write buffer and flushing the Icache over that region
+ *
+ * start: virtual start address
+ * end:   virtual end address
+ *
+ * NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to
+ * loop twice, once for i-cache, once for d-cache)
+ */
+	.align	5
+ENTRY(cpu_arm922_icache_invalidate_range)
+	bic	r0, r0, #ICACHELINESIZE - 1	@ Safety check
+	sub	r1, r1, r0
+	cmp	r1, #MAX_AREA_SIZE
+	bgt	cpu_arm922_cache_clean_invalidate_all_r2
+
+	bic	r1, r1, #ICACHELINESIZE - 1
+	add	r1, r1, #ICACHELINESIZE
+
+1:	mcr	p15, 0, r0, c7, c5, 1		@ Clean I entry
+	mcr	p15, 0, r0, c7, c10, 1		@ Clean D entry
+	add	r0, r0, #ICACHELINESIZE
+	subs	r1, r1, #ICACHELINESIZE
+	bne	1b
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+ENTRY(cpu_arm922_icache_invalidate_page)
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
+	mov	pc, lr
+
+/* ================================== TLB ================================= */
+
+/*
+ * cpu_arm922_tlb_invalidate_all()
+ *
+ * Invalidate all TLB entries
+ */
+	.align	5
+ENTRY(cpu_arm922_tlb_invalidate_all)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I & D TLBs
+	mov	pc, lr
+
+/*
+ * cpu_arm922_tlb_invalidate_range(start, end)
+ *
+ * invalidate TLB entries covering the specified range
+ *
+ * start: range start address
+ * end:   range end address
+ */
+	.align	5
+ENTRY(cpu_arm922_tlb_invalidate_range)
+	mov	r3, #0
+	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
+
+	mov	r3, #PAGESIZE
+	sub	r3, r3, #1
+	bic 	r0, r0, r3
+	bic	r1, r1, r3
+
+1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
+	mcr	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
+	add	r0, r0, #PAGESIZE
+	cmp	r0, r1
+	blt	1b
+	mov	pc, lr
+
+/*
+ * cpu_arm922_tlb_invalidate_page(page, flags)
+ *
+ * invalidate the TLB entries for the specified page.
+ *
+ * page:  page to invalidate
+ * flags: non-zero if we include the I TLB
+ */
+	.align	5
+ENTRY(cpu_arm922_tlb_invalidate_page)
+	mov	r3, #0
+	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
+	teq	r1, #0
+	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
+	mcrne	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
+	mov	pc, lr
+
+/* =============================== PageTable ============================== */
+
+/*
+ * cpu_arm922_set_pgd(pgd)
+ *
+ * Set the translation base pointer to be as described by pgd.
+ *
+ * pgd: new page tables
+ */
+	.align	5
+ENTRY(cpu_arm922_set_pgd)
+	mov	ip, #0
+#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+	/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
+	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
+#else
+@ && 'Clean & Invalidate whole DCache'
+@ && Re-written to use Index Ops.
+@ && Uses registers r1, r3 and ip
+
+	mov	r1, #3 << 5			@ 4 segments
+1:	orr	r3, r1, #63 << 26		@ 64 entries
+2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
+	subs	r3, r3, #1 << 26
+	bcs	2b				@ entries 63 to 0
+	subs	r1, r1, #1 << 5
+	bcs	1b				@ segments 7 to 0
+#endif
+	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
+	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
+	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
+	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
+	mov	pc, lr
+
+/*
+ * cpu_arm922_set_pmd(pmdp, pmd)
+ *
+ * Set a level 1 translation table entry, and clean it out of
+ * any caches such that the MMUs can load it correctly.
+ *
+ * pmdp: pointer to PMD entry
+ * pmd:  PMD value to store
+ */
+	.align	5
+ENTRY(cpu_arm922_set_pmd)
+#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+	eor	r2, r1, #0x0a			@ C & Section
+	tst	r2, #0x0b
+	biceq	r1, r1, #4			@ clear bufferable bit
+#endif
+	str	r1, [r0]
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+/*
+ * cpu_arm922_set_pte(ptep, pte)
+ *
+ * Set a PTE and flush it out
+ */
+	.align	5
+ENTRY(cpu_arm922_set_pte)
+	str	r1, [r0], #-1024		@ linux version
+
+	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+
+	bic	r2, r1, #0xff0
+	bic	r2, r2, #3
+	orr	r2, r2, #HPTE_TYPE_SMALL
+
+	tst	r1, #LPTE_USER | LPTE_EXEC	@ User or Exec?
+	orrne	r2, r2, #HPTE_AP_READ
+
+	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
+	orreq	r2, r2, #HPTE_AP_WRITE
+
+	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
+	movne	r2, #0
+
+#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+	eor	r3, r2, #0x0a			@ C & small page?
+	tst	r3, #0x0b
+	biceq	r2, r2, #4
+#endif
+	str	r2, [r0]			@ hardware version
+	mov	r0, r0
+	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
+	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
+
+cpu_manu_name:
+	.asciz	"ARM/ALTERA"
+ENTRY(cpu_arm922_name)
+	.ascii	"Arm922T"
+#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
+	.ascii	"s"
+#endif
+#if defined(CONFIG_CPU_ARM922_I_CACHE_ON)
+	.ascii	"i"
+#endif
+#if defined(CONFIG_CPU_ARM922_D_CACHE_ON)
+	.ascii	"d"
+#if defined(CONFIG_CPU_ARM922_WRITETHROUGH)
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+	.align
+
+	.section ".text.init", #alloc, #execinstr
+
+__arm922_setup:
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
+	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
+	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
+	mcr	p15, 0, r4, c2, c0		@ load page table pointer
+	mov	r0, #0x1f			@ Domains 0, 1 = client
+	mcr	p15, 0, r0, c3, c0		@ load domain access register
+	mrc	p15, 0, r0, c1, c0		@ get control register v4
+/*
+ * Clear out 'unwanted' bits (then put them in if we need them)
+ */
+						@   VI ZFRS BLDP WCAM
+	bic	r0, r0, #0x0e00
+	bic	r0, r0, #0x0002
+	bic	r0, r0, #0x000c
+	bic	r0, r0, #0x1000			@ ...0 000. .... 000.
+/*
+ * Turn on what we want
+ */
+	orr	r0, r0, #0x0031
+	orr	r0, r0, #0x2100			@ ..1. ...1 ..11 ...1
+
+#ifdef CONFIG_CPU_ARM922_D_CACHE_ON
+	orr	r0, r0, #0x0004			@ .... .... .... .1..
+#endif
+#ifdef CONFIG_CPU_ARM922_I_CACHE_ON
+	orr	r0, r0, #0x1000			@ ...1 .... .... ....
+#endif
+	mov	pc, lr
+
+	.text
+
+/*
+ * Purpose : Function pointers used to access above functions - all calls
+ *	     come through these
+ */
+	.type	arm922_processor_functions, #object
+arm922_processor_functions:
+	.word	cpu_arm922_data_abort
+	.word	cpu_arm922_check_bugs
+	.word	cpu_arm922_proc_init
+	.word	cpu_arm922_proc_fin
+	.word	cpu_arm922_reset
+	.word   cpu_arm922_do_idle
+
+	/* cache */
+	.word	cpu_arm922_cache_clean_invalidate_all
+	.word	cpu_arm922_cache_clean_invalidate_range
+	.word	cpu_arm922_flush_ram_page
+
+	/* dcache */
+	.word	cpu_arm922_dcache_invalidate_range
+	.word	cpu_arm922_dcache_clean_range
+	.word	cpu_arm922_dcache_clean_page
+	.word	cpu_arm922_dcache_clean_entry
+
+	/* icache */
+	.word	cpu_arm922_icache_invalidate_range
+	.word	cpu_arm922_icache_invalidate_page
+
+	/* tlb */
+	.word	cpu_arm922_tlb_invalidate_all
+	.word	cpu_arm922_tlb_invalidate_range
+	.word	cpu_arm922_tlb_invalidate_page
+
+	/* pgtable */
+	.word	cpu_arm922_set_pgd
+	.word	cpu_arm922_set_pmd
+	.word	cpu_arm922_set_pte
+	.size	arm922_processor_functions, . - arm922_processor_functions
+
+	.type	cpu_arm922_info, #object
+cpu_arm922_info:
+	.long	cpu_manu_name
+	.long	cpu_arm922_name
+	.size	cpu_arm922_info, . - cpu_arm922_info
+
+	.type	cpu_arch_name, #object
+cpu_arch_name:
+	.asciz	"armv4"
+	.size	cpu_arch_name, . - cpu_arch_name
+
+	.type	cpu_elf_name, #object
+cpu_elf_name:
+	.asciz	"v4"
+	.size	cpu_elf_name, . - cpu_elf_name
+	.align
+
+	.section ".proc.info", #alloc, #execinstr
+
+	.type	__arm922_proc_info,#object
+__arm922_proc_info:
+	.long	0x41009220
+	.long	0xff00fff0
+	.long	0x00000c1e			@ mmuflags
+	b	__arm922_setup
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
+	.long	cpu_arm922_info
+	.long	arm922_processor_functions
+	.size	__arm922_proc_info, . - __arm922_proc_info
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/proc-arm926.S linux/arch/arm/mm/proc-arm926.S
--- linux.orig/arch/arm/mm/proc-arm926.S	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/arm/mm/proc-arm926.S	2002-08-01 06:42:28.000000000 +0000
@@ -56,35 +56,39 @@
  * cpu_arm926_data_abort()
  *
  * obtain information about current aborted instruction
+ * Note: we read user space.  This means we might cause a data
+ * abort here if the I-TLB and D-TLB aren't seeing the same
+ * picture.  Unfortunately, this does happen.  We live with it.
  *
  * Inputs:
- *  r0 = address of abort 
- *  r1 = cpsr of abort 
+ *  r2 = address of abort 
+ *  r3 = cpsr of abort
  *
  * Returns:
  *  r0 = address of abort
  *  r1 != 0 if writing
  *  r3 = FSR
+ *  r4 = corrupted
  */
 	.align	5
 ENTRY(cpu_arm926_data_abort)
-	tst	r1, #1<<24			@ Check for Jbit (NE -> found)
-	movne	r1, #-1 			@ Mark as writing
+	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	mrc	p15, 0, r4, c5, c0, 0		@ get FSR
+
+	tst	r3, #1<<24			@ Check for Jbit (NE -> found)
+	movne	r3, #-1 			@ Mark as writing
 	bne	2f
 
-	tst	r1, #1<<5			@ Check for Thumb-bit (NE -> found)
-	ldrneh	r1, [r0]			@ Read aborted Thumb instruction        
+	tst	r3, #1<<5			@ Check for Thumb-bit (NE -> found)
+	ldrneh	r1, [r2]			@ Read aborted Thumb instruction        
 	tstne	r1, r1, lsr #12 		@ C = bit 11
 
-	ldreq	r1, [r0]			@ Read aborted ARM instruction
+	ldreq	r1, [r2]			@ Read aborted ARM instruction
 	tsteq	r1, r1, lsr #21 		@ C = bit 20
 
 	sbc	r1, r1, r1			@ r1 = C - 1
 2:
-	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
-	and	r3, r3, #255
-	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
-
+	and	r3, r4, #255
 	mov	pc, lr
 
 /*
@@ -193,10 +197,9 @@
 	.align	5
 ENTRY(cpu_arm926_cache_clean_invalidate_range)
 	bic	r0, r0, #DCACHELINESIZE - 1	@ && added by PGM
-	bic	r1, r1, #DCACHELINESIZE - 1	@ && added by DHM
 	sub	r3, r1, r0
 	cmp	r3, #MAX_AREA_SIZE
-	bgt	cpu_arm926_cache_clean_invalidate_all_r2
+	bhi	cpu_arm926_cache_clean_invalidate_all_r2
 
 1:	teq	r2, #0
 #ifdef CONFIG_CPU_ARM926_WRITETHROUGH
@@ -216,7 +219,7 @@
 #endif
         
 	cmp	r0, r1
-	blt	1b
+	blo	1b
 
 	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
 
@@ -267,14 +270,13 @@
 	tst	r0, #DCACHELINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
 	tst	r1, #DCACHELINESIZE - 1
-	mcrne	p15, 0, r1, c7, c10, 1
-#endif		@ clean D entry
+	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
+#endif
 	bic	r0, r0, #DCACHELINESIZE - 1
-	bic	r1, r1, #DCACHELINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
 	add	r0, r0, #DCACHELINESIZE
 	cmp	r0, r1
-	blt	1b
+	blo	1b
 	mov	pc, lr
 
 /*
@@ -291,18 +293,15 @@
 ENTRY(cpu_arm926_dcache_clean_range)
 #ifndef CONFIG_CPU_ARM926_WRITETHROUGH
 	bic	r0, r0, #DCACHELINESIZE - 1
-	sub	r1, r1, r0
-	cmp	r1, #MAX_AREA_SIZE
+	sub	r3, r1, r0
+	cmp	r3, #MAX_AREA_SIZE
 	mov	r2, #0
-	bgt	cpu_arm926_cache_clean_invalidate_all_r2
-
-	bic	r1, r1, #DCACHELINESIZE -1
-	add	r1, r1, #DCACHELINESIZE
+	bhi	cpu_arm926_cache_clean_invalidate_all_r2
 
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #DCACHELINESIZE
-	subs	r1, r1, #DCACHELINESIZE
-	bpl	1b
+	cmp	r0, r1
+	blo	1b
 #endif
 	mcr	p15, 0, r2, c7, c10, 4		@ drain WB
 	mov	pc, lr
@@ -354,7 +353,12 @@
 /*
  * cpu_arm926_icache_invalidate_range(start, end)
  *
- * invalidate a range of virtual addresses from the Icache
+ * This *is not* just icache.  It is to make data written to memory
+ * consistent such that instructions fetched from the region are what
+ * we expect.
+ *
+ * This is typically used after we have copied a module into kernel space,
+ * and we're about to start executing code from that module.
  *
  * start: virtual start address
  * end:   virtual end address
@@ -362,17 +366,14 @@
 	.align	5
 ENTRY(cpu_arm926_icache_invalidate_range)
 	bic	r0, r0, #DCACHELINESIZE - 1	@ Safety check
-	sub	r1, r1, r0
-	cmp	r1, #MAX_AREA_SIZE
-	bgt	cpu_arm926_cache_clean_invalidate_all_r2
-
-	bic	r1, r1, #DCACHELINESIZE - 1
-	add	r1, r1, #DCACHELINESIZE
+	sub	r3, r1, r0
+	cmp	r3, #MAX_AREA_SIZE
+	bhi	cpu_arm926_cache_clean_invalidate_all_r2
 
 1:	mcr	p15, 0, r0, c7, c5, 1		@ clean I entries
 	add	r0, r0, #DCACHELINESIZE
-	subs	r1, r1, #DCACHELINESIZE
-	bne	1b
+	cmp	r0, r1
+	blo	1b
 
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
@@ -410,16 +411,14 @@
 	mov	r3, #0
 	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
 
-	mov	r3, #PAGESIZE
-	sub	r3, r3, #1
-	bic	r0, r0, r3
-	bic	r1, r1, r3
+	bic	r0, r0, #(PAGESIZE - 1) & 0x00ff
+	bic	r0, r0, #(PAGESIZE - 1) & 0xff00
 
 1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
 	mcr	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
 	add	r0, r0, #PAGESIZE
 	cmp	r0, r1
-	blt	1b
+	blo	1b
 	mov	pc, lr
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/mm/proc-sa110.S linux/arch/arm/mm/proc-sa110.S
--- linux.orig/arch/arm/mm/proc-sa110.S	2001-10-25 20:53:46.000000000 +0000
+++ linux/arch/arm/mm/proc-sa110.S	2002-08-01 06:42:43.000000000 +0000
@@ -69,24 +69,29 @@
 /*
  * cpu_sa110_data_abort()
  *
- * obtain information about current aborted instruction
+ * obtain information about current aborted instruction.
+ * Note: we read user space.  This means we might cause a data
+ * abort here if the I-TLB and D-TLB aren't seeing the same
+ * picture.  Unfortunately, this does happen.  We live with it.
  *
- * r0 = address of aborted instruction
+ *  r2 = address of aborted instruction
+ *  r3 = cpsr
  *
  * Returns:
  *  r0 = address of abort
  *  r1 != 0 if writing
  *  r3 = FSR
+ *  r4 = corrupted
  */
 	.align	5
 ENTRY(cpu_sa110_data_abort)
 ENTRY(cpu_sa1100_data_abort)
-	ldr	r1, [r0]			@ read aborted instruction
+	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+	ldr	r1, [r2]			@ read aborted instruction
+	and	r3, r3, #255
 	tst	r1, r1, lsr #21			@ C = bit 20
-	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 	sbc	r1, r1, r1			@ r1 = C - 1
-	and	r3, r3, #255
 	mov	pc, lr
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/ARM-gcc.h linux/arch/arm/nwfpe/ARM-gcc.h
--- linux.orig/arch/arm/nwfpe/ARM-gcc.h	1999-06-17 08:11:35.000000000 +0000
+++ linux/arch/arm/nwfpe/ARM-gcc.h	2002-08-01 06:42:42.000000000 +0000
@@ -1,11 +1,3 @@
-
-/*
--------------------------------------------------------------------------------
-One of the macros `BIGENDIAN' or `LITTLEENDIAN' must be defined.
--------------------------------------------------------------------------------
-*/
-#define LITTLEENDIAN
-
 /*
 -------------------------------------------------------------------------------
 The macro `BITS64' can be defined to indicate that 64-bit integer types are
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/ChangeLog linux/arch/arm/nwfpe/ChangeLog
--- linux.orig/arch/arm/nwfpe/ChangeLog	1999-10-20 23:29:08.000000000 +0000
+++ linux/arch/arm/nwfpe/ChangeLog	2002-08-01 06:42:45.000000000 +0000
@@ -1,3 +1,26 @@
+2002-01-19  Russell King <rmk@arm.linux.org.uk>
+
+	* fpa11.h - Add documentation
+	          - remove userRegisters pointer from this structure.
+	          - add new method to obtain integer register values.
+	* softfloat.c - Remove float128
+	* softfloat.h - Remove float128
+	* softfloat-specialize - Remove float128
+
+	* The FPA11 structure is not a kernel-specific data structure.
+	  It is used by users of ptrace to examine the values of the
+	  floating point registers.  Therefore, any changes to the
+	  FPA11 structure (size or position of elements contained
+	  within) have to be well thought out.
+
+	* Since 128-bit float requires the FPA11 structure to change
+	  size, it has been removed.  128-bit float is currently unused,
+	  and needs various things to be re-worked so that we won't
+	  overflow the available space in the task structure.
+
+	* The changes are designed to break any patch that goes on top
+	  of this code, so that the authors properly review their changes.
+
 1999-08-19  Scott Bambrough  <scottb@netwinder.org>
 
 	* fpmodule.c - Changed version number to 0.95
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/double_cpdo.c linux/arch/arm/nwfpe/double_cpdo.c
--- linux.orig/arch/arm/nwfpe/double_cpdo.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/double_cpdo.c	2002-08-01 06:42:28.000000000 +0000
@@ -19,9 +19,9 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
 #include "softfloat.h"
 #include "fpopcode.h"
-#include "fpa11.h"
 
 float64 float64_exp(float64 Fm);
 float64 float64_ln(float64 Fm);
@@ -165,8 +165,7 @@
 
       case RND_CODE:
       case URD_CODE:
-         fpa11->fpreg[Fd].fDouble = 
-             int32_to_float64(float64_to_int32(rFm));
+         fpa11->fpreg[Fd].fDouble = float64_round_to_int(rFm);
       break;
 
       case SQT_CODE:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/entry.S linux/arch/arm/nwfpe/entry.S
--- linux.orig/arch/arm/nwfpe/entry.S	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/entry.S	2002-08-01 06:42:29.000000000 +0000
@@ -50,11 +50,8 @@
 
 This routine does three things:
 
-1) It saves SP into a variable called userRegisters.  The kernel has
-created a struct pt_regs on the stack and saved the user registers
-into it.  See /usr/include/asm/proc/ptrace.h for details.  The
-emulator code uses userRegisters as the base of an array of words from
-which the contents of the registers can be extracted.
+1) The kernel has created a struct pt_regs on the stack and saved the
+user registers into it.  See inclue/asm-arm/proc/ptrace.h for details.
 
 2) It calls EmulateAll to emulate a floating point instruction.
 EmulateAll returns 1 if the emulation was successful, or 0 if not.
@@ -73,21 +70,16 @@
 
 	.globl	nwfpe_enter
 nwfpe_enter:
-	/* ?? Could put userRegisters and fpa11 into fixed regs during
-	   emulation.  This would reduce load/store overhead at the expense
-	   of stealing two regs from the register allocator.  Not sure if
-	   it's worth it.  */
-	str sp, [r10]                   @ Store the user registers pointer in the fpa11 structure.
-        mov r4, sp			@ use r4 for local pointer
-        mov r10, lr			@ save the failure-return addresses
+        mov r4, lr			@ save the failure-return addresses
+	mov sl, sp			@ we access the registers via 'sl'
 
-        ldr r5, [r4, #60]	 	@ get contents of PC;
+        ldr r5, [sp, #60]	 	@ get contents of PC;
 	sub r8, r5, #4
 .Lx2:	ldrt r0, [r8]			@ get actual instruction into r0
 emulate:
 	bl EmulateAll			@ emulate the instruction
    	cmp r0, #0			@ was emulation successful
-        moveq pc, r10			@ no, return failure
+        moveq pc, r4			@ no, return failure
 
 next:
 .Lx1:	ldrt r6, [r5], #4		@ get the next instruction and
@@ -99,10 +91,10 @@
         teqne r2, #0x0E000000
         movne pc, r9			@ return ok if not a fp insn
 
-        str r5, [r4, #60]		@ update PC copy in regs
+        str r5, [sp, #60]		@ update PC copy in regs
 
         mov r0, r6			@ save a copy
-        ldr r1, [r4, #64]		@ fetch the condition codes
+        ldr r1, [sp, #64]		@ fetch the condition codes
    	bl  checkCondition		@ check the condition
    	cmp r0, #0			@ r0 = 0 ==> condition failed
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/entry26.S linux/arch/arm/nwfpe/entry26.S
--- linux.orig/arch/arm/nwfpe/entry26.S	2001-04-12 02:02:27.000000000 +0000
+++ linux/arch/arm/nwfpe/entry26.S	2002-08-01 06:42:38.000000000 +0000
@@ -65,18 +65,8 @@
 
 	.globl	nwfpe_enter
 nwfpe_enter:
-	ldr	r4, =userRegisters
-	str	sp, [r4]		@ save pointer to user regs
-
-	mov	r10, sp, lsr #13	@ find workspace
-	mov	r10, r10, lsl #13
-	add	r10, r10, #TSS_FPESAVE
-
-	ldr	r4, =fpa11
-	str	r10, [r4]		@ store pointer to our state
-	mov	r4, sp			@ use r4 for local pointer
-
-	ldr	r5, [r4, #60]		@ get contents of PC
+	mov	sl, sp
+	ldr	r5, [sp, #60]		@ get contents of PC
 	bic	r5, r5, #0xfc000003
 	ldr	r0, [r5, #-4]		@ get actual instruction into r0
 	bl	EmulateAll		@ emulate the instruction
@@ -93,10 +83,10 @@
 	teqne	r2, #0x0E000000
 	bne	ret_from_exception	@ return ok if not a fp insn
 
-	ldr	r9, [r4, #60]		@ get new condition codes
+	ldr	r9, [sp, #60]		@ get new condition codes
 	and	r9, r9, #0xfc000003
 	orr	r7, r5, r9
-	str	r7, [r4, #60]		@ update PC copy in regs
+	str	r7, [sp, #60]		@ update PC copy in regs
 
 	mov	r0, r6			@ save a copy
 	mov	r1, r9			@ fetch the condition codes
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/extended_cpdo.c linux/arch/arm/nwfpe/extended_cpdo.c
--- linux.orig/arch/arm/nwfpe/extended_cpdo.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/extended_cpdo.c	2002-08-01 06:42:28.000000000 +0000
@@ -19,9 +19,9 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
 #include "softfloat.h"
 #include "fpopcode.h"
-#include "fpa11.h"
 
 floatx80 floatx80_exp(floatx80 Fm);
 floatx80 floatx80_ln(floatx80 Fm);
@@ -157,8 +157,7 @@
 
       case RND_CODE:
       case URD_CODE:
-         fpa11->fpreg[Fd].fExtended = 
-             int32_to_floatx80(floatx80_to_int32(rFm));
+         fpa11->fpreg[Fd].fExtended = floatx80_round_to_int(rFm);
       break;
 
       case SQT_CODE:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/fpa11.c linux/arch/arm/nwfpe/fpa11.c
--- linux.orig/arch/arm/nwfpe/fpa11.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/fpa11.c	2002-08-01 06:42:40.000000000 +0000
@@ -19,14 +19,15 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
-#include <asm/system.h>
-
 #include "fpa11.h"
+
 #include "fpopcode.h"
 
 #include "fpmodule.h"
 #include "fpmodule.inl"
 
+#include <asm/system.h>
+
 /* forward declarations */
 unsigned int EmulateCPDO(const unsigned int);
 unsigned int EmulateCPDT(const unsigned int);
@@ -56,6 +57,7 @@
 void SetRoundingMode(const unsigned int opcode)
 {
 #if MAINTAIN_FPCR
+   FPA11 *fpa11 = GET_FPA11();
    fpa11->fpcr &= ~MASK_ROUNDING_MODE;
 #endif   
    switch (opcode & MASK_ROUNDING_MODE)
@@ -94,6 +96,7 @@
 void SetRoundingPrecision(const unsigned int opcode)
 {
 #if MAINTAIN_FPCR
+   FPA11 *fpa11 = GET_FPA11();
    fpa11->fpcr &= ~MASK_ROUNDING_PRECISION;
 #endif   
    switch (opcode & MASK_ROUNDING_PRECISION)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/fpa11.h linux/arch/arm/nwfpe/fpa11.h
--- linux.orig/arch/arm/nwfpe/fpa11.h	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/fpa11.h	2002-08-01 06:42:42.000000000 +0000
@@ -22,45 +22,67 @@
 #ifndef __FPA11_H__
 #define __FPA11_H__
 
-/* includes */
-#include "fpsr.h"		/* FP control and status register definitions */
-#include "softfloat.h"
+#define GET_FPA11() ((FPA11 *)(&current->thread.fpstate))
+
+/*
+ * The processes registers are always at the very top of the 8K
+ * stack+task struct.  Use the same method as 'current' uses to
+ * reach them.
+ */
+register unsigned int *user_registers asm("sl");
+
+#define GET_USERREG() (user_registers)
 
 /* Need task_struct */
 #include <linux/sched.h>
 
+/* includes */
+#include "fpsr.h"		/* FP control and status register definitions */
+#include "softfloat.h"
+
 #define		typeNone		0x00
 #define		typeSingle		0x01
 #define		typeDouble		0x02
 #define		typeExtended		0x03
 
+/*
+ * This must be no more and no less than 12 bytes.
+ */
 typedef union tagFPREG {
-   float32  fSingle;
-   float64  fDouble;
    floatx80 fExtended;
+   float64  fDouble;
+   float32  fSingle;
 } FPREG;
 
-/* FPA11 device model */
+/*
+ * FPA11 device model.
+ *
+ * This structure is exported to user space.  Do not re-order.
+ * Only add new stuff to the end, and do not change the size of
+ * any element.  Elements of this structure are used by user
+ * space, and must match struct user_fp in include/asm-arm/user.h.
+ * We include the byte offsets below for documentation purposes.
+ *
+ * The size of this structure and FPREG are checked by fpmodule.c
+ * on initialisation.  If the rules have been broken, NWFPE will
+ * not initialise.
+ */
 typedef struct tagFPA11 {
-  unsigned int *userRegisters;
-  FPREG fpreg[8];		/* 8 floating point registers */
-  FPSR fpsr;			/* floating point status register */
-  FPCR fpcr;			/* floating point control register */
-  unsigned char fType[8];	/* type of floating point value held in
-				   floating point registers.  One of none
-				   single, double or extended. */
-  int initflag;			/* this is special.  The kernel guarantees
-				   to set it to 0 when a thread is launched,
-				   so we can use it to detect whether this
-				   instance of the emulator needs to be
-				   initialised. */
+/*   0 */  FPREG fpreg[8];		/* 8 floating point registers */
+/*  96 */  FPSR fpsr;			/* floating point status register */
+/* 100 */  FPCR fpcr;			/* floating point control register */
+/* 104 */  unsigned char fType[8];	/* type of floating point value held in
+					   floating point registers.  One of none
+					   single, double or extended. */
+/* 112 */  int initflag;		/* this is special.  The kernel guarantees
+					   to set it to 0 when a thread is launched,
+					   so we can use it to detect whether this
+					   instance of the emulator needs to be
+					   initialised. */
 } FPA11;
 
 extern void resetFPA11(void);
 extern void SetRoundingMode(const unsigned int);
 extern void SetRoundingPrecision(const unsigned int);
 
-#define GET_FPA11() ((FPA11 *)(&current->thread.fpstate))
-#define GET_USERREG() (GET_FPA11()->userRegisters)
-
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/fpa11_cpdt.c linux/arch/arm/nwfpe/fpa11_cpdt.c
--- linux.orig/arch/arm/nwfpe/fpa11_cpdt.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/fpa11_cpdt.c	2002-08-01 06:42:48.000000000 +0000
@@ -20,9 +20,9 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
 #include "softfloat.h"
 #include "fpopcode.h"
-#include "fpa11.h"
 #include "fpmodule.h"
 #include "fpmodule.inl"
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/fpa11_cprt.c linux/arch/arm/nwfpe/fpa11_cprt.c
--- linux.orig/arch/arm/nwfpe/fpa11_cprt.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/fpa11_cprt.c	2002-08-01 06:42:32.000000000 +0000
@@ -20,10 +20,10 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
 #include "milieu.h"
 #include "softfloat.h"
 #include "fpopcode.h"
-#include "fpa11.h"
 #include "fpa11.inl"
 #include "fpmodule.h"
 #include "fpmodule.inl"
@@ -82,8 +82,7 @@
    
    unsigned int nRc = 1;
    SetRoundingMode(opcode);
-   SetRoundingPrecision(opcode);
-   
+
    switch (opcode & MASK_ROUNDING_PRECISION)
    {
       case ROUND_SINGLE:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/fpmodule.c linux/arch/arm/nwfpe/fpmodule.c
--- linux.orig/arch/arm/nwfpe/fpmodule.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/fpmodule.c	2002-08-01 06:42:42.000000000 +0000
@@ -21,6 +21,8 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
+
 #include <linux/module.h>
 #include <linux/version.h>
 #include <linux/config.h>
@@ -36,7 +38,6 @@
 #include "softfloat.h"
 #include "fpopcode.h"
 #include "fpmodule.h"
-#include "fpa11.h"
 #include "fpa11.inl"
 
 /* kernel symbols required for signal handling */
@@ -86,6 +87,11 @@
     return -EINVAL;
   }
 
+  if (sizeof(FPREG) != 12) {
+    printk(KERN_ERR "nwfpe: bad register size\n");
+    return -EINVAL;
+  }
+
 #ifdef MODULE
   if (!mod_member_present(&__this_module, can_unload))
     return -EINVAL;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/fpopcode.c linux/arch/arm/nwfpe/fpopcode.c
--- linux.orig/arch/arm/nwfpe/fpopcode.c	2001-04-12 02:02:27.000000000 +0000
+++ linux/arch/arm/nwfpe/fpopcode.c	2002-08-01 06:42:42.000000000 +0000
@@ -19,10 +19,10 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
 #include "softfloat.h"
 #include "fpopcode.h"
 #include "fpsr.h"
-#include "fpa11.h"
 #include "fpmodule.h"
 #include "fpmodule.inl"
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/single_cpdo.c linux/arch/arm/nwfpe/single_cpdo.c
--- linux.orig/arch/arm/nwfpe/single_cpdo.c	2001-08-12 18:13:59.000000000 +0000
+++ linux/arch/arm/nwfpe/single_cpdo.c	2002-08-01 06:42:41.000000000 +0000
@@ -19,9 +19,9 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
+#include "fpa11.h"
 #include "softfloat.h"
 #include "fpopcode.h"
-#include "fpa11.h"
 
 float32 float32_exp(float32 Fm);
 float32 float32_ln(float32 Fm);
@@ -139,8 +139,7 @@
 
       case RND_CODE:
       case URD_CODE:
-         fpa11->fpreg[Fd].fSingle = 
-             int32_to_float32(float32_to_int32(rFm));
+         fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm);
       break;
 
       case SQT_CODE:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/softfloat-specialize linux/arch/arm/nwfpe/softfloat-specialize
--- linux.orig/arch/arm/nwfpe/softfloat-specialize	1999-06-17 08:11:35.000000000 +0000
+++ linux/arch/arm/nwfpe/softfloat-specialize	2002-08-01 06:42:48.000000000 +0000
@@ -364,108 +364,3 @@
 }
 
 #endif
-
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-The pattern for a default generated quadruple-precision NaN.  The `high' and
-`low' values hold the most- and least-significant bits, respectively.
--------------------------------------------------------------------------------
-*/
-#define float128_default_nan_high LIT64( 0xFFFFFFFFFFFFFFFF )
-#define float128_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is a NaN;
-otherwise returns 0.
--------------------------------------------------------------------------------
-*/
-flag float128_is_nan( float128 a )
-{
-
-    return
-           ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
-        && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is a
-signaling NaN; otherwise returns 0.
--------------------------------------------------------------------------------
-*/
-flag float128_is_signaling_nan( float128 a )
-{
-
-    return
-           ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
-        && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the quadruple-precision floating-point NaN
-`a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
-exception is raised.
--------------------------------------------------------------------------------
-*/
-static commonNaNT float128ToCommonNaN( float128 a )
-{
-    commonNaNT z;
-
-    if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
-    z.sign = a.high>>63;
-    shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
-    return z;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the canonical NaN `a' to the quadruple-
-precision floating-point format.
--------------------------------------------------------------------------------
-*/
-static float128 commonNaNToFloat128( commonNaNT a )
-{
-    float128 z;
-
-    shift128Right( a.high, a.low, 16, &z.high, &z.low );
-    z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );
-    return z;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Takes two quadruple-precision floating-point values `a' and `b', one of
-which is a NaN, and returns the appropriate NaN result.  If either `a' or
-`b' is a signaling NaN, the invalid exception is raised.
--------------------------------------------------------------------------------
-*/
-static float128 propagateFloat128NaN( float128 a, float128 b )
-{
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
-
-    aIsNaN = float128_is_nan( a );
-    aIsSignalingNaN = float128_is_signaling_nan( a );
-    bIsNaN = float128_is_nan( b );
-    bIsSignalingNaN = float128_is_signaling_nan( b );
-    a.high |= LIT64( 0x0000800000000000 );
-    b.high |= LIT64( 0x0000800000000000 );
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
-    if ( aIsNaN ) {
-        return ( aIsSignalingNaN & bIsNaN ) ? b : a;
-    }
-    else {
-        return b;
-    }
-
-}
-
-#endif
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/softfloat.c linux/arch/arm/nwfpe/softfloat.c
--- linux.orig/arch/arm/nwfpe/softfloat.c	2000-11-28 01:07:59.000000000 +0000
+++ linux/arch/arm/nwfpe/softfloat.c	2002-08-01 06:42:44.000000000 +0000
@@ -28,6 +28,7 @@
 ===============================================================================
 */
 
+#include "fpa11.h"
 #include "milieu.h"
 #include "softfloat.h"
 
@@ -753,277 +754,6 @@
 
 #endif
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Returns the least-significant 64 fraction bits of the quadruple-precision
-floating-point value `a'.
--------------------------------------------------------------------------------
-*/
-INLINE bits64 extractFloat128Frac1( float128 a )
-{
-
-    return a.low;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the most-significant 48 fraction bits of the quadruple-precision
-floating-point value `a'.
--------------------------------------------------------------------------------
-*/
-INLINE bits64 extractFloat128Frac0( float128 a )
-{
-
-    return a.high & LIT64( 0x0000FFFFFFFFFFFF );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the exponent bits of the quadruple-precision floating-point value
-`a'.
--------------------------------------------------------------------------------
-*/
-INLINE int32 extractFloat128Exp( float128 a )
-{
-
-    return ( a.high>>48 ) & 0x7FFF;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the sign bit of the quadruple-precision floating-point value `a'.
--------------------------------------------------------------------------------
-*/
-INLINE flag extractFloat128Sign( float128 a )
-{
-
-    return a.high>>63;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Normalizes the subnormal quadruple-precision floating-point value
-represented by the denormalized significand formed by the concatenation of
-`aSig0' and `aSig1'.  The normalized exponent is stored at the location
-pointed to by `zExpPtr'.  The most significant 49 bits of the normalized
-significand are stored at the location pointed to by `zSig0Ptr', and the
-least significant 64 bits of the normalized significand are stored at the
-location pointed to by `zSig1Ptr'.
--------------------------------------------------------------------------------
-*/
-static void
- normalizeFloat128Subnormal(
-     bits64 aSig0,
-     bits64 aSig1,
-     int32 *zExpPtr,
-     bits64 *zSig0Ptr,
-     bits64 *zSig1Ptr
- )
-{
-    int8 shiftCount;
-
-    if ( aSig0 == 0 ) {
-        shiftCount = countLeadingZeros64( aSig1 ) - 15;
-        if ( shiftCount < 0 ) {
-            *zSig0Ptr = aSig1>>( - shiftCount );
-            *zSig1Ptr = aSig1<<( shiftCount & 63 );
-        }
-        else {
-            *zSig0Ptr = aSig1<<shiftCount;
-            *zSig1Ptr = 0;
-        }
-        *zExpPtr = - shiftCount - 63;
-    }
-    else {
-        shiftCount = countLeadingZeros64( aSig0 ) - 15;
-        shortShift128Left( aSig0, aSig1, shiftCount, zSig0Ptr, zSig1Ptr );
-        *zExpPtr = 1 - shiftCount;
-    }
-
-}
-
-/*
--------------------------------------------------------------------------------
-Packs the sign `zSign', the exponent `zExp', and the significand formed
-by the concatenation of `zSig0' and `zSig1' into a quadruple-precision
-floating-point value, returning the result.  After being shifted into the
-proper positions, the three fields `zSign', `zExp', and `zSig0' are simply
-added together to form the most significant 32 bits of the result.  This
-means that any integer portion of `zSig0' will be added into the exponent.
-Since a properly normalized significand will have an integer portion equal
-to 1, the `zExp' input should be 1 less than the desired result exponent
-whenever `zSig0' and `zSig1' concatenated form a complete, normalized
-significand.
--------------------------------------------------------------------------------
-*/
-INLINE float128
- packFloat128( flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )
-{
-    float128 z;
-
-    z.low = zSig1;
-    z.high = ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<48 ) + zSig0;
-    return z;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Takes an abstract floating-point value having sign `zSign', exponent `zExp',
-and extended significand formed by the concatenation of `zSig0', `zSig1',
-and `zSig2', and returns the proper quadruple-precision floating-point value
-corresponding to the abstract input.  Ordinarily, the abstract value is
-simply rounded and packed into the quadruple-precision format, with the
-inexact exception raised if the abstract input cannot be represented
-exactly.  If the abstract value is too large, however, the overflow and
-inexact exceptions are raised and an infinity or maximal finite value is
-returned.  If the abstract value is too small, the input value is rounded to
-a subnormal number, and the underflow and inexact exceptions are raised if
-the abstract input cannot be represented exactly as a subnormal quadruple-
-precision floating-point number.
-    The input significand must be normalized or smaller.  If the input
-significand is not normalized, `zExp' must be 0; in that case, the result
-returned is a subnormal number, and it must not require rounding.  In the
-usual case that the input significand is normalized, `zExp' must be 1 less
-than the ``true'' floating-point exponent.  The handling of underflow and
-overflow follows the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-static float128
- roundAndPackFloat128(
-     flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1, bits64 zSig2 )
-{
-    int8 roundingMode;
-    flag roundNearestEven, increment, isTiny;
-
-    roundingMode = float_rounding_mode;
-    roundNearestEven = ( roundingMode == float_round_nearest_even );
-    increment = ( (sbits64) zSig2 < 0 );
-    if ( ! roundNearestEven ) {
-        if ( roundingMode == float_round_to_zero ) {
-            increment = 0;
-        }
-        else {
-            if ( zSign ) {
-                increment = ( roundingMode == float_round_down ) && zSig2;
-            }
-            else {
-                increment = ( roundingMode == float_round_up ) && zSig2;
-            }
-        }
-    }
-    if ( 0x7FFD <= (bits32) zExp ) {
-        if (    ( 0x7FFD < zExp )
-             || (    ( zExp == 0x7FFD )
-                  && eq128(
-                         LIT64( 0x0001FFFFFFFFFFFF ),
-                         LIT64( 0xFFFFFFFFFFFFFFFF ),
-                         zSig0,
-                         zSig1
-                     )
-                  && increment
-                )
-           ) {
-            float_raise( float_flag_overflow | float_flag_inexact );
-            if (    ( roundingMode == float_round_to_zero )
-                 || ( zSign && ( roundingMode == float_round_up ) )
-                 || ( ! zSign && ( roundingMode == float_round_down ) )
-               ) {
-                return
-                    packFloat128(
-                        zSign,
-                        0x7FFE,
-                        LIT64( 0x0000FFFFFFFFFFFF ),
-                        LIT64( 0xFFFFFFFFFFFFFFFF )
-                    );
-            }
-            return packFloat128( zSign, 0x7FFF, 0, 0 );
-        }
-        if ( zExp < 0 ) {
-            isTiny =
-                   ( float_detect_tininess == float_tininess_before_rounding )
-                || ( zExp < -1 )
-                || ! increment
-                || lt128(
-                       zSig0,
-                       zSig1,
-                       LIT64( 0x0001FFFFFFFFFFFF ),
-                       LIT64( 0xFFFFFFFFFFFFFFFF )
-                   );
-            shift128ExtraRightJamming(
-                zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 );
-            zExp = 0;
-            if ( isTiny && zSig2 ) float_raise( float_flag_underflow );
-            if ( roundNearestEven ) {
-                increment = ( (sbits64) zSig2 < 0 );
-            }
-            else {
-                if ( zSign ) {
-                    increment = ( roundingMode == float_round_down ) && zSig2;
-                }
-                else {
-                    increment = ( roundingMode == float_round_up ) && zSig2;
-                }
-            }
-        }
-    }
-    if ( zSig2 ) float_exception_flags |= float_flag_inexact;
-    if ( increment ) {
-        add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 );
-        zSig1 &= ~ ( ( zSig2 + zSig2 == 0 ) & roundNearestEven );
-    }
-    else {
-        if ( ( zSig0 | zSig1 ) == 0 ) zExp = 0;
-    }
-    return packFloat128( zSign, zExp, zSig0, zSig1 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Takes an abstract floating-point value having sign `zSign', exponent `zExp',
-and significand formed by the concatenation of `zSig0' and `zSig1', and
-returns the proper quadruple-precision floating-point value corresponding to
-the abstract input.  This routine is just like `roundAndPackFloat128' except
-that the input significand has fewer bits and does not have to be normalized
-in any way.  In all cases, `zExp' must be 1 less than the ``true'' floating-
-point exponent.
--------------------------------------------------------------------------------
-*/
-static float128
- normalizeRoundAndPackFloat128(
-     flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )
-{
-    int8 shiftCount;
-    bits64 zSig2;
-
-    if ( zSig0 == 0 ) {
-        zSig0 = zSig1;
-        zSig1 = 0;
-        zExp -= 64;
-    }
-    shiftCount = countLeadingZeros64( zSig0 ) - 15;
-    if ( 0 <= shiftCount ) {
-        zSig2 = 0;
-        shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
-    }
-    else {
-        shift128ExtraRightJamming(
-            zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 );
-    }
-    zExp -= shiftCount;
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-#endif
-
 /*
 -------------------------------------------------------------------------------
 Returns the result of converting the 32-bit two's complement integer `a' to
@@ -1093,33 +823,6 @@
 
 #endif
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the 32-bit two's complement integer `a' to
-the quadruple-precision floating-point format.  The conversion is performed
-according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 int32_to_float128( int32 a )
-{
-    flag zSign;
-    uint32 absA;
-    int8 shiftCount;
-    bits64 zSig0;
-
-    if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );
-    zSign = ( a < 0 );
-    absA = zSign ? - a : a;
-    shiftCount = countLeadingZeros32( absA ) + 17;
-    zSig0 = absA;
-    return packFloat128( zSign, 0x402E - shiftCount, zSig0<<shiftCount, 0 );
-
-}
-
-#endif
-
 /*
 -------------------------------------------------------------------------------
 Returns the result of converting the single-precision floating-point value
@@ -1256,40 +959,6 @@
 
 #endif
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the single-precision floating-point value
-`a' to the double-precision floating-point format.  The conversion is
-performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float32_to_float128( float32 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits32 aSig;
-
-    aSig = extractFloat32Frac( a );
-    aExp = extractFloat32Exp( a );
-    aSign = extractFloat32Sign( a );
-    if ( aExp == 0xFF ) {
-        if ( aSig ) return commonNaNToFloat128( float32ToCommonNaN( a ) );
-        return packFloat128( aSign, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );
-        --aExp;
-    }
-    return packFloat128( aSign, aExp + 0x3F80, ( (bits64) aSig )<<25, 0 );
-
-}
-
-#endif
-
 /*
 -------------------------------------------------------------------------------
 Rounds the single-precision floating-point value `a' to an integer, and
@@ -2183,41 +1852,6 @@
 
 #endif
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the double-precision floating-point value
-`a' to the quadruple-precision floating-point format.  The conversion is
-performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float64_to_float128( float64 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits64 aSig, zSig0, zSig1;
-
-    aSig = extractFloat64Frac( a );
-    aExp = extractFloat64Exp( a );
-    aSign = extractFloat64Sign( a );
-    if ( aExp == 0x7FF ) {
-        if ( aSig ) return commonNaNToFloat128( float64ToCommonNaN( a ) );
-        return packFloat128( aSign, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );
-        --aExp;
-    }
-    shift128Right( aSig, 0, 4, &zSig0, &zSig1 );
-    return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 );
-
-}
-
-#endif
-
 /*
 -------------------------------------------------------------------------------
 Rounds the double-precision floating-point value `a' to an integer, and
@@ -3029,35 +2663,6 @@
 
 }
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the extended double-precision floating-
-point value `a' to the quadruple-precision floating-point format.  The
-conversion is performed according to the IEC/IEEE Standard for Binary
-Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 floatx80_to_float128( floatx80 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits64 aSig, zSig0, zSig1;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) {
-        return commonNaNToFloat128( floatx80ToCommonNaN( a ) );
-    }
-    shift128Right( aSig<<1, 0, 16, &zSig0, &zSig1 );
-    return packFloat128( aSign, aExp, zSig0, zSig1 );
-
-}
-
-#endif
-
 /*
 -------------------------------------------------------------------------------
 Rounds the extended double-precision floating-point value `a' to an integer,
@@ -3832,1045 +3437,3 @@
 
 #endif
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the quadruple-precision floating-point
-value `a' to the 32-bit two's complement integer format.  The conversion
-is performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic---which means in particular that the conversion is rounded
-according to the current rounding mode.  If `a' is a NaN, the largest
-positive integer is returned.  Otherwise, if the conversion overflows, the
-largest integer with the same sign as `a' is returned.
--------------------------------------------------------------------------------
-*/
-int32 float128_to_int32( float128 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0;
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );
-    aSig0 |= ( aSig1 != 0 );
-    shiftCount = 0x4028 - aExp;
-    if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 );
-    return roundAndPackInt32( aSign, aSig0 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the quadruple-precision floating-point
-value `a' to the 32-bit two's complement integer format.  The conversion
-is performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic, except that the conversion is always rounded toward zero.  If
-`a' is a NaN, the largest positive integer is returned.  Otherwise, if the
-conversion overflows, the largest integer with the same sign as `a' is
-returned.
--------------------------------------------------------------------------------
-*/
-int32 float128_to_int32_round_to_zero( float128 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig0, aSig1, savedASig;
-    int32 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    aSig0 |= ( aSig1 != 0 );
-    shiftCount = 0x402F - aExp;
-    if ( shiftCount < 17 ) {
-        if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0;
-        goto invalid;
-    }
-    else if ( 48 < shiftCount ) {
-        if ( aExp || aSig0 ) float_exception_flags |= float_flag_inexact;
-        return 0;
-    }
-    aSig0 |= LIT64( 0x0001000000000000 );
-    savedASig = aSig0;
-    aSig0 >>= shiftCount;
-    z = aSig0;
-    if ( aSign ) z = - z;
-    if ( ( z < 0 ) ^ aSign ) {
- invalid:
-        float_exception_flags |= float_flag_invalid;
-        return aSign ? 0x80000000 : 0x7FFFFFFF;
-    }
-    if ( ( aSig0<<shiftCount ) != savedASig ) {
-        float_exception_flags |= float_flag_inexact;
-    }
-    return z;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the quadruple-precision floating-point
-value `a' to the single-precision floating-point format.  The conversion
-is performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic.
--------------------------------------------------------------------------------
-*/
-float32 float128_to_float32( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig0, aSig1;
-    bits32 zSig;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) {
-            return commonNaNToFloat32( float128ToCommonNaN( a ) );
-        }
-        return packFloat32( aSign, 0xFF, 0 );
-    }
-    aSig0 |= ( aSig1 != 0 );
-    shift64RightJamming( aSig0, 18, &aSig0 );
-    zSig = aSig0;
-    if ( aExp || zSig ) {
-        zSig |= 0x40000000;
-        aExp -= 0x3F81;
-    }
-    return roundAndPackFloat32( aSign, aExp, zSig );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the quadruple-precision floating-point
-value `a' to the double-precision floating-point format.  The conversion
-is performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic.
--------------------------------------------------------------------------------
-*/
-float64 float128_to_float64( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) {
-            return commonNaNToFloat64( float128ToCommonNaN( a ) );
-        }
-        return packFloat64( aSign, 0x7FF, 0 );
-    }
-    shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );
-    aSig0 |= ( aSig1 != 0 );
-    if ( aExp || aSig0 ) {
-        aSig0 |= LIT64( 0x4000000000000000 );
-        aExp -= 0x3C01;
-    }
-    return roundAndPackFloat64( aSign, aExp, aSig0 );
-
-}
-
-#ifdef FLOATX80
-
-/*
--------------------------------------------------------------------------------
-Returns the result of converting the quadruple-precision floating-point
-value `a' to the extended double-precision floating-point format.  The
-conversion is performed according to the IEC/IEEE Standard for Binary
-Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-floatx80 float128_to_floatx80( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) {
-            return commonNaNToFloatx80( float128ToCommonNaN( a ) );
-        }
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloatx80( aSign, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    else {
-        aSig0 |= LIT64( 0x0001000000000000 );
-    }
-    shortShift128Left( aSig0, aSig1, 15, &aSig0, &aSig1 );
-    return roundAndPackFloatx80( 80, aSign, aExp, aSig0, aSig1 );
-
-}
-
-#endif
-
-/*
--------------------------------------------------------------------------------
-Rounds the quadruple-precision floating-point value `a' to an integer, and
-returns the result as a quadruple-precision floating-point value.  The
-operation is performed according to the IEC/IEEE Standard for Binary
-Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_round_to_int( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 lastBitMask, roundBitsMask;
-    int8 roundingMode;
-    float128 z;
-
-    aExp = extractFloat128Exp( a );
-    if ( 0x402F <= aExp ) {
-        if ( 0x406F <= aExp ) {
-            if (    ( aExp == 0x7FFF )
-                 && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) )
-               ) {
-                return propagateFloat128NaN( a, a );
-            }
-            return a;
-        }
-        lastBitMask = 1;
-        lastBitMask = ( lastBitMask<<( 0x406E - aExp ) )<<1;
-        roundBitsMask = lastBitMask - 1;
-        z = a;
-        roundingMode = float_rounding_mode;
-        if ( roundingMode == float_round_nearest_even ) {
-            if ( lastBitMask ) {
-                add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low );
-                if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;
-            }
-            else {
-                if ( (sbits64) z.low < 0 ) {
-                    ++z.high;
-                    if ( (bits64) ( z.low<<1 ) == 0 ) z.high &= ~1;
-                }
-            }
-        }
-        else if ( roundingMode != float_round_to_zero ) {
-            if (   extractFloat128Sign( z )
-                 ^ ( roundingMode == float_round_up ) ) {
-                add128( z.high, z.low, 0, roundBitsMask, &z.high, &z.low );
-            }
-        }
-        z.low &= ~ roundBitsMask;
-    }
-    else {
-        if ( aExp <= 0x3FFE ) {
-            if ( ( ( (bits64) ( a.high<<1 ) ) | a.low ) == 0 ) return a;
-            float_exception_flags |= float_flag_inexact;
-            aSign = extractFloat128Sign( a );
-            switch ( float_rounding_mode ) {
-             case float_round_nearest_even:
-                if (    ( aExp == 0x3FFE )
-                     && (   extractFloat128Frac0( a )
-                          | extractFloat128Frac1( a ) )
-                   ) {
-                    return packFloat128( aSign, 0x3FFF, 0, 0 );
-                }
-                break;
-             case float_round_down:
-                return
-                      aSign ? packFloat128( 1, 0x3FFF, 0, 0 )
-                    : packFloat128( 0, 0, 0, 0 );
-             case float_round_up:
-                return
-                      aSign ? packFloat128( 1, 0, 0, 0 )
-                    : packFloat128( 0, 0x3FFF, 0, 0 );
-            }
-            return packFloat128( aSign, 0, 0, 0 );
-        }
-        lastBitMask = 1;
-        lastBitMask <<= 0x402F - aExp;
-        roundBitsMask = lastBitMask - 1;
-        z.low = 0;
-        z.high = a.high;
-        roundingMode = float_rounding_mode;
-        if ( roundingMode == float_round_nearest_even ) {
-            z.high += lastBitMask>>1;
-            if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) {
-                z.high &= ~ lastBitMask;
-            }
-        }
-        else if ( roundingMode != float_round_to_zero ) {
-            if (   extractFloat128Sign( z )
-                 ^ ( roundingMode == float_round_up ) ) {
-                z.high |= ( a.low != 0 );
-                z.high += roundBitsMask;
-            }
-        }
-        z.high &= ~ roundBitsMask;
-    }
-    if ( ( z.low != a.low ) || ( z.high != a.high ) ) {
-        float_exception_flags |= float_flag_inexact;
-    }
-    return z;
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of adding the absolute values of the quadruple-precision
-floating-point values `a' and `b'.  If `zSign' is true, the sum is negated
-before being returned.  `zSign' is ignored if the result is a NaN.  The
-addition is performed according to the IEC/IEEE Standard for Binary
-Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-static float128 addFloat128Sigs( float128 a, float128 b, flag zSign )
-{
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;
-    int32 expDiff;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    expDiff = aExp - bExp;
-    if ( 0 < expDiff ) {
-        if ( aExp == 0x7FFF ) {
-            if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );
-            return a;
-        }
-        if ( bExp == 0 ) {
-            --expDiff;
-        }
-        else {
-            bSig0 |= LIT64( 0x0001000000000000 );
-        }
-        shift128ExtraRightJamming(
-            bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 );
-        zExp = aExp;
-    }
-    else if ( expDiff < 0 ) {
-        if ( bExp == 0x7FFF ) {
-            if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-            return packFloat128( zSign, 0x7FFF, 0, 0 );
-        }
-        if ( aExp == 0 ) {
-            ++expDiff;
-        }
-        else {
-            aSig0 |= LIT64( 0x0001000000000000 );
-        }
-        shift128ExtraRightJamming(
-            aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 );
-        zExp = bExp;
-    }
-    else {
-        if ( aExp == 0x7FFF ) {
-            if ( aSig0 | aSig1 | bSig0 | bSig1 ) {
-                return propagateFloat128NaN( a, b );
-            }
-            return a;
-        }
-        add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );
-        if ( aExp == 0 ) return packFloat128( zSign, 0, zSig0, zSig1 );
-        zSig2 = 0;
-        zSig0 |= LIT64( 0x0002000000000000 );
-        zExp = aExp;
-        goto shiftRight1;
-    }
-    aSig0 |= LIT64( 0x0001000000000000 );
-    add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );
-    --zExp;
-    if ( zSig0 < LIT64( 0x0002000000000000 ) ) goto roundAndPack;
-    ++zExp;
- shiftRight1:
-    shift128ExtraRightJamming(
-        zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );
- roundAndPack:
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of subtracting the absolute values of the quadruple-
-precision floating-point values `a' and `b'.  If `zSign' is true, the
-difference is negated before being returned.  `zSign' is ignored if the
-result is a NaN.  The subtraction is performed according to the IEC/IEEE
-Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-static float128 subFloat128Sigs( float128 a, float128 b, flag zSign )
-{
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;
-    int32 expDiff;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    expDiff = aExp - bExp;
-    shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );
-    shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 );
-    if ( 0 < expDiff ) goto aExpBigger;
-    if ( expDiff < 0 ) goto bExpBigger;
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 | bSig0 | bSig1 ) {
-            return propagateFloat128NaN( a, b );
-        }
-        float_raise( float_flag_invalid );
-        z.low = float128_default_nan_low;
-        z.high = float128_default_nan_high;
-        return z;
-    }
-    if ( aExp == 0 ) {
-        aExp = 1;
-        bExp = 1;
-    }
-    if ( bSig0 < aSig0 ) goto aBigger;
-    if ( aSig0 < bSig0 ) goto bBigger;
-    if ( bSig1 < aSig1 ) goto aBigger;
-    if ( aSig1 < bSig1 ) goto bBigger;
-    return packFloat128( float_rounding_mode == float_round_down, 0, 0, 0 );
- bExpBigger:
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        ++expDiff;
-    }
-    else {
-        aSig0 |= LIT64( 0x4000000000000000 );
-    }
-    shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );
-    bSig0 |= LIT64( 0x4000000000000000 );
- bBigger:
-    sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 );
-    zExp = bExp;
-    zSign ^= 1;
-    goto normalizeRoundAndPack;
- aExpBigger:
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );
-        return a;
-    }
-    if ( bExp == 0 ) {
-        --expDiff;
-    }
-    else {
-        bSig0 |= LIT64( 0x4000000000000000 );
-    }
-    shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 );
-    aSig0 |= LIT64( 0x4000000000000000 );
- aBigger:
-    sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );
-    zExp = aExp;
- normalizeRoundAndPack:
-    --zExp;
-    return normalizeRoundAndPackFloat128( zSign, zExp - 14, zSig0, zSig1 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of adding the quadruple-precision floating-point values
-`a' and `b'.  The operation is performed according to the IEC/IEEE Standard
-for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_add( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign == bSign ) {
-        return addFloat128Sigs( a, b, aSign );
-    }
-    else {
-        return subFloat128Sigs( a, b, aSign );
-    }
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of subtracting the quadruple-precision floating-point
-values `a' and `b'.  The operation is performed according to the IEC/IEEE
-Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_sub( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign == bSign ) {
-        return subFloat128Sigs( a, b, aSign );
-    }
-    else {
-        return addFloat128Sigs( a, b, aSign );
-    }
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of multiplying the quadruple-precision floating-point
-values `a' and `b'.  The operation is performed according to the IEC/IEEE
-Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_mul( float128 a, float128 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    bSign = extractFloat128Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FFF ) {
-        if (    ( aSig0 | aSig1 )
-             || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {
-            return propagateFloat128NaN( a, b );
-        }
-        if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid;
-        return packFloat128( zSign, 0x7FFF, 0, 0 );
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
- invalid:
-            float_raise( float_flag_invalid );
-            z.low = float128_default_nan_low;
-            z.high = float128_default_nan_high;
-            return z;
-        }
-        return packFloat128( zSign, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    if ( bExp == 0 ) {
-        if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
-    }
-    zExp = aExp + bExp - 0x4000;
-    aSig0 |= LIT64( 0x0001000000000000 );
-    shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 );
-    mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 );
-    add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 );
-    zSig2 |= ( zSig3 != 0 );
-    if ( LIT64( 0x0002000000000000 ) <= zSig0 ) {
-        shift128ExtraRightJamming(
-            zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );
-        ++zExp;
-    }
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the result of dividing the quadruple-precision floating-point value
-`a' by the corresponding value `b'.  The operation is performed according to
-the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_div( float128 a, float128 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    bSign = extractFloat128Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );
-        if ( bExp == 0x7FFF ) {
-            if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-            goto invalid;
-        }
-        return packFloat128( zSign, 0x7FFF, 0, 0 );
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        return packFloat128( zSign, 0, 0, 0 );
-    }
-    if ( bExp == 0 ) {
-        if ( ( bSig0 | bSig1 ) == 0 ) {
-            if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
- invalid:
-                float_raise( float_flag_invalid );
-                z.low = float128_default_nan_low;
-                z.high = float128_default_nan_high;
-                return z;
-            }
-            float_raise( float_flag_divbyzero );
-            return packFloat128( zSign, 0x7FFF, 0, 0 );
-        }
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    zExp = aExp - bExp + 0x3FFD;
-    shortShift128Left(
-        aSig0 | LIT64( 0x0001000000000000 ), aSig1, 15, &aSig0, &aSig1 );
-    shortShift128Left(
-        bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );
-    if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) {
-        shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 );
-        ++zExp;
-    }
-    zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 );
-    mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 );
-    sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 );
-    while ( (sbits64) rem0 < 0 ) {
-        --zSig0;
-        add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 );
-    }
-    zSig1 = estimateDiv128To64( rem1, rem2, bSig0 );
-    if ( ( zSig1 & 0x3FFF ) <= 4 ) {
-        mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 );
-        sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 );
-        while ( (sbits64) rem1 < 0 ) {
-            --zSig1;
-            add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 );
-        }
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
-    }
-    shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 );
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the remainder of the quadruple-precision floating-point value `a'
-with respect to the corresponding value `b'.  The operation is performed
-according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_rem( float128 a, float128 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, expDiff;
-    bits64 aSig0, aSig1, bSig0, bSig1;
-    bits64 q, term0, term1, term2, allZero, alternateASig0, alternateASig1;
-    bits64 sigMean1;
-    sbits64 sigMean0;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    bSign = extractFloat128Sign( b );
-    if ( aExp == 0x7FFF ) {
-        if (    ( aSig0 | aSig1 )
-             || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {
-            return propagateFloat128NaN( a, b );
-        }
-        goto invalid;
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        return a;
-    }
-    if ( bExp == 0 ) {
-        if ( ( bSig0 | bSig1 ) == 0 ) {
- invalid:
-            float_raise( float_flag_invalid );
-            z.low = float128_default_nan_low;
-            z.high = float128_default_nan_high;
-            return z;
-        }
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return a;
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    expDiff = aExp - bExp;
-    if ( expDiff < -1 ) return a;
-    shortShift128Left(
-        aSig0 | LIT64( 0x0001000000000000 ),
-        aSig1,
-        15 - ( expDiff < 0 ),
-        &aSig0,
-        &aSig1
-    );
-    shortShift128Left(
-        bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );
-    q = le128( bSig0, bSig1, aSig0, aSig1 );
-    if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );
-    expDiff -= 64;
-    while ( 0 < expDiff ) {
-        q = estimateDiv128To64( aSig0, aSig1, bSig0 );
-        q = ( 4 < q ) ? q - 4 : 0;
-        mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );
-        shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZero );
-        shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero );
-        sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 );
-        expDiff -= 61;
-    }
-    if ( -64 < expDiff ) {
-        q = estimateDiv128To64( aSig0, aSig1, bSig0 );
-        q = ( 4 < q ) ? q - 4 : 0;
-        q >>= - expDiff;
-        shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );
-        expDiff += 52;
-        if ( expDiff < 0 ) {
-            shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );
-        }
-        else {
-            shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 );
-        }
-        mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );
-        sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 );
-    }
-    else {
-        shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 );
-        shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );
-    }
-    do {
-        alternateASig0 = aSig0;
-        alternateASig1 = aSig1;
-        ++q;
-        sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );
-    } while ( 0 <= (sbits64) aSig0 );
-    add128(
-        aSig0, aSig1, alternateASig0, alternateASig1, &sigMean0, &sigMean1 );
-    if (    ( sigMean0 < 0 )
-         || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) {
-        aSig0 = alternateASig0;
-        aSig1 = alternateASig1;
-    }
-    zSign = ( (sbits64) aSig0 < 0 );
-    if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 );
-    return
-        normalizeRoundAndPackFloat128( aSign ^ zSign, bExp - 4, aSig0, aSig1 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns the square root of the quadruple-precision floating-point value `a'.
-The operation is performed according to the IEC/IEEE Standard for Binary
-Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-float128 float128_sqrt( float128 a )
-{
-    flag aSign;
-    int32 aExp, zExp;
-    bits64 aSig0, aSig1, zSig0, zSig1, zSig2;
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
-    bits64 shiftedRem0, shiftedRem1;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, a );
-        if ( ! aSign ) return a;
-        goto invalid;
-    }
-    if ( aSign ) {
-        if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;
- invalid:
-        float_raise( float_flag_invalid );
-        z.low = float128_default_nan_low;
-        z.high = float128_default_nan_high;
-        return z;
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE;
-    aSig0 |= LIT64( 0x0001000000000000 );
-    zSig0 = estimateSqrt32( aExp, aSig0>>17 );
-    zSig0 <<= 31;
-    shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 );
-    zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0 ) + zSig0 + 4;
-    if ( 0 <= (sbits64) zSig0 ) zSig0 = LIT64( 0xFFFFFFFFFFFFFFFF );
-    shortShift128Left( aSig0, aSig1, 2, &aSig0, &aSig1 );
-    mul64To128( zSig0, zSig0, &term0, &term1 );
-    sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );
-    while ( (sbits64) rem0 < 0 ) {
-        --zSig0;
-        shortShift128Left( 0, zSig0, 1, &term0, &term1 );
-        term1 |= 1;
-        add128( rem0, rem1, term0, term1, &rem0, &rem1 );
-    }
-    shortShift128Left( rem0, rem1, 63, &shiftedRem0, &shiftedRem1 );
-    zSig1 = estimateDiv128To64( shiftedRem0, shiftedRem1, zSig0 );
-    if ( ( zSig1 & 0x3FFF ) <= 5 ) {
-        if ( zSig1 == 0 ) zSig1 = 1;
-        mul64To128( zSig0, zSig1, &term1, &term2 );
-        shortShift128Left( term1, term2, 1, &term1, &term2 );
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );
-        mul64To128( zSig1, zSig1, &term2, &term3 );
-        sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );
-        while ( (sbits64) rem1 < 0 ) {
-            --zSig1;
-            shortShift192Left( 0, zSig0, zSig1, 1, &term1, &term2, &term3 );
-            term3 |= 1;
-            add192(
-                rem1, rem2, rem3, term1, term2, term3, &rem1, &rem2, &rem3 );
-        }
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
-    }
-    shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 );
-    return roundAndPackFloat128( 0, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is equal to
-the corresponding value `b', and 0 otherwise.  The comparison is performed
-according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-flag float128_eq( float128 a, float128 b )
-{
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        if (    float128_is_signaling_nan( a )
-             || float128_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    return
-           ( a.low == b.low )
-        && (    ( a.high == b.high )
-             || (    ( a.low == 0 )
-                  && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )
-           );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is less than
-or equal to the corresponding value `b', and 0 otherwise.  The comparison
-is performed according to the IEC/IEEE Standard for Binary Floating-point
-Arithmetic.
--------------------------------------------------------------------------------
-*/
-flag float128_le( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            || (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 == 0 );
-    }
-    return
-          aSign ? le128( b.high, b.low, a.high, a.low )
-        : le128( a.high, a.low, b.high, b.low );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is less than
-the corresponding value `b', and 0 otherwise.  The comparison is performed
-according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-flag float128_lt( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            && (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 != 0 );
-    }
-    return
-          aSign ? lt128( b.high, b.low, a.high, a.low )
-        : lt128( a.high, a.low, b.high, b.low );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is equal to
-the corresponding value `b', and 0 otherwise.  The invalid exception is
-raised if either operand is a NaN.  Otherwise, the comparison is performed
-according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-flag float128_eq_signaling( float128 a, float128 b )
-{
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    return
-           ( a.low == b.low )
-        && (    ( a.high == b.high )
-             || (    ( a.low == 0 )
-                  && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )
-           );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is less than
-or equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs do not
-cause an exception.  Otherwise, the comparison is performed according to the
-IEC/IEEE Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-flag float128_le_quiet( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        if (    float128_is_signaling_nan( a )
-             || float128_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            || (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 == 0 );
-    }
-    return
-          aSign ? le128( b.high, b.low, a.high, a.low )
-        : le128( a.high, a.low, b.high, b.low );
-
-}
-
-/*
--------------------------------------------------------------------------------
-Returns 1 if the quadruple-precision floating-point value `a' is less than
-the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause an
-exception.  Otherwise, the comparison is performed according to the IEC/IEEE
-Standard for Binary Floating-point Arithmetic.
--------------------------------------------------------------------------------
-*/
-flag float128_lt_quiet( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        if (    float128_is_signaling_nan( a )
-             || float128_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            && (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 != 0 );
-    }
-    return
-          aSign ? lt128( b.high, b.low, a.high, a.low )
-        : lt128( a.high, a.low, b.high, b.low );
-
-}
-
-#endif
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/nwfpe/softfloat.h linux/arch/arm/nwfpe/softfloat.h
--- linux.orig/arch/arm/nwfpe/softfloat.h	1999-06-17 08:11:35.000000000 +0000
+++ linux/arch/arm/nwfpe/softfloat.h	2002-08-01 06:42:31.000000000 +0000
@@ -37,12 +37,10 @@
 The macro `FLOATX80' must be defined to enable the extended double-precision
 floating-point format `floatx80'.  If this macro is not defined, the
 `floatx80' type will not be defined, and none of the functions that either
-input or output the `floatx80' type will be defined.  The same applies to
-the `FLOAT128' macro and the quadruple-precision format `float128'.
+input or output the `floatx80' type will be defined.
 -------------------------------------------------------------------------------
 */
 #define FLOATX80
-/* #define FLOAT128 */
 
 /*
 -------------------------------------------------------------------------------
@@ -51,17 +49,10 @@
 */
 typedef unsigned long int float32;
 typedef unsigned long long float64;
-#ifdef FLOATX80
 typedef struct {
     unsigned short high;
     unsigned long long low;
 } floatx80;
-#endif
-#ifdef FLOAT128
-typedef struct {
-    unsigned long long high, low;
-} float128;
-#endif
 
 /*
 -------------------------------------------------------------------------------
@@ -131,9 +122,6 @@
 #ifdef FLOATX80
 floatx80 int32_to_floatx80( signed int );
 #endif
-#ifdef FLOAT128
-float128 int32_to_float128( signed int );
-#endif
 
 /*
 -------------------------------------------------------------------------------
@@ -146,9 +134,6 @@
 #ifdef FLOATX80
 floatx80 float32_to_floatx80( float32 );
 #endif
-#ifdef FLOAT128
-float128 float32_to_float128( float32 );
-#endif
 
 /*
 -------------------------------------------------------------------------------
@@ -181,9 +166,6 @@
 #ifdef FLOATX80
 floatx80 float64_to_floatx80( float64 );
 #endif
-#ifdef FLOAT128
-float128 float64_to_float128( float64 );
-#endif
 
 /*
 -------------------------------------------------------------------------------
@@ -216,9 +198,6 @@
 signed int floatx80_to_int32_round_to_zero( floatx80 );
 float32 floatx80_to_float32( floatx80 );
 float64 floatx80_to_float64( floatx80 );
-#ifdef FLOAT128
-float128 floatx80_to_float128( floatx80 );
-#endif
 
 /*
 -------------------------------------------------------------------------------
@@ -250,41 +229,4 @@
 
 #endif
 
-#ifdef FLOAT128
-
-/*
--------------------------------------------------------------------------------
-Software IEC/IEEE quadruple-precision conversion routines.
--------------------------------------------------------------------------------
-*/
-signed int float128_to_int32( float128 );
-signed int float128_to_int32_round_to_zero( float128 );
-float32 float128_to_float32( float128 );
-float64 float128_to_float64( float128 );
-#ifdef FLOATX80
-floatx80 float128_to_floatx80( float128 );
-#endif
-
-/*
--------------------------------------------------------------------------------
-Software IEC/IEEE quadruple-precision operations.
--------------------------------------------------------------------------------
-*/
-float128 float128_round_to_int( float128 );
-float128 float128_add( float128, float128 );
-float128 float128_sub( float128, float128 );
-float128 float128_mul( float128, float128 );
-float128 float128_div( float128, float128 );
-float128 float128_rem( float128, float128 );
-float128 float128_sqrt( float128 );
-char float128_eq( float128, float128 );
-char float128_le( float128, float128 );
-char float128_lt( float128, float128 );
-char float128_eq_signaling( float128, float128 );
-char float128_le_quiet( float128, float128 );
-char float128_lt_quiet( float128, float128 );
-char float128_is_signaling_nan( float128 );
-
-#endif
-
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/tools/Makefile linux/arch/arm/tools/Makefile
--- linux.orig/arch/arm/tools/Makefile	2001-10-11 16:04:57.000000000 +0000
+++ linux/arch/arm/tools/Makefile	2002-08-01 06:42:29.000000000 +0000
@@ -15,13 +15,17 @@
 # what we want.  We do this in several stages so make picks up on
 # any errors that occur along the way.
 
-$(TOPDIR)/include/asm-arm/constants.h: constants-hdr getconstants.c
-	$(CC) $(CFLAGS) -S -o - getconstants.c > $@.tmp.1
+constants.h: constants-hdr getconstants.c
+	$(CC) $(CFLAGS) -S -o $@.tmp.1 getconstants.c
 	sed 's/^\(#define .* \)[#$$]\(.*\)/\1\2/;/^#define/!d' $@.tmp.1 > $@.tmp.2
-	cat constants-hdr $@.tmp.2 > $@.tmp
-	cmp $@.tmp $@ >/dev/null 2>&1 || mv $@.tmp $@
+	cat constants-hdr $@.tmp.2 > $@
 	$(RM) $@.tmp*
 
+# Only update include/asm-arm/constants.h when it has actually changed.
+
+$(TOPDIR)/include/asm-arm/constants.h: constants.h
+	cmp constants.h $@ >/dev/null 2>&1 || cp -p constants.h $@
+
 # Build our dependencies, and then generate the constants and
 # mach-types header files.  If we do it now, mkdep will pick
 # the dependencies up later on when it runs through the other
@@ -29,7 +33,7 @@
 
 dep:
 	$(TOPDIR)/scripts/mkdep $(CFLAGS) $(EXTRA_CFLAGS) -- getconstants.c |\
-	 sed s,getconstants.o,$(TOPDIR)/include/asm-arm/constants.h, > .depend
+	 sed s,getconstants.o,constants.h, > .depend
 	$(MAKE) all
 
 .PHONY:	all dep
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/arm/tools/mach-types linux/arch/arm/tools/mach-types
--- linux.orig/arch/arm/tools/mach-types	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/arm/tools/mach-types	2002-08-01 06:42:43.000000000 +0000
@@ -6,7 +6,7 @@
 # To add an entry into this database, please see Documentation/arm/README,
 # or contact rmk@arm.linux.org.uk
 #
-# Last update: Fri Oct 26 17:37:13 2001
+# Last update: Sat Mar 16 15:56:27 2002
 #
 # machine_is_xxx	CONFIG_xxxx		MACH_TYPE_xxx		number
 #
@@ -118,10 +118,10 @@
 cdb89712		ARCH_CDB89712		CDB89712		107
 graphicsmaster		SA1100_GRAPHICSMASTER	GRAPHICSMASTER		108
 adsbitsy		SA1100_ADSBITSY		ADSBITSY		109
-cotulla_idp		ARCH_COTULLA_IDP	COTULLA_IDP		110
+pxa_idp			ARCH_PXA_IDP		PXA_IDP			110
 plce			ARCH_PLCE		PLCE			111
 pt_system3		SA1100_PT_SYSTEM3	PT_SYSTEM3		112
-medalb			ARCH_MEDALB		MEDALB			113
+murphy			ARCH_MEDALB		MEDALB			113
 eagle			ARCH_EAGLE		EAGLE			114
 dsc21			ARCH_DSC21		DSC21			115
 dsc24			ARCH_DSC24		DSC24			116
@@ -137,3 +137,44 @@
 elroy			SA1100_ELROY		ELROY			126
 gms720			ARCH_GMS720		GMS720			127
 s24x			ARCH_S24X		S24X			128
+jtel_clep7312		ARCH_JTEL_CLEP7312	JTEL_CLEP7312		129
+cx821xx			ARCH_CX821XX		CX821XX			130
+edb7312			ARCH_EDB7312		EDB7312			131
+bsa1110			SA1100_BSA1110		BSA1110			132
+powerpin		ARCH_POWERPIN		POWERPIN		133
+openarm			ARCH_OPENARM		OPENARM			134
+whitechapel		SA1100_WHITECHAPEL	WHITECHAPEL		135
+h3100			SA1100_H3100		H3100			136
+h3800			SA1100_H3800		H3800			137
+blue_v1			ARCH_BLUE_V1		BLUE_V1			138
+pxa_cerf		ARCH_PXA_CERF		PXA_CERF		139
+arm7tevb		ARCH_ARM7TEVB		ARM7TEVB		140
+d7400			ARCH_D7400		D7400			141
+piranha			ARCH_PIRANHA		PIRANHA			142
+sbcamelot		SA1100_SBCAMELOT	SBCAMELOT		143
+kings			SA1100_KINGS		KINGS			144
+smdk2400		ARCH_SMDK2400		SMDK2400		145
+collie			ARCH_COLLIE		COLLIE			146
+idr			ARCH_IDR		IDR			147
+badge4			SA1100_BADGE4		BADGE4			148
+webnet			ARCH_WEBNET		WEBNET			149
+d7300			SA1100_D7300		D7300			150
+cep			SA1100_CEP		CEP			151
+fortunet		ARCH_FORTUNET		FORTUNET		152
+vc547x			ARCH_VC547X		VC547X			153
+filewalker		SA1100_FILEWALKER	FILEWALKER		154
+netgateway		SA1100_NETGATEWAY	NETGATEWAY		155
+symbol2800		SA1100_SYMBOL2800	SYMBOL2800		156
+suns			SA1100_SUNS		SUNS			157
+frodo			SA1100_FRODO		FRODO			158
+ms301			SA1100_MACH_TYTE_MS301	MACH_TYTE_MS301		159
+mx1ads			ARCH_MX1ADS		MX1ADS			160
+h7201			ARCH_H7201		H7201			161
+h7202			ARCH_H7202		H7202			162
+amico			ARCH_AMICO		AMICO			163
+iam			SA1100_IAM		IAM			164
+tt530			SA1100_TT530		TT530			165
+sam2400			ARCH_SAM2400		SAM2400			166
+jornada56x		ARCH_JORNADA56X		JORNADA56X		167
+active			SA1100_ACTIVE		ACTIVE			168
+iq80321			ARCH_IQ80321		IQ80321			169
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/Makefile linux/arch/cris/Makefile
--- linux.orig/arch/cris/Makefile	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/Makefile	2002-08-01 06:42:43.000000000 +0000
@@ -1,4 +1,4 @@
-# $Id: Makefile,v 1.26 2001/11/16 17:42:17 pkj Exp $
+# $Id: Makefile,v 1.27 2002/03/08 13:08:50 bjornw Exp $
 # cris/Makefile
 #
 # This file is included by the global makefile so that you can add your own
@@ -29,9 +29,9 @@
               -e s/@CONFIG_ETRAX_DRAM_SIZE_M@/$(CONFIG_ETRAX_DRAM_SIZE)/ \
               < $(LD_SCRIPT) > $(LD_SCRIPT).tmp; \
      else true; \
-     fi && $(CROSS_COMPILE)gcc -mlinux -nostdlib
+     fi && $(CROSS_COMPILE)ld -mcrislinux
 
-LINKFLAGS = -mlinux -T $(LD_SCRIPT).tmp
+LINKFLAGS = -T $(LD_SCRIPT).tmp
 
 # objcopy is used to make binary images from the resulting linked file
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/defconfig linux/arch/cris/defconfig
--- linux.orig/arch/cris/defconfig	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/cris/defconfig	2002-08-01 06:42:37.000000000 +0000
@@ -99,6 +99,7 @@
 CONFIG_MTD_CFI=y
 # CONFIG_MTD_CFI_INTELEXT is not set
 CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_OBSOLETE_CHIPS=y
 CONFIG_MTD_AMDSTD=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/Config.in linux/arch/cris/drivers/Config.in
--- linux.orig/arch/cris/drivers/Config.in	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/cris/drivers/Config.in	2002-08-01 06:42:35.000000000 +0000
@@ -143,6 +143,7 @@
 	define_bool CONFIG_MTD_CFI_INTELEXT n
 	define_bool CONFIG_MTD_CFI_AMDSTD y
 
+	define_bool CONFIG_MTD_OBSOLETE_CHIPS y
 	define_bool CONFIG_MTD_AMDSTD y
 
 	define_bool CONFIG_MTD_CHAR y
@@ -178,7 +179,7 @@
 bool 'ARTPEC-1 support' CONFIG_JULIETTE
 
 if [ "$CONFIG_JULIETTE" = "y" ]; then
-   source arch/cris/drivers/juliette/Config.in
+
 fi
 
 bool 'USB host' CONFIG_ETRAX_USB_HOST
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/axisflashmap.c linux/arch/cris/drivers/axisflashmap.c
--- linux.orig/arch/cris/drivers/axisflashmap.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/drivers/axisflashmap.c	2002-08-01 06:42:47.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * Physical mapping layer for MTD using the Axis partitiontable format
  *
- * Copyright (c) 2001 Axis Communications AB
+ * Copyright (c) 2001, 2002 Axis Communications AB
  *
  * This file is under the GPL.
  *
@@ -11,6 +11,27 @@
  * partition split defined below.
  *
  * $Log: axisflashmap.c,v $
+ * Revision 1.23  2002/05/13 12:12:28  johana
+ * Allow compile without CONFIG_MTD_MTDRAM but warn at compiletime and
+ * be informative at runtime.
+ *
+ * Revision 1.22  2002/05/13 10:24:44  johana
+ * Added #if checks on MTDRAM CONFIG
+ *
+ * Revision 1.21  2002/05/06 16:05:20  johana
+ * Removed debug printout.
+ *
+ * Revision 1.20  2002/05/06 16:03:00  johana
+ * No more cramfs as root hack in generic code.
+ * It's handled by axisflashmap using mtdram.
+ *
+ * Revision 1.19  2002/03/15 17:10:28  bjornw
+ * Changed comment about cached access since we changed this before
+ *
+ * Revision 1.18  2002/03/05 17:06:15  jonashg
+ * Try amd_flash probe before cfi_probe since amd_flash driver can handle two
+ * (or more) flash chips of different model and the cfi driver cannot.
+ *
  * Revision 1.17  2001/11/12 19:42:38  pkj
  * Fixed compiler warnings.
  *
@@ -80,6 +101,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mtd/mtdram.h>
 
 #include <asm/axisflashmap.h>
 #include <asm/mmu.h>
@@ -106,9 +128,8 @@
 /* 
  * Map driver
  *
- * Ok this is the scoop - we need to access the flash both with and without
- * the cache - without when doing all the fancy flash interfacing, and with
- * when we do actual copying because otherwise it will be slow like molasses.
+ * We run into tricky coherence situations if we mix cached with uncached
+ * accesses to we use the uncached version here.
  */
 
 static __u8 flash_read8(struct map_info *map, unsigned long ofs)
@@ -239,6 +260,7 @@
 static int __init
 init_axis_flash(void)
 {
+	int err = 0;
 	int pidx = 0;
 	struct partitiontable_head *ptable_head;
 	struct partitiontable_entry *ptable;
@@ -247,14 +269,13 @@
 
 	printk(KERN_NOTICE "Axis flash mapping: %x at %lx\n",
 	       WINDOW_SIZE, FLASH_CACHED_ADDR);
-
-#ifdef CONFIG_MTD_CFI
-	mymtd = (struct mtd_info *)do_map_probe("cfi_probe", &axis_map);
+#ifdef CONFIG_MTD_AMDSTD
+	mymtd = (struct mtd_info *)do_map_probe("amd_flash", &axis_map);
 #endif
 
-#ifdef CONFIG_MTD_AMDSTD
+#ifdef CONFIG_MTD_CFI
 	if (!mymtd) {
-		mymtd = (struct mtd_info *)do_map_probe("amd_flash", &axis_map);
+		mymtd = (struct mtd_info *)do_map_probe("cfi_probe", &axis_map);
 	}
 #endif
 
@@ -333,8 +354,8 @@
 
 	if (use_default_ptable) {
 		printk(" Using default partition table\n");
-		return add_mtd_partitions(mymtd, axis_default_partitions,
-					  NUM_DEFAULT_PARTITIONS);
+		err = add_mtd_partitions(mymtd, axis_default_partitions,
+		                         NUM_DEFAULT_PARTITIONS);
 	} else {
 		if (romfs_in_flash) {
 			axis_partitions[pidx].name = "romfs";
@@ -348,8 +369,39 @@
 			       axis_partitions[pidx].size);
 			pidx++;
 		}
-		return add_mtd_partitions(mymtd, axis_partitions, pidx);
-	}		
+
+		err = add_mtd_partitions(mymtd, axis_partitions, pidx);
+	}
+	if (!err && !romfs_in_flash) {
+#ifdef CONFIG_MTD_MTDRAM
+		/* Allocate, initialise and forget the mtd ram struct
+		 * when booting from RAM
+		 */
+		struct mtd_info *romfs_mtd = (struct mtd_info *)kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
+		printk("MTD RAM device romfs_start: 0x%08lX len %lu\n",
+		       romfs_start, romfs_length);
+
+#if (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0)
+#error "You must set CONFIG_MTDRAM_TOTAL_SIZE and CONFIG_MTDRAM_ABS_POS to 0"
+#endif
+		err = mtdram_init_device(romfs_mtd, (void*)romfs_start, 
+		                         romfs_length, "romfs in RAM");
+#else
+#warning ######################################
+#warning # You must enable CONFIG_MTD_MTDRAM  #
+#warning # with TOTAL_SIZE 0 and ABS_POS 0 to # 
+#warning # be able to boot with cramfs in RAM #
+#warning ######################################
+/* Maybe overkill to save these bytes in non debug builds, but let's do it..
+ * (No point in printing if we don't have a debug port anyway...)
+ */
+#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL
+		printk("## Can't mount romfs in RAM using MTDRAM.\n");
+		printk("## You must enable MTD_MTDRAM with TOTAL_SIZE 0 and ABS_POS 0\n");
+#endif
+#endif /* CONFIG_MTD_MTDRAM */
+	}
+	return err;
 }
 
 /* This adds the above to the kernels init-call chain */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/bluetooth/Makefile linux/arch/cris/drivers/bluetooth/Makefile
--- linux.orig/arch/cris/drivers/bluetooth/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/cris/drivers/bluetooth/Makefile	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,26 @@
+include $(APPS)/Rules.elinux
+
+all:
+
+install:	src/bluetooth.c include/btcommon.h
+	ln -sfn ../../arch/cris/drivers/bluetooth/include ../../../../include/linux/bluetooth
+	if ! grep arch/cris/drivers/bluetooth/src/Config.in ../Config.in; then \
+	  echo '' >> ../Config.in; \
+	  echo '# The following if statement was added by arch/cris/drivers/bluetooth/Makefile' >> ../Config.in; \
+	  echo 'if [ "$$CONFIG_ETRAX_SERIAL" = "y" ]; then' >> ../Config.in; \
+	  echo '  source arch/cris/drivers/bluetooth/src/Config.in' >> ../Config.in; \
+	  echo 'fi' >> ../Config.in; \
+	fi
+	if ! grep bluetooth/src/bt.o ../Makefile; then \
+	  perl -pi -e "s:include:\# The following two lines were added by arch/cris/drivers/bluetooth/Makefile\nobj-\\\$$(CONFIG_BLUETOOTH)                 += bluetooth/src/bt.o\nsubdir-\\\$$(CONFIG_BLUETOOTH)              += bluetooth/src\n\ninclude:" ../Makefile; \
+	fi
+
+clean:
+
+src/bluetooth.c:
+	@echo "You must install the OpenBT src directory before install can be done here!"
+	@exit 1
+
+include/btcommon.h:
+	@echo "You must install the OpenBT include directory before install can be done here!"
+	@exit 1
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/ds1302.c linux/arch/cris/drivers/ds1302.c
--- linux.orig/arch/cris/drivers/ds1302.c	2001-07-04 18:50:38.000000000 +0000
+++ linux/arch/cris/drivers/ds1302.c	2002-08-01 06:42:47.000000000 +0000
@@ -7,6 +7,9 @@
 *! Functions exported: ds1302_readreg, ds1302_writereg, ds1302_init, get_rtc_status
 *!
 *! $Log: ds1302.c,v $
+*! Revision 1.12  2002/04/10 15:35:25  johana
+*! Moved probe function closer to init function and marked it __init.
+*!
 *! Revision 1.11  2001/06/14 12:35:52  jonashg
 *! The ATA hack is back. It is unfortunately the only way to set g27 to output.
 *!
@@ -82,7 +85,7 @@
 *!
 *! (C) Copyright 1999, 2000, 2001  Axis Communications AB, LUND, SWEDEN
 *!
-*! $Id: ds1302.c,v 1.11 2001/06/14 12:35:52 jonashg Exp $
+*! $Id: ds1302.c,v 1.12 2002/04/10 15:35:25 johana Exp $
 *!
 *!***************************************************************************/
 
@@ -228,54 +231,6 @@
 	stop();
 }
 
-/* Probe for the chip by writing something to its RAM and try reading it back. */
-
-#define MAGIC_PATTERN 0x42
-
-static int
-ds1302_probe(void) 
-{
-	int retval, res; 
-
-	TK_RST_DIR(1);
-	TK_SCL_DIR(1);
-	TK_SDA_DIR(0);
-	
-	/* Try to talk to timekeeper. */
-
-	ds1302_wenable();  
-	start();
-	out_byte(0xc0); /* write RAM byte 0 */	
-	out_byte(MAGIC_PATTERN); /* write something magic */
-	start();
-	out_byte(0xc1); /* read RAM byte 0 */
-
-	if((res = in_byte()) == MAGIC_PATTERN) {
-		char buf[100];
-		stop();
-		ds1302_wdisable();
-		printk("%s: RTC found.\n", ds1302_name);
-		printk("%s: SDA, SCL, RST on PB%i, PB%i, %s%i\n",
-		       ds1302_name,
-		       CONFIG_ETRAX_DS1302_SDABIT,
-		       CONFIG_ETRAX_DS1302_SCLBIT,
-#ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT
-		       "GENIO",
-#else
-		       "PB",
-#endif
-		       CONFIG_ETRAX_DS1302_RSTBIT);
-                get_rtc_status(buf);
-                printk(buf);
-		retval = 1;
-	} else {
-		stop();
-		printk("%s: RTC not found.\n", ds1302_name);
-		retval = 0;
-	}
-
-	return retval;
-}
 
 
 /* Read a byte from the selected register in the DS1302. */
@@ -480,6 +435,56 @@
         ioctl:          rtc_ioctl,	
 }; 
 
+/* Probe for the chip by writing something to its RAM and try reading it back. */
+
+#define MAGIC_PATTERN 0x42
+
+static int __init
+ds1302_probe(void) 
+{
+	int retval, res; 
+
+	TK_RST_DIR(1);
+	TK_SCL_DIR(1);
+	TK_SDA_DIR(0);
+	
+	/* Try to talk to timekeeper. */
+
+	ds1302_wenable();  
+	start();
+	out_byte(0xc0); /* write RAM byte 0 */	
+	out_byte(MAGIC_PATTERN); /* write something magic */
+	start();
+	out_byte(0xc1); /* read RAM byte 0 */
+
+	if((res = in_byte()) == MAGIC_PATTERN) {
+		char buf[100];
+		stop();
+		ds1302_wdisable();
+		printk("%s: RTC found.\n", ds1302_name);
+		printk("%s: SDA, SCL, RST on PB%i, PB%i, %s%i\n",
+		       ds1302_name,
+		       CONFIG_ETRAX_DS1302_SDABIT,
+		       CONFIG_ETRAX_DS1302_SCLBIT,
+#ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT
+		       "GENIO",
+#else
+		       "PB",
+#endif
+		       CONFIG_ETRAX_DS1302_RSTBIT);
+                get_rtc_status(buf);
+                printk(buf);
+		retval = 1;
+	} else {
+		stop();
+		printk("%s: RTC not found.\n", ds1302_name);
+		retval = 0;
+	}
+
+	return retval;
+}
+
+
 /* Just probe for the RTC and register the device to handle the ioctl needed. */
 
 int __init
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/ethernet.c linux/arch/cris/drivers/ethernet.c
--- linux.orig/arch/cris/drivers/ethernet.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/drivers/ethernet.c	2002-08-01 06:42:42.000000000 +0000
@@ -1,12 +1,52 @@
-/* $Id: ethernet.c,v 1.22 2002/01/30 07:48:22 matsfg Exp $
+/* $Id: ethernet.c,v 1.30 2002/05/07 18:50:08 johana Exp $
  *
  * e100net.c: A network driver for the ETRAX 100LX network controller.
  *
- * Copyright (c) 1998-2001 Axis Communications AB.
+ * Copyright (c) 1998-2002 Axis Communications AB.
  *
  * The outline of this driver comes from skeleton.c.
  *
  * $Log: ethernet.c,v $
+ * Revision 1.30  2002/05/07 18:50:08  johana
+ * Correct spelling in comments.
+ *
+ * Revision 1.29  2002/05/06 05:38:49  starvik
+ * Performance improvements:
+ *    Large packets are not copied (breakpoint set to 256 bytes)
+ *    The cache bug workaround is delayed until half of the receive list
+ *      has been used
+ *    Added transmit list
+ *    Transmit interrupts are only enabled when transmit queue is full
+ *
+ * Revision 1.28.2.1  2002/04/30 08:15:51  starvik
+ * Performance improvements:
+ *   Large packets are not copied (breakpoint set to 256 bytes)
+ *   The cache bug workaround is delayed until half of the receive list
+ *     has been used.
+ *   Added transmit list
+ *   Transmit interrupts are only enabled when transmit queue is full
+ *
+ * Revision 1.28  2002/04/22 11:47:21  johana
+ * Fix according to 2.4.19-pre7. time_after/time_before and
+ * missing end of comment.
+ * The patch has a typo for ethernet.c in e100_clear_network_leds(),
+ *  that is fixed here.
+ *
+ * Revision 1.27  2002/04/12 11:55:11  bjornw
+ * Added TODO
+ *
+ * Revision 1.26  2002/03/15 17:11:02  bjornw
+ * Use prepare_rx_descriptor after the CPU has touched the receiving descs
+ *
+ * Revision 1.25  2002/03/08 13:07:53  bjornw
+ * Unnecessary spinlock removed
+ *
+ * Revision 1.24  2002/02/20 12:57:43  fredriks
+ * Replaced MIN() with min().
+ *
+ * Revision 1.23  2002/02/20 10:58:14  fredriks
+ * Strip the Ethernet checksum (4 bytes) before forwarding a frame to upper layers.
+ *
  * Revision 1.22  2002/01/30 07:48:22  matsfg
  * Initiate R_NETWORK_TR_CTRL
  *
@@ -127,7 +167,6 @@
 //#define ETHDEBUG
 #define D(x)
 
-
 /*
  * The name of the card. Is used for messages and in the requests for
  * io regions, irqs and dma channels
@@ -154,6 +193,11 @@
 	spinlock_t lock;
 };
 
+typedef struct etrax_eth_descr
+{
+	etrax_dma_descr descr;
+	struct sk_buff* skb;
+} etrax_eth_descr;
 
 /* Duplex settings */
 enum duplex
@@ -165,8 +209,6 @@
 
 /* Dma descriptors etc. */
 
-#define RX_BUF_SIZE 32768
-
 #define MAX_MEDIA_DATA_SIZE 1518
 
 #define MIN_PACKET_LEN      46
@@ -207,9 +249,17 @@
 #define NO_NETWORK_ACTIVITY 0
 #define NETWORK_ACTIVITY    1
 
-#define RX_DESC_BUF_SIZE   256
-#define NBR_OF_RX_DESC     (RX_BUF_SIZE / \
-                            RX_DESC_BUF_SIZE)
+#define NBR_OF_RX_DESC     64
+#define NBR_OF_TX_DESC     256
+
+/* Large packets are sent directly to upper layers while small packets are */
+/* copied (to reduce memory waste). The following constant decides the breakpoint */
+#define RX_COPYBREAK 256
+
+/* Due to a chip bug we need to flush the cache when descriptors are returned */
+/* to the DMA. To decrease performance impact we return descriptors in chunks. */
+/* The following constant determines the number of descriptors to return. */
+#define RX_QUEUE_THRESHOLD  NBR_OF_RX_DESC/2
 
 #define GET_BIT(bit,val)   (((val) >> (bit)) & 0x01)
 
@@ -219,17 +269,17 @@
 #define SETS(var, reg, field, val) var = (var & ~IO_MASK(##reg##, field)) | \
 					  IO_STATE(##reg##, field, val)
 
-static etrax_dma_descr *myNextRxDesc;  /* Points to the next descriptor to
+static etrax_eth_descr *myNextRxDesc;  /* Points to the next descriptor to
                                           to be processed */
-static etrax_dma_descr *myLastRxDesc;  /* The last processed descriptor */
-static etrax_dma_descr *myPrevRxDesc;  /* The descriptor right before myNextRxDesc */
+static etrax_eth_descr *myLastRxDesc;  /* The last processed descriptor */
+static etrax_eth_descr *myPrevRxDesc;  /* The descriptor right before myNextRxDesc */
 
-static unsigned char RxBuf[RX_BUF_SIZE];
+static etrax_eth_descr RxDescList[NBR_OF_RX_DESC] __attribute__ ((aligned(32)));
 
-static etrax_dma_descr RxDescList[NBR_OF_RX_DESC] __attribute__ ((aligned(4)));
-static etrax_dma_descr TxDesc __attribute__ ((aligned(4)));
-
-static struct sk_buff *tx_skb;
+static etrax_eth_descr* myFirstTxDesc; /* First packet not yet sent */
+static etrax_eth_descr* myLastTxDesc;  /* End of send queue */
+static etrax_eth_descr* myNextTxDesc;  /* Next descriptor to use */
+static etrax_eth_descr TxDescList[NBR_OF_TX_DESC] __attribute__ ((aligned(32)));
 
 static unsigned int network_rec_config_shadow = 0;
 
@@ -240,6 +290,7 @@
 static int current_speed_selection; /* Speed selected by user */
 static int led_next_time;
 static int led_active;
+static int rx_queue_len;
 
 /* Duplex */
 static struct timer_list duplex_timer;
@@ -295,7 +346,6 @@
 etrax_ethernet_init(struct net_device *dev)
 {
 	int i;
-	int anOffset = 0;
 
 	printk("ETRAX 100LX 10/100MBit ethernet v2.0 (c) 2000-2001 Axis Communications AB\n");
 
@@ -348,28 +398,44 @@
 
 	/* Initialise receive descriptors */
 
-	for (i = 0; i < (NBR_OF_RX_DESC - 1); i++) {
-		RxDescList[i].ctrl   = 0;
-		RxDescList[i].sw_len = RX_DESC_BUF_SIZE;
-		RxDescList[i].next   = virt_to_phys(&RxDescList[i + 1]);
-		RxDescList[i].buf    = virt_to_phys(RxBuf + anOffset);
-		RxDescList[i].status = 0;
-		RxDescList[i].hw_len = 0;
-		anOffset += RX_DESC_BUF_SIZE;
-	}
-
-	RxDescList[i].ctrl   = d_eol;
-	RxDescList[i].sw_len = RX_DESC_BUF_SIZE;
-	RxDescList[i].next   = virt_to_phys(&RxDescList[0]);
-	RxDescList[i].buf    = virt_to_phys(RxBuf + anOffset);
-	RxDescList[i].status = 0;
-	RxDescList[i].hw_len = 0;
+	for (i = 0; i < NBR_OF_RX_DESC; i++) {
+		RxDescList[i].skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
+		RxDescList[i].descr.ctrl   = 0;
+		RxDescList[i].descr.sw_len = MAX_MEDIA_DATA_SIZE;
+		RxDescList[i].descr.next   = virt_to_phys(&RxDescList[i + 1]);
+		RxDescList[i].descr.buf    = virt_to_phys(RxDescList[i].skb->data);
+		RxDescList[i].descr.status = 0;
+		RxDescList[i].descr.hw_len = 0;
+             
+		prepare_rx_descriptor(&RxDescList[i].descr);
+	}
+
+	RxDescList[NBR_OF_RX_DESC - 1].descr.ctrl   = d_eol;
+	RxDescList[NBR_OF_RX_DESC - 1].descr.next   = virt_to_phys(&RxDescList[0]);
+	rx_queue_len = 0;
+
+	/* Initialize transmit descriptors */
+	for (i = 0; i < NBR_OF_TX_DESC; i++) {
+		TxDescList[i].descr.ctrl   = 0;
+		TxDescList[i].descr.sw_len = 0;
+		TxDescList[i].descr.next   = virt_to_phys(&TxDescList[i + 1].descr);
+		TxDescList[i].descr.buf    = 0;
+		TxDescList[i].descr.status = 0;
+		TxDescList[i].descr.hw_len = 0;
+		TxDescList[i].skb = 0;
+	}
 
+	TxDescList[NBR_OF_TX_DESC - 1].descr.ctrl   = d_eol;
+	TxDescList[NBR_OF_TX_DESC - 1].descr.next   = virt_to_phys(&TxDescList[0].descr);
+        
 	/* Initialise initial pointers */
 
-	myNextRxDesc = &RxDescList[0];
-	myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1];
-	myPrevRxDesc = &RxDescList[NBR_OF_RX_DESC - 1];
+	myNextRxDesc  = &RxDescList[0];
+	myLastRxDesc  = &RxDescList[NBR_OF_RX_DESC - 1];
+	myPrevRxDesc  = &RxDescList[NBR_OF_RX_DESC - 1];
+	myFirstTxDesc = &TxDescList[0];
+	myNextTxDesc  = &TxDescList[0];
+	myLastTxDesc  = &TxDescList[NBR_OF_TX_DESC - 1];
 
 	/* Initialize speed indicator stuff. */
 
@@ -530,14 +596,14 @@
 		IO_STATE(R_NETWORK_GEN_CONFIG, phy,    mii_clk) |
 		IO_STATE(R_NETWORK_GEN_CONFIG, enable, on);
 
-        *R_NETWORK_TR_CTRL = 
-                IO_STATE(R_NETWORK_TR_CTRL, clr_error, clr) |
-                IO_STATE(R_NETWORK_TR_CTRL, delay, none) |
-                IO_STATE(R_NETWORK_TR_CTRL, cancel, dont) |
-                IO_STATE(R_NETWORK_TR_CTRL, cd, enable) |
-                IO_STATE(R_NETWORK_TR_CTRL, retry, enable) |
-                IO_STATE(R_NETWORK_TR_CTRL, pad, enable) |
-                IO_STATE(R_NETWORK_TR_CTRL, crc, enable);
+	*R_NETWORK_TR_CTRL = 
+		IO_STATE(R_NETWORK_TR_CTRL, clr_error, clr) |
+		IO_STATE(R_NETWORK_TR_CTRL, delay, none) |
+		IO_STATE(R_NETWORK_TR_CTRL, cancel, dont) |
+		IO_STATE(R_NETWORK_TR_CTRL, cd, enable) |
+		IO_STATE(R_NETWORK_TR_CTRL, retry, enable) |
+		IO_STATE(R_NETWORK_TR_CTRL, pad, enable) |
+		IO_STATE(R_NETWORK_TR_CTRL, crc, enable);
 
 	save_flags(flags);
 	cli();
@@ -545,16 +611,13 @@
 	/* enable the irq's for ethernet DMA */
 
 	*R_IRQ_MASK2_SET =
-		IO_STATE(R_IRQ_MASK2_SET, dma0_eop, set) |
-		IO_STATE(R_IRQ_MASK2_SET, dma1_eop, set);
+		IO_STATE(R_IRQ_MASK2_SET, dma1_eop, set); 
 
 	*R_IRQ_MASK0_SET =
 		IO_STATE(R_IRQ_MASK0_SET, overrun,       set) |
 		IO_STATE(R_IRQ_MASK0_SET, underrun,      set) |
 		IO_STATE(R_IRQ_MASK0_SET, excessive_col, set);
 
-	tx_skb = 0;
-
 	/* make sure the irqs are cleared */
 
 	*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);
@@ -570,6 +633,11 @@
 	*R_DMA_CH1_FIRST = virt_to_phys(myNextRxDesc);
 	*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, start);
 
+	/* Set up transmit DMA channel so it can be restarted later */
+        
+	*R_DMA_CH0_FIRST = 0;
+	*R_DMA_CH0_DESCR = virt_to_phys(myLastTxDesc);
+
 	restore_flags(flags);
 	
 	/* We are now ready to accept transmit requeusts from
@@ -839,11 +907,18 @@
 	
 	e100_reset_tranceiver();
 	
-	/* and get rid of the packet that never got an interrupt */
-	
-	dev_kfree_skb(tx_skb);
-	tx_skb = 0;
-	
+	/* and get rid of the packets that never got an interrupt */
+	while (myFirstTxDesc != myNextTxDesc)
+	{
+		dev_kfree_skb(myFirstTxDesc->skb);
+		myFirstTxDesc->skb = 0;
+		myFirstTxDesc = phys_to_virt(myFirstTxDesc->descr.next);
+	}
+
+	/* Set up transmit DMA channel so it can be restarted later */
+	*R_DMA_CH0_FIRST = 0;
+	*R_DMA_CH0_DESCR = virt_to_phys(myLastTxDesc);	
+
 	/* tell the upper layers we're ok again */
 	
 	netif_wake_queue(dev);
@@ -866,19 +941,38 @@
 #ifdef ETHDEBUG
 	printk("send packet len %d\n", length);
 #endif
-	spin_lock_irq(&np->lock);  /* protect from tx_interrupt */
+	spin_lock_irq(&np->lock);  /* protect from tx_interrupt and ourself */
+
+	myNextTxDesc->skb = skb;
 
-	tx_skb = skb; /* remember it so we can free it in the tx irq handler later */
 	dev->trans_start = jiffies;
 	
 	e100_hardware_send_packet(buf, length);
 
-	/* this simple TX driver has only one send-descriptor so we're full
-	 * directly. If this had a send-ring instead, we would only do this if
-	 * the ring got full.
-	 */
+	myNextTxDesc = phys_to_virt(myNextTxDesc->descr.next);
 
-	netif_stop_queue(dev);
+	/* Stop queue if full */
+	if (myNextTxDesc == myFirstTxDesc) {
+		/* Enable transmit interrupt to wake up queue */
+		*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);		
+		*R_IRQ_MASK2_SET = IO_STATE(R_IRQ_MASK2_SET, dma0_eop, set);
+		netif_stop_queue(dev);
+	}
+	else {
+	  /* Report any packets that have been sent */
+		while (myFirstTxDesc != phys_to_virt(*R_DMA_CH0_FIRST) &&
+		       myFirstTxDesc != myNextTxDesc)
+		{
+			np->stats.tx_bytes += myFirstTxDesc->skb->len;
+			np->stats.tx_packets++;
+
+			/* dma is ready with the transmission of the data in tx_skb, so now
+			   we can release the skb memory */
+			dev_kfree_skb(myFirstTxDesc->skb);
+			myFirstTxDesc->skb = 0;
+			myFirstTxDesc = phys_to_virt(myFirstTxDesc->descr.next);				
+		}
+	}
 
 	spin_unlock_irq(&np->lock);
 
@@ -936,31 +1030,28 @@
 	struct net_local *np = (struct net_local *)dev->priv;
 
 	/* check for a dma0_eop interrupt */
-	if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma0_eop, active)) { 
-		/* This protects us from concurrent execution of
-		 * our dev->hard_start_xmit function above.
-		 */
-
-		spin_lock(&np->lock);
-		
-		/* acknowledge the eop interrupt */
-
-		*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);
+	if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma0_eop, active)) {
+		/* Report all sent packets */
+		do {
+			/* acknowledge the eop interrupt */
+			*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);
 
-		if (*R_DMA_CH0_FIRST == 0 && tx_skb) {
-			np->stats.tx_bytes += tx_skb->len;
+			np->stats.tx_bytes += myFirstTxDesc->skb->len;
 			np->stats.tx_packets++;
+
 			/* dma is ready with the transmission of the data in tx_skb, so now
 			   we can release the skb memory */
-			dev_kfree_skb_irq(tx_skb);
-			tx_skb = 0;
-			netif_wake_queue(dev);
-		} else {
-			printk(KERN_WARNING "%s: tx weird interrupt\n",
-			       cardname);
-		}
+			dev_kfree_skb_irq(myFirstTxDesc->skb);
+			myFirstTxDesc->skb = 0;
 
-		spin_unlock(&np->lock);
+			if (netif_queue_stopped(dev)) {
+			  	/* Queue is running, disable tx IRQ */
+			  	*R_IRQ_MASK2_CLR = IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr);		
+				netif_wake_queue(dev);
+			}
+			myFirstTxDesc = phys_to_virt(myFirstTxDesc->descr.next);
+		} while (myFirstTxDesc != phys_to_virt(*R_DMA_CH0_FIRST) &&
+		         myFirstTxDesc != myNextTxDesc);
 	}
 }
 
@@ -989,7 +1080,6 @@
 		np->stats.tx_errors++;
 		D(printk("ethernet excessive collisions!\n"));
 	}
-
 }
 
 /* We have a good packet(s), get it/them out of the buffers. */
@@ -999,13 +1089,12 @@
 	struct sk_buff *skb;
 	int length = 0;
 	struct net_local *np = (struct net_local *)dev->priv;
-	struct etrax_dma_descr *mySaveRxDesc = myNextRxDesc;
 	unsigned char *skb_data_ptr;
 #ifdef ETHDEBUG
 	int i;
 #endif
 
-	if (!led_active && jiffies > led_next_time) {
+	if (!led_active && time_after(jiffies, led_next_time)) {
 		/* light the network leds depending on the current speed. */
 		e100_set_network_leds(NETWORK_ACTIVITY);
 
@@ -1015,24 +1104,13 @@
 		mod_timer(&clear_led_timer, jiffies + HZ/10);
 	}
 
-	/* If the packet is broken down in many small packages then merge
-	 * count how much space we will need to alloc with skb_alloc() for
-	 * it to fit.
-	 */
-
-	while (!(myNextRxDesc->status & d_eop)) {
-		length += myNextRxDesc->sw_len; /* use sw_len for the first descs */
-		myNextRxDesc->status = 0;
-		myNextRxDesc = phys_to_virt(myNextRxDesc->next);
-	}
-
-	length += myNextRxDesc->hw_len; /* use hw_len for the last descr */
+	length = myNextRxDesc->descr.hw_len - 4;
 	((struct net_local *)dev->priv)->stats.rx_bytes += length;
 
 #ifdef ETHDEBUG
 	printk("Got a packet of length %d:\n", length);
 	/* dump the first bytes in the packet */
-	skb_data_ptr = (unsigned char *)phys_to_virt(mySaveRxDesc->buf);
+	skb_data_ptr = (unsigned char *)phys_to_virt(myNextRxDesc->descr.buf);
 	for (i = 0; i < 8; i++) {
 		printk("%d: %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x\n", i * 8,
 		       skb_data_ptr[0],skb_data_ptr[1],skb_data_ptr[2],skb_data_ptr[3],
@@ -1041,53 +1119,55 @@
 	}
 #endif
 
-	skb = dev_alloc_skb(length - ETHER_HEAD_LEN);
-	if (!skb) {
-		np->stats.rx_errors++;
-		printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
-		       dev->name);
-		return;
-	}
+	if (length < RX_COPYBREAK) {
+		/* Small packet, copy data */
+		skb = dev_alloc_skb(length - ETHER_HEAD_LEN);
+		if (!skb) {
+			np->stats.rx_errors++;
+			printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
+			return;
+		}
 
-	skb_put(skb, length - ETHER_HEAD_LEN);        /* allocate room for the packet body */
-	skb_data_ptr = skb_push(skb, ETHER_HEAD_LEN); /* allocate room for the header */
+		skb_put(skb, length - ETHER_HEAD_LEN);        /* allocate room for the packet body */
+		skb_data_ptr = skb_push(skb, ETHER_HEAD_LEN); /* allocate room for the header */
 
 #ifdef ETHDEBUG
-	printk("head = 0x%x, data = 0x%x, tail = 0x%x, end = 0x%x\n",
-	       skb->head, skb->data, skb->tail, skb->end);
-	printk("copying packet to 0x%x.\n", skb_data_ptr);
+		printk("head = 0x%x, data = 0x%x, tail = 0x%x, end = 0x%x\n",
+		  skb->head, skb->data, skb->tail, skb->end);
+		printk("copying packet to 0x%x.\n", skb_data_ptr);
 #endif
-
-	/* this loop can be made using max two memcpy's if optimized */
-
-	while (mySaveRxDesc != myNextRxDesc) {
-		memcpy(skb_data_ptr, phys_to_virt(mySaveRxDesc->buf),
-		       mySaveRxDesc->sw_len);
-		skb_data_ptr += mySaveRxDesc->sw_len;
-		mySaveRxDesc = phys_to_virt(mySaveRxDesc->next);
+          
+		memcpy(skb_data_ptr, phys_to_virt(myNextRxDesc->descr.buf), length);
+	}
+	else {
+		/* Large packet, send directly to upper layers and allocate new memory */		 
+		skb = myNextRxDesc->skb;
+		skb_put(skb, length);
+		myNextRxDesc->skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
+		myNextRxDesc->descr.buf = virt_to_phys(myNextRxDesc->skb->data);
 	}
-
-	memcpy(skb_data_ptr, phys_to_virt(mySaveRxDesc->buf),
-	       mySaveRxDesc->hw_len);
 
 	skb->dev = dev;
 	skb->protocol = eth_type_trans(skb, dev);
 
 	/* Send the packet to the upper layers */
-
 	netif_rx(skb);
 
 	/* Prepare for next packet */
-
-	myNextRxDesc->status = 0;
+	myNextRxDesc->descr.status = 0;
 	myPrevRxDesc = myNextRxDesc;
-	myNextRxDesc = phys_to_virt(myNextRxDesc->next);
+	myNextRxDesc = phys_to_virt(myNextRxDesc->descr.next);
 
-	myPrevRxDesc->ctrl |= d_eol;
-	myLastRxDesc->ctrl &= ~d_eol;
-	myLastRxDesc = myPrevRxDesc;
+	rx_queue_len++;
 
-	return;
+	/* Check if descriptors should be returned */
+	if (rx_queue_len == RX_QUEUE_THRESHOLD) {
+		flush_etrax_cache();
+		myPrevRxDesc->descr.ctrl |= d_eol;
+		myLastRxDesc->descr.ctrl &= ~d_eol;
+		myLastRxDesc = myPrevRxDesc;
+		rx_queue_len = 0;
+	}
 }
 
 /* The inverse routine to net_open(). */
@@ -1297,7 +1377,7 @@
 {
 	D(printk("e100 send pack, buf 0x%x len %d\n", buf, length));
 
-	if (!led_active && jiffies > led_next_time) {
+	if (!led_active && time_after(jiffies, led_next_time)) {
 		/* light the network leds depending on the current speed. */
 		e100_set_network_leds(NETWORK_ACTIVITY);
 
@@ -1308,21 +1388,22 @@
 	}
 
 	/* configure the tx dma descriptor */
+	myNextTxDesc->descr.sw_len = length;
+	myNextTxDesc->descr.ctrl = d_eop | d_eol | d_wait;
+	myNextTxDesc->descr.buf = virt_to_phys(buf);
+
+        /* Move end of list */
+        myLastTxDesc->descr.ctrl &= ~d_eol;
+        myLastTxDesc = myNextTxDesc;
 
-	TxDesc.sw_len = length;
-	TxDesc.ctrl = d_eop | d_eol | d_wait;
-	TxDesc.buf = virt_to_phys(buf);
-
-	/* setup the dma channel and start it */
-
-	*R_DMA_CH0_FIRST = virt_to_phys(&TxDesc);
-	*R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, start);
+	/* Restart DMA channel */
+	*R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, restart);
 }
 
 static void
 e100_clear_network_leds(unsigned long dummy)
 {
-	if (led_active && jiffies > led_next_time) {
+	if (led_active && time_after(jiffies, led_next_time)) {
 		e100_set_network_leds(NO_NETWORK_ACTIVITY);
 
 		/* Set the earliest time we may set the LED */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/gpio.c linux/arch/cris/drivers/gpio.c
--- linux.orig/arch/cris/drivers/gpio.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/drivers/gpio.c	2002-08-01 06:42:27.000000000 +0000
@@ -1,14 +1,26 @@
-/* $Id: gpio.c,v 1.12 2001/11/12 19:42:15 pkj Exp $
+/* $Id: gpio.c,v 1.15 2002/05/06 13:19:13 johana Exp $
  *
  * Etrax general port I/O device
  *
- * Copyright (c) 1999, 2000, 2001 Axis Communications AB
+ * Copyright (c) 1999, 2000, 2001, 2002 Axis Communications AB
  *
  * Authors:    Bjorn Wesen      (initial version)
  *             Ola Knutsson     (LED handling)
- *             Johan Adolfsson  (read/set directions, write)
+ *             Johan Adolfsson  (read/set directions, write, port G)
  *
  * $Log: gpio.c,v $
+ * Revision 1.15  2002/05/06 13:19:13  johana
+ * IO_SETINPUT returns mask with bit set = inputs for PA and PB as well.
+ *
+ * Revision 1.14  2002/04/12 12:01:53  johana
+ * Use global r_port_g_data_shadow.
+ * Moved gpio_init_port_g() closer to gpio_init() and marked it __init.
+ *
+ * Revision 1.13  2002/04/10 12:03:55  johana
+ * Added support for port G /dev/gpiog (minor 3).
+ * Changed indentation on switch cases.
+ * Fixed other spaces to tabs.
+ *
  * Revision 1.12  2001/11/12 19:42:15  pkj
  * * Corrected return values from gpio_leds_ioctl().
  * * Fixed compiler warnings.
@@ -94,14 +106,17 @@
 
 struct gpio_private {
 	struct gpio_private *next;
+	/* These fields are for PA and PB only */
 	volatile unsigned char *port, *shadow;
 	volatile unsigned char *dir, *dir_shadow;
 	unsigned char changeable_dir;
 	unsigned char changeable_bits;
-	unsigned char highalarm, lowalarm;
 	unsigned char clk_mask;
 	unsigned char data_mask;
 	unsigned char write_msb;
+	unsigned char pad1, pad2, pad3;
+	/* These fields are generic */
+	unsigned long highalarm, lowalarm;
 	wait_queue_head_t alarm_wq;
 	int minor;
 };
@@ -110,10 +125,17 @@
 
 static struct gpio_private *alarmlist = 0;
 
-#define NUM_PORTS 2
-static volatile unsigned char *ports[2] = { R_PORT_PA_DATA, R_PORT_PB_DATA };
-static volatile unsigned char *shads[2] = {
-	&port_pa_data_shadow, &port_pb_data_shadow };
+/* Port A and B use 8 bit access, but Port G is 32 bit */
+#define NUM_PORTS (GPIO_MINOR_B+1)
+
+static volatile unsigned char *ports[NUM_PORTS] = { 
+	R_PORT_PA_DATA, 
+	R_PORT_PB_DATA,
+};
+static volatile unsigned char *shads[NUM_PORTS] = {
+	&port_pa_data_shadow, 
+	&port_pb_data_shadow
+};
 
 /* What direction bits that are user changeable 1=changeable*/
 #ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
@@ -131,17 +153,36 @@
 #endif
 
 
-static unsigned char changeable_dir[2] = { CONFIG_ETRAX_PA_CHANGEABLE_DIR,
-                                           CONFIG_ETRAX_PB_CHANGEABLE_DIR };
-static unsigned char changeable_bits[2] = { CONFIG_ETRAX_PA_CHANGEABLE_BITS,
-                                            CONFIG_ETRAX_PB_CHANGEABLE_BITS };
+static unsigned char changeable_dir[NUM_PORTS] = { 
+	CONFIG_ETRAX_PA_CHANGEABLE_DIR,
+	CONFIG_ETRAX_PB_CHANGEABLE_DIR 
+};
+static unsigned char changeable_bits[NUM_PORTS] = { 
+	CONFIG_ETRAX_PA_CHANGEABLE_BITS,
+	CONFIG_ETRAX_PB_CHANGEABLE_BITS 
+};
 
-static volatile unsigned char *dir[2] = { R_PORT_PA_DIR, R_PORT_PB_DIR };
+static volatile unsigned char *dir[NUM_PORTS] = { 
+	R_PORT_PA_DIR, 
+	R_PORT_PB_DIR 
+};
+
+static volatile unsigned char *dir_shadow[NUM_PORTS] = {
+	&port_pa_dir_shadow, 
+	&port_pb_dir_shadow 
+};
+
+/* Port G is 32 bit, handle it special, some bits are both inputs 
+   and outputs at the same time, only some of the bits can change direction
+   and some of them in groups of 8 bit. */
+static unsigned long changeable_dir_g;
+static unsigned long dir_g_in_bits;
+static unsigned long dir_g_out_bits;
+static unsigned long dir_g_shadow; /* 1=output */
+
+#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
 
-static volatile unsigned char *dir_shadow[2] = {
-	&port_pa_dir_shadow, &port_pb_dir_shadow };
 
-#define LEDS 2
 
 static unsigned int 
 gpio_poll(struct file *filp,
@@ -149,10 +190,10 @@
 {
 	/* TODO poll on alarms! */
 #if 0
-        if (!ANYTHING_WANTED) {
+	if (!ANYTHING_WANTED) {
 		D(printk("gpio_select sleeping task\n"));
-	        select_wait(&gpio_wq, table);
-	        return 0;
+		select_wait(&gpio_wq, table);
+		return 0;
 	}
 	D(printk("gpio_select ready\n"));
 #endif
@@ -166,6 +207,10 @@
 	unsigned char data, clk_mask, data_mask, write_msb;
 	unsigned long flags;
 	ssize_t retval = count;
+	if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) {
+		return -EFAULT;
+	}
+    
 	if (verify_area(VERIFY_READ, buf, count)) {
 		return -EFAULT;
 	}
@@ -210,13 +255,15 @@
 	return retval;
 }
 
+
+
 static int
 gpio_open(struct inode *inode, struct file *filp)
 {
 	struct gpio_private *priv;
 	int p = MINOR(inode->i_rdev);
 
-	if (p >= NUM_PORTS && p != LEDS)
+	if (p > GPIO_MINOR_LAST)
 		return -EINVAL;
 
 	priv = (struct gpio_private *)kmalloc(sizeof(struct gpio_private), 
@@ -231,13 +278,21 @@
 
 	priv->next = alarmlist;
 	alarmlist = priv;
-	priv->port = ports[p];
-	priv->shadow = shads[p];
-
-	priv->changeable_dir = changeable_dir[p];
-	priv->changeable_bits = changeable_bits[p];
-	priv->dir = dir[p];
-	priv->dir_shadow = dir_shadow[p];
+	if (USE_PORTS(priv)) { /* A and B */
+		priv->port = ports[p];
+		priv->shadow = shads[p];
+		priv->dir = dir[p];
+		priv->dir_shadow = dir_shadow[p];
+		priv->changeable_dir = changeable_dir[p];
+		priv->changeable_bits = changeable_bits[p];
+	} else {
+		priv->port = NULL;
+		priv->shadow = NULL;
+		priv->dir = NULL;
+		priv->dir_shadow = NULL;
+		priv->changeable_dir = 0;
+		priv->changeable_bits = 0;
+	}
 
 	priv->highalarm = 0;
 	priv->lowalarm = 0;
@@ -289,87 +344,189 @@
 	}
 
 	switch (_IOC_NR(cmd)) {
-		case IO_READBITS:
-			// read the port
+	case IO_READBITS:
+		// read the port
+		if (USE_PORTS(priv)) {
 			return *priv->port;
-		case IO_SETBITS:
-			save_flags(flags); cli();
-			// set changeable bits with a 1 in arg
+		} else if (priv->minor == GPIO_MINOR_G) {
+			return *R_PORT_G_DATA;
+		}
+		break;
+	case IO_SETBITS:
+		save_flags(flags); cli();
+		// set changeable bits with a 1 in arg
+		if (USE_PORTS(priv)) {
 			*priv->port = *priv->shadow |= 
 			  ((unsigned char)arg & priv->changeable_bits);
-			restore_flags(flags);
-			break;
-		case IO_CLRBITS:
-			save_flags(flags); cli();
-			// clear changeable bits with a 1 in arg
+		} else if (priv->minor == GPIO_MINOR_G) {
+			*R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
+		}
+		restore_flags(flags);
+		break;
+	case IO_CLRBITS:
+		save_flags(flags); cli();
+		// clear changeable bits with a 1 in arg
+		if (USE_PORTS(priv)) {
 			*priv->port = *priv->shadow &= 
-			  ~((unsigned char)arg & priv->changeable_bits);
-			restore_flags(flags);
-			break;
-		case IO_HIGHALARM:
-			// set alarm when bits with 1 in arg go high
-			priv->highalarm |= (unsigned char)arg;
-			break;
-		case IO_LOWALARM:
-			// set alarm when bits with 1 in arg go low
-			priv->lowalarm |= (unsigned char)arg;
-			break;
-		case IO_CLRALARM:
-			// clear alarm for bits with 1 in arg
-			priv->highalarm &= ~(unsigned char)arg;
-			priv->lowalarm  &= ~(unsigned char)arg;
-			break;
-		case IO_READDIR:
-			/* Read direction 0=input 1=output */
+			 ~((unsigned char)arg & priv->changeable_bits);
+		} else if (priv->minor == GPIO_MINOR_G) {
+			*R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
+		}
+		restore_flags(flags);
+		break;
+	case IO_HIGHALARM:
+		// set alarm when bits with 1 in arg go high
+		priv->highalarm |= arg;
+		break;
+	case IO_LOWALARM:
+		// set alarm when bits with 1 in arg go low
+		priv->lowalarm |= arg;
+		break;
+	case IO_CLRALARM:
+		// clear alarm for bits with 1 in arg
+		priv->highalarm &= ~arg;
+		priv->lowalarm  &= ~arg;
+		break;
+	case IO_READDIR:
+		/* Read direction 0=input 1=output */
+		if (USE_PORTS(priv)) {
 			return *priv->dir_shadow;
-		case IO_SETINPUT:
+		} else if (priv->minor == GPIO_MINOR_G) {
+			/* Note: Some bits are both in and out,
+			 * Those that are dual is set hare as well.
+			 */
+			return dir_g_shadow | dir_g_out_bits;
+		}
+	case IO_SETINPUT:
+		/* Set direction 0=unchanged 1=input, 
+		 * return mask with 1=input 
+		 */
+		if (USE_PORTS(priv)) {
 			save_flags(flags); cli();
-			/* Set direction 0=unchanged 1=input */
 			*priv->dir = *priv->dir_shadow &= 
 			~((unsigned char)arg & priv->changeable_dir);
 			restore_flags(flags);
-			return *priv->dir_shadow;
-		case IO_SETOUTPUT:
+			return ~(*priv->dir_shadow);
+		} else if (priv->minor == GPIO_MINOR_G) {
+			/* We must fiddle with R_GEN_CONFIG to change dir */
+			if (((arg & dir_g_in_bits) != arg) && 
+			    (arg & changeable_dir_g)) {
+				arg &= changeable_dir_g;
+				/* Clear bits in genconfig to set to input */
+				if (arg & (1<<0)) {
+					genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g0dir);
+					dir_g_in_bits |= (1<<0);
+					dir_g_out_bits &= ~(1<<0);
+				}
+				if ((arg & 0x0000FF00) == 0x0000FF00) {
+					genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g8_15dir);
+					dir_g_in_bits |= 0x0000FF00;
+					dir_g_out_bits &= ~0x0000FF00;
+				}
+				if ((arg & 0x00FF0000) == 0x00FF0000) {
+					genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g16_23dir);
+					dir_g_in_bits |= 0x00FF0000;
+					dir_g_out_bits &= ~0x00FF0000;
+				}
+				if (arg & (1<<24)) {
+					genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g24dir);
+					dir_g_in_bits |= (1<<24);
+					dir_g_out_bits &= ~(1<<24);
+				}
+				printk("gpio: SETINPUT on port G set "
+					"genconfig to 0x%08lX "
+					"in_bits: 0x%08lX "
+					"out_bits: 0x%08lX\n", 
+				       (unsigned long)genconfig_shadow, 
+				       dir_g_in_bits, dir_g_out_bits);
+				*R_GEN_CONFIG = genconfig_shadow;
+				/* Must be a >120 ns delay before writing this again */
+				
+			}
+			return dir_g_in_bits;
+		}
+		return 0;
+
+	case IO_SETOUTPUT:
+		/* Set direction 0=unchanged 1=output, 
+		 * return mask with 1=output 
+		 */
+		if (USE_PORTS(priv)) {
 			save_flags(flags); cli();
-			/* Set direction 0=unchanged 1=output */
 			*priv->dir = *priv->dir_shadow |= 
 			  ((unsigned char)arg & priv->changeable_dir);
 			restore_flags(flags);
 			return *priv->dir_shadow;
-                case IO_SHUTDOWN:
-                       SOFT_SHUTDOWN();
-                       break;
-                case IO_GET_PWR_BT:
+		} else if (priv->minor == GPIO_MINOR_G) {
+			/* We must fiddle with R_GEN_CONFIG to change dir */			
+			if (((arg & dir_g_out_bits) != arg) &&
+			    (arg & changeable_dir_g)) {
+				/* Set bits in genconfig to set to output */
+				if (arg & (1<<0)) {
+					genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g0dir);
+					dir_g_out_bits |= (1<<0);
+					dir_g_in_bits &= ~(1<<0);
+				}
+				if ((arg & 0x0000FF00) == 0x0000FF00) {
+					genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g8_15dir);
+					dir_g_out_bits |= 0x0000FF00;
+					dir_g_in_bits &= ~0x0000FF00;
+				}
+				if ((arg & 0x00FF0000) == 0x00FF0000) {
+					genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g16_23dir);
+					dir_g_out_bits |= 0x00FF0000;
+					dir_g_in_bits &= ~0x00FF0000;
+				}
+				if (arg & (1<<24)) {
+					genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g24dir);
+					dir_g_out_bits |= (1<<24);
+					dir_g_in_bits &= ~(1<<24);
+				}
+				printk("gpio: SETOUTPUT on port G set "
+					"genconfig to 0x%08lX "
+					"in_bits: 0x%08lX "
+					"out_bits: 0x%08lX\n", 
+				       (unsigned long)genconfig_shadow, 
+				       dir_g_in_bits, dir_g_out_bits);
+				*R_GEN_CONFIG = genconfig_shadow;
+				/* Must be a >120 ns delay before writing this again */
+			}
+			return dir_g_out_bits;
+		}
+		return 0;
+	case IO_SHUTDOWN:
+		SOFT_SHUTDOWN();
+		break;
+	case IO_GET_PWR_BT:
 #if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
-                       return (*R_PORT_G_DATA & 
-                               ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
+		return (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
 #else
-                       return 0;
+		return 0;
 #endif
-			break;
-		case IO_CFG_WRITE_MODE:
-			priv->clk_mask = arg & 0xFF;
-			priv->data_mask = (arg >> 8) & 0xFF;
-			priv->write_msb = (arg >> 16) & 0x01;
-			/* Check if we're allowed to change the bits and
-			 * the direction is correct
-			 */
-			if (!((priv->clk_mask & priv->changeable_bits) &&
-			      (priv->data_mask & priv->changeable_bits) &&
-			      (priv->clk_mask & *priv->dir_shadow) &&
-			      (priv->data_mask & *priv->dir_shadow)))
-			{
-				priv->clk_mask = 0;
-				priv->data_mask = 0;
-				return -EPERM;
-			}
-			break;
-		default:
-			if (priv->minor == LEDS)
-				return gpio_leds_ioctl(cmd, arg);
-                        else
-				return -EINVAL;
-	}
+		break;
+	case IO_CFG_WRITE_MODE:
+		priv->clk_mask = arg & 0xFF;
+		priv->data_mask = (arg >> 8) & 0xFF;
+		priv->write_msb = (arg >> 16) & 0x01;
+		/* Check if we're allowed to change the bits and
+		 * the direction is correct
+		 */
+		if (!((priv->clk_mask & priv->changeable_bits) &&
+		      (priv->data_mask & priv->changeable_bits) &&
+		      (priv->clk_mask & *priv->dir_shadow) &&
+		      (priv->data_mask & *priv->dir_shadow)))
+		{
+			priv->clk_mask = 0;
+			priv->data_mask = 0;
+			return -EPERM;
+		}
+		break;
+	default:
+		if (priv->minor == GPIO_MINOR_LEDS)
+			return gpio_leds_ioctl(cmd, arg);
+		else
+			return -EINVAL;
+	} /* switch */
 	
 	return 0;
 }
@@ -381,24 +538,24 @@
 	unsigned char red;
 
 	switch (_IOC_NR(cmd)) {
-		case IO_LEDACTIVE_SET:
-			green = ((unsigned char) arg) & 1;
-			red   = (((unsigned char) arg) >> 1) & 1;
-			LED_ACTIVE_SET_G(green);
-			LED_ACTIVE_SET_R(red);
-			break;
-
-		case IO_LED_SETBIT:                 
-			LED_BIT_SET(arg);
-			break;
-
-		case IO_LED_CLRBIT:
-			LED_BIT_CLR(arg);
-			break;
+	case IO_LEDACTIVE_SET:
+		green = ((unsigned char) arg) & 1;
+		red   = (((unsigned char) arg) >> 1) & 1;
+		LED_ACTIVE_SET_G(green);
+		LED_ACTIVE_SET_R(red);
+		break;
+
+	case IO_LED_SETBIT:
+		LED_BIT_SET(arg);
+		break;
+
+	case IO_LED_CLRBIT:
+		LED_BIT_CLR(arg);
+		break;
 
-		default:
-			return -EINVAL;
-	}
+	default:
+		return -EINVAL;
+	} /* switch */
 
 	return 0;
 }
@@ -412,6 +569,92 @@
 	release:     gpio_release,
 };
 
+
+static void __init gpio_init_port_g(void)
+{
+#define GROUPA (0x0000FF3F)
+#define GROUPB (1<<6 | 1<<7)
+#define GROUPC (1<<30 | 1<<31)
+#define GROUPD (0x3FFF0000)
+#define GROUPD_LOW (0x00FF0000)
+	unsigned long used_in_bits = 0;
+	unsigned long used_out_bits = 0;
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0, select)){
+		used_in_bits  |= GROUPA | GROUPB | 0 | 0;
+		used_out_bits |= GROUPA | GROUPB | 0 | 0;
+	}
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ata, select)) {
+		used_in_bits  |= GROUPA | GROUPB | GROUPC | (GROUPD & ~(1<<25|1<<26));
+		used_out_bits |= GROUPA | GROUPB | GROUPC | GROUPD;
+	}
+
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par0, select)) {
+		used_in_bits  |= (GROUPA & ~(1<<0)) | 0 | 0 | 0;
+		used_out_bits |= (GROUPA & ~(1<<0)) | 0 | 0 | 0;
+	}
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser2, select)) {
+		used_in_bits  |= 0 | GROUPB | 0 | 0;
+		used_out_bits |= 0 | GROUPB | 0 | 0;
+	}
+	/* mio same as shared RAM ? */
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio, select)) {
+		used_in_bits  |= (GROUPA & ~(1<<0)) | 0 |0 |GROUPD_LOW;
+		used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 |0 |GROUPD_LOW;
+	}
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi1, select)) {
+		used_in_bits  |= 0 | 0 | GROUPC | GROUPD;
+		used_out_bits |= 0 | 0 | GROUPC | GROUPD;
+	}
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0w, select)) {
+		used_in_bits  |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24);
+		used_out_bits |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24 | 1<<25|1<<26);
+	}
+
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par1, select)) {
+		used_in_bits  |= 0 | 0 | 0 | (GROUPD & ~(1<<24));
+		used_out_bits |= 0 | 0 | 0 | (GROUPD & ~(1<<24));
+	}
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser3, select)) {
+		used_in_bits  |= 0 | 0 | GROUPC | 0;
+		used_out_bits |= 0 | 0 | GROUPC | 0;
+	}
+	/* mio same as shared RAM-W? */
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio_w, select)) {
+		used_in_bits  |= (GROUPA & ~(1<<0)) | 0 | 0 |GROUPD_LOW;
+		used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 | 0 |GROUPD_LOW;
+	}
+	/* TODO: USB p2, parw, sync ser3? */
+
+	/* Initialise the dir_g_shadow etc. depending on genconfig */
+	/* 0=input 1=output */
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) 
+		dir_g_shadow |= (1 << 0);
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
+		dir_g_shadow |= 0x0000FF00;
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
+		dir_g_shadow |= 0x00FF0000;
+	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
+		dir_g_shadow |= (1 << 24);
+
+	dir_g_in_bits = ~used_in_bits;
+	dir_g_out_bits = ~used_out_bits;
+
+	changeable_dir_g = 0x01FFFF01; /* all that can change dir */
+	changeable_dir_g &= dir_g_out_bits;
+	changeable_dir_g &= dir_g_in_bits;
+	/* Correct the bits that can change direction */ 
+	dir_g_out_bits &= ~changeable_dir_g;
+	dir_g_out_bits |= dir_g_shadow;
+	dir_g_in_bits &= ~changeable_dir_g;
+	dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
+
+
+	printk("GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n",
+	       dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
+	printk("GPIO port G: dir: %08lX changeable: %08lX\n", 
+	       dir_g_shadow, changeable_dir_g);
+}
+
 /* main driver initialization routine, called from mem.c */
 
 static __init int
@@ -431,13 +674,13 @@
 		return res;
 	}
 
-        /* Clear all leds */
+	/* Clear all leds */
 #if defined (CONFIG_ETRAX_CSP0_LEDS) ||  defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) 
 	init_ioremap();
 	LED_NETWORK_SET(0);
 	LED_ACTIVE_SET(0);
 	LED_DISK_READ(0);
-	LED_DISK_WRITE(0);        
+	LED_DISK_WRITE(0);
 
 #if defined (CONFIG_ETRAX_CSP0_LEDS)
 	for (i = 0; i < 32; i++) {
@@ -446,8 +689,8 @@
 #endif
 
 #endif
-	
-	printk("ETRAX 100LX GPIO driver v2.2, (c) 2001 Axis Communications AB\n");
+	gpio_init_port_g();
+	printk("ETRAX 100LX GPIO driver v2.3, (c) 2001, 2002 Axis Communications AB\n");
 
 	return res;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/ide.c linux/arch/cris/drivers/ide.c
--- linux.orig/arch/cris/drivers/ide.c	2001-07-04 18:50:38.000000000 +0000
+++ linux/arch/cris/drivers/ide.c	2002-08-01 06:42:35.000000000 +0000
@@ -1,13 +1,34 @@
-/* $Id: ide.c,v 1.19 2001/05/09 12:53:16 johana Exp $
+/* $Id: ide.c,v 1.24 2002/04/22 11:47:21 johana Exp $
  *
  * Etrax specific IDE functions, like init and PIO-mode setting etc.
  * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
- * Copyright (c) 2000, 2001 Axis Communications AB 
+ * Copyright (c) 2000, 2001, 2002 Axis Communications AB 
  *
  * Authors:    Bjorn Wesen        (initial version)
  *             Mikael Starvik     (pio setup stuff)
  *
  * $Log: ide.c,v $
+ * Revision 1.24  2002/04/22 11:47:21  johana
+ * Fix according to 2.4.19-pre7. time_after/time_before and
+ * missing end of comment.
+ * The patch has a typo for ethernet.c in e100_clear_network_leds(),
+ *  that is fixed here.
+ *
+ * Revision 1.23  2002/03/19 15:35:51  bjornw
+ * Cleaned up the bus-reset code a bit and made G27-reset work
+ *
+ * Revision 1.22  2002/03/19 15:23:05  bjornw
+ * Added flush_etrax_cache before starting the receiving DMA
+ *
+ * Revision 1.21  2002/03/06 15:37:56  hp
+ * 	* ide.c (OUT_BYTE): If timing out in the first busy-loop, do a
+ * 	printk, fall through and still do the write.
+ * 	(IN_BYTE): If timing out in the first loop, and reg indicated it's
+ * 	the ATA status register in the device being read, return BUSY_STAT.
+ *
+ * Revision 1.20  2002/02/22 11:47:56  bjornw
+ * Added a timeout to IN_BYTE and OUT_BYTE
+ *
  * Revision 1.19  2001/05/09 12:53:16  johana
  * Added #include <asm/dma.h>
  *
@@ -112,6 +133,13 @@
 /* number of Etrax DMA descriptors */
 #define MAX_DMA_DESCRS 64
 
+/* number of times to retry busy-flags when reading/writing IDE-registers 
+ * this can't be too high because a hung harddisk might cause the watchdog
+ * to trigger (sometimes IN_BYTE and OUT_BYTE are called with irq's disabled)
+ */
+
+#define IDE_REGISTER_TIMEOUT 300
+
 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
 /* address where the memory-mapped IDE reset bit lives, if used */
 static volatile unsigned long *reset_addr;
@@ -120,21 +148,84 @@
 #define LOWDB(x)
 #define D(x) 
 
-void OUT_BYTE(unsigned char data, ide_ioreg_t reg) {
+void 
+OUT_BYTE(unsigned char data, ide_ioreg_t reg) {
+	int timeleft;
 	LOWDB(printk("ob: data 0x%x, reg 0x%x\n", data, reg));
-	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag */
+
+	/* note the lack of handling any timeouts. we stop waiting, but we don't
+	 * really notify anybody.
+	 */
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for busy flag */
+	while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
+		timeleft--;
+
+	/*
+	 * Fall through at a timeout, so the ongoing command will be
+	 * aborted by the write below, which is expected to be a dummy
+	 * command to the command register.  This happens when a faulty
+	 * drive times out on a command.  See comment on timeout in
+	 * IN_BYTE.
+	 */
+	if(!timeleft)
+		printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
+
 	*R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */
-	while(!(*R_ATA_STATUS_DATA &
-		IO_MASK(R_ATA_STATUS_DATA, tr_rdy))); /* wait for transmitter ready */
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for transmitter ready */
+	while(timeleft && !(*R_ATA_STATUS_DATA &
+			    IO_MASK(R_ATA_STATUS_DATA, tr_rdy)))
+		timeleft--;
 }
 
-unsigned char IN_BYTE(ide_ioreg_t reg) {
+unsigned char 
+IN_BYTE(ide_ioreg_t reg) {
 	int status;
-	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag */
+	int timeleft;
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for busy flag */
+	while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
+		timeleft--;
+
+	if(!timeleft) {
+		/*
+		 * If we're asked to read the status register, like for
+		 * example when a command does not complete for an
+		 * extended time, but the ATA interface is stuck in a
+		 * busy state at the *ETRAX* ATA interface level (as has
+		 * happened repeatedly with at least one bad disk), then
+		 * the best thing to do is to pretend that we read
+		 * "busy" in the status register, so the IDE driver will
+		 * time-out, abort the ongoing command and perform a
+		 * reset sequence.  Note that the subsequent OUT_BYTE
+		 * call will also timeout on busy, but as long as the
+		 * write is still performed, everything will be fine.
+		 */
+		if ((reg & IO_MASK (R_ATA_CTRL_DATA, addr))
+		    == IO_FIELD (R_ATA_CTRL_DATA, addr, IDE_STATUS_OFFSET))
+			return BUSY_STAT;
+		else
+			/* For other rare cases we assume 0 is good enough.  */
+			return 0;
+	}
+
 	*R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */ 
-	while(!((status = *R_ATA_STATUS_DATA) &
-		IO_MASK(R_ATA_STATUS_DATA, dav))); /* wait for available */
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for available */
+	while(timeleft && !((status = *R_ATA_STATUS_DATA) &
+			    IO_MASK(R_ATA_STATUS_DATA, dav)))
+		timeleft--;
+
+	if(!timeleft)
+		return 0;
+
 	LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg));
+
 	return (unsigned char)status; /* data was in the lower 16 bits in the status reg */
 }
 
@@ -279,20 +370,8 @@
 		hwif->dmaproc = &e100_dmaproc;
 		hwif->ideproc = &e100_ideproc;
 	}
-	/* actually reset and configure the etrax100 ide/ata interface */
 
-	/* This is mystifying; why is not G27 SET anywhere ? It's just reset here twice. */
-
-	/* de-assert bus-reset */
-#ifdef CONFIG_ETRAX_IDE_PB7_RESET  
-	port_pb_dir_shadow = port_pb_dir_shadow | 
-		IO_STATE(R_PORT_PB_DIR, dir7, output);
-	*R_PORT_PB_DIR = port_pb_dir_shadow;
-	REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
-#endif
-#ifdef CONFIG_ETRAX_IDE_G27_RESET
-	*R_PORT_G_DATA = 0;
-#endif 
+	/* actually reset and configure the etrax100 ide/ata interface */
 
 	*R_ATA_CTRL_DATA = 0;
 	*R_ATA_TRANSFER_CNT = 0;
@@ -308,19 +387,32 @@
 
 	*R_GEN_CONFIG = genconfig_shadow;
 
+        /* pull the chosen /reset-line low */
+        
+#ifdef CONFIG_ETRAX_IDE_G27_RESET
+        REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 0);
+#endif 
 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
         init_ioremap();
         REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0);
 #endif
-
 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
         init_ioremap();
         REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0);
 #endif
+#ifdef CONFIG_ETRAX_IDE_PB7_RESET  
+	port_pb_dir_shadow = port_pb_dir_shadow | 
+		IO_STATE(R_PORT_PB_DIR, dir7, output);
+	*R_PORT_PB_DIR = port_pb_dir_shadow;
+	REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
+#endif
 
 	/* wait some */
+
 	udelay(25);
 
+	/* de-assert bus-reset */
+
 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
 	REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1);
 #endif
@@ -328,7 +420,7 @@
 	REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1);
 #endif
 #ifdef CONFIG_ETRAX_IDE_G27_RESET
-	*R_PORT_G_DATA = 0; /* de-assert bus-reset */
+	REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 1);
 #endif 
 
 	/* make a dummy read to set the ata controller in a proper state */
@@ -351,12 +443,13 @@
 			     IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
 			     IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
 
-	printk("ide: waiting %d seconds for drives to regain consciousness\n", CONFIG_ETRAX_IDE_DELAY);
+	printk("ide: waiting %d seconds for drives to regain consciousness\n",
+	       CONFIG_ETRAX_IDE_DELAY);
 
 	h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ);
-	while(jiffies < h) ;
+	while(time_before(jiffies, h)) /* nothing */ ;
 
-  /* reset the dma channels we will use */
+	/* reset the dma channels we will use */
 
 	RESET_DMA(ATA_TX_DMA_NBR);
 	RESET_DMA(ATA_RX_DMA_NBR);
@@ -657,10 +750,9 @@
                 }
 		/* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
                 if(size == 65536) {
-                  ata_descrs[count].sw_len = 0;  /* 0 means 65536, this is a 16-bit field */
-                }
-                else {
-                  ata_descrs[count].sw_len = size;
+			ata_descrs[count].sw_len = 0;  /* 0 means 65536, this is a 16-bit field */
+                } else {
+			ata_descrs[count].sw_len = size;
                 }
 		ata_descrs[count].ctrl = 0;
 		ata_descrs[count].buf = addr;
@@ -823,7 +915,15 @@
 		}
 
 		/* begin DMA */
-	      
+		
+		/* need to do this before RX DMA due to a chip bug
+		 * it is enough to just flush the part of the cache that
+		 * corresponds to the buffers we start, but since HD transfers
+		 * usually are more than 8 kB, it is easier to optimize for the
+		 * normal case and just flush the entire cache. its the only
+		 * way to be sure! (OB movie quote)
+		 */
+		flush_etrax_cache();  
 		*R_DMA_CH3_FIRST = virt_to_phys(ata_descrs);
 		*R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);
 		
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/lpslave/e100lpslavenet.c linux/arch/cris/drivers/lpslave/e100lpslavenet.c
--- linux.orig/arch/cris/drivers/lpslave/e100lpslavenet.c	2001-07-26 22:10:06.000000000 +0000
+++ linux/arch/cris/drivers/lpslave/e100lpslavenet.c	2002-08-01 06:42:40.000000000 +0000
@@ -1,4 +1,4 @@
-/* $Id: e100lpslavenet.c,v 1.4 2001/06/21 16:55:26 olof Exp $
+/* $Id: e100lpslavenet.c,v 1.5 2002/04/22 11:47:24 johana Exp $
  *
  * e100lpslavenet.c: A network driver for the ETRAX 100LX slave controller.
  *
@@ -7,6 +7,12 @@
  * The outline of this driver comes from skeleton.c.
  *
  * $Log: e100lpslavenet.c,v $
+ * Revision 1.5  2002/04/22 11:47:24  johana
+ * Fix according to 2.4.19-pre7. time_after/time_before and
+ * missing end of comment.
+ * The patch has a typo for ethernet.c in e100_clear_network_leds(),
+ *  that is fixed here.
+ *
  * Revision 1.4  2001/06/21 16:55:26  olof
  * Minimized par port setup time to gain bandwidth
  *
@@ -310,7 +316,7 @@
 		IO_STATE(R_PAR0_CONFIG, iautofd, noninv)    |
           /* Not used in reverse direction, don't care */
 		IO_STATE(R_PAR0_CONFIG, istrb,   noninv)    |
-          /* Not connected, don't care /
+          /* Not connected, don't care */
 		IO_STATE(R_PAR0_CONFIG, iinit,   noninv)    |
           /* perror is GND and reverse wants 0, noninv */
 		IO_STATE(R_PAR0_CONFIG, iperr,   noninv)    |
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/parport.c linux/arch/cris/drivers/parport.c
--- linux.orig/arch/cris/drivers/parport.c	2001-10-08 18:43:54.000000000 +0000
+++ linux/arch/cris/drivers/parport.c	2002-08-01 06:42:30.000000000 +0000
@@ -1,4 +1,4 @@
-/* $Id: parport.c,v 1.8 2001/09/26 11:51:52 bjornw Exp $
+/* $Id: parport.c,v 1.9 2002/05/15 12:30:24 starvik Exp $
  * 
  * Elinux parallel port driver
  * NOTE!
@@ -204,7 +204,7 @@
 	SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, autofd,
 	     (control & PARPORT_CONTROL_AUTOFD) > 0);
 	SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, init,
-	     (control & PARPORT_CONTROL_INIT) > 0);
+	     (control & PARPORT_CONTROL_INIT) == 0);
 	SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, seli,
 	     (control & PARPORT_CONTROL_SELECT) > 0);
 
@@ -223,7 +223,7 @@
 		ret |= PARPORT_CONTROL_STROBE;
 	if (IO_EXTRACT(R_PAR0_CTRL_DATA, autofd, info->reg_ctrl_data_shadow))
 		ret |= PARPORT_CONTROL_AUTOFD;
-	if (IO_EXTRACT(R_PAR0_CTRL_DATA, init, info->reg_ctrl_data_shadow))
+	if (!IO_EXTRACT(R_PAR0_CTRL_DATA, init, info->reg_ctrl_data_shadow))
 		ret |= PARPORT_CONTROL_INIT;
 	if (IO_EXTRACT(R_PAR0_CTRL_DATA, seli, info->reg_ctrl_data_shadow))
 		ret |= PARPORT_CONTROL_SELECT;
@@ -258,7 +258,7 @@
 		ret |= PARPORT_STATUS_ERROR;
 	if (IO_EXTRACT(R_PAR0_STATUS_DATA, sel, *info->reg_status_data))
 		ret |= PARPORT_STATUS_SELECT;
-	if (!IO_EXTRACT(R_PAR0_STATUS_DATA, perr, *info->reg_status_data))
+	if (IO_EXTRACT(R_PAR0_STATUS_DATA, perr, *info->reg_status_data))
 		ret |= PARPORT_STATUS_PAPEROUT;
 	if (IO_EXTRACT(R_PAR0_STATUS_DATA, ack, *info->reg_status_data))
 		ret |= PARPORT_STATUS_ACK;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/serial.c linux/arch/cris/drivers/serial.c
--- linux.orig/arch/cris/drivers/serial.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/drivers/serial.c	2002-08-01 06:42:32.000000000 +0000
@@ -1,12 +1,24 @@
-/* $Id: serial.c,v 1.29 2002/01/14 16:10:01 pkj Exp $
+/* $Id: serial.c,v 1.32 2002/05/22 13:58:00 johana Exp $
  *
  * Serial port driver for the ETRAX 100LX chip
  *
- *      Copyright (C) 1998, 1999, 2000, 2001  Axis Communications AB
+ *      Copyright (C) 1998, 1999, 2000, 2001, 2002  Axis Communications AB
  *
  *      Many, many authors. Based once upon a time on serial.c for 16x50.
  *
  * $Log: serial.c,v $
+ * Revision 1.32  2002/05/22 13:58:00  johana
+ * Renamed rs_write() to raw_write() and made it inline.
+ * New rs_write() handles RS-485 if configured and enabled
+ * (moved code from e100_write_rs485()).
+ * RS-485 ioctl's uses copy_from_user() instead of verify_area().
+ *
+ * Revision 1.31  2002/04/22 11:20:03  johana
+ * Updated copyright years.
+ *
+ * Revision 1.30  2002/04/22 09:39:12  johana
+ * RS-485 support compiles.
+ *
  * Revision 1.29  2002/01/14 16:10:01  pkj
  * Allocate the receive buffers dynamically. The static 4kB buffer was
  * too small for the peaks. This means that we can get rid of the extra
@@ -291,7 +303,7 @@
  *
  */
 
-static char *serial_version = "$Revision: 1.29 $";
+static char *serial_version = "$Revision: 1.32 $";
 
 #include <linux/config.h>
 #include <linux/version.h>
@@ -322,7 +334,7 @@
 #include <asm/system.h>
 #include <asm/segment.h>
 #include <asm/bitops.h>
-#include <asm/delay.h>
+#include <linux/delay.h>
 
 #include <asm/svinto.h>
 
@@ -390,6 +402,13 @@
 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
 static int rs_write(struct tty_struct * tty, int from_user,
                     const unsigned char *buf, int count);
+static inline int raw_write(struct tty_struct * tty, int from_user,
+                            const unsigned char *buf, int count);
+static int e100_write_rs485(struct tty_struct * tty, int from_user,
+                            const unsigned char *buf, int count);
+static int 
+get_lsr_info(struct e100_serial * info, unsigned int *value);
+
 
 #define DEF_BAUD 0x99   /* 115.2 kbit/s */
 #define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
@@ -827,12 +846,12 @@
 e100_rts(struct e100_serial *info, int set)
 {
 #ifndef CONFIG_SVINTO_SIM
-#ifdef SERIAL_DEBUG_IO  
-	printk("ser%i rts %i\n", info->line, set);
-#endif
 	info->rx_ctrl &= ~E100_RTS_MASK;
 	info->rx_ctrl |= (set ? 0 : E100_RTS_MASK);  /* RTS is active low */
 	info->port[REG_REC_CTRL] = info->rx_ctrl;
+#ifdef SERIAL_DEBUG_IO  
+	printk("ser%i rts %i\n", info->line, set);
+#endif
 #endif
 }
 
@@ -985,63 +1004,32 @@
 	info->rs485.rts_after_sent = 0x01 & r->rts_after_sent;
 	info->rs485.delay_rts_before_send = r->delay_rts_before_send;
 	info->rs485.enabled = r->enabled;
-	
+/*	printk("rts: on send = %i, after = %i, enabled = %i",
+		    info->rs485.rts_on_send,
+		    info->rs485.rts_after_sent,
+		    info->rs485.enabled
+	);
+*/		
 	return 0;
 }
 
 static int
-e100_write_rs485(struct tty_struct *tty,struct rs485_write *r)
+e100_write_rs485(struct tty_struct *tty, int from_user, 
+                 const unsigned char *buf, int count)
 {
-	int total;
 	struct e100_serial * info = (struct e100_serial *)tty->driver_data;
+	int old_enabled = info->rs485.enabled;
 
-	/* If we are in RS-485 mode, we need to toggle RTS and disable
-	 * the receiver before initiating a DMA transfer
-	 */
-	e100_rts(info, info->rs485.rts_on_send);
-#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
-	e100_disable_rx(info);
-	e100_disable_rxdma_irq(info);
-#endif
-
-	if (info->rs485.delay_rts_before_send > 0) {
-		current->timeout = jiffies + (info->rs485.delay_rts_before_send * HZ)/1000;
-		current->state = TASK_INTERRUPTIBLE;
-		schedule();
-		current->timeout = 0;
-	}
-	total = rs_write(tty, 1, (*r).outc, (*r).outc_size);
-
-	/* If we are in RS-485 mode the following things has to be done:
-	 * wait until DMA is ready
-	 * wait on transmit shift register
-	 * wait to toggle RTS
-	 * enable the receiver
-	 */	
-
-	/* Sleep until all sent */
-	tty_wait_until_sent(tty, 0);
-#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
-	/* Now sleep a little more so that shift register is empty */
-	schedule_usleep(info->char_time_usec * 2);
-#else
-	{
-		unsigned int val;
-		/* wait on transmit shift register */
-		do{
-			get_lsr_info(info, &val);
-		}while (!(val & TIOCSER_TEMT));
-	}
-#endif
-
-	e100_rts(info, info->rs485.rts_after_sent);
-	
-#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
-	e100_enable_rx(info);
-	e100_enable_rxdma_irq(info);
-#endif
-
-	return total;
+	/* rs485 is always implicitly enabled if we're using the ioctl() 
+	 * but it doesn't have to be set in the rs485_control
+	 * (to be backward compatible with old apps)
+	 * So we store, set and restore it.
+	 */
+	info->rs485.enabled = 1;
+	/* rs_write now deals with RS485 if enabled */
+	count = rs_write(tty, from_user, buf, count);
+	info->rs485.enabled = old_enabled;
+	return count;
 }
 #endif
 
@@ -1186,26 +1174,6 @@
 		/* our job here is done, don't schedule any new DMA transfer */
 		info->tr_running = 0;
 
-#if defined(CONFIG_ETRAX_RS485)
-		/* Check if we should toggle RTS now */
-		if (info->rs485.enabled) {
-			/* Make sure fifo is empty */
-			int in_fifo = 0;
-
-			do {
-				in_fifo = IO_EXTRACT(R_DMA_CH6_STATUS, avail,
-						     *info->ostatusadr);
-			}  while (in_fifo > 0);
-			/* Any way to really check transmitter empty? (TEMT) */
-			/* Control RTS to set to RX mode */
-			e100_rts(info, info->rs485.rts_after_sent); 
-#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
-			e100_enable_rx(info);
-			e100_enable_rxdma_irq(info);
-#endif
-		}
-#endif /* RS485 */
-
 		return;
 	}
 
@@ -2352,8 +2320,8 @@
 	restore_flags(flags);
 }
 
-static int 
-rs_write(struct tty_struct * tty, int from_user,
+static inline int 
+raw_write(struct tty_struct * tty, int from_user,
 	 const unsigned char *buf, int count)
 {
 	int	c, ret = 0;
@@ -2367,7 +2335,7 @@
 	
 #ifdef SERIAL_DEBUG_DATA
 	if (info->line == SERIAL_DEBUG_LINE)
-		printk("rs_write (%d), status %d\n", 
+		printk("raw_write (%d), status %d\n", 
 		       count, info->port[REG_STATUS]);
 #endif
 
@@ -2453,8 +2421,70 @@
 	}
  	
 	return ret;
+} /* raw_write() */
+
+static int 
+rs_write(struct tty_struct * tty, int from_user,
+	 const unsigned char *buf, int count)
+{
+#if defined(CONFIG_ETRAX_RS485)
+	struct e100_serial *info = (struct e100_serial *)tty->driver_data;
+
+	if (info->rs485.enabled)
+	{
+		/* If we are in RS-485 mode, we need to toggle RTS and disable
+		 * the receiver before initiating a DMA transfer
+		 */
+		e100_rts(info, info->rs485.rts_on_send);
+#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
+		e100_disable_rx(info);
+		e100_disable_rxdma_irq(info);
+#endif
+
+		if (info->rs485.delay_rts_before_send > 0) {
+			set_current_state(TASK_INTERRUPTIBLE);
+			schedule_timeout((info->rs485.delay_rts_before_send * HZ)/1000);
+		}
+	}
+#endif /* CONFIG_ETRAX_RS485 */
+
+	count = raw_write(tty, from_user, buf, count);
+
+#if defined(CONFIG_ETRAX_RS485)
+	if (info->rs485.enabled)
+	{
+		unsigned int val;
+		/* If we are in RS-485 mode the following has to be done:
+		 * wait until DMA is ready
+		 * wait on transmit shift register
+		 * toggle RTS
+		 * enable the receiver
+		 */	
+
+		/* Sleep until all sent */
+		tty_wait_until_sent(tty, 0);
+#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
+		/* Now sleep a little more so that shift register is empty */
+		schedule_usleep(info->char_time_usec * 2);
+#endif
+		/* wait on transmit shift register */
+		do{
+			get_lsr_info(info, &val);
+		}while (!(val & TIOCSER_TEMT));
+
+		e100_rts(info, info->rs485.rts_after_sent);
+	
+#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
+		e100_enable_rx(info);
+		e100_enable_rxdma_irq(info);
+#endif
+	}
+#endif /* CONFIG_ETRAX_RS485 */
+
+	return count;
 }
 
+
 /* how much space is available in the xmit buffer? */
 
 static int 
@@ -2882,7 +2912,7 @@
 	 unsigned int cmd, unsigned long arg)
 {
 	struct e100_serial * info = (struct e100_serial *)tty->driver_data;
-#if defined(CONFIG_ETRAX_RS485) || (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
+#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
 	int error;
 #endif
 #if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
@@ -2959,22 +2989,22 @@
 
 #if defined(CONFIG_ETRAX_RS485)
 		case TIOCSERSETRS485:
-			error = verify_area(VERIFY_WRITE, (void *) arg,
-					sizeof(struct rs485_control));
-			
-			if (error)
-				return error;
-			
-			return e100_enable_rs485(tty, (struct rs485_control *) arg);
+		{
+			struct rs485_control rs485ctrl;
+			if (copy_from_user(&rs485ctrl, (struct rs485_control*)arg, sizeof(rs485ctrl)))
+				return -EFAULT;
+
+			return e100_enable_rs485(tty, &rs485ctrl);
+		}
 
 		case TIOCSERWRRS485:
-			error = verify_area(VERIFY_WRITE, (void *) arg,
-					sizeof(struct rs485_write));
-			
-			if (error)
-				return error;
-			
-			return e100_write_rs485(tty, (struct rs485_write *) arg);
+		{
+			struct rs485_write rs485wr;
+			if (copy_from_user(&rs485wr, (struct rs485_write*)arg, sizeof(rs485wr)))
+				return -EFAULT;
+
+			return e100_write_rs485(tty, 1, rs485wr.outc, rs485wr.outc_size);
+		}
 #endif
 			
 		default:
@@ -3518,8 +3548,8 @@
 static void 
 show_serial_version(void)
 {
-	printk("ETRAX 100LX serial-driver %s, (c) 2000 Axis Communications AB\r\n",
-	       serial_version);
+	printk("ETRAX 100LX serial-driver %s, (c) 2000-2002 Axis Communications AB\r\n",
+	       &serial_version[11]); /* "$Revision: x.yy" */
 }
 
 /* rs_init inits the driver at boot (using the module_init chain) */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/serial.h linux/arch/cris/drivers/serial.h
--- linux.orig/arch/cris/drivers/serial.h	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/drivers/serial.h	2002-08-01 06:42:39.000000000 +0000
@@ -116,7 +116,7 @@
 	int			break_detected_cnt;
 	int			errorcode;
 
-#ifdef CONFIG_RS485
+#ifdef CONFIG_ETRAX_RS485
 	struct rs485_control	rs485;  /* RS-485 support */
 #endif
 };
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/drivers/sync_serial.c linux/arch/cris/drivers/sync_serial.c
--- linux.orig/arch/cris/drivers/sync_serial.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/drivers/sync_serial.c	2002-08-01 06:42:31.000000000 +0000
@@ -199,7 +199,6 @@
 	/* Deselect synchronous serial ports */
 	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
 	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
-	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, ser3, select);
 	*R_GEN_CONFIG_II = gen_config_ii_shadow;
   
 	/* Initialize Ports */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/kernel/debugport.c linux/arch/cris/kernel/debugport.c
--- linux.orig/arch/cris/kernel/debugport.c	2001-05-01 23:04:56.000000000 +0000
+++ linux/arch/cris/kernel/debugport.c	2002-08-01 06:42:29.000000000 +0000
@@ -12,6 +12,9 @@
  *    init_etrax_debug()
  *
  * $Log: debugport.c,v $
+ * Revision 1.7  2002/04/23 15:35:50  bjornw
+ * Cleaned up sercons struct and removed the waitkey ptr (2.4.19-pre)
+ *
  * Revision 1.6  2001/04/17 13:58:39  orjanf
  * * Renamed CONFIG_KGDB to CONFIG_ETRAX_KGDB.
  *
@@ -224,17 +227,16 @@
 }
 
 static struct console sercons = {
-        "ttyS",
-        console_write,
-        NULL,
-        console_device,
-        NULL,
-	NULL,
-	console_setup,
-	CON_PRINTBUFFER,
-	DEBUG_PORT_IDX,
-	0,
-	NULL
+        name : "ttyS",
+        write: console_write,
+        read : NULL,
+        device : console_device,
+	unblank : NULL,
+	setup : console_setup,
+	flags : CON_PRINTBUFFER,
+	index : DEBUG_PORT_IDX,
+	cflag : 0,
+	next : NULL
 };
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/kernel/entry.S linux/arch/cris/kernel/entry.S
--- linux.orig/arch/cris/kernel/entry.S	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/kernel/entry.S	2002-08-01 06:42:41.000000000 +0000
@@ -1,12 +1,15 @@
-/* $Id: entry.S,v 1.38 2002/01/16 15:15:30 bjornw Exp $
+/* $Id: entry.S,v 1.39 2002/04/24 00:46:45 bjornw Exp $
  *
  *  linux/arch/cris/entry.S
  *
- *  Copyright (C) 2000, 2001 Axis Communications AB
+ *  Copyright (C) 2000, 2001, 2002 Axis Communications AB
  *
  *  Authors:	Bjorn Wesen (bjornw@axis.com)
  *
  *  $Log: entry.S,v $
+ *  Revision 1.39  2002/04/24 00:46:45  bjornw
+ *  Added sys_tkill
+ *
  *  Revision 1.38  2002/01/16 15:15:30  bjornw
  *  Use a C-code compatible watchdog reset when NICE_DOGGY is enabled
  *
@@ -1013,7 +1016,8 @@
         .long SYMBOL_NAME(sys_ni_syscall)       /* Reserved for Security */
         .long SYMBOL_NAME(sys_gettid)
         .long SYMBOL_NAME(sys_readahead)        /* 225 */
-
+	.long SYMBOL_NAME(sys_tkill)
+	
         /*
          * NOTE!! This doesn't have to be exact - we just have
          * to make sure we have _enough_ of the "sys_ni_syscall"
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/kernel/head.S linux/arch/cris/kernel/head.S
--- linux.orig/arch/cris/kernel/head.S	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/kernel/head.S	2002-08-01 06:42:40.000000000 +0000
@@ -1,4 +1,4 @@
-/* $Id: head.S,v 1.43 2001/11/08 15:09:43 starvik Exp $
+/* $Id: head.S,v 1.44 2002/02/05 15:39:57 bjornw Exp $
  * 
  * Head of the kernel - alter with care
  *
@@ -7,6 +7,9 @@
  * Authors:	Bjorn Wesen (bjornw@axis.com)
  * 
  * $Log: head.S,v $
+ * Revision 1.44  2002/02/05 15:39:57  bjornw
+ * Oops.. non-CRAMFS_MAGIC should jump over the copying, not into it...
+ *
  * Revision 1.43  2001/11/08 15:09:43  starvik
  * Only start MII clock if Ethernet is configured
  *
@@ -420,7 +423,7 @@
 	move.d	__vmlinux_end, $r0; the image will be after the vmlinux end address
 	move.d	[$r0], $r1	; cramfs assumes same endian on host/target
 	cmp.d	CRAMFS_MAGIC, $r1; magic value in cramfs superblock
-	bne	1f
+	bne	2f
 	nop
 
 	;; Ok. What is its size ? 
@@ -450,7 +453,8 @@
 	subq	1, $r2
 	bne	1b
 	nop
-	
+
+2:	
 	;; Dont worry that the BSS is tainted. It will be cleared later.
 
 	moveq	0, $r0
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/kernel/signal.c linux/arch/cris/kernel/signal.c
--- linux.orig/arch/cris/kernel/signal.c	2001-10-08 18:43:54.000000000 +0000
+++ linux/arch/cris/kernel/signal.c	2002-08-01 06:42:30.000000000 +0000
@@ -7,7 +7,7 @@
  *
  *  Ideas also taken from arch/arm.
  *
- *  Copyright (C) 2000, 2001 Axis Communications AB
+ *  Copyright (C) 2000, 2001, 2002 Axis Communications AB
  *
  *  Authors:  Bjorn Wesen (bjornw@axis.com)
  *
@@ -679,10 +679,7 @@
 
 			default:
 				lock_kernel();
-				sigaddset(&current->pending.signal, signr);
-				recalc_sigpending(current);
-				current->flags |= PF_SIGNALED;
-				do_exit(exit_code);
+				sig_exit(signr, exit_code, &info);
 				/* NOTREACHED */
 			}
 		}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/kernel/time.c linux/arch/cris/kernel/time.c
--- linux.orig/arch/cris/kernel/time.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/kernel/time.c	2002-08-01 06:42:28.000000000 +0000
@@ -1,4 +1,4 @@
-/* $Id: time.c,v 1.11 2001/11/12 18:26:22 pkj Exp $
+/* $Id: time.c,v 1.14 2002/03/05 13:31:03 johana Exp $
  *
  *  linux/arch/cris/kernel/time.c
  *
@@ -19,6 +19,12 @@
  *
  * Authors:    Bjorn Wesen
  *             Johan Adolfsson  
+ * 2002-03-04    Johan Adolfsson
+ *      Use prescale timer at 25000 Hz instead of the baudrate timer at 
+ *      19200 to get rid of the 64ppm to fast timer (and we get better 
+ *      resolution within a jiffie as well.
+ * 2002-03-05    Johan Adolfsson
+ *      Use prescaler in do_slow_gettimeoffset() to get 1 us resolution (40ns)
  *
  */
 
@@ -44,6 +50,8 @@
 
 #include <asm/svinto.h>
 
+#define CRIS_TEST_TIMERS 0
+
 static int have_rtc;  /* used to remember if we have an RTC or not */
 
 /* define this if you need to use print_timestamp */
@@ -52,19 +60,85 @@
 
 extern int setup_etrax_irq(int, struct irqaction *);
 
-/* Lookup table to convert *R_TIMER0 to microseconds (us) 
- * Timer goes from TIMER0_DIV down to 1 meaning 0-10000us in step of approx 52us
- */
-unsigned short cris_timer0_value_us[TIMER0_DIV+1];
-
 #define TICK_SIZE tick
 
+/* The timers count from their initial value down to 1 
+ * The R_TIMER0_DATA counts down when R_TIM_PRESC_STATUS reaches halv
+ * of the divider value.
+ */ 
+unsigned long get_ns_in_jiffie(void)
+{
+	unsigned char timer_count, t1;
+	unsigned short presc_count;
+	unsigned long ns;
+	unsigned long flags;
+
+	save_flags(flags);
+	cli();	
+	timer_count = *R_TIMER0_DATA;
+	presc_count = *R_TIM_PRESC_STATUS;  
+	/* presc_count might be wrapped */
+	t1 = *R_TIMER0_DATA;
+
+	if (timer_count != t1){
+		/* it wrapped, read prescaler again...  */
+		presc_count = *R_TIM_PRESC_STATUS;
+		timer_count = t1;
+	}
+	restore_flags(flags);
+	if (presc_count >= PRESCALE_VALUE/2 ){
+		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
+	} else {
+		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
+	}
+
+	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + 
+	     ( (presc_count) * (1000000000/PRESCALE_FREQ));
+	return ns;
+}
+
+
+
+#if CRIS_TEST_TIMERS 
+#define NS_TEST_SIZE 4000
+static unsigned long ns_test[NS_TEST_SIZE];
+void cris_test_timers(void)
+{
+	int i;
+#if 0
+	for (i = 0; i < NS_TEST_SIZE; i++)
+	{
+		ns_test[i] = *R_TIMER0_DATA | (*R_TIM_PRESC_STATUS<<16);
+	}
+	for (i = 1; i < NS_TEST_SIZE; i++)
+	{
+		printk("%4i. %lu %lu %09lu ns \n",
+		       i, ns_test[i]&0x0FFFF, (ns_test[i]>>16), 
+	get_ns_in_jiffie_from_data(ns_test[i]&0x0FFFF, ns_test[i]>>16));
+	}
+#else
+	for (i = 0; i < NS_TEST_SIZE; i++)
+	{
+		ns_test[i] = get_ns_in_jiffie();
+	}
+
+	for (i = 1; i < NS_TEST_SIZE; i++)
+	{
+		printk("%4i. %09lu ns diff %li ns\n",
+		       i, ns_test[i], ns_test[i]- ns_test[i-1]);
+	}
+#endif
+}
+
+#endif
+
 static unsigned long do_slow_gettimeoffset(void)
 {
-	unsigned long count;
+	unsigned long count, t1;
 	unsigned long usec_count = 0;
+	unsigned short presc_count;
 
-	static unsigned long count_p = LATCH;    /* for the first call after boot */
+	static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
 	static unsigned long jiffies_p = 0;
 
 	/*
@@ -80,8 +154,17 @@
 #ifndef CONFIG_SVINTO_SIM
 	/* Not available in the xsim simulator. */
 	count = *R_TIMER0_DATA;
+	presc_count = *R_TIM_PRESC_STATUS;  
+	/* presc_count might be wrapped */
+	t1 = *R_TIMER0_DATA;
+	if (count != t1){
+		/* it wrapped, read prescaler again...  */
+		presc_count = *R_TIM_PRESC_STATUS;
+		count = t1;
+	}
 #else
 	count = 0;
+	presc_count = 0;
 #endif
 
  	jiffies_t = jiffies;
@@ -92,22 +175,26 @@
 	 *  1. the timer counter underflows
 	 *  2. we are after the timer interrupt, but the bottom half handler
 	 *     hasn't executed yet.
- */
+	 */
 	if( jiffies_t == jiffies_p ) {
 		if( count > count_p ) {
-			/* Timer wrapped */
-			count = count_p;
-			usec_count = 1000000/CLOCK_TICK_RATE/2;
+			/* Timer wrapped, use new count and prescale 
+			 * increase the time corresponding to one jiffie
+			 */
+			usec_count = 1000000/HZ;
 		}
 	} else
 		jiffies_p = jiffies_t;
         count_p = count;
-	/* Convert timer value to usec using table lookup */
-	usec_count += cris_timer0_value_us[count];
-#if 0
-	count = ((LATCH-1) - count) * TICK_SIZE;
-	count = (count + LATCH/2) / LATCH;
-#endif
+	if (presc_count >= PRESCALE_VALUE/2 ){
+		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
+	} else {
+		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
+	}
+	/* Convert timer value to usec */
+	usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
+	              (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
+
 	return usec_count;
 }
 
@@ -124,11 +211,11 @@
 	cli();
 	*tv = xtime;
 	tv->tv_usec += do_gettimeoffset();
-	if (tv->tv_usec >= 1000000) {
+	restore_flags(flags);
+	while (tv->tv_usec >= 1000000) {
 		tv->tv_usec -= 1000000;
 		tv->tv_sec++;
 	}
-	restore_flags(flags);
 }
 
 void do_settimeofday(struct timeval *tv)
@@ -392,7 +479,6 @@
 void __init
 time_init(void)
 {	
-	int i;
 	/* probe for the RTC and read it if it exists */
 
 	if(RTC_INIT() < 0) {
@@ -435,33 +521,33 @@
 		IO_STATE( R_TIMER_CTRL, tm0, run) |
 		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 #else
+  
 	*R_TIMER_CTRL = 
 		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
-		IO_FIELD(R_TIMER_CTRL, timerdiv0, 192)      |
+		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 		IO_STATE(R_TIMER_CTRL, i1,        nop)      | 
 		IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 		IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
-		IO_STATE(R_TIMER_CTRL, clksel0,   c19k2Hz);
+		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 	
 	*R_TIMER_CTRL = r_timer_ctrl_shadow =
 		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
-		IO_FIELD(R_TIMER_CTRL, timerdiv0, 192)      |
+		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 		IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 		IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 		IO_STATE(R_TIMER_CTRL, tm0,       run)      |
-		IO_STATE(R_TIMER_CTRL, clksel0,   c19k2Hz);
+		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
+
+	*R_TIMER_PRESCALE = PRESCALE_VALUE;
 #endif
 
-	for (i=0; i <= TIMER0_DIV; i++) {
-		/* We must be careful not to get overflow... */
-		cris_timer0_value_us[TIMER0_DIV-i] = 
-		  (unsigned short)((unsigned long)
-		  ((i*(1000000/HZ))/TIMER0_DIV)&0x0000FFFFL);
-	}
+#if CRIS_TEST_TIMERS
+	cris_test_timers();
+#endif
 	
 	*R_IRQ_MASK0_SET =
 		IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/mm/extable.c linux/arch/cris/mm/extable.c
--- linux.orig/arch/cris/mm/extable.c	2001-10-08 18:43:54.000000000 +0000
+++ linux/arch/cris/mm/extable.c	2002-08-01 06:42:45.000000000 +0000
@@ -2,6 +2,9 @@
  * linux/arch/cris/mm/extable.c
  *
  * $Log: extable.c,v $
+ * Revision 1.4  2002/03/19 15:21:10  bjornw
+ * Fixed warning
+ *
  * Revision 1.3  2001/09/27 13:52:40  bjornw
  * Harmonize underscore-ness with other parts
  *
@@ -39,13 +42,12 @@
 unsigned long
 search_exception_table(unsigned long addr)
 {
-	unsigned long ret;
-
 #ifndef CONFIG_MODULES
 	/* There is only the kernel to search.  */
 	return search_one_table(__start___ex_table, __stop___ex_table-1, addr);
 #else
 	/* The kernel is the last "module" -- no need to treat it special.  */
+	unsigned long ret;
 	struct module *mp;
 	for (mp = module_list; mp != NULL; mp = mp->next) {
 		if (mp->ex_table_start == NULL)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/mm/fault.c linux/arch/cris/mm/fault.c
--- linux.orig/arch/cris/mm/fault.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/mm/fault.c	2002-08-01 06:42:39.000000000 +0000
@@ -437,7 +437,7 @@
 	 * Send a sigbus, regardless of whether we were in kernel
 	 * or user mode.
 	 */
-	info.si_code = SIGBUS;
+	info.si_signo = SIGBUS;
 	info.si_errno = 0;
 	info.si_code = BUS_ADRERR;
 	info.si_addr = (void *)address;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/cris/mm/init.c linux/arch/cris/mm/init.c
--- linux.orig/arch/cris/mm/init.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/cris/mm/init.c	2002-08-01 06:42:43.000000000 +0000
@@ -7,6 +7,18 @@
  *  Authors:  Bjorn Wesen (bjornw@axis.com)
  *
  *  $Log: init.c,v $
+ *  Revision 1.35  2002/05/17 05:33:59  starvik
+ *  Limit cache flush range to the size of the cache
+ *
+ *  Revision 1.34  2002/04/22 11:48:51  johana
+ *  Added KERN_INFO (2.4.19-pre7)
+ *
+ *  Revision 1.33  2002/03/19 15:22:17  bjornw
+ *  Added flush_etrax_cache
+ *
+ *  Revision 1.32  2002/03/15 17:09:31  bjornw
+ *  Added prepare_rx_descriptor as a workaround for a bug
+ *
  *  Revision 1.31  2001/11/13 16:22:00  bjornw
  *  Skip calculating totalram and sharedram in si_meminfo
  *
@@ -219,13 +231,15 @@
 #ifndef CONFIG_CRIS_LOW_MAP
 	/* This code is for the corrected Etrax-100 LX version 2... */
 
+#define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
+
 	*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg  ) | /* cached flash */
 			IO_STATE(R_MMU_KSEG, seg_e, seg  ) | /* uncached flash */
 			IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
 			IO_STATE(R_MMU_KSEG, seg_c, seg  ) | /* kernel area */
 			IO_STATE(R_MMU_KSEG, seg_b, seg  ) | /* kernel reg area */
-			IO_STATE(R_MMU_KSEG, seg_a, page ) | /* user area */
-			IO_STATE(R_MMU_KSEG, seg_9, page ) |
+			IO_STATE(R_MMU_KSEG, seg_a, seg  ) | /* bootrom/regs cached */ 
+			IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
 			IO_STATE(R_MMU_KSEG, seg_8, page ) |
 			IO_STATE(R_MMU_KSEG, seg_7, page ) |
 			IO_STATE(R_MMU_KSEG, seg_6, page ) |
@@ -241,7 +255,7 @@
 			    IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
-			    IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
+			    IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
 	
@@ -268,7 +282,9 @@
 	 * We map them straight over in LOW_MAP, but use vremap in LX version 2.
 	 */
 
-	*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, page ) | 
+#define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
+
+	*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg  ) |  /* cached bootrom/regs */ 
 			IO_STATE(R_MMU_KSEG, seg_e, page ) |
 			IO_STATE(R_MMU_KSEG, seg_d, page ) | 
 			IO_STATE(R_MMU_KSEG, seg_c, page ) |   
@@ -289,7 +305,7 @@
 			IO_STATE(R_MMU_KSEG, seg_1, page ) |  /* user area */
 			IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
 
-	*R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
+	*R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
 			    IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
@@ -450,6 +466,48 @@
         }
 }
 
+/* Helper function for the two below */
+
+static inline void
+flush_etrax_cacherange(void *startadr, int length)
+{
+	/* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
+	 * we can use to get fast dummy-reads of cachelines
+	 */
+
+	volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
+						      CACHED_BOOTROM);
+
+	length = length > 8192 ? 8192 : length;  /* No need to flush more than cache size */
+
+	while(length > 0) {
+		short tmp = *flushadr;           /* dummy read to flush */
+		flushadr += (32/sizeof(short));  /* a cacheline is 32 bytes */
+		length -= 32;
+	}
+}
+
+/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
+ * will occationally corrupt certain CPU writes if the DMA buffers
+ * happen to be hot in the cache.
+ * 
+ * As a workaround, we have to flush the relevant parts of the cache
+ * before (re) inserting any receiving descriptor into the DMA HW.
+ */
+
+void
+prepare_rx_descriptor(struct etrax_dma_descr *desc)
+{
+	flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
+}
+
+/* Do the same thing but flush the entire cache */
+
+void
+flush_etrax_cache(void)
+{
+	flush_etrax_cacherange(0, 8192);
+}
 
 /* free the pages occupied by initialization code */
 
@@ -465,7 +523,7 @@
                 free_page(addr);
                 totalram_pages++;
         }
-        printk ("Freeing unused kernel memory: %luk freed\n", 
+        printk (KERN_INFO "Freeing unused kernel memory: %luk freed\n", 
 		(&__init_end - &__init_begin) >> 10);
 }
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/boot/compressed/misc.c linux/arch/i386/boot/compressed/misc.c
--- linux.orig/arch/i386/boot/compressed/misc.c	2001-11-12 17:59:43.000000000 +0000
+++ linux/arch/i386/boot/compressed/misc.c	2002-08-01 06:42:45.000000000 +0000
@@ -125,7 +125,7 @@
 static int lines, cols;
 
 #ifdef CONFIG_MULTIQUAD
-static void *xquad_portio = NULL;
+static void * const xquad_portio = NULL;
 #endif
 
 #include "../../../../lib/inflate.c"
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/boot/setup.S linux/arch/i386/boot/setup.S
--- linux.orig/arch/i386/boot/setup.S	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/i386/boot/setup.S	2002-08-01 06:42:28.000000000 +0000
@@ -805,7 +805,7 @@
 #
 #	but we yet haven't reloaded the CS register, so the default size 
 #	of the target offset still is 16 bit.
-#       However, using an operant prefix (0x66), the CPU will properly
+#       However, using an operand prefix (0x66), the CPU will properly
 #	take our 48 bit far pointer. (INTeL 80386 Programmer's Reference
 #	Manual, Mixing 16-bit and 32-bit code, page 16-6)
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/config.in linux/arch/i386/config.in
--- linux.orig/arch/i386/config.in	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/i386/config.in	2002-08-01 06:42:38.000000000 +0000
@@ -42,7 +42,7 @@
 	 Winchip-C6				CONFIG_MWINCHIPC6 \
 	 Winchip-2				CONFIG_MWINCHIP2 \
 	 Winchip-2A/Winchip-3			CONFIG_MWINCHIP3D \
-	 CyrixIII/C3				CONFIG_MCYRIXIII" Pentium-Pro
+	 CyrixIII/VIA-C3/VIA-C5			CONFIG_MCYRIXIII" Pentium-Pro
 #
 # Define implied options from the CPU selection here
 #
@@ -163,6 +163,9 @@
    define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
    define_bool CONFIG_X86_OOSTORE y
 fi
+
+bool 'Machine Check Exception' CONFIG_X86_MCE
+
 tristate 'Toshiba Laptop support' CONFIG_TOSHIBA
 tristate 'Dell laptop support' CONFIG_I8K
 
@@ -407,9 +410,7 @@
 
 source drivers/usb/Config.in
 
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
-   source net/bluetooth/Config.in
-fi
+source net/bluetooth/Config.in
 
 mainmenu_option next_comment
 comment 'Kernel hacking'
@@ -421,7 +422,7 @@
    bool '  Memory mapped I/O debugging' CONFIG_DEBUG_IOVIRT
    bool '  Magic SysRq key' CONFIG_MAGIC_SYSRQ
    bool '  Spinlock debugging' CONFIG_DEBUG_SPINLOCK
-   bool '  Verbose BUG() reporting (adds 70K)' CONFIG_DEBUG_BUGVERBOSE
+   bool '  Compile the kernel with frame pointers' CONFIG_FRAME_POINTER
 fi
 
 endmenu
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/defconfig linux/arch/i386/defconfig
--- linux.orig/arch/i386/defconfig	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/i386/defconfig	2002-08-01 06:42:32.000000000 +0000
@@ -31,6 +31,7 @@
 # CONFIG_MPENTIUM4 is not set
 # CONFIG_MK6 is not set
 # CONFIG_MK7 is not set
+# CONFIG_MELAN is not set
 # CONFIG_MCRUSOE is not set
 # CONFIG_MWINCHIPC6 is not set
 # CONFIG_MWINCHIP2 is not set
@@ -49,6 +50,7 @@
 CONFIG_X86_GOOD_APIC=y
 CONFIG_X86_PGE=y
 CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_MCE=y
 # CONFIG_TOSHIBA is not set
 # CONFIG_I8K is not set
 # CONFIG_MICROCODE is not set
@@ -85,9 +87,9 @@
 #
 CONFIG_PCMCIA=y
 CONFIG_CARDBUS=y
+# CONFIG_TCIC is not set
 # CONFIG_I82092 is not set
 # CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
 
 #
 # PCI Hotplug Support
@@ -95,6 +97,8 @@
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HOTPLUG_PCI_COMPAQ is not set
 # CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set
+# CONFIG_HOTPLUG_PCI_IBM is not set
+# CONFIG_HOTPLUG_PCI_ACPI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
@@ -130,7 +134,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
@@ -153,7 +159,7 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -166,12 +172,18 @@
 # CONFIG_IP_MROUTE is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 
@@ -181,6 +193,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -204,6 +221,7 @@
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_BLK_DEV_IDEDISK=y
 CONFIG_IDEDISK_MULTI_MODE=y
+# CONFIG_IDEDISK_STROKE is not set
 # CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
 # CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
 # CONFIG_BLK_DEV_IDEDISK_IBM is not set
@@ -218,6 +236,7 @@
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
 
 #
 # IDE chipset support/bugfixes
@@ -229,12 +248,15 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
 CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
 CONFIG_BLK_DEV_IDEDMA=y
 # CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
 # CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_AEC62XX_TUNING is not set
 # CONFIG_BLK_DEV_ALI15X3 is not set
@@ -242,6 +264,7 @@
 # CONFIG_BLK_DEV_AMD74XX is not set
 # CONFIG_AMD74XX_OVERRIDE is not set
 # CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CMD680 is not set
 # CONFIG_BLK_DEV_CY82C693 is not set
 # CONFIG_BLK_DEV_CS5530 is not set
 # CONFIG_BLK_DEV_HPT34X is not set
@@ -394,7 +417,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -411,6 +433,7 @@
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
 # CONFIG_TULIP is not set
+# CONFIG_TC35815 is not set
 # CONFIG_DE4X5 is not set
 # CONFIG_DGRS is not set
 # CONFIG_DM9102 is not set
@@ -426,11 +449,13 @@
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_NET_POCKET is not set
 
@@ -444,6 +469,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_PLIP is not set
 # CONFIG_PPP is not set
@@ -473,10 +499,10 @@
 # CONFIG_PCMCIA_3C574 is not set
 # CONFIG_PCMCIA_FMVJ18X is not set
 CONFIG_PCMCIA_PCNET=y
+# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_PCMCIA_NMCLAN is not set
 # CONFIG_PCMCIA_SMC91C92 is not set
 # CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_ARCNET_COM20020_CS is not set
 # CONFIG_PCMCIA_IBMTR is not set
 # CONFIG_PCMCIA_XIRCOM is not set
@@ -496,9 +522,6 @@
 # IrDA (infrared) support
 #
 # CONFIG_IRDA is not set
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRDA_DEBUG=y
 
 #
 # ISDN subsystem
@@ -544,6 +567,7 @@
 CONFIG_PSMOUSE=y
 # CONFIG_82C710_MOUSE is not set
 # CONFIG_PC110_PAD is not set
+# CONFIG_MK712_MOUSE is not set
 
 #
 # Joysticks
@@ -563,6 +587,7 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
+# CONFIG_AMD_RNG is not set
 # CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
@@ -583,12 +608,18 @@
 CONFIG_AGP_ALI=y
 # CONFIG_AGP_SWORKS is not set
 CONFIG_DRM=y
+# CONFIG_DRM_OLD is not set
+
+#
+# DRM 4.1 drivers
+#
+CONFIG_DRM_NEW=y
 CONFIG_DRM_TDFX=y
-# CONFIG_DRM_GAMMA is not set
 # CONFIG_DRM_R128 is not set
 CONFIG_DRM_RADEON=y
 # CONFIG_DRM_I810 is not set
 # CONFIG_DRM_MGA is not set
+# CONFIG_DRM_SIS is not set
 
 #
 # PCMCIA character devices
@@ -627,7 +658,7 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 CONFIG_TMPFS=y
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 CONFIG_ISO9660_FS=y
 # CONFIG_JOLIET is not set
 # CONFIG_ZISOFS is not set
@@ -730,8 +761,9 @@
 # CONFIG_USB_LONG_TIMEOUT is not set
 
 #
-# USB Controllers
+# USB Host Controller Drivers
 #
+# CONFIG_USB_EHCI_HCD is not set
 CONFIG_USB_UHCI_ALT=y
 # CONFIG_USB_OHCI is not set
 
@@ -739,6 +771,7 @@
 # USB Device Class drivers
 #
 # CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
 # CONFIG_USB_BLUETOOTH is not set
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
@@ -755,10 +788,16 @@
 #
 # USB Human Interface Devices (HID)
 #
+# CONFIG_USB_HID is not set
 
 #
-#   Input core support is needed for USB HID
+#     Input core support is needed for USB HID input layer or HIDBP support
 #
+# CONFIG_USB_HIDINPUT is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_WACOM is not set
 
 #
 # USB Imaging devices
@@ -781,6 +820,7 @@
 # USB Network adaptors
 #
 # CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_CATC is not set
 # CONFIG_USB_CDCETHER is not set
@@ -802,6 +842,7 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
 # CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
@@ -815,6 +856,7 @@
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
@@ -824,6 +866,13 @@
 # USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_BRLVGER is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
 
 #
 # Kernel hacking
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/acpitable.c linux/arch/i386/kernel/acpitable.c
--- linux.orig/arch/i386/kernel/acpitable.c	2001-11-12 03:15:06.000000000 +0000
+++ linux/arch/i386/kernel/acpitable.c	2002-08-01 06:42:46.000000000 +0000
@@ -172,40 +172,41 @@
 
 
 /*
- * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_0,
+ * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
  * to map the target physical address. The problem is that set_fixmap()
  * provides a single page, and it is possible that the page is not
  * sufficient.
  * By using this area, we can map up to MAX_IO_APICS pages temporarily,
  * i.e. until the next __va_range() call.
+ *
+ * Important Safety Note:  The fixed I/O APIC page numbers are *subtracted*
+ * from the fixed base.  That's why we start at FIX_IO_APIC_BASE_END and
+ * count idx down while incrementing the phys address.
  */
-static __inline__ char *
+static __init char *
 __va_range(unsigned long phys, unsigned long size)
 {
-	unsigned long base, offset, mapped_size, mapped_phys = phys;
-	int idx = FIX_IO_APIC_BASE_0;
+	unsigned long base, offset, mapped_size;
+	int idx;
 
 	offset = phys & (PAGE_SIZE - 1);
 	mapped_size = PAGE_SIZE - offset;
-	set_fixmap(idx, mapped_phys);
-	base = fix_to_virt(FIX_IO_APIC_BASE_0);
+	set_fixmap(FIX_IO_APIC_BASE_END, phys);
+	base = fix_to_virt(FIX_IO_APIC_BASE_END);
+	dprintk("__va_range(0x%lx, 0x%lx): idx=%d mapped at %lx\n", phys, size,
+		FIX_IO_APIC_BASE_END, base);
 
 	/*
 	 * Most cases can be covered by the below.
 	 */
-	if (mapped_size >= size)
-		return ((unsigned char *) base + offset);
-
-	dprintk("__va_range: mapping more than a single page, size = 0x%lx\n",
-		size);
-
-	do {
-		if (idx++ == FIX_IO_APIC_BASE_END)
+	idx = FIX_IO_APIC_BASE_END;
+	while (mapped_size < size) {
+		if (--idx < FIX_IO_APIC_BASE_0)
 			return 0;	/* cannot handle this */
-		mapped_phys = mapped_phys + PAGE_SIZE;
-		set_fixmap(idx, mapped_phys);
-		mapped_size = mapped_size + PAGE_SIZE;
-	} while (mapped_size < size);
+		phys += PAGE_SIZE;
+		set_fixmap(idx, phys);
+		mapped_size += PAGE_SIZE;
+	}
 
 	return ((unsigned char *) base + offset);
 }
@@ -267,11 +268,14 @@
 	}
 
 	for (i = 0; i < tables; i++) {
-
+		/* Map in header, then map in full table length. */
 		header = (acpi_table_header *)
 			    __va_range(saved_rsdt.entry[i],
 				       sizeof(acpi_table_header));
-
+		if (!header)
+			break;
+		header = (acpi_table_header *)
+			    __va_range(saved_rsdt.entry[i], header->length);
 		if (!header)
 			break;
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/apic.c linux/arch/i386/kernel/apic.c
--- linux.orig/arch/i386/kernel/apic.c	2002-02-25 19:37:52.000000000 +0000
+++ linux/arch/i386/kernel/apic.c	2002-08-01 06:42:44.000000000 +0000
@@ -582,12 +582,17 @@
  * Detect and enable local APICs on non-SMP boards.
  * Original code written by Keir Fraser.
  */
+int dont_enable_local_apic __initdata = 0;
 
 static int __init detect_init_APIC (void)
 {
 	u32 h, l, features;
 	extern void get_cpu_vendor(struct cpuinfo_x86*);
 
+	/* Disabled by DMI scan or kernel option? */
+	if (dont_enable_local_apic)
+		return -1;
+
 	/* Workaround for us being called before identify_cpu(). */
 	get_cpu_vendor(&boot_cpu_data);
 
@@ -679,7 +684,15 @@
 		for (i = 0; i < nr_ioapics; i++) {
 			if (smp_found_config) {
 				ioapic_phys = mp_ioapics[i].mpc_apicaddr;
+				if (!ioapic_phys) {
+					printk(KERN_ERR "WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO/APIC support!\n");
+
+					smp_found_config = 0;
+					skip_ioapic_setup = 1;
+					goto fake_ioapic_page;
+				}
 			} else {
+fake_ioapic_page:
 				ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
 				ioapic_phys = __pa(ioapic_phys);
 			}
@@ -796,8 +809,7 @@
 	 */
 
 	slice = clocks / (smp_num_cpus+1);
-	printk("cpu: %d, clocks: %d, slice: %d\n",
-		smp_processor_id(), clocks, slice);
+	printk("cpu: %d, clocks: %d, slice: %d\n", smp_processor_id(), clocks, slice);
 
 	/*
 	 * Wait for IRQ0's slice:
@@ -820,8 +832,7 @@
 
 	__setup_APIC_LVTT(clocks);
 
-	printk("CPU%d<T0:%d,T1:%d,D:%d,S:%d,C:%d>\n",
-			smp_processor_id(), t0, t1, delta, slice, clocks);
+	printk("CPU%d<T0:%d,T1:%d,D:%d,S:%d,C:%d>\n", smp_processor_id(), t0, t1, delta, slice, clocks);
 
 	__restore_flags(flags);
 }
@@ -905,8 +916,14 @@
 
 static unsigned int calibration_result;
 
+int dont_use_local_apic_timer __initdata = 0;
+
 void __init setup_APIC_clocks (void)
 {
+	/* Disabled by DMI scan or kernel option? */
+	if (dont_use_local_apic_timer)
+		return;
+
 	printk("Using local APIC timer interrupts.\n");
 	using_apic_timer = 1;
 
@@ -924,6 +941,26 @@
 	smp_call_function(setup_APIC_timer, (void *)calibration_result, 1, 1);
 }
 
+void __init disable_APIC_timer(void)
+{
+	if (using_apic_timer) {
+		unsigned long v;
+
+		v = apic_read(APIC_LVTT);
+		apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+	}
+}
+
+void enable_APIC_timer(void)
+{
+	if (using_apic_timer) {
+		unsigned long v;
+
+		v = apic_read(APIC_LVTT);
+		apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
+	}
+}
+
 /*
  * the frequency of the profiling timer can be changed
  * by writing a multiplier value into /proc/profile.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/apm.c linux/arch/i386/kernel/apm.c
--- linux.orig/arch/i386/kernel/apm.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/apm.c	2002-08-01 06:42:30.000000000 +0000
@@ -275,10 +275,11 @@
  */
 
 /*
- * Define to always call the APM BIOS busy routine even if the clock was
- * not slowed by the idle routine.
+ * Define as 1 to make the driver always call the APM BIOS busy
+ * routine even if the clock was not reported as slowed by the
+ * idle routine.  Otherwise, define as 0.
  */
-#define ALWAYS_CALL_BUSY
+#define ALWAYS_CALL_BUSY   1
 
 /*
  * Define to make the APM BIOS calls zero all data segment registers (so
@@ -380,7 +381,7 @@
 static int			set_pm_idle;
 static int			suspends_pending;
 static int			standbys_pending;
-static int			waiting_for_resume;
+static int			ignore_sys_suspend;
 static int			ignore_normal_resume;
 static int			bounce_interval = DEFAULT_BOUNCE_INTERVAL;
 
@@ -470,6 +471,28 @@
 };
 #define ERROR_COUNT	(sizeof(error_table)/sizeof(lookup_t))
 
+/**
+ *	apm_error	-	display an APM error
+ *	@str: information string
+ *	@err: APM BIOS return code
+ *
+ *	Write a meaningful log entry to the kernel log in the event of
+ *	an APM error.
+ */
+ 
+static void apm_error(char *str, int err)
+{
+	int	i;
+
+	for (i = 0; i < ERROR_COUNT; i++)
+		if (error_table[i].key == err) break;
+	if (i < ERROR_COUNT)
+		printk(KERN_NOTICE "apm: %s: %s\n", str, error_table[i].msg);
+	else
+		printk(KERN_NOTICE "apm: %s: unknown error code %#2.2x\n",
+			str, err);
+}
+
 /*
  * These are the actual BIOS calls.  Depending on APM_ZERO_SEGS and
  * apm_info.allow_ints, we are being really paranoid here!  Not only
@@ -701,13 +724,13 @@
 }
 
 /**
- *	apm_set_power_state - set system wide power state
+ *	set_system_power_state - set system wide power state
  *	@state: which state to enter
  *
  *	Transition the entire system into a new APM power state.
  */
  
-static int apm_set_power_state(u_short state)
+static int set_system_power_state(u_short state)
 {
 	return set_power_state(APM_DEVICE_ALL, state);
 }
@@ -724,7 +747,6 @@
 static int apm_do_idle(void)
 {
 	u32	eax;
-	int	slowed;
 
 	if (apm_bios_call_simple(APM_FUNC_IDLE, 0, 0, &eax)) {
 		static unsigned long t;
@@ -736,13 +758,8 @@
 		}
 		return -1;
 	}
-	slowed = (apm_info.bios.flags & APM_IDLE_SLOWS_CLOCK) != 0;
-#ifdef ALWAYS_CALL_BUSY
-	clock_slowed = 1;
-#else
-	clock_slowed = slowed;
-#endif
-	return slowed;
+	clock_slowed = (apm_info.bios.flags & APM_IDLE_SLOWS_CLOCK) != 0;
+	return clock_slowed;
 }
 
 /**
@@ -755,7 +772,7 @@
 {
 	u32	dummy;
 
-	if (clock_slowed) {
+	if (clock_slowed || ALWAYS_CALL_BUSY) {
 		(void) apm_bios_call_simple(APM_FUNC_BUSY, 0, 0, &dummy);
 		clock_slowed = 0;
 	}
@@ -770,7 +787,7 @@
 #define IDLE_CALC_LIMIT   (HZ * 100)
 #define IDLE_LEAKY_MAX    16
 
-static void (*sys_idle)(void);
+static void (*original_pm_idle)(void);
 
 extern void default_idle(void);
 
@@ -784,14 +801,13 @@
 
 static void apm_cpu_idle(void)
 {
-	static int use_apm_idle = 0;
-	static unsigned int last_jiffies = 0;
-	static unsigned int last_stime = 0;
+	static int use_apm_idle; /* = 0 */
+	static unsigned int last_jiffies; /* = 0 */
+	static unsigned int last_stime; /* = 0 */
 
-	int apm_is_idle = 0;
+	int apm_idle_done = 0;
 	unsigned int jiffies_since_last_check = jiffies - last_jiffies;
-	unsigned int t1;
-
+	unsigned int bucket;
 
 recalc:
 	if (jiffies_since_last_check > IDLE_CALC_LIMIT) {
@@ -809,7 +825,7 @@
 		last_stime = current->times.tms_stime;
 	}
 
-	t1 = IDLE_LEAKY_MAX;
+	bucket = IDLE_LEAKY_MAX;
 
 	while (!current->need_resched) {
 		if (use_apm_idle) {
@@ -817,23 +833,24 @@
 
 			t = jiffies;
 			switch (apm_do_idle()) {
-			case 0: apm_is_idle = 1;
+			case 0: apm_idle_done = 1;
 				if (t != jiffies) {
-					if (t1) {
-						t1 = IDLE_LEAKY_MAX;
+					if (bucket) {
+						bucket = IDLE_LEAKY_MAX;
 						continue;
 					}
-				} else if (t1) {
-					t1--;
+				} else if (bucket) {
+					bucket--;
 					continue;
 				}
 				break;
-			case 1: apm_is_idle = 1;
+			case 1: apm_idle_done = 1;
 				break;
+			default: /* BIOS refused */
 			}
 		}
-		if (sys_idle)
-			sys_idle();
+		if (original_pm_idle)
+			original_pm_idle();
 		else
 			default_idle();
 		jiffies_since_last_check = jiffies - last_jiffies;
@@ -841,7 +858,7 @@
 			goto recalc;
 	}
 
-	if (apm_is_idle)
+	if (apm_idle_done)
 		apm_do_busy();
 }
 
@@ -889,7 +906,7 @@
 	if (apm_info.realmode_power_off)
 		machine_real_restart(po_bios_call, sizeof(po_bios_call));
 	else
-		(void) apm_set_power_state(APM_STATE_OFF);
+		(void) set_system_power_state(APM_STATE_OFF);
 }
 
 /**
@@ -1034,28 +1051,6 @@
 	return APM_SUCCESS;
 }
 
-/**
- *	apm_error	-	display an APM error
- *	@str: information string
- *	@err: APM BIOS return code
- *
- *	Write a meaningful log entry to the kernel log in the event of
- *	an APM error.
- */
- 
-static void apm_error(char *str, int err)
-{
-	int	i;
-
-	for (i = 0; i < ERROR_COUNT; i++)
-		if (error_table[i].key == err) break;
-	if (i < ERROR_COUNT)
-		printk(KERN_NOTICE "apm: %s: %s\n", str, error_table[i].msg);
-	else
-		printk(KERN_NOTICE "apm: %s: unknown error code %#2.2x\n",
-			str, err);
-}
-
 #if defined(CONFIG_APM_DISPLAY_BLANK) && defined(CONFIG_VT)
 
 /**
@@ -1194,20 +1189,21 @@
 		/* Vetoed */
 		if (vetoable) {
 			if (apm_info.connection_version > 0x100)
-				apm_set_power_state(APM_STATE_REJECT);
+				set_system_power_state(APM_STATE_REJECT);
 			err = -EBUSY;
-			waiting_for_resume = 0;
+			ignore_sys_suspend = 0;
 			printk(KERN_WARNING "apm: suspend was vetoed.\n");
 			goto out;
 		}
 		printk(KERN_CRIT "apm: suspend was vetoed, but suspending anyway.\n");
 	}
 	get_time_diff();
-	cli();
-	err = apm_set_power_state(APM_STATE_SUSPEND);
+	__cli();
+	err = set_system_power_state(APM_STATE_SUSPEND);
 	reinit_timer();
 	set_time();
-	sti();
+	ignore_normal_resume = 1;
+	__sti();
 	if (err == APM_NO_ERROR)
 		err = APM_SUCCESS;
 	if (err != APM_SUCCESS)
@@ -1215,7 +1211,6 @@
 	err = (err == APM_SUCCESS) ? 0 : -EIO;
 	pm_send_all(PM_RESUME, (void *)0);
 	queue_event(APM_NORMAL_RESUME, NULL);
-	ignore_normal_resume = 1;
  out:
 	for (as = user_list; as != NULL; as = as->next) {
 		as->suspend_wait = 0;
@@ -1231,7 +1226,7 @@
 
 	/* If needed, notify drivers here */
 	get_time_diff();
-	err = apm_set_power_state(APM_STATE_STANDBY);
+	err = set_system_power_state(APM_STATE_STANDBY);
 	if ((err != APM_SUCCESS) && (err != APM_NO_ERROR))
 		apm_error("standby", err);
 }
@@ -1285,13 +1280,13 @@
 		case APM_USER_SUSPEND:
 #ifdef CONFIG_APM_IGNORE_USER_SUSPEND
 			if (apm_info.connection_version > 0x100)
-				apm_set_power_state(APM_STATE_REJECT);
+				set_system_power_state(APM_STATE_REJECT);
 			break;
 #endif
 		case APM_SYS_SUSPEND:
 			if (ignore_bounce) {
 				if (apm_info.connection_version > 0x100)
-					apm_set_power_state(APM_STATE_REJECT);
+					set_system_power_state(APM_STATE_REJECT);
 				break;
 			}
 			/*
@@ -1302,9 +1297,9 @@
 			 * sending a SUSPEND event until something else
 			 * happens!
 			 */
-			if (waiting_for_resume)
+			if (ignore_sys_suspend)
 				return;
-			waiting_for_resume = 1;
+			ignore_sys_suspend = 1;
 			queue_event(event, NULL);
 			if (suspends_pending <= 0)
 				(void) suspend(1);
@@ -1313,7 +1308,7 @@
 		case APM_NORMAL_RESUME:
 		case APM_CRITICAL_RESUME:
 		case APM_STANDBY_RESUME:
-			waiting_for_resume = 0;
+			ignore_sys_suspend = 0;
 			last_resume = jiffies;
 			ignore_bounce = 1;
 			if ((event != APM_NORMAL_RESUME)
@@ -1357,7 +1352,7 @@
 			pending_count = 4;
 			if (debug)
 				printk(KERN_DEBUG "apm: setting state busy\n");
-			err = apm_set_power_state(APM_STATE_BUSY);
+			err = set_system_power_state(APM_STATE_BUSY);
 			if (err)
 				apm_error("busy", err);
 		}
@@ -1788,7 +1783,7 @@
 			idle_threshold = simple_strtol(str + 15, NULL, 0);
 		if ((strncmp(str, "idle-period=", 12) == 0) ||
 		    (strncmp(str, "idle_period=", 12) == 0))
-			idle_threshold = simple_strtol(str + 15, NULL, 0);
+			idle_period = simple_strtol(str + 12, NULL, 0);
 		invert = (strncmp(str, "no-", 3) == 0) ||
 			(strncmp(str, "no_", 3) == 0);
 		if (invert)
@@ -1964,7 +1959,7 @@
 	if (HZ != 100)
 		idle_period = (idle_period * HZ) / 100;
 	if (idle_threshold < 100) {
-		sys_idle = pm_idle;
+		original_pm_idle = pm_idle;
 		pm_idle  = apm_cpu_idle;
 		set_pm_idle = 1;
 	}
@@ -1977,7 +1972,7 @@
 	int	error;
 
 	if (set_pm_idle)
-		pm_idle = sys_idle;
+		pm_idle = original_pm_idle;
 	if (((apm_info.bios.flags & APM_BIOS_DISENGAGED) == 0)
 	    && (apm_info.connection_version > 0x0100)) {
 		error = apm_engage_power_management(APM_DEVICE_ALL, 0);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/bluesmoke.c linux/arch/i386/kernel/bluesmoke.c
--- linux.orig/arch/i386/kernel/bluesmoke.c	2001-11-12 17:59:43.000000000 +0000
+++ linux/arch/i386/kernel/bluesmoke.c	2002-08-01 06:42:39.000000000 +0000
@@ -3,9 +3,12 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/config.h>
 #include <asm/processor.h> 
 #include <asm/msr.h>
 
+#ifdef CONFIG_X86_MCE
+
 static int mce_disabled __initdata = 0;
 
 /*
@@ -41,13 +44,12 @@
 			if(high&(1<<27))
 			{
 				rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
-				printk("[%08x%08x]", alow, ahigh);
+				printk("[%08x%08x]", ahigh, alow);
 			}
 			if(high&(1<<26))
 			{
 				rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
-				printk(" at %08x%08x", 
-					high, low);
+				printk(" at %08x%08x", ahigh, alow);
 			}
 			printk("\n");
 			/* Clear it */
@@ -247,3 +249,8 @@
 
 __setup("nomce", mcheck_disable);
 __setup("mce", mcheck_enable);
+
+#else
+asmlinkage void do_machine_check(struct pt_regs * regs, long error_code) {}
+void __init mcheck_init(struct cpuinfo_x86 *c) {}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/dmi_scan.c linux/arch/i386/kernel/dmi_scan.c
--- linux.orig/arch/i386/kernel/dmi_scan.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/dmi_scan.c	2002-08-01 06:42:40.000000000 +0000
@@ -9,6 +9,7 @@
 #include <linux/pm.h>
 #include <asm/keyboard.h>
 #include <asm/system.h>
+#include <linux/bootmem.h>
 
 unsigned long dmi_broken;
 int is_sony_vaio_laptop;
@@ -51,7 +52,7 @@
 	u8 *data;
 	int i=1;
 		
-	buf = ioremap(base, len);
+	buf = bt_ioremap(base, len);
 	if(buf==NULL)
 		return -1;
 
@@ -83,7 +84,7 @@
 		data+=2;
 		i++;
 	}
-	iounmap(buf);
+	bt_iounmap(buf, len);
 	return 0;
 }
 
@@ -155,7 +156,7 @@
 		return;
 	if (dmi_ident[slot])
 		return;
-	dmi_ident[slot] = kmalloc(strlen(p)+1, GFP_KERNEL);
+	dmi_ident[slot] = alloc_bootmem(strlen(p)+1);
 	if(dmi_ident[slot])
 		strcpy(dmi_ident[slot], p);
 	else
@@ -292,6 +293,62 @@
 	return 0;
 }
 
+/*
+ * Some machines, usually laptops, can't handle an enabled local APIC.
+ * The symptoms include hangs or reboots when suspending or resuming,
+ * attaching or detaching the power cord, or entering BIOS setup screens
+ * through magic key sequences.
+ */
+static int __init local_apic_kills_bios(struct dmi_blacklist *d)
+{
+#ifdef CONFIG_X86_LOCAL_APIC
+	extern int dont_enable_local_apic;
+	if (!dont_enable_local_apic) {
+		dont_enable_local_apic = 1;
+		printk(KERN_WARNING "%s with broken BIOS detected. "
+		       "Refusing to enable the local APIC.\n",
+		       d->ident);
+	}
+#endif
+	return 0;
+}
+
+/*
+ * The Microstar 6163-2 (a.k.a Pro) mainboard will hang shortly after
+ * resumes, and also at what appears to be asynchronous APM events,
+ * if the local APIC is enabled.
+ */
+static int __init apm_kills_local_apic(struct dmi_blacklist *d)
+{
+#ifdef CONFIG_X86_LOCAL_APIC
+	extern int dont_enable_local_apic;
+	if (apm_info.bios.version && !dont_enable_local_apic) {
+		dont_enable_local_apic = 1;
+		printk(KERN_WARNING "%s with broken BIOS detected. "
+		       "Refusing to enable the local APIC.\n",
+		       d->ident);
+	}
+#endif
+	return 0;
+}
+
+/*
+ * The Intel AL440LX mainboard will hang randomly if the local APIC
+ * timer is running and the APM BIOS hasn't been disabled.
+ */
+static int __init apm_kills_local_apic_timer(struct dmi_blacklist *d)
+{
+#ifdef CONFIG_X86_LOCAL_APIC
+	extern int dont_use_local_apic_timer;
+	if (apm_info.bios.version && !dont_use_local_apic_timer) {
+		dont_use_local_apic_timer = 1;
+		printk(KERN_WARNING "%s with broken BIOS detected. "
+		       "The local APIC timer will not be used.\n",
+		       d->ident);
+	}
+#endif
+	return 0;
+}
 
 /*
  *  Check for clue free BIOS implementations who use
@@ -353,6 +410,7 @@
  * The MP1.4 table is right however and so SMP kernels tend to work. 
  */
  
+extern int skip_ioapic_setup;
 static __init int broken_pirq(struct dmi_blacklist *d)
 {
 	printk(KERN_INFO " *** Possibly defective BIOS detected (irqtable)\n");
@@ -360,6 +418,9 @@
 	printk(KERN_INFO " *** If you see IRQ problems, in paticular SCSI resets and hangs at boot\n");
 	printk(KERN_INFO " *** contact your hardware vendor and ask about updates.\n");
 	printk(KERN_INFO " *** Building an SMP kernel may evade the bug some of the time.\n");
+#ifdef CONFIG_X86_IO_APIC
+	skip_ioapic_setup = 0;
+#endif
 	return 0;
 }
 
@@ -452,6 +513,11 @@
 			MATCH(DMI_BIOS_VERSION, "A04"),
 			MATCH(DMI_BIOS_DATE, "08/24/2000"), NO_MATCH
 			} },
+	{ broken_apm_power, "Dell Inspiron 2500", {	/* Handle problems with APM on Inspiron 2500 */
+			MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
+			MATCH(DMI_BIOS_VERSION, "A12"),
+			MATCH(DMI_BIOS_DATE, "02/04/2002"), NO_MATCH
+			} },
 	{ set_realmode_power_off, "Award Software v4.60 PGMA", {	/* broken PM poweroff bios */
 			MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
 			MATCH(DMI_BIOS_VERSION, "4.60 PGMA"),
@@ -493,12 +559,23 @@
 			MATCH(DMI_PRODUCT_NAME, "Delhi3"),
 			NO_MATCH, NO_MATCH,
 			} },
+	{ apm_is_horked, "Fujitsu-Siemens", { /* APM crashes */
+			MATCH(DMI_BIOS_VENDOR, "hoenix/FUJITSU SIEMENS"),
+			MATCH(DMI_BIOS_VERSION, "Version1.01"),
+			NO_MATCH, NO_MATCH,
+			} },
 	{ apm_is_horked, "Sharp PC-PJ/AX", { /* APM crashes */
 			MATCH(DMI_SYS_VENDOR, "SHARP"),
 			MATCH(DMI_PRODUCT_NAME, "PC-PJ/AX"),
 			MATCH(DMI_BIOS_VENDOR,"SystemSoft"),
 			MATCH(DMI_BIOS_VERSION,"Version R2.08")
 			} },
+	{ apm_is_horked, "Dell Inspiron 2500", { /* APM crashes */
+			MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"),
+			MATCH(DMI_PRODUCT_NAME, "Inspiron 2500"),
+			MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
+			MATCH(DMI_BIOS_VERSION,"A11")
+			} },
 	{ sony_vaio_laptop, "Sony Vaio", { /* This is a Sony Vaio laptop */
 			MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
 			MATCH(DMI_PRODUCT_NAME, "PCG-"),
@@ -534,6 +611,12 @@
 			MATCH(DMI_BIOS_DATE, "08/11/00"), NO_MATCH
 			} },
 
+	{ swab_apm_power_in_minutes, "Sony VAIO", {	/* Handle problems with APM on Sony Vaio PCG-Z600LEK(DE) */
+			MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
+			MATCH(DMI_BIOS_VERSION, "R0206Z3"),
+			MATCH(DMI_BIOS_DATE, "12/25/00"), NO_MATCH
+			} },
+
 	{ swab_apm_power_in_minutes, "Sony VAIO", {	/* Handle problems with APM on Sony Vaio PCG-Z505LS */
 			MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
 			MATCH(DMI_BIOS_VERSION, "R0203D0"),
@@ -546,6 +629,12 @@
 			MATCH(DMI_BIOS_DATE, "08/25/00"), NO_MATCH
 			} },
 	
+	{ swab_apm_power_in_minutes, "Sony VAIO", {	/* Handle problems with APM on Sony Vaio PCG-Z505LS (with updated BIOS) */
+			MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
+			MATCH(DMI_BIOS_VERSION, "R0209Z3"),
+			MATCH(DMI_BIOS_DATE, "05/12/01"), NO_MATCH
+			} },
+	
 	{ swab_apm_power_in_minutes, "Sony VAIO", {	/* Handle problems with APM on Sony Vaio PCG-F104K */
 			MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
 			MATCH(DMI_BIOS_VERSION, "R0204K2"),
@@ -563,6 +652,36 @@
 			MATCH(DMI_BIOS_DATE, "09/12/00"), NO_MATCH
 			} },
 
+	/* Machines which have problems handling enabled local APICs */
+
+	{ local_apic_kills_bios, "Dell Inspiron", {
+			MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"),
+			MATCH(DMI_PRODUCT_NAME, "Inspiron"),
+			NO_MATCH, NO_MATCH
+			} },
+
+	{ local_apic_kills_bios, "Dell Latitude", {
+			MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"),
+			MATCH(DMI_PRODUCT_NAME, "Latitude"),
+			NO_MATCH, NO_MATCH
+			} },
+
+	{ local_apic_kills_bios, "IBM Thinkpad T20", {
+			MATCH(DMI_BOARD_VENDOR, "IBM"),
+			MATCH(DMI_BOARD_NAME, "264741U"),
+			NO_MATCH, NO_MATCH
+			} },
+
+	{ apm_kills_local_apic, "Microstar 6163", {
+			MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
+			MATCH(DMI_BOARD_NAME, "MS-6163"),
+			NO_MATCH, NO_MATCH } },
+
+	{ apm_kills_local_apic_timer, "Intel AL440LX", {
+			MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
+			MATCH(DMI_BOARD_NAME, "AL440LX"),
+			NO_MATCH, NO_MATCH } },
+
 	/* Problem Intel 440GX bioses */
 
 	{ broken_pirq, "SABR1 Bios", {			/* Bad $PIR */
@@ -731,12 +850,9 @@
 	}
 }
 
-static int __init dmi_scan_machine(void)
+void __init dmi_scan_machine(void)
 {
 	int err = dmi_iterate(dmi_decode);
 	if(err == 0)
 		dmi_check_blacklist();
-	return err;
 }
-
-module_init(dmi_scan_machine);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/entry.S linux/arch/i386/kernel/entry.S
--- linux.orig/arch/i386/kernel/entry.S	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/entry.S	2002-08-01 06:42:37.000000000 +0000
@@ -634,6 +634,11 @@
 	.long SYMBOL_NAME(sys_ni_syscall)	/* 235 reserved for removexattr */
 	.long SYMBOL_NAME(sys_ni_syscall)	/* reserved for lremovexattr */
 	.long SYMBOL_NAME(sys_ni_syscall)	/* reserved for fremovexattr */
+ 	.long SYMBOL_NAME(sys_tkill)
+	.long SYMBOL_NAME(sys_ni_syscall)	/* reserved for sendfile64 */
+	.long SYMBOL_NAME(sys_ni_syscall)	/* 240 reserved for futex */
+	.long SYMBOL_NAME(sys_ni_syscall)	/* reserved for sched_setaffinity */
+	.long SYMBOL_NAME(sys_ni_syscall)	/* reserved for sched_getaffinity */
 
 	.rept NR_syscalls-(.-sys_call_table)/4
 		.long SYMBOL_NAME(sys_ni_syscall)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/head.S linux/arch/i386/kernel/head.S
--- linux.orig/arch/i386/kernel/head.S	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/head.S	2002-08-01 06:42:31.000000000 +0000
@@ -178,7 +178,7 @@
  * we don't need to preserve eflags.
  */
 
-	movl $3,X86		# at least 386
+	movb $3,X86		# at least 386
 	pushfl			# push EFLAGS
 	popl %eax		# get EFLAGS
 	movl %eax,%ecx		# save original EFLAGS
@@ -191,7 +191,7 @@
 	andl $0x40000,%eax	# check if AC bit changed
 	je is386
 
-	movl $4,X86		# at least 486
+	movb $4,X86		# at least 486
 	movl %ecx,%eax
 	xorl $0x200000,%eax	# check ID flag
 	pushl %eax
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/i386_ksyms.c linux/arch/i386/kernel/i386_ksyms.c
--- linux.orig/arch/i386/kernel/i386_ksyms.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/i386_ksyms.c	2002-08-01 06:42:43.000000000 +0000
@@ -73,6 +73,7 @@
 EXPORT_SYMBOL(get_cmos_time);
 EXPORT_SYMBOL(apm_info);
 EXPORT_SYMBOL(gdt);
+EXPORT_SYMBOL(empty_zero_page);
 
 #ifdef CONFIG_DEBUG_IOVIRT
 EXPORT_SYMBOL(__io_virt_debug);
@@ -126,7 +127,7 @@
 
 #ifdef CONFIG_SMP
 EXPORT_SYMBOL(cpu_data);
-EXPORT_SYMBOL(kernel_flag);
+EXPORT_SYMBOL(kernel_flag_cacheline);
 EXPORT_SYMBOL(smp_num_cpus);
 EXPORT_SYMBOL(cpu_online_map);
 EXPORT_SYMBOL_NOVERS(__write_lock_failed);
@@ -145,6 +146,10 @@
 EXPORT_SYMBOL(flush_tlb_page);
 #endif
 
+#ifdef CONFIG_X86_IO_APIC
+EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
+#endif
+
 #ifdef CONFIG_MCA
 EXPORT_SYMBOL(machine_id);
 #endif
@@ -168,9 +173,9 @@
 EXPORT_SYMBOL(atomic_dec_and_lock);
 #endif
 
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-EXPORT_SYMBOL(do_BUG);
-#endif
-
 extern int is_sony_vaio_laptop;
 EXPORT_SYMBOL(is_sony_vaio_laptop);
+
+#ifdef CONFIG_MULTIQUAD
+EXPORT_SYMBOL(xquad_portio);
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/i387.c linux/arch/i386/kernel/i387.c
--- linux.orig/arch/i386/kernel/i387.c	2001-02-23 18:09:08.000000000 +0000
+++ linux/arch/i386/kernel/i387.c	2002-08-01 06:42:48.000000000 +0000
@@ -10,6 +10,7 @@
 
 #include <linux/config.h>
 #include <linux/sched.h>
+#include <linux/init.h>
 #include <asm/processor.h>
 #include <asm/i387.h>
 #include <asm/math_emu.h>
@@ -24,6 +25,29 @@
 #define HAVE_HWFP 1
 #endif
 
+static union i387_union empty_fpu_state;
+
+void __init boot_init_fpu(void)
+{
+	memset(&empty_fpu_state, 0, sizeof(union i387_union));
+
+	if (!cpu_has_fxsr) {
+		empty_fpu_state.fsave.cwd = 0xffff037f;
+		empty_fpu_state.fsave.swd = 0xffff0000;
+		empty_fpu_state.fsave.twd = 0xffffffff;
+		empty_fpu_state.fsave.fos = 0xffff0000;
+	} else {
+		empty_fpu_state.fxsave.cwd = 0x37f;
+		if (cpu_has_xmm)
+			empty_fpu_state.fxsave.mxcsr = 0x1f80;
+	}
+}
+
+void load_empty_fpu(struct task_struct * tsk)
+{
+	memcpy(&tsk->thread.i387, &empty_fpu_state, sizeof(union i387_union));
+}
+
 /*
  * The _current_ task is using the FPU for the first time
  * so initialize it and set the mxcsr to its default
@@ -32,10 +56,10 @@
  */
 void init_fpu(void)
 {
-	__asm__("fninit");
-	if ( cpu_has_xmm )
-		load_mxcsr(0x1f80);
-		
+	if (cpu_has_fxsr)
+		asm volatile("fxrstor %0" : : "m" (empty_fpu_state.fxsave));
+	else
+		__asm__("fninit");
 	current->used_math = 1;
 }
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/io_apic.c linux/arch/i386/kernel/io_apic.c
--- linux.orig/arch/i386/kernel/io_apic.c	2001-11-14 01:28:41.000000000 +0000
+++ linux/arch/i386/kernel/io_apic.c	2002-08-01 06:42:39.000000000 +0000
@@ -67,7 +67,7 @@
  * shared ISA-space IRQs, so we have to support them. We are super
  * fast in the common case, and fast for shared ISA-space IRQs.
  */
-static void add_pin_to_irq(unsigned int irq, int apic, int pin)
+static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
 {
 	static int first_free_entry = NR_IRQS;
 	struct irq_pin_list *entry = irq_2_pin + irq;
@@ -85,6 +85,26 @@
 	entry->pin = pin;
 }
 
+/*
+ * Reroute an IRQ to a different pin.
+ */
+static void __init replace_pin_at_irq(unsigned int irq,
+				      int oldapic, int oldpin,
+				      int newapic, int newpin)
+{
+	struct irq_pin_list *entry = irq_2_pin + irq;
+
+	while (1) {
+		if (entry->apic == oldapic && entry->pin == oldpin) {
+			entry->apic = newapic;
+			entry->pin = newpin;
+		}
+		if (!entry->next)
+			break;
+		entry = irq_2_pin + entry->next;
+	}
+}
+
 #define __DO_ACTION(R, ACTION, FINAL)					\
 									\
 {									\
@@ -173,13 +193,21 @@
 int pirqs_enabled;
 int skip_ioapic_setup;
 
-static int __init ioapic_setup(char *str)
+static int __init noioapic_setup(char *str)
 {
 	skip_ioapic_setup = 1;
 	return 1;
 }
 
-__setup("noapic", ioapic_setup);
+__setup("noapic", noioapic_setup);
+
+static int __init ioapic_setup(char *str)
+{
+	skip_ioapic_setup = 0;
+	return 1;
+}
+
+__setup("apic", ioapic_setup);
 
 static int __init ioapic_pirq_setup(char *str)
 {
@@ -622,7 +650,14 @@
 		}
 
 		irq = pin_2_irq(idx, apic, pin);
-		add_pin_to_irq(irq, apic, pin);
+		/*
+		 * skip adding the timer int on secondary nodes, which causes
+		 * a small but painful rift in the time-space continuum
+		 */
+		if (clustered_apic_mode && (apic != 0) && (irq == 0))
+			continue;
+		else
+			add_pin_to_irq(irq, apic, pin);
 
 		if (!apic && !IO_APIC_IRQ(irq))
 			continue;
@@ -1533,6 +1568,10 @@
 		setup_ExtINT_IRQ0_pin(pin2, vector);
 		if (timer_irq_works()) {
 			printk("works.\n");
+			if (pin1 != -1)
+				replace_pin_at_irq(0, 0, pin1, 0, pin2);
+			else
+				add_pin_to_irq(0, 0, pin2);
 			if (nmi_watchdog == NMI_IO_APIC) {
 				setup_nmi();
 				check_nmi_watchdog();
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/microcode.c linux/arch/i386/kernel/microcode.c
--- linux.orig/arch/i386/kernel/microcode.c	2001-10-30 23:13:17.000000000 +0000
+++ linux/arch/i386/kernel/microcode.c	2002-08-01 06:42:35.000000000 +0000
@@ -51,6 +51,12 @@
  *		Bugfix for HT (Hyper-Threading) enabled processors
  *		whereby processor resources are shared by all logical processors
  *		in a single CPU package.
+ *	1.10	28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
+ *		Tigran Aivazian <tigran@veritas.com>,
+ *		Serialize updates as required on HT processors due to speculative
+ *		nature of implementation.
+ *	1.11	22 Mar 2001 Tigran Aivazian <tigran@veritas.com>
+ *		Fix the panic when writing zero-length microcode chunk.
  */
 
 #include <linux/init.h>
@@ -60,12 +66,16 @@
 #include <linux/vmalloc.h>
 #include <linux/miscdevice.h>
 #include <linux/devfs_fs_kernel.h>
+#include <linux/spinlock.h>
 
 #include <asm/msr.h>
 #include <asm/uaccess.h>
 #include <asm/processor.h>
 
-#define MICROCODE_VERSION 	"1.09"
+
+static spinlock_t microcode_update_lock = SPIN_LOCK_UNLOCKED;
+
+#define MICROCODE_VERSION 	"1.11"
 
 MODULE_DESCRIPTION("Intel CPU (IA-32) microcode update driver");
 MODULE_AUTHOR("Tigran Aivazian <tigran@veritas.com>");
@@ -195,7 +205,8 @@
 	struct cpuinfo_x86 *c = cpu_data + cpu_num;
 	struct update_req *req = update_req + cpu_num;
 	unsigned int pf = 0, val[2], rev, sig;
-	int i,found=0;
+	unsigned long flags;
+	int i;
 
 	req->err = 1; /* assume update will fail on this cpu */
 
@@ -216,8 +227,9 @@
 	for (i=0; i<microcode_num; i++)
 		if (microcode[i].sig == sig && microcode[i].pf == pf &&
 		    microcode[i].ldrver == 1 && microcode[i].hdrver == 1) {
-
-			found=1;
+			int sum = 0;
+			struct microcode *m = &microcode[i];
+			unsigned int *sump = (unsigned int *)(m+1);
 
 			printf("Microcode\n");
 			printf("   Header Revision %d\n",microcode[i].hdrver);
@@ -234,54 +246,69 @@
 			printf("   Loader Revision %x\n",microcode[i].ldrver);
 			printf("   Processor Flags %x\n\n",microcode[i].pf);
 
+			req->slot = i;
+
+			/* serialize access to update decision */
+			spin_lock_irqsave(&microcode_update_lock, flags);          
+
 			/* trick, to work even if there was no prior update by the BIOS */
 			wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 			__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
 
 			/* get current (on-cpu) revision into rev (ignore val[0]) */
 			rdmsr(MSR_IA32_UCODE_REV, val[0], rev);
+			
 			if (microcode[i].rev < rev) {
+				spin_unlock_irqrestore(&microcode_update_lock, flags);
 				printk(KERN_ERR 
-					"microcode: CPU%d not 'upgrading' to earlier revision"
+				       "microcode: CPU%d not 'upgrading' to earlier revision"
+				       " %d (current=%d)\n", cpu_num, microcode[i].rev, rev);
+				return;
+			} else if (microcode[i].rev == rev) {
+				/* notify the caller of success on this cpu */
+				req->err = 0;
+				spin_unlock_irqrestore(&microcode_update_lock, flags);
+				printk(KERN_ERR 
+					"microcode: CPU%d already at revision"
 					" %d (current=%d)\n", cpu_num, microcode[i].rev, rev);
-			} else {
-				int sum = 0;
-				struct microcode *m = &microcode[i];
-				unsigned int *sump = (unsigned int *)(m+1);
-
-				while (--sump >= (unsigned int *)m)
-					sum += *sump;
-				if (sum != 0) {
-					printk(KERN_ERR "microcode: CPU%d aborting, "
-							"bad checksum\n", cpu_num);
-					break;
-				}
-
-				/* write microcode via MSR 0x79 */
-				wrmsr(MSR_IA32_UCODE_WRITE, (unsigned int)(m->bits), 0);
+				return;
+			}
 
-				/* serialize */
-				__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
+			/* Verify the checksum */
+			while (--sump >= (unsigned int *)m)
+				sum += *sump;
+			if (sum != 0) {
+				req->err = 1;
+				spin_unlock_irqrestore(&microcode_update_lock, flags);
+				printk(KERN_ERR "microcode: CPU%d aborting, "
+				       "bad checksum\n", cpu_num);
+				return;
+			}
+			
+			/* write microcode via MSR 0x79 */
+			wrmsr(MSR_IA32_UCODE_WRITE, (unsigned int)(m->bits), 0);
 
-				/* get the current revision from MSR 0x8B */
-				rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
+			/* serialize */
+			__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
 
-				/* notify the caller of success on this cpu */
-				req->err = 0;
-				req->slot = i;
+			/* get the current revision from MSR 0x8B */
+			rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
 
-				printk(KERN_INFO "microcode: CPU%d updated from revision "
-						"%d to %d, date=%08x\n", 
-						cpu_num, rev, val[1], m->date);
-			}
-			break;
+			/* notify the caller of success on this cpu */
+			req->err = 0;
+			spin_unlock_irqrestore(&microcode_update_lock, flags);
+			printk(KERN_INFO "microcode: CPU%d updated from revision "
+			       "%d to %d, date=%08x\n", 
+			       cpu_num, rev, val[1], microcode[i].date);
+			return;
 		}
-
-	if(!found)
-		printk(KERN_ERR "microcode: CPU%d no microcode found! (sig=%x, pflags=%d)\n",
-				cpu_num, sig, pf);
+	
+	printk(KERN_ERR
+	       "microcode: CPU%d no microcode found! (sig=%x, pflags=%d)\n", 
+	       cpu_num, sig, pf);
 }
 
+
 static ssize_t microcode_read(struct file *file, char *buf, size_t len, loff_t *ppos)
 {
 	ssize_t ret = 0;
@@ -305,11 +332,15 @@
 {
 	ssize_t ret;
 
-	if (len % sizeof(struct microcode) != 0) {
+	if (!len || len % sizeof(struct microcode) != 0) {
 		printk(KERN_ERR "microcode: can only write in N*%d bytes units\n", 
 			sizeof(struct microcode));
 		return -EINVAL;
 	}
+	if ((len >> PAGE_SHIFT) > num_physpages) {
+		printk(KERN_ERR "microcode: too much data (max %ld pages)\n", num_physpages);
+		return -EINVAL;
+	}
 	down_write(&microcode_rwsem);
 	if (!mc_applied) {
 		mc_applied = kmalloc(smp_num_cpus*sizeof(struct microcode),
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/mpparse.c linux/arch/i386/kernel/mpparse.c
--- linux.orig/arch/i386/kernel/mpparse.c	2001-11-09 22:58:18.000000000 +0000
+++ linux/arch/i386/kernel/mpparse.c	2002-08-01 06:42:38.000000000 +0000
@@ -37,6 +37,8 @@
 int apic_version [MAX_APICS];
 int mp_bus_id_to_type [MAX_MP_BUSSES];
 int mp_bus_id_to_node [MAX_MP_BUSSES];
+int mp_bus_id_to_local [MAX_MP_BUSSES];
+int quad_local_to_mp_bus_id [NR_CPUS/4][4];
 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
 int mp_current_pci_id;
 
@@ -241,13 +243,17 @@
 static void __init MP_bus_info (struct mpc_config_bus *m)
 {
 	char str[7];
+	int quad;
 
 	memcpy(str, m->mpc_bustype, 6);
 	str[6] = 0;
 	
 	if (clustered_apic_mode) {
-		mp_bus_id_to_node[m->mpc_busid] = translation_table[mpc_record]->trans_quad;
-		printk("Bus #%d is %s (node %d)\n", m->mpc_busid, str, mp_bus_id_to_node[m->mpc_busid]);
+		quad = translation_table[mpc_record]->trans_quad;
+		mp_bus_id_to_node[m->mpc_busid] = quad;
+		mp_bus_id_to_local[m->mpc_busid] = translation_table[mpc_record]->trans_local;
+		quad_local_to_mp_bus_id[quad][translation_table[mpc_record]->trans_local] = m->mpc_busid;
+		printk("Bus #%d is %s (node %d)\n", m->mpc_busid, str, quad);
 	} else {
 		Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
 	}
@@ -324,13 +330,14 @@
 
 static void __init MP_translation_info (struct mpc_config_translation *m)
 {
-	printk("Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, 
-		m->trans_quad, m->trans_global, m->trans_local);
+	printk("Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
 
 	if (mpc_record >= MAX_MPC_ENTRY) 
 		printk("MAX_MPC_ENTRY exceeded!\n");
 	else
 		translation_table[mpc_record] = m; /* stash this for later */
+	if (m->trans_quad+1 > numnodes)
+		numnodes = m->trans_quad+1;
 }
 
 /*
@@ -495,10 +502,6 @@
 		}
 		++mpc_record;
 	}
-	if (clustered_apic_mode && nr_ioapics > 2) {
-		/* don't initialise IO apics on secondary quads */
-		nr_ioapics = 2;
-	}
 	if (!num_processors)
 		printk(KERN_ERR "SMP mptable: no processors registered!\n");
 	return num_processors;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/mtrr.c linux/arch/i386/kernel/mtrr.c
--- linux.orig/arch/i386/kernel/mtrr.c	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/i386/kernel/mtrr.c	2002-08-01 06:42:30.000000000 +0000
@@ -378,10 +378,8 @@
 static int arr3_protected;
 
 /*  Put the processor into a state where MTRRs can be safely set  */
-static void set_mtrr_prepare (struct set_mtrr_context *ctxt)
+static void set_mtrr_prepare_save (struct set_mtrr_context *ctxt)
 {
-    unsigned long tmp;
-
     /*  Disable interrupts locally  */
     __save_flags (ctxt->flags); __cli ();
 
@@ -404,16 +402,27 @@
     }
 
     if ( mtrr_if == MTRR_IF_INTEL ) {
-	/*  Disable MTRRs, and set the default type to uncached  */
+	/*  Save MTRR state */
 	rdmsr (MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
+    } else {
+	/* Cyrix ARRs - everything else were excluded at the top */
+	ctxt->ccr3 = getCx86 (CX86_CCR3);
+    }
+}   /*  End Function set_mtrr_prepare_save  */
+
+static void set_mtrr_disable (struct set_mtrr_context *ctxt)
+{
+    if ( mtrr_if != MTRR_IF_INTEL && mtrr_if != MTRR_IF_CYRIX_ARR )
+	 return;
+
+    if ( mtrr_if == MTRR_IF_INTEL ) {
+	/*  Disable MTRRs, and set the default type to uncached  */
 	wrmsr (MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL, ctxt->deftype_hi);
     } else {
 	/* Cyrix ARRs - everything else were excluded at the top */
-	tmp = getCx86 (CX86_CCR3);
-	setCx86 (CX86_CCR3, (tmp & 0x0f) | 0x10);
-	ctxt->ccr3 = tmp;
+	setCx86 (CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
     }
-}   /*  End Function set_mtrr_prepare  */
+}   /*  End Function set_mtrr_disable  */
 
 /*  Restore the processor after a set_mtrr_prepare  */
 static void set_mtrr_done (struct set_mtrr_context *ctxt)
@@ -674,7 +683,10 @@
 {
     struct set_mtrr_context ctxt;
 
-    if (do_safe) set_mtrr_prepare (&ctxt);
+    if (do_safe) {
+	set_mtrr_prepare_save (&ctxt);
+	set_mtrr_disable (&ctxt);
+	}
     if (size == 0)
     {
 	/* The invalid bit is kept in the mask, so we simply clear the
@@ -726,7 +738,10 @@
 	}
     }
 
-    if (do_safe) set_mtrr_prepare (&ctxt);
+    if (do_safe) {
+	set_mtrr_prepare_save (&ctxt);
+	set_mtrr_disable (&ctxt);
+    }
     base <<= PAGE_SHIFT;
     setCx86(arr,    ((unsigned char *) &base)[3]);
     setCx86(arr+1,  ((unsigned char *) &base)[2]);
@@ -750,7 +765,10 @@
     u32 regs[2];
     struct set_mtrr_context ctxt;
 
-    if (do_safe) set_mtrr_prepare (&ctxt);
+    if (do_safe) {
+	set_mtrr_prepare_save (&ctxt);
+	set_mtrr_disable (&ctxt);
+    }
     /*
      *	Low is MTRR0 , High MTRR 1
      */
@@ -788,7 +806,10 @@
     struct set_mtrr_context ctxt;
     unsigned long low, high;
 
-    if (do_safe) set_mtrr_prepare( &ctxt );
+    if (do_safe) {
+	set_mtrr_prepare_save (&ctxt);
+	set_mtrr_disable (&ctxt);
+    }
     if (size == 0)
     {
         /*  Disable  */
@@ -985,6 +1006,7 @@
 
 
 static atomic_t undone_count;
+static volatile int wait_barrier_mtrr_disable = FALSE;
 static volatile int wait_barrier_execute = FALSE;
 static volatile int wait_barrier_cache_enable = FALSE;
 
@@ -1003,18 +1025,21 @@
 {
     struct set_mtrr_data *data = info;
     struct set_mtrr_context ctxt;
-
-    set_mtrr_prepare (&ctxt);
+    set_mtrr_prepare_save (&ctxt);
     /*  Notify master that I've flushed and disabled my cache  */
     atomic_dec (&undone_count);
-    while (wait_barrier_execute) barrier ();
+    while (wait_barrier_mtrr_disable) { rep_nop(); barrier(); }
+    set_mtrr_disable (&ctxt);
+    /*  Notify master that I've flushed and disabled my cache  */
+    atomic_dec (&undone_count);
+    while (wait_barrier_execute) { rep_nop(); barrier(); }
     /*  The master has cleared me to execute  */
     (*set_mtrr_up) (data->smp_reg, data->smp_base, data->smp_size,
 		    data->smp_type, FALSE);
     /*  Notify master CPU that I've executed the function  */
     atomic_dec (&undone_count);
     /*  Wait for master to clear me to enable cache and return  */
-    while (wait_barrier_cache_enable) barrier ();
+    while (wait_barrier_cache_enable) { rep_nop(); barrier(); }
     set_mtrr_done (&ctxt);
 }   /*  End Function ipi_handler  */
 
@@ -1028,6 +1053,7 @@
     data.smp_base = base;
     data.smp_size = size;
     data.smp_type = type;
+    wait_barrier_mtrr_disable = TRUE;
     wait_barrier_execute = TRUE;
     wait_barrier_cache_enable = TRUE;
     atomic_set (&undone_count, smp_num_cpus - 1);
@@ -1035,15 +1061,22 @@
     if (smp_call_function (ipi_handler, &data, 1, 0) != 0)
 	panic ("mtrr: timed out waiting for other CPUs\n");
     /* Flush and disable the local CPU's cache */
-    set_mtrr_prepare (&ctxt);
+    set_mtrr_prepare_save (&ctxt);
+    /*  Wait for all other CPUs to flush and disable their caches  */
+    while (atomic_read (&undone_count) > 0) { rep_nop(); barrier(); }
+    /* Set up for completion wait and then release other CPUs to change MTRRs*/
+    atomic_set (&undone_count, smp_num_cpus - 1);
+    wait_barrier_mtrr_disable = FALSE;
+    set_mtrr_disable (&ctxt);
+
     /*  Wait for all other CPUs to flush and disable their caches  */
-    while (atomic_read (&undone_count) > 0) barrier ();
+    while (atomic_read (&undone_count) > 0) { rep_nop(); barrier(); }
     /* Set up for completion wait and then release other CPUs to change MTRRs*/
     atomic_set (&undone_count, smp_num_cpus - 1);
     wait_barrier_execute = FALSE;
     (*set_mtrr_up) (reg, base, size, type, FALSE);
     /*  Now wait for other CPUs to complete the function  */
-    while (atomic_read (&undone_count) > 0) barrier ();
+    while (atomic_read (&undone_count) > 0) { rep_nop(); barrier(); }
     /*  Now all CPUs should have finished the function. Release the barrier to
 	allow them to re-enable their caches and return from their interrupt,
 	then enable the local cache and return  */
@@ -1889,7 +1922,9 @@
     struct set_mtrr_context ctxt;
     int i;
 
-    set_mtrr_prepare (&ctxt); /* flush cache and enable MAPEN */
+    /* flush cache and enable MAPEN */
+    set_mtrr_prepare_save (&ctxt);
+    set_mtrr_disable (&ctxt);
 
      /* the CCRs are not contiguous */
     for(i=0; i<4; i++) setCx86(CX86_CCR0 + i, ccr_state[i]);
@@ -1926,7 +1961,9 @@
     int i;
 #endif
 
-    set_mtrr_prepare (&ctxt); /* flush cache and enable MAPEN */
+    /* flush cache and enable MAPEN */
+    set_mtrr_prepare_save (&ctxt);
+    set_mtrr_disable (&ctxt);
 
     /* Save all CCRs locally */
     ccr[0] = getCx86 (CX86_CCR0);
@@ -2075,7 +2112,8 @@
 {
     struct set_mtrr_context ctxt;
 
-    set_mtrr_prepare (&ctxt);
+    set_mtrr_prepare_save (&ctxt);
+    set_mtrr_disable (&ctxt);
 
     if(boot_cpu_data.x86_model==4)
     	centaur_mcr0_init();
@@ -2192,7 +2230,8 @@
     /*  Note that this is not ideal, since the cache is only flushed/disabled
 	for this CPU while the MTRRs are changed, but changing this requires
 	more invasive changes to the way the kernel boots  */
-    set_mtrr_prepare (&ctxt);
+    set_mtrr_prepare_save (&ctxt);
+    set_mtrr_disable (&ctxt);
     mask = set_mtrr_state (&smp_mtrr_state, &ctxt);
     set_mtrr_done (&ctxt);
     /*  Use the atomic bitops to update the global mask  */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/nmi.c linux/arch/i386/kernel/nmi.c
--- linux.orig/arch/i386/kernel/nmi.c	2001-09-21 03:55:24.000000000 +0000
+++ linux/arch/i386/kernel/nmi.c	2002-08-01 06:42:45.000000000 +0000
@@ -8,6 +8,7 @@
  *  Fixes:
  *  Mikael Pettersson	: AMD K7 support for local APIC NMI watchdog.
  *  Mikael Pettersson	: Power Management for local APIC NMI watchdog.
+ *  Mikael Pettersson	: Pentium 4 support for local APIC NMI watchdog.
  */
 
 #include <linux/config.h>
@@ -43,6 +44,32 @@
 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
 #define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
 
+#define MSR_P4_MISC_ENABLE	0x1A0
+#define MSR_P4_MISC_ENABLE_PERF_AVAIL	(1<<7)
+#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL	(1<<12)
+#define MSR_P4_PERFCTR0		0x300
+#define MSR_P4_CCCR0		0x360
+#define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
+#define P4_ESCR_OS		(1<<3)
+#define P4_ESCR_USR		(1<<2)
+#define P4_CCCR_OVF_PMI		(1<<26)
+#define P4_CCCR_THRESHOLD(N)	((N)<<20)
+#define P4_CCCR_COMPLEMENT	(1<<19)
+#define P4_CCCR_COMPARE		(1<<18)
+#define P4_CCCR_REQUIRED	(3<<16)
+#define P4_CCCR_ESCR_SELECT(N)	((N)<<13)
+#define P4_CCCR_ENABLE		(1<<12)
+/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
+   CRU_ESCR0 (with any non-null event selector) through a complemented
+   max threshold. [IA32-Vol3, Section 14.9.9] */
+#define MSR_P4_IQ_COUNTER0	0x30C
+#define MSR_P4_IQ_CCCR0		0x36C
+#define MSR_P4_CRU_ESCR0	0x3B8
+#define P4_NMI_CRU_ESCR0	(P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
+#define P4_NMI_IQ_CCCR0	\
+	(P4_CCCR_OVF_PMI|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|	\
+	 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
+
 int __init check_nmi_watchdog (void)
 {
 	irq_cpustat_t tmp[NR_CPUS];
@@ -84,11 +111,11 @@
 	/*
 	 * If any other x86 CPU has a local APIC, then
 	 * please test the NMI stuff there and send me the
-	 * missing bits. Right now Intel P6 and AMD K7 only.
+	 * missing bits. Right now Intel P6/P4 and AMD K7 only.
 	 */
 	if ((nmi == NMI_LOCAL_APIC) &&
 			(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
-			(boot_cpu_data.x86 == 6))
+			(boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 		nmi_watchdog = nmi;
 	if ((nmi == NMI_LOCAL_APIC) &&
 			(boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
@@ -118,7 +145,15 @@
 		wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 		break;
 	case X86_VENDOR_INTEL:
-		wrmsr(MSR_IA32_EVNTSEL0, 0, 0);
+		switch (boot_cpu_data.x86) {
+		case 6:
+			wrmsr(MSR_P6_EVNTSEL0, 0, 0);
+			break;
+		case 15:
+			wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
+			wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
+			break;
+		}
 		break;
 	}
 }
@@ -157,17 +192,22 @@
  * Original code written by Keith Owens.
  */
 
+static void __pminit clear_msr_range(unsigned int base, unsigned int n)
+{
+	unsigned int i;
+
+	for(i = 0; i < n; ++i)
+		wrmsr(base+i, 0, 0);
+}
+
 static void __pminit setup_k7_watchdog(void)
 {
-	int i;
 	unsigned int evntsel;
 
 	nmi_perfctr_msr = MSR_K7_PERFCTR0;
 
-	for(i = 0; i < 4; ++i) {
-		wrmsr(MSR_K7_EVNTSEL0+i, 0, 0);
-		wrmsr(MSR_K7_PERFCTR0+i, 0, 0);
-	}
+	clear_msr_range(MSR_K7_EVNTSEL0, 4);
+	clear_msr_range(MSR_K7_PERFCTR0, 4);
 
 	evntsel = K7_EVNTSEL_INT
 		| K7_EVNTSEL_OS
@@ -184,27 +224,54 @@
 
 static void __pminit setup_p6_watchdog(void)
 {
-	int i;
 	unsigned int evntsel;
 
-	nmi_perfctr_msr = MSR_IA32_PERFCTR0;
+	nmi_perfctr_msr = MSR_P6_PERFCTR0;
 
-	for(i = 0; i < 2; ++i) {
-		wrmsr(MSR_IA32_EVNTSEL0+i, 0, 0);
-		wrmsr(MSR_IA32_PERFCTR0+i, 0, 0);
-	}
+	clear_msr_range(MSR_P6_EVNTSEL0, 2);
+	clear_msr_range(MSR_P6_PERFCTR0, 2);
 
 	evntsel = P6_EVNTSEL_INT
 		| P6_EVNTSEL_OS
 		| P6_EVNTSEL_USR
 		| P6_NMI_EVENT;
 
-	wrmsr(MSR_IA32_EVNTSEL0, evntsel, 0);
-	Dprintk("setting IA32_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
-	wrmsr(MSR_IA32_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
+	wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
+	Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
+	wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
 	apic_write(APIC_LVTPC, APIC_DM_NMI);
 	evntsel |= P6_EVNTSEL0_ENABLE;
-	wrmsr(MSR_IA32_EVNTSEL0, evntsel, 0);
+	wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
+}
+
+static int __pminit setup_p4_watchdog(void)
+{
+	unsigned int misc_enable, dummy;
+
+	rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
+	if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
+		return 0;
+
+	nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
+
+	if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
+		clear_msr_range(0x3F1, 2);
+	/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
+	   docs doesn't fully define it, so leave it alone for now. */
+	clear_msr_range(0x3A0, 31);
+	clear_msr_range(0x3C0, 6);
+	clear_msr_range(0x3C8, 6);
+	clear_msr_range(0x3E0, 2);
+	clear_msr_range(MSR_P4_CCCR0, 18);
+	clear_msr_range(MSR_P4_PERFCTR0, 18);
+
+	wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
+	wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
+	Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
+	wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
+	apic_write(APIC_LVTPC, APIC_DM_NMI);
+	wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
+	return 1;
 }
 
 void __pminit setup_apic_nmi_watchdog (void)
@@ -216,9 +283,17 @@
 		setup_k7_watchdog();
 		break;
 	case X86_VENDOR_INTEL:
-		if (boot_cpu_data.x86 != 6)
+		switch (boot_cpu_data.x86) {
+		case 6:
+			setup_p6_watchdog();
+			break;
+		case 15:
+			if (!setup_p4_watchdog())
+				return;
+			break;
+		default:
 			return;
-		setup_p6_watchdog();
+		}
 		break;
 	default:
 		return;
@@ -283,7 +358,7 @@
 			 * to get a message out.
 			 */
 			bust_spinlocks(1);
-			printk("NMI Watchdog detected LOCKUP on CPU%d, registers:\n", cpu);
+			printk("NMI Watchdog detected LOCKUP on CPU%d, eip %08lx, registers:\n", cpu, regs->eip);
 			show_registers(regs);
 			printk("console shuts up ...\n");
 			console_silent();
@@ -295,6 +370,18 @@
 		last_irq_sums[cpu] = sum;
 		alert_counter[cpu] = 0;
 	}
-	if (nmi_perfctr_msr)
+	if (nmi_perfctr_msr) {
+		if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
+			/*
+			 * P4 quirks:
+			 * - An overflown perfctr will assert its interrupt
+			 *   until the OVF flag in its CCCR is cleared.
+			 * - LVTPC is masked on interrupt and must be
+			 *   unmasked by the LVTPC handler.
+			 */
+			wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
+			apic_write(APIC_LVTPC, APIC_DM_NMI);
+		}
 		wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
+	}
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/pci-irq.c linux/arch/i386/kernel/pci-irq.c
--- linux.orig/arch/i386/kernel/pci-irq.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/pci-irq.c	2002-08-01 06:42:48.000000000 +0000
@@ -206,6 +206,24 @@
 }
 
 /*
+ * ITE 8330G pirq rules are nibble-based
+ * FIXME: pirqmap may be { 1, 0, 3, 2 },
+ * 	  2+3 are both mapped to irq 9 on my system
+ */
+static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
+{
+	static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
+	return read_config_nybble(router,0x43, pirqmap[pirq-1]);
+}
+
+static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
+{
+	static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
+	write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
+	return 1;
+}
+
+/*
  * OPTI: high four bits are nibble pointer..
  * I wonder what the low bits do?
  */
@@ -443,10 +461,19 @@
 	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, pirq_piix_get, pirq_piix_set },
 	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX,   pirq_piix_get, pirq_piix_set },
 	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_0, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, pirq_piix_get, pirq_piix_set },
 	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, pirq_piix_get, pirq_piix_set },
+	{ "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, pirq_piix_get, pirq_piix_set },
 
 	{ "ALI", PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, pirq_ali_get, pirq_ali_set },
 
+	{ "ITE", PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8330G_0, pirq_ite_get, pirq_ite_set },
+
 	{ "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, pirq_via_get, pirq_via_set },
 	{ "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, pirq_via_get, pirq_via_set },
 	{ "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, pirq_via_get, pirq_via_set },
@@ -462,6 +489,10 @@
 	  pirq_serverworks_get, pirq_serverworks_set },
 	{ "AMD756 VIPER", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B,
 		pirq_amd756_get, pirq_amd756_set },
+	{ "AMD766", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413,
+		pirq_amd756_get, pirq_amd756_set },
+	{ "AMD768", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443,
+		pirq_amd756_get, pirq_amd756_set },
 
 	{ "default", 0, 0, NULL, NULL }
 };
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/pci-pc.c linux/arch/i386/kernel/pci-pc.c
--- linux.orig/arch/i386/kernel/pci-pc.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/pci-pc.c	2002-08-01 06:42:41.000000000 +0000
@@ -14,6 +14,7 @@
 
 #include <asm/segment.h>
 #include <asm/io.h>
+#include <asm/smp.h>
 
 #include "pci-i386.h"
 
@@ -26,6 +27,16 @@
 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
 
+#ifdef CONFIG_MULTIQUAD
+#define BUS2QUAD(global) (mp_bus_id_to_node[global])
+#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
+#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
+#else
+#define BUS2QUAD(global) (0)
+#define BUS2LOCAL(global) (global)
+#define QUADLOCAL2BUS(quad,local) (local)
+#endif
+
 /*
  * This interrupt-safe spinlock protects all accesses to PCI
  * configuration space.
@@ -39,10 +50,71 @@
 
 #ifdef CONFIG_PCI_DIRECT
 
+#ifdef CONFIG_MULTIQUAD
+#define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
+	(0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
+
+static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* CONFIG_MULTIQUAD */
+{
+	unsigned long flags;
+
+	if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
+		return -EINVAL;
+
+	spin_lock_irqsave(&pci_config_lock, flags);
+
+	outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
+
+	switch (len) {
+	case 1:
+		*value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
+		break;
+	case 2:
+		*value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
+		break;
+	case 4:
+		*value = inl_quad(0xCFC, BUS2QUAD(bus));
+		break;
+	}
+
+	spin_unlock_irqrestore(&pci_config_lock, flags);
+
+	return 0;
+}
+
+static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* CONFIG_MULTIQUAD */
+{
+	unsigned long flags;
+
+	if ((bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) 
+		return -EINVAL;
+
+	spin_lock_irqsave(&pci_config_lock, flags);
+
+	outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
+
+	switch (len) {
+	case 1:
+		outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
+		break;
+	case 2:
+		outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
+		break;
+	case 4:
+		outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
+		break;
+	}
+
+	spin_unlock_irqrestore(&pci_config_lock, flags);
+
+	return 0;
+}
+
+#else /* !CONFIG_MULTIQUAD */
 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
 	(0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
 
-static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
+static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* !CONFIG_MULTIQUAD */
 {
 	unsigned long flags;
 
@@ -70,7 +142,7 @@
 	return 0;
 }
 
-static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
+static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* !CONFIG_MULTIQUAD */
 {
 	unsigned long flags;
 
@@ -98,6 +170,8 @@
 	return 0;
 }
 
+#endif /* CONFIG_MULTIQUAD */
+
 #undef PCI_CONF1_ADDRESS
 
 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
@@ -347,7 +421,7 @@
 		    pci_sanity_check(&pci_direct_conf1)) {
 			outl (tmp, 0xCF8);
 			__restore_flags(flags);
-			printk("PCI: Using configuration type 1\n");
+			printk(KERN_INFO "PCI: Using configuration type 1\n");
 			request_region(0xCF8, 8, "PCI conf1");
 			return &pci_direct_conf1;
 		}
@@ -364,7 +438,7 @@
 		if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
 		    pci_sanity_check(&pci_direct_conf2)) {
 			__restore_flags(flags);
-			printk("PCI: Using configuration type 2\n");
+			printk(KERN_INFO "PCI: Using configuration type 2\n");
 			request_region(0xCF8, 4, "PCI conf2");
 			return &pci_direct_conf2;
 		}
@@ -472,10 +546,10 @@
 		case 0:
 			return address + entry;
 		case 0x80:	/* Not present */
-			printk("bios32_service(0x%lx): not present\n", service);
+			printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
 			return 0;
 		default: /* Shouldn't happen */
-			printk("bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
+			printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
 				service, return_code);
 			return 0;
 	}
@@ -525,7 +599,7 @@
 				status, signature);
 			return 0;
 		}
-		printk("PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
+		printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
 			major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
 #ifdef CONFIG_PCI_DIRECT
 		if (!(hw_mech & PCIBIOS_HW_TYPE1))
@@ -827,7 +901,7 @@
 				}
 			}
 			if (ln == &pci_devices) {
-				printk("PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
+				printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
 				/*
 				 * We must not continue scanning as several buggy BIOSes
 				 * return garbage after the last device. Grr.
@@ -836,7 +910,7 @@
 			}
 		}
 		if (!found) {
-			printk("PCI: Device %02x:%02x not found by BIOS\n",
+			printk(KERN_WARNING "PCI: Device %02x:%02x not found by BIOS\n",
 				dev->bus->number, dev->devfn);
 			list_del(&dev->global_list);
 			list_add_tail(&dev->global_list, &sorted_devices);
@@ -896,7 +970,7 @@
 			rt->size = opt.size + sizeof(struct irq_routing_table);
 			rt->exclusive_irqs = map;
 			memcpy(rt->slots, (void *) page, opt.size);
-			printk("PCI: Using BIOS Interrupt Routing Table\n");
+			printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
 		}
 	}
 	free_page(page);
@@ -961,7 +1035,7 @@
 	}
 	if (!seen_host_bridge)
 		return;
-	printk("PCI: Ignoring ghost devices on bus %02x\n", b->number);
+	printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
 
 	ln = &b->devices;
 	while (ln->next != &b->devices) {
@@ -999,7 +1073,7 @@
 			if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
 			    l != 0x0000 && l != 0xffff) {
 				DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
-				printk("PCI: Discovered peer bus %02x\n", n);
+				printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
 				pci_scan_bus(n, pci_root_ops, NULL);
 				break;
 			}
@@ -1017,6 +1091,9 @@
 	 */
 	int pxb, reg;
 	u8 busno, suba, subb;
+#ifdef CONFIG_MULTIQUAD
+	int quad = BUS2QUAD(d->bus->number);
+#endif
 	printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
 	reg = 0xd0;
 	for(pxb=0; pxb<2; pxb++) {
@@ -1025,9 +1102,9 @@
 		pci_read_config_byte(d, reg++, &subb);
 		DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
 		if (busno)
-			pci_scan_bus(busno, pci_root_ops, NULL);	/* Bus A */
+			pci_scan_bus(QUADLOCAL2BUS(quad,busno), pci_root_ops, NULL);	/* Bus A */
 		if (suba < subb)
-			pci_scan_bus(suba+1, pci_root_ops, NULL);	/* Bus B */
+			pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), pci_root_ops, NULL);	/* Bus B */
 	}
 	pcibios_last_bus = -1;
 }
@@ -1040,7 +1117,7 @@
 	 */
 	u8 busno;
 	pci_read_config_byte(d, 0x4a, &busno);
-	printk("PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
+	printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
 	pci_scan_bus(busno, pci_root_ops, NULL);
 	pcibios_last_bus = -1;
 }
@@ -1053,11 +1130,23 @@
 	 */
 	int i;
 
-	printk("PCI: Fixing base address flags for device %s\n", d->slot_name);
+	printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", d->slot_name);
 	for(i=0; i<4; i++)
 		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
 }
 
+static void __devinit  pci_fixup_ncr53c810(struct pci_dev *d)
+{
+	/*
+	 * NCR 53C810 returns class code 0 (at least on some systems).
+	 * Fix class to be PCI_CLASS_STORAGE_SCSI
+	 */
+	if (!d->class) {
+		printk("PCI: fixing NCR 53C810 class code for %s\n", d->slot_name);
+		d->class = PCI_CLASS_STORAGE_SCSI << 8;
+	}
+}
+
 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
 {
 	int i;
@@ -1110,27 +1199,48 @@
 
 /*
  * Addresses issues with problems in the memory write queue timer in
- * certain VIA Northbridges.  This bugfix is per VIA's specifications.
- *
+ * certain VIA Northbridges.  This bugfix is per VIA's specifications,
+ * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
+ * to trigger a bug in its integrated ProSavage video card, which
+ * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
+ * until VIA can provide us with definitive information on why screen
+ * corruption occurs, and what exactly those bits do.
+ * 
  * VIA 8363,8622,8361 Northbridges:
  *  - bits  5, 6, 7 at offset 0x55 need to be turned off
  * VIA 8367 (KT266x) Northbridges:
  *  - bits  5, 6, 7 at offset 0x95 need to be turned off
+ * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
+ *  - bits     6, 7 at offset 0x55 need to be turned off
  */
+
+#define VIA_8363_KL133_REVISION_ID 0x81
+#define VIA_8363_KM133_REVISION_ID 0x84
+
 static void __init pci_fixup_via_northbridge_bug(struct pci_dev *d)
 {
 	u8 v;
+	u8 revision;
 	int where = 0x55;
+	int mask = 0x1f; /* clear bits 5, 6, 7 by default */
 
+	pci_read_config_byte(d, PCI_REVISION_ID, &revision);
+	
 	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
 		where = 0x95; /* the memory write queue timer register is 
-				 different for the kt266x's: 0x95 not 0x55 */
+				 different for the KT266x's: 0x95 not 0x55 */
+	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
+	           (revision == VIA_8363_KL133_REVISION_ID || 
+		    revision == VIA_8363_KM133_REVISION_ID)) {
+		mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
+				causes screen corruption on the KL133/KM133 */
 	}
 
 	pci_read_config_byte(d, where, &v);
-	if (v & 0xe0) {
-		printk("Disabling VIA memory write queue: [%02x] %02x->%02x\n", where, v, v & 0x1f);
-		v &= 0x1f; /* clear bits 5, 6, 7 */
+	if (v & ~mask) {
+		printk("Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
+			d->device, revision, where, v, mask, v & mask);
+		v &= mask;
 		pci_write_config_byte(d, where, v);
 	}
 }
@@ -1148,6 +1258,7 @@
 	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8622,	        pci_fixup_via_northbridge_bug },
 	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,	        pci_fixup_via_northbridge_bug },
 	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8367_0,	pci_fixup_via_northbridge_bug },
+	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_NCR,	PCI_DEVICE_ID_NCR_53C810,	pci_fixup_ncr53c810 },
 	{ 0 }
 };
 
@@ -1199,15 +1310,25 @@
 
 void __init pcibios_init(void)
 {
+	int quad;
+
 	if (!pci_root_ops)
 		pcibios_config_init();
 	if (!pci_root_ops) {
-		printk("PCI: System does not support PCI\n");
+		printk(KERN_WARNING "PCI: System does not support PCI\n");
 		return;
 	}
 
-	printk("PCI: Probing PCI hardware\n");
+	printk(KERN_INFO "PCI: Probing PCI hardware\n");
 	pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
+	if (clustered_apic_mode && (numnodes > 1)) {
+		for (quad = 1; quad < numnodes; ++quad) {
+			printk("Scanning PCI bus %d for quad %d\n", 
+				QUADLOCAL2BUS(quad,0), quad);
+			pci_scan_bus(QUADLOCAL2BUS(quad,0), 
+				pci_root_ops, NULL);
+		}
+	}
 
 	pcibios_irq_init();
 	pcibios_fixup_peer_bridges();
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/process.c linux/arch/i386/kernel/process.c
--- linux.orig/arch/i386/kernel/process.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/process.c	2002-08-01 06:42:27.000000000 +0000
@@ -311,7 +311,7 @@
 	/*
 	 * Use `swapper_pg_dir' as our page directory.
 	 */
-	asm volatile("movl %0,%%cr3": :"r" (__pa(swapper_pg_dir)));
+	load_cr3(swapper_pg_dir);
 
 	/* Write 0x1234 to absolute memory location 0x472.  The BIOS reads
 	   this on booting to tell it to "Bypass memory test (also warm
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/ptrace.c linux/arch/i386/kernel/ptrace.c
--- linux.orig/arch/i386/kernel/ptrace.c	2001-11-21 18:42:41.000000000 +0000
+++ linux/arch/i386/kernel/ptrace.c	2002-08-01 06:42:37.000000000 +0000
@@ -369,12 +369,8 @@
 			break;
 		}
 		ret = 0;
-		if ( !child->used_math ) {
-			/* Simulate an empty FPU. */
-			set_fpu_cwd(child, 0x037f);
-			set_fpu_swd(child, 0x0000);
-			set_fpu_twd(child, 0xffff);
-		}
+		if ( !child->used_math )
+			load_empty_fpu(child);
 		get_fpregs((struct user_i387_struct *)data, child);
 		break;
 	}
@@ -397,13 +393,8 @@
 			ret = -EIO;
 			break;
 		}
-		if ( !child->used_math ) {
-			/* Simulate an empty FPU. */
-			set_fpu_cwd(child, 0x037f);
-			set_fpu_swd(child, 0x0000);
-			set_fpu_twd(child, 0xffff);
-			set_fpu_mxcsr(child, 0x1f80);
-		}
+		if ( !child->used_math )
+			load_empty_fpu(child);
 		ret = get_fpxregs((struct user_fxsr_struct *)data, child);
 		break;
 	}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/semaphore.c linux/arch/i386/kernel/semaphore.c
--- linux.orig/arch/i386/kernel/semaphore.c	2001-11-09 21:58:02.000000000 +0000
+++ linux/arch/i386/kernel/semaphore.c	2002-08-01 06:42:41.000000000 +0000
@@ -182,6 +182,10 @@
 ".align 4\n"
 ".globl __down_failed\n"
 "__down_failed:\n\t"
+#if defined(CONFIG_FRAME_POINTER)
+	"pushl %ebp\n\t"
+	"movl  %esp,%ebp\n\t"
+#endif
 	"pushl %eax\n\t"
 	"pushl %edx\n\t"
 	"pushl %ecx\n\t"
@@ -189,6 +193,10 @@
 	"popl %ecx\n\t"
 	"popl %edx\n\t"
 	"popl %eax\n\t"
+#if defined(CONFIG_FRAME_POINTER)
+	"movl %ebp,%esp\n\t"
+	"popl %ebp\n\t"
+#endif
 	"ret"
 );
 
@@ -197,11 +205,19 @@
 ".align 4\n"
 ".globl __down_failed_interruptible\n"
 "__down_failed_interruptible:\n\t"
+#if defined(CONFIG_FRAME_POINTER)
+	"pushl %ebp\n\t"
+	"movl  %esp,%ebp\n\t"
+#endif
 	"pushl %edx\n\t"
 	"pushl %ecx\n\t"
 	"call __down_interruptible\n\t"
 	"popl %ecx\n\t"
 	"popl %edx\n\t"
+#if defined(CONFIG_FRAME_POINTER)
+	"movl %ebp,%esp\n\t"
+	"popl %ebp\n\t"
+#endif
 	"ret"
 );
 
@@ -210,11 +226,19 @@
 ".align 4\n"
 ".globl __down_failed_trylock\n"
 "__down_failed_trylock:\n\t"
+#if defined(CONFIG_FRAME_POINTER)
+	"pushl %ebp\n\t"
+	"movl  %esp,%ebp\n\t"
+#endif
 	"pushl %edx\n\t"
 	"pushl %ecx\n\t"
 	"call __down_trylock\n\t"
 	"popl %ecx\n\t"
 	"popl %edx\n\t"
+#if defined(CONFIG_FRAME_POINTER)
+	"movl %ebp,%esp\n\t"
+	"popl %ebp\n\t"
+#endif
 	"ret"
 );
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/setup.c linux/arch/i386/kernel/setup.c
--- linux.orig/arch/i386/kernel/setup.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/setup.c	2002-08-01 06:42:43.000000000 +0000
@@ -71,6 +71,13 @@
  *  CacheSize bug workaround updates for AMD, Intel & VIA Cyrix.
  *  Dave Jones <davej@suse.de>, September, October 2001.
  *
+ *  Short-term fix for a conflicting cache attribute bug in the kernel
+ *  that is exposed by advanced speculative caching on new AMD Athlon
+ *  processors.
+ *  Richard Brunner <richard.brunner@amd.com> and Mark Langsdorf
+ *  <mark.langsdorf@amd.com>, June 2002 
+ *  Adapted to work with uniprocessor APIC by Bryan O'Sullivan
+ *  <bos@serpentine.com>, June 2002.
  */
 
 /*
@@ -98,6 +105,8 @@
 #endif
 #include <linux/highmem.h>
 #include <linux/bootmem.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
 #include <linux/seq_file.h>
 #include <asm/processor.h>
 #include <linux/console.h>
@@ -139,6 +148,9 @@
 /* For PCI or other memory-mapped resources */
 unsigned long pci_mem_start = 0x10000000;
 
+/* user-defined highmem size */
+static unsigned int highmem_pages __initdata = -1;
+
 /*
  * Setup options
  */
@@ -155,14 +167,22 @@
 unsigned char aux_device_present;
 
 extern void mcheck_init(struct cpuinfo_x86 *c);
+extern void dmi_scan_machine(void);
 extern int root_mountflags;
 extern char _text, _etext, _edata, _end;
 
 static int disable_x86_serial_nr __initdata = 1;
 static int disable_x86_fxsr __initdata = 0;
+static int disable_x86_ht __initdata = 0;
 
 int enable_acpi_smp_table;
 
+#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
+int disable_adv_spec_cache __initdata = 1;
+#else
+int disable_adv_spec_cache __initdata = 0;
+#endif /* CONFIG_AGP */
+
 /*
  * This is set up by the setup-routine at boot-time
  */
@@ -408,6 +428,22 @@
 	}
 }
 
+static void __init limit_regions (unsigned long long size)
+{
+	unsigned long long current_addr = 0;
+	int i;
+
+	for (i = 0; i < e820.nr_map; i++) {
+		if (e820.map[i].type == E820_RAM) {
+			current_addr = e820.map[i].addr + e820.map[i].size;
+			if (current_addr >= size) {
+				e820.map[i].size -= current_addr-size;
+				e820.nr_map = i + 1;
+				return;
+			}
+		}
+	}
+}
 static void __init add_memory_region(unsigned long long start,
                                   unsigned long long size, int type)
 {
@@ -705,17 +741,54 @@
 } /* setup_memory_region */
 
 
-static void __init parse_mem_cmdline (char ** cmdline_p)
+int __init amd_adv_spec_cache_feature(void)
+{
+	char vendor_id[16];
+	int ident;
+	int family, model;
+ 
+	/* Must have CPUID */
+	if(!have_cpuid_p())
+		goto donthave;
+	if(cpuid_eax(0)<1)
+		goto donthave;
+	
+	/* Must be x86 architecture */
+	cpuid(0, &ident,  
+		(int *)&vendor_id[0],
+		(int *)&vendor_id[8],
+		(int *)&vendor_id[4]);
+
+	if (memcmp(vendor_id, "AuthenticAMD", 12)) 
+	       goto donthave;
+
+	ident = cpuid_eax(1);
+	family = (ident >> 8) & 0xf;
+	model  = (ident >> 4) & 0xf;
+	if (((family == 6)  && (model >= 6)) || (family == 15)) {
+		printk(KERN_INFO "Advanced speculative caching feature present\n");
+		return 1;
+	}
+
+donthave:
+	printk(KERN_INFO "Advanced speculative caching feature not present\n");
+	return 0;
+}
+
+
+static void __init parse_cmdline_early (char ** cmdline_p)
 {
 	char c = ' ', *to = command_line, *from = COMMAND_LINE;
 	int len = 0;
-	int usermem = 0;
+	int userdef = 0;
 
 	/* Save unparsed command line copy for /proc/cmdline */
 	memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
 	saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
 
 	for (;;) {
+		if (c != ' ')
+			goto nextchar;
 		/*
 		 * "mem=nopentium" disables the 4MB page tables.
 		 * "mem=XXX[kKmM]" defines a memory region from HIGH_MEM
@@ -723,7 +796,7 @@
 		 * "mem=XXX[KkmM]@XXX[KkmM]" defines a memory region from
 		 * <start> to <start>+<mem>, overriding the bios size.
 		 */
-		if (c == ' ' && !memcmp(from, "mem=", 4)) {
+		if (!memcmp(from, "mem=", 4)) {
 			if (to != command_line)
 				to--;
 			if (!memcmp(from+4, "nopentium", 9)) {
@@ -732,38 +805,54 @@
 			} else if (!memcmp(from+4, "exactmap", 8)) {
 				from += 8+4;
 				e820.nr_map = 0;
-				usermem = 1;
+				userdef = 1;
 			} else {
 				/* If the user specifies memory size, we
-				 * blow away any automatically generated
-				 * size
+				 * limit the BIOS-provided memory map to
+				 * that size. exactmap can be used to specify
+				 * the exact map. mem=number can be used to
+				 * trim the existing memory map.
 				 */
 				unsigned long long start_at, mem_size;
  
-				if (usermem == 0) {
-					/* first time in: zap the whitelist
-					 * and reinitialize it with the
-					 * standard low-memory region.
-					 */
-					e820.nr_map = 0;
-					usermem = 1;
-					add_memory_region(0, LOWMEMSIZE(), E820_RAM);
-				}
 				mem_size = memparse(from+4, &from);
-				if (*from == '@')
+				if (*from == '@') {
 					start_at = memparse(from+1, &from);
-				else {
-					start_at = HIGH_MEMORY;
-					mem_size -= HIGH_MEMORY;
-					usermem=0;
+					add_memory_region(start_at, mem_size, E820_RAM);
+				} else {
+					limit_regions(mem_size);
+					userdef=1;
 				}
-				add_memory_region(start_at, mem_size, E820_RAM);
 			}
 		}
-		/* acpismp=force forces parsing and use of the ACPI SMP table */
-		if (c == ' ' && !memcmp(from, "acpismp=force", 13)) 	
-			 enable_acpi_smp_table = 1;
-	
+
+		/* "noht" disables HyperThreading (2 logical cpus per Xeon) */
+		else if (!memcmp(from, "noht", 4))
+			disable_x86_ht = 1;
+
+		/* "acpismp=force" forces parsing and use of the ACPI SMP table */
+		else if (!memcmp(from, "acpismp=force", 13))
+			enable_acpi_smp_table = 1;
+
+		/*
+		 * highmem=size forces highmem to be exactly 'size' bytes.
+		 * This works even on boxes that have no highmem otherwise.
+		 * This also works to reduce highmem size on bigger boxes.
+		 */
+		else if (!memcmp(from, "highmem=", 8))
+			highmem_pages = memparse(from+8, &from) >> PAGE_SHIFT;
+		/*
+		 * unsafe-gart-alias overrides the short-term fix for a
+		 * conflicting cache attribute bug in the kernel that is
+		 * exposed by advanced speculative caching in newer AMD
+		 * Athlon processors.  Overriding the fix will allow
+		 * higher performance but the kernel bug can cause system
+		 * lock-ups if the system uses an AGP card.  unsafe-gart-alias
+		 * can be turned on for higher performance in servers.
+		 */
+		else if (!memcmp(from, "unsafe-gart-alias", 17))
+			disable_adv_spec_cache = 0;
+nextchar:
 		c = *(from++);
 		if (!c)
 			break;
@@ -773,7 +862,7 @@
 	}
 	*to = '\0';
 	*cmdline_p = command_line;
-	if (usermem) {
+	if (userdef) {
 		printk(KERN_INFO "user-defined physical RAM map:\n");
 		print_memory_map("user");
 	}
@@ -820,7 +909,7 @@
 	data_resource.start = virt_to_bus(&_etext);
 	data_resource.end = virt_to_bus(&_edata)-1;
 
-	parse_mem_cmdline(cmdline_p);
+	parse_cmdline_early(cmdline_p);
 
 #define PFN_UP(x)	(((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
 #define PFN_DOWN(x)	((x) >> PAGE_SHIFT)
@@ -860,6 +949,14 @@
 	 */
 	max_low_pfn = max_pfn;
 	if (max_low_pfn > MAXMEM_PFN) {
+		if (highmem_pages == -1)
+			highmem_pages = max_pfn - MAXMEM_PFN;
+		if (highmem_pages + MAXMEM_PFN < max_pfn)
+			max_pfn = MAXMEM_PFN + highmem_pages;
+		if (highmem_pages + MAXMEM_PFN > max_pfn) {
+			printk("only %luMB highmem pages available, ignoring highmem size of %uMB.\n", pages_to_mb(max_pfn - MAXMEM_PFN), pages_to_mb(highmem_pages));
+			highmem_pages = 0;
+		}
 		max_low_pfn = MAXMEM_PFN;
 #ifndef CONFIG_HIGHMEM
 		/* Maximum memory usable is what is directly addressable */
@@ -878,16 +975,37 @@
 		}
 #endif /* !CONFIG_X86_PAE */
 #endif /* !CONFIG_HIGHMEM */
+	} else {
+		if (highmem_pages == -1)
+			highmem_pages = 0;
+#if CONFIG_HIGHMEM
+		if (highmem_pages >= max_pfn) {
+			printk(KERN_ERR "highmem size specified (%uMB) is bigger than pages available (%luMB)!.\n", pages_to_mb(highmem_pages), pages_to_mb(max_pfn));
+			highmem_pages = 0;
+		}
+		if (highmem_pages) {
+			if (max_low_pfn-highmem_pages < 64*1024*1024/PAGE_SIZE){
+				printk(KERN_ERR "highmem size %uMB results in smaller than 64MB lowmem, ignoring it.\n", pages_to_mb(highmem_pages));
+				highmem_pages = 0;
+			}
+			max_low_pfn -= highmem_pages;
+		}
+#else
+		if (highmem_pages)
+			printk(KERN_ERR "ignoring highmem size on non-highmem kernel!\n");
+#endif
 	}
 
 #ifdef CONFIG_HIGHMEM
 	highstart_pfn = highend_pfn = max_pfn;
-	if (max_pfn > MAXMEM_PFN) {
-		highstart_pfn = MAXMEM_PFN;
-		printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
-			pages_to_mb(highend_pfn - highstart_pfn));
+	if (max_pfn > max_low_pfn) {
+		highstart_pfn = max_low_pfn;
 	}
+	printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
+		pages_to_mb(highend_pfn - highstart_pfn));
 #endif
+	printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
+			pages_to_mb(max_low_pfn));
 	/*
 	 * Initialize the boot-time allocator (with low memory only):
 	 */
@@ -976,6 +1094,21 @@
 #endif
 
 	/*
+	 * If enable_acpi_smp_table and HT feature present, acpitable.c
+	 * will find all logical cpus despite disable_x86_ht: so if both
+	 * "noht" and "acpismp=force" are specified, let "noht" override
+	 * "acpismp=force" cleanly.  Why retain "acpismp=force"? because
+	 * parsing ACPI SMP table might prove useful on some non-HT cpu.
+	 */
+	if (disable_x86_ht) {
+		clear_bit(X86_FEATURE_HT, &boot_cpu_data.x86_capability[0]);
+		enable_acpi_smp_table = 0;
+	}
+	if (test_bit(X86_FEATURE_HT, &boot_cpu_data.x86_capability[0]))
+		enable_acpi_smp_table = 1;
+	
+
+	/*
 	 * NOTE: before this point _nobody_ is allowed to allocate
 	 * any memory using the bootmem allocator.
 	 */
@@ -983,6 +1116,14 @@
 #ifdef CONFIG_SMP
 	smp_alloc_memory(); /* AP processor realmode stacks in low memory*/
 #endif
+	/*
+	 * short-term fix for a conflicting cache attribute bug in the 
+	 * kernel that is exposed by advanced speculative caching on
+	 * newer AMD Athlon processors.
+	 */
+	if (disable_adv_spec_cache && amd_adv_spec_cache_feature())
+		clear_bit(X86_FEATURE_PSE, &boot_cpu_data.x86_capability);
+
 	paging_init();
 #ifdef CONFIG_X86_LOCAL_APIC
 	/*
@@ -990,7 +1131,6 @@
 	 */
 	if (smp_found_config)
 		get_smp_config();
-	init_apic_mappings();
 #endif
 
 
@@ -1042,6 +1182,7 @@
 	conswitchp = &dummy_con;
 #endif
 #endif
+	dmi_scan_machine();
 }
 
 static int cachesize_override __initdata = -1;
@@ -1151,6 +1292,31 @@
 	       l2size, ecx & 0xFF);
 }
 
+
+/*=======================================================================
+ * amd_adv_spec_cache_disable
+ * Setting a special MSR big that disables a small part of advanced
+ * speculative caching as part of a short-term fix for a conflicting cache
+ * attribute bug in the kernel that is exposed by advanced speculative
+ * caching in newer AMD Athlon processors.
+ =======================================================================*/
+static void amd_adv_spec_cache_disable(void)
+{
+	printk(KERN_INFO "Disabling advanced speculative caching\n");
+
+	__asm__ __volatile__ (
+		" movl	 $0x9c5a203a,%%edi   \n" /* msr enable */
+		" movl	 $0xc0011022,%%ecx   \n" /* msr addr	 */
+		" rdmsr			     \n" /* get reg val	 */
+		" orl	 $0x00010000,%%eax   \n" /* set bit 16	 */
+		" wrmsr			     \n" /* put it back	 */
+		" xorl	%%edi, %%edi	     \n" /* clear msr enable */
+		: /* no outputs */
+		: /* no inputs, either */
+		: "%eax","%ecx","%edx","%edi" /* clobbered regs */ );
+}
+
+
 /*
  *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  *	misexecution of code under Linux. Owners of such processors should
@@ -1284,10 +1450,21 @@
  			 * to enable SSE on Palomino/Morgan CPU's.
 			 * If the BIOS didn't enable it already, enable it
 			 * here.
+			 *
+			 * Avoiding the use of 4MB/2MB pages along with
+			 * setting a special MSR bit that disables a small
+			 * part of advanced speculative caching as part of a
+			 * short-term fix for a conflicting cache attribute
+			 * bug in the kernel that is exposed by advanced
+			 * speculative caching in newer AMD Atlon processors.
+			 *
+			 * If we cleared the PSE bit earlier as part
+			 * of the workaround for this problem, we need
+			 * to clear it again, as our caller may have
+			 * clobbered it if uniprocessor APIC is enabled.
 			 */
-			if (c->x86_model == 6 || c->x86_model == 7) {
-				if (!test_bit(X86_FEATURE_XMM,
-					      &c->x86_capability)) {
+			if (c->x86_model >= 6) {
+				if (!cpu_has_xmm) {
 					printk(KERN_INFO
 					       "Enabling Disabled K7/SSE Support...\n");
 					rdmsr(MSR_K7_HWCR, l, h);
@@ -1296,6 +1473,18 @@
 					set_bit(X86_FEATURE_XMM,
                                                 &c->x86_capability);
 				}
+				if (disable_adv_spec_cache &&
+				    amd_adv_spec_cache_feature()) {
+					clear_bit(X86_FEATURE_PSE,
+						  &c->x86_capability);
+					amd_adv_spec_cache_disable();
+				}
+			}
+			break;
+		case 15: 
+			if (disable_adv_spec_cache && amd_adv_spec_cache_feature()) {
+				clear_bit(X86_FEATURE_PSE, &c->x86_capability);
+				amd_adv_spec_cache_disable();
 			}
 			break;
 
@@ -1306,7 +1495,7 @@
 }
 
 /*
- * Read Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
+ * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
  */
 static void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
 {
@@ -1468,11 +1657,6 @@
 		break;
 
 	case 4: /* MediaGX/GXm */
-		/*
-		 *	Life sometimes gets weiiiiiiiird if we use this
-		 *	on the MediaGX. So we turn it off for now. 
-		 */
-		
 #ifdef CONFIG_PCI
 		/* It isnt really a PCI quirk directly, but the cure is the
 		   same. The MediaGX has deep magic SMM stuff that handles the
@@ -1494,14 +1678,22 @@
 		/* GXm supports extended cpuid levels 'ala' AMD */
 		if (c->cpuid_level == 2) {
 			get_model_name(c);  /* get CPU marketing name */
-			clear_bit(X86_FEATURE_TSC, c->x86_capability);
+			/*
+	 		 *	The 5510/5520 companion chips have a funky PIT
+			 *	that breaks the TSC synchronizing, so turn it off
+			 */
+			if(pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, NULL) ||
+			   pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, NULL))
+				clear_bit(X86_FEATURE_TSC, c->x86_capability);
 			return;
 		}
 		else {  /* MediaGX */
 			Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
 			p = Cx86_cb+2;
 			c->x86_model = (dir1 & 0x20) ? 1 : 2;
-			clear_bit(X86_FEATURE_TSC, &c->x86_capability);
+			if(pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, NULL) ||
+			   pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, NULL))
+				clear_bit(X86_FEATURE_TSC, &c->x86_capability);
 		}
 		break;
 
@@ -2210,7 +2402,7 @@
 		strcpy(c->x86_model_id, p);
 	
 #ifdef CONFIG_SMP
-	if (test_bit(X86_FEATURE_HT, &c->x86_capability)) {
+	if (test_bit(X86_FEATURE_HT, &c->x86_capability) && !disable_x86_ht) {
 		extern	int phys_proc_id[NR_CPUS];
 		
 		u32 	eax, ebx, ecx, edx;
@@ -2270,6 +2462,8 @@
 		c->x86_vendor = X86_VENDOR_AMD;
 	else if (!strcmp(v, "CyrixInstead"))
 		c->x86_vendor = X86_VENDOR_CYRIX;
+	else if (!strcmp(v, "Geode by NSC"))
+		c->x86_vendor = X86_VENDOR_NSC;
 	else if (!strcmp(v, "UMC UMC UMC "))
 		c->x86_vendor = X86_VENDOR_UMC;
 	else if (!strcmp(v, "CentaurHauls"))
@@ -2555,6 +2749,12 @@
 			      &c->x86_capability[0]);
 			c->x86 = (tfms >> 8) & 15;
 			c->x86_model = (tfms >> 4) & 15;
+			if ( (c->x86_vendor == X86_VENDOR_AMD) &&
+				(c->x86 == 0xf)) {
+				/* AMD Extended Family and Model Values */
+				c->x86 += (tfms >> 20) & 0xff;
+				c->x86_model += (tfms >> 12) & 0xf0;
+			}
 			c->x86_mask = tfms & 15;
 		} else {
 			/* Have CPUID level 0 only - unheard of */
@@ -2613,6 +2813,10 @@
 		init_cyrix(c);
 		break;
 
+	case X86_VENDOR_NSC:
+	        init_cyrix(c);
+		break;
+
 	case X86_VENDOR_AMD:
 		init_amd(c);
 		break;
@@ -2655,6 +2859,10 @@
 		clear_bit(X86_FEATURE_TSC, &c->x86_capability);
 #endif
 
+	/* HT disabled? */
+	if (disable_x86_ht)
+		clear_bit(X86_FEATURE_HT, &c->x86_capability);
+
 	/* FXSR disabled? */
 	if (disable_x86_fxsr) {
 		clear_bit(X86_FEATURE_FXSR, &c->x86_capability);
@@ -2713,14 +2921,17 @@
 {
 	get_cpu_vendor(&boot_cpu_data);
 
-	if ( boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX )
+	if ( boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX ||
+	     boot_cpu_data.x86_vendor == X86_VENDOR_NSC )
 		init_cyrix(&boot_cpu_data);
 }
 
 
 /* These need to match <asm/processor.h> */
 static char *cpu_vendor_names[] __initdata = {
-	"Intel", "Cyrix", "AMD", "UMC", "NexGen", "Centaur", "Rise", "Transmeta" };
+	"Intel", "Cyrix", "AMD", "UMC", "NexGen", 
+	"Centaur", "Rise", "Transmeta", "NSC"
+};
 
 
 void __init print_cpu_info(struct cpuinfo_x86 *c)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/signal.c linux/arch/i386/kernel/signal.c
--- linux.orig/arch/i386/kernel/signal.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/signal.c	2002-08-01 06:42:43.000000000 +0000
@@ -658,7 +658,7 @@
 				continue;
 
 			switch (signr) {
-			case SIGCONT: case SIGCHLD: case SIGWINCH:
+			case SIGCONT: case SIGCHLD: case SIGWINCH: case SIGURG:
 				continue;
 
 			case SIGTSTP: case SIGTTIN: case SIGTTOU:
@@ -685,10 +685,7 @@
 				/* FALLTHRU */
 
 			default:
-				sigaddset(&current->pending.signal, signr);
-				recalc_sigpending(current);
-				current->flags |= PF_SIGNALED;
-				do_exit(exit_code);
+				sig_exit(signr, exit_code, &info);
 				/* NOTREACHED */
 			}
 		}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/smp.c linux/arch/i386/kernel/smp.c
--- linux.orig/arch/i386/kernel/smp.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/i386/kernel/smp.c	2002-08-01 06:42:31.000000000 +0000
@@ -103,9 +103,9 @@
  */
 
 /* The 'big kernel lock' */
-spinlock_t kernel_flag __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
+spinlock_cacheline_t kernel_flag_cacheline = {SPIN_LOCK_UNLOCKED};
 
-struct tlb_state cpu_tlbstate[NR_CPUS] = {[0 ... NR_CPUS-1] = { &init_mm, 0 }};
+struct tlb_state cpu_tlbstate[NR_CPUS] __cacheline_aligned = {[0 ... NR_CPUS-1] = { &init_mm, 0, }};
 
 /*
  * the following functions deal with sending IPIs between CPUs.
@@ -298,12 +298,15 @@
 /*
  * We cannot call mmdrop() because we are in interrupt context, 
  * instead update mm->cpu_vm_mask.
+ *
+ * We need to reload %cr3 since the page tables may be going
+ * away frm under us...
  */
 static void inline leave_mm (unsigned long cpu)
 {
-	if (cpu_tlbstate[cpu].state == TLBSTATE_OK)
-		BUG();
+	BUG_ON(cpu_tlbstate[cpu].state == TLBSTATE_OK);
 	clear_bit(cpu, &cpu_tlbstate[cpu].active_mm->cpu_vm_mask);
+	load_cr3(swapper_pg_dir);
 }
 
 /*
@@ -529,7 +532,7 @@
  * remote CPUs are nearly ready to execute <<func>> or are or have executed.
  *
  * You must not call this function with disabled interrupts or from a
- * hardware interrupt handler, you may call it from a bottom half handler.
+ * hardware interrupt handler or from a bottom half handler.
  */
 {
 	struct call_data_struct data;
@@ -545,7 +548,7 @@
 	if (wait)
 		atomic_set(&data.finished, 0);
 
-	spin_lock_bh(&call_lock);
+	spin_lock(&call_lock);
 	call_data = &data;
 	wmb();
 	/* Send a message to all other CPUs and wait for them to respond */
@@ -558,7 +561,7 @@
 	if (wait)
 		while (atomic_read(&data.finished) != cpus)
 			barrier();
-	spin_unlock_bh(&call_lock);
+	spin_unlock(&call_lock);
 
 	return 0;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/smpboot.c linux/arch/i386/kernel/smpboot.c
--- linux.orig/arch/i386/kernel/smpboot.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/i386/kernel/smpboot.c	2002-08-01 06:42:43.000000000 +0000
@@ -213,7 +213,7 @@
  *		    ^---- (this multiplication can overflow)
  */
 
-static unsigned long long div64 (unsigned long long a, unsigned long b0)
+static unsigned long long __init div64 (unsigned long long a, unsigned long b0)
 {
 	unsigned int a1, a2;
 	unsigned long long res;
@@ -973,7 +973,7 @@
 
 static int boot_cpu_logical_apicid;
 /* Where the IO area was mapped on multiquad, always 0 otherwise */
-void *xquad_portio = NULL;
+void *xquad_portio;
 
 int cpu_sibling_map[NR_CPUS] __cacheline_aligned;
 
@@ -981,11 +981,14 @@
 {
 	int apicid, cpu, bit;
 
-        if (clustered_apic_mode) {
-                /* remap the 1st quad's 256k range for cross-quad I/O */
-                xquad_portio = ioremap (XQUAD_PORTIO_BASE, XQUAD_PORTIO_LEN);
-                printk("Cross quad port I/O vaddr 0x%08lx, len %08lx\n",
-                        (u_long) xquad_portio, (u_long) XQUAD_PORTIO_LEN);
+        if (clustered_apic_mode && (numnodes > 1)) {
+                printk("Remapping cross-quad port I/O for %d quads\n",
+			numnodes);
+                printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
+                        (u_long) xquad_portio, 
+			(u_long) numnodes * XQUAD_PORTIO_LEN);
+                xquad_portio = ioremap (XQUAD_PORTIO_BASE, 
+			numnodes * XQUAD_PORTIO_LEN);
         }
 
 #ifdef CONFIG_MTRR
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/traps.c linux/arch/i386/kernel/traps.c
--- linux.orig/arch/i386/kernel/traps.c	2001-09-30 19:26:08.000000000 +0000
+++ linux/arch/i386/kernel/traps.c	2002-08-01 06:42:34.000000000 +0000
@@ -139,14 +139,14 @@
 	if (!stack)
 		stack = (unsigned long*)&stack;
 
-	printk("Call Trace: ");
+	printk("Call Trace:   ");
 	i = 1;
 	while (((long) stack & (THREAD_SIZE-1)) != 0) {
 		addr = *stack++;
 		if (kernel_text_address(addr)) {
 			if (i && ((i % 6) == 0))
-				printk("\n   ");
-			printk("[<%08lx>] ", addr);
+				printk("\n ");
+			printk(" [<%08lx>]", addr);
 			i++;
 		}
 	}
@@ -237,6 +237,41 @@
 	printk("\n");
 }	
 
+static void handle_BUG(struct pt_regs *regs)
+{
+	unsigned short ud2;
+	unsigned short line;
+	char *file;
+	char c;
+	unsigned long eip;
+
+	if (regs->xcs & 3)
+		goto no_bug;		/* Not in kernel */
+
+	eip = regs->eip;
+
+	if (eip < PAGE_OFFSET)
+		goto no_bug;
+	if (__get_user(ud2, (unsigned short *)eip))
+		goto no_bug;
+	if (ud2 != 0x0b0f)
+		goto no_bug;
+	if (__get_user(line, (unsigned short *)(eip + 2)))
+		goto bug;
+	if (__get_user(file, (char **)(eip + 4)) ||
+		(unsigned long)file < PAGE_OFFSET || __get_user(c, file))
+		file = "<bad filename>";
+
+	printk("kernel BUG at %s:%d!\n", file, line);
+
+no_bug:
+	return;
+
+	/* Here we know it was a BUG but file-n-line is unavailable */
+bug:
+	printk("Kernel BUG\n");
+}
+
 spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
 
 void die(const char * str, struct pt_regs * regs, long err)
@@ -244,6 +279,7 @@
 	console_verbose();
 	spin_lock_irq(&die_lock);
 	bust_spinlocks(1);
+	handle_BUG(regs);
 	printk("%s: %04lx\n", str, err & 0xffff);
 	show_registers(regs);
 	bust_spinlocks(0);
@@ -505,6 +541,8 @@
 		 * allowing programs to debug themselves without the ptrace()
 		 * interface.
 		 */
+		if ((regs->xcs & 3) == 0)
+			goto clear_TF;
 		if ((tsk->ptrace & (PT_DTRACE|PT_PTRACED)) == PT_DTRACE)
 			goto clear_TF;
 	}
@@ -580,9 +618,10 @@
 		default:
 			break;
 		case 0x001: /* Invalid Op */
-		case 0x040: /* Stack Fault */
-		case 0x240: /* Stack Fault | Direction */
+		case 0x041: /* Stack Fault */
+		case 0x241: /* Stack Fault | Direction */
 			info.si_code = FPE_FLTINV;
+			/* Should we clear the SF or let user space do it ???? */
 			break;
 		case 0x002: /* Denormalize */
 		case 0x010: /* Underflow */
@@ -920,6 +959,10 @@
 		EISA_bus = 1;
 #endif
 
+#ifdef CONFIG_X86_LOCAL_APIC
+	init_apic_mappings();
+#endif
+
 	set_trap_gate(0,&divide_error);
 	set_trap_gate(1,&debug);
 	set_intr_gate(2,&nmi);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/kernel/vm86.c linux/arch/i386/kernel/vm86.c
--- linux.orig/arch/i386/kernel/vm86.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/kernel/vm86.c	2002-08-01 06:42:32.000000000 +0000
@@ -2,7 +2,34 @@
  *  linux/kernel/vm86.c
  *
  *  Copyright (C) 1994  Linus Torvalds
+ *
+ *  29 dec 2001 - Fixed oopses caused by unchecked access to the vm86
+ *                stack - Manfred Spraul <manfreds@colorfullife.com>
+ *
+ *  22 mar 2002 - Manfred detected the stackfaults, but didn't handle
+ *                them correctly. Now the emulation will be in a
+ *                consistent state after stackfaults - Kasper Dupont
+ *                <kasperd@daimi.au.dk>
+ *
+ *  22 mar 2002 - Added missing clear_IF in set_vflags_* Kasper Dupont
+ *                <kasperd@daimi.au.dk>
+ *
+ *  ?? ??? 2002 - Fixed premature returns from handle_vm86_fault
+ *                caused by Kasper Dupont's changes - Stas Sergeev
+ *
+ *   4 apr 2002 - Fixed CHECK_IF_IN_TRAP broken by Stas' changes.
+ *                Kasper Dupont <kasperd@daimi.au.dk>
+ *
+ *   9 apr 2002 - Changed syntax of macros in handle_vm86_fault.
+ *                Kasper Dupont <kasperd@daimi.au.dk>
+ *
+ *   9 apr 2002 - Changed stack access macros to jump to a label
+ *                instead of returning to userspace. This simplifies
+ *                do_int, and is needed by handle_vm6_fault. Kasper
+ *                Dupont <kasperd@daimi.au.dk>
+ *   
  */
+
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
@@ -97,21 +124,22 @@
 	pte_t *pte;
 	int i;
 
+	spin_lock(&tsk->mm->page_table_lock);
 	pgd = pgd_offset(tsk->mm, 0xA0000);
 	if (pgd_none(*pgd))
-		return;
+		goto out;
 	if (pgd_bad(*pgd)) {
 		pgd_ERROR(*pgd);
 		pgd_clear(pgd);
-		return;
+		goto out;
 	}
 	pmd = pmd_offset(pgd, 0xA0000);
 	if (pmd_none(*pmd))
-		return;
+		goto out;
 	if (pmd_bad(*pmd)) {
 		pmd_ERROR(*pmd);
 		pmd_clear(pmd);
-		return;
+		goto out;
 	}
 	pte = pte_offset(pmd, 0xA0000);
 	for (i = 0; i < 32; i++) {
@@ -119,6 +147,8 @@
 			set_pte(pte, pte_wrprotect(*pte));
 		pte++;
 	}
+out:
+	spin_unlock(&tsk->mm->page_table_lock);
 	flush_tlb();
 }
 
@@ -290,12 +320,30 @@
 	regs->eflags &= ~TF_MASK;
 }
 
+static inline void clear_AC(struct kernel_vm86_regs * regs)
+{
+	regs->eflags &= ~AC_MASK;
+}
+
+/* It is correct to call set_IF(regs) from the set_vflags_*
+ * functions. However someone forgot to call clear_IF(regs)
+ * in the opposite case.
+ * After the command sequence CLI PUSHF STI POPF you should
+ * end up with interrups disabled, but you ended up with
+ * interrupts enabled.
+ *  ( I was testing my own changes, but the only bug I
+ *    could find was in a function I had not changed. )
+ * [KD]
+ */
+
 static inline void set_vflags_long(unsigned long eflags, struct kernel_vm86_regs * regs)
 {
 	set_flags(VEFLAGS, eflags, current->thread.v86mask);
 	set_flags(regs->eflags, eflags, SAFE_MASK);
 	if (eflags & IF_MASK)
 		set_IF(regs);
+	else
+		clear_IF(regs);
 }
 
 static inline void set_vflags_short(unsigned short flags, struct kernel_vm86_regs * regs)
@@ -304,6 +352,8 @@
 	set_flags(regs->eflags, flags, SAFE_MASK);
 	if (flags & IF_MASK)
 		set_IF(regs);
+	else
+		clear_IF(regs);
 }
 
 static inline unsigned long get_vflags(struct kernel_vm86_regs * regs)
@@ -323,80 +373,90 @@
 	return nr;
 }
 
-/*
- * Boy are these ugly, but we need to do the correct 16-bit arithmetic.
- * Gcc makes a mess of it, so we do it inline and use non-obvious calling
- * conventions..
- */
-#define pushb(base, ptr, val) \
-__asm__ __volatile__( \
-	"decw %w0\n\t" \
-	"movb %2,0(%1,%0)" \
-	: "=r" (ptr) \
-	: "r" (base), "q" (val), "0" (ptr))
-
-#define pushw(base, ptr, val) \
-__asm__ __volatile__( \
-	"decw %w0\n\t" \
-	"movb %h2,0(%1,%0)\n\t" \
-	"decw %w0\n\t" \
-	"movb %b2,0(%1,%0)" \
-	: "=r" (ptr) \
-	: "r" (base), "q" (val), "0" (ptr))
-
-#define pushl(base, ptr, val) \
-__asm__ __volatile__( \
-	"decw %w0\n\t" \
-	"rorl $16,%2\n\t" \
-	"movb %h2,0(%1,%0)\n\t" \
-	"decw %w0\n\t" \
-	"movb %b2,0(%1,%0)\n\t" \
-	"decw %w0\n\t" \
-	"rorl $16,%2\n\t" \
-	"movb %h2,0(%1,%0)\n\t" \
-	"decw %w0\n\t" \
-	"movb %b2,0(%1,%0)" \
-	: "=r" (ptr) \
-	: "r" (base), "q" (val), "0" (ptr))
-
-#define popb(base, ptr) \
-({ unsigned long __res; \
-__asm__ __volatile__( \
-	"movb 0(%1,%0),%b2\n\t" \
-	"incw %w0" \
-	: "=r" (ptr), "=r" (base), "=q" (__res) \
-	: "0" (ptr), "1" (base), "2" (0)); \
-__res; })
-
-#define popw(base, ptr) \
-({ unsigned long __res; \
-__asm__ __volatile__( \
-	"movb 0(%1,%0),%b2\n\t" \
-	"incw %w0\n\t" \
-	"movb 0(%1,%0),%h2\n\t" \
-	"incw %w0" \
-	: "=r" (ptr), "=r" (base), "=q" (__res) \
-	: "0" (ptr), "1" (base), "2" (0)); \
-__res; })
-
-#define popl(base, ptr) \
-({ unsigned long __res; \
-__asm__ __volatile__( \
-	"movb 0(%1,%0),%b2\n\t" \
-	"incw %w0\n\t" \
-	"movb 0(%1,%0),%h2\n\t" \
-	"incw %w0\n\t" \
-	"rorl $16,%2\n\t" \
-	"movb 0(%1,%0),%b2\n\t" \
-	"incw %w0\n\t" \
-	"movb 0(%1,%0),%h2\n\t" \
-	"incw %w0\n\t" \
-	"rorl $16,%2" \
-	: "=r" (ptr), "=r" (base), "=q" (__res) \
-	: "0" (ptr), "1" (base)); \
-__res; })
+#define val_byte(val, n) (((__u8 *)&val)[n])
 
-static void do_int(struct kernel_vm86_regs *regs, int i, unsigned char * ssp, unsigned long sp)
+#define pushb(base, ptr, val, err_label) \
+	do { \
+		__u8 __val = val; \
+		ptr--; \
+		if (put_user(__val, base + ptr) < 0) \
+			goto err_label; \
+	} while(0)
+
+#define pushw(base, ptr, val, err_label) \
+	do { \
+		__u16 __val = val; \
+		ptr--; \
+		if (put_user(val_byte(__val, 1), base + ptr) < 0) \
+			goto err_label; \
+		ptr--; \
+		if (put_user(val_byte(__val, 0), base + ptr) < 0) \
+			goto err_label; \
+	} while(0)
+
+#define pushl(base, ptr, val, err_label) \
+	do { \
+		__u32 __val = val; \
+		ptr--; \
+		if (put_user(val_byte(__val, 3), base + ptr) < 0) \
+			goto err_label; \
+		ptr--; \
+		if (put_user(val_byte(__val, 2), base + ptr) < 0) \
+			goto err_label; \
+		ptr--; \
+		if (put_user(val_byte(__val, 1), base + ptr) < 0) \
+			goto err_label; \
+		ptr--; \
+		if (put_user(val_byte(__val, 0), base + ptr) < 0) \
+			goto err_label; \
+	} while(0)
+
+#define popb(base, ptr, err_label) \
+	({ \
+	 	__u8 __res; \
+		if (get_user(__res, base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		__res; \
+	})
+
+#define popw(base, ptr, err_label) \
+	({ \
+	 	__u16 __res; \
+		if (get_user(val_byte(__res, 0), base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		if (get_user(val_byte(__res, 1), base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		__res; \
+	})
+
+#define popl(base, ptr, err_label) \
+	({ \
+	 	__u32 __res; \
+		if (get_user(val_byte(__res, 0), base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		if (get_user(val_byte(__res, 1), base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		if (get_user(val_byte(__res, 2), base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		if (get_user(val_byte(__res, 3), base + ptr) < 0) \
+			goto err_label; \
+		ptr++; \
+		__res; \
+	})
+
+/* There are so many possible reasons for this function to return
+ * VM86_INTx, so adding another doesn't bother me. We can expect
+ * userspace programs to be able to handle it. (Getting a problem
+ * in userspace is always better than an Oops anyway.) [KD]
+ */
+static void do_int(struct kernel_vm86_regs *regs, int i,
+    unsigned char * ssp, unsigned short sp)
 {
 	unsigned long *intr_ptr, segoffs;
 
@@ -411,14 +471,15 @@
 		goto cannot_handle;
 	if ((segoffs >> 16) == BIOSSEG)
 		goto cannot_handle;
-	pushw(ssp, sp, get_vflags(regs));
-	pushw(ssp, sp, regs->cs);
-	pushw(ssp, sp, IP(regs));
+	pushw(ssp, sp, get_vflags(regs), cannot_handle);
+	pushw(ssp, sp, regs->cs, cannot_handle);
+	pushw(ssp, sp, IP(regs), cannot_handle);
 	regs->cs = segoffs >> 16;
 	SP(regs) -= 6;
 	IP(regs) = segoffs & 0xffff;
 	clear_TF(regs);
 	clear_IF(regs);
+	clear_AC(regs);
 	return;
 
 cannot_handle:
@@ -450,75 +511,80 @@
 
 void handle_vm86_fault(struct kernel_vm86_regs * regs, long error_code)
 {
-	unsigned char *csp, *ssp;
-	unsigned long ip, sp;
+	unsigned char *csp, *ssp, opcode;
+	unsigned short ip, sp;
+	int data32, pref_done;
 
 #define CHECK_IF_IN_TRAP \
 	if (VMPI.vm86dbg_active && VMPI.vm86dbg_TFpendig) \
-		pushw(ssp,sp,popw(ssp,sp) | TF_MASK);
-#define VM86_FAULT_RETURN \
+		newflags |= TF_MASK
+#define VM86_FAULT_RETURN do { \
 	if (VMPI.force_return_for_pic  && (VEFLAGS & (IF_MASK | VIF_MASK))) \
 		return_to_32bit(regs, VM86_PICRETURN); \
-	return;
+	return; } while (0)
 	                                   
 	csp = (unsigned char *) (regs->cs << 4);
 	ssp = (unsigned char *) (regs->ss << 4);
 	sp = SP(regs);
 	ip = IP(regs);
 
-	switch (popb(csp, ip)) {
-
-	/* operand size override */
-	case 0x66:
-		switch (popb(csp, ip)) {
-
-		/* pushfd */
-		case 0x9c:
-			SP(regs) -= 4;
-			IP(regs) += 2;
-			pushl(ssp, sp, get_vflags(regs));
-			VM86_FAULT_RETURN;
-
-		/* popfd */
-		case 0x9d:
-			SP(regs) += 4;
-			IP(regs) += 2;
-			CHECK_IF_IN_TRAP
-			set_vflags_long(popl(ssp, sp), regs);
-			VM86_FAULT_RETURN;
-
-		/* iretd */
-		case 0xcf:
-			SP(regs) += 12;
-			IP(regs) = (unsigned short)popl(ssp, sp);
-			regs->cs = (unsigned short)popl(ssp, sp);
-			CHECK_IF_IN_TRAP
-			set_vflags_long(popl(ssp, sp), regs);
-			VM86_FAULT_RETURN;
-		/* need this to avoid a fallthrough */
-		default:
-			return_to_32bit(regs, VM86_UNKNOWN);
+	data32 = 0;
+	pref_done = 0;
+	do {
+		switch (opcode = popb(csp, ip, simulate_sigsegv)) {
+			case 0x66:      /* 32-bit data */     data32=1; break;
+			case 0x67:      /* 32-bit address */  break;
+			case 0x2e:      /* CS */              break;
+			case 0x3e:      /* DS */              break;
+			case 0x26:      /* ES */              break;
+			case 0x36:      /* SS */              break;
+			case 0x65:      /* GS */              break;
+			case 0x64:      /* FS */              break;
+			case 0xf2:      /* repnz */	      break;
+			case 0xf3:      /* rep */             break;
+			default: pref_done = 1;
 		}
+	} while (!pref_done);
+
+	switch (opcode) {
 
 	/* pushf */
 	case 0x9c:
-		SP(regs) -= 2;
-		IP(regs)++;
-		pushw(ssp, sp, get_vflags(regs));
+		if (data32) {
+			pushl(ssp, sp, get_vflags(regs), simulate_sigsegv);
+			SP(regs) -= 4;
+		} else {
+			pushw(ssp, sp, get_vflags(regs), simulate_sigsegv);
+			SP(regs) -= 2;
+		}
+		IP(regs) = ip;
 		VM86_FAULT_RETURN;
 
 	/* popf */
 	case 0x9d:
-		SP(regs) += 2;
-		IP(regs)++;
-		CHECK_IF_IN_TRAP
-		set_vflags_short(popw(ssp, sp), regs);
+		{
+		unsigned long newflags;
+		if (data32) {
+			newflags=popl(ssp, sp, simulate_sigsegv);
+			SP(regs) += 4;
+		} else {
+			newflags = popw(ssp, sp, simulate_sigsegv);
+			SP(regs) += 2;
+		}
+		IP(regs) = ip;
+		CHECK_IF_IN_TRAP;
+		if (data32) {
+			set_vflags_long(newflags, regs);
+		} else {
+			set_vflags_short(newflags, regs);
+		}
 		VM86_FAULT_RETURN;
+		}
 
 	/* int xx */
 	case 0xcd: {
-	        int intno=popb(csp, ip);
-		IP(regs) += 2;
+	        int intno=popb(csp, ip, simulate_sigsegv);
+		IP(regs) = ip;
 		if (VMPI.vm86dbg_active) {
 			if ( (1 << (intno &7)) & VMPI.vm86dbg_intxxtab[intno >> 3] )
 				return_to_32bit(regs, VM86_INTx + (intno << 8));
@@ -529,16 +595,35 @@
 
 	/* iret */
 	case 0xcf:
-		SP(regs) += 6;
-		IP(regs) = popw(ssp, sp);
-		regs->cs = popw(ssp, sp);
-		CHECK_IF_IN_TRAP
-		set_vflags_short(popw(ssp, sp), regs);
+		{
+		unsigned long newip;
+		unsigned long newcs;
+		unsigned long newflags;
+		if (data32) {
+			newip=popl(ssp, sp, simulate_sigsegv);
+			newcs=popl(ssp, sp, simulate_sigsegv);
+			newflags=popl(ssp, sp, simulate_sigsegv);
+			SP(regs) += 12;
+		} else {
+			newip = popw(ssp, sp, simulate_sigsegv);
+			newcs = popw(ssp, sp, simulate_sigsegv);
+			newflags = popw(ssp, sp, simulate_sigsegv);
+			SP(regs) += 6;
+		}
+		IP(regs) = newip;
+		regs->cs = newcs;
+		CHECK_IF_IN_TRAP;
+		if (data32) {
+			set_vflags_long(newflags, regs);
+		} else {
+			set_vflags_short(newflags, regs);
+		}
 		VM86_FAULT_RETURN;
+		}
 
 	/* cli */
 	case 0xfa:
-		IP(regs)++;
+		IP(regs) = ip;
 		clear_IF(regs);
 		VM86_FAULT_RETURN;
 
@@ -550,13 +635,28 @@
 	 * Probably needs some horsing around with the TF flag. Aiee..
 	 */
 	case 0xfb:
-		IP(regs)++;
+		IP(regs) = ip;
 		set_IF(regs);
 		VM86_FAULT_RETURN;
 
 	default:
 		return_to_32bit(regs, VM86_UNKNOWN);
 	}
+
+	return;
+
+simulate_sigsegv:
+	/* FIXME: After a long discussion with Stas we finally
+	 *        agreed, that this is wrong. Here we should
+	 *        really send a SIGSEGV to the user program.
+	 *        But how do we create the correct context? We
+	 *        are inside a general protection fault handler
+	 *        and has just returned from a page fault handler.
+	 *        The correct context for the signal handler
+	 *        should be a mixture of the two, but how do we
+	 *        get the information? [KD]
+	 */
+	return_to_32bit(regs, VM86_UNKNOWN);
 }
 
 /* ---------------- vm86 special IRQ passing stuff ----------------- */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/lib/mmx.c linux/arch/i386/lib/mmx.c
--- linux.orig/arch/i386/lib/mmx.c	2001-05-22 17:23:16.000000000 +0000
+++ linux/arch/i386/lib/mmx.c	2002-08-01 06:42:45.000000000 +0000
@@ -57,7 +57,7 @@
 		: : "r" (from) );
 		
 	
-	for(; i>0; i--)
+	for(; i>5; i--)
 	{
 		__asm__ __volatile__ (
 		"1:  prefetch 320(%0)\n"
@@ -89,6 +89,30 @@
 		from+=64;
 		to+=64;
 	}
+
+	for(; i>0; i--)
+	{
+		__asm__ __volatile__ (
+		"  movq (%0), %%mm0\n"
+		"  movq 8(%0), %%mm1\n"
+		"  movq 16(%0), %%mm2\n"
+		"  movq 24(%0), %%mm3\n"
+		"  movq %%mm0, (%1)\n"
+		"  movq %%mm1, 8(%1)\n"
+		"  movq %%mm2, 16(%1)\n"
+		"  movq %%mm3, 24(%1)\n"
+		"  movq 32(%0), %%mm0\n"
+		"  movq 40(%0), %%mm1\n"
+		"  movq 48(%0), %%mm2\n"
+		"  movq 56(%0), %%mm3\n"
+		"  movq %%mm0, 32(%1)\n"
+		"  movq %%mm1, 40(%1)\n"
+		"  movq %%mm2, 48(%1)\n"
+		"  movq %%mm3, 56(%1)\n"
+		: : "r" (from), "r" (to) : "memory");
+		from+=64;
+		to+=64;
+	}
 	/*
 	 *	Now do the tail of the block
 	 */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/math-emu/reg_add_sub.c linux/arch/i386/math-emu/reg_add_sub.c
--- linux.orig/arch/i386/math-emu/reg_add_sub.c	1997-12-10 01:57:09.000000000 +0000
+++ linux/arch/i386/math-emu/reg_add_sub.c	2002-08-01 06:42:44.000000000 +0000
@@ -140,7 +140,7 @@
   FPU_REG const *a, *b;
   FPU_REG *dest;
   u_char taga, tagb, signa, signb, saved_sign, sign;
-  int diff, tag, expa, expb, deststnr;
+  int diff, tag = 0, expa, expb, deststnr;
 
   a = &st(0);
   taga = FPU_gettag0();
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/math-emu/reg_compare.c linux/arch/i386/math-emu/reg_compare.c
--- linux.orig/arch/i386/math-emu/reg_compare.c	2001-04-06 17:42:47.000000000 +0000
+++ linux/arch/i386/math-emu/reg_compare.c	2002-08-01 06:42:38.000000000 +0000
@@ -174,7 +174,7 @@
 /* This function requires that st(0) is not empty */
 int FPU_compare_st_data(FPU_REG const *loaded_data, u_char loaded_tag)
 {
-  int f, c;
+  int f = 0, c;
 
   c = compare(loaded_data, loaded_tag);
 
@@ -216,7 +216,7 @@
 
 static int compare_st_st(int nr)
 {
-  int f, c;
+  int f = 0, c;
   FPU_REG *st_ptr;
 
   if ( !NOT_EMPTY(0) || !NOT_EMPTY(nr) )
@@ -268,7 +268,7 @@
 
 static int compare_u_st_st(int nr)
 {
-  int f, c;
+  int f = 0, c;
   FPU_REG *st_ptr;
 
   if ( !NOT_EMPTY(0) || !NOT_EMPTY(nr) )
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/math-emu/reg_divide.c linux/arch/i386/math-emu/reg_divide.c
--- linux.orig/arch/i386/math-emu/reg_divide.c	2001-04-06 17:42:47.000000000 +0000
+++ linux/arch/i386/math-emu/reg_divide.c	2002-08-01 06:42:28.000000000 +0000
@@ -203,4 +203,5 @@
     }
 #endif /* PARANOID */ 
 
+	return 0;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/math-emu/reg_ld_str.c linux/arch/i386/math-emu/reg_ld_str.c
--- linux.orig/arch/i386/math-emu/reg_ld_str.c	2001-04-06 17:42:47.000000000 +0000
+++ linux/arch/i386/math-emu/reg_ld_str.c	2002-08-01 06:42:32.000000000 +0000
@@ -632,7 +632,7 @@
 /* Put a float into user memory */
 int FPU_store_single(FPU_REG *st0_ptr, u_char st0_tag, float *single)
 {
-  long templ;
+  long templ = 0;
   unsigned long increment = 0;     	/* avoid gcc warnings */
   int precision_loss;
   int exp;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/math-emu/reg_mul.c linux/arch/i386/math-emu/reg_mul.c
--- linux.orig/arch/i386/math-emu/reg_mul.c	2001-04-06 17:42:47.000000000 +0000
+++ linux/arch/i386/math-emu/reg_mul.c	2002-08-01 06:42:37.000000000 +0000
@@ -128,4 +128,5 @@
     }
 #endif /* PARANOID */ 
 
+	return 0;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/mm/fault.c linux/arch/i386/mm/fault.c
--- linux.orig/arch/i386/mm/fault.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/i386/mm/fault.c	2002-08-01 06:42:28.000000000 +0000
@@ -125,12 +125,6 @@
 	}
 }
 
-void do_BUG(const char *file, int line)
-{
-	bust_spinlocks(1);
-	printk("kernel BUG at %s:%d!\n", file, line);
-}
-
 asmlinkage void do_invalid_op(struct pt_regs *, unsigned long);
 extern unsigned long idt;
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/mm/init.c linux/arch/i386/mm/init.c
--- linux.orig/arch/i386/mm/init.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/i386/mm/init.c	2002-08-01 06:42:35.000000000 +0000
@@ -128,7 +128,6 @@
 static inline void set_pte_phys (unsigned long vaddr,
 			unsigned long phys, pgprot_t flags)
 {
-	pgprot_t prot;
 	pgd_t *pgd;
 	pmd_t *pmd;
 	pte_t *pte;
@@ -144,10 +143,8 @@
 		return;
 	}
 	pte = pte_offset(pmd, vaddr);
-	if (pte_val(*pte))
-		pte_ERROR(*pte);
-	pgprot_val(prot) = pgprot_val(PAGE_KERNEL) | pgprot_val(flags);
-	set_pte(pte, mk_pte_phys(phys, prot));
+	/* <phys,flags> stored as-is, to permit clearing entries */
+	set_pte(pte, mk_pte_phys(phys, flags));
 
 	/*
 	 * It's enough to flush this one mapping.
@@ -334,7 +331,7 @@
 {
 	pagetable_init();
 
-	__asm__( "movl %%ecx,%%cr3\n" ::"c"(__pa(swapper_pg_dir)));
+	load_cr3(swapper_pg_dir);	
 
 #if CONFIG_X86_PAE
 	/*
@@ -462,8 +459,9 @@
 #ifdef CONFIG_HIGHMEM
 	highmem_start_page = mem_map + highstart_pfn;
 	max_mapnr = num_physpages = highend_pfn;
+	num_mappedpages = max_low_pfn;
 #else
-	max_mapnr = num_physpages = max_low_pfn;
+	max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
 #endif
 	high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
 
@@ -505,7 +503,7 @@
 	datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
 	initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
 
-	printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init, %ldk highmem)\n",
+	printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init, %ldk highmem)\n",
 		(unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
 		max_mapnr << (PAGE_SHIFT-10),
 		codesize >> 10,
@@ -569,14 +567,14 @@
 		free_page(addr);
 		totalram_pages++;
 	}
-	printk ("Freeing unused kernel memory: %dk freed\n", (&__init_end - &__init_begin) >> 10);
+	printk (KERN_INFO "Freeing unused kernel memory: %dk freed\n", (&__init_end - &__init_begin) >> 10);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (start < end)
-		printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+		printk (KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
 	for (; start < end; start += PAGE_SIZE) {
 		ClearPageReserved(virt_to_page(start));
 		set_page_count(virt_to_page(start), 1);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/i386/mm/ioremap.c linux/arch/i386/mm/ioremap.c
--- linux.orig/arch/i386/mm/ioremap.c	2001-03-20 16:13:33.000000000 +0000
+++ linux/arch/i386/mm/ioremap.c	2002-08-01 06:42:36.000000000 +0000
@@ -161,3 +161,68 @@
 	if (addr > high_memory)
 		return vfree((void *) (PAGE_MASK & (unsigned long) addr));
 }
+
+void __init *bt_ioremap(unsigned long phys_addr, unsigned long size)
+{
+	unsigned long offset, last_addr;
+	unsigned int nrpages;
+	enum fixed_addresses idx;
+
+	/* Don't allow wraparound or zero size */
+	last_addr = phys_addr + size - 1;
+	if (!size || last_addr < phys_addr)
+		return NULL;
+
+	/*
+	 * Don't remap the low PCI/ISA area, it's always mapped..
+	 */
+	if (phys_addr >= 0xA0000 && last_addr < 0x100000)
+		return phys_to_virt(phys_addr);
+
+	/*
+	 * Mappings have to be page-aligned
+	 */
+	offset = phys_addr & ~PAGE_MASK;
+	phys_addr &= PAGE_MASK;
+	size = PAGE_ALIGN(last_addr) - phys_addr;
+
+	/*
+	 * Mappings have to fit in the FIX_BTMAP area.
+	 */
+	nrpages = size >> PAGE_SHIFT;
+	if (nrpages > NR_FIX_BTMAPS)
+		return NULL;
+
+	/*
+	 * Ok, go for it..
+	 */
+	idx = FIX_BTMAP_BEGIN;
+	while (nrpages > 0) {
+		set_fixmap(idx, phys_addr);
+		phys_addr += PAGE_SIZE;
+		--idx;
+		--nrpages;
+	}
+	return (void*) (offset + fix_to_virt(FIX_BTMAP_BEGIN));
+}
+
+void __init bt_iounmap(void *addr, unsigned long size)
+{
+	unsigned long virt_addr;
+	unsigned long offset;
+	unsigned int nrpages;
+	enum fixed_addresses idx;
+
+	virt_addr = (unsigned long)addr;
+	if (virt_addr < fix_to_virt(FIX_BTMAP_BEGIN))
+		return;
+	offset = virt_addr & ~PAGE_MASK;
+	nrpages = PAGE_ALIGN(offset + size - 1) >> PAGE_SHIFT;
+
+	idx = FIX_BTMAP_BEGIN;
+	while (nrpages > 0) {
+		__set_fixmap(idx, 0, __pgprot(0));
+		--idx;
+		--nrpages;
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/Makefile linux/arch/ia64/Makefile
--- linux.orig/arch/ia64/Makefile	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/Makefile	2002-08-01 06:42:29.000000000 +0000
@@ -25,7 +25,7 @@
 GCC_VERSION=$(shell $(CROSS_COMPILE)$(HOSTCC) -v 2>&1 | fgrep 'gcc version' | cut -f3 -d' ' | cut -f1 -d'.')
 
 ifneq ($(GCC_VERSION),2)
-	CFLAGS += -frename-registers --param max-inline-insns=400
+	CFLAGS += -frename-registers --param max-inline-insns=2000
 endif
 
 ifeq ($(CONFIG_ITANIUM_BSTEP_SPECIFIC),y)
@@ -58,7 +58,7 @@
 	CFLAGS		+= -DBRINGUP
         SUBDIRS         :=      arch/$(ARCH)/sn/kernel	\
 				arch/$(ARCH)/sn/io	\
-				arch/$(ARCH)/sn/fprom	\
+				arch/$(ARCH)/sn/fakeprom	\
 				$(SUBDIRS)
         CORE_FILES      :=      arch/$(ARCH)/sn/kernel/sn.o	\
 				arch/$(ARCH)/sn/io/sgiio.o	\
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/config.in linux/arch/ia64/config.in
--- linux.orig/arch/ia64/config.in	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/config.in	2002-08-01 06:42:45.000000000 +0000
@@ -135,6 +135,7 @@
 source drivers/mtd/Config.in
 source drivers/pnp/Config.in
 source drivers/block/Config.in
+source drivers/ieee1394/Config.in
 source drivers/message/i2o/Config.in
 source drivers/md/Config.in
 
@@ -163,6 +164,10 @@
 fi
 endmenu
 
+if [ "$CONFIG_PCI" = "y" ]; then
+  source drivers/message/fusion/Config.in
+fi
+
 if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then
 
 if [ "$CONFIG_NET" = "y" ]; then
@@ -244,7 +249,7 @@
   mainmenu_option next_comment
   comment 'Simulated drivers'
 
-  tristate 'Simulated Ethernet ' CONFIG_SIMETH
+  bool 'Simulated Ethernet ' CONFIG_SIMETH
   bool 'Simulated serial driver support' CONFIG_SIM_SERIAL
   if [ "$CONFIG_SCSI" != "n" ]; then
     bool 'Simulated SCSI disk' CONFIG_SCSI_SIM
@@ -266,9 +271,7 @@
    bool '  Disable VHPT' CONFIG_DISABLE_VHPT
    bool '  Magic SysRq key' CONFIG_MAGIC_SYSRQ
 
-# early printk is currently broken for SMP: the secondary processors get stuck...
-#   bool '  Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK
-
+   bool '  Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK
    bool '  Debug memory allocations' CONFIG_DEBUG_SLAB
    bool '  Spinlock debugging' CONFIG_DEBUG_SPINLOCK
    bool '  Turn on compare-and-exchange bug checking (slow!)' CONFIG_IA64_DEBUG_CMPXCHG
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/defconfig linux/arch/ia64/defconfig
--- linux.orig/arch/ia64/defconfig	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/defconfig	2002-08-01 06:42:31.000000000 +0000
@@ -299,6 +299,7 @@
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
 # CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_NCR53C8XX is not set
 # CONFIG_SCSI_SYM53C8XX is not set
 # CONFIG_SCSI_PAS16 is not set
@@ -373,6 +374,7 @@
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_NET_POCKET is not set
 
@@ -554,6 +556,9 @@
 # CONFIG_TUNER_3036 is not set
 # CONFIG_VIDEO_STRADIS is not set
 # CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIDEO_ZORAN_BUZ is not set
+# CONFIG_VIDEO_ZORAN_DC10 is not set
+# CONFIG_VIDEO_ZORAN_LML33 is not set
 # CONFIG_VIDEO_ZR36120 is not set
 # CONFIG_VIDEO_MEYE is not set
 
@@ -584,11 +589,15 @@
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
 # CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
 CONFIG_FAT_FS=y
 CONFIG_MSDOS_FS=y
 # CONFIG_UMSDOS_FS is not set
@@ -626,6 +635,7 @@
 # Network File Systems
 #
 # CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_ROOT_NFS is not set
@@ -874,6 +884,7 @@
 CONFIG_IA64_PRINT_HAZARDS=y
 # CONFIG_DISABLE_VHPT is not set
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_IA64_DEBUG_CMPXCHG is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/hp/hpsim_console.c linux/arch/ia64/hp/hpsim_console.c
--- linux.orig/arch/ia64/hp/hpsim_console.c	2000-10-12 21:20:48.000000000 +0000
+++ linux/arch/ia64/hp/hpsim_console.c	2002-08-01 06:42:37.000000000 +0000
@@ -24,14 +24,12 @@
 
 static int simcons_init (struct console *, char *);
 static void simcons_write (struct console *, const char *, unsigned);
-static int simcons_wait_key (struct console *);
 static kdev_t simcons_console_device (struct console *);
 
 struct console hpsim_cons = {
 	name:		"simcons",
 	write:		simcons_write,
 	device:		simcons_console_device,
-	wait_key:	simcons_wait_key,
 	setup:		simcons_init,
 	flags:		CON_PRINTBUFFER,
 	index:		-1,
@@ -56,17 +54,6 @@
 	}
 }
 
-static int
-simcons_wait_key (struct console *cons)
-{
-	char ch;
-
-	do {
-		ch = ia64_ssc(0, 0, 0, 0, SSC_GETCHAR);
-	} while (ch == '\0');
-	return ch;
-}
-
 static kdev_t
 simcons_console_device (struct console *c)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/binfmt_elf32.c linux/arch/ia64/ia32/binfmt_elf32.c
--- linux.orig/arch/ia64/ia32/binfmt_elf32.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/binfmt_elf32.c	2002-08-01 06:42:47.000000000 +0000
@@ -142,10 +142,11 @@
 	/*
 	 * Setup GDTD.  Note: GDTD is the descrambled version of the pseudo-descriptor
 	 * format defined by Figure 3-11 "Pseudo-Descriptor Format" in the IA-32
-	 * architecture manual.
+	 * architecture manual. Also note that the only fields that are not ignored are
+	 * `base', `limit', 'G', `P' (must be 1) and `S' (must be 0).
 	 */
-	regs->r31 = IA32_SEG_UNSCRAMBLE(IA32_SEG_DESCRIPTOR(IA32_GDT_OFFSET, IA32_PAGE_SIZE - 1, 0,
-							    0, 0, 0, 0, 0, 0));
+	regs->r31 = IA32_SEG_UNSCRAMBLE(IA32_SEG_DESCRIPTOR(IA32_GDT_OFFSET, IA32_PAGE_SIZE - 1,
+							    0, 0, 0, 1, 0, 0, 0));
 	/* Setup the segment selectors */
 	regs->r16 = (__USER_DS << 16) | __USER_DS; /* ES == DS, GS, FS are zero */
 	regs->r17 = (__USER_DS << 16) | __USER_CS; /* SS, CS; ia32_load_state() sets TSS and LDT */
@@ -206,6 +207,7 @@
 	set_personality(PER_LINUX32);
 	current->thread.map_base  = IA32_PAGE_OFFSET/3;
 	current->thread.task_size = IA32_PAGE_OFFSET;	/* use what Linux/x86 uses... */
+	current->thread.flags |= IA64_THREAD_XSTACK;	/* data must be executable */
 	set_fs(USER_DS);				/* set addr limit for new TASK_SIZE */
 }
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/ia32_entry.S linux/arch/ia64/ia32/ia32_entry.S
--- linux.orig/arch/ia64/ia32/ia32_entry.S	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/ia32_entry.S	2002-08-01 06:42:28.000000000 +0000
@@ -37,7 +37,7 @@
 	mov loc1=r16				// save ar.pfs across do_fork
 	.body
 	zxt4 out1=in1				// newsp
-	mov out3=0				// stacksize
+	mov out3=16				// stacksize (compensates for 16-byte scratch area)
 	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
 	zxt4 out0=in0				// out0 = clone_flags
 	br.call.sptk.many rp=do_fork
@@ -220,7 +220,7 @@
 	data8 sys32_pipe
 	data8 sys32_times
 	data8 sys32_ni_syscall	  /* old prof syscall holder */
-	data8 sys_brk		  /* 45 */
+	data8 sys32_brk		  /* 45 */
 	data8 sys_setgid	/* 16-bit version */
 	data8 sys_getgid	/* 16-bit version */
 	data8 sys32_signal
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/ia32_ioctl.c linux/arch/ia64/ia32/ia32_ioctl.c
--- linux.orig/arch/ia64/ia32/ia32_ioctl.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/ia32_ioctl.c	2002-08-01 06:42:46.000000000 +0000
@@ -79,6 +79,38 @@
 
 		      return ret;
 	      }
+		case IOCTL_NR(SIOCGIFCONF):
+		{
+			struct ifconf32 {
+				int		ifc_len;
+				unsigned int	ifc_ptr;
+			} ifconf32;
+			struct ifconf ifconf;
+			int i, n;
+			char *p32, *p64;
+			char buf[32];	/* sizeof IA32 ifreq structure */
+
+			if (copy_from_user(&ifconf32, P(arg), sizeof(ifconf32)))
+				return -EFAULT;
+			ifconf.ifc_len = ifconf32.ifc_len;
+			ifconf.ifc_req = P(ifconf32.ifc_ptr);
+			ret = DO_IOCTL(fd, SIOCGIFCONF, &ifconf);
+			ifconf32.ifc_len = ifconf.ifc_len;
+			if (copy_to_user(P(arg), &ifconf32, sizeof(ifconf32)))
+				return -EFAULT;
+			n = ifconf.ifc_len / sizeof(struct ifreq);
+			p32 = P(ifconf32.ifc_ptr);
+			p64 = P(ifconf32.ifc_ptr);
+			for (i = 0; i < n; i++) {
+				if (copy_from_user(buf, p64, sizeof(struct ifreq)))
+					return -EFAULT;
+				if (copy_to_user(p32, buf, sizeof(buf)))
+					return -EFAULT;
+				p32 += sizeof(buf);
+				p64 += sizeof(struct ifreq);
+			}
+			return ret;
+		}
 
 	      case IOCTL_NR(DRM_IOCTL_VERSION):
 	      {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/ia32_signal.c linux/arch/ia64/ia32/ia32_signal.c
--- linux.orig/arch/ia64/ia32/ia32_signal.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/ia32_signal.c	2002-08-01 06:42:29.000000000 +0000
@@ -522,6 +522,7 @@
 static int
 setup_frame_ia32 (int sig, struct k_sigaction *ka, sigset_t *set, struct pt_regs * regs)
 {
+	struct exec_domain *ed = current->exec_domain;
 	struct sigframe_ia32 *frame;
 	int err = 0;
 
@@ -530,12 +531,8 @@
 	if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
 		goto give_sigsegv;
 
-	err |= __put_user((current->exec_domain
-			   && current->exec_domain->signal_invmap
-			   && sig < 32
-			   ? (int)(current->exec_domain->signal_invmap[sig])
-			   : sig),
-			  &frame->sig);
+	err |= __put_user((ed && ed->signal_invmap
+			   && sig < 32 ? (int)(ed->signal_invmap[sig]) : sig), &frame->sig);
 
 	err |= setup_sigcontext_ia32(&frame->sc, &frame->fpstate, regs, set->sig[0]);
 
@@ -590,6 +587,7 @@
 setup_rt_frame_ia32 (int sig, struct k_sigaction *ka, siginfo_t *info,
 		     sigset_t *set, struct pt_regs * regs)
 {
+	struct exec_domain *ed = current->exec_domain;
 	struct rt_sigframe_ia32 *frame;
 	int err = 0;
 
@@ -598,11 +596,8 @@
 	if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
 		goto give_sigsegv;
 
-	err |= __put_user((current->exec_domain
-			   && current->exec_domain->signal_invmap
-			   && sig < 32
-			   ? current->exec_domain->signal_invmap[sig]
-			   : sig),
+	err |= __put_user((ed && ed->signal_invmap
+			   && sig < 32 ? ed->signal_invmap[sig] : sig),
 			  &frame->sig);
 	err |= __put_user((long)&frame->info, &frame->pinfo);
 	err |= __put_user((long)&frame->uc, &frame->puc);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/ia32_support.c linux/arch/ia64/ia32/ia32_support.c
--- linux.orig/arch/ia64/ia32/ia32_support.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/ia32_support.c	2002-08-01 06:42:31.000000000 +0000
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 2000 Asit K. Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 2001 Hewlett-Packard Co
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 06/16/00	A. Mallick	added csd/ssd/tssd for ia32 thread context
@@ -153,10 +153,12 @@
 	/* We never change the TSS and LDT descriptors, so we can share them across all CPUs.  */
 	ldt_size = PAGE_ALIGN(IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE);
 	for (nr = 0; nr < NR_CPUS; ++nr) {
-		ia32_gdt[_TSS(nr)] = IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235,
-							 0xb, 0, 3, 1, 1, 1, 0);
-		ia32_gdt[_LDT(nr)] = IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1,
-							 0x2, 0, 3, 1, 1, 1, 0);
+		ia32_gdt[_TSS(nr) >> IA32_SEGSEL_INDEX_SHIFT]
+			= IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235,
+					      0xb, 0, 3, 1, 1, 1, 0);
+		ia32_gdt[_LDT(nr) >> IA32_SEGSEL_INDEX_SHIFT]
+			= IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1,
+					      0x2, 0, 3, 1, 1, 1, 0);
 	}
 }
 
@@ -172,6 +174,10 @@
 
 	siginfo.si_signo = SIGTRAP;
 	siginfo.si_errno = int_num;	/* XXX is it OK to abuse si_errno like this? */
+	siginfo.si_flags = 0;
+	siginfo.si_isr = 0;
+	siginfo.si_addr = 0;
+	siginfo.si_imm = 0;
 	siginfo.si_code = TRAP_BRKPT;
 	force_sig_info(SIGTRAP, &siginfo, current);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/ia32_traps.c linux/arch/ia64/ia32/ia32_traps.c
--- linux.orig/arch/ia64/ia32/ia32_traps.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/ia32_traps.c	2002-08-01 06:42:39.000000000 +0000
@@ -2,7 +2,7 @@
  * IA-32 exception handlers
  *
  * Copyright (C) 2000 Asit K. Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 2001 Hewlett-Packard Co
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 06/16/00	A. Mallick	added siginfo for most cases (close to IA32)
@@ -40,7 +40,11 @@
 {
 	struct siginfo siginfo;
 
+	/* initialize these fields to avoid leaking kernel bits to user space: */
 	siginfo.si_errno = 0;
+	siginfo.si_flags = 0;
+	siginfo.si_isr = 0;
+	siginfo.si_imm = 0;
 	switch ((isr >> 16) & 0xff) {
 	      case 1:
 	      case 2:
@@ -103,6 +107,8 @@
 			 * and it will suffer the consequences since we won't be able to
 			 * fully reproduce the context of the exception
 			 */
+			siginfo.si_isr = isr;
+			siginfo.si_flags = __ISR_VALID;
 			switch(((~fcr) & (fsr & 0x3f)) | (fsr & 0x240)) {
 				case 0x000:
 				default:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/ia32/sys_ia32.c linux/arch/ia64/ia32/sys_ia32.c
--- linux.orig/arch/ia64/ia32/sys_ia32.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/ia32/sys_ia32.c	2002-08-01 06:42:30.000000000 +0000
@@ -6,7 +6,7 @@
  * Copyright (C) 1999		Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 1997,1998	Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  * Copyright (C) 1997		David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2000-2001 Hewlett-Packard Co
+ * Copyright (C) 2000-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * These routines maintain argument size conversion between 32bit and 64bit
@@ -82,6 +82,7 @@
 
 /* forward declaration: */
 asmlinkage long sys32_mprotect (unsigned int, unsigned int, int);
+asmlinkage unsigned long sys_brk(unsigned long);
 
 /*
  * Anything that modifies or inspects ia32 user virtual memory must hold this semaphore
@@ -412,7 +413,7 @@
 			return -EINVAL;
 		}
 		if (!(prot & PROT_WRITE) && sys_mprotect(pstart, pend - pstart, prot) < 0)
-			return EINVAL;
+			return -EINVAL;
 	}
 	return start;
 }
@@ -2590,6 +2591,7 @@
 	      default:
 		return -EINVAL;
 	}
+	return -EINVAL;
 }
 
 /*
@@ -3810,6 +3812,19 @@
 	return ret;
 }
 
+asmlinkage unsigned long
+sys32_brk (unsigned int brk)
+{
+	unsigned long ret, obrk;
+	struct mm_struct *mm = current->mm;
+
+	obrk = mm->brk;
+	ret = sys_brk(brk);
+	if (ret < obrk)
+		clear_user((void *) ret, PAGE_ALIGN(ret) - ret);
+	return ret;
+}
+
 #ifdef	NOTYET  /* UNTESTED FOR IA64 FROM HERE DOWN */
 
 struct ncp_mount_data32 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/Makefile linux/arch/ia64/kernel/Makefile
--- linux.orig/arch/ia64/kernel/Makefile	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/Makefile	2002-08-01 06:42:43.000000000 +0000
@@ -14,7 +14,7 @@
 export-objs := ia64_ksyms.o
 
 obj-y := acpi.o entry.o gate.o efi.o efi_stub.o ia64_ksyms.o irq.o irq_ia64.o irq_lsapic.o ivt.o \
-	 machvec.o pal.o process.o perfmon.o ptrace.o sal.o semaphore.o setup.o	\
+	 machvec.o pal.o process.o perfmon.o ptrace.o sal.o salinfo.o semaphore.o setup.o	 \
 	 signal.o sys_ia64.o traps.o time.o unaligned.o unwind.o
 obj-$(CONFIG_IA64_GENERIC) += iosapic.o
 obj-$(CONFIG_IA64_DIG) += iosapic.o
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/acpi.c linux/arch/ia64/kernel/acpi.c
--- linux.orig/arch/ia64/kernel/acpi.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/acpi.c	2002-08-01 06:42:44.000000000 +0000
@@ -401,7 +401,7 @@
 # ifdef CONFIG_ACPI
 	acpi_xsdt_t *xsdt;
 	acpi_desc_table_hdr_t *hdrp;
-	acpi_madt_t *madt;
+	acpi_madt_t *madt = NULL;
 	int tables, i;
 
 	if (strncmp(rsdp20->signature, ACPI_RSDP_SIG, ACPI_RSDP_SIG_LEN)) {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/brl_emu.c linux/arch/ia64/kernel/brl_emu.c
--- linux.orig/arch/ia64/kernel/brl_emu.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/kernel/brl_emu.c	2002-08-01 06:42:36.000000000 +0000
@@ -2,6 +2,9 @@
  *  Emulation of the "brl" instruction for IA64 processors that
  *  don't support it in hardware.
  *  Author: Stephan Zeisset, Intel Corp. <Stephan.Zeisset@intel.com>
+ *
+ *    02/22/02	D. Mosberger	Clear si_flgs, si_isr, and si_imm to avoid
+ *				leaking kernel bits.
  */
 
 #include <linux/kernel.h>
@@ -195,6 +198,9 @@
 		printk("Woah! Unimplemented Instruction Address Trap!\n");
 		siginfo.si_signo = SIGILL;
 		siginfo.si_errno = 0;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_imm = 0;
 		siginfo.si_code = ILL_BADIADDR;
 		force_sig_info(SIGILL, &siginfo, current);
 	} else if (ia64_psr(regs)->tb) {
@@ -205,6 +211,10 @@
 		siginfo.si_signo = SIGTRAP;
 		siginfo.si_errno = 0;
 		siginfo.si_code = TRAP_BRANCH;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_addr = 0;
+		siginfo.si_imm = 0;
 		force_sig_info(SIGTRAP, &siginfo, current);
 	} else if (ia64_psr(regs)->ss) {
 		/*
@@ -214,6 +224,10 @@
 		siginfo.si_signo = SIGTRAP;
 		siginfo.si_errno = 0;
 		siginfo.si_code = TRAP_TRACE;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_addr = 0;
+		siginfo.si_imm = 0;
 		force_sig_info(SIGTRAP, &siginfo, current);
 	}
 	return rv;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/efi.c linux/arch/ia64/kernel/efi.c
--- linux.orig/arch/ia64/kernel/efi.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/efi.c	2002-08-01 06:42:29.000000000 +0000
@@ -346,6 +346,9 @@
 		} else if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == 0) {
 			efi.sal_systab = __va(config_tables[i].table);
 			printk(" SALsystab=0x%lx", config_tables[i].table);
+		} else if (efi_guidcmp(config_tables[i].guid, HCDP_TABLE_GUID) == 0) {
+			efi.hcdp = __va(config_tables[i].table);
+			printk(" HCDP=0x%lx", config_tables[i].table);
 		}
 	}
 	printk("\n");
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/efivars.c linux/arch/ia64/kernel/efivars.c
--- linux.orig/arch/ia64/kernel/efivars.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/ia64/kernel/efivars.c	2002-08-01 06:42:43.000000000 +0000
@@ -29,6 +29,11 @@
  *
  * Changelog:
  *
+ *  12 Feb 2002 - Matt Domsch <Matt_Domsch@dell.com>
+ *   use list_for_each_safe when deleting vars.
+ *   remove ifdef CONFIG_SMP around include <linux/smp.h>
+ *   v0.04 release to linux-ia64@linuxia64.org
+ *
  *  20 April 2001 - Matt Domsch <Matt_Domsch@dell.com>
  *   Moved vars from /proc/efi to /proc/efi/vars, and made
  *   efi.c own the /proc/efi directory.
@@ -56,18 +61,16 @@
 #include <linux/sched.h>		/* for capable() */
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/smp.h>
 
 #include <asm/efi.h>
 #include <asm/uaccess.h>
-#ifdef CONFIG_SMP
-#include <linux/smp.h>
-#endif
 
 MODULE_AUTHOR("Matt Domsch <Matt_Domsch@Dell.com>");
 MODULE_DESCRIPTION("/proc interface to EFI Variables");
 MODULE_LICENSE("GPL");
 
-#define EFIVARS_VERSION "0.03 2001-Apr-20"
+#define EFIVARS_VERSION "0.04 2002-Feb-12"
 
 static int
 efivar_read(char *page, char **start, off_t off,
@@ -265,7 +268,7 @@
 {
 	unsigned long strsize1, strsize2;
 	int found=0;
-	struct list_head *pos;
+	struct list_head *pos, *n;
 	unsigned long size = sizeof(efi_variable_t);
 	efi_status_t status;
 	efivar_entry_t *efivar = data, *search_efivar = NULL;
@@ -297,7 +300,7 @@
 	   This allows any properly formatted data structure to
 	   be written to any of the files in /proc/efi/vars and it will work.
 	*/
-	list_for_each(pos, &efivar_list) {
+	list_for_each_safe(pos, n, &efivar_list) {
 		search_efivar = efivar_entry(pos);
 		strsize1 = utf8_strsize(search_efivar->var.VariableName, 1024);
 		strsize2 = utf8_strsize(var_data->VariableName, 1024);
@@ -413,12 +416,12 @@
 static void __exit
 efivars_exit(void)
 {
-	struct list_head *pos;
+	struct list_head *pos, *n;
 	efivar_entry_t *efivar;
 
 	spin_lock(&efivars_lock);
 
-	list_for_each(pos, &efivar_list) {
+	list_for_each_safe(pos, n, &efivar_list) {
 		efivar = efivar_entry(pos);
 		remove_proc_entry(efivar->entry->name, efi_vars_dir);
 		list_del(&efivar->list);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/entry.S linux/arch/ia64/kernel/entry.S
--- linux.orig/arch/ia64/kernel/entry.S	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/entry.S	2002-08-01 06:42:36.000000000 +0000
@@ -115,7 +115,7 @@
 	mov loc1=r16				// save ar.pfs across do_fork
 	.body
 	mov out1=in1
-	mov out3=0
+	mov out3=16				// stacksize (compensates for 16-byte scratch area)
 	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
 	mov out0=in0				// out0 = clone_flags
 	br.call.sptk.many rp=do_fork
@@ -521,35 +521,38 @@
 	;;
 	mov.ret.sptk rp=r14,.restart
 .restart:
+	// need_resched and signals atomic test
+(pUser)	rsm psr.i
 	adds r17=IA64_TASK_NEED_RESCHED_OFFSET,r13
 	adds r18=IA64_TASK_SIGPENDING_OFFSET,r13
 #ifdef CONFIG_PERFMON
-	adds r19=IA64_TASK_PFM_MUST_BLOCK_OFFSET,r13
+	adds r19=IA64_TASK_PFM_OVFL_BLOCK_RESET_OFFSET,r13
 #endif
 	;;
 #ifdef CONFIG_PERFMON
-(pUser)	ld8 r19=[r19]				// load current->thread.pfm_must_block
+(pUser)	ld8 r19=[r19]				// load current->thread.pfm_ovfl_block_reset
 #endif
 (pUser)	ld8 r17=[r17]				// load current->need_resched
 (pUser)	ld4 r18=[r18]				// load current->sigpending
 	;;
 #ifdef CONFIG_PERFMON
-(pUser)	cmp.ne.unc p9,p0=r19,r0			// current->thread.pfm_must_block != 0?
+(pUser)	cmp.ne.unc p9,p0=r19,r0			// current->thread.pfm_ovfl_block_reset != 0?
 #endif
 (pUser)	cmp.ne.unc p7,p0=r17,r0			// current->need_resched != 0?
 (pUser)	cmp.ne.unc p8,p0=r18,r0			// current->sigpending != 0?
 	;;
-	adds r2=PT(R8)+16,r12
-	adds r3=PT(R9)+16,r12
 #ifdef CONFIG_PERFMON
-(p9)	br.call.spnt.many b7=pfm_block_on_overflow
+(p9)	br.call.spnt.many b7=pfm_ovfl_block_reset
 #endif
 #if __GNUC__ < 3
 (p7)	br.call.spnt.many b7=invoke_schedule
 #else
 (p7)	br.call.spnt.many b7=schedule
 #endif
-(p8)	br.call.spnt.many b7=handle_signal_delivery	// check & deliver pending signals
+(p8)	br.call.spnt.many rp=handle_signal_delivery	// check & deliver pending signals (once)
+	;;
+.ret9:	adds r2=PT(R8)+16,r12
+	adds r3=PT(R9)+16,r12
 	;;
 	// start restoring the state saved on the kernel stack (struct pt_regs):
 	ld8.fill r8=[r2],16
@@ -582,7 +585,7 @@
 	ld8.fill r30=[r2],16
 	ld8.fill r31=[r3],16
 	;;
-	rsm psr.i | psr.ic	// initiate turning off of interrupts & interruption collection
+	rsm psr.i | psr.ic	// initiate turning off of interrupt and interruption collection
 	invala			// invalidate ALAT
 	;;
 	ld8 r1=[r2],16		// ar.ccv
@@ -601,7 +604,7 @@
 	mov ar.fpsr=r13
 	mov b0=r14
 	;;
-	srlz.i			// ensure interrupts & interruption collection are off
+	srlz.i			// ensure interruption collection is off
 	mov b7=r15
 	;;
 	bsw.0			// switch back to bank 0
@@ -1142,7 +1145,7 @@
 	data8 ia64_ni_syscall
 	data8 ia64_ni_syscall
 	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
+	data8 sys_tkill
 	data8 ia64_ni_syscall			// 1230
 	data8 ia64_ni_syscall
 	data8 ia64_ni_syscall
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/gate.S linux/arch/ia64/kernel/gate.S
--- linux.orig/arch/ia64/kernel/gate.S	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/gate.S	2002-08-01 06:42:37.000000000 +0000
@@ -90,7 +90,7 @@
 (p8)	br.cond.spnt setup_rbs		// yup -> (clobbers r14, r15, and r16)
 back_from_setup_rbs:
 
-	.save ar.pfs, r8
+	.spillreg ar.pfs, r8
 	alloc r8=ar.pfs,0,0,3,0		// get CFM0, EC0, and CPL0 into r8
 	ld8 out0=[base0],16		// load arg0 (signum)
 	adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/head.S linux/arch/ia64/kernel/head.S
--- linux.orig/arch/ia64/kernel/head.S	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/head.S	2002-08-01 06:42:46.000000000 +0000
@@ -180,10 +180,12 @@
 	.rodata
 alive_msg:
 	stringz "I'm alive and well\n"
+alive_msg_end:
 	.previous
 
 	alloc r2=ar.pfs,0,0,2,0
 	movl out0=alive_msg
+	movl out1=alive_msg_end-alive_msg-1
 	;;
 	br.call.sptk.many rp=early_printk
 1:	// force new bundle
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/ia64_ksyms.c linux/arch/ia64/kernel/ia64_ksyms.c
--- linux.orig/arch/ia64/kernel/ia64_ksyms.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/ia64_ksyms.c	2002-08-01 06:42:43.000000000 +0000
@@ -24,6 +24,7 @@
 EXPORT_SYMBOL(strrchr);
 EXPORT_SYMBOL(strstr);
 EXPORT_SYMBOL(strtok);
+EXPORT_SYMBOL(strpbrk);
 
 #include <linux/irq.h>
 EXPORT_SYMBOL(isa_irq_to_vector_map);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/iosapic.c linux/arch/ia64/kernel/iosapic.c
--- linux.orig/arch/ia64/kernel/iosapic.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/iosapic.c	2002-08-01 06:42:43.000000000 +0000
@@ -3,8 +3,9 @@
  *
  * Copyright (C) 1999 Intel Corp.
  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 1999-2000 Hewlett-Packard Co.
- * Copyright (C) 1999-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
+ * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co.
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  *
@@ -15,6 +16,12 @@
  *				PCI to vector mapping, shared PCI interrupts.
  * 00/10/27	D. Mosberger	Document things a bit more to make them more understandable.
  *				Clean up much of the old IOSAPIC cruft.
+ * 01/07/27	J.I. Lee	PCI irq routing, Platform/Legacy interrupts and fixes for
+ *				ACPI S5(SoftOff) support.
+ * 02/01/23	J.I. Lee	iosapic pgm fixes for PCI irq routing from _PRT
+ * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt vectors in
+ *                              iosapic_set_affinity(), initializations for
+ *                              /proc/irq/#/smp_affinity
  */
 /*
  * Here is what the interrupt logic between a PCI device and the CPU looks like:
@@ -63,6 +70,7 @@
 
 
 #undef DEBUG_IRQ_ROUTING
+#undef	OVERRIDE_DEBUG
 
 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
 
@@ -88,7 +96,7 @@
  * Translate IOSAPIC irq number to the corresponding IA-64 interrupt vector.  If no
  * entry exists, return -1.
  */
-static int
+int
 iosapic_irq_to_vector (int irq)
 {
 	int vector;
@@ -121,6 +129,7 @@
 	u32 low32, high32;
 	char *addr;
 	int pin;
+	char redir;
 
 	pin = iosapic_irq[vector].pin;
 	if (pin < 0)
@@ -131,6 +140,11 @@
 	trigger = iosapic_irq[vector].trigger;
 	dmode   = iosapic_irq[vector].dmode;
 
+	redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
+#ifdef CONFIG_SMP
+	set_irq_affinity_info(vector, (int)(dest & 0xffff), redir);
+#endif
+
 	low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 		 (trigger << IOSAPIC_TRIGGER_SHIFT) |
 		 (dmode << IOSAPIC_DELIVERY_SHIFT) |
@@ -211,6 +225,7 @@
 	u32 high32, low32;
 	int dest, pin;
 	char *addr;
+	int redir = (irq & (1<<31)) ? 1 : 0;
 
 	mask &= (1UL << smp_num_cpus) - 1;
 
@@ -225,6 +240,8 @@
 	if (pin < 0)
 		return;			/* not an IOSAPIC interrupt */
 
+	set_irq_affinity_info(irq,dest,redir);
+
 	/* dest contains both id and eid */
 	high32 = dest << IOSAPIC_DEST_SHIFT;
 
@@ -234,9 +251,13 @@
 		writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
 		low32 = readl(addr + IOSAPIC_WINDOW);
 
-		/* change delivery mode to fixed */
 		low32 &= ~(7 << IOSAPIC_DELIVERY_SHIFT);
-		low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
+		if (redir)
+		        /* change delivery mode to lowest priority */
+			low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
+		else
+		        /* change delivery mode to fixed */
+			low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 
 		writel(IOSAPIC_RTE_HIGH(pin), addr + IOSAPIC_REG_SELECT);
 		writel(high32, addr + IOSAPIC_WINDOW);
@@ -343,29 +364,64 @@
 }
 
 /*
- * ACPI can describe IOSAPIC interrupts via static tables and namespace
- * methods.  This provides an interface to register those interrupts and
- * program the IOSAPIC RTE.
+ * if the given vector is already owned by other,
+ *  assign a new vector for the other and make the vector available
  */
-int
-iosapic_register_irq (u32 global_vector, unsigned long polarity, unsigned long
-                      edge_triggered, u32 base_irq, char *iosapic_address)
+static void
+iosapic_reassign_vector (int vector)
+{
+	int new_vector;
+
+	if (iosapic_irq[vector].pin >= 0 || iosapic_irq[vector].addr
+	    || iosapic_irq[vector].base_irq || iosapic_irq[vector].dmode
+	    || iosapic_irq[vector].polarity || iosapic_irq[vector].trigger)
+	{
+		new_vector = ia64_alloc_irq();
+		printk("Reassigning Vector 0x%x to 0x%x\n", vector, new_vector);
+		memcpy (&iosapic_irq[new_vector], &iosapic_irq[vector],
+			sizeof(struct iosapic_irq));
+		memset (&iosapic_irq[vector], 0, sizeof(struct iosapic_irq));
+		iosapic_irq[vector].pin = -1;
+	}
+}
+
+static void
+register_irq (u32 global_vector, int vector, int pin, unsigned char delivery,
+	      unsigned long polarity, unsigned long edge_triggered,
+	      u32 base_irq, char *iosapic_address)
 {
 	irq_desc_t *idesc;
 	struct hw_interrupt_type *irq_type;
-	int vector;
 
-	vector = iosapic_irq_to_vector(global_vector);
-	if (vector < 0)
-		vector = ia64_alloc_irq();
-
-	/* fill in information from this vector's IOSAPIC */
-	iosapic_irq[vector].addr = iosapic_address;
-	iosapic_irq[vector].base_irq = base_irq;
-	iosapic_irq[vector].pin	= global_vector - iosapic_irq[vector].base_irq;
+	iosapic_irq[vector].pin	= pin;
 	iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
-	iosapic_irq[vector].dmode    = IOSAPIC_LOWEST_PRIORITY;
+	iosapic_irq[vector].dmode    = delivery;
 
+	/*
+	 * In override, it does not provide addr/base_irq.  global_vector is enough to
+	 * locate iosapic addr, base_irq and pin by examining base_irq and max_pin of
+	 * registered iosapics (tbd)
+	 */
+#ifndef	OVERRIDE_DEBUG
+	if (iosapic_address) {
+		iosapic_irq[vector].addr = iosapic_address;
+		iosapic_irq[vector].base_irq = base_irq;
+	}
+#else
+	if (iosapic_address) {
+		if (iosapic_irq[vector].addr && (iosapic_irq[vector].addr != iosapic_address))
+			printk("WARN: register_irq: diff IOSAPIC ADDRESS for gv %x, v %x\n",
+			       global_vector, vector);
+		iosapic_irq[vector].addr = iosapic_address;
+		if (iosapic_irq[vector].base_irq && (iosapic_irq[vector].base_irq != base_irq)) {
+			printk("WARN: register_irq: diff BASE IRQ %x for gv %x, v %x\n",
+			       base_irq, global_vector, vector);
+		}
+		iosapic_irq[vector].base_irq = base_irq;
+	} else if (!iosapic_irq[vector].addr)
+		printk("WARN: register_irq: invalid override for gv %x, v %x\n",
+		       global_vector, vector);
+#endif
 	if (edge_triggered) {
 		iosapic_irq[vector].trigger = IOSAPIC_EDGE;
 		irq_type = &irq_type_iosapic_edge;
@@ -377,12 +433,32 @@
 	idesc = irq_desc(vector);
 	if (idesc->handler != irq_type) {
 		if (idesc->handler != &no_irq_type)
-			printk("iosapic_register_irq(): changing vector 0x%02x from"
+			printk("register_irq(): changing vector 0x%02x from "
 			       "%s to %s\n", vector, idesc->handler->typename, irq_type->typename);
 		idesc->handler = irq_type;
 	}
+}
+
+/*
+ * ACPI can describe IOSAPIC interrupts via static tables and namespace
+ * methods.  This provides an interface to register those interrupts and
+ * program the IOSAPIC RTE.
+ */
+int
+iosapic_register_irq (u32 global_vector, unsigned long polarity, unsigned long
+                      edge_triggered, u32 base_irq, char *iosapic_address)
+{
+	int vector;
 
-	printk("IOSAPIC %x(%s,%s) -> Vector %x\n", global_vector,
+	vector = iosapic_irq_to_vector(global_vector);
+	if (vector < 0)
+		vector = ia64_alloc_irq();
+
+	register_irq (global_vector, vector, global_vector - base_irq,
+			IOSAPIC_LOWEST_PRIORITY, polarity, edge_triggered,
+			base_irq, iosapic_address);
+
+	printk("IOSAPIC 0x%x(%s,%s) -> Vector 0x%x\n", global_vector,
 	       (polarity ? "high" : "low"), (edge_triggered ? "edge" : "level"), vector);
 
 	/* program the IOSAPIC routing table */
@@ -395,51 +471,40 @@
  * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
  */
 int
-iosapic_register_platform_irq (u32 int_type, u32 global_vector, u32 iosapic_vector,
-			       u16 eid, u16 id, unsigned long polarity,
+iosapic_register_platform_irq (u32 int_type, u32 global_vector,
+			       u32 iosapic_vector, u16 eid, u16 id, unsigned long polarity,
 			       unsigned long edge_triggered, u32 base_irq, char *iosapic_address)
 {
-	struct hw_interrupt_type *irq_type;
-	irq_desc_t *idesc;
+	unsigned char delivery;
 	int vector;
 
 	switch (int_type) {
-	      case ACPI20_ENTRY_PIS_CPEI:
+	case ACPI20_ENTRY_PIS_PMI:
+		vector = iosapic_vector;
+		/*
+		 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
+		 * we need to make sure the vector is available
+		 */
+		iosapic_reassign_vector(vector);
+		delivery = IOSAPIC_PMI;
+		break;
+	case ACPI20_ENTRY_PIS_CPEI:
 		vector = IA64_PCE_VECTOR;
-		iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
+		delivery = IOSAPIC_LOWEST_PRIORITY;
 		break;
-	      case ACPI20_ENTRY_PIS_INIT:
+	case ACPI20_ENTRY_PIS_INIT:
 		vector = ia64_alloc_irq();
-		iosapic_irq[vector].dmode = IOSAPIC_INIT;
+		delivery = IOSAPIC_INIT;
 		break;
-	      default:
+	default:
 		printk("iosapic_register_platform_irq(): invalid int type\n");
 		return -1;
 	}
 
-	/* fill in information from this vector's IOSAPIC */
-	iosapic_irq[vector].addr = iosapic_address;
-	iosapic_irq[vector].base_irq = base_irq;
-	iosapic_irq[vector].pin	= global_vector - iosapic_irq[vector].base_irq;
-	iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
-
-	if (edge_triggered) {
-		iosapic_irq[vector].trigger = IOSAPIC_EDGE;
-		irq_type = &irq_type_iosapic_edge;
-	} else {
-		iosapic_irq[vector].trigger = IOSAPIC_LEVEL;
-		irq_type = &irq_type_iosapic_level;
-	}
-
-	idesc = irq_desc(vector);
-	if (idesc->handler != irq_type) {
-		if (idesc->handler != &no_irq_type)
-			printk("iosapic_register_platform_irq(): changing vector 0x%02x from"
-			       "%s to %s\n", vector, idesc->handler->typename, irq_type->typename);
-		idesc->handler = irq_type;
-	}
+	register_irq(global_vector, vector, global_vector - base_irq, delivery, polarity,
+		     edge_triggered, base_irq, iosapic_address);
 
-	printk("PLATFORM int %x: IOSAPIC %x(%s,%s) -> Vector %x CPU %.02u:%.02u\n",
+	printk("PLATFORM int 0x%x: IOSAPIC 0x%x(%s,%s) -> Vector 0x%x CPU %.02u:%.02u\n",
 	       int_type, global_vector, (polarity ? "high" : "low"),
 	       (edge_triggered ? "edge" : "level"), vector, eid, id);
 
@@ -450,15 +515,18 @@
 
 
 /*
- * ACPI calls this when it finds an entry for a legacy ISA interrupt.  Note that the
- * irq_base and IOSAPIC address must be set in iosapic_init().
+ * ACPI calls this when it finds an entry for a legacy ISA interrupt.
+ * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
  */
 void
 iosapic_register_legacy_irq (unsigned long irq,
 			     unsigned long pin, unsigned long polarity,
 			     unsigned long edge_triggered)
 {
-	unsigned int vector = isa_irq_to_vector(irq);
+	int vector = isa_irq_to_vector(irq);
+
+	register_irq(irq, vector, (int)pin, IOSAPIC_LOWEST_PRIORITY, polarity, edge_triggered,
+		     0, NULL);		/* ignored for override */
 
 #ifdef DEBUG_IRQ_ROUTING
 	printk("ISA: IRQ %u -> IOSAPIC irq 0x%02x (%s, %s) -> vector %02x\n",
@@ -467,18 +535,14 @@
 	       vector);
 #endif
 
-	iosapic_irq[vector].pin = pin;
-	iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
-	iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
-	iosapic_irq[vector].trigger = edge_triggered ? IOSAPIC_EDGE : IOSAPIC_LEVEL;
+	/* program the IOSAPIC routing table */
+	set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 }
 
 void __init
 iosapic_init (unsigned long phys_addr, unsigned int base_irq, int pcat_compat)
 {
-	struct hw_interrupt_type *irq_type;
-	int i, irq, max_pin, vector;
-	irq_desc_t *idesc;
+	int i, irq, max_pin, vector, pin;
 	unsigned int ver;
 	char *addr;
 	static int first_time = 1;
@@ -496,7 +560,6 @@
 	}
 
 	addr = ioremap(phys_addr, 0);
-
 	ver = iosapic_version(addr);
 	max_pin = (ver >> 16) & 0xff;
 
@@ -511,27 +574,18 @@
 		 */
 		for (irq = 0; irq < 16; ++irq) {
 			vector = isa_irq_to_vector(irq);
-			iosapic_irq[vector].addr = addr;
-			iosapic_irq[vector].base_irq = 0;
-			if (iosapic_irq[vector].pin == -1)
-				iosapic_irq[vector].pin = irq;
-			iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
-			iosapic_irq[vector].trigger  = IOSAPIC_EDGE;
-			iosapic_irq[vector].polarity = IOSAPIC_POL_HIGH;
+			if ((pin = iosapic_irq[vector].pin) == -1)
+				pin = irq;
+
+			register_irq(irq, vector, pin,
+				     /* IOSAPIC_POL_HIGH, IOSAPIC_EDGE */
+				     IOSAPIC_LOWEST_PRIORITY, 1, 1, base_irq, addr);
+
 #ifdef DEBUG_IRQ_ROUTING
 			printk("ISA: IRQ %u -> IOSAPIC irq 0x%02x (high, edge) -> vector 0x%02x\n",
 			       irq, iosapic_irq[vector].base_irq + iosapic_irq[vector].pin,
 			       vector);
 #endif
-			irq_type = &irq_type_iosapic_edge;
-			idesc = irq_desc(vector);
-			if (idesc->handler != irq_type) {
-				if (idesc->handler != &no_irq_type)
-					printk("iosapic_init: changing vector 0x%02x from %s to "
-					       "%s\n", irq, idesc->handler->typename,
-					       irq_type->typename);
-				idesc->handler = irq_type;
-			}
 
 			/* program the IOSAPIC routing table: */
 			set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
@@ -540,7 +594,7 @@
 	for (i = 0; i < pci_irq.num_routes; i++) {
 		irq = pci_irq.route[i].irq;
 
-		if ((unsigned) (irq - base_irq) > max_pin)
+		if ((irq < (int)base_irq) || (irq > (int)(base_irq + max_pin)))
 			/* the interrupt route is for another controller... */
 			continue;
 
@@ -553,29 +607,18 @@
 				vector = ia64_alloc_irq();
 		}
 
-		iosapic_irq[vector].addr     = addr;
-		iosapic_irq[vector].base_irq = base_irq;
-		iosapic_irq[vector].pin	     = (irq - base_irq);
-		iosapic_irq[vector].dmode    = IOSAPIC_LOWEST_PRIORITY;
-		iosapic_irq[vector].trigger  = IOSAPIC_LEVEL;
-		iosapic_irq[vector].polarity = IOSAPIC_POL_LOW;
+		register_irq(irq, vector, irq - base_irq,
+			     /* IOSAPIC_POL_LOW, IOSAPIC_LEVEL */
+			     IOSAPIC_LOWEST_PRIORITY, 0, 0, base_irq, addr);
 
 # ifdef DEBUG_IRQ_ROUTING
 		printk("PCI: (B%d,I%d,P%d) -> IOSAPIC irq 0x%02x -> vector 0x%02x\n",
 		       pci_irq.route[i].bus, pci_irq.route[i].pci_id>>16, pci_irq.route[i].pin,
 		       iosapic_irq[vector].base_irq + iosapic_irq[vector].pin, vector);
 # endif
-		irq_type = &irq_type_iosapic_level;
-		idesc = irq_desc(vector);
-		if (idesc->handler != irq_type){
-			if (idesc->handler != &no_irq_type)
-				printk("iosapic_init: changing vector 0x%02x from %s to %s\n",
-				       vector, idesc->handler->typename, irq_type->typename);
-			idesc->handler = irq_type;
-		}
 
-		/* program the IOSAPIC routing table: */
-		set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
+			/* program the IOSAPIC routing table: */
+			set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 	}
 }
 
@@ -585,6 +628,8 @@
 	struct	pci_dev	*dev;
 	unsigned char pin;
 	int vector;
+	struct hw_interrupt_type *irq_type;
+	irq_desc_t *idesc;
 
 	if (phase != 1)
 		return;
@@ -611,19 +656,28 @@
 				if (vector >= 0)
 					printk(KERN_WARNING
 					       "PCI: using PPB(B%d,I%d,P%d) to get vector %02x\n",
-					       bridge->bus->number, PCI_SLOT(bridge->devfn),
+					       dev->bus->number, PCI_SLOT(dev->devfn),
 					       pin, vector);
 				else
 					printk(KERN_WARNING
-					       "PCI: Couldn't map irq for (B%d,I%d,P%d)o\n",
-					       bridge->bus->number, PCI_SLOT(bridge->devfn),
-					       pin);
+					       "PCI: Couldn't map irq for (B%d,I%d,P%d)\n",
+					       dev->bus->number, PCI_SLOT(dev->devfn), pin);
 			}
 			if (vector >= 0) {
 				printk("PCI->APIC IRQ transform: (B%d,I%d,P%d) -> 0x%02x\n",
 				       dev->bus->number, PCI_SLOT(dev->devfn), pin, vector);
 				dev->irq = vector;
 
+				irq_type = &irq_type_iosapic_level;
+				idesc = irq_desc(vector);
+				if (idesc->handler != irq_type){
+					if (idesc->handler != &no_irq_type)
+						printk("iosapic_pci_fixup: changing vector 0x%02x "
+						       "from %s to %s\n", vector,
+						       idesc->handler->typename,
+						       irq_type->typename);
+					idesc->handler = irq_type;
+				}
 #ifdef CONFIG_SMP
 				/*
 				 * For platforms that do not support interrupt redirect
@@ -638,7 +692,16 @@
 					cpu_index++;
 					if (cpu_index >= smp_num_cpus)
 						cpu_index = 0;
+				} else {
+					/*
+					 * Direct the interrupt vector to the current cpu,
+					 * platform redirection will distribute them.
+					 */
+					set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 				}
+#else
+				/* direct the interrupt vector to the running cpu id */
+				set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 #endif
 			}
 		}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/irq.c linux/arch/ia64/kernel/irq.c
--- linux.orig/arch/ia64/kernel/irq.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/irq.c	2002-08-01 06:42:39.000000000 +0000
@@ -287,10 +287,11 @@
 		 * already executing in one..
 		 */
 		if (!irqs_running())
-			if (local_bh_count() || !spin_is_locked(&global_bh_lock))
+			if (really_local_bh_count() || !spin_is_locked(&global_bh_lock))
 				break;
 
 		/* Duh, we have to loop. Release the lock to avoid deadlocks */
+		smp_mb__before_clear_bit();	/* need barrier before releasing lock... */
 		clear_bit(0,&global_irq_lock);
 
 		for (;;) {
@@ -305,7 +306,7 @@
 				continue;
 			if (global_irq_lock)
 				continue;
-			if (!local_bh_count() && spin_is_locked(&global_bh_lock))
+			if (!really_local_bh_count() && spin_is_locked(&global_bh_lock))
 				continue;
 			if (!test_and_set_bit(0,&global_irq_lock))
 				break;
@@ -378,14 +379,14 @@
 	__save_flags(flags);
 	if (flags & IA64_PSR_I) {
 		__cli();
-		if (!local_irq_count())
+		if (!really_local_irq_count())
 			get_irqlock();
 	}
 #else
 	__save_flags(flags);
 	if (flags & (1 << EFLAGS_IF_SHIFT)) {
 		__cli();
-		if (!local_irq_count())
+		if (!really_local_irq_count())
 			get_irqlock();
 	}
 #endif
@@ -393,7 +394,7 @@
 
 void __global_sti(void)
 {
-	if (!local_irq_count())
+	if (!really_local_irq_count())
 		release_irqlock(smp_processor_id());
 	__sti();
 }
@@ -422,7 +423,7 @@
 	retval = 2 + local_enabled;
 
 	/* check for global flags if we're not in an interrupt */
-	if (!local_irq_count()) {
+	if (!really_local_irq_count()) {
 		if (local_enabled)
 			retval = 1;
 		if (global_irq_holder == cpu)
@@ -529,7 +530,7 @@
 	disable_irq_nosync(irq);
 
 #ifdef CONFIG_SMP
-	if (!local_irq_count()) {
+	if (!really_local_irq_count()) {
 		do {
 			barrier();
 		} while (irq_desc(irq)->status & IRQ_INPROGRESS);
@@ -1009,6 +1010,11 @@
 		rand_initialize_irq(irq);
 	}
 
+	if (new->flags & SA_PERCPU_IRQ) {
+		desc->status |= IRQ_PER_CPU;
+		desc->handler = &irq_type_ia64_lsapic;
+	}
+
 	/*
 	 * The following block of code has to be executed atomically
 	 */
@@ -1089,13 +1095,25 @@
 static struct proc_dir_entry * smp_affinity_entry [NR_IRQS];
 
 static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL };
+static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
+
+void set_irq_affinity_info(int irq, int hwid, int redir)
+{
+	unsigned long mask = 1UL<<cpu_logical_id(hwid);
+
+	if (irq >= 0 && irq < NR_IRQS) {
+		irq_affinity[irq] = mask;
+		irq_redir[irq] = (char) (redir & 0xff);
+	}
+}
 
 static int irq_affinity_read_proc (char *page, char **start, off_t off,
 			int count, int *eof, void *data)
 {
-	if (count < HEX_DIGITS+1)
+	if (count < HEX_DIGITS+3)
 		return -EINVAL;
-	return sprintf (page, "%08lx\n", irq_affinity[(long)data]);
+	return sprintf (page, "%s%08lx\n", irq_redir[(long)data] ? "r " : "",
+			irq_affinity[(long)data]);
 }
 
 static int irq_affinity_write_proc (struct file *file, const char *buffer,
@@ -1103,11 +1121,20 @@
 {
 	int irq = (long) data, full_count = count, err;
 	unsigned long new_value;
+	const char *buf = buffer;
+	int redir;
 
 	if (!irq_desc(irq)->handler->set_affinity)
 		return -EIO;
 
-	err = parse_hex_value(buffer, count, &new_value);
+	if (buf[0] == 'r' || buf[0] == 'R') {
+		++buf;
+		while (*buf == ' ') ++buf;
+		redir = 1;
+	} else
+		redir = 0;
+
+	err = parse_hex_value(buf, count, &new_value);
 
 	/*
 	 * Do not allow disabling IRQs completely - it's a too easy
@@ -1117,8 +1144,7 @@
 	if (!(new_value & cpu_online_map))
 		return -EINVAL;
 
-	irq_affinity[irq] = new_value;
-	irq_desc(irq)->handler->set_affinity(irq, new_value);
+	irq_desc(irq)->handler->set_affinity(irq | (redir?(1<<31):0), new_value);
 
 	return full_count;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/ivt.S linux/arch/ia64/kernel/ivt.S
--- linux.orig/arch/ia64/kernel/ivt.S	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/ivt.S	2002-08-01 06:42:33.000000000 +0000
@@ -275,6 +275,7 @@
 	mov r16=cr.ifa		// get address that caused the TLB miss
 	movl r17=PAGE_KERNEL
 	mov r21=cr.ipsr
+	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
 	mov r31=pr
 	;;
 #ifdef CONFIG_DISABLE_VHPT
@@ -289,12 +290,12 @@
 (p8)	br.cond.dptk itlb_fault
 #endif
 	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
+	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
 	shr.u r18=r16,57	// move address bit 61 to bit 4
-	dep r19=0,r16,IA64_MAX_PHYS_BITS,(64-IA64_MAX_PHYS_BITS)	// clear ed & reserved bits
 	;;
 	andcm r18=0x10,r18	// bit 4=~address-bit(61)
 	cmp.ne p8,p0=r0,r23	// psr.cpl != 0?
-	dep r19=r17,r19,0,12	// insert PTE control bits into r19
+	or r19=r17,r19		// insert PTE control bits into r19
 	;;
 	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
 (p8)	br.cond.spnt page_fault
@@ -312,6 +313,7 @@
 	mov r16=cr.ifa		// get address that caused the TLB miss
 	movl r17=PAGE_KERNEL
 	mov r20=cr.isr
+	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
 	mov r21=cr.ipsr
 	mov r31=pr
 	;;
@@ -328,15 +330,15 @@
 #endif
 	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
 	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
+	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
 	shr.u r18=r16,57	// move address bit 61 to bit 4
-	dep r19=0,r16,IA64_MAX_PHYS_BITS,(64-IA64_MAX_PHYS_BITS) // clear ed & reserved bits
 	;;
 	andcm r18=0x10,r18	// bit 4=~address-bit(61)
 	cmp.ne p8,p0=r0,r23
 (p8)	br.cond.spnt page_fault
 
 	dep r21=-1,r21,IA64_PSR_ED_BIT,1
-	dep r19=r17,r19,0,12	// insert PTE control bits into r19
+	or r19=r19,r17		// insert PTE control bits into r19
 	;;
 	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
 (p6)	mov cr.ipsr=r21
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/mca.c linux/arch/ia64/kernel/mca.c
--- linux.orig/arch/ia64/kernel/mca.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/mca.c	2002-08-01 06:42:43.000000000 +0000
@@ -3,6 +3,9 @@
  * Purpose:	Generic MCA handling layer
  *
  * Updated for latest kernel
+ * Copyright (C) 2002 Intel
+ * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
+ *
  * Copyright (C) 2001 Intel
  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  *
@@ -12,6 +15,11 @@
  * Copyright (C) 1999 Silicon Graphics, Inc.
  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  *
+ * 02/01/04 J. Hall	Aligned MCA stack to 16 bytes, added platform vs. CPU
+ *			error flag, set SAL default return values, changed
+ *			error record structure to linked list, added init call
+ *			to sal_get_state_info_size().
+ *
  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  *                      platform errors, completed code for logging of
  *                      corrected & uncorrected machine check errors, and
@@ -27,6 +35,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/smp_lock.h>
+#include <linux/bootmem.h>
 
 #include <asm/machvec.h>
 #include <asm/page.h>
@@ -50,18 +59,22 @@
 ia64_mca_sal_to_os_state_t	ia64_sal_to_os_handoff_state;
 ia64_mca_os_to_sal_state_t	ia64_os_to_sal_handoff_state;
 u64				ia64_mca_proc_state_dump[512];
-u64				ia64_mca_stack[1024];
+u64				ia64_mca_stack[1024] __attribute__((aligned(16)));
 u64				ia64_mca_stackframe[32];
 u64				ia64_mca_bspstore[1024];
 u64				ia64_init_stack[INIT_TASK_SIZE] __attribute__((aligned(16)));
+u64				ia64_mca_sal_data_area[1356];
+u64				ia64_mca_min_state_save_info;
+u64				ia64_tlb_functional;
+u64				ia64_os_mca_recovery_successful;
 
 static void			ia64_mca_wakeup_ipi_wait(void);
 static void			ia64_mca_wakeup(int cpu);
 static void			ia64_mca_wakeup_all(void);
 static void			ia64_log_init(int);
-extern void		        ia64_monarch_init_handler (void);
-extern void		        ia64_slave_init_handler (void);
-extern struct hw_interrupt_type irq_type_iosapic_level;
+extern void			ia64_monarch_init_handler (void);
+extern void			ia64_slave_init_handler (void);
+extern struct hw_interrupt_type	irq_type_iosapic_level;
 
 static struct irqaction cmci_irqaction = {
 	handler:    ia64_mca_cmc_int_handler,
@@ -95,25 +108,31 @@
  *  memory.
  *
  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE/INIT)
- *  Outputs :   None
+ *  Outputs :   platform error status
  */
-void
+int
 ia64_mca_log_sal_error_record(int sal_info_type)
 {
+	int platform_err = 0;
+
 	/* Get the MCA error record */
 	if (!ia64_log_get(sal_info_type, (prfunc_t)printk))
-		return;                 // no record retrieved
+		return platform_err;                 // no record retrieved
 
-	/* Log the error record */
-	ia64_log_print(sal_info_type, (prfunc_t)printk);
+	/* TODO:
+	 * 1. analyze error logs to determine recoverability
+	 * 2. perform error recovery procedures, if applicable
+	 * 3. set ia64_os_mca_recovery_successful flag, if applicable
+	 */
 
-	/* Clear the CMC SAL logs now that they have been logged */
+	platform_err = ia64_log_print(sal_info_type, (prfunc_t)printk);
 	ia64_sal_clear_state_info(sal_info_type);
+
+	return platform_err;
 }
 
 /*
- * hack for now, add platform dependent handlers
- * here
+ * platform dependent error handling
  */
 #ifndef PLATFORM_MCA_HANDLERS
 void
@@ -275,8 +294,8 @@
 	cmcv_reg_t	cmcv;
 
 	cmcv.cmcv_regval	= 0;
-	cmcv.cmcv_mask      = 0;        /* Unmask/enable interrupt */
-	cmcv.cmcv_vector    = IA64_CMC_VECTOR;
+	cmcv.cmcv_mask		= 0;        /* Unmask/enable interrupt */
+	cmcv.cmcv_vector	= IA64_CMC_VECTOR;
 	ia64_set_cmcv(cmcv.cmcv_regval);
 
 	IA64_MCA_DEBUG("ia64_mca_platform_init: CPU %d corrected "
@@ -374,6 +393,9 @@
 
 	IA64_MCA_DEBUG("ia64_mca_init: begin\n");
 
+	/* initialize recovery success indicator */
+	ia64_os_mca_recovery_successful = 0;
+
 	/* Clear the Rendez checkin flag for all cpus */
 	for(i = 0 ; i < NR_CPUS; i++)
 		ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
@@ -459,7 +481,7 @@
 
 	/*
 	 *  Configure the CMCI vector and handler. Interrupts for CMC are
-	 *  per-processor, so AP CMC interrupts are setup in smp_callin() (smp.c).
+	 *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
 	 */
 	register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
 	ia64_mca_cmc_vector_setup();       /* Setup vector on BSP & enable */
@@ -498,6 +520,9 @@
 	ia64_log_init(SAL_INFO_TYPE_CMC);
 	ia64_log_init(SAL_INFO_TYPE_CPE);
 
+	/* Zero the min state save info */
+	ia64_mca_min_state_save_info = 0;
+
 #if defined(MCA_TEST)
 	mca_test();
 #endif /* #if defined(MCA_TEST) */
@@ -576,7 +601,7 @@
 	int cpu;
 
 	/* Clear the Rendez checkin flag for all cpus */
-	for(cpu = 0 ; cpu < smp_num_cpus; cpu++)
+	for(cpu = 0; cpu < smp_num_cpus; cpu++)
 		if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 			ia64_mca_wakeup(cpu);
 
@@ -668,6 +693,13 @@
 
 	/* Cold Boot for uncorrectable MCA */
 	ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
+
+	/* Default = tell SAL to return to same context */
+	ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
+
+	/* Register pointer to new min state values */
+	/* NOTE: need to do something with this during recovery phase */
+	ia64_os_to_sal_handoff_state.imots_new_min_state = &ia64_mca_min_state_save_info;
 }
 
 /*
@@ -678,10 +710,10 @@
  *	This is the place where the core of OS MCA handling is done.
  *	Right now the logs are extracted and displayed in a well-defined
  *	format. This handler code is supposed to be run only on the
- *	monarch processor. Once the  monarch is done with MCA handling
+ *	monarch processor. Once the monarch is done with MCA handling
  *	further MCA logging is enabled by clearing logs.
  *	Monarch also has the duty of sending wakeup-IPIs to pull the
- *  slave processors out of rendezvous spinloop.
+ *	slave processors out of rendezvous spinloop.
  *
  *  Inputs  :   None
  *  Outputs :   None
@@ -689,20 +721,16 @@
 void
 ia64_mca_ucmc_handler(void)
 {
-#if 0   /* stubbed out @FVL */
-	/*
-	 *  Attempting to log a DBE error Causes "reserved register/field panic"
-	 *  in printk.
-	 */
+	int platform_err = 0;
 
 	/* Get the MCA error record and log it */
-	ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
-#endif  /* stubbed out @FVL */
+	platform_err = ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
 
 	/*
 	 *  Do Platform-specific mca error handling if required.
 	 */
-	mca_handler_platform() ;
+	if (platform_err)
+		mca_handler_platform();
 
 	/*
 	 *  Wakeup all the processors which are spinning in the rendezvous
@@ -749,13 +777,16 @@
 {
 	spinlock_t	isl_lock;
 	int		isl_index;
-	ia64_err_rec_t  isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
+	ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 } ia64_state_log_t;
 
 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 
-/* Note:  Some of these macros assume IA64_MAX_LOGS is always 2.  Should be */
-/* fixed. @FVL                                                              */
+#define IA64_LOG_ALLOCATE(it, size) \
+	{ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
+		(ia64_err_rec_t *)alloc_bootmem(size); \
+	ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
+		(ia64_err_rec_t *)alloc_bootmem(size);}
 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
@@ -765,13 +796,13 @@
     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 #define IA64_LOG_INDEX_DEC(it) \
     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
-#define IA64_LOG_NEXT_BUFFER(it)   (void *)(&(ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
-#define IA64_LOG_CURR_BUFFER(it)   (void *)(&(ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
+#define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
+#define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 
 /*
  * C portion of the OS INIT handler
  *
- * Called from ia64_<monarch/slave>_init_handler
+ * Called from ia64_monarch_init_handler
  *
  * Inputs: pointer to pt_regs where processor info was saved.
  *
@@ -885,10 +916,18 @@
 void
 ia64_log_init(int sal_info_type)
 {
-	IA64_LOG_LOCK_INIT(sal_info_type);
+	u64	max_size = 0;
+
 	IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
-	memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0,
-	       sizeof(ia64_err_rec_t) * IA64_MAX_LOGS);
+	IA64_LOG_LOCK_INIT(sal_info_type);
+
+	// SAL will tell us the maximum size of any error record of this type
+	max_size = ia64_sal_get_state_info_size(sal_info_type);
+
+	// set up OS data structures to hold error info
+	IA64_LOG_ALLOCATE(sal_info_type, max_size);
+	memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
+	memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 }
 
 /*
@@ -923,8 +962,7 @@
 		return total_len;
 	} else {
 		IA64_LOG_UNLOCK(sal_info_type);
-		prfunc("ia64_log_get: Failed to retrieve SAL error record type %d\n",
-		       sal_info_type);
+		prfunc("ia64_log_get: No SAL error record available for type %d\n", sal_info_type);
 		return 0;
 	}
 }
@@ -1268,7 +1306,7 @@
 	}
 
 	if (mdei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)mdei->header.len,
+		platform_mem_dev_err_print((int)mdei->header.len,
 				      (int)sizeof(sal_log_mem_dev_err_info_t) - 1,
 				      &(mdei->oem_data[0]), prfunc);
 	}
@@ -1357,7 +1395,7 @@
 		prfunc("\n");
 
 	if (pbei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)pbei->header.len,
+		platform_pci_bus_err_print((int)pbei->header.len,
 				      (int)sizeof(sal_log_pci_bus_err_info_t) - 1,
 				      &(pbei->oem_data[0]), prfunc);
 	}
@@ -1456,7 +1494,7 @@
 		}
 	}
 	if (pcei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)pcei->header.len, n_pci_data,
+		platform_pci_comp_err_print((int)pcei->header.len, n_pci_data,
 				      p_oem_data, prfunc);
 		prfunc("\n");
 	}
@@ -1485,7 +1523,7 @@
 		ia64_log_prt_guid(&psei->guid, prfunc);
 	}
 	if (psei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)psei->header.len,
+		platform_plat_specific_err_print((int)psei->header.len,
 				      (int)sizeof(sal_log_plat_specific_err_info_t) - 1,
 				      &(psei->oem_data[0]), prfunc);
 	}
@@ -1519,7 +1557,7 @@
 	if (hcei->valid.bus_spec_data)
 		prfunc(" Bus Specific Data: %#lx", hcei->bus_spec_data);
 	if (hcei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)hcei->header.len,
+		platform_host_ctlr_err_print((int)hcei->header.len,
 				      (int)sizeof(sal_log_host_ctlr_err_info_t) - 1,
 				      &(hcei->oem_data[0]), prfunc);
 	}
@@ -1553,7 +1591,7 @@
 	if (pbei->valid.bus_spec_data)
 		prfunc(" Bus Specific Data: %#lx", pbei->bus_spec_data);
 	if (pbei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)pbei->header.len,
+		platform_plat_bus_err_print((int)pbei->header.len,
 				      (int)sizeof(sal_log_plat_bus_err_info_t) - 1,
 				      &(pbei->oem_data[0]), prfunc);
 	}
@@ -1745,17 +1783,18 @@
  *  Inputs  :   lh      (Pointer to the sal error record header with format
  *                       specified by the SAL spec).
  *              prfunc  (fn ptr of log output function to use)
- *  Outputs :   None
+ *  Outputs :	platform error status
  */
-void
+int
 ia64_log_platform_info_print (sal_log_record_header_t *lh, prfunc_t prfunc)
 {
-	sal_log_section_hdr_t       *slsh;
-	int                         n_sects;
-	int                         ercd_pos;
+	sal_log_section_hdr_t	*slsh;
+	int			n_sects;
+	int			ercd_pos;
+	int			platform_err = 0;
 
 	if (!lh)
-		return;
+		return platform_err;
 
 #ifdef MCA_PRT_XTRA_DATA    // for test only @FVL
 	ia64_log_prt_record_header(lh, prfunc);
@@ -1765,7 +1804,7 @@
 		IA64_MCA_DEBUG("ia64_mca_log_print: "
 			       "truncated SAL error record. len = %d\n",
 			       lh->len);
-		return;
+		return platform_err;
 	}
 
 	/* Print record header info */
@@ -1796,35 +1835,43 @@
 			ia64_log_proc_dev_err_info_print((sal_log_processor_info_t *)slsh,
 							 prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_MEM_DEV_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Memory Device Error Info Section\n");
 			ia64_log_mem_dev_err_info_print((sal_log_mem_dev_err_info_t *)slsh,
 							prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_SEL_DEV_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform SEL Device Error Info Section\n");
 			ia64_log_sel_dev_err_info_print((sal_log_sel_dev_err_info_t *)slsh,
 							prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_PCI_BUS_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform PCI Bus Error Info Section\n");
 			ia64_log_pci_bus_err_info_print((sal_log_pci_bus_err_info_t *)slsh,
 							prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform SMBIOS Device Error Info Section\n");
 			ia64_log_smbios_dev_err_info_print((sal_log_smbios_dev_err_info_t *)slsh,
 							   prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_PCI_COMP_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform PCI Component Error Info Section\n");
 			ia64_log_pci_comp_err_info_print((sal_log_pci_comp_err_info_t *)slsh,
 							 prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_SPECIFIC_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Specific Error Info Section\n");
 			ia64_log_plat_specific_err_info_print((sal_log_plat_specific_err_info_t *)
 							      slsh,
 							      prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_HOST_CTLR_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Host Controller Error Info Section\n");
 			ia64_log_host_ctlr_err_info_print((sal_log_host_ctlr_err_info_t *)slsh,
 							  prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_BUS_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Bus Error Info Section\n");
 			ia64_log_plat_bus_err_info_print((sal_log_plat_bus_err_info_t *)slsh,
 							 prfunc);
@@ -1838,8 +1885,9 @@
 		       n_sects, lh->len);
 	if (!n_sects) {
 		prfunc("No Platform Error Info Sections found\n");
-		return;
+		return platform_err;
 	}
+	return platform_err;
 }
 
 /*
@@ -1849,15 +1897,17 @@
  *
  *  Inputs   :  info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
  *              prfunc      (fn ptr of log output function to use)
- * Outputs	:	None
+ * Outputs	:	platform error status
  */
-void
+int
 ia64_log_print(int sal_info_type, prfunc_t prfunc)
 {
+	int platform_err = 0;
+
 	switch(sal_info_type) {
 	      case SAL_INFO_TYPE_MCA:
 		prfunc("+BEGIN HARDWARE ERROR STATE AT MCA\n");
-		ia64_log_platform_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc);
+		platform_err = ia64_log_platform_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc);
 		prfunc("+END HARDWARE ERROR STATE AT MCA\n");
 		break;
 	      case SAL_INFO_TYPE_INIT:
@@ -1877,4 +1927,5 @@
 		prfunc("+MCA UNKNOWN ERROR LOG (UNIMPLEMENTED)\n");
 		break;
 	}
+	return platform_err;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/mca_asm.S linux/arch/ia64/kernel/mca_asm.S
--- linux.orig/arch/ia64/kernel/mca_asm.S	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/mca_asm.S	2002-08-01 06:42:38.000000000 +0000
@@ -7,6 +7,12 @@
 // 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
 //		   kstack, switch modes, jump to C INIT handler
 //
+// 02/01/04 J.Hall <jenna.s.hall@intel.com>
+//		   Before entering virtual mode code:
+//		   1. Check for TLB CPU error
+//		   2. Restore current thread pointer to kr6
+//		   3. Move stack ptr 16 bytes to conform to C calling convention
+//
 #include <linux/config.h>
 
 #include <asm/asmmacro.h>
@@ -21,10 +27,21 @@
  */
 #define	MINSTATE_PHYS	/* Make sure stack access is physical for MINSTATE */
 
+/*
+ * Needed for ia64_sal call
+ */
+#define SAL_GET_STATE_INFO      0x01000001
+
+/*
+ * Needed for return context to SAL
+ */
+#define IA64_MCA_SAME_CONTEXT	0x0
+#define IA64_MCA_COLD_BOOT	-2
+
 #include "minstate.h"
 
 /*
- *  SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
+ * SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
  *		1. GR1 = OS GP
  *		2. GR8 = PAL_PROC physical address
  *		3. GR9 = SAL_PROC physical address
@@ -40,26 +57,34 @@
 	st8	[_tmp]=r9,0x08;;			\
 	st8	[_tmp]=r10,0x08;;			\
 	st8	[_tmp]=r11,0x08;;			\
-	st8	[_tmp]=r12,0x08;;
+	st8	[_tmp]=r12,0x08
 
 /*
- *  OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
- *      1. GR8 = OS_MCA return status
+ * OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
+ * (p6) is executed if we never entered virtual mode (TLB error)
+ * (p7) is executed if we entered virtual mode as expected (normal case)
+ *	1. GR8 = OS_MCA return status
  *	2. GR9 = SAL GP (physical)
- *      3. GR10 = 0/1 returning same/new context
- *      4. GR22 = New min state save area pointer
- *      returns ptr to SAL rtn save loc in _tmp
+ *	3. GR10 = 0/1 returning same/new context
+ *	4. GR22 = New min state save area pointer
+ *	returns ptr to SAL rtn save loc in _tmp
  */
-#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp)				\
-	movl	_tmp=ia64_os_to_sal_handoff_state;;				\
-	DATA_VA_TO_PA(_tmp);;							\
-	ld8	r8=[_tmp],0x08;;						\
-	ld8	r9=[_tmp],0x08;;						\
-	ld8     r10=[_tmp],0x08;;						\
-	ld8     r22=[_tmp],0x08;;						\
-	movl    _tmp=ia64_sal_to_os_handoff_state;;				\
-	DATA_VA_TO_PA(_tmp);;							\
-	add     _tmp=0x28,_tmp;;            // point to SAL rtn save location
+#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp)	\
+(p6)	movl	_tmp=ia64_sal_to_os_handoff_state;;	\
+(p7)	movl	_tmp=ia64_os_to_sal_handoff_state;;	\
+	DATA_VA_TO_PA(_tmp);;				\
+(p6)	movl	r8=IA64_MCA_COLD_BOOT;			\
+(p6)	movl	r10=IA64_MCA_SAME_CONTEXT;		\
+(p6)	add     _tmp=0x18,_tmp;;			\
+(p6)	ld8	r9=[_tmp],0x10;				\
+(p6)	movl	r22=ia64_mca_min_state_save_info;;	\
+(p7)	ld8	r8=[_tmp],0x08;;			\
+(p7)	ld8	r9=[_tmp],0x08;;			\
+(p7)	ld8     r10=[_tmp],0x08;;			\
+(p7)	ld8     r22=[_tmp],0x08;;			\
+	DATA_VA_TO_PA(r22)
+	// now _tmp is pointing to SAL rtn save location
+
 
 	.global ia64_os_mca_dispatch
 	.global ia64_os_mca_dispatch_end
@@ -70,6 +95,9 @@
 	.global	ia64_mca_stackframe
 	.global	ia64_mca_bspstore
 	.global ia64_init_stack
+	.global ia64_mca_sal_data_area
+	.global ia64_tlb_functional
+	.global ia64_mca_min_state_save_info
 
 	.text
 	.align 16
@@ -90,26 +118,34 @@
 	//	  for ia64_mca_sal_to_os_state_t has been
 	//	  defined in include/asm/mca.h
 	SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
+	;;
 
 	// LOG PROCESSOR STATE INFO FROM HERE ON..
-	;;
 begin_os_mca_dump:
 	br	ia64_os_mca_proc_state_dump;;
 
 ia64_os_mca_done_dump:
 
 	// Setup new stack frame for OS_MCA handling
-	movl    r2=ia64_mca_bspstore;;      // local bspstore area location in r2
+	movl	r2=ia64_mca_bspstore;;	// local bspstore area location in r2
 	DATA_VA_TO_PA(r2);;
-	movl    r3=ia64_mca_stackframe;;    // save stack frame to memory in r3
+	movl	r3=ia64_mca_stackframe;; // save stack frame to memory in r3
 	DATA_VA_TO_PA(r3);;
-	rse_switch_context(r6,r3,r2);;                  // RSC management in this new context
-	movl        r12=ia64_mca_stack;;
-	mov     r2=8*1024;;                 // stack size must be same as c array
-	add     r12=r2,r12;;                // stack base @ bottom of array
+	rse_switch_context(r6,r3,r2);;	// RSC management in this new context
+	movl	r12=ia64_mca_stack
+	mov	r2=8*1024;;		// stack size must be same as C array
+	add	r12=r2,r12;;		// stack base @ bottom of array
+	adds	r12=-16,r12;;		// allow 16 bytes of scratch
+					// (C calling convention)
 	DATA_VA_TO_PA(r12);;
 
-	// Enter virtual mode from physical mode
+	// Check to see if the MCA resulted from a TLB error
+begin_tlb_error_check:
+        br      ia64_os_mca_tlb_error_check;;
+
+done_tlb_error_check:
+
+        // If TLB is functional, enter virtual mode from physical mode
 	VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
 ia64_os_mca_virtual_begin:
 
@@ -130,25 +166,28 @@
 #endif	/* #if defined(MCA_TEST) */
 
 	// restore the original stack frame here
-	movl    r2=ia64_mca_stackframe               // restore stack frame from memory at r2
+	movl    r2=ia64_mca_stackframe	// restore stack frame from memory at r2
 	;;
 	DATA_VA_TO_PA(r2)
 	movl    r4=IA64_PSR_MC
 	;;
-	rse_return_context(r4,r3,r2)                 // switch from interrupt context for RSE
+	rse_return_context(r4,r3,r2)	// switch from interrupt context for RSE
 
 	// let us restore all the registers from our PSI structure
-	mov		r8=gp
+	mov	r8=gp
 	;;
 begin_os_mca_restore:
 	br	ia64_os_mca_proc_state_restore;;
 
 ia64_os_mca_done_restore:
-	;;
+	movl	r3=ia64_tlb_functional;;
+	DATA_VA_TO_PA(r3);;
+	ld8	r3=[r3];;
+	cmp.eq	p6,p7=r0,r3;;
+	OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2);;
 	// branch back to SALE_CHECK
-	OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2)
 	ld8		r3=[r2];;
-	mov		b0=r3;;			      // SAL_CHECK return address
+	mov		b0=r3;;		// SAL_CHECK return address
 	br		b0
 	;;
 ia64_os_mca_dispatch_end:
@@ -405,7 +444,7 @@
 	movl		r2=ia64_mca_proc_state_dump	// Convert virtual address
 	;;						// of OS state dump area
 	DATA_VA_TO_PA(r2)				// to physical address
-	;;
+
 restore_GRs:                                    // restore bank-1 GRs 16-31
 	bsw.1;;
 	add		r3=16*8,r2;;                // to get to NaT of GR 16-31
@@ -621,6 +660,80 @@
 
 //EndStub//////////////////////////////////////////////////////////////////////
 
+//++
+// Name:
+//	ia64_os_mca_tlb_error_check()
+//
+// Stub Description:
+//
+//	This stub checks to see if the MCA resulted from a TLB error
+//
+//--
+
+ia64_os_mca_tlb_error_check:
+
+	// Retrieve sal data structure for uncorrected MCA
+
+	// Make the ia64_sal_get_state_info() call
+	movl	r4=ia64_mca_sal_data_area;;
+	movl	r7=ia64_sal;;
+	mov	r6=r1			// save gp
+	DATA_VA_TO_PA(r4)		// convert to physical address
+	DATA_VA_TO_PA(r7);;		// convert to physical address
+	ld8	r7=[r7]			// get addr of pdesc from ia64_sal
+	movl	r3=SAL_GET_STATE_INFO;;
+	DATA_VA_TO_PA(r7);;		// convert to physical address
+	ld8	r8=[r7],8;;		// get pdesc function pointer
+	DATA_VA_TO_PA(r8)		// convert to physical address
+	ld8	r1=[r7];;		// set new (ia64_sal) gp
+	DATA_VA_TO_PA(r1)		// convert to physical address
+	mov	b6=r8
+
+	alloc	r5=ar.pfs,8,0,8,0;;	// allocate stack frame for SAL call
+	mov	out0=r3			// which SAL proc to call
+	mov	out1=r0			// error type == MCA
+	mov	out2=r0			// null arg
+	mov	out3=r4			// data copy area
+	mov	out4=r0			// null arg
+	mov	out5=r0			// null arg
+	mov	out6=r0			// null arg
+	mov	out7=r0;;		// null arg
+
+	br.call.sptk.few	b0=b6;;
+
+	mov	r1=r6			// restore gp
+	mov	ar.pfs=r5;;		// restore ar.pfs
+
+	movl	r6=ia64_tlb_functional;;
+	DATA_VA_TO_PA(r6)		// needed later
+
+	cmp.eq	p6,p7=r0,r8;;		// check SAL call return address
+(p7)	st8	[r6]=r0			// clear tlb_functional flag
+(p7)    br	tlb_failure		// error; return to SAL
+
+	// examine processor error log for type of error
+	add	r4=40+24,r4;;		// parse past record header (length=40)
+					// and section header (length=24)
+	ld4	r4=[r4]			// get valid field of processor log
+	mov	r5=0xf00;;
+	and	r5=r4,r5;;		// read bits 8-11 of valid field
+					// to determine if we have a TLB error
+	movl	r3=0x1
+	cmp.eq	p6,p7=r0,r5;;
+	// if no TLB failure, set tlb_functional flag
+(p6)	st8	[r6]=r3
+	// else clear flag
+(p7)	st8	[r6]=r0
+
+	// if no TLB failure, continue with normal virtual mode logging
+(p6)    br	done_tlb_error_check
+	// else no point in entering virtual mode for logging
+tlb_failure:
+	br      ia64_os_mca_virtual_end
+
+//EndStub//////////////////////////////////////////////////////////////////////
+
+
 // ok, the issue here is that we need to save state information so
 // it can be useable by the kernel debugger and show regs routines.
 // In order to do this, our best bet is save the current state (plus
@@ -633,7 +746,7 @@
 // This has been defined for registration purposes with SAL
 // as a part of ia64_mca_init.
 //
-// When we get here, the follow registers have been
+// When we get here, the following registers have been
 // set by the SAL for our use
 //
 //		1. GR1 = OS INIT GP
@@ -649,42 +762,10 @@
 
 
 GLOBAL_ENTRY(ia64_monarch_init_handler)
-#if defined(CONFIG_SMP) && defined(SAL_MPINIT_WORKAROUND)
-	//
-	// work around SAL bug that sends all processors to monarch entry
-	//
-	mov	r17=cr.lid
-	// XXX fix me: this is wrong: hard_smp_processor_id() is a pair of lid/eid
-	movl	r18=ia64_cpu_to_sapicid
-	;;
-	dep	r18=0,r18,61,3		// convert to physical address
-	;;
-	shr.u	r17=r17,16
-	ld4	r18=[r18]		// get the BSP ID
-	;;
-	dep	r17=0,r17,16,48
-	;;
-	cmp4.ne	p6,p0=r17,r18		// Am I the BSP ?
-(p6)	br.cond.spnt slave_init_spin_me
-	;;
-#endif
-
 
-//
-// ok, the first thing we do is stash the information
-// the SAL passed to os
-//
-_tmp = r2
-	movl	_tmp=ia64_sal_to_os_handoff_state
-	;;
-	dep	_tmp=0,_tmp, 61, 3	// get physical address
+	// stash the information the SAL passed to os
+	SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
 	;;
-	st8	[_tmp]=r1,0x08;;
-	st8	[_tmp]=r8,0x08;;
-	st8	[_tmp]=r9,0x08;;
-	st8	[_tmp]=r10,0x08;;
-	st8	[_tmp]=r11,0x08;;
-	st8	[_tmp]=r12,0x08;;
 
 // now we want to save information so we can dump registers
 	SAVE_MIN_WITH_COVER
@@ -695,12 +776,10 @@
 	;;
 	SAVE_REST
 
-// ok, enough should be saved at this point to be dangerous, and  supply
+// ok, enough should be saved at this point to be dangerous, and supply
 // information for a dump
 // We need to switch to Virtual mode before hitting the C functions.
-//
-//
-//
+
 	movl	r2=IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN
 	mov	r3=psr	// get the current psr, minimum enabled at this point
 	;;
@@ -708,8 +787,8 @@
 	;;
 	movl	r3=IVirtual_Switch
 	;;
-	mov	cr.iip=r3		// short return to set the appropriate bits
-	mov	cr.ipsr=r2		// need to do an rfi to set appropriate bits
+	mov	cr.iip=r3	// short return to set the appropriate bits
+	mov	cr.ipsr=r2	// need to do an rfi to set appropriate bits
 	;;
 	rfi
 	;;
@@ -717,7 +796,7 @@
 	//
 	// We should now be running virtual
 	//
-	// Lets call the C handler to get the rest of the state info
+	// Let's call the C handler to get the rest of the state info
 	//
 	alloc r14=ar.pfs,0,0,1,0		// now it's safe (must be first in insn group!)
 	;;					//
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/palinfo.c linux/arch/ia64/kernel/palinfo.c
--- linux.orig/arch/ia64/kernel/palinfo.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/palinfo.c	2002-08-01 06:42:28.000000000 +0000
@@ -724,7 +724,7 @@
 
 		status = ia64_pal_tr_read(j, i, tr_buffer, &tr_valid);
 		if (status != 0) {
-			printk(__FUNCTION__ " pal call failed on tr[%d:%d]=%ld\n", i, j, status);
+			printk("palinfo: pal call failed on tr[%d:%d]=%ld\n", i, j, status);
 			continue;
 		}
 
@@ -842,9 +842,8 @@
 palinfo_smp_call(void *info)
 {
 	palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
-	/* printk(__FUNCTION__" called on CPU %d\n", smp_processor_id());*/
 	if (data == NULL) {
-		printk(KERN_ERR __FUNCTION__" data pointer is NULL\n");
+		printk("%s palinfo: data pointer is NULL\n", KERN_ERR);
 		data->ret = 0; /* no output */
 		return;
 	}
@@ -868,11 +867,10 @@
 	ptr.page = page;
 	ptr.ret  = 0; /* just in case */
 
-	/*printk(__FUNCTION__" calling CPU %d from CPU %d for function %d\n", f->req_cpu,smp_processor_id(), f->func_id);*/
 
 	/* will send IPI to other CPU and wait for completion of remote call */
 	if ((ret=smp_call_function_single(f->req_cpu, palinfo_smp_call, &ptr, 0, 1))) {
-		printk(__FUNCTION__" remote CPU call from %d to %d on function %d: error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
+		printk("palinfo: remote CPU call from %d to %d on function %d: error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
 		return 0;
 	}
 	return ptr.ret;
@@ -881,7 +879,7 @@
 static
 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
 {
-	printk(__FUNCTION__" should not be called with non SMP kernel\n");
+	printk("palinfo: should not be called with non SMP kernel\n");
 	return 0;
 }
 #endif /* CONFIG_SMP */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/perfmon.c linux/arch/ia64/kernel/perfmon.c
--- linux.orig/arch/ia64/kernel/perfmon.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/perfmon.c	2002-08-01 06:42:40.000000000 +0000
@@ -1,13 +1,16 @@
 /*
- * This file contains the code to configure and read/write the ia64 performance
- * monitoring stuff.
+ * This file implements the perfmon subsystem which is used
+ * to program the IA-64 Performance Monitoring Unit (PMU).
  *
  * Originaly Written by Ganesh Venkitachalam, IBM Corp.
- * Modifications by David Mosberger-Tang, Hewlett-Packard Co.
- * Modifications by Stephane Eranian, Hewlett-Packard Co.
  * Copyright (C) 1999 Ganesh Venkitachalam <venkitac@us.ibm.com>
- * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 2000-2001 Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * Modifications by Stephane Eranian, Hewlett-Packard Co.
+ * Modifications by David Mosberger-Tang, Hewlett-Packard Co.
+ *
+ * Copyright (C) 1999-2002  Hewlett Packard Co
+ *               Stephane Eranian <eranian@hpl.hp.com>
+ *               David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/config.h>
@@ -22,151 +25,137 @@
 #include <linux/mm.h>
 
 #include <asm/bitops.h>
-#include <asm/efi.h>
 #include <asm/errno.h>
-#include <asm/hw_irq.h>
 #include <asm/page.h>
 #include <asm/pal.h>
 #include <asm/perfmon.h>
-#include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/signal.h>
 #include <asm/system.h>
-#include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/delay.h> /* for ia64_get_itc() */
 
 #ifdef CONFIG_PERFMON
 
-#define PFM_VERSION		"0.3"
-#define PFM_SMPL_HDR_VERSION	1
-
-#define PMU_FIRST_COUNTER	4	/* first generic counter */
-
-#define PFM_WRITE_PMCS		0xa0
-#define PFM_WRITE_PMDS		0xa1
-#define PFM_READ_PMDS		0xa2
-#define PFM_STOP		0xa3
-#define PFM_START		0xa4
-#define PFM_ENABLE		0xa5	/* unfreeze only */
-#define PFM_DISABLE		0xa6	/* freeze only */
-#define PFM_RESTART		0xcf
-#define PFM_CREATE_CONTEXT	0xa7
-#define PFM_DESTROY_CONTEXT	0xa8
 /*
- * Those 2 are just meant for debugging. I considered using sysctl() for
- * that but it is a little bit too pervasive. This solution is at least
- * self-contained.
+ * For PMUs which rely on the debug registers for some features, you must
+ * you must enable the following flag to activate the support for
+ * accessing the registers via the perfmonctl() interface.
  */
-#define PFM_DEBUG_ON		0xe0
-#define PFM_DEBUG_OFF		0xe1
-
-#define PFM_DEBUG_BASE		PFM_DEBUG_ON
-
+#ifdef CONFIG_ITANIUM
+#define PFM_PMU_USES_DBR	1
+#endif
 
 /*
- * perfmon API flags
+ * perfmon context states
  */
-#define PFM_FL_INHERIT_NONE	 0x00	/* never inherit a context across fork (default) */
-#define PFM_FL_INHERIT_ONCE	 0x01	/* clone pfm_context only once across fork() */
-#define PFM_FL_INHERIT_ALL	 0x02	/* always clone pfm_context across fork() */
-#define PFM_FL_SMPL_OVFL_NOBLOCK 0x04	/* do not block on sampling buffer overflow */
-#define PFM_FL_SYSTEM_WIDE	 0x08	/* create a system wide context */
-#define PFM_FL_EXCL_INTR	 0x10	/* exclude interrupt from system wide monitoring */
+#define PFM_CTX_DISABLED	0
+#define PFM_CTX_ENABLED		1
 
 /*
- * PMC API flags
+ * Reset register flags
  */
-#define PFM_REGFL_OVFL_NOTIFY	1		/* send notification on overflow */
+#define PFM_RELOAD_LONG_RESET	1
+#define PFM_RELOAD_SHORT_RESET	2
 
 /*
- * Private flags and masks
+ * Misc macros and definitions
  */
+#define PMU_FIRST_COUNTER	4
+
+#define PFM_IS_DISABLED() pmu_conf.pfm_is_disabled
+
+#define PMC_OVFL_NOTIFY(ctx, i)	((ctx)->ctx_soft_pmds[i].flags &  PFM_REGFL_OVFL_NOTIFY)
 #define PFM_FL_INHERIT_MASK	(PFM_FL_INHERIT_NONE|PFM_FL_INHERIT_ONCE|PFM_FL_INHERIT_ALL)
 
-#ifdef CONFIG_SMP
-#define cpu_is_online(i) (cpu_online_map & (1UL << i))
-#else
-#define cpu_is_online(i)	1
-#endif
+#define PMC_IS_IMPL(i)	  (i<pmu_conf.num_pmcs && pmu_conf.impl_regs[i>>6] & (1UL<< (i) %64))
+#define PMD_IS_IMPL(i)	  (i<pmu_conf.num_pmds &&  pmu_conf.impl_regs[4+(i>>6)] & (1UL<<(i) % 64))
+
+#define PMD_IS_COUNTING(i) (i >=0  && i < 256 && pmu_conf.counter_pmds[i>>6] & (1UL <<(i) % 64))
+#define PMC_IS_COUNTING(i) PMD_IS_COUNTING(i)
+
+#define IBR_IS_IMPL(k)	  (k<pmu_conf.num_ibrs)
+#define DBR_IS_IMPL(k)	  (k<pmu_conf.num_dbrs)
+
+#define PMC_IS_BTB(a)	  (((pfm_monitor_t *)(a))->pmc_es == PMU_BTB_EVENT)
+
+#define LSHIFT(x)		(1UL<<(x))
+#define PMM(x)			LSHIFT(x)
+#define PMC_IS_MONITOR(c)	((pmu_conf.monitor_pmcs[0] & PMM((c))) != 0)
+
+#define CTX_IS_ENABLED(c) 	((c)->ctx_flags.state == PFM_CTX_ENABLED)
+#define CTX_OVFL_NOBLOCK(c)	((c)->ctx_fl_block == 0)
+#define CTX_INHERIT_MODE(c)	((c)->ctx_fl_inherit)
+#define CTX_HAS_SMPL(c)		((c)->ctx_psb != NULL)
+#define CTX_USED_PMD(ctx,n) 	(ctx)->ctx_used_pmds[(n)>>6] |= 1UL<< ((n) % 64)
+
+#define CTX_USED_IBR(ctx,n) 	(ctx)->ctx_used_ibrs[(n)>>6] |= 1UL<< ((n) % 64)
+#define CTX_USED_DBR(ctx,n) 	(ctx)->ctx_used_dbrs[(n)>>6] |= 1UL<< ((n) % 64)
+#define CTX_USES_DBREGS(ctx)	(((pfm_context_t *)(ctx))->ctx_fl_using_dbreg==1)
+
+#define LOCK_CTX(ctx)	spin_lock(&(ctx)->ctx_lock)
+#define UNLOCK_CTX(ctx)	spin_unlock(&(ctx)->ctx_lock)
+
+#define SET_PMU_OWNER(t)    do { pmu_owners[smp_processor_id()].owner = (t); } while(0)
+#define PMU_OWNER()	    pmu_owners[smp_processor_id()].owner
+
+#define LOCK_PFS()	    spin_lock(&pfm_sessions.pfs_lock)
+#define UNLOCK_PFS()	    spin_unlock(&pfm_sessions.pfs_lock)
+
+#define PFM_REG_RETFLAG_SET(flags, val)	do { flags &= ~PFM_REG_RETFL_MASK; flags |= (val); } while(0)
+
+/*
+ * debugging
+ */
+#define DBprintk(a) \
+	do { \
+		if (pfm_debug_mode >0) { printk("%s.%d: CPU%d ", __FUNCTION__, __LINE__, smp_processor_id()); printk a; } \
+	} while (0)
 
-#define PMC_IS_IMPL(i)		(i < pmu_conf.num_pmcs && pmu_conf.impl_regs[i>>6] & (1<< (i&~(64-1))))
-#define PMD_IS_IMPL(i)		(i < pmu_conf.num_pmds &&  pmu_conf.impl_regs[4+(i>>6)] & (1<< (i&~(64-1))))
-#define PMD_IS_COUNTER(i)	(i>=PMU_FIRST_COUNTER && i < (PMU_FIRST_COUNTER+pmu_conf.max_counters))
-#define PMC_IS_COUNTER(i)	(i>=PMU_FIRST_COUNTER && i < (PMU_FIRST_COUNTER+pmu_conf.max_counters))
 
-/* This is the Itanium-specific PMC layout for counter config */
+/* 
+ * These are some helpful architected PMC and IBR/DBR register layouts
+ */
 typedef struct {
 	unsigned long pmc_plm:4;	/* privilege level mask */
 	unsigned long pmc_ev:1;		/* external visibility */
 	unsigned long pmc_oi:1;		/* overflow interrupt */
 	unsigned long pmc_pm:1;		/* privileged monitor */
 	unsigned long pmc_ig1:1;	/* reserved */
-	unsigned long pmc_es:7;		/* event select */
-	unsigned long pmc_ig2:1;	/* reserved */
-	unsigned long pmc_umask:4;	/* unit mask */
-	unsigned long pmc_thres:3;	/* threshold */
-	unsigned long pmc_ig3:1;	/* reserved (missing from table on p6-17) */
-	unsigned long pmc_ism:2;	/* instruction set mask */
-	unsigned long pmc_ig4:38;	/* reserved */
-} pmc_counter_reg_t;
-
-/* test for EAR/BTB configuration */
-#define PMU_DEAR_EVENT	0x67
-#define PMU_IEAR_EVENT	0x23
-#define PMU_BTB_EVENT	0x11
-
-#define PMC_IS_DEAR(a)		(((pmc_counter_reg_t *)(a))->pmc_es == PMU_DEAR_EVENT)
-#define PMC_IS_IEAR(a)		(((pmc_counter_reg_t *)(a))->pmc_es == PMU_IEAR_EVENT)
-#define PMC_IS_BTB(a)		(((pmc_counter_reg_t *)(a))->pmc_es == PMU_BTB_EVENT)
-
-/*
- * This header is at the beginning of the sampling buffer returned to the user.
- * It is exported as Read-Only at this point. It is directly followed with the
- * first record.
- */
-typedef struct {
-	int		hdr_version;		/* could be used to differentiate formats */
-	int		hdr_reserved;
-	unsigned long	hdr_entry_size;		/* size of one entry in bytes */
-	unsigned long	hdr_count;		/* how many valid entries */
-	unsigned long	hdr_pmds;		/* which pmds are recorded */
-} perfmon_smpl_hdr_t;
-
-/*
- * Header entry in the buffer as a header as follows.
- * The header is directly followed with the PMDS to saved in increasing index order:
- * PMD4, PMD5, .... How many PMDs are present is determined by the tool which must
- * keep track of it when generating the final trace file.
- */
-typedef struct {
-	int		pid;		/* identification of process */
-	int		cpu;		/* which cpu was used */
-	unsigned long	rate;		/* initial value of this counter */
-	unsigned long	stamp;		/* timestamp */
-	unsigned long	ip;		/* where did the overflow interrupt happened */
-	unsigned long	regs;		/* which registers overflowed (up to 64)*/
-} perfmon_smpl_entry_t;
+	unsigned long pmc_es:8;		/* event select */
+	unsigned long pmc_ig2:48;	/* reserved */
+} pfm_monitor_t;
 
 /*
  * There is one such data structure per perfmon context. It is used to describe the
- * sampling buffer. It is to be shared among siblings whereas the pfm_context isn't.
+ * sampling buffer. It is to be shared among siblings whereas the pfm_context 
+ * is not.
  * Therefore we maintain a refcnt which is incremented on fork().
- * This buffer is private to the kernel only the actual sampling buffer including its
- * header are exposed to the user. This construct allows us to export the buffer read-write,
- * if needed, without worrying about security problems.
- */
-typedef struct {
-	atomic_t		psb_refcnt;	/* how many users for the buffer */
-	int			reserved;
+ * This buffer is private to the kernel only the actual sampling buffer 
+ * including its header are exposed to the user. This construct allows us to 
+ * export the buffer read-write, if needed, without worrying about security 
+ * problems.
+ */
+typedef struct _pfm_smpl_buffer_desc {
+	spinlock_t		psb_lock;	/* protection lock */
+	unsigned long		psb_refcnt;	/* how many users for the buffer */
+	int			psb_flags;	/* bitvector of flags */
+
 	void			*psb_addr;	/* points to location of first entry */
 	unsigned long		psb_entries;	/* maximum number of entries */
 	unsigned long		psb_size;	/* aligned size of buffer */
-	unsigned long		psb_index;	/* next free entry slot */
+	unsigned long		psb_index;	/* next free entry slot XXX: must use the one in buffer */
 	unsigned long		psb_entry_size;	/* size of each entry including entry header */
 	perfmon_smpl_hdr_t	*psb_hdr;	/* points to sampling buffer header */
+
+	struct _pfm_smpl_buffer_desc *psb_next;	/* next psb, used for rvfreeing of psb_hdr */
+
 } pfm_smpl_buffer_desc_t;
 
+#define LOCK_PSB(p)	spin_lock(&(p)->psb_lock)
+#define UNLOCK_PSB(p)	spin_unlock(&(p)->psb_lock)
+
+#define PFM_PSB_VMA	0x1			/* a VMA is describing the buffer */
 
 /*
  * This structure is initialized at boot time and contains
@@ -180,126 +169,192 @@
 	unsigned long num_pmcs ;	/* highest PMC implemented (may have holes) */
 	unsigned long num_pmds;		/* highest PMD implemented (may have holes) */
 	unsigned long impl_regs[16];	/* buffer used to hold implememted PMC/PMD mask */
+	unsigned long num_ibrs;		/* number of instruction debug registers */
+	unsigned long num_dbrs;		/* number of data debug registers */
+	unsigned long monitor_pmcs[4];	/* which pmc are controlling monitors */
+	unsigned long counter_pmds[4];	/* which pmd are used as counters */
 } pmu_config_t;
 
-#define PERFMON_IS_DISABLED() pmu_conf.pfm_is_disabled
-
+/*
+ * 64-bit software counter structure
+ */
 typedef struct {
-	__u64		val;		/* virtual 64bit counter value */
-	__u64		ival;		/* initial value from user */
-	__u64		smpl_rval;	/* reset value on sampling overflow */
-	__u64		ovfl_rval;	/* reset value on overflow */
-	int		flags;		/* notify/do not notify */
+	u64 val;	/* virtual 64bit counter value */
+	u64 ival;	/* initial value from user */
+	u64 long_reset;	/* reset value on sampling overflow */
+	u64 short_reset;/* reset value on overflow */
+	u64 reset_pmds[4]; /* which other pmds to reset when this counter overflows */
+	int flags;	/* notify/do not notify */
 } pfm_counter_t;
-#define PMD_OVFL_NOTIFY(ctx, i)	((ctx)->ctx_pmds[i].flags &  PFM_REGFL_OVFL_NOTIFY)
 
 /*
- * perfmon context. One per process, is cloned on fork() depending on inheritance flags
+ * perfmon context. One per process, is cloned on fork() depending on 
+ * inheritance flags
  */
 typedef struct {
-	unsigned int inherit:2;	/* inherit mode */
-	unsigned int noblock:1;	/* block/don't block on overflow with notification */
-	unsigned int system:1;	/* do system wide monitoring */
-	unsigned int frozen:1;	/* pmu must be kept frozen on ctxsw in */
-	unsigned int exclintr:1;/* exlcude interrupts from system wide monitoring */
-	unsigned int reserved:26;
+	unsigned int state:1;		/* 0=disabled, 1=enabled */
+	unsigned int inherit:2;		/* inherit mode */
+	unsigned int block:1;		/* when 1, task will blocked on user notifications */
+	unsigned int system:1;		/* do system wide monitoring */
+	unsigned int frozen:1;		/* pmu must be kept frozen on ctxsw in */
+	unsigned int protected:1;	/* allow access to creator of context only */
+	unsigned int using_dbreg:1;	/* using range restrictions (debug registers) */
+	unsigned int reserved:24;
 } pfm_context_flags_t;
 
+/*
+ * perfmon context: encapsulates all the state of a monitoring session
+ * XXX: probably need to change layout
+ */
 typedef struct pfm_context {
+	pfm_smpl_buffer_desc_t	*ctx_psb;		/* sampling buffer, if any */
+	unsigned long		ctx_smpl_vaddr;		/* user level virtual address of smpl buffer */
 
-	pfm_smpl_buffer_desc_t	*ctx_smpl_buf;		/* sampling buffer descriptor, if any */
-	unsigned long		ctx_dear_counter;	/* which PMD holds D-EAR */
-	unsigned long		ctx_iear_counter;	/* which PMD holds I-EAR */
-	unsigned long		ctx_btb_counter;	/* which PMD holds BTB */
-
-	spinlock_t		ctx_notify_lock;
+	spinlock_t		ctx_lock;
 	pfm_context_flags_t	ctx_flags;		/* block/noblock */
-	int			ctx_notify_sig;		/* XXX: SIGPROF or other */
+
 	struct task_struct	*ctx_notify_task;	/* who to notify on overflow */
-	struct task_struct	*ctx_creator;		/* pid of creator (debug) */
+	struct task_struct	*ctx_owner;		/* pid of creator (debug) */
+
+	unsigned long		ctx_ovfl_regs[4];	/* which registers overflowed (notification) */
+	unsigned long		ctx_smpl_regs[4];	/* which registers to record on overflow */
 
-	unsigned long		ctx_ovfl_regs;		/* which registers just overflowed (notification) */
-	unsigned long		ctx_smpl_regs;		/* which registers to record on overflow */
+	struct semaphore	ctx_restart_sem;   	/* use for blocking notification mode */
 
-	struct semaphore	ctx_restart_sem; 	/* use for blocking notification mode */
+	unsigned long		ctx_used_pmds[4];	/* bitmask of used PMD (speedup ctxsw) */
+	unsigned long		ctx_saved_pmcs[4];	/* bitmask of PMC to save on ctxsw */
+	unsigned long		ctx_reload_pmcs[4];	/* bitmask of PMC to reload on ctxsw (SMP) */
 
-	unsigned long		ctx_used_pmds[4]; 	/* bitmask of used PMD (speedup ctxsw) */
-	unsigned long		ctx_used_pmcs[4]; 	/* bitmask of used PMC (speedup ctxsw) */
+	unsigned long		ctx_used_ibrs[4];	/* bitmask of used IBR (speedup ctxsw) */
+	unsigned long		ctx_used_dbrs[4];	/* bitmask of used DBR (speedup ctxsw) */
 
-	pfm_counter_t		ctx_pmds[IA64_NUM_PMD_COUNTERS]; /* XXX: size should be dynamic */
+	pfm_counter_t		ctx_soft_pmds[IA64_NUM_PMD_REGS]; /* XXX: size should be dynamic */
 
+	u64			ctx_saved_psr;		/* copy of psr used for lazy ctxsw */
+	unsigned long		ctx_saved_cpus_allowed;	/* copy of the task cpus_allowed (system wide) */
+	unsigned long		ctx_cpu;		/* cpu to which perfmon is applied (system wide) */
+
+	atomic_t		ctx_saving_in_progress;	/* flag indicating actual save in progress */
+	atomic_t		ctx_last_cpu;		/* CPU id of current or last CPU used */
 } pfm_context_t;
 
-#define CTX_USED_PMD(ctx,n) (ctx)->ctx_used_pmds[(n)>>6] |= 1<< ((n) % 64)
-#define CTX_USED_PMC(ctx,n) (ctx)->ctx_used_pmcs[(n)>>6] |= 1<< ((n) % 64)
+#define ctx_fl_inherit		ctx_flags.inherit
+#define ctx_fl_block		ctx_flags.block
+#define ctx_fl_system		ctx_flags.system
+#define ctx_fl_frozen		ctx_flags.frozen
+#define ctx_fl_protected	ctx_flags.protected
+#define ctx_fl_using_dbreg	ctx_flags.using_dbreg
+
+/*
+ * global information about all sessions
+ * mostly used to synchronize between system wide and per-process
+ */
+typedef struct {
+	spinlock_t		pfs_lock;		/* lock the structure */
 
-#define ctx_fl_inherit	ctx_flags.inherit
-#define ctx_fl_noblock	ctx_flags.noblock
-#define ctx_fl_system	ctx_flags.system
-#define ctx_fl_frozen	ctx_flags.frozen
-#define ctx_fl_exclintr	ctx_flags.exclintr
+	unsigned long		pfs_task_sessions;	/* number of per task sessions */
+	unsigned long		pfs_sys_sessions;	/* number of per system wide sessions */
+	unsigned long   	pfs_sys_use_dbregs;	  	/* incremented when a system wide session uses debug regs */
+	unsigned long   	pfs_ptrace_use_dbregs;	  /* incremented when a process uses debug regs */
+	struct task_struct	*pfs_sys_session[NR_CPUS];  /* point to task owning a system-wide session */
+} pfm_session_t;
 
-#define CTX_OVFL_NOBLOCK(c)	((c)->ctx_fl_noblock == 1)
-#define CTX_INHERIT_MODE(c)	((c)->ctx_fl_inherit)
-#define CTX_HAS_SMPL(c)		((c)->ctx_smpl_buf != NULL)
+/*
+ * structure used to pass argument to/from remote CPU 
+ * using IPI to check and possibly save the PMU context on SMP systems.
+ *
+ * not used in UP kernels
+ */
+typedef struct {
+	struct task_struct *task;	/* which task we are interested in */
+	int retval;			/* return value of the call: 0=you can proceed, 1=need to wait for completion */
+} pfm_smp_ipi_arg_t;
 
-static pmu_config_t pmu_conf;
+/*
+ * perfmon command descriptions
+ */
+typedef struct {
+	int		(*cmd_func)(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs);
+	int		cmd_flags;
+	unsigned int	cmd_narg;
+	size_t		cmd_argsize;
+} pfm_cmd_desc_t;
 
-/* for debug only */
-static int pfm_debug=0;	/* 0= nodebug, >0= debug output on */
+#define PFM_CMD_PID		0x1	/* command requires pid argument */
+#define PFM_CMD_ARG_READ	0x2	/* command must read argument(s) */
+#define PFM_CMD_ARG_WRITE	0x4	/* command must write argument(s) */
+#define PFM_CMD_CTX		0x8	/* command needs a perfmon context */
+#define PFM_CMD_NOCHK		0x10	/* command does not need to check task's state */
 
-#define DBprintk(a) \
-	do { \
-		if (pfm_debug >0) { printk(__FUNCTION__" %d: ", __LINE__); printk a; } \
-	} while (0);
+#define PFM_CMD_IDX(cmd)	(cmd)
+
+#define PFM_CMD_IS_VALID(cmd)	((PFM_CMD_IDX(cmd) >= 0) && (PFM_CMD_IDX(cmd) < PFM_CMD_COUNT) \
+				  && pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_func != NULL)
+
+#define PFM_CMD_USE_PID(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_PID) != 0)
+#define PFM_CMD_READ_ARG(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_ARG_READ) != 0)
+#define PFM_CMD_WRITE_ARG(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_ARG_WRITE) != 0)
+#define PFM_CMD_USE_CTX(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_CTX) != 0)
+#define PFM_CMD_CHK(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_NOCHK) == 0)
+
+#define PFM_CMD_ARG_MANY	-1 /* cannot be zero */
+#define PFM_CMD_NARG(cmd)	(pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_narg)
+#define PFM_CMD_ARG_SIZE(cmd)	(pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_argsize)
 
-static void ia64_reset_pmu(void);
 
 /*
- * structure used to pass information between the interrupt handler
- * and the tasklet.
+ * perfmon internal variables
  */
-typedef struct {
-	pid_t		to_pid;		/* which process to notify */
-	pid_t		from_pid;	/* which process is source of overflow */
-	int		sig;		/* with which signal */
-	unsigned long	bitvect;	/* which counters have overflowed */
-} notification_info_t;
+static pmu_config_t	pmu_conf; 	/* PMU configuration */
+static int		pfm_debug_mode;	/* 0= nodebug, >0= debug output on */
+static pfm_session_t	pfm_sessions;	/* global sessions information */
+static struct proc_dir_entry *perfmon_dir; /* for debug only */
+static unsigned long pfm_spurious_ovfl_intr_count; /* keep track of spurious ovfl interrupts */
+static unsigned long pfm_ovfl_intr_count; /* keep track of spurious ovfl interrupts */
+static unsigned long pfm_recorded_samples_count;
 
 
-typedef struct {
-	unsigned long pfs_proc_sessions;
-	unsigned long pfs_sys_session; /* can only be 0/1 */
-	unsigned long pfs_dfl_dcr;	/* XXX: hack */
-	unsigned int  pfs_pp;
-} pfm_session_t;
+static unsigned long reset_pmcs[IA64_NUM_PMC_REGS];	/* contains PAL reset values for PMCS */
+
+static void pfm_vm_close(struct vm_area_struct * area);
+static struct vm_operations_struct pfm_vm_ops={
+	close: pfm_vm_close
+};
 
-struct {
+/*
+ * keep track of task owning the PMU per CPU.
+ */
+static struct {
 	struct task_struct *owner;
 } ____cacheline_aligned pmu_owners[NR_CPUS];
 
 
-/* 
- * helper macros
- */
-#define SET_PMU_OWNER(t)	do { pmu_owners[smp_processor_id()].owner = (t); } while(0);
-#define PMU_OWNER()		pmu_owners[smp_processor_id()].owner
 
+/*
+ * forward declarations
+ */
+static void ia64_reset_pmu(struct task_struct *);
 #ifdef CONFIG_SMP
-#define PFM_CAN_DO_LAZY()	(smp_num_cpus==1 && pfs_info.pfs_sys_session==0)
-#else
-#define PFM_CAN_DO_LAZY()	(pfs_info.pfs_sys_session==0)
+static void pfm_fetch_regs(int cpu, struct task_struct *task, pfm_context_t *ctx);
 #endif
-
 static void pfm_lazy_save_regs (struct task_struct *ta);
 
-/* for debug only */
-static struct proc_dir_entry *perfmon_dir;
+static inline unsigned long
+pfm_read_soft_counter(pfm_context_t *ctx, int i)
+{
+	return ctx->ctx_soft_pmds[i].val + (ia64_get_pmd(i) & pmu_conf.perf_ovfl_val);
+}
 
-/*
- * XXX: hack to indicate that a system wide monitoring session is active
- */
-static pfm_session_t pfs_info;
+static inline void
+pfm_write_soft_counter(pfm_context_t *ctx, int i, unsigned long val)
+{
+	ctx->ctx_soft_pmds[i].val = val  & ~pmu_conf.perf_ovfl_val;
+	/*
+	 * writing to unimplemented part is ignore, so we do not need to
+	 * mask off top part
+	 */
+	ia64_set_pmd(i, val);
+}
 
 /*
  * finds the number of PM(C|D) registers given
@@ -324,10 +379,10 @@
  * Generates a unique (per CPU) timestamp
  */
 static inline unsigned long
-perfmon_get_stamp(void)
+pfm_get_stamp(void)
 {
 	/*
-	 * XXX: maybe find something more efficient
+	 * XXX: must find something more efficient
 	 */
 	return ia64_get_itc();
 }
@@ -353,80 +408,185 @@
 			}
 		}
 	}
-	DBprintk(("uv2kva(%lx-->%lx)\n", adr, ret));
+	DBprintk(("[%d] uv2kva(%lx-->%lx)\n", current->pid, adr, ret));
 	return ret;
 }
 
-
 /* Here we want the physical address of the memory.
  * This is used when initializing the contents of the
  * area and marking the pages as reserved.
  */
 static inline unsigned long
-kvirt_to_pa(unsigned long adr)
+pfm_kvirt_to_pa(unsigned long adr)
 {
 	__u64 pa = ia64_tpa(adr);
-	DBprintk(("kv2pa(%lx-->%lx)\n", adr, pa));
+	//DBprintk(("kv2pa(%lx-->%lx)\n", adr, pa));
 	return pa;
 }
 
+
 static void *
-rvmalloc(unsigned long size)
+pfm_rvmalloc(unsigned long size)
 {
 	void *mem;
 	unsigned long adr, page;
 
-	/* XXX: may have to revisit this part because
-	 * vmalloc() does not necessarily return a page-aligned buffer.
-	 * This maybe a security problem when mapped at user level
-	 */
 	mem=vmalloc(size);
 	if (mem) {
+		//printk("perfmon: CPU%d pfm_rvmalloc(%ld)=%p\n", smp_processor_id(), size, mem);
 		memset(mem, 0, size); /* Clear the ram out, no junk to the user */
 		adr=(unsigned long) mem;
 		while (size > 0) {
-			page = kvirt_to_pa(adr);
+			page = pfm_kvirt_to_pa(adr);
 			mem_map_reserve(virt_to_page(__va(page)));
-			adr+=PAGE_SIZE;
-			size-=PAGE_SIZE;
+			adr  += PAGE_SIZE;
+			size -= PAGE_SIZE;
 		}
 	}
 	return mem;
 }
 
 static void
-rvfree(void *mem, unsigned long size)
+pfm_rvfree(void *mem, unsigned long size)
 {
-	unsigned long adr, page;
+	unsigned long adr, page = 0;
 
 	if (mem) {
 		adr=(unsigned long) mem;
 		while (size > 0) {
-			page = kvirt_to_pa(adr);
+			page = pfm_kvirt_to_pa(adr);
 			mem_map_unreserve(virt_to_page(__va(page)));
 			adr+=PAGE_SIZE;
 			size-=PAGE_SIZE;
 		}
 		vfree(mem);
 	}
+	return;
+}
+
+/*
+ * This function gets called from mm/mmap.c:exit_mmap() only when there is a sampling buffer
+ * attached to the context AND the current task has a mapping for it, i.e., it is the original
+ * creator of the context.
+ *
+ * This function is used to remember the fact that the vma describing the sampling buffer
+ * has now been removed. It can only be called when no other tasks share the same mm context.
+ *
+ */
+static void 
+pfm_vm_close(struct vm_area_struct *vma)
+{
+	pfm_smpl_buffer_desc_t *psb = (pfm_smpl_buffer_desc_t *)vma->vm_private_data;
+
+	if (psb == NULL) {
+		printk("perfmon: psb is null in [%d]\n", current->pid);
+		return;
+	}
+	/*
+	 * Add PSB to list of buffers to free on release_thread() when no more users
+	 *
+	 * This call is safe because, once the count is zero is cannot be modified anymore.
+	 * This is not because there is no more user of the mm context, that the sampling
+	 * buffer is not being used anymore outside of this task. In fact, it can still
+	 * be accessed from within the kernel by another task (such as the monitored task).
+	 *
+	 * Therefore, we only move the psb into the list of buffers to free when we know
+	 * nobody else is using it.
+	 * The linked list if independent of the perfmon context, because in the case of
+	 * multi-threaded processes, the last thread may not have been involved with
+	 * monitoring however it will be the one removing the vma and it should therefore
+	 * also remove the sampling buffer. This buffer cannot be removed until the vma
+	 * is removed.
+	 *
+	 * This function cannot remove the buffer from here, because exit_mmap() must first
+	 * complete. Given that there is no other vma related callback in the generic code,
+	 * we have created on own with the linked list of sampling buffer to free which
+	 * is part of the thread structure. In release_thread() we check if the list is
+	 * empty. If not we call into perfmon to free the buffer and psb. That is the only
+	 * way to ensure a safe deallocation of the sampling buffer which works when
+	 * the buffer is shared between distinct processes or with multi-threaded programs.
+	 *
+	 * We need to lock the psb because the refcnt test and flag manipulation must
+	 * looked like an atomic operation vis a vis pfm_context_exit()
+	 */
+	LOCK_PSB(psb);
+
+	if (psb->psb_refcnt == 0) {
+
+		psb->psb_next = current->thread.pfm_smpl_buf_list;
+		current->thread.pfm_smpl_buf_list = psb;
+
+		DBprintk(("psb for [%d] smpl @%p size %ld inserted into list\n", 
+			current->pid, psb->psb_hdr, psb->psb_size));
+	}
+	DBprintk(("psb vma flag cleared for [%d] smpl @%p size %ld inserted into list\n", 
+			current->pid, psb->psb_hdr, psb->psb_size));
+
+	/*
+	 * indicate to pfm_context_exit() that the vma has been removed. 
+	 */
+	psb->psb_flags &= ~PFM_PSB_VMA;
+
+	UNLOCK_PSB(psb);
+}
+
+/*
+ * This function is called from pfm_destroy_context() and also from pfm_inherit()
+ * to explicitely remove the sampling buffer mapping from the user level address space.
+ */
+static int
+pfm_remove_smpl_mapping(struct task_struct *task)
+{
+	pfm_context_t *ctx = task->thread.pfm_context;
+	pfm_smpl_buffer_desc_t *psb;
+	int r;
+
+	/*
+	 * some sanity checks first
+	 */
+	if (ctx == NULL || task->mm == NULL || ctx->ctx_smpl_vaddr == 0 || ctx->ctx_psb == NULL) {
+		printk("perfmon: invalid context mm=%p\n", task->mm);
+		return -1;
+	}
+	psb = ctx->ctx_psb;	
+
+	down_write(&task->mm->mmap_sem);
+
+	r = do_munmap(task->mm, ctx->ctx_smpl_vaddr, psb->psb_size);
+
+	up_write(&task->mm->mmap_sem);
+	if (r !=0) {
+		printk("perfmon: pid %d unable to unmap sampling buffer @0x%lx size=%ld\n", 
+				task->pid, ctx->ctx_smpl_vaddr, psb->psb_size);
+	}
+	DBprintk(("[%d] do_unmap(0x%lx, %ld)=%d\n", 
+		task->pid, ctx->ctx_smpl_vaddr, psb->psb_size, r));
+
+	/* 
+	 * make sure we suppress all traces of this buffer
+	 * (important for pfm_inherit)
+	 */
+	ctx->ctx_smpl_vaddr = 0;
+
+	return 0;
 }
 
 static pfm_context_t *
 pfm_context_alloc(void)
 {
-	pfm_context_t *pfc;
+	pfm_context_t *ctx;
 
 	/* allocate context descriptor */
-	pfc = vmalloc(sizeof(*pfc));
-	if (pfc) memset(pfc, 0, sizeof(*pfc));
-
-	return pfc;
+	ctx = kmalloc(sizeof(pfm_context_t), GFP_KERNEL);
+	if (ctx) memset(ctx, 0, sizeof(pfm_context_t));
+	
+	return ctx;
 }
 
 static void
-pfm_context_free(pfm_context_t *pfc)
+pfm_context_free(pfm_context_t *ctx)
 {
-	if (pfc) vfree(pfc);
+	if (ctx) kfree(ctx);
 }
 
 static int
@@ -434,11 +594,13 @@
 {
 	unsigned long page;
 
+	DBprintk(("CPU%d buf=0x%lx addr=0x%lx size=%ld\n", smp_processor_id(), buf, addr, size));
+
 	while (size > 0) {
-		page = kvirt_to_pa(buf);
+		page = pfm_kvirt_to_pa(buf);
 
 		if (remap_page_range(addr, page, PAGE_SIZE, PAGE_SHARED)) return -ENOMEM;
-
+		
 		addr  += PAGE_SIZE;
 		buf   += PAGE_SIZE;
 		size  -= PAGE_SIZE;
@@ -458,7 +620,7 @@
 
 	for (i=0; i < size; i++, which++) res += hweight64(*which);
 
-	DBprintk((" res=%ld\n", res));
+	DBprintk(("weight=%ld\n", res));
 
 	return res;
 }
@@ -467,15 +629,16 @@
  * Allocates the sampling buffer and remaps it into caller's address space
  */
 static int
-pfm_smpl_buffer_alloc(pfm_context_t *ctx, unsigned long which_pmds, unsigned long entries, void **user_addr)
+pfm_smpl_buffer_alloc(pfm_context_t *ctx, unsigned long *which_pmds, unsigned long entries, 
+		      void **user_vaddr)
 {
 	struct mm_struct *mm = current->mm;
-	struct vm_area_struct *vma;
-	unsigned long addr, size, regcount;
+	struct vm_area_struct *vma = NULL;
+	unsigned long size, regcount;
 	void *smpl_buf;
 	pfm_smpl_buffer_desc_t *psb;
 
-	regcount = pfm_smpl_entry_size(&which_pmds, 1);
+	regcount = pfm_smpl_entry_size(which_pmds, 1);
 
 	/* note that regcount might be 0, in this case only the header for each
 	 * entry will be recorded.
@@ -488,133 +651,207 @@
 			  + entries * (sizeof(perfmon_smpl_entry_t) + regcount*sizeof(u64)));
 	/*
 	 * check requested size to avoid Denial-of-service attacks
-	 * XXX: may have to refine this test
+	 * XXX: may have to refine this test	
+	 * Check against address space limit.
+	 *
+	 * if ((mm->total_vm << PAGE_SHIFT) + len> current->rlim[RLIMIT_AS].rlim_cur) 
+	 * 	return -ENOMEM;
 	 */
 	if (size > current->rlim[RLIMIT_MEMLOCK].rlim_cur) return -EAGAIN;
 
-	/* find some free area in address space */
-	addr = get_unmapped_area(NULL, 0, size, 0, MAP_PRIVATE);
-	if (!addr) goto no_addr;
+	/*
+	 * We do the easy to undo allocations first.
+ 	 *
+	 * pfm_rvmalloc(), clears the buffer, so there is no leak
+	 */
+	smpl_buf = pfm_rvmalloc(size);
+	if (smpl_buf == NULL) {
+		DBprintk(("Can't allocate sampling buffer\n"));
+		return -ENOMEM;
+	}
+
+	DBprintk(("smpl_buf @%p\n", smpl_buf));
 
-	DBprintk((" entries=%ld aligned size=%ld, unmapped @0x%lx\n", entries, size, addr));
+	/* allocate sampling buffer descriptor now */
+	psb = kmalloc(sizeof(*psb), GFP_KERNEL);
+	if (psb == NULL) {
+		DBprintk(("Can't allocate sampling buffer descriptor\n"));
+		pfm_rvfree(smpl_buf, size);
+		return -ENOMEM;
+	}
 
 	/* allocate vma */
 	vma = kmem_cache_alloc(vm_area_cachep, SLAB_KERNEL);
-	if (!vma) goto no_vma;
-
-	/* XXX: see rvmalloc() for page alignment problem */
-	smpl_buf = rvmalloc(size);
-	if (smpl_buf == NULL) goto no_buffer;
-
-	DBprintk((" smpl_buf @%p\n", smpl_buf));
-
-	if (pfm_remap_buffer((unsigned long)smpl_buf, addr, size)) goto cant_remap;
-
-	/* allocate sampling buffer descriptor now */
-	psb = vmalloc(sizeof(*psb));
-	if (psb == NULL) goto no_buffer_desc;
+	if (!vma) {
+		DBprintk(("Cannot allocate vma\n"));
+		goto error;
+	}
+	/*
+	 * partially initialize the vma for the sampling buffer
+	 */
+	vma->vm_mm	     = mm;
+	vma->vm_flags	     = VM_READ| VM_MAYREAD |VM_RESERVED;
+	vma->vm_page_prot    = PAGE_READONLY; /* XXX may need to change */
+	vma->vm_ops	     = &pfm_vm_ops; /* necesarry to get the close() callback */
+	vma->vm_pgoff	     = 0;
+	vma->vm_file	     = NULL;
+	vma->vm_raend	     = 0;
+	vma->vm_private_data = psb;	/* information needed by the pfm_vm_close() function */
 
-	/* start with something clean */
-	memset(smpl_buf, 0x0, size);
+	/*
+	 * Now we have everything we need and we can initialize
+	 * and connect all the data structures
+	 */
 
 	psb->psb_hdr	 = smpl_buf;
-	psb->psb_addr    = (char *)smpl_buf+sizeof(perfmon_smpl_hdr_t); /* first entry */
+	psb->psb_addr    = ((char *)smpl_buf)+sizeof(perfmon_smpl_hdr_t); /* first entry */
 	psb->psb_size    = size; /* aligned size */
 	psb->psb_index   = 0;
 	psb->psb_entries = entries;
+	psb->psb_flags   = PFM_PSB_VMA; /* remember that there is a vma describing the buffer */
+	psb->psb_refcnt  = 1;
 
-	atomic_set(&psb->psb_refcnt, 1);
+	spin_lock_init(&psb->psb_lock);
 
+	/*
+	 * XXX: will need to do cacheline alignment to avoid false sharing in SMP mode and
+	 * multitask monitoring.
+	 */
 	psb->psb_entry_size = sizeof(perfmon_smpl_entry_t) + regcount*sizeof(u64);
 
-	DBprintk((" psb @%p entry_size=%ld hdr=%p addr=%p\n", (void *)psb,psb->psb_entry_size, (void *)psb->psb_hdr, (void *)psb->psb_addr));
-
-	/* initialize some of the fields of header */
-	psb->psb_hdr->hdr_version    = PFM_SMPL_HDR_VERSION;
-	psb->psb_hdr->hdr_entry_size = sizeof(perfmon_smpl_entry_t)+regcount*sizeof(u64);
-	psb->psb_hdr->hdr_pmds	     = which_pmds;
-
-	/* store which PMDS to record */
-	ctx->ctx_smpl_regs = which_pmds;
+	DBprintk(("psb @%p entry_size=%ld hdr=%p addr=%p\n", 
+		  (void *)psb,psb->psb_entry_size, (void *)psb->psb_hdr, 
+		  (void *)psb->psb_addr));
 
-	/* link to perfmon context */
-	ctx->ctx_smpl_buf  = psb;
+	/* initialize some of the fields of user visible buffer header */
+	psb->psb_hdr->hdr_version    = PFM_SMPL_VERSION;
+	psb->psb_hdr->hdr_entry_size = psb->psb_entry_size;
+	psb->psb_hdr->hdr_pmds[0]    = which_pmds[0];
 
 	/*
-	 * initialize the vma for the sampling buffer
+	 * Let's do the difficult operations next.
+	 *
+	 * now we atomically find some area in the address space and
+	 * remap the buffer in it.
 	 */
-	vma->vm_mm	  = mm;
-	vma->vm_start	  = addr;
-	vma->vm_end	  = addr + size;
-	vma->vm_flags	  = VM_READ|VM_MAYREAD;
-	vma->vm_page_prot = PAGE_READONLY; /* XXX may need to change */
-	vma->vm_ops	  = NULL;
-	vma->vm_pgoff	  = 0;
-	vma->vm_file	  = NULL;
-	vma->vm_raend	  = 0;
+	down_write(&current->mm->mmap_sem);
+
 
-	vma->vm_private_data = ctx;	/* link to pfm_context(not yet used) */
+	/* find some free area in address space, must have mmap sem held */
+	vma->vm_start = get_unmapped_area(NULL, 0, size, 0, MAP_PRIVATE|MAP_ANONYMOUS);
+	if (vma->vm_start == 0UL) {
+		DBprintk(("Cannot find unmapped area for size %ld\n", size));
+		up_write(&current->mm->mmap_sem);
+		goto error;
+	}
+	vma->vm_end = vma->vm_start + size;
+
+	DBprintk(("entries=%ld aligned size=%ld, unmapped @0x%lx\n", entries, size, vma->vm_start));
+		
+	/* can only be applied to current, need to have the mm semaphore held when called */
+	if (pfm_remap_buffer((unsigned long)smpl_buf, vma->vm_start, size)) {
+		DBprintk(("Can't remap buffer\n"));
+		up_write(&current->mm->mmap_sem);
+		goto error;
+	}
 
 	/*
-	 * now insert the vma in the vm list for the process
+	 * now insert the vma in the vm list for the process, must be
+	 * done with mmap lock held
 	 */
 	insert_vm_struct(mm, vma);
 
 	mm->total_vm  += size >> PAGE_SHIFT;
 
+	up_write(&current->mm->mmap_sem);
+
+	/* store which PMDS to record */
+	ctx->ctx_smpl_regs[0] = which_pmds[0];
+
+
+	/* link to perfmon context */
+	ctx->ctx_psb        = psb;
+
 	/*
-	 * that's the address returned to the user
+	 * keep track of user level virtual address 
 	 */
-	*user_addr = (void *)addr;
+	ctx->ctx_smpl_vaddr = *(unsigned long *)user_vaddr = vma->vm_start;
 
 	return 0;
 
-	/* outlined error handling */
-no_addr:
-	DBprintk(("Cannot find unmapped area for size %ld\n", size));
-	return -ENOMEM;
-no_vma:
-	DBprintk(("Cannot allocate vma\n"));
-	return -ENOMEM;
-cant_remap:
-	DBprintk(("Can't remap buffer\n"));
-	rvfree(smpl_buf, size);
-no_buffer:
-	DBprintk(("Can't allocate sampling buffer\n"));
-	kmem_cache_free(vm_area_cachep, vma);
-	return -ENOMEM;
-no_buffer_desc:
-	DBprintk(("Can't allocate sampling buffer descriptor\n"));
-	kmem_cache_free(vm_area_cachep, vma);
-	rvfree(smpl_buf, size);
+error:
+	pfm_rvfree(smpl_buf, size);
+	kfree(psb);
 	return -ENOMEM;
 }
 
+/*
+ * XXX: do something better here
+ */
+static int
+pfm_bad_permissions(struct task_struct *task)
+{
+	/* stolen from bad_signal() */
+	return (current->session != task->session)
+	    && (current->euid ^ task->suid) && (current->euid ^ task->uid)
+	    && (current->uid ^ task->suid) && (current->uid ^ task->uid);
+}
+
+
 static int
-pfx_is_sane(pfreq_context_t *pfx)
+pfx_is_sane(struct task_struct *task, pfarg_context_t *pfx)
 {
 	int ctx_flags;
+	int cpu;
 
 	/* valid signal */
-	//if (pfx->notify_sig < 1 || pfx->notify_sig >= _NSIG) return -EINVAL;
-	if (pfx->notify_sig !=0 && pfx->notify_sig != SIGPROF) return -EINVAL;
 
 	/* cannot send to process 1, 0 means do not notify */
-	if (pfx->notify_pid < 0 || pfx->notify_pid == 1) return -EINVAL;
-
-	ctx_flags = pfx->flags;
+	if (pfx->ctx_notify_pid == 1) {
+		DBprintk(("invalid notify_pid %d\n", pfx->ctx_notify_pid));
+		return -EINVAL;
+	}
+	ctx_flags = pfx->ctx_flags;
 
 	if (ctx_flags & PFM_FL_SYSTEM_WIDE) {
-#ifdef CONFIG_SMP
-		if (smp_num_cpus > 1) {
-			printk("perfmon: system wide monitoring on SMP not yet supported\n");
+		DBprintk(("cpu_mask=0x%lx\n", pfx->ctx_cpu_mask));
+		/*
+		 * cannot block in this mode 
+		 */
+		if (ctx_flags & PFM_FL_NOTIFY_BLOCK) {
+			DBprintk(("cannot use blocking mode when in system wide monitoring\n"));
 			return -EINVAL;
 		}
-#endif
-		if ((ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) == 0) {
-			printk("perfmon: system wide monitoring cannot use blocking notification mode\n");
+		/*
+		 * must only have one bit set in the CPU mask
+		 */
+		if (hweight64(pfx->ctx_cpu_mask) != 1UL) {
+			DBprintk(("invalid CPU mask specified\n"));
+			return -EINVAL;
+		}
+		/*
+		 * and it must be a valid CPU
+		 */
+		cpu = ffs(pfx->ctx_cpu_mask);
+		if (cpu > smp_num_cpus) {
+			DBprintk(("CPU%d is not online\n", cpu));
+			return -EINVAL;
+		}
+		/*
+		 * check for pre-existing pinning, if conflicting reject
+		 */
+		if (task->cpus_allowed != ~0UL && (task->cpus_allowed & (1UL<<cpu)) == 0) {
+			DBprintk(("[%d] pinned on 0x%lx, mask for CPU%d \n", task->pid, 
+				task->cpus_allowed, cpu));
 			return -EINVAL;
 		}
+
+	} else {
+		/*
+		 * must provide a target for the signal in blocking mode even when
+		 * no counter is configured with PFM_FL_REG_OVFL_NOTIFY
+		 */
+		if ((ctx_flags & PFM_FL_NOTIFY_BLOCK) && pfx->ctx_notify_pid == 0) return -EINVAL;
 	}
 	/* probably more to add here */
 
@@ -622,68 +859,97 @@
 }
 
 static int
-pfm_context_create(int flags, perfmon_req_t *req)
+pfm_create_context(struct task_struct *task, pfm_context_t *ctx, void *req, int count, 
+		   struct pt_regs *regs)
 {
-	pfm_context_t *ctx;
-	struct task_struct *task = NULL;
-	perfmon_req_t tmp;
+	pfarg_context_t tmp;
 	void *uaddr = NULL;
-	int ret;
+	int ret, cpu = 0;
 	int ctx_flags;
-	pid_t pid;
+	pid_t notify_pid;
 
-	/* to go away */
-	if (flags) {
-		printk("perfmon: use context flags instead of perfmon() flags. Obsoleted API\n");
-	}
+	/* a context has already been defined */
+	if (ctx) return -EBUSY;
+
+	/*
+	 * not yet supported
+	 */
+	if (task != current) return -EINVAL;
 
 	if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-	ret = pfx_is_sane(&tmp.pfr_ctx);
+	ret = pfx_is_sane(task, &tmp);
 	if (ret < 0) return ret;
 
-	ctx_flags = tmp.pfr_ctx.flags;
+	ctx_flags = tmp.ctx_flags;
+
+	ret =  -EBUSY;
+
+	LOCK_PFS();
 
 	if (ctx_flags & PFM_FL_SYSTEM_WIDE) {
+
+		/* at this point, we know there is at least one bit set */
+		cpu = ffs(tmp.ctx_cpu_mask) - 1;
+
+		DBprintk(("requesting CPU%d currently on CPU%d\n",cpu, smp_processor_id()));
+
+		if (pfm_sessions.pfs_task_sessions > 0) {
+			DBprintk(("system wide not possible, task_sessions=%ld\n", pfm_sessions.pfs_task_sessions));
+			goto abort;
+		}
+
+		if (pfm_sessions.pfs_sys_session[cpu]) {
+			DBprintk(("system wide not possible, conflicting session [%d] on CPU%d\n",pfm_sessions.pfs_sys_session[cpu]->pid, cpu));
+			goto abort;
+		}
+		pfm_sessions.pfs_sys_session[cpu] = task;
 		/*
-		 * XXX: This is not AT ALL SMP safe
+		 * count the number of system wide sessions
 		 */
-		if (pfs_info.pfs_proc_sessions > 0) return -EBUSY;
-		if (pfs_info.pfs_sys_session > 0) return -EBUSY;
+		pfm_sessions.pfs_sys_sessions++;
 
-		pfs_info.pfs_sys_session = 1;
-
-	} else if (pfs_info.pfs_sys_session >0) {
+	} else if (pfm_sessions.pfs_sys_sessions == 0) {
+		pfm_sessions.pfs_task_sessions++;
+	} else {
 		/* no per-process monitoring while there is a system wide session */
-		return -EBUSY;
-	} else
-		pfs_info.pfs_proc_sessions++;
+		goto abort;
+	}
+
+	UNLOCK_PFS();
+
+	ret = -ENOMEM;
 
 	ctx = pfm_context_alloc();
 	if (!ctx) goto error;
 
-	/* record the creator (debug only) */
-	ctx->ctx_creator = current;
+	/* record the creator (important for inheritance) */
+	ctx->ctx_owner = current;
+
+	notify_pid = tmp.ctx_notify_pid;
 
-	pid = tmp.pfr_ctx.notify_pid;
+	spin_lock_init(&ctx->ctx_lock);
 
-	spin_lock_init(&ctx->ctx_notify_lock);
+	if (notify_pid == current->pid) {
 
-	if (pid == current->pid) {
 		ctx->ctx_notify_task = task = current;
 		current->thread.pfm_context = ctx;
 
-		atomic_set(&current->thread.pfm_notifiers_check, 1);
+	} else if (notify_pid!=0) {
+		struct task_struct *notify_task;
 
-	} else if (pid!=0) {
 		read_lock(&tasklist_lock);
 
-		task = find_task_by_pid(pid);
-		if (task) {
+		notify_task = find_task_by_pid(notify_pid);
+
+		if (notify_task) {
+
+			ret = -EPERM;
+
 			/*
-		 	 * record who to notify
-		 	 */
-			ctx->ctx_notify_task = task;
+			 * check if we can send this task a signal
+			 */
+			if (pfm_bad_permissions(notify_task)) goto buffer_error;
 
 			/* 
 		 	 * make visible
@@ -702,7 +968,9 @@
 			 * task has been detached from the tasklist otherwise you are
 			 * exposed to race conditions.
 			 */
-			atomic_add(1, &task->thread.pfm_notifiers_check);
+			atomic_add(1, &ctx->ctx_notify_task->thread.pfm_notifiers_check);
+
+			ctx->ctx_notify_task = notify_task;
 		}
 		read_unlock(&tasklist_lock);
 	}
@@ -710,37 +978,48 @@
 	/*
 	 * notification process does not exist
 	 */
-	if (pid != 0 && task == NULL) {
+	if (notify_pid != 0 && ctx->ctx_notify_task == NULL) {
 		ret = -EINVAL;
 		goto buffer_error;
 	}
 
-	ctx->ctx_notify_sig = SIGPROF;	/* siginfo imposes a fixed signal */
+	if (tmp.ctx_smpl_entries) {
+		DBprintk(("sampling entries=%ld\n",tmp.ctx_smpl_entries));
 
-	if (tmp.pfr_ctx.smpl_entries) {
-		DBprintk((" sampling entries=%ld\n",tmp.pfr_ctx.smpl_entries));
-
-		ret = pfm_smpl_buffer_alloc(ctx, tmp.pfr_ctx.smpl_regs, 
-						 tmp.pfr_ctx.smpl_entries, &uaddr);
+		ret = pfm_smpl_buffer_alloc(ctx, tmp.ctx_smpl_regs, 
+						 tmp.ctx_smpl_entries, &uaddr);
 		if (ret<0) goto buffer_error;
 
-		tmp.pfr_ctx.smpl_vaddr = uaddr;
+		tmp.ctx_smpl_vaddr = uaddr;
 	}
 	/* initialization of context's flags */
-	ctx->ctx_fl_inherit  = ctx_flags & PFM_FL_INHERIT_MASK;
-	ctx->ctx_fl_noblock  = (ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) ? 1 : 0;
-	ctx->ctx_fl_system   = (ctx_flags & PFM_FL_SYSTEM_WIDE) ? 1: 0;
-	ctx->ctx_fl_exclintr = (ctx_flags & PFM_FL_EXCL_INTR) ? 1: 0;
-	ctx->ctx_fl_frozen   = 0;
+	ctx->ctx_fl_inherit   = ctx_flags & PFM_FL_INHERIT_MASK;
+	ctx->ctx_fl_block     = (ctx_flags & PFM_FL_NOTIFY_BLOCK) ? 1 : 0;
+	ctx->ctx_fl_system    = (ctx_flags & PFM_FL_SYSTEM_WIDE) ? 1: 0;
+	ctx->ctx_fl_frozen    = 0;
+	/*
+	 * setting this flag to 0 here means, that the creator or the task that the
+	 * context is being attached are granted access. Given that a context can only
+	 * be created for the calling process this, in effect only allows the creator
+	 * to access the context. See pfm_protect() for more.
+	 */
+	ctx->ctx_fl_protected = 0;
+
+	/* for system wide mode only (only 1 bit set) */
+	ctx->ctx_cpu         = cpu;
+
+	atomic_set(&ctx->ctx_last_cpu,-1); /* SMP only, means no CPU */
 
 	/* 
 	 * Keep track of the pmds we want to sample
 	 * XXX: may be we don't need to save/restore the DEAR/IEAR pmds
 	 * but we do need the BTB for sure. This is because of a hardware
 	 * buffer of 1 only for non-BTB pmds.
+	 *
+	 * We ignore the unimplemented pmds specified by the user
 	 */
-	ctx->ctx_used_pmds[0] = tmp.pfr_ctx.smpl_regs;
-	ctx->ctx_used_pmcs[0] = 1; /* always save/restore PMC[0] */
+	ctx->ctx_used_pmds[0]  = tmp.ctx_smpl_regs[0] & pmu_conf.impl_regs[4];
+	ctx->ctx_saved_pmcs[0] = 1; /* always save/restore PMC[0] */
 
 	sema_init(&ctx->ctx_restart_sem, 0); /* init this semaphore to locked */
 
@@ -750,31 +1029,28 @@
 		goto buffer_error;
 	}
 
-	DBprintk((" context=%p, pid=%d notify_sig %d notify_task=%p\n",(void *)ctx, current->pid, ctx->ctx_notify_sig, ctx->ctx_notify_task));
-	DBprintk((" context=%p, pid=%d flags=0x%x inherit=%d noblock=%d system=%d\n",(void *)ctx, current->pid, ctx_flags, ctx->ctx_fl_inherit, ctx->ctx_fl_noblock, ctx->ctx_fl_system));
+	DBprintk(("context=%p, pid=%d notify_task=%p\n",
+			(void *)ctx, task->pid, ctx->ctx_notify_task));
+
+	DBprintk(("context=%p, pid=%d flags=0x%x inherit=%d block=%d system=%d\n", 
+			(void *)ctx, task->pid, ctx_flags, ctx->ctx_fl_inherit, 
+			ctx->ctx_fl_block, ctx->ctx_fl_system));
 
 	/*
 	 * when no notification is required, we can make this visible at the last moment
 	 */
-	if (pid == 0) current->thread.pfm_context = ctx;
-
+	if (notify_pid == 0) task->thread.pfm_context = ctx;
 	/*
-	 * by default, we always include interrupts for system wide
-	 * DCR.pp is set by default to zero by kernel  in cpu_init()
+	 * pin task to CPU and force reschedule on exit to ensure
+	 * that when back to user level the task runs on the designated
+	 * CPU.
 	 */
 	if (ctx->ctx_fl_system) {
-		if (ctx->ctx_fl_exclintr == 0) {
-			unsigned long dcr = ia64_get_dcr();
-
-			ia64_set_dcr(dcr|IA64_DCR_PP);
-			/*
-			* keep track of the kernel default value
-			 */
-			pfs_info.pfs_dfl_dcr = dcr;
-
-			DBprintk((" dcr.pp is set\n"));
-		}
-	} 
+		ctx->ctx_saved_cpus_allowed = task->cpus_allowed;
+		task->cpus_allowed = 1UL << cpu;
+		task->need_resched = 1;
+		DBprintk(("[%d] rescheduled allowed=0x%lx\n", task->pid,task->cpus_allowed));
+	}
 
 	return 0;
 
@@ -784,225 +1060,492 @@
 	/*
 	 * undo session reservation
 	 */
+	LOCK_PFS();
+
 	if (ctx_flags & PFM_FL_SYSTEM_WIDE) {
-		pfs_info.pfs_sys_session = 0;
+		pfm_sessions.pfs_sys_session[cpu] = NULL;
+		pfm_sessions.pfs_sys_sessions--;
 	} else {
-		pfs_info.pfs_proc_sessions--;
+		pfm_sessions.pfs_task_sessions--;
 	}
+abort:
+	UNLOCK_PFS();
+
 	return ret;
 }
 
 static void
-pfm_reset_regs(pfm_context_t *ctx)
+pfm_reset_regs(pfm_context_t *ctx, unsigned long *ovfl_regs, int flag)
 {
-	unsigned long mask = ctx->ctx_ovfl_regs;
-	int i, cnum;
+	unsigned long mask = ovfl_regs[0];
+	unsigned long reset_others = 0UL;
+	unsigned long val;
+	int i;
+
+	DBprintk(("masks=0x%lx\n", mask));
 
-	DBprintk((" ovfl_regs=0x%lx\n", mask));
 	/*
 	 * now restore reset value on sampling overflowed counters
 	 */
-	for(i=0, cnum=PMU_FIRST_COUNTER; i < pmu_conf.max_counters; i++, cnum++, mask >>= 1) {
+	mask >>= PMU_FIRST_COUNTER;
+	for(i = PMU_FIRST_COUNTER; mask; i++, mask >>= 1) {
 		if (mask & 0x1) {
-			DBprintk((" reseting PMD[%d]=%lx\n", cnum, ctx->ctx_pmds[i].smpl_rval & pmu_conf.perf_ovfl_val));
+			val  = flag == PFM_RELOAD_LONG_RESET ? 
+					ctx->ctx_soft_pmds[i].long_reset:
+					ctx->ctx_soft_pmds[i].short_reset;
+
+			reset_others |= ctx->ctx_soft_pmds[i].reset_pmds[0];
+
+			DBprintk(("[%d] %s reset soft_pmd[%d]=%lx\n", 
+			  	current->pid, 
+				flag == PFM_RELOAD_LONG_RESET ? "long" : "short", i, val));
 
 			/* upper part is ignored on rval */
-			ia64_set_pmd(cnum, ctx->ctx_pmds[i].smpl_rval);
+			pfm_write_soft_counter(ctx, i, val);
+		}
+	}
 
-			/*
-			 * we must reset BTB index (clears pmd16.full to make
-			 * sure we do not report the same branches twice.
-			 * The non-blocking case in handled in update_counters()
-			 */
-			if (cnum == ctx->ctx_btb_counter) {
-				DBprintk(("reseting PMD16\n"));
-				ia64_set_pmd(16, 0);
-			}
+	/*
+	 * Now take care of resetting the other registers
+	 */
+	for(i = 0; reset_others; i++, reset_others >>= 1) {
+
+		if ((reset_others & 0x1) == 0) continue;
+
+		val  = flag == PFM_RELOAD_LONG_RESET ? 
+					ctx->ctx_soft_pmds[i].long_reset:
+					ctx->ctx_soft_pmds[i].short_reset;
+
+		if (PMD_IS_COUNTING(i)) {
+			pfm_write_soft_counter(ctx, i, val);
+		} else {
+			ia64_set_pmd(i, val);
 		}
+
+		DBprintk(("[%d] %s reset_others pmd[%d]=%lx\n", 
+			  	current->pid, 
+				flag == PFM_RELOAD_LONG_RESET ? "long" : "short", i, val));
 	}
 	/* just in case ! */
-	ctx->ctx_ovfl_regs = 0;
+	ctx->ctx_ovfl_regs[0] = 0UL;
 }
 
 static int
-pfm_write_pmcs(struct task_struct *ta, perfmon_req_t *req, int count)
+pfm_write_pmcs(struct task_struct *ta, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
 {
 	struct thread_struct *th = &ta->thread;
-	pfm_context_t *ctx = th->pfm_context;
-	perfmon_req_t tmp;
-	unsigned long cnum;
+	pfarg_reg_t tmp, *req = (pfarg_reg_t *)arg;
+	unsigned int cnum;
 	int i;
+	int ret = 0, reg_retval = 0;
+
+	/* we don't quite support this right now */
+	if (ta != current) return -EINVAL;
+
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
 	/* XXX: ctx locking may be required here */
 
 	for (i = 0; i < count; i++, req++) {
 
+
 		if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-		cnum = tmp.pfr_reg.reg_num;
+		cnum = tmp.reg_num;
 
-		/* XXX needs to check validity of the data maybe */
-		if (!PMC_IS_IMPL(cnum)) {
-			DBprintk((" invalid pmc[%ld]\n", cnum));
-			return -EINVAL;
+		/* 
+		 * we reject all non implemented PMC as well
+		 * as attempts to modify PMC[0-3] which are used
+		 * as status registers by the PMU
+		 */
+		if (!PMC_IS_IMPL(cnum) || cnum < 4) {
+			DBprintk(("pmc[%u] is unimplemented or invalid\n", cnum));
+			ret = -EINVAL;
+			goto abort_mission;
 		}
+		/*
+		 * A PMC used to configure monitors must be:
+		 * 	- system-wide session: privileged monitor
+		 * 	- per-task : user monitor
+		 * any other configuration is rejected.
+		 */
+		if (PMC_IS_MONITOR(cnum)) {
+			pfm_monitor_t *p = (pfm_monitor_t *)&tmp.reg_value;
 
-		if (PMC_IS_COUNTER(cnum)) {
+			DBprintk(("pmc[%u].pm = %d\n", cnum, p->pmc_pm));
 
+			if (ctx->ctx_fl_system ^ p->pmc_pm) {
+			//if ((ctx->ctx_fl_system == 1 && p->pmc_pm == 0)
+			 //  ||(ctx->ctx_fl_system == 0 && p->pmc_pm == 1)) {
+				ret = -EINVAL;
+				goto abort_mission;
+			}
 			/*
-			 * we keep track of EARS/BTB to speed up sampling later
+			 * enforce generation of overflow interrupt. Necessary on all
+			 * CPUs which do not implement 64-bit hardware counters.
 			 */
-			if (PMC_IS_DEAR(&tmp.pfr_reg.reg_value)) {
-				ctx->ctx_dear_counter = cnum;
-			} else if (PMC_IS_IEAR(&tmp.pfr_reg.reg_value)) {
-				ctx->ctx_iear_counter = cnum;
-			} else if (PMC_IS_BTB(&tmp.pfr_reg.reg_value)) {
-				ctx->ctx_btb_counter = cnum;
+			p->pmc_oi = 1;
+		}
+
+		if (PMC_IS_COUNTING(cnum)) {
+			if (tmp.reg_flags & PFM_REGFL_OVFL_NOTIFY) {
+				/*
+				 * must have a target for the signal
+				 */
+				if (ctx->ctx_notify_task == NULL) {
+					ret = -EINVAL;
+					goto abort_mission;
+				}
+
+				ctx->ctx_soft_pmds[cnum].flags |= PFM_REGFL_OVFL_NOTIFY;
 			}
-#if 0
-			if (tmp.pfr_reg.reg_flags & PFM_REGFL_OVFL_NOTIFY)
-				ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags |= PFM_REGFL_OVFL_NOTIFY;
-#endif
+			/*
+			 * copy reset vector
+			 */
+			ctx->ctx_soft_pmds[cnum].reset_pmds[0] = tmp.reg_reset_pmds[0];
+			ctx->ctx_soft_pmds[cnum].reset_pmds[1] = tmp.reg_reset_pmds[1];
+			ctx->ctx_soft_pmds[cnum].reset_pmds[2] = tmp.reg_reset_pmds[2];
+			ctx->ctx_soft_pmds[cnum].reset_pmds[3] = tmp.reg_reset_pmds[3];
+
+			/*
+			 * needed in case the user does not initialize the equivalent
+			 * PMD. Clearing is done in reset_pmu() so there is no possible
+			 * leak here.
+			 */
+			CTX_USED_PMD(ctx, cnum);
 		}
-		/* keep track of what we use */
-		CTX_USED_PMC(ctx, cnum);
-		ia64_set_pmc(cnum, tmp.pfr_reg.reg_value);
+abort_mission:
+		if (ret == -EINVAL) reg_retval = PFM_REG_RETFL_EINVAL;
 
-		DBprintk((" setting PMC[%ld]=0x%lx flags=0x%x used_pmcs=0%lx\n", cnum, tmp.pfr_reg.reg_value, ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags, ctx->ctx_used_pmcs[0]));
+		PFM_REG_RETFLAG_SET(tmp.reg_flags, reg_retval);
 
-	}
-	/*
-	 * we have to set this here event hough we haven't necessarily started monitoring
-	 * because we may be context switched out
-	 */
-	if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
+		/*
+		 * update register return value, abort all if problem during copy.
+		 */
+		if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT;
 
-	return 0;
+		/*
+		 * if there was something wrong on this register, don't touch
+		 * the hardware at all and abort write request for others.
+		 *
+		 * On error, the user mut sequentially scan the table and the first
+		 * entry which has a return flag set is the one that caused the error.
+		 */
+		if (ret != 0) {
+			DBprintk(("[%d] pmc[%u]=0x%lx error %d\n",
+				  ta->pid, cnum, tmp.reg_value, reg_retval));
+			break;
+		}
+
+		/* 
+		 * We can proceed with this register!
+		 */
+		
+		/* 
+		 * keep copy the pmc, used for register reload
+		 */
+		th->pmc[cnum] = tmp.reg_value;
+
+		ia64_set_pmc(cnum, tmp.reg_value);
+
+		DBprintk(("[%d] pmc[%u]=0x%lx flags=0x%x save_pmcs=0%lx reload_pmcs=0x%lx\n", 
+			  ta->pid, cnum, tmp.reg_value, 
+			  ctx->ctx_soft_pmds[cnum].flags, 
+			  ctx->ctx_saved_pmcs[0], ctx->ctx_reload_pmcs[0]));
+
+	}
+	return ret;
 }
 
 static int
-pfm_write_pmds(struct task_struct *ta, perfmon_req_t *req, int count)
+pfm_write_pmds(struct task_struct *ta, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
 {
-	struct thread_struct *th = &ta->thread;
-	pfm_context_t *ctx = th->pfm_context;
-	perfmon_req_t tmp;
-	unsigned long cnum;
+	pfarg_reg_t tmp, *req = (pfarg_reg_t *)arg;
+	unsigned int cnum;
 	int i;
+	int ret = 0, reg_retval = 0;
+
+	/* we don't quite support this right now */
+	if (ta != current) return -EINVAL;
+
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
 
 	/* XXX: ctx locking may be required here */
 
 	for (i = 0; i < count; i++, req++) {
-		int k;
 
 		if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-		cnum = tmp.pfr_reg.reg_num;
-
-		k = cnum - PMU_FIRST_COUNTER;
+		cnum = tmp.reg_num;
 
-		if (!PMD_IS_IMPL(cnum)) return -EINVAL;
+		if (!PMD_IS_IMPL(cnum)) {
+			ret = -EINVAL;
+			goto abort_mission;
+		}
 
 		/* update virtualized (64bits) counter */
-		if (PMD_IS_COUNTER(cnum)) {
-			ctx->ctx_pmds[k].ival = tmp.pfr_reg.reg_value;
-			ctx->ctx_pmds[k].val  = tmp.pfr_reg.reg_value & ~pmu_conf.perf_ovfl_val;
-			ctx->ctx_pmds[k].smpl_rval = tmp.pfr_reg.reg_smpl_reset;
-			ctx->ctx_pmds[k].ovfl_rval = tmp.pfr_reg.reg_ovfl_reset;
+		if (PMD_IS_COUNTING(cnum)) {
+			ctx->ctx_soft_pmds[cnum].ival = tmp.reg_value;
+			ctx->ctx_soft_pmds[cnum].val  = tmp.reg_value & ~pmu_conf.perf_ovfl_val;
+			ctx->ctx_soft_pmds[cnum].long_reset = tmp.reg_long_reset;
+			ctx->ctx_soft_pmds[cnum].short_reset = tmp.reg_short_reset;
+
+		}
+abort_mission:
+		if (ret == -EINVAL) reg_retval = PFM_REG_RETFL_EINVAL;
+
+		PFM_REG_RETFLAG_SET(tmp.reg_flags, reg_retval);
 
-			if (tmp.pfr_reg.reg_flags & PFM_REGFL_OVFL_NOTIFY)
-				ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags |= PFM_REGFL_OVFL_NOTIFY;
+		if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT;
+
+		/*
+		 * if there was something wrong on this register, don't touch
+		 * the hardware at all and abort write request for others.
+		 *
+		 * On error, the user mut sequentially scan the table and the first
+		 * entry which has a return flag set is the one that caused the error.
+		 */
+		if (ret != 0) {
+			DBprintk(("[%d] pmc[%u]=0x%lx error %d\n",
+				  ta->pid, cnum, tmp.reg_value, reg_retval));
+			break;
 		}
+
 		/* keep track of what we use */
 		CTX_USED_PMD(ctx, cnum);
 
 		/* writes to unimplemented part is ignored, so this is safe */
-		ia64_set_pmd(cnum, tmp.pfr_reg.reg_value);
+		ia64_set_pmd(cnum, tmp.reg_value);
 
 		/* to go away */
 		ia64_srlz_d();
-		DBprintk((" setting PMD[%ld]:  ovfl_notify=%d pmd.val=0x%lx pmd.ovfl_rval=0x%lx pmd.smpl_rval=0x%lx pmd=%lx used_pmds=0%lx\n",
-					cnum,
-					PMD_OVFL_NOTIFY(ctx, cnum - PMU_FIRST_COUNTER),
-					ctx->ctx_pmds[k].val,
-					ctx->ctx_pmds[k].ovfl_rval,
-					ctx->ctx_pmds[k].smpl_rval,
-					ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val,
-					ctx->ctx_used_pmds[0]));
+		DBprintk(("[%d] pmd[%u]: soft_pmd=0x%lx  short_reset=0x%lx "
+			  "long_reset=0x%lx hw_pmd=%lx notify=%c used_pmds=0x%lx reset_pmds=0x%lx\n",
+				ta->pid, cnum,
+				ctx->ctx_soft_pmds[cnum].val,
+				ctx->ctx_soft_pmds[cnum].short_reset,
+				ctx->ctx_soft_pmds[cnum].long_reset,
+				ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val,
+				PMC_OVFL_NOTIFY(ctx, cnum) ? 'Y':'N',
+				ctx->ctx_used_pmds[0],
+				ctx->ctx_soft_pmds[cnum].reset_pmds[0]));
 	}
-	/*
-	 * we have to set this here event hough we haven't necessarily started monitoring
-	 * because we may be context switched out
-	 */
-	if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
-
-	return 0;
+	return ret;
 }
 
 static int
-pfm_read_pmds(struct task_struct *ta, perfmon_req_t *req, int count)
+pfm_read_pmds(struct task_struct *ta, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
 {
 	struct thread_struct *th = &ta->thread;
-	pfm_context_t *ctx = th->pfm_context;
 	unsigned long val=0;
-	perfmon_req_t tmp;
+	pfarg_reg_t tmp, *req = (pfarg_reg_t *)arg;
 	int i;
 
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
 	/*
 	 * XXX: MUST MAKE SURE WE DON"T HAVE ANY PENDING OVERFLOW BEFORE READING
-	 * This is required when the monitoring has been stoppped by user of kernel.
-	 * If ity is still going on, then that's fine because we a re not gauranteed
-	 * to return an accurate value in this case
+	 * This is required when the monitoring has been stoppped by user or kernel.
+	 * If it is still going on, then that's fine because we a re not guaranteed
+	 * to return an accurate value in this case.
 	 */
 
 	/* XXX: ctx locking may be required here */
 
+	DBprintk(("ctx_last_cpu=%d for [%d]\n", atomic_read(&ctx->ctx_last_cpu), ta->pid));
+
 	for (i = 0; i < count; i++, req++) {
-		unsigned long reg_val = ~0, ctx_val = ~0;
+		unsigned long reg_val = ~0UL, ctx_val = ~0UL;
 
 		if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-		if (!PMD_IS_IMPL(tmp.pfr_reg.reg_num)) return -EINVAL;
+		if (!PMD_IS_IMPL(tmp.reg_num)) goto abort_mission;
 
-		if (PMD_IS_COUNTER(tmp.pfr_reg.reg_num)) {
-			if (ta == current){
-				val = ia64_get_pmd(tmp.pfr_reg.reg_num);
-			} else {
-				val = reg_val = th->pmd[tmp.pfr_reg.reg_num];
+		/*
+		 * If the task is not the current one, then we check if the
+		 * PMU state is still in the local live register due to lazy ctxsw.
+		 * If true, then we read directly from the registers.
+		 */
+		if (atomic_read(&ctx->ctx_last_cpu) == smp_processor_id()){
+			ia64_srlz_d();
+			val = reg_val = ia64_get_pmd(tmp.reg_num);
+			DBprintk(("reading pmd[%u]=0x%lx from hw\n", tmp.reg_num, val));
+		} else {
+#ifdef CONFIG_SMP
+			int cpu;
+			/*
+			 * for SMP system, the context may still be live on another
+			 * CPU so we need to fetch it before proceeding with the read
+			 * This call we only be made once for the whole loop because
+			 * of ctx_last_cpu becoming == -1.
+			 *
+			 * We cannot reuse ctx_last_cpu as it may change before we get to the
+			 * actual IPI call. In this case, we will do the call for nothing but
+			 * there is no way around it. The receiving side will simply do nothing.
+			 */
+			cpu = atomic_read(&ctx->ctx_last_cpu);
+			if (cpu != -1) {
+				DBprintk(("must fetch on CPU%d for [%d]\n", cpu, ta->pid));
+				pfm_fetch_regs(cpu, ta, ctx);
 			}
-			val &= pmu_conf.perf_ovfl_val;
+#endif
+			/* context has been saved */
+			val = reg_val = th->pmd[tmp.reg_num];
+		}
+		if (PMD_IS_COUNTING(tmp.reg_num)) {
 			/*
-			 * lower part of .val may not be zero, so we must be an addition because of
-			 * residual count (see update_counters).
+			 * XXX: need to check for overflow
 			 */
-			val += ctx_val = ctx->ctx_pmds[tmp.pfr_reg.reg_num - PMU_FIRST_COUNTER].val;
+
+			val &= pmu_conf.perf_ovfl_val;
+			val += ctx_val = ctx->ctx_soft_pmds[tmp.reg_num].val;
 		} else {
-			/* for now */
-			if (ta != current) return -EINVAL;
 
-			ia64_srlz_d();
-			val = ia64_get_pmd(tmp.pfr_reg.reg_num);
+			val = reg_val = ia64_get_pmd(tmp.reg_num);
 		}
-		tmp.pfr_reg.reg_value = val;
+		PFM_REG_RETFLAG_SET(tmp.reg_flags, 0);
+		tmp.reg_value = val;
 
-		DBprintk((" reading PMD[%ld]=0x%lx reg=0x%lx ctx_val=0x%lx pmc=0x%lx\n", 
-					tmp.pfr_reg.reg_num, val, reg_val, ctx_val, ia64_get_pmc(tmp.pfr_reg.reg_num)));
+		DBprintk(("read pmd[%u] soft_pmd=0x%lx reg=0x%lx pmc=0x%lx\n", 
+					tmp.reg_num, ctx_val, reg_val, 
+					ia64_get_pmc(tmp.reg_num)));
 
 		if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT;
 	}
 	return 0;
+abort_mission:
+	PFM_REG_RETFLAG_SET(tmp.reg_flags, PFM_REG_RETFL_EINVAL);
+	/* 
+	 * XXX: if this fails, we stick we the original failure, flag not updated!
+	 */
+	copy_to_user(req, &tmp, sizeof(tmp));
+	return -EINVAL;
+
+}
+
+#ifdef PFM_PMU_USES_DBR
+/*
+ * Only call this function when a process it trying to
+ * write the debug registers (reading is always allowed)
+ */
+int
+pfm_use_debug_registers(struct task_struct *task)
+{
+	pfm_context_t *ctx = task->thread.pfm_context;
+	int ret = 0;
+
+	DBprintk(("called for [%d]\n", task->pid));
+
+	/*
+	 * do it only once
+	 */
+	if (task->thread.flags & IA64_THREAD_DBG_VALID) return 0;
+
+	/*
+	 * Even on SMP, we do not need to use an atomic here because
+	 * the only way in is via ptrace() and this is possible only when the
+	 * process is stopped. Even in the case where the ctxsw out is not totally
+	 * completed by the time we come here, there is no way the 'stopped' process
+	 * could be in the middle of fiddling with the pfm_write_ibr_dbr() routine.
+	 * So this is always safe.
+	 */
+	if (ctx && ctx->ctx_fl_using_dbreg == 1) return -1;
+
+	/*
+	 * XXX: not pretty
+	 */
+	LOCK_PFS();
+
+	/*
+	 * We only allow the use of debug registers when there is no system
+	 * wide monitoring 
+	 * XXX: we could relax this by 
+	 */
+	if (pfm_sessions.pfs_sys_use_dbregs> 0)
+		ret = -1;
+	else
+		pfm_sessions.pfs_ptrace_use_dbregs++;
+
+	DBprintk(("ptrace_use_dbregs=%lu  sys_use_dbregs=%lu by [%d] ret = %d\n", 
+		  pfm_sessions.pfs_ptrace_use_dbregs, 
+		  pfm_sessions.pfs_sys_use_dbregs, 
+		  task->pid, ret));
+
+	UNLOCK_PFS();
+
+	return ret;
+}
+
+/*
+ * This function is called for every task that exits with the
+ * IA64_THREAD_DBG_VALID set. This indicates a task which was
+ * able to use the debug registers for debugging purposes via
+ * ptrace(). Therefore we know it was not using them for
+ * perfmormance monitoring, so we only decrement the number
+ * of "ptraced" debug register users to keep the count up to date
+ */
+int
+pfm_release_debug_registers(struct task_struct *task)
+{
+	int ret;
+
+	LOCK_PFS();
+	if (pfm_sessions.pfs_ptrace_use_dbregs == 0) {
+		printk("perfmon: invalid release for [%d] ptrace_use_dbregs=0\n", task->pid);
+		ret = -1;
+	}  else {
+		pfm_sessions.pfs_ptrace_use_dbregs--;
+		ret = 0;
+	}
+	UNLOCK_PFS();
+
+	return ret;
+}
+#else /* PFM_PMU_USES_DBR is true */
+/*
+ * in case, the PMU does not use the debug registers, these two functions are nops.
+ * The first function is called from arch/ia64/kernel/ptrace.c.
+ * The second function is called from arch/ia64/kernel/process.c.
+ */
+int
+pfm_use_debug_registers(struct task_struct *task)
+{
+	return 0;
+}
+int
+pfm_release_debug_registers(struct task_struct *task)
+{
+	return 0;
 }
+#endif /* PFM_PMU_USES_DBR */
 
 static int
-pfm_do_restart(struct task_struct *task)
+pfm_restart(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
 {
-	struct thread_struct *th = &task->thread;
-	pfm_context_t *ctx = th->pfm_context;
 	void *sem = &ctx->ctx_restart_sem;
 
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+
+	if (ctx->ctx_fl_frozen==0) {
+		printk("task %d without pmu_frozen set\n", task->pid);
+		return -EINVAL;
+	}
+
 	if (task == current) {
-		DBprintk((" restarting self %d frozen=%d \n", current->pid, ctx->ctx_fl_frozen));
+		DBprintk(("restarting self %d frozen=%d \n", current->pid, ctx->ctx_fl_frozen));
+
+		pfm_reset_regs(ctx, ctx->ctx_ovfl_regs, PFM_RELOAD_LONG_RESET);
 
-		pfm_reset_regs(ctx);
+		ctx->ctx_ovfl_regs[0] = 0UL;
 
 		/*
 		 * We ignore block/don't block because we never block
@@ -1011,26 +1554,36 @@
 		ctx->ctx_fl_frozen = 0;
 
 		if (CTX_HAS_SMPL(ctx)) {
-			ctx->ctx_smpl_buf->psb_hdr->hdr_count = 0;
-			ctx->ctx_smpl_buf->psb_index = 0;
+			ctx->ctx_psb->psb_hdr->hdr_count = 0;
+			ctx->ctx_psb->psb_index = 0;
 		}
 
-		/* pfm_reset_smpl_buffers(ctx,th->pfm_ovfl_regs);*/
-
 		/* simply unfreeze */
 		ia64_set_pmc(0, 0);
 		ia64_srlz_d();
 
 		return 0;
-	}
+	} 
+	/* restart on another task */
 
-	/* check if blocking */
+	/*
+	 * if blocking, then post the semaphore.
+	 * if non-blocking, then we ensure that the task will go into
+	 * pfm_overflow_must_block() before returning to user mode. 
+	 * We cannot explicitely reset another task, it MUST always
+	 * be done by the task itself. This works for system wide because
+	 * the tool that is controlling the session is doing "self-monitoring".
+	 *
+	 * XXX: what if the task never goes back to user?
+	 *
+	 */
 	if (CTX_OVFL_NOBLOCK(ctx) == 0) {
-		DBprintk((" unblocking %d \n", task->pid));
+		DBprintk(("unblocking %d \n", task->pid));
 		up(sem);
-		return 0;
+	} else {
+		task->thread.pfm_ovfl_block_reset = 1;
 	}
-
+#if 0
 	/*
 	 * in case of non blocking mode, then it's just a matter of
 	 * of reseting the sampling buffer (if any) index. The PMU
@@ -1041,281 +1594,719 @@
 	 * must reset the header count first
 	 */
 	if (CTX_HAS_SMPL(ctx)) {
-		DBprintk((" resetting sampling indexes for %d \n", task->pid));
-		ctx->ctx_smpl_buf->psb_hdr->hdr_count = 0;
-		ctx->ctx_smpl_buf->psb_index = 0;
+		DBprintk(("resetting sampling indexes for %d \n", task->pid));
+		ctx->ctx_psb->psb_hdr->hdr_count = 0;
+		ctx->ctx_psb->psb_index = 0;
 	}
-
+#endif
 	return 0;
 }
 
+#ifndef CONFIG_SMP
 /*
- * system-wide mode: propagate activation/desactivation throughout the tasklist
- *
- * XXX: does not work for SMP, of course
+ * On UP kernels, we do not need to constantly set the psr.pp bit
+ * when a task is scheduled. The psr.pp bit can only be changed in
+ * the kernel because of a user request. Given we are on a UP non preeemptive 
+ * kernel we know that no other task is running, so we cna simply update their
+ * psr.pp from their saved state. There is this no impact on the context switch
+ * code compared to the SMP case.
  */
 static void
-pfm_process_tasklist(int cmd)
+pfm_tasklist_toggle_pp(unsigned int val)
 {
 	struct task_struct *p;
 	struct pt_regs *regs;
 
+	DBprintk(("invoked by [%d] pp=%u\n", current->pid, val));
+
+	read_lock(&tasklist_lock);
+
 	for_each_task(p) {
-		regs = (struct pt_regs *)((unsigned long)p + IA64_STK_OFFSET);
+       		regs = (struct pt_regs *)((unsigned long) p + IA64_STK_OFFSET);
+
+		/*
+		 * position on pt_regs saved on stack on 1st entry into the kernel
+		 */
 		regs--;
-		ia64_psr(regs)->pp = cmd;
+
+		/*
+		 * update psr.pp
+		 */
+		ia64_psr(regs)->pp = val;
 	}
+	read_unlock(&tasklist_lock);
 }
+#endif
+
+
 
 static int
-do_perfmonctl (struct task_struct *task, int cmd, int flags, perfmon_req_t *req, int count, struct pt_regs *regs)
+pfm_stop(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
 {
-	perfmon_req_t tmp;
-	struct thread_struct *th = &task->thread;
-	pfm_context_t *ctx = th->pfm_context;
-
-	memset(&tmp, 0, sizeof(tmp));
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-	if (ctx == NULL && cmd != PFM_CREATE_CONTEXT && cmd < PFM_DEBUG_BASE) {
-		DBprintk((" PFM_WRITE_PMCS: no context for task %d\n", task->pid));
-		return -EINVAL;
-	}
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
-	switch (cmd) {
-		case PFM_CREATE_CONTEXT:
-			/* a context has already been defined */
-			if (ctx) return -EBUSY;
+	DBprintk(("[%d] fl_system=%d owner=%p current=%p\n",
+				current->pid,
+				ctx->ctx_fl_system, PMU_OWNER(),
+				current));
+	/* simply stop monitoring but not the PMU */
+	if (ctx->ctx_fl_system) {
 
-			/*
-			 * cannot directly create a context in another process
-			 */
-			if (task != current) return -EINVAL;
+		__asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
 
-			if (req == NULL || count != 1) return -EINVAL;
+		/* disable dcr pp */
+		ia64_set_dcr(ia64_get_dcr() & ~IA64_DCR_PP);
 
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_dcr_pp  = 0;
+#else
+		pfm_tasklist_toggle_pp(0);
+#endif
 
-			return pfm_context_create(flags, req);
+		ia64_psr(regs)->pp = 0;
 
-		case PFM_WRITE_PMCS:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+	} else {
+		__asm__ __volatile__ ("rum psr.up;;"::: "memory");
 
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
+		ia64_psr(regs)->up = 0;
+	}
+	return 0;
+}
 
-			return pfm_write_pmcs(task, req, count);
+static int
+pfm_disable(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	   struct pt_regs *regs)
+{	
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-		case PFM_WRITE_PMDS:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
+	/*
+	 * stop monitoring, freeze PMU, and save state in context
+	 * this call will clear IA64_THREAD_PM_VALID for per-task sessions.
+	 */
+	pfm_flush_regs(task);
 
-			return pfm_write_pmds(task, req, count);
+	if (ctx->ctx_fl_system) {	
+		ia64_psr(regs)->pp = 0;
+	} else {
+		ia64_psr(regs)->up = 0;
+	}
+	/* 
+	 * goes back to default behavior 
+	 * no need to change live psr.sp because useless at the kernel level
+	 */
+	ia64_psr(regs)->sp = 1;
 
-		case PFM_START:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+	DBprintk(("enabling psr.sp for [%d]\n", current->pid));
 
-			if (PMU_OWNER()  && PMU_OWNER() != current && PFM_CAN_DO_LAZY()) pfm_lazy_save_regs(PMU_OWNER());
+	ctx->ctx_flags.state = PFM_CTX_DISABLED;
 
-			SET_PMU_OWNER(current);
+	return 0;
+}
 
-			/* will start monitoring right after rfi */
-			ia64_psr(regs)->up = 1;
-			ia64_psr(regs)->pp = 1;
 
-			if (ctx->ctx_fl_system) {
-				pfm_process_tasklist(1);
-				pfs_info.pfs_pp = 1;
-			}
 
-			/*
-			 * mark the state as valid.
-			 * this will trigger save/restore at context switch
-			 */
-			if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
+static int
+pfm_destroy_context(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-			ia64_set_pmc(0, 0);
-			ia64_srlz_d();
+	/*
+	 * if context was never enabled, then there is not much
+	 * to do
+	 */
+	if (!CTX_IS_ENABLED(ctx)) goto skipped_stop;
 
-			break;
+	/*
+	 * Disable context: stop monitoring, flush regs to software state (useless here), 
+	 * and freeze PMU
+	 * 
+	 * The IA64_THREAD_PM_VALID is cleared by pfm_flush_regs() called from pfm_disable()
+	 */
+	pfm_disable(task, ctx, arg, count, regs);
 
-		case PFM_ENABLE:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+	if (ctx->ctx_fl_system) {	
+		ia64_psr(regs)->pp = 0;
+	} else {
+		ia64_psr(regs)->up = 0;
+	}
 
-			if (PMU_OWNER()  && PMU_OWNER() != current && PFM_CAN_DO_LAZY()) pfm_lazy_save_regs(PMU_OWNER());
+	/* restore security level */
+	ia64_psr(regs)->sp = 1;
 
-			/* reset all registers to stable quiet state */
-			ia64_reset_pmu();
+skipped_stop:
+	/*
+	 * remove sampling buffer mapping, if any
+	 */
+	if (ctx->ctx_smpl_vaddr) pfm_remove_smpl_mapping(task);
 
-			/* make sure nothing starts */
-			ia64_psr(regs)->up = 0;
-			ia64_psr(regs)->pp = 0;
+	/* now free context and related state */
+	pfm_context_exit(task);
 
-			/* do it on the live register as well */
-			__asm__ __volatile__ ("rsm psr.pp|psr.pp;;"::: "memory");
+	return 0;
+}
 
-			SET_PMU_OWNER(current);
+/*
+ * does nothing at the moment
+ */
+static int
+pfm_unprotect_context(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	return 0;
+}
 
-			/*
-			 * mark the state as valid.
-			 * this will trigger save/restore at context switch
-			 */
-			if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
+static int
+pfm_protect_context(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	DBprintk(("context from [%d] is protected\n", task->pid));
+	/*
+	 * from now on, only the creator of the context has access to it
+	 */
+	ctx->ctx_fl_protected = 1;
 
-			/* simply unfreeze */
-			ia64_set_pmc(0, 0);
-			ia64_srlz_d();
-			break;
+	/*
+	 * reinforce secure monitoring: cannot toggle psr.up
+	 */
+	ia64_psr(regs)->sp = 1;
 
-		case PFM_DISABLE:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+	return 0;
+}
 
-			/* simply freeze */
-			ia64_set_pmc(0, 1);
-			ia64_srlz_d();
-			/*
-			 * XXX: cannot really toggle IA64_THREAD_PM_VALID
-			 * but context is still considered valid, so any 
-			 * read request would return something valid. Same
-			 * thing when this task terminates (pfm_flush_regs()).
-			 */
-			break;
+static int
+pfm_debug(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	unsigned int mode = *(unsigned int *)arg;
 
-		case PFM_READ_PMDS:
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
-			if (!access_ok(VERIFY_WRITE, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
-
-			return pfm_read_pmds(task, req, count);
-
-	      case PFM_STOP:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
-
-			/* simply stop monitors, not PMU */
-			ia64_psr(regs)->up = 0;
-			ia64_psr(regs)->pp = 0;
-
-			if (ctx->ctx_fl_system) {
-				pfm_process_tasklist(0);
-				pfs_info.pfs_pp = 0;
-			}
+	pfm_debug_mode = mode == 0 ? 0 : 1;
 
-			break;
+	printk("perfmon debugging %s\n", pfm_debug_mode ? "on" : "off");
+
+	return 0;
+}
+
+#ifdef PFM_PMU_USES_DBR
+
+typedef struct {
+	unsigned long ibr_mask:56;
+	unsigned long ibr_plm:4;
+	unsigned long ibr_ig:3;
+	unsigned long ibr_x:1;
+} ibr_mask_reg_t;
+
+typedef struct {
+	unsigned long dbr_mask:56;
+	unsigned long dbr_plm:4;
+	unsigned long dbr_ig:2;
+	unsigned long dbr_w:1;
+	unsigned long dbr_r:1;
+} dbr_mask_reg_t;
+
+typedef union {
+	unsigned long  val;
+	ibr_mask_reg_t ibr;
+	dbr_mask_reg_t dbr;
+} dbreg_t;
+
+
+static int
+pfm_write_ibr_dbr(int mode, struct task_struct *task, void *arg, int count, struct pt_regs *regs)
+{
+	struct thread_struct *thread = &task->thread;
+	pfm_context_t *ctx = task->thread.pfm_context;
+	pfarg_dbreg_t tmp, *req = (pfarg_dbreg_t *)arg;
+	dbreg_t dbreg;
+	unsigned int rnum;
+	int first_time;
+	int i, ret = 0;
+
+	/*
+	 * for range restriction: psr.db must be cleared or the
+	 * the PMU will ignore the debug registers.
+	 *
+	 * XXX: may need more in system wide mode,
+	 * no task can have this bit set?
+	 */
+	if (ia64_psr(regs)->db == 1) return -EINVAL;
+
+
+	first_time = ctx->ctx_fl_using_dbreg == 0;
+
+	/*
+	 * check for debug registers in system wide mode
+	 *
+	 */
+	LOCK_PFS();
+	if (ctx->ctx_fl_system && first_time) {
+		if (pfm_sessions.pfs_ptrace_use_dbregs) 
+			ret = -EBUSY;
+		else
+			pfm_sessions.pfs_sys_use_dbregs++;
+	}
+	UNLOCK_PFS();
 
-	      case PFM_RESTART: /* temporary, will most likely end up as a PFM_ENABLE */
+	if (ret != 0) return ret;
 
-			if ((th->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system==0) {
-				printk(" PFM_RESTART not monitoring\n");
-				return -EINVAL;
+	if (ctx->ctx_fl_system) {
+		/* we mark ourselves as owner  of the debug registers */
+		ctx->ctx_fl_using_dbreg = 1;
+	} else {
+       		if (ctx->ctx_fl_using_dbreg == 0) {
+			ret= -EBUSY;
+			if ((thread->flags & IA64_THREAD_DBG_VALID) != 0) {
+				DBprintk(("debug registers already in use for [%d]\n", task->pid));
+				goto abort_mission;
+			}
+			/* we mark ourselves as owner  of the debug registers */
+			ctx->ctx_fl_using_dbreg = 1;
+
+			/* 
+			 * Given debug registers cannot be used for both debugging 
+			 * and performance monitoring at the same time, we reuse
+			 * the storage area to save and restore the registers on ctxsw.
+			 */
+			memset(task->thread.dbr, 0, sizeof(task->thread.dbr));
+			memset(task->thread.ibr, 0, sizeof(task->thread.ibr));
+
+			/*
+			 * clear hardware registers to make sure we don't leak
+			 * information and pick up stale state
+			 */
+			for (i=0; i < pmu_conf.num_ibrs; i++) {
+				ia64_set_ibr(i, 0UL);
 			}
-			if (CTX_OVFL_NOBLOCK(ctx) == 0 && ctx->ctx_fl_frozen==0) {
-				printk("task %d without pmu_frozen set\n", task->pid);
-				return -EINVAL;
+			for (i=0; i < pmu_conf.num_dbrs; i++) {
+				ia64_set_dbr(i, 0UL);
 			}
+		}
+	}
 
-			return pfm_do_restart(task); /* we only look at first entry */
+	ret = -EFAULT;
 
-	      case PFM_DESTROY_CONTEXT:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
-
-			/* first stop monitors */
-			ia64_psr(regs)->up = 0;
-			ia64_psr(regs)->pp = 0;
+	/*
+	 * Now install the values into the registers
+	 */
+	for (i = 0; i < count; i++, req++) {
 
-			/* then freeze PMU */
-			ia64_set_pmc(0, 1);
-			ia64_srlz_d();
+		
+		if (copy_from_user(&tmp, req, sizeof(tmp))) goto abort_mission;
+		
+		rnum      = tmp.dbreg_num;
+		dbreg.val = tmp.dbreg_value;
+		
+		ret = -EINVAL;
 
-			/* don't save/restore on context switch */
-			if (ctx->ctx_fl_system ==0) task->thread.flags &= ~IA64_THREAD_PM_VALID;
+		if ((mode == 0 && !IBR_IS_IMPL(rnum)) || ((mode == 1) && !DBR_IS_IMPL(rnum))) {
+			DBprintk(("invalid register %u val=0x%lx mode=%d i=%d count=%d\n", 
+				  rnum, dbreg.val, mode, i, count));
 
-			SET_PMU_OWNER(NULL);
+			goto abort_mission;
+		}
 
-			/* now free context and related state */
-			pfm_context_exit(task);
-			break;
+		/*
+		 * make sure we do not install enabled breakpoint
+		 */
+		if (rnum & 0x1) {
+			if (mode == 0) 
+				dbreg.ibr.ibr_x = 0;
+			else
+				dbreg.dbr.dbr_r = dbreg.dbr.dbr_w = 0;
+		}
 
-	      case PFM_DEBUG_ON:
-			printk("perfmon debugging on\n");
-			pfm_debug = 1;
-			break;
+		/*
+		 * clear return flags and copy back to user
+		 *
+		 * XXX: fix once EAGAIN is implemented
+		 */
+		ret = -EFAULT;
 
-	      case PFM_DEBUG_OFF:
-			printk("perfmon debugging off\n");
-			pfm_debug = 0;
-			break;
+		PFM_REG_RETFLAG_SET(tmp.dbreg_flags, 0);
+
+		if (copy_to_user(req, &tmp, sizeof(tmp))) goto abort_mission;
+
+		/*
+		 * Debug registers, just like PMC, can only be modified
+		 * by a kernel call. Moreover, perfmon() access to those
+		 * registers are centralized in this routine. The hardware
+		 * does not modify the value of these registers, therefore,
+		 * if we save them as they are written, we can avoid having
+		 * to save them on context switch out. This is made possible
+		 * by the fact that when perfmon uses debug registers, ptrace()
+		 * won't be able to modify them concurrently.
+		 */
+		if (mode == 0) {
+			CTX_USED_IBR(ctx, rnum);
+
+			ia64_set_ibr(rnum, dbreg.val);
 
-	      default:
-			DBprintk((" UNknown command 0x%x\n", cmd));
+			thread->ibr[rnum] = dbreg.val;
+
+			DBprintk(("write ibr%u=0x%lx used_ibrs=0x%lx\n", rnum, dbreg.val, ctx->ctx_used_ibrs[0]));
+		} else {
+			CTX_USED_DBR(ctx, rnum);
+
+			ia64_set_dbr(rnum, dbreg.val);
+
+			thread->dbr[rnum] = dbreg.val;
+
+			DBprintk(("write dbr%u=0x%lx used_dbrs=0x%lx\n", rnum, dbreg.val, ctx->ctx_used_dbrs[0]));
+		}
+	}
+
+	return 0;
+
+abort_mission:
+	/*
+	 * in case it was our first attempt, we undo the global modifications
+	 */
+	if (first_time) {
+		LOCK_PFS();
+		if (ctx->ctx_fl_system) {
+			pfm_sessions.pfs_sys_use_dbregs--;
+		}
+		UNLOCK_PFS();
+		ctx->ctx_fl_using_dbreg = 0;
+	}
+	/*
+	 * install error return flag
+	 */
+	if (ret != -EFAULT) {
+		/*
+		 * XXX: for now we can only come here on EINVAL
+		 */
+		PFM_REG_RETFLAG_SET(tmp.dbreg_flags, PFM_REG_RETFL_EINVAL);
+		copy_to_user(req, &tmp, sizeof(tmp));
+	}
+	return ret;
+}
+
+static int
+pfm_write_ibrs(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{	
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+	return pfm_write_ibr_dbr(0, task, arg, count, regs);
+}
+
+static int
+pfm_write_dbrs(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{	
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+	return pfm_write_ibr_dbr(1, task, arg, count, regs);
+}
+
+#endif /* PFM_PMU_USES_DBR */
+
+static int
+pfm_get_features(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
+{
+	pfarg_features_t tmp;
+
+	memset(&tmp, 0, sizeof(tmp));
+
+	tmp.ft_version      = PFM_VERSION;
+	tmp.ft_smpl_version = PFM_SMPL_VERSION;
+
+	if (copy_to_user(arg, &tmp, sizeof(tmp))) return -EFAULT;
+
+	return 0;
+}
+
+static int
+pfm_start(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	  struct pt_regs *regs)
+{
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+	DBprintk(("[%d] fl_system=%d owner=%p current=%p\n",
+				current->pid,
+				ctx->ctx_fl_system, PMU_OWNER(),
+				current));
+
+	if (PMU_OWNER() != task) {
+		printk("perfmon: pfm_start task [%d] not pmu owner\n", task->pid);
+		return -EINVAL;
+	}
+
+	if (ctx->ctx_fl_system) {
+		
+		/* enable dcr pp */
+		ia64_set_dcr(ia64_get_dcr()|IA64_DCR_PP);
+
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_dcr_pp  = 1;
+#else
+		pfm_tasklist_toggle_pp(1);
+#endif
+		ia64_psr(regs)->pp = 1;
+
+		__asm__ __volatile__ ("ssm psr.pp;;"::: "memory");
+
+	} else {
+		if ((task->thread.flags & IA64_THREAD_PM_VALID) == 0) {
+			printk("perfmon: pfm_start task flag not set for [%d]\n", task->pid);
 			return -EINVAL;
+		}
+		ia64_psr(regs)->up = 1;
+		__asm__ __volatile__ ("sum psr.up;;"::: "memory");
+	}
+	ia64_srlz_d();
+
+	return 0;
+}
+
+static int
+pfm_enable(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	   struct pt_regs *regs)
+{
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	if (ctx->ctx_fl_system == 0 && PMU_OWNER()  && PMU_OWNER() != current) 
+		pfm_lazy_save_regs(PMU_OWNER());
+
+	/* reset all registers to stable quiet state */
+	ia64_reset_pmu(task);
+
+	/* make sure nothing starts */
+	if (ctx->ctx_fl_system) {
+		ia64_psr(regs)->pp = 0;
+		ia64_psr(regs)->up = 0; /* just to make sure! */
+
+		__asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
+
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_syst_wide = 1;
+		local_cpu_data->pfm_dcr_pp    = 0;
+#endif
+	} else {
+		/*
+		 * needed in case the task was a passive task during
+		 * a system wide session and now wants to have its own
+		 * session
+		 */
+		ia64_psr(regs)->pp = 0; /* just to make sure! */
+		ia64_psr(regs)->up = 0;
+
+		__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+		/*
+		 * allow user control (user monitors only)
+		if (task  == ctx->ctx_owner) {
+		 */
+		{
+			DBprintk(("clearing psr.sp for [%d]\n", current->pid));
+			ia64_psr(regs)->sp = 0;
+		}
+		task->thread.flags |= IA64_THREAD_PM_VALID;
 	}
+
+	SET_PMU_OWNER(task);
+
+
+	ctx->ctx_flags.state = PFM_CTX_ENABLED;
+	atomic_set(&ctx->ctx_last_cpu, smp_processor_id());
+
+	/* simply unfreeze */
+	ia64_set_pmc(0, 0);
+	ia64_srlz_d();
+
 	return 0;
 }
 
 /*
- * XXX: do something better here
+ * functions MUST be listed in the increasing order of their index (see permfon.h)
  */
+static pfm_cmd_desc_t pfm_cmd_tab[]={
+/* 0  */{ NULL, 0, 0, 0}, /* not used */
+/* 1  */{ pfm_write_pmcs, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_reg_t)}, 
+/* 2  */{ pfm_write_pmds, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ, PFM_CMD_ARG_MANY, sizeof(pfarg_reg_t)},
+/* 3  */{ pfm_read_pmds, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_reg_t)},
+/* 4  */{ pfm_stop, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 5  */{ pfm_start, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 6  */{ pfm_enable, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 7  */{ pfm_disable, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 8  */{ pfm_create_context, PFM_CMD_ARG_READ, 1, sizeof(pfarg_context_t)},
+/* 9  */{ pfm_destroy_context, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 10 */{ pfm_restart, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_NOCHK, 0, 0},
+/* 11 */{ pfm_protect_context, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 12 */{ pfm_get_features, PFM_CMD_ARG_WRITE, 0, 0},
+/* 13 */{ pfm_debug, 0, 1, sizeof(unsigned int)},
+/* 14 */{ pfm_unprotect_context, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 15 */{ NULL, 0, 0, 0}, /* not used */
+/* 16 */{ NULL, 0, 0, 0}, /* not used */
+/* 17 */{ NULL, 0, 0, 0}, /* not used */
+/* 18 */{ NULL, 0, 0, 0}, /* not used */
+/* 19 */{ NULL, 0, 0, 0}, /* not used */
+/* 20 */{ NULL, 0, 0, 0}, /* not used */
+/* 21 */{ NULL, 0, 0, 0}, /* not used */
+/* 22 */{ NULL, 0, 0, 0}, /* not used */
+/* 23 */{ NULL, 0, 0, 0}, /* not used */
+/* 24 */{ NULL, 0, 0, 0}, /* not used */
+/* 25 */{ NULL, 0, 0, 0}, /* not used */
+/* 26 */{ NULL, 0, 0, 0}, /* not used */
+/* 27 */{ NULL, 0, 0, 0}, /* not used */
+/* 28 */{ NULL, 0, 0, 0}, /* not used */
+/* 29 */{ NULL, 0, 0, 0}, /* not used */
+/* 30 */{ NULL, 0, 0, 0}, /* not used */
+/* 31 */{ NULL, 0, 0, 0}, /* not used */
+#ifdef PFM_PMU_USES_DBR
+/* 32 */{ pfm_write_ibrs, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_dbreg_t)},
+/* 33 */{ pfm_write_dbrs, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_dbreg_t)}
+#endif
+};
+#define PFM_CMD_COUNT	(sizeof(pfm_cmd_tab)/sizeof(pfm_cmd_desc_t))
+
 static int
-perfmon_bad_permissions(struct task_struct *task)
+check_task_state(struct task_struct *task)
 {
-	/* stolen from bad_signal() */
-	return (current->session != task->session)
-	    && (current->euid ^ task->suid) && (current->euid ^ task->uid)
-	    && (current->uid ^ task->suid) && (current->uid ^ task->uid);
+	int ret = 0;
+#ifdef CONFIG_SMP
+	/* We must wait until the state has been completely
+	 * saved. There can be situations where the reader arrives before
+	 * after the task is marked as STOPPED but before pfm_save_regs()
+	 * is completed.
+	 */
+	for (;;) {
+
+		task_lock(task);
+		if (!task_has_cpu(task)) break;
+		task_unlock(task);
+
+		do {
+			if (task->state != TASK_ZOMBIE && task->state != TASK_STOPPED) return -EBUSY;
+			barrier();
+			cpu_relax();
+		} while (task_has_cpu(task));
+	}
+	task_unlock(task);
+#else
+	if (task->state != TASK_ZOMBIE && task->state != TASK_STOPPED) {
+		DBprintk(("warning [%d] not in stable state %ld\n", task->pid, task->state));
+		ret = -EBUSY;
+	}
+#endif
+	return ret;
 }
 
 asmlinkage int
-sys_perfmonctl (int pid, int cmd, int flags, perfmon_req_t *req, int count, long arg6, long arg7, long arg8, long stack)
+sys_perfmonctl (pid_t pid, int cmd, void *arg, int count, long arg5, long arg6, long arg7, 
+		long arg8, long stack)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
-	struct task_struct *child = current;
-	int ret = -ESRCH;
+	struct pt_regs *regs = (struct pt_regs *)&stack;
+	struct task_struct *task = current;
+	pfm_context_t *ctx = task->thread.pfm_context;
+	size_t sz;
+	int ret = -ESRCH, narg;
 
-	/* sanity check:
-	 *
-	 * ensures that we don't do bad things in case the OS
-	 * does not have enough storage to save/restore PMC/PMD
+	/* 
+	 * reject any call if perfmon was disabled at initialization time
 	 */
-	if (PERFMON_IS_DISABLED()) return -ENOSYS;
+	if (PFM_IS_DISABLED()) return -ENOSYS;
 
-	/* XXX: pid interface is going away in favor of pfm context */
-	if (pid != current->pid) {
-		read_lock(&tasklist_lock);
+	DBprintk(("cmd=%d idx=%d valid=%d narg=0x%x\n", cmd, PFM_CMD_IDX(cmd), 
+		  PFM_CMD_IS_VALID(cmd), PFM_CMD_NARG(cmd)));
 
-		child = find_task_by_pid(pid);
+	if (PFM_CMD_IS_VALID(cmd) == 0) return -EINVAL;
 
-		if (!child) goto abort_call;
+	/* ingore arguments when command has none */
+	narg = PFM_CMD_NARG(cmd);
+	if ((narg == PFM_CMD_ARG_MANY  && count == 0) || (narg > 0 && narg != count)) return -EINVAL;
 
-		ret = -EPERM;
+	sz = PFM_CMD_ARG_SIZE(cmd);
 
-		if (perfmon_bad_permissions(child)) goto abort_call;
+	if (PFM_CMD_READ_ARG(cmd) && !access_ok(VERIFY_READ, arg, sz*count)) return -EFAULT;
 
-		/*
-		 * XXX: need to do more checking here
+	if (PFM_CMD_WRITE_ARG(cmd) && !access_ok(VERIFY_WRITE, arg, sz*count)) return -EFAULT;
+
+	if (PFM_CMD_USE_PID(cmd))  {
+		/* 
+		 * XXX: may need to fine tune this one
 		 */
-		if (child->state != TASK_ZOMBIE && child->state != TASK_STOPPED) {
-			DBprintk((" warning process %d not in stable state %ld\n", pid, child->state));
+		if (pid < 2) return -EPERM;
+
+		if (pid != current->pid) {
+
+			read_lock(&tasklist_lock);
+
+			task = find_task_by_pid(pid);
+
+			if (!task) goto abort_call;
+
+			ret = -EPERM;
+
+			if (pfm_bad_permissions(task)) goto abort_call;
+
+			if (PFM_CMD_CHK(cmd)) {
+				ret = check_task_state(task);
+				if (ret != 0) goto abort_call;
+			}
+			ctx = task->thread.pfm_context;
 		}
+	} 
+
+	if (PFM_CMD_USE_CTX(cmd)) {
+		ret = -EINVAL;
+	       if (ctx == NULL) {
+			DBprintk(("no context for task %d\n", task->pid));
+			goto abort_call;
+	       }
+	       ret = -EPERM;
+	       /*
+		* we only grant access to the context if:
+		* 	- the caller is the creator of the context (ctx_owner)
+		*  OR   - the context is attached to the caller AND The context IS NOT 
+		*  	  in protected mode
+		*/
+	       if (ctx->ctx_owner != current && (ctx->ctx_fl_protected || task != current)) {
+				DBprintk(("context protected, no access for [%d]\n", task->pid));
+				goto abort_call;
+	       }
 	}
-	ret = do_perfmonctl(child, cmd, flags, req, count, regs);
+
+	ret = (*pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_func)(task, ctx, arg, count, regs);
 
 abort_call:
-	if (child != current) read_unlock(&tasklist_lock);
+	if (task != current) read_unlock(&tasklist_lock);
 
 	return ret;
 }
 
 #if __GNUC__ >= 3
 void asmlinkage
-pfm_block_on_overflow(void)
+pfm_ovfl_block_reset(u64 arg0, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, 
+		      u64 arg6, u64 arg7, long info)
 #else
 void asmlinkage
-pfm_block_on_overflow(u64 arg0, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7)
+pfm_ovfl_block_reset(u64 arg0, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, 
+		      u64 arg6, u64 arg7, long info)
 #endif
 {
 	struct thread_struct *th = &current->thread;
@@ -1323,32 +2314,22 @@
 	int ret;
 
 	/*
-	 * NO matter what notify_pid is,
-	 * we clear overflow, won't notify again
+	 * clear the flag, to make sure we won't get here
+	 * again
 	 */
-	th->pfm_must_block = 0;
+	th->pfm_ovfl_block_reset = 0;
 
 	/*
 	 * do some sanity checks first
 	 */
 	if (!ctx) {
-		printk("perfmon: process %d has no PFM context\n", current->pid);
-		return;
-	}
-	if (ctx->ctx_notify_task == 0) {
-		printk("perfmon: process %d has no task to notify\n", current->pid);
+		printk("perfmon: [%d] has no PFM context\n", current->pid);
 		return;
 	}
 
-	DBprintk((" current=%d task=%d\n", current->pid, ctx->ctx_notify_task->pid));
-
-	/* should not happen */
-	if (CTX_OVFL_NOBLOCK(ctx)) {
-		printk("perfmon: process %d non-blocking ctx should not be here\n", current->pid);
-		return;
-	}
+	if (CTX_OVFL_NOBLOCK(ctx)) goto non_blocking;
 
-	DBprintk((" CPU%d %d before sleep\n", smp_processor_id(), current->pid));
+	DBprintk(("[%d] before sleeping\n", current->pid));
 
 	/*
 	 * may go through without blocking on SMP systems
@@ -1356,12 +2337,14 @@
 	 */
 	ret = down_interruptible(&ctx->ctx_restart_sem);
 
-	DBprintk((" CPU%d %d after sleep ret=%d\n", smp_processor_id(), current->pid, ret));
+	DBprintk(("[%d] after sleeping ret=%d\n", current->pid, ret));
 
 	/*
 	 * in case of interruption of down() we don't restart anything
 	 */
 	if (ret >= 0) {
+
+non_blocking:
 		/* we reactivate on context switch */
 		ctx->ctx_fl_frozen = 0;
 		/*
@@ -1369,19 +2352,19 @@
 		 * use the local reference
 		 */
 
-		pfm_reset_regs(ctx);
+		pfm_reset_regs(ctx, ctx->ctx_ovfl_regs, PFM_RELOAD_LONG_RESET);
+
+		ctx->ctx_ovfl_regs[0] = 0UL;
 
 		/*
 		 * Unlock sampling buffer and reset index atomically
 		 * XXX: not really needed when blocking
 		 */
 		if (CTX_HAS_SMPL(ctx)) {
-			ctx->ctx_smpl_buf->psb_hdr->hdr_count = 0;
-			ctx->ctx_smpl_buf->psb_index = 0;
+			ctx->ctx_psb->psb_hdr->hdr_count = 0;
+			ctx->ctx_psb->psb_index = 0;
 		}
 
-		DBprintk((" CPU%d %d unfreeze PMU\n", smp_processor_id(), current->pid));
-
 		ia64_set_pmc(0, 0);
 		ia64_srlz_d();
 
@@ -1390,23 +2373,111 @@
 }
 
 /*
+ * This function will record an entry in the sampling if it is not full already.
+ * Return:
+ * 	0 : buffer is not full (did not BECOME full: still space or was already full)
+ * 	1 : buffer is full (recorded the last entry)
+ */
+static int
+pfm_record_sample(struct task_struct *task, pfm_context_t *ctx, unsigned long ovfl_mask, struct pt_regs *regs)
+{
+	pfm_smpl_buffer_desc_t *psb = ctx->ctx_psb;
+	unsigned long *e, m, idx;
+	perfmon_smpl_entry_t *h;
+	int j;
+
+
+pfm_recorded_samples_count++;
+	idx = ia64_fetch_and_add(1, &psb->psb_index);
+	DBprintk(("recording index=%ld entries=%ld\n", idx-1, psb->psb_entries));
+
+	/*
+	* XXX: there is a small chance that we could run out on index before resetting
+	* but index is unsigned long, so it will take some time.....
+	* We use > instead of == because fetch_and_add() is off by one (see below)
+	*
+	* This case can happen in non-blocking mode or with multiple processes.
+	* For non-blocking, we need to reload and continue.
+	 */
+	if (idx > psb->psb_entries) return 0;
+
+	/* first entry is really entry 0, not 1 caused by fetch_and_add */
+	idx--;
+
+	h = (perfmon_smpl_entry_t *)(((char *)psb->psb_addr) + idx*(psb->psb_entry_size));
+
+	/*
+	 * initialize entry header
+	 */
+	h->pid  = task->pid;
+	h->cpu  = smp_processor_id();
+	h->rate = 0; /* XXX: add the sampling rate used here */
+	h->ip   = regs ? regs->cr_iip : 0x0;	/* where did the fault happened */
+	h->regs = ovfl_mask; 			/* which registers overflowed */
+
+	/* guaranteed to monotonically increase on each cpu */
+	h->stamp  = pfm_get_stamp();
+	h->period = 0UL; /* not yet used */
+
+	/* position for first pmd */
+	e = (unsigned long *)(h+1);
+
+	/*
+	 * selectively store PMDs in increasing index number
+	 */
+	m = ctx->ctx_smpl_regs[0];
+	for (j=0; m; m >>=1, j++) {
+
+		if ((m & 0x1) == 0) continue;
+
+		if (PMD_IS_COUNTING(j)) {
+			*e  =  pfm_read_soft_counter(ctx, j);
+			/* check if this pmd overflowed as well */
+			*e +=  ovfl_mask & (1UL<<j) ? 1 + pmu_conf.perf_ovfl_val : 0;
+		} else {
+			*e = ia64_get_pmd(j); /* slow */
+		}
+		DBprintk(("e=%p pmd%d =0x%lx\n", (void *)e, j, *e));
+		e++;
+	}
+	/*
+	 * make the new entry visible to user, needs to be atomic
+	 */
+	ia64_fetch_and_add(1, &psb->psb_hdr->hdr_count);
+
+	DBprintk(("index=%ld entries=%ld hdr_count=%ld\n", 
+				idx, psb->psb_entries, psb->psb_hdr->hdr_count));
+	/* 
+	 * sampling buffer full ? 
+	 */
+	if (idx == (psb->psb_entries-1)) {
+		DBprintk(("sampling buffer full\n"));
+		/*
+		 * XXX: must reset buffer in blocking mode and lost notified
+		 */
+		return 1;
+	}
+	return 0;
+}
+
+/*
  * main overflow processing routine.
  * it can be called from the interrupt path or explicitely during the context switch code
  * Return:
  *	new value of pmc[0]. if 0x0 then unfreeze, else keep frozen
  */
-unsigned long
-update_counters (struct task_struct *task, u64 pmc0, struct pt_regs *regs)
+static unsigned long
+pfm_overflow_handler(struct task_struct *task, u64 pmc0, struct pt_regs *regs)
 {
-	unsigned long mask, i, cnum;
-	struct thread_struct *th;
+	unsigned long mask;
+	struct thread_struct *t;
 	pfm_context_t *ctx;
-	unsigned long bv = 0;
+	unsigned long old_val;
+	unsigned long ovfl_notify = 0UL, ovfl_pmds = 0UL;
+	int i;
 	int my_cpu = smp_processor_id();
-	int ret = 1, buffer_is_full = 0;
-	int ovfl_has_long_recovery, can_notify, need_reset_pmd16=0;
+	int ret = 1;
 	struct siginfo si;
-
 	/*
 	 * It is never safe to access the task for which the overflow interrupt is destinated
 	 * using the current variable as the interrupt may occur in the middle of a context switch
@@ -1421,233 +2492,151 @@
 	 */
 
 	if (task == NULL) {
-		DBprintk((" owners[%d]=NULL\n", my_cpu));
+		DBprintk(("owners[%d]=NULL\n", my_cpu));
 		return 0x1;
 	}
-	th  = &task->thread;
-	ctx = th->pfm_context;
+	t   = &task->thread;
+	ctx = task->thread.pfm_context;
+
+	if (!ctx) {
+		printk("perfmon: Spurious overflow interrupt: process %d has no PFM context\n", 
+			task->pid);
+		return 0;
+	}
 
 	/*
 	 * XXX: debug test
 	 * Don't think this could happen given upfront tests
 	 */
-	if ((th->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system == 0) {
-		printk("perfmon: Spurious overflow interrupt: process %d not using perfmon\n", task->pid);
+	if ((t->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system == 0) {
+		printk("perfmon: Spurious overflow interrupt: process %d not using perfmon\n", 
+			task->pid);
 		return 0x1;
 	}
-	if (!ctx) {
-		printk("perfmon: Spurious overflow interrupt: process %d has no PFM context\n", task->pid);
-		return 0;
-	}
-
 	/*
 	 * sanity test. Should never happen
 	 */
-	if ((pmc0 & 0x1 )== 0) {
-		printk("perfmon: pid %d pmc0=0x%lx assumption error for freeze bit\n", task->pid, pmc0);
+	if ((pmc0 & 0x1) == 0) {
+		printk("perfmon: pid %d pmc0=0x%lx assumption error for freeze bit\n", 
+			task->pid, pmc0);
 		return 0x0;
 	}
 
 	mask = pmc0 >> PMU_FIRST_COUNTER;
 
-	DBprintk(("pmc0=0x%lx pid=%d owner=%d iip=0x%lx, ctx is in %s mode used_pmds=0x%lx used_pmcs=0x%lx\n", 
-				pmc0, task->pid, PMU_OWNER()->pid, regs->cr_iip, 
-				CTX_OVFL_NOBLOCK(ctx) ? "NO-BLOCK" : "BLOCK",
-				ctx->ctx_used_pmds[0],
-				ctx->ctx_used_pmcs[0]));
+	DBprintk(("pmc0=0x%lx pid=%d iip=0x%lx, %s"
+		  " mode used_pmds=0x%lx save_pmcs=0x%lx reload_pmcs=0x%lx\n", 
+			pmc0, task->pid, (regs ? regs->cr_iip : 0), 
+			CTX_OVFL_NOBLOCK(ctx) ? "nonblocking" : "blocking",
+			ctx->ctx_used_pmds[0],
+			ctx->ctx_saved_pmcs[0],
+			ctx->ctx_reload_pmcs[0]));
 
 	/*
-	 * XXX: need to record sample only when an EAR/BTB has overflowed
+	 * First we update the virtual counters
 	 */
-	if (CTX_HAS_SMPL(ctx)) {
-		pfm_smpl_buffer_desc_t *psb = ctx->ctx_smpl_buf;
-		unsigned long *e, m, idx=0;
-		perfmon_smpl_entry_t *h;
-		int j;
-
-		idx = ia64_fetch_and_add(1, &psb->psb_index);
-		DBprintk((" recording index=%ld entries=%ld\n", idx, psb->psb_entries));
+	for (i = PMU_FIRST_COUNTER; mask ; i++, mask >>= 1) {
+
+		/* skip pmd which did not overflow */
+		if ((mask & 0x1) == 0) continue;
+
+		DBprintk(("PMD[%d] overflowed hw_pmd=0x%lx soft_pmd=0x%lx\n", 
+			  i, ia64_get_pmd(i), ctx->ctx_soft_pmds[i].val));
 
 		/*
-		 * XXX: there is a small chance that we could run out on index before resetting
-		 * but index is unsigned long, so it will take some time.....
-		 * We use > instead of == because fetch_and_add() is off by one (see below)
-		 *
-		 * This case can happen in non-blocking mode or with multiple processes.
-		 * For non-blocking, we need to reload and continue.
+		 * Because we sometimes (EARS/BTB) reset to a specific value, we cannot simply use
+		 * val to count the number of times we overflowed. Otherwise we would loose the 
+		 * current value in the PMD (which can be >0). So to make sure we don't loose
+		 * the residual counts we set val to contain full 64bits value of the counter.
 		 */
-		if (idx > psb->psb_entries) {
-			buffer_is_full = 1;
-			goto reload_pmds;
-		}
-
-		/* first entry is really entry 0, not 1 caused by fetch_and_add */
-		idx--;
+		old_val = ctx->ctx_soft_pmds[i].val;
+		ctx->ctx_soft_pmds[i].val = 1 + pmu_conf.perf_ovfl_val + pfm_read_soft_counter(ctx, i);
 
-		h = (perfmon_smpl_entry_t *)(((char *)psb->psb_addr) + idx*(psb->psb_entry_size));
 
-		h->pid  = task->pid;
-		h->cpu  = my_cpu;
-		h->rate = 0;
-		h->ip   = regs ? regs->cr_iip : 0x0; /* where did the fault happened */
-		h->regs = mask; /* which registers overflowed */
+		DBprintk(("soft_pmd[%d].val=0x%lx old_val=0x%lx pmd=0x%lx\n", 
+			  i, ctx->ctx_soft_pmds[i].val, old_val, 
+			  ia64_get_pmd(i) & pmu_conf.perf_ovfl_val));
 
-		/* guaranteed to monotonically increase on each cpu */
-		h->stamp = perfmon_get_stamp();
-
-		e = (unsigned long *)(h+1);
-
-		/*
-		 * selectively store PMDs in increasing index number
-		 */
-		for (j=0, m = ctx->ctx_smpl_regs; m; m >>=1, j++) {
-			if (m & 0x1) {
-				if (PMD_IS_COUNTER(j))
-					*e =  ctx->ctx_pmds[j-PMU_FIRST_COUNTER].val
-					    + (ia64_get_pmd(j) & pmu_conf.perf_ovfl_val);
-				else {
-					*e = ia64_get_pmd(j); /* slow */
-				}
-				DBprintk((" e=%p pmd%d =0x%lx\n", (void *)e, j, *e));
-				e++;
-			}
-		}
 		/*
-		 * make the new entry visible to user, needs to be atomic
+		 * now that we have extracted the hardware counter, we can clear it to ensure
+		 * that a subsequent PFM_READ_PMDS will not include it again.
 		 */
-		ia64_fetch_and_add(1, &psb->psb_hdr->hdr_count);
+		ia64_set_pmd(i, 0UL);
 
-		DBprintk((" index=%ld entries=%ld hdr_count=%ld\n", idx, psb->psb_entries, psb->psb_hdr->hdr_count));
-		/* 
-		 * sampling buffer full ? 
+		/*
+		 * check for overflow condition
 		 */
-		if (idx == (psb->psb_entries-1)) {
-			/*
-			 * will cause notification, cannot be 0
-			 */
-			bv = mask << PMU_FIRST_COUNTER;
+		if (old_val > ctx->ctx_soft_pmds[i].val) {
 
-			buffer_is_full = 1;
+			ovfl_pmds |= 1UL << i;
 
-			DBprintk((" sampling buffer full must notify bv=0x%lx\n", bv));
+			DBprintk(("soft_pmd[%d] overflowed flags=0x%x, ovfl=0x%lx\n", i, ctx->ctx_soft_pmds[i].flags, ovfl_pmds));
 
-			/*
-			 * we do not reload here, when context is blocking
-			 */
-			if (!CTX_OVFL_NOBLOCK(ctx)) goto no_reload;
-
-			/*
-			 * here, we have a full buffer but we are in non-blocking mode
-			 * so we need to reload overflowed PMDs with sampling reset values
-			 * and restart right away.
-			 */
+			if (PMC_OVFL_NOTIFY(ctx, i)) {
+				ovfl_notify |= 1UL << i;
+			}
 		}
-		/* FALL THROUGH */
 	}
-reload_pmds:
-
-	/*
-	 * in the case of a non-blocking context, we reload
-	 * with the ovfl_rval when no user notification is taking place (short recovery)
-	 * otherwise when the buffer is full which requires user interaction) then we use
-	 * smpl_rval which is the long_recovery path (disturbance introduce by user execution).
-	 *
-	 * XXX: implies that when buffer is full then there is always notification.
-	 */
-	ovfl_has_long_recovery = CTX_OVFL_NOBLOCK(ctx) && buffer_is_full;
 
 	/*
-	 * XXX: CTX_HAS_SMPL() should really be something like CTX_HAS_SMPL() and is activated,i.e.,
-	 * one of the PMC is configured for EAR/BTB.
+	 * check for sampling buffer
 	 *
-	 * When sampling, we can only notify when the sampling buffer is full.
+	 * if present, record sample. We propagate notification ONLY when buffer
+	 * becomes full.
 	 */
-	can_notify   = CTX_HAS_SMPL(ctx) == 0 && ctx->ctx_notify_task;
-
-	DBprintk((" ovfl_has_long_recovery=%d can_notify=%d\n", ovfl_has_long_recovery, can_notify));
-
-	for (i = 0, cnum = PMU_FIRST_COUNTER; mask ; cnum++, i++, mask >>= 1) {
-
-		if ((mask & 0x1) == 0) continue;
-
-		DBprintk((" PMD[%ld] overflowed pmd=0x%lx pmod.val=0x%lx\n", cnum, ia64_get_pmd(cnum), ctx->ctx_pmds[i].val));
-
-		/*
-		 * Because we sometimes (EARS/BTB) reset to a specific value, we cannot simply use
-		 * val to count the number of times we overflowed. Otherwise we would loose the current value
-		 * in the PMD (which can be >0). So to make sure we don't loose
-		 * the residual counts we set val to contain full 64bits value of the counter.
-		 *
-		 * XXX: is this needed for EARS/BTB ?
-		 */
-		ctx->ctx_pmds[i].val += 1 + pmu_conf.perf_ovfl_val
-				      + (ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val); /* slow */
-
-		DBprintk((" pmod[%ld].val=0x%lx pmd=0x%lx\n", i, ctx->ctx_pmds[i].val, ia64_get_pmd(cnum)&pmu_conf.perf_ovfl_val));
-
-		if (can_notify && PMD_OVFL_NOTIFY(ctx, i)) {
-			DBprintk((" CPU%d should notify task %p with signal %d\n", my_cpu, ctx->ctx_notify_task, ctx->ctx_notify_sig));
-			bv |= 1 << i;
-		} else {
-			DBprintk((" CPU%d PMD[%ld] overflow, no notification\n", my_cpu, cnum));
+	if(CTX_HAS_SMPL(ctx)) {
+		ret = pfm_record_sample(task, ctx, ovfl_pmds, regs);
+		if (ret == 1) {
 			/*
-			 * In case no notification is requested, we reload the reset value right away
-			 * otherwise we wait until the notify_pid process has been called and has
-			 * has finished processing data. Check out pfm_overflow_notify()
+			 * Sampling buffer became full
+			 * If no notication was requested, then we reset buffer index
+			 * and reset registers (done below) and resume.
+			 * If notification requested, then defer reset until pfm_restart()
 			 */
-
-			/* writes to upper part are ignored, so this is safe */
-			if (ovfl_has_long_recovery) {
-				DBprintk((" CPU%d PMD[%ld] reload with smpl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval));
-				ia64_set_pmd(cnum, ctx->ctx_pmds[i].smpl_rval);
-			} else {
-				DBprintk((" CPU%d PMD[%ld] reload with ovfl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval));
-				ia64_set_pmd(cnum, ctx->ctx_pmds[i].ovfl_rval);
+			if (ovfl_notify == 0UL) {
+				ctx->ctx_psb->psb_hdr->hdr_count = 0UL;
+				ctx->ctx_psb->psb_index		 = 0UL;
 			}
+		} else {
+			/*
+			 * sample recorded in buffer, no need to notify user
+			 */
+			ovfl_notify = 0UL;
 		}
-		if (cnum == ctx->ctx_btb_counter) need_reset_pmd16=1;
 	}
-	/*
-	 * In case of BTB overflow we need to reset the BTB index.
-	 */
-	if (need_reset_pmd16) {
-		DBprintk(("reset PMD16\n"));
-		ia64_set_pmd(16, 0);
-	}
-
-no_reload:
 
 	/*
-	 * some counters overflowed, but they did not require
-	 * user notification, so after having reloaded them above
-	 * we simply restart
+	 * No overflow requiring a user level notification
 	 */
-	if (!bv) return 0x0;
+	if (ovfl_notify == 0UL) {
+		pfm_reset_regs(ctx, &ovfl_pmds, PFM_RELOAD_SHORT_RESET);
+		return 0x0;
+	}
 
-	ctx->ctx_ovfl_regs  = bv; /* keep track of what to reset when unblocking */
-	/*
-	 * Now we know that:
-	 * 	- we have some counters which overflowed (contains in bv)
-	 * 	- someone has asked to be notified on overflow. 
+	/* 
+	 * keep track of what to reset when unblocking 
 	 */
+	ctx->ctx_ovfl_regs[0]  = ovfl_pmds; 
 
-	
 	/*
-	 * If the notification task is still present, then notify_task is non
-	 * null. It is clean by that task if it ever exits before we do. 
+	 * we have come to this point because there was an overflow and that notification
+	 * was requested. The notify_task may have disappeared, in which case notify_task
+	 * is NULL.
 	 */
-
 	if (ctx->ctx_notify_task) {
 
 		si.si_errno    = 0;
 		si.si_addr     = NULL;
 		si.si_pid      = task->pid; /* who is sending */
 
-		si.si_signo    = ctx->ctx_notify_sig; /* is SIGPROF */
-		si.si_code     = PROF_OVFL; /* goes to user */
-		si.si_pfm_ovfl = bv;
-
-
+		si.si_signo    = SIGPROF;
+		si.si_code     = PROF_OVFL; /* indicates a perfmon SIGPROF signal */
+		/*
+		 * Shift the bitvector such that the user sees bit 4 for PMD4 and so on.
+		 * We only use smpl_ovfl[0] for now. It should be fine for quite a while
+		 * until we have more than 61 PMD available.
+		 */
+		si.si_pfm_ovfl[0] = ovfl_notify;
 	
 		/*
 		 * when the target of the signal is not ourself, we have to be more
@@ -1659,15 +2648,29 @@
 		if (ctx->ctx_notify_task != current) {
 			/*
 			 * grab the notification lock for this task
+			 * This guarantees that the sequence: test + send_signal
+			 * is atomic with regards to the ctx_notify_task field.
+			 *
+			 * We need a spinlock and not just an atomic variable for this.
+			 *
 			 */
-			spin_lock(&ctx->ctx_notify_lock);
+			spin_lock(&ctx->ctx_lock);
 
 			/*
 			 * now notify_task cannot be modified until we're done
 			 * if NULL, they it got modified while we were in the handler
 			 */
 			if (ctx->ctx_notify_task == NULL) {
-				spin_unlock(&ctx->ctx_notify_lock);
+
+				spin_unlock(&ctx->ctx_lock);
+
+				/*
+				 * If we've lost the notified task, then we will run
+				 * to completion wbut keep the PMU frozen. Results
+				 * will be incorrect anyway. We do not kill task
+				 * to leave it possible to attach perfmon context
+				 * to already running task.
+				 */
 				goto lost_notify;
 			}
 			/*
@@ -1681,20 +2684,23 @@
 	 	 * necessarily go to the signal handler (if any) when it goes back to
 	 	 * user mode.
 	 	 */
-		DBprintk((" %d sending %d notification to %d\n", task->pid, si.si_signo, ctx->ctx_notify_task->pid));
+		DBprintk(("[%d] sending notification to [%d]\n", 
+			  task->pid, ctx->ctx_notify_task->pid));
 
 
 		/* 
 		 * this call is safe in an interrupt handler, so does read_lock() on tasklist_lock
 		 */
-		ret = send_sig_info(ctx->ctx_notify_sig, &si, ctx->ctx_notify_task);
-		if (ret != 0) printk(" send_sig_info(process %d, SIGPROF)=%d\n",  ctx->ctx_notify_task->pid, ret);
+		ret = send_sig_info(SIGPROF, &si, ctx->ctx_notify_task);
+		if (ret != 0) 
+			printk("send_sig_info(process %d, SIGPROF)=%d\n",  
+			       ctx->ctx_notify_task->pid, ret);
 		/*
 		 * now undo the protections in order
 		 */
 		if (ctx->ctx_notify_task != current) {
 			read_unlock(&tasklist_lock);
-			spin_unlock(&ctx->ctx_notify_lock);
+			spin_unlock(&ctx->ctx_lock);
 		}
 
 		/*
@@ -1711,35 +2717,41 @@
 		 * before, changing it to NULL will still maintain this invariant.
 		 * Of course, when it is equal to current it cannot change at this point.
 		 */
-		if (!CTX_OVFL_NOBLOCK(ctx) && ctx->ctx_notify_task != current) {
-				th->pfm_must_block = 1; /* will cause blocking */
+		DBprintk(("block=%d notify [%d] current [%d]\n", 
+			ctx->ctx_fl_block,
+			ctx->ctx_notify_task ? ctx->ctx_notify_task->pid: -1, 
+			current->pid ));
+
+		if (!CTX_OVFL_NOBLOCK(ctx) && ctx->ctx_notify_task != task) {
+			t->pfm_ovfl_block_reset = 1; /* will cause blocking */
 		}
 	} else {
-lost_notify:
-		DBprintk((" notification task has disappeared !\n"));
+lost_notify: /* XXX: more to do here, to convert to non-blocking (reset values) */
+
+		DBprintk(("notification task has disappeared !\n"));
 		/*
-		 * for a non-blocking context, we make sure we do not fall into the pfm_overflow_notify()
-		 * trap. Also in the case of a blocking context with lost notify process, then we do not
-		 * want to block either (even though it is interruptible). In this case, the PMU will be kept
-		 * frozen and the process will run to completion without monitoring enabled.
+		 * for a non-blocking context, we make sure we do not fall into the 
+		 * pfm_overflow_notify() trap. Also in the case of a blocking context with lost 
+		 * notify process, then we do not want to block either (even though it is 
+		 * interruptible). In this case, the PMU will be kept frozen and the process will 
+		 * run to completion without monitoring enabled.
 		 *
 		 * Of course, we cannot loose notify process when self-monitoring.
 		 */
-		th->pfm_must_block = 0; 
+		t->pfm_ovfl_block_reset = 0; 
 
 	}
 	/*
-	 * if we block, we keep the PMU frozen. If non-blocking we restart.
-	 * in the case of non-blocking were the notify process is lost, we also 
-	 * restart. 
+	 * If notification was successful, then we rely on the pfm_restart()
+	 * call to unfreeze and reset (in both blocking or non-blocking mode).
+	 *
+	 * If notification failed, then we will keep the PMU frozen and run
+	 * the task to completion
 	 */
-	if (!CTX_OVFL_NOBLOCK(ctx)) 
-		ctx->ctx_fl_frozen  = 1;
-	else
-		ctx->ctx_fl_frozen = 0;
+	ctx->ctx_fl_frozen = 1;
 
-	DBprintk((" reload pmc0=0x%x must_block=%ld\n",
-				ctx->ctx_fl_frozen ? 0x1 : 0x0, th->pfm_must_block));
+	DBprintk(("reload pmc0=0x%x must_block=%ld\n",
+				ctx->ctx_fl_frozen ? 0x1 : 0x0, t->pfm_ovfl_block_reset));
 
 	return ctx->ctx_fl_frozen ? 0x1 : 0x0;
 }
@@ -1748,29 +2760,40 @@
 perfmon_interrupt (int irq, void *arg, struct pt_regs *regs)
 {
 	u64 pmc0;
-	struct task_struct *ta;
+	struct task_struct *task;
 
-	pmc0 = ia64_get_pmc(0); /* slow */
+	pfm_ovfl_intr_count++;
+
+	/* 
+	 * srlz.d done before arriving here
+	 *
+	 * This is slow
+	 */
+	pmc0 = ia64_get_pmc(0); 
 
 	/*
 	 * if we have some pending bits set
 	 * assumes : if any PM[0].bit[63-1] is set, then PMC[0].fr = 1
 	 */
-	if ((pmc0 & ~0x1) && (ta=PMU_OWNER())) {
+	if ((pmc0 & ~0x1UL)!=0UL && (task=PMU_OWNER())!= NULL) {
 
-		/* assumes, PMC[0].fr = 1 at this point */
-		pmc0 = update_counters(ta, pmc0, regs);
-
-		/*
-		 * if pmu_frozen = 0
-		 *	pmc0 = 0 and we resume monitoring right away
-		 * else
-		 *	pmc0 = 0x1 frozen but all pending bits are cleared
+		/* 
+		 * assumes, PMC[0].fr = 1 at this point 
+		 *
+		 * XXX: change protype to pass &pmc0
 		 */
-		ia64_set_pmc(0, pmc0);
-		ia64_srlz_d();
+		pmc0 = pfm_overflow_handler(task, pmc0, regs);
+
+		/* we never explicitely freeze PMU here */
+		if (pmc0 == 0) {
+			ia64_set_pmc(0, 0);
+			ia64_srlz_d();
+		}
 	} else {
-		printk("perfmon: Spurious PMU overflow interrupt: pmc0=0x%lx owner=%p\n", pmc0, (void *)PMU_OWNER());
+		pfm_spurious_ovfl_intr_count++;
+
+		DBprintk(("perfmon: Spurious PMU overflow interrupt on CPU%d: pmc0=0x%lx owner=%p\n", 
+			smp_processor_id(), pmc0, (void *)PMU_OWNER()));
 	}
 }
 
@@ -1778,14 +2801,39 @@
 static int
 perfmon_proc_info(char *page)
 {
+#ifdef CONFIG_SMP
+#define cpu_is_online(i) (cpu_online_map & (1UL << i))
+#else
+#define cpu_is_online(i)        1
+#endif
 	char *p = page;
 	u64 pmc0 = ia64_get_pmc(0);
 	int i;
 
-	p += sprintf(p, "CPU%d.pmc[0]=%lx\nPerfmon debug: %s\n", smp_processor_id(), pmc0, pfm_debug ? "On" : "Off");
-	p += sprintf(p, "proc_sessions=%lu sys_sessions=%lu\n", 
-			pfs_info.pfs_proc_sessions, 
-			pfs_info.pfs_sys_session);
+	p += sprintf(p, "perfmon enabled: %s\n", pmu_conf.pfm_is_disabled ? "No": "Yes");
+
+	p += sprintf(p, "monitors_pmcs0]=0x%lx\n", pmu_conf.monitor_pmcs[0]);
+	p += sprintf(p, "counter_pmcds[0]=0x%lx\n", pmu_conf.counter_pmds[0]);
+	p += sprintf(p, "overflow interrupts=%lu\n", pfm_ovfl_intr_count);
+	p += sprintf(p, "spurious overflow interrupts=%lu\n", pfm_spurious_ovfl_intr_count);
+	p += sprintf(p, "recorded samples=%lu\n", pfm_recorded_samples_count);
+
+	p += sprintf(p, "CPU%d.pmc[0]=%lx\nPerfmon debug: %s\n", 
+			smp_processor_id(), pmc0, pfm_debug_mode ? "On" : "Off");
+
+#ifdef CONFIG_SMP
+	p += sprintf(p, "CPU%d cpu_data.pfm_syst_wide=%d cpu_data.dcr_pp=%d\n", 
+			smp_processor_id(), local_cpu_data->pfm_syst_wide, local_cpu_data->pfm_dcr_pp);
+#endif
+
+	LOCK_PFS();
+	p += sprintf(p, "proc_sessions=%lu\nsys_sessions=%lu\nsys_use_dbregs=%lu\nptrace_use_dbregs=%lu\n", 
+			pfm_sessions.pfs_task_sessions, 
+			pfm_sessions.pfs_sys_sessions,
+			pfm_sessions.pfs_sys_use_dbregs,
+			pfm_sessions.pfs_ptrace_use_dbregs);
+
+	UNLOCK_PFS();
 
 	for(i=0; i < NR_CPUS; i++) {
 		if (cpu_is_online(i)) {
@@ -1794,10 +2842,11 @@
 					pmu_owners[i].owner ? pmu_owners[i].owner->pid: -1);
 		}
 	}
+
 	return p - page;
 }
 
-/* for debug only */
+/* /proc interface, for debug only */
 static int
 perfmon_read_entry(char *page, char **start, off_t off, int count, int *eof, void *data)
 {
@@ -1814,153 +2863,90 @@
 	return len;
 }
 
-static struct irqaction perfmon_irqaction = {
-	handler:	perfmon_interrupt,
-	flags:		SA_INTERRUPT,
-	name:		"perfmon"
-};
-
-void __init
-perfmon_init (void)
+#ifdef CONFIG_SMP
+void
+pfm_syst_wide_update_task(struct task_struct *task, int mode)
 {
-	pal_perf_mon_info_u_t pm_info;
-	s64 status;
+	struct pt_regs *regs = (struct pt_regs *)((unsigned long) task + IA64_STK_OFFSET);
 
-	register_percpu_irq(IA64_PERFMON_VECTOR, &perfmon_irqaction);
+	regs--;
 
-	ia64_set_pmv(IA64_PERFMON_VECTOR);
-	ia64_srlz_d();
-
-	pmu_conf.pfm_is_disabled = 1;
+	/*
+	 * propagate the value of the dcr_pp bit to the psr
+	 */
+	ia64_psr(regs)->pp = mode ? local_cpu_data->pfm_dcr_pp : 0;
+}
+#endif
 
-	printk("perfmon: version %s (sampling format v%d)\n", PFM_VERSION, PFM_SMPL_HDR_VERSION);
-	printk("perfmon: Interrupt vectored to %u\n", IA64_PERFMON_VECTOR);
 
-	if ((status=ia64_pal_perf_mon_info(pmu_conf.impl_regs, &pm_info)) != 0) {
-		printk("perfmon: PAL call failed (%ld)\n", status);
-		return;
-	}
-	pmu_conf.perf_ovfl_val = (1L << pm_info.pal_perf_mon_info_s.width) - 1;
-	pmu_conf.max_counters  = pm_info.pal_perf_mon_info_s.generic;
-	pmu_conf.num_pmcs      = find_num_pm_regs(pmu_conf.impl_regs);
-	pmu_conf.num_pmds      = find_num_pm_regs(&pmu_conf.impl_regs[4]);
+void
+pfm_save_regs (struct task_struct *task)
+{
+	pfm_context_t *ctx;
+	u64 psr;
 
-	printk("perfmon: %d bits counters (max value 0x%lx)\n", pm_info.pal_perf_mon_info_s.width, pmu_conf.perf_ovfl_val);
-	printk("perfmon: %ld PMC/PMD pairs, %ld PMCs, %ld PMDs\n", pmu_conf.max_counters, pmu_conf.num_pmcs, pmu_conf.num_pmds);
+	ctx = task->thread.pfm_context;
 
-	/* sanity check */
-	if (pmu_conf.num_pmds >= IA64_NUM_PMD_REGS || pmu_conf.num_pmcs >= IA64_NUM_PMC_REGS) {
-		printk(KERN_ERR "perfmon: ERROR not enough PMC/PMD storage in kernel, perfmon is DISABLED\n");
-		return; /* no need to continue anyway */
-	}
-	/* we are all set */
-	pmu_conf.pfm_is_disabled = 0;
 
 	/*
-	 * Insert the tasklet in the list.
-	 * It is still disabled at this point, so it won't run
-	printk(__FUNCTION__" tasklet is %p state=%d, count=%d\n", &perfmon_tasklet, perfmon_tasklet.state, perfmon_tasklet.count);
+	 * save current PSR: needed because we modify it
 	 */
+	__asm__ __volatile__ ("mov %0=psr;;": "=r"(psr) :: "memory");
 
 	/*
-	 * for now here for debug purposes
+	 * stop monitoring:
+	 * This is the last instruction which can generate an overflow
+	 *
+	 * We do not need to set psr.sp because, it is irrelevant in kernel.
+	 * It will be restored from ipsr when going back to user level
 	 */
-	perfmon_dir = create_proc_read_entry ("perfmon", 0, 0, perfmon_read_entry, NULL);
-}
+	__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+
+	ctx->ctx_saved_psr = psr;
+
+	//ctx->ctx_last_cpu  = smp_processor_id();
 
-void
-perfmon_init_percpu (void)
-{
-	ia64_set_pmv(IA64_PERFMON_VECTOR);
-	ia64_srlz_d();
 }
 
-void
-pfm_save_regs (struct task_struct *ta)
+static void
+pfm_lazy_save_regs (struct task_struct *task)
 {
-	struct task_struct *owner;
 	pfm_context_t *ctx;
 	struct thread_struct *t;
-	u64 pmc0, psr;
 	unsigned long mask;
 	int i;
 
-	t   = &ta->thread;
-	ctx = ta->thread.pfm_context;
+	DBprintk(("on [%d] by [%d]\n", task->pid, current->pid));
 
-	/*
-	 * We must make sure that we don't loose any potential overflow
-	 * interrupt while saving PMU context. In this code, external
-	 * interrupts are always enabled.
-	 */
+	t   = &task->thread;
+	ctx = task->thread.pfm_context;
 
-	/*
-	 * save current PSR: needed because we modify it
+#ifdef CONFIG_SMP
+	/* 
+	 * announce we are saving this PMU state
+	 * This will cause other CPU, to wait until we're done
+	 * before using the context.h
+	 *
+	 * must be an atomic operation
 	 */
-	__asm__ __volatile__ ("mov %0=psr;;": "=r"(psr) :: "memory");
+	atomic_set(&ctx->ctx_saving_in_progress, 1);
 
-	/*
-	 * stop monitoring:
-	 * This is the only way to stop monitoring without destroying overflow
-	 * information in PMC[0].
-	 * This is the last instruction which can cause overflow when monitoring
-	 * in kernel.
-	 * By now, we could still have an overflow interrupt in-flight.
-	 */
-	__asm__ __volatile__ ("rsm psr.up|psr.pp;;"::: "memory");
+	 /*
+	  * if owner is NULL, it means that the other CPU won the race
+	  * and the IPI has caused the context to be saved in pfm_handle_fectch_regs()
+	  * instead of here. We have nothing to do
+	  *
+	  * note that this is safe, because the other CPU NEVER modifies saving_in_progress.
+	  */
+	if (PMU_OWNER() == NULL) goto do_nothing;
+#endif
 
 	/*
-	 * Mark the PMU as not owned
-	 * This will cause the interrupt handler to do nothing in case an overflow
-	 * interrupt was in-flight
-	 * This also guarantees that pmc0 will contain the final state
-	 * It virtually gives us full control over overflow processing from that point
-	 * on.
-	 * It must be an atomic operation.
+	 * do not own the PMU
 	 */
-	owner = PMU_OWNER();
 	SET_PMU_OWNER(NULL);
 
-	/*
-	 * read current overflow status:
-	 *
-	 * we are guaranteed to read the final stable state
-	 */
 	ia64_srlz_d();
-	pmc0 = ia64_get_pmc(0); /* slow */
-
-	/*
-	 * freeze PMU:
-	 *
-	 * This destroys the overflow information. This is required to make sure
-	 * next process does not start with monitoring on if not requested
-	 */
-	ia64_set_pmc(0, 1);
-
-	/*
-	 * Check for overflow bits and proceed manually if needed
-	 *
-	 * It is safe to call the interrupt handler now because it does
-	 * not try to block the task right away. Instead it will set a
-	 * flag and let the task proceed. The blocking will only occur
-	 * next time the task exits from the kernel.
-	 */
-	if (pmc0 & ~0x1) {
-		update_counters(owner, pmc0, NULL);
-		/* we will save the updated version of pmc0 */
-	}
-	/*
-	 * restore PSR for context switch to save
-	 */
-	__asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory");
-
-	/*
-	 * we do not save registers if we can do lazy
-	 */
-	if (PFM_CAN_DO_LAZY()) {
-		SET_PMU_OWNER(owner);
-		return;
-	}
 
 	/*
 	 * XXX needs further optimization.
@@ -1970,30 +2956,75 @@
 	for (i=0; mask; i++, mask>>=1) {
 		if (mask & 0x1) t->pmd[i] =ia64_get_pmd(i);
 	}
-
-	/* skip PMC[0], we handle it separately */
-	mask = ctx->ctx_used_pmcs[0]>>1;
-	for (i=1; mask; i++, mask>>=1) {
+	/*
+	 * XXX: simplify to pmc0 only
+	 */
+	mask = ctx->ctx_saved_pmcs[0];
+	for (i=0; mask; i++, mask>>=1) {
 		if (mask & 0x1) t->pmc[i] = ia64_get_pmc(i);
 	}
+
+	/* not owned by this CPU */
+	atomic_set(&ctx->ctx_last_cpu, -1);
+
+#ifdef CONFIG_SMP
+do_nothing:
+#endif
 	/*
-	 * Throughout this code we could have gotten an overflow interrupt. It is transformed
-	 * into a spurious interrupt as soon as we give up pmu ownership.
+	 * declare we are done saving this context
+	 *
+	 * must be an atomic operation
 	 */
+	atomic_set(&ctx->ctx_saving_in_progress,0);
+
 }
 
-static void
-pfm_lazy_save_regs (struct task_struct *ta)
+#ifdef CONFIG_SMP
+/*
+ * Handles request coming from other CPUs
+ */
+static void 
+pfm_handle_fetch_regs(void *info)
 {
-	pfm_context_t *ctx;
+	pfm_smp_ipi_arg_t *arg = info;
 	struct thread_struct *t;
+	pfm_context_t *ctx;
 	unsigned long mask;
 	int i;
 
-	DBprintk(("  on [%d] by [%d]\n", ta->pid, current->pid));
+	ctx = arg->task->thread.pfm_context;
+	t   = &arg->task->thread;
+
+	DBprintk(("task=%d owner=%d saving=%d\n", 
+		  arg->task->pid,
+		  PMU_OWNER() ? PMU_OWNER()->pid: -1,
+		  atomic_read(&ctx->ctx_saving_in_progress)));
+
+	/* must wait if saving was interrupted */
+	if (atomic_read(&ctx->ctx_saving_in_progress)) {
+		arg->retval = 1;
+		return;
+	}
+
+	/* can proceed, done with context */
+	if (PMU_OWNER() != arg->task) {
+		arg->retval = 0;
+		return;
+	}
+
+	DBprintk(("saving state for [%d] save_pmcs=0x%lx all_pmcs=0x%lx used_pmds=0x%lx\n", 
+		arg->task->pid,
+		ctx->ctx_saved_pmcs[0],
+		ctx->ctx_reload_pmcs[0],
+		ctx->ctx_used_pmds[0]));
+
+	/*
+	 * XXX: will be replaced with pure assembly call
+	 */
+	SET_PMU_OWNER(NULL);
+
+	ia64_srlz_d();
 
-	t   = &ta->thread;
-	ctx = ta->thread.pfm_context;
 	/*
 	 * XXX needs further optimization.
 	 * Also must take holes into account
@@ -2003,84 +3034,295 @@
 		if (mask & 0x1) t->pmd[i] =ia64_get_pmd(i);
 	}
 	
-	/* skip PMC[0], we handle it separately */
-	mask = ctx->ctx_used_pmcs[0]>>1;
-	for (i=1; mask; i++, mask>>=1) {
+	mask = ctx->ctx_saved_pmcs[0];
+	for (i=0; mask; i++, mask>>=1) {
 		if (mask & 0x1) t->pmc[i] = ia64_get_pmc(i);
 	}
-	SET_PMU_OWNER(NULL);
+	/* not owned by this CPU */
+	atomic_set(&ctx->ctx_last_cpu, -1);
+
+	/* can proceed */
+	arg->retval = 0;
+}
+
+/*
+ * Function call to fetch PMU state from another CPU identified by 'cpu'.
+ * If the context is being saved on the remote CPU, then we busy wait until
+ * the saving is done and then we return. In this case, non IPI is sent.
+ * Otherwise, we send an IPI to the remote CPU, potentially interrupting 
+ * pfm_lazy_save_regs() over there.
+ *
+ * If the retval==1, then it means that we interrupted remote save and that we must
+ * wait until the saving is over before proceeding.
+ * Otherwise, we did the saving on the remote CPU, and it was done by the time we got there.
+ * in either case, we can proceed.
+ */
+static void
+pfm_fetch_regs(int cpu, struct task_struct *task, pfm_context_t *ctx)
+{
+	pfm_smp_ipi_arg_t  arg;
+	int ret;
+
+	arg.task   = task;
+	arg.retval = -1;
+
+	if (atomic_read(&ctx->ctx_saving_in_progress)) {
+		DBprintk(("no IPI, must wait for [%d] to be saved on [%d]\n", task->pid, cpu));
+
+		/* busy wait */
+		while (atomic_read(&ctx->ctx_saving_in_progress));
+		return;
+	}
+	DBprintk(("calling CPU %d from CPU %d\n", cpu, smp_processor_id()));
+
+	if (cpu == -1) {
+		printk("refusing to use -1 for [%d]\n", task->pid);
+		return;
+	}
+
+	/* will send IPI to other CPU and wait for completion of remote call */
+	if ((ret=smp_call_function_single(cpu, pfm_handle_fetch_regs, &arg, 0, 1))) {
+		printk("perfmon: remote CPU call from %d to %d error %d\n", smp_processor_id(), cpu, ret);
+		return;
+	}
+	/*
+	 * we must wait until saving is over on the other CPU
+	 * This is the case, where we interrupted the saving which started just at the time we sent the
+	 * IPI.
+	 */
+	if (arg.retval == 1) {
+		DBprintk(("must wait for [%d] to be saved on [%d]\n", task->pid, cpu));
+		while (atomic_read(&ctx->ctx_saving_in_progress));
+		DBprintk(("done saving for [%d] on [%d]\n", task->pid, cpu));
+	}
 }
+#endif /* CONFIG_SMP */
 
 void
-pfm_load_regs (struct task_struct *ta)
+pfm_load_regs (struct task_struct *task)
 {
-	struct thread_struct *t = &ta->thread;
-	pfm_context_t *ctx = ta->thread.pfm_context;
+	struct thread_struct *t;
+	pfm_context_t *ctx;
 	struct task_struct *owner;
 	unsigned long mask;
+	u64 psr;
 	int i;
+#ifdef CONFIG_SMP
+	int cpu;
+#endif
 
 	owner = PMU_OWNER();
-	if (owner == ta) goto skip_restore;
+	ctx   = task->thread.pfm_context;
+
+	/*
+	 * if we were the last user, then nothing to do except restore psr
+	 */
+	if (owner == task) {
+		if (atomic_read(&ctx->ctx_last_cpu) != smp_processor_id())
+			DBprintk(("invalid last_cpu=%d for [%d]\n", 
+				atomic_read(&ctx->ctx_last_cpu), task->pid));
+
+		psr = ctx->ctx_saved_psr;
+		__asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory");
+
+		return;
+	}
+	DBprintk(("load_regs: must reload for [%d] owner=%d\n", 
+		task->pid, owner ? owner->pid : -1 ));
+	/*
+	 * someone else is still using the PMU, first push it out and
+	 * then we'll be able to install our stuff !
+	 */
 	if (owner) pfm_lazy_save_regs(owner);
 
-	SET_PMU_OWNER(ta);
+#ifdef CONFIG_SMP
+	/* 
+	 * check if context on another CPU (-1 means saved)
+	 * We MUST use the variable, as last_cpu may change behind our 
+	 * back. If it changes to -1 (not on a CPU anymore), then in cpu
+	 * we have the last CPU the context was on. We may be sending the 
+	 * IPI for nothing, but we have no way of verifying this. 
+	 */
+	cpu = atomic_read(&ctx->ctx_last_cpu);
+	if (cpu != -1) {
+		pfm_fetch_regs(cpu, task, ctx);
+	}
+#endif
+	t   = &task->thread;
 
+	/*
+	 * XXX: will be replaced by assembly routine
+	 * We clear all unused PMDs to avoid leaking information
+	 */
 	mask = ctx->ctx_used_pmds[0];
 	for (i=0; mask; i++, mask>>=1) {
-		if (mask & 0x1) ia64_set_pmd(i, t->pmd[i]);
+		if (mask & 0x1) 
+			ia64_set_pmd(i, t->pmd[i]);
+		else
+			ia64_set_pmd(i, 0UL);
 	}
+	/* XXX: will need to clear all unused pmd, for security */
 
-	/* skip PMC[0] to avoid side effects */
-	mask = ctx->ctx_used_pmcs[0]>>1;
+	/* 
+	 * skip pmc[0] to avoid side-effects, 
+	 * all PMCs are systematically reloaded, unsued get default value
+	 * to avoid picking up stale configuration
+	 */	
+	mask = ctx->ctx_reload_pmcs[0]>>1;
 	for (i=1; mask; i++, mask>>=1) {
 		if (mask & 0x1) ia64_set_pmc(i, t->pmc[i]);
 	}
-skip_restore:
+
+	/*
+	 * restore debug registers when used for range restrictions.
+	 * We must restore the unused registers to avoid picking up
+	 * stale information.
+	 */
+	mask = ctx->ctx_used_ibrs[0];
+	for (i=0; mask; i++, mask>>=1) {
+		if (mask & 0x1) 
+			ia64_set_ibr(i, t->ibr[i]);
+		else
+			ia64_set_ibr(i, 0UL);
+	}
+
+	mask = ctx->ctx_used_dbrs[0];
+	for (i=0; mask; i++, mask>>=1) {
+		if (mask & 0x1) 
+			ia64_set_dbr(i, t->dbr[i]);
+		else
+			ia64_set_dbr(i, 0UL);
+	}
+
+	if (t->pmc[0] & ~0x1) {
+		ia64_srlz_d();
+		pfm_overflow_handler(task, t->pmc[0], NULL);
+	}
+
+	/*
+	 * fl_frozen==1 when we are in blocking mode waiting for restart
+	 */
+	if (ctx->ctx_fl_frozen == 0) {
+		ia64_set_pmc(0, 0);
+		ia64_srlz_d();
+	}
+	atomic_set(&ctx->ctx_last_cpu, smp_processor_id());
+
+	SET_PMU_OWNER(task);
+
+	/*
+	 * restore the psr we changed in pfm_save_regs()
+	 */
+	psr = ctx->ctx_saved_psr;
+	__asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory");
+
+}
+
+/*
+ * XXX: make this routine able to work with non current context
+ */
+static void
+ia64_reset_pmu(struct task_struct *task)
+{
+	struct thread_struct *t = &task->thread;
+	pfm_context_t *ctx = t->pfm_context;
+	unsigned long mask;
+	int i;
+
+	if (task != current) {
+		printk("perfmon: invalid task in ia64_reset_pmu()\n");
+		return;
+	}
+
+	/* Let's make sure the PMU is frozen */
+	ia64_set_pmc(0,1);
+
+	/*
+	 * install reset values for PMC. We skip PMC0 (done above)
+	 * XX: good up to 64 PMCS
+	 */
+	mask = pmu_conf.impl_regs[0] >> 1;
+	for(i=1; mask; mask>>=1, i++) {
+		if (mask & 0x1) {
+			ia64_set_pmc(i, reset_pmcs[i]);
+			/*
+			 * When restoring context, we must restore ALL pmcs, even the ones 
+			 * that the task does not use to avoid leaks and possibly corruption
+			 * of the sesion because of configuration conflicts. So here, we 
+			 * initializaed the table used in the context switch restore routine.
+	 		 */
+			t->pmc[i] = reset_pmcs[i];
+			DBprintk((" pmc[%d]=0x%lx\n", i, reset_pmcs[i]));
+						 
+		}
+	}
+	/*
+	 * clear reset values for PMD. 
+	 * XX: good up to 64 PMDS. Suppose that zero is a valid value.
+	 */
+	mask = pmu_conf.impl_regs[4];
+	for(i=0; mask; mask>>=1, i++) {
+		if (mask & 0x1) ia64_set_pmd(i, 0UL);
+	}
+
 	/*
-	 * unfreeze only when possible
+	 * On context switched restore, we must restore ALL pmc even
+	 * when they are not actively used by the task. In UP, the incoming process 
+	 * may otherwise pick up left over PMC state from the previous process.
+	 * As opposed to PMD, stale PMC can cause harm to the incoming
+	 * process because they may change what is being measured. 
+	 * Therefore, we must systematically reinstall the entire
+	 * PMC state. In SMP, the same thing is possible on the 
+	 * same CPU but also on between 2 CPUs.
+	 *
+	 * There is unfortunately no easy way to avoid this problem
+	 * on either UP or SMP. This definitively slows down the 
+	 * pfm_load_regs(). 
 	 */
-	if (ctx->ctx_fl_frozen == 0) {
-		ia64_set_pmc(0, 0);
-		ia64_srlz_d();
-		/* place where we potentially (kernel level) start monitoring again */
-	}
-}
+	
+	 /*
+	  * We must include all the PMC in this mask to make sure we don't
+	  * see any side effect of the stale state, such as opcode matching
+	  * or range restrictions, for instance.
+	  */
+	ctx->ctx_reload_pmcs[0] = pmu_conf.impl_regs[0];
 
+	/*
+	 * useful in case of re-enable after disable
+	 */
+	ctx->ctx_used_pmds[0] = 0UL;
+	ctx->ctx_used_ibrs[0] = 0UL;
+	ctx->ctx_used_dbrs[0] = 0UL;
+
+	ia64_srlz_d();
+}
 
 /*
  * This function is called when a thread exits (from exit_thread()).
  * This is a simplified pfm_save_regs() that simply flushes the current
  * register state into the save area taking into account any pending
- * overflow. This time no notification is sent because the taks is dying
+ * overflow. This time no notification is sent because the task is dying
  * anyway. The inline processing of overflows avoids loosing some counts.
  * The PMU is frozen on exit from this call and is to never be reenabled
  * again for this task.
+ *
  */
 void
-pfm_flush_regs (struct task_struct *ta)
+pfm_flush_regs (struct task_struct *task)
 {
 	pfm_context_t *ctx;
-	u64 pmc0, psr, mask;
-	int i,j;
+	u64 pmc0;
+	unsigned long mask, mask2, val;
+	int i;
 
-	if (ta == NULL) {
-		panic(__FUNCTION__" task is NULL\n");
-	}
-	ctx = ta->thread.pfm_context;
-	if (ctx == NULL) {
-		panic(__FUNCTION__" no PFM ctx is NULL\n");
-	}
-	/*
-	 * We must make sure that we don't loose any potential overflow
-	 * interrupt while saving PMU context. In this code, external
-	 * interrupts are always enabled.
-	 */
+	ctx = task->thread.pfm_context;
 
-	/*
-	 * save current PSR: needed because we modify it
+	if (ctx == NULL) return;
+
+	/* 
+	 * that's it if context already disabled
 	 */
-	__asm__ __volatile__ ("mov %0=psr;;": "=r"(psr) :: "memory");
+	if (ctx->ctx_flags.state == PFM_CTX_DISABLED) return;
 
 	/*
 	 * stop monitoring:
@@ -2090,7 +3332,27 @@
 	 * in kernel.
 	 * By now, we could still have an overflow interrupt in-flight.
 	 */
-	__asm__ __volatile__ ("rsm psr.up;;"::: "memory");
+	if (ctx->ctx_fl_system) {
+
+		__asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
+
+		/* disable dcr pp */
+		ia64_set_dcr(ia64_get_dcr() & ~IA64_DCR_PP);
+
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_syst_wide = 0;
+		local_cpu_data->pfm_dcr_pp    = 0;
+#else
+		pfm_tasklist_toggle_pp(0);
+#endif
+
+	} else  {
+
+		__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+
+		/* no more save/restore on ctxsw */
+		current->thread.flags &= ~IA64_THREAD_PM_VALID;
+	}
 
 	/*
 	 * Mark the PMU as not owned
@@ -2121,85 +3383,68 @@
 	ia64_srlz_d();
 
 	/*
-	 * restore PSR for context switch to save
+	 * We don't need to restore psr, because we are on our way out anyway
 	 */
-	__asm__ __volatile__ ("mov psr.l=%0;;srlz.i;"::"r"(psr): "memory");
 
 	/*
 	 * This loop flushes the PMD into the PFM context.
-	 * IT also processes overflow inline.
+	 * It also processes overflow inline.
 	 *
 	 * IMPORTANT: No notification is sent at this point as the process is dying.
 	 * The implicit notification will come from a SIGCHILD or a return from a
 	 * waitpid().
 	 *
-	 * XXX: must take holes into account
 	 */
-	mask = pmc0 >> PMU_FIRST_COUNTER;
-	for (i=0,j=PMU_FIRST_COUNTER; i< pmu_conf.max_counters; i++,j++) {
-
-		/* collect latest results */
-		ctx->ctx_pmds[i].val += ia64_get_pmd(j) & pmu_conf.perf_ovfl_val;
-
-		/*
-		 * now everything is in ctx_pmds[] and we need
-		 * to clear the saved context from save_regs() such that
-		 * pfm_read_pmds() gets the correct value
-		 */
-		ta->thread.pmd[j] = 0;
 
-		/* take care of overflow inline */
-		if (mask & 0x1) {
-			ctx->ctx_pmds[i].val += 1 + pmu_conf.perf_ovfl_val;
-			DBprintk((" PMD[%d] overflowed pmd=0x%lx pmds.val=0x%lx\n",
-			j, ia64_get_pmd(j), ctx->ctx_pmds[i].val));
-		}
-		mask >>=1;
-	}
-}
+	if (atomic_read(&ctx->ctx_last_cpu) != smp_processor_id()) 
+		printk("perfmon: [%d] last_cpu=%d\n", task->pid, atomic_read(&ctx->ctx_last_cpu));
 
-/*
- * XXX: this routine is not very portable for PMCs
- * XXX: make this routine able to work with non current context
- */
-static void
-ia64_reset_pmu(void)
-{
-	int i;
+	mask  = pmc0 >> PMU_FIRST_COUNTER;
+	mask2 = ctx->ctx_used_pmds[0] >> PMU_FIRST_COUNTER;
 
-	/* PMU is frozen, no pending overflow bits */
-	ia64_set_pmc(0,1);
+	for (i = PMU_FIRST_COUNTER; mask2; i++, mask>>=1, mask2>>=1) {
 
-	/* extra overflow bits + counter configs cleared */
-	for(i=1; i< PMU_FIRST_COUNTER + pmu_conf.max_counters ; i++) {
-		ia64_set_pmc(i,0);
-	}
+		/* skip non used pmds */
+		if ((mask2 & 0x1) == 0) continue;
 
-	/* opcode matcher set to all 1s */
-	ia64_set_pmc(8,~0);
-	ia64_set_pmc(9,~0);
+		val = ia64_get_pmd(i);
 
-	/* I-EAR config cleared, plm=0 */
-	ia64_set_pmc(10,0);
+		if (PMD_IS_COUNTING(i)) {
 
-	/* D-EAR config cleared, PMC[11].pt must be 1 */
-	ia64_set_pmc(11,1 << 28);
+			DBprintk(("[%d] pmd[%d] soft_pmd=0x%lx hw_pmd=0x%lx\n", task->pid, i, ctx->ctx_soft_pmds[i].val, val & pmu_conf.perf_ovfl_val));
 
-	/* BTB config. plm=0 */
-	ia64_set_pmc(12,0);
+			/* collect latest results */
+			ctx->ctx_soft_pmds[i].val += val & pmu_conf.perf_ovfl_val;
 
-	/* Instruction address range, PMC[13].ta must be 1 */
-	ia64_set_pmc(13,1);
+			/*
+			 * now everything is in ctx_soft_pmds[] and we need
+			 * to clear the saved context from save_regs() such that
+			 * pfm_read_pmds() gets the correct value
+			 */
+			task->thread.pmd[i] = 0;
 
-	/* clears all PMD registers */
-	for(i=0;i< pmu_conf.num_pmds; i++) {
-		if (PMD_IS_IMPL(i))  ia64_set_pmd(i,0);
+			/* take care of overflow inline */
+			if (mask & 0x1) {
+				ctx->ctx_soft_pmds[i].val += 1 + pmu_conf.perf_ovfl_val;
+				DBprintk(("[%d] pmd[%d] overflowed soft_pmd=0x%lx\n",
+					task->pid, i, ctx->ctx_soft_pmds[i].val));
+			}
+		} else {
+			DBprintk(("[%d] pmd[%d] hw_pmd=0x%lx\n", task->pid, i, val));
+			/* not a counter, just save value as is */
+			task->thread.pmd[i] = val;
+		}
 	}
-	ia64_srlz_d();
+	/* 
+	 * indicates that context has been saved
+	 */
+	atomic_set(&ctx->ctx_last_cpu, -1);
+
 }
 
+
 /*
- * task is the newly created task
+ * task is the newly created task, pt_regs for new child
  */
 int
 pfm_inherit(struct task_struct *task, struct pt_regs *regs)
@@ -2207,25 +3452,29 @@
 	pfm_context_t *ctx = current->thread.pfm_context;
 	pfm_context_t *nctx;
 	struct thread_struct *th = &task->thread;
-	int i, cnum;
+	unsigned long m;
+	int i;
 
 	/*
-	 * bypass completely for system wide
+	 * make sure child cannot mess up the monitoring session
 	 */
-	if (pfs_info.pfs_sys_session) {
-		DBprintk((" enabling psr.pp for %d\n", task->pid));
-		ia64_psr(regs)->pp = pfs_info.pfs_pp;
-		return 0;
-	}
+	 ia64_psr(regs)->sp = 1;
+	 DBprintk(("enabling psr.sp for [%d]\n", task->pid));
+
+	 /*
+	  * remove any sampling buffer mapping from child user 
+	  * address space. Must be done for all cases of inheritance.
+	  */
+	 if (ctx->ctx_smpl_vaddr) pfm_remove_smpl_mapping(task);
 
 	/*
 	 * takes care of easiest case first
 	 */
 	if (CTX_INHERIT_MODE(ctx) == PFM_FL_INHERIT_NONE) {
-		DBprintk((" removing PFM context for %d\n", task->pid));
+		DBprintk(("removing PFM context for [%d]\n", task->pid));
 		task->thread.pfm_context     = NULL;
-		task->thread.pfm_must_block  = 0;
-		atomic_set(&task->thread.pfm_notifiers_check, 0);
+		task->thread.pfm_ovfl_block_reset  = 0;
+
 		/* copy_thread() clears IA64_THREAD_PM_VALID */
 		return 0;
 	}
@@ -2235,45 +3484,81 @@
 	/* copy content */
 	*nctx = *ctx;
 
+
 	if (CTX_INHERIT_MODE(ctx) == PFM_FL_INHERIT_ONCE) {
 		nctx->ctx_fl_inherit = PFM_FL_INHERIT_NONE;
-		atomic_set(&task->thread.pfm_notifiers_check, 0);
-		DBprintk((" downgrading to INHERIT_NONE for %d\n", task->pid));
-		pfs_info.pfs_proc_sessions++;
+		atomic_set(&nctx->ctx_last_cpu, -1);
+
+		/*
+		 * task is not yet visible in the tasklist, so we do 
+		 * not need to lock the newly created context.
+		 * However, we must grab the tasklist_lock to ensure
+		 * that the ctx_owner or ctx_notify_task do not disappear
+		 * while we increment their check counters.
+		 */
+		read_lock(&tasklist_lock);
+
+		if (nctx->ctx_notify_task) 
+			atomic_inc(&nctx->ctx_notify_task->thread.pfm_notifiers_check);
+
+		if (nctx->ctx_owner)
+			atomic_inc(&nctx->ctx_owner->thread.pfm_owners_check);
+
+		read_unlock(&tasklist_lock);
+
+		DBprintk(("downgrading to INHERIT_NONE for [%d]\n", task->pid));
+
+		LOCK_PFS();
+		pfm_sessions.pfs_task_sessions++;
+		UNLOCK_PFS();
 	}
 
 	/* initialize counters in new context */
-	for(i=0, cnum= PMU_FIRST_COUNTER; i < pmu_conf.max_counters; cnum++, i++) {
-		nctx->ctx_pmds[i].val = nctx->ctx_pmds[i].ival & ~pmu_conf.perf_ovfl_val;
-		th->pmd[cnum]	      = nctx->ctx_pmds[i].ival & pmu_conf.perf_ovfl_val;
+	m = pmu_conf.counter_pmds[0] >> PMU_FIRST_COUNTER;
+	for(i = PMU_FIRST_COUNTER ; m ; m>>=1, i++) {
+		if (m & 0x1) {
+			nctx->ctx_soft_pmds[i].val = nctx->ctx_soft_pmds[i].ival & ~pmu_conf.perf_ovfl_val;
+			th->pmd[i]	      	   = nctx->ctx_soft_pmds[i].ival & pmu_conf.perf_ovfl_val;
+		}
 
 	}
 	/* clear BTB index register */
 	th->pmd[16] = 0;
 
 	/* if sampling then increment number of users of buffer */
-	if (nctx->ctx_smpl_buf) {
-		atomic_inc(&nctx->ctx_smpl_buf->psb_refcnt);
+	if (nctx->ctx_psb) {
+
+		/*
+		 * XXX: nopt very pretty!
+		 */
+		LOCK_PSB(nctx->ctx_psb);
+		nctx->ctx_psb->psb_refcnt++;
+		UNLOCK_PSB(nctx->ctx_psb);
+		/*
+	 	 * remove any pointer to sampling buffer mapping
+	 	 */
+		nctx->ctx_smpl_vaddr = 0;
 	}
 
 	nctx->ctx_fl_frozen = 0;
-	nctx->ctx_ovfl_regs = 0;
+	nctx->ctx_ovfl_regs[0] = 0UL;
+
 	sema_init(&nctx->ctx_restart_sem, 0); /* reset this semaphore to locked */
 
 	/* clear pending notification */
-	th->pfm_must_block = 0;
+	th->pfm_ovfl_block_reset = 0;
 
 	/* link with new task */
-	th->pfm_context     = nctx;
+	th->pfm_context    = nctx;
 
-	DBprintk((" nctx=%p for process %d\n", (void *)nctx, task->pid));
+	DBprintk(("nctx=%p for process [%d]\n", (void *)nctx, task->pid));
 
 	/*
 	 * the copy_thread routine automatically clears
 	 * IA64_THREAD_PM_VALID, so we need to reenable it, if it was used by the caller
 	 */
 	if (current->thread.flags & IA64_THREAD_PM_VALID) {
-		DBprintk(("  setting PM_VALID for %d\n", task->pid));
+		DBprintk(("setting PM_VALID for [%d]\n", task->pid));
 		th->flags |= IA64_THREAD_PM_VALID;
 	}
 
@@ -2281,100 +3566,249 @@
 }
 
 /* 
- * called from release_thread(), at this point this task is not in the 
- * tasklist anymore
+ *
+ * We cannot touch any of the PMU registers at this point as we may
+ * not be running on the same CPU the task was last run on.  Therefore
+ * it is assumed that the PMU has been stopped appropriately in
+ * pfm_flush_regs() called from exit_thread(). 
+ *
+ * The function is called in the context of the parent via a release_thread()
+ * and wait4(). The task is not in the tasklist anymore.
  */
 void
 pfm_context_exit(struct task_struct *task)
 {
 	pfm_context_t *ctx = task->thread.pfm_context;
 
-	if (!ctx) {
-		DBprintk((" invalid context for %d\n", task->pid));
-		return;
-	}
+	/*
+	 * check sampling buffer
+	 */
+	if (ctx->ctx_psb) {
+		pfm_smpl_buffer_desc_t *psb = ctx->ctx_psb;
+
+		LOCK_PSB(psb);
+
+		DBprintk(("sampling buffer from [%d] @%p size %ld vma_flag=0x%x\n",
+			task->pid,
+			psb->psb_hdr, psb->psb_size, psb->psb_flags));
+
+		/*
+		 * in the case where we are the last user, we may be able to free
+		 * the buffer
+		 */
+		psb->psb_refcnt--;
+
+		if (psb->psb_refcnt == 0) {
+
+			/*
+			 * The flag is cleared in pfm_vm_close(). which gets 
+			 * called from do_exit() via exit_mm(). 
+			 * By the time we come here, the task has no more mm context.
+			 *
+			 * We can only free the psb and buffer here after the vm area
+			 * describing the buffer has been removed. This normally happens 
+			 * as part of do_exit() but the entire mm context is ONLY removed
+			 * once its reference counts goes to zero. This is typically
+			 * the case except for multi-threaded (several tasks) processes.
+			 *
+			 * See pfm_vm_close() and pfm_cleanup_smpl_buf() for more details.
+			 */
+			if ((psb->psb_flags & PFM_PSB_VMA) == 0) {
+
+				DBprintk(("cleaning sampling buffer from [%d] @%p size %ld\n",
+					task->pid,
+					psb->psb_hdr, psb->psb_size));
+
+				/* 
+				 * free the buffer and psb 
+				 */
+				pfm_rvfree(psb->psb_hdr, psb->psb_size);
+				kfree(psb);
+				psb = NULL;
+			} 
+		} 
+		/* psb may have been deleted */
+		if (psb) UNLOCK_PSB(psb);
+	} 
+
+	DBprintk(("cleaning [%d] pfm_context @%p notify_task=%p check=%d mm=%p\n", 
+		task->pid, ctx, 
+		ctx->ctx_notify_task, 
+		atomic_read(&task->thread.pfm_notifiers_check), task->mm));
 
-	/* check is we have a sampling buffer attached */
-	if (ctx->ctx_smpl_buf) {
-		pfm_smpl_buffer_desc_t *psb = ctx->ctx_smpl_buf;
-
-		/* if only user left, then remove */
-		DBprintk((" [%d] [%d] psb->refcnt=%d\n", current->pid, task->pid, psb->psb_refcnt.counter));
-
-		if (atomic_dec_and_test(&psb->psb_refcnt) ) {
-			rvfree(psb->psb_hdr, psb->psb_size);
-			vfree(psb);
-			DBprintk((" [%d] cleaning [%d] sampling buffer\n", current->pid, task->pid ));
-		}
-	}
-	DBprintk((" [%d] cleaning [%d] pfm_context @%p\n", current->pid, task->pid, (void *)ctx));
-
-	/*
-	 * To avoid getting the notified task scan the entire process list
-	 * when it exits because it would have pfm_notifiers_check set, we 
-	 * decrease it by 1 to inform the task, that one less task is going
-	 * to send it notification. each new notifer increases this field by
-	 * 1 in pfm_context_create(). Of course, there is race condition between
-	 * decreasing the value and the notified task exiting. The danger comes
-	 * from the fact that we have a direct pointer to its task structure
-	 * thereby bypassing the tasklist. We must make sure that if we have 
-	 * notify_task!= NULL, the target task is still somewhat present. It may
-	 * already be detached from the tasklist but that's okay. Note that it is
-	 * okay if we 'miss the deadline' and the task scans the list for nothing,
-	 * it will affect performance but not correctness. The correctness is ensured
-	 * by using the notify_lock whic prevents the notify_task from changing on us.
-	 * Once holdhing this lock, if we see notify_task!= NULL, then it will stay like
+	/*
+	 * To avoid getting the notified task or owner task scan the entire process 
+	 * list when they exit, we decrement notifiers_check and owners_check respectively.
+	 *
+	 * Of course, there is race condition between decreasing the value and the 
+	 * task exiting. The danger comes from the fact that, in both cases, we have a 
+	 * direct pointer to a task structure thereby bypassing the tasklist. 
+	 * We must make sure that, if we have task!= NULL, the target task is still 
+	 * present and is identical to the initial task specified 
+	 * during pfm_create_context(). It may already be detached from the tasklist but 
+	 * that's okay. Note that it is okay if we miss the deadline and the task scans 
+	 * the list for nothing, it will affect performance but not correctness. 
+	 * The correctness is ensured by using the ctx_lock which prevents the 
+	 * notify_task from changing the fields in our context.
+	 * Once holdhing this lock, if we see task!= NULL, then it will stay like
 	 * that until we release the lock. If it is NULL already then we came too late.
 	 */
-	spin_lock(&ctx->ctx_notify_lock);
+	LOCK_CTX(ctx);
 
-	if (ctx->ctx_notify_task) {
-		DBprintk((" [%d] [%d] atomic_sub on [%d] notifiers=%u\n", current->pid, task->pid,
-					ctx->ctx_notify_task->pid, 
-					atomic_read(&ctx->ctx_notify_task->thread.pfm_notifiers_check)));
+	if (ctx->ctx_notify_task != NULL) {
+		DBprintk(("[%d], [%d] atomic_sub on [%d] notifiers=%u\n", current->pid,
+			task->pid,
+			ctx->ctx_notify_task->pid, 
+			atomic_read(&ctx->ctx_notify_task->thread.pfm_notifiers_check)));
+
+		atomic_dec(&ctx->ctx_notify_task->thread.pfm_notifiers_check);
+	}
+
+	if (ctx->ctx_owner != NULL) {
+		DBprintk(("[%d], [%d] atomic_sub on [%d] owners=%u\n", 
+			 current->pid, 
+			 task->pid,
+			 ctx->ctx_owner->pid, 
+			 atomic_read(&ctx->ctx_owner->thread.pfm_owners_check)));
 
-		atomic_sub(1, &ctx->ctx_notify_task->thread.pfm_notifiers_check);
+		atomic_dec(&ctx->ctx_owner->thread.pfm_owners_check);
 	}
 
-	spin_unlock(&ctx->ctx_notify_lock);
+	UNLOCK_CTX(ctx);
+
+	LOCK_PFS();
 
 	if (ctx->ctx_fl_system) {
-		/*
-		 * if included interrupts (true by default), then reset
-		 * to get default value
-		 */
-		if (ctx->ctx_fl_exclintr == 0) {
-			/*
-			 * reload kernel default DCR value
-			 */
-			ia64_set_dcr(pfs_info.pfs_dfl_dcr);
-			DBprintk((" restored dcr to 0x%lx\n", pfs_info.pfs_dfl_dcr));
+
+		pfm_sessions.pfs_sys_session[ctx->ctx_cpu] = NULL;
+		pfm_sessions.pfs_sys_sessions--;
+		DBprintk(("freeing syswide session on CPU%ld\n", ctx->ctx_cpu));
+		/* update perfmon debug register counter */
+		if (ctx->ctx_fl_using_dbreg) {
+			if (pfm_sessions.pfs_sys_use_dbregs == 0) {
+				printk("perfmon: invalid release for [%d] sys_use_dbregs=0\n", task->pid);
+			} else
+				pfm_sessions.pfs_sys_use_dbregs--;
 		}
-		/* 
-		 * free system wide session slot
-		 */
-		pfs_info.pfs_sys_session = 0;
+
+		/*
+	 	 * remove any CPU pinning
+	 	 */
+		task->cpus_allowed = ctx->ctx_saved_cpus_allowed;
+		task->need_resched = 1;
 	} else {
-		pfs_info.pfs_proc_sessions--;
+		pfm_sessions.pfs_task_sessions--;
 	}
+	UNLOCK_PFS();
 
 	pfm_context_free(ctx);
 	/* 
 	 *  clean pfm state in thread structure,
 	 */
-	task->thread.pfm_context    = NULL;
-	task->thread.pfm_must_block = 0;
+	task->thread.pfm_context          = NULL;
+	task->thread.pfm_ovfl_block_reset = 0;
+
 	/* pfm_notifiers is cleaned in pfm_cleanup_notifiers() */
+}
+
+/*
+ * function invoked from release_thread when pfm_smpl_buf_list is not NULL
+ */
+int
+pfm_cleanup_smpl_buf(struct task_struct *task)
+{
+	pfm_smpl_buffer_desc_t *tmp, *psb = task->thread.pfm_smpl_buf_list;
 
+	if (psb == NULL) {
+		printk("perfmon: psb is null in [%d]\n", current->pid);
+		return -1;
+	}
+	/*
+	 * Walk through the list and free the sampling buffer and psb
+	 */
+	while (psb) {
+		DBprintk(("[%d] freeing smpl @%p size %ld\n", current->pid, psb->psb_hdr, psb->psb_size));
+
+		pfm_rvfree(psb->psb_hdr, psb->psb_size);
+		tmp = psb->psb_next;
+		kfree(psb);
+		psb = tmp;
+	}
+
+	/* just in case */
+	task->thread.pfm_smpl_buf_list = NULL;
+
+	return 0;
+}
+
+/*
+ * function invoked from release_thread to make sure that the ctx_owner field does not
+ * point to an unexisting task.
+ */
+void
+pfm_cleanup_owners(struct task_struct *task)
+{
+	struct task_struct *p;
+	pfm_context_t *ctx;
+
+	DBprintk(("called by [%d] for [%d]\n", current->pid, task->pid));
+
+	read_lock(&tasklist_lock);
+
+	for_each_task(p) {
+		/*
+		 * It is safe to do the 2-step test here, because thread.ctx
+		 * is cleaned up only in release_thread() and at that point
+		 * the task has been detached from the tasklist which is an
+		 * operation which uses the write_lock() on the tasklist_lock
+		 * so it cannot run concurrently to this loop. So we have the
+		 * guarantee that if we find p and it has a perfmon ctx then
+		 * it is going to stay like this for the entire execution of this
+		 * loop.
+		 */
+		ctx = p->thread.pfm_context;
+
+		//DBprintk(("[%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx));
+
+		if (ctx && ctx->ctx_owner == task) {
+			DBprintk(("trying for owner [%d] in [%d]\n", task->pid, p->pid));
+			/*
+			 * the spinlock is required to take care of a race condition
+			 * with the send_sig_info() call. We must make sure that 
+			 * either the send_sig_info() completes using a valid task,
+			 * or the notify_task is cleared before the send_sig_info()
+			 * can pick up a stale value. Note that by the time this
+			 * function is executed the 'task' is already detached from the
+			 * tasklist. The problem is that the notifiers have a direct
+			 * pointer to it. It is okay to send a signal to a task in this
+			 * stage, it simply will have no effect. But it is better than sending
+			 * to a completely destroyed task or worse to a new task using the same
+			 * task_struct address.
+			 */
+			LOCK_CTX(ctx);
+
+			ctx->ctx_owner = NULL;
+
+			UNLOCK_CTX(ctx);
+
+			DBprintk(("done for notifier [%d] in [%d]\n", task->pid, p->pid));
+		}
+	}
+	read_unlock(&tasklist_lock);
 }
 
+
+/*
+ * function called from release_thread to make sure that the ctx_notify_task is not pointing
+ * to an unexisting task
+ */
 void
 pfm_cleanup_notifiers(struct task_struct *task)
 {
 	struct task_struct *p;
 	pfm_context_t *ctx;
 
-	DBprintk((" [%d] called\n", task->pid));
+	DBprintk(("called by [%d] for [%d]\n", current->pid, task->pid));
 
 	read_lock(&tasklist_lock);
 
@@ -2391,10 +3825,10 @@
 		 */
 		ctx = p->thread.pfm_context;
 
-		DBprintk((" [%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx));
+		//DBprintk(("[%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx));
 
 		if (ctx && ctx->ctx_notify_task == task) {
-			DBprintk((" trying for notifier %d in %d\n", task->pid, p->pid));
+			DBprintk(("trying for notifier [%d] in [%d]\n", task->pid, p->pid));
 			/*
 			 * the spinlock is required to take care of a race condition
 			 * with the send_sig_info() call. We must make sure that 
@@ -2408,23 +3842,146 @@
 			 * to a completely destroyed task or worse to a new task using the same
 			 * task_struct address.
 			 */
-			spin_lock(&ctx->ctx_notify_lock);
+			LOCK_CTX(ctx);
 
 			ctx->ctx_notify_task = NULL;
 
-			spin_unlock(&ctx->ctx_notify_lock);
+			UNLOCK_CTX(ctx);
 
-			DBprintk((" done for notifier %d in %d\n", task->pid, p->pid));
+			DBprintk(("done for notifier [%d] in [%d]\n", task->pid, p->pid));
 		}
 	}
 	read_unlock(&tasklist_lock);
+}
+
+static struct irqaction perfmon_irqaction = {
+	handler:	perfmon_interrupt,
+	flags:		SA_INTERRUPT,
+	name:		"perfmon"
+};
+
 
+static void
+pfm_pmu_snapshot(void)
+{
+	int i;
+
+	for (i=0; i < IA64_NUM_PMC_REGS; i++) {
+		if (i >= pmu_conf.num_pmcs) break;
+		if (PMC_IS_IMPL(i)) reset_pmcs[i] = ia64_get_pmc(i);
+	}
+}
+
+/*
+ * perfmon initialization routine, called from the initcall() table
+ */
+int __init
+perfmon_init (void)
+{
+	pal_perf_mon_info_u_t pm_info;
+	s64 status;
+
+	register_percpu_irq(IA64_PERFMON_VECTOR, &perfmon_irqaction);
+
+	ia64_set_pmv(IA64_PERFMON_VECTOR);
+	ia64_srlz_d();
+
+	pmu_conf.pfm_is_disabled = 1;
+
+	printk("perfmon: version %u.%u (sampling format v%u.%u) IRQ %u\n", 
+		PFM_VERSION_MAJ, 
+		PFM_VERSION_MIN, 
+		PFM_SMPL_VERSION_MAJ, 
+		PFM_SMPL_VERSION_MIN, 
+		IA64_PERFMON_VECTOR);
+
+	if ((status=ia64_pal_perf_mon_info(pmu_conf.impl_regs, &pm_info)) != 0) {
+		printk("perfmon: PAL call failed (%ld), perfmon disabled\n", status);
+		return -1;
+	}
+
+	pmu_conf.perf_ovfl_val = (1UL << pm_info.pal_perf_mon_info_s.width) - 1;
+	pmu_conf.max_counters  = pm_info.pal_perf_mon_info_s.generic;
+	pmu_conf.num_pmcs      = find_num_pm_regs(pmu_conf.impl_regs);
+	pmu_conf.num_pmds      = find_num_pm_regs(&pmu_conf.impl_regs[4]);
+
+	printk("perfmon: %u bits counters\n", pm_info.pal_perf_mon_info_s.width);
+
+	printk("perfmon: %lu PMC/PMD pairs, %lu PMCs, %lu PMDs\n", 
+	       pmu_conf.max_counters, pmu_conf.num_pmcs, pmu_conf.num_pmds);
+
+	/* sanity check */
+	if (pmu_conf.num_pmds >= IA64_NUM_PMD_REGS || pmu_conf.num_pmcs >= IA64_NUM_PMC_REGS) {
+		printk(KERN_ERR "perfmon: not enough pmc/pmd, perfmon is DISABLED\n");
+		return -1; /* no need to continue anyway */
+	}
+
+	if (ia64_pal_debug_info(&pmu_conf.num_ibrs, &pmu_conf.num_dbrs)) {
+		printk(KERN_WARNING "perfmon: unable to get number of debug registers\n");
+		pmu_conf.num_ibrs = pmu_conf.num_dbrs = 0;
+	}
+	/* PAL reports the number of pairs */
+	pmu_conf.num_ibrs <<=1;
+	pmu_conf.num_dbrs <<=1;
+
+	/*
+	 * take a snapshot of all PMU registers. PAL is supposed
+	 * to configure them with stable/safe values, i.e., not
+	 * capturing anything.
+	 * We take a snapshot now, before we make any modifications. This
+	 * will become our master copy. Then we will reuse the snapshot
+	 * to reset the PMU in pfm_enable(). Using this technique, perfmon
+	 * does NOT have to know about the specific values to program for
+	 * the PMC/PMD. The safe values may be different from one CPU model to
+	 * the other.
+	 */
+	pfm_pmu_snapshot();
+
+	/* 
+	 * list the pmc registers used to control monitors 
+	 * XXX: unfortunately this information is not provided by PAL
+	 *
+	 * We start with the architected minimum and then refine for each CPU model
+	 */
+	pmu_conf.monitor_pmcs[0] = PMM(4)|PMM(5)|PMM(6)|PMM(7);
+
+	/*
+	 * architected counters
+	 */
+	pmu_conf.counter_pmds[0] |= PMM(4)|PMM(5)|PMM(6)|PMM(7);
+
+#ifdef CONFIG_ITANIUM
+	pmu_conf.monitor_pmcs[0] |= PMM(10)|PMM(11)|PMM(12);
+	/* Itanium does not add more counters */
+#endif
+	/* we are all set */
+	pmu_conf.pfm_is_disabled = 0;
+
+	/*
+	 * for now here for debug purposes
+	 */
+	perfmon_dir = create_proc_read_entry ("perfmon", 0, 0, perfmon_read_entry, NULL);
+
+	spin_lock_init(&pfm_sessions.pfs_lock);
+
+	return 0;
+}
+
+__initcall(perfmon_init);
+
+void
+perfmon_init_percpu (void)
+{
+	ia64_set_pmv(IA64_PERFMON_VECTOR);
+	ia64_srlz_d();
 }
 
+
 #else /* !CONFIG_PERFMON */
 
 asmlinkage int
-sys_perfmonctl (int pid, int cmd, int flags, perfmon_req_t *req, int count, long arg6, long arg7, long arg8, long stack)
+sys_perfmonctl (int pid, int cmd, void *req, int count, long arg5, long arg6, 
+		long arg7, long arg8, long stack)
 {
 	return -ENOSYS;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/process.c linux/arch/ia64/kernel/process.c
--- linux.orig/arch/ia64/kernel/process.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/process.c	2002-08-01 06:42:43.000000000 +0000
@@ -1,8 +1,8 @@
 /*
  * Architecture-specific setup.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #define __KERNEL_SYSCALLS__	/* see <asm/unistd.h> */
 #include <linux/config.h>
@@ -12,6 +12,7 @@
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
+#include <linux/personality.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/smp_lock.h>
@@ -28,6 +29,10 @@
 #include <asm/unwind.h>
 #include <asm/user.h>
 
+#ifdef CONFIG_IA64_SGI_SN
+#include <asm/sn/idle.h>
+#endif
+
 static void
 do_show_stack (struct unw_frame_info *info, void *arg)
 {
@@ -46,6 +51,15 @@
 }
 
 void
+show_trace_task (struct task_struct *task)
+{
+	struct unw_frame_info info;
+
+	unw_init_from_blocked_task(&info, task);
+	do_show_stack(&info, 0);
+}
+
+void
 show_stack (struct task_struct *task)
 {
 	if (!task)
@@ -90,8 +104,8 @@
 	printk("r26 : %016lx r27 : %016lx r28 : %016lx\n", regs->r26, regs->r27, regs->r28);
 	printk("r29 : %016lx r30 : %016lx r31 : %016lx\n", regs->r29, regs->r30, regs->r31);
 
-	/* print the stacked registers if cr.ifs is valid: */
-	if (regs->cr_ifs & 0x8000000000000000) {
+	if (user_mode(regs)) {
+		/* print the stacked registers */
 		unsigned long val, sof, *bsp, ndirty;
 		int i, is_nat = 0;
 
@@ -122,8 +136,18 @@
 		if (!current->need_resched)
 			min_xtp();
 #endif
-		while (!current->need_resched)
+
+		while (!current->need_resched) {
+#ifdef CONFIG_IA64_SGI_SN
+			snidle();
+#endif
 			continue;
+		}
+
+#ifdef CONFIG_IA64_SGI_SN
+		snidleoff();
+#endif
+
 #ifdef CONFIG_SMP
 		normal_xtp();
 #endif
@@ -139,10 +163,17 @@
 {
 	if ((task->thread.flags & IA64_THREAD_DBG_VALID) != 0)
 		ia64_save_debug_regs(&task->thread.dbr[0]);
+
 #ifdef CONFIG_PERFMON
 	if ((task->thread.flags & IA64_THREAD_PM_VALID) != 0)
 		pfm_save_regs(task);
+
+# ifdef CONFIG_SMP
+	if (local_cpu_data->pfm_syst_wide)
+		pfm_syst_wide_update_task(task, 0);
+# endif
 #endif
+
 	if (IS_IA32_PROCESS(ia64_task_regs(task)))
 		ia32_save_state(task);
 }
@@ -152,10 +183,17 @@
 {
 	if ((task->thread.flags & IA64_THREAD_DBG_VALID) != 0)
 		ia64_load_debug_regs(&task->thread.dbr[0]);
+
 #ifdef CONFIG_PERFMON
 	if ((task->thread.flags & IA64_THREAD_PM_VALID) != 0)
 		pfm_load_regs(task);
+
+# ifdef CONFIG_SMP
+	if (local_cpu_data->pfm_syst_wide)
+		pfm_syst_wide_update_task(task, 1);
+# endif
 #endif
+
 	if (IS_IA32_PROCESS(ia64_task_regs(task)))
 		ia32_load_state(task);
 }
@@ -235,7 +273,7 @@
 
 	if (user_mode(child_ptregs)) {
 		if (user_stack_base) {
-			child_ptregs->r12 = user_stack_base + user_stack_size;
+			child_ptregs->r12 = user_stack_base + user_stack_size - 16;
 			child_ptregs->ar_bspstore = user_stack_base;
 			child_ptregs->ar_rnat = 0;
 			child_ptregs->loadrs = 0;
@@ -288,9 +326,15 @@
 	if (IS_IA32_PROCESS(ia64_task_regs(current)))
 		ia32_save_state(p);
 #endif
+
 #ifdef CONFIG_PERFMON
-	if (p->thread.pfm_context)
-		retval = pfm_inherit(p, child_ptregs);
+	/*
+	 * reset notifiers and owner check (may not have a perfmon context)
+	 */
+	atomic_set(&p->thread.pfm_notifiers_check, 0);
+	atomic_set(&p->thread.pfm_owners_check, 0);
+
+	if (current->thread.pfm_context) retval = pfm_inherit(p, child_ptregs);
 #endif
 	return retval;
 }
@@ -414,6 +458,16 @@
 	return error;
 }
 
+void
+ia64_set_personality (struct elf64_hdr *elf_ex, int ibcs2_interpreter)
+{
+	set_personality(PER_LINUX);
+	if (elf_ex->e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK)
+		current->thread.flags |= IA64_THREAD_XSTACK;
+	else
+		current->thread.flags &= ~IA64_THREAD_XSTACK;
+}
+
 pid_t
 kernel_thread (int (*fn)(void *), void *arg, unsigned long flags)
 {
@@ -445,15 +499,15 @@
 
 #ifdef CONFIG_PERFMON
 /*
- * By the time we get here, the task is detached from the tasklist. This is important
- * because it means that no other tasks can ever find it as a notifiied task, therfore
- * there is no race condition between this code and let's say a pfm_context_create().
- * Conversely, the pfm_cleanup_notifiers() cannot try to access a task's pfm context if
- * this other task is in the middle of its own pfm_context_exit() because it would alreayd
- * be out of the task list. Note that this case is very unlikely between a direct child
- * and its parents (if it is the notified process) because of the way the exit is notified
- * via SIGCHLD.
+ * by the time we get here, the task is detached from the tasklist. This is important
+ * because it means that no other tasks can ever find it as a notified task, therfore there
+ * is no race condition between this code and let's say a pfm_context_create().
+ * Conversely, the pfm_cleanup_notifiers() cannot try to access a task's pfm context if this
+ * other task is in the middle of its own pfm_context_exit() because it would already be out of
+ * the task list. Note that this case is very unlikely between a direct child and its parents
+ * (if it is the notified process) because of the way the exit is notified via SIGCHLD.
  */
+
 void
 release_thread (struct task_struct *task)
 {
@@ -462,6 +516,12 @@
 
 	if (atomic_read(&task->thread.pfm_notifiers_check) > 0)
 		pfm_cleanup_notifiers(task);
+
+	if (atomic_read(&task->thread.pfm_owners_check) > 0)
+		pfm_cleanup_owners(task);
+
+	if (task->thread.pfm_smpl_buf_list)
+		pfm_cleanup_smpl_buf(task);
 }
 #endif
 
@@ -477,21 +537,13 @@
 		ia64_set_fpu_owner(0);
 #endif
 #ifdef CONFIG_PERFMON
-       /* stop monitoring */
-	if ((current->thread.flags & IA64_THREAD_PM_VALID) != 0) {
-		/*
-		 * we cannot rely on switch_to() to save the PMU
-		 * context for the last time. There is a possible race
-		 * condition in SMP mode between the child and the
-		 * parent.  by explicitly saving the PMU context here
-		 * we garantee no race.  this call we also stop
-		 * monitoring
-		 */
+       /* if needed, stop monitoring and flush state to perfmon context */
+	if (current->thread.pfm_context) 
 		pfm_flush_regs(current);
-		/*
-		 * make sure that switch_to() will not save context again
-		 */
-		current->thread.flags &= ~IA64_THREAD_PM_VALID;
+
+	/* free debug register resources */
+	if ((current->thread.flags & IA64_THREAD_DBG_VALID) != 0) {
+		pfm_release_debug_registers(current);
 	}
 #endif
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/ptrace.c linux/arch/ia64/kernel/ptrace.c
--- linux.orig/arch/ia64/kernel/ptrace.c	2001-11-21 19:04:18.000000000 +0000
+++ linux/arch/ia64/kernel/ptrace.c	2002-08-01 06:42:43.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * Kernel support for the ptrace() and syscall tracing interfaces.
  *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Derived from the x86 and Alpha versions.  Most of the code in here
@@ -23,6 +23,9 @@
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/unwind.h>
+#ifdef CONFIG_PERFMON
+# include <asm/perfmon.h>
+#endif
 
 /*
  * Bits in the PSR that we allow ptrace() to change:
@@ -755,11 +758,6 @@
 	} else {
 		/* access debug registers */
 
-		if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
-			child->thread.flags |= IA64_THREAD_DBG_VALID;
-			memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
-			memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
-		}
 		if (addr >= PT_IBR) {
 			regnum = (addr - PT_IBR) >> 3;
 			ptr = &child->thread.ibr[0];
@@ -772,6 +770,30 @@
 			dprintk("ptrace: rejecting access to register address 0x%lx\n", addr);
 			return -1;
 		}
+#ifdef CONFIG_PERFMON
+		/*
+		 * Check if debug registers are used by perfmon. This test must be done
+		 * once we know that we can do the operation, i.e. the arguments are all
+		 * valid, but before we start modifying the state.
+		 *
+		 * Perfmon needs to keep a count of how many processes are trying to
+		 * modify the debug registers for system wide monitoring sessions.
+		 *
+		 * We also include read access here, because they may cause the
+		 * PMU-installed debug register state (dbr[], ibr[]) to be reset. The two
+		 * arrays are also used by perfmon, but we do not use
+		 * IA64_THREAD_DBG_VALID. The registers are restored by the PMU context
+		 * switch code.
+		 */
+		if (pfm_use_debug_registers(child))
+			return -1;
+#endif
+
+		if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
+			child->thread.flags |= IA64_THREAD_DBG_VALID;
+			memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
+			memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
+		}
 
 		ptr += regnum;
 
@@ -789,6 +811,260 @@
 	return 0;
 }
 
+static long
+ptrace_getregs (struct task_struct *child, struct pt_all_user_regs *ppr)
+{
+	struct switch_stack *sw;
+	struct pt_regs *pt;
+	long ret, retval;
+	struct unw_frame_info info;
+	char nat = 0;
+	int i;
+
+	retval = verify_area(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs));
+	if (retval != 0) {
+		return -EIO;
+	}
+
+	pt = ia64_task_regs(child);
+	sw = (struct switch_stack *) (child->thread.ksp + 16);
+	unw_init_from_blocked_task(&info, child);
+	if (unw_unwind_to_user(&info) < 0) {
+		return -EIO;
+	}
+
+	if (((unsigned long) ppr & 0x7) != 0) {
+		dprintk("ptrace:unaligned register address %p\n", ppr);
+		return -EIO;
+	}
+
+	retval = 0;
+
+	/* control regs */
+
+	retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
+	retval |= access_uarea(child, PT_CR_IPSR, &ppr->cr_ipsr, 0);
+
+	/* app regs */
+
+	retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
+	retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
+	retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
+	retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
+	retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
+	retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
+
+	retval |= access_uarea(child, PT_AR_EC, &ppr->ar[PT_AUR_EC], 0);
+	retval |= access_uarea(child, PT_AR_LC, &ppr->ar[PT_AUR_LC], 0);
+	retval |= access_uarea(child, PT_AR_RNAT, &ppr->ar[PT_AUR_RNAT], 0);
+	retval |= access_uarea(child, PT_AR_BSP, &ppr->ar[PT_AUR_BSP], 0);
+	retval |= access_uarea(child, PT_CFM, &ppr->cfm, 0);
+
+	/* gr1-gr3 */
+
+	retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long) * 3);
+
+	/* gr4-gr7 */
+
+	for (i = 4; i < 8; i++) {
+		retval |= unw_access_gr(&info, i, &ppr->gr[i], &nat, 0);
+	}
+
+	/* gr8-gr11 */
+
+	retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
+
+	/* gr12-gr15 */
+
+	retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 4);
+
+	/* gr16-gr31 */
+
+	retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
+
+	/* b0 */
+
+	retval |= __put_user(pt->b0, &ppr->br[0]);
+
+	/* b1-b5 */
+
+	for (i = 1; i < 6; i++) {
+		retval |= unw_access_br(&info, i, &ppr->br[i], 0);
+	}
+
+	/* b6-b7 */
+
+	retval |= __put_user(pt->b6, &ppr->br[6]);
+	retval |= __put_user(pt->b7, &ppr->br[7]);
+
+	/* fr2-fr5 */
+
+	for (i = 2; i < 6; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 0);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 0);
+	}
+
+	/* fr6-fr9 */
+
+	retval |= __copy_to_user(&ppr->fr[6], &pt->f6, sizeof(struct ia64_fpreg) * 4);
+
+	/* fp scratch regs(10-15) */
+
+	retval |= __copy_to_user(&ppr->fr[10], &sw->f10, sizeof(struct ia64_fpreg) * 6);
+
+	/* fr16-fr31 */
+
+	for (i = 16; i < 32; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 0);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 0);
+	}
+
+	/* fph */
+
+	ia64_flush_fph(child);
+	retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph, sizeof(ppr->fr[32]) * 96);
+
+	/* preds */
+
+	retval |= __put_user(pt->pr, &ppr->pr);
+
+	/* nat bits */
+
+	retval |= access_uarea(child, PT_NAT_BITS, &ppr->nat, 0);
+
+	ret = retval ? -EIO : 0;
+	return ret;
+}
+
+static long
+ptrace_setregs (struct task_struct *child, struct pt_all_user_regs *ppr)
+{
+	struct switch_stack *sw;
+	struct pt_regs *pt;
+	long ret, retval;
+	struct unw_frame_info info;
+	char nat = 0;
+	int i;
+
+	retval = verify_area(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs));
+	if (retval != 0) {
+		return -EIO;
+	}
+
+	pt = ia64_task_regs(child);
+	sw = (struct switch_stack *) (child->thread.ksp + 16);
+	unw_init_from_blocked_task(&info, child);
+	if (unw_unwind_to_user(&info) < 0) {
+		return -EIO;
+	}
+
+	if (((unsigned long) ppr & 0x7) != 0) {
+		dprintk("ptrace:unaligned register address %p\n", ppr);
+		return -EIO;
+	}
+
+	retval = 0;
+
+	/* control regs */
+
+	retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
+	retval |= access_uarea(child, PT_CR_IPSR, &ppr->cr_ipsr, 1);
+
+	/* app regs */
+
+	retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
+	retval |= __get_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
+	retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
+	retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
+	retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
+	retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
+
+	retval |= access_uarea(child, PT_AR_EC, &ppr->ar[PT_AUR_EC], 1);
+	retval |= access_uarea(child, PT_AR_LC, &ppr->ar[PT_AUR_LC], 1);
+	retval |= access_uarea(child, PT_AR_RNAT, &ppr->ar[PT_AUR_RNAT], 1);
+	retval |= access_uarea(child, PT_AR_BSP, &ppr->ar[PT_AUR_BSP], 1);
+	retval |= access_uarea(child, PT_CFM, &ppr->cfm, 1);
+
+	/* gr1-gr3 */
+
+	retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long) * 3);
+
+	/* gr4-gr7 */
+
+	for (i = 4; i < 8; i++) {
+		long ret = unw_get_gr(&info, i, &ppr->gr[i], &nat);
+		if (ret < 0) {
+			return ret;
+		}
+		retval |= unw_access_gr(&info, i, &ppr->gr[i], &nat, 1);
+	}
+
+	/* gr8-gr11 */
+
+	retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
+
+	/* gr12-gr15 */
+
+	retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 4);
+
+	/* gr16-gr31 */
+
+	retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
+
+	/* b0 */
+
+	retval |= __get_user(pt->b0, &ppr->br[0]);
+
+	/* b1-b5 */
+
+	for (i = 1; i < 6; i++) {
+		retval |= unw_access_br(&info, i, &ppr->br[i], 1);
+	}
+
+	/* b6-b7 */
+
+	retval |= __get_user(pt->b6, &ppr->br[6]);
+	retval |= __get_user(pt->b7, &ppr->br[7]);
+
+	/* fr2-fr5 */
+
+	for (i = 2; i < 6; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 1);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 1);
+	}
+
+	/* fr6-fr9 */
+
+	retval |= __copy_from_user(&pt->f6, &ppr->fr[6], sizeof(ppr->fr[6]) * 4);
+
+	/* fp scratch regs(10-15) */
+
+	retval |= __copy_from_user(&sw->f10, &ppr->fr[10], sizeof(ppr->fr[10]) * 6);
+
+	/* fr16-fr31 */
+
+	for (i = 16; i < 32; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 1);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 1);
+	}
+
+	/* fph */
+
+	ia64_sync_fph(child);
+	retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32], sizeof(ppr->fr[32]) * 96);
+
+	/* preds */
+
+	retval |= __get_user(pt->pr, &ppr->pr);
+
+	/* nat bits */
+
+	retval |= access_uarea(child, PT_NAT_BITS, &ppr->nat, 1);
+
+	ret = retval ? -EIO : 0;
+	return ret;
+}
+
 /*
  * Called by kernel/ptrace.c when detaching..
  *
@@ -979,6 +1255,14 @@
 		ret = ptrace_detach(child, data);
 		goto out_tsk;
 
+	      case PTRACE_GETREGS:
+		ret = ptrace_getregs(child, (struct pt_all_user_regs*) data);
+		goto out_tsk;
+
+	      case PTRACE_SETREGS:
+		ret = ptrace_setregs(child, (struct pt_all_user_regs*) data);
+		goto out_tsk;
+
 	      default:
 		ret = -EIO;
 		goto out_tsk;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/sal.c linux/arch/ia64/kernel/sal.c
--- linux.orig/arch/ia64/kernel/sal.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/sal.c	2002-08-01 06:42:48.000000000 +0000
@@ -18,7 +18,8 @@
 #include <asm/sal.h>
 #include <asm/pal.h>
 
-spinlock_t sal_lock = SPIN_LOCK_UNLOCKED;
+spinlock_t sal_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
+unsigned long sal_platform_features;
 
 static struct {
 	void *addr;	/* function entry point */
@@ -76,7 +77,7 @@
 	return str;
 }
 
-static void __init 
+static void __init
 ia64_sal_handler_init (void *entry_point, void *gpval)
 {
 	/* fill in the SAL procedure descriptor and point ia64_sal to it: */
@@ -102,7 +103,7 @@
 	if (strncmp(systab->signature, "SST_", 4) != 0)
 		printk("bad signature in system table!");
 
-	/* 
+	/*
 	 * revisions are coded in BCD, so %x does the job for us
 	 */
 	printk("SAL v%x.%02x: oem=%.32s, product=%.32s\n",
@@ -152,12 +153,12 @@
 		      case SAL_DESC_PLATFORM_FEATURE:
 		      {
 			      struct ia64_sal_desc_platform_feature *pf = (void *) p;
+			      sal_platform_features = pf->feature_mask;
 			      printk("SAL: Platform features ");
 
-			      if (pf->feature_mask & (1 << 0))
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_BUS_LOCK)
 				      printk("BusLock ");
-
-			      if (pf->feature_mask & (1 << 1)) {
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT) {
 				      printk("IRQ_Redirection ");
 #ifdef CONFIG_SMP
 				      if (no_int_routing)
@@ -166,15 +167,17 @@
 					      smp_int_redirect |= SMP_IRQ_REDIRECTION;
 #endif
 			      }
-			      if (pf->feature_mask & (1 << 2)) {
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT) {
 				      printk("IPI_Redirection ");
 #ifdef CONFIG_SMP
-				      if (no_int_routing) 
+				      if (no_int_routing)
 					      smp_int_redirect &= ~SMP_IPI_REDIRECTION;
 				      else
 					      smp_int_redirect |= SMP_IPI_REDIRECTION;
 #endif
 			      }
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)
+				      printk("ITC_Drift ");
 			      printk("\n");
 			      break;
  		      }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/setup.c linux/arch/ia64/kernel/setup.c
--- linux.orig/arch/ia64/kernel/setup.c	2001-11-13 17:01:16.000000000 +0000
+++ linux/arch/ia64/kernel/setup.c	2002-08-01 06:42:33.000000000 +0000
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1998-2001 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998, 1999, 2001 Stephane Eranian <eranian@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
  * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
@@ -147,6 +147,10 @@
 }
 
 
+/*
+ * Find a place to put the bootmap and return its starting address in bootmap_start.
+ * This address must be page-aligned.
+ */
 static int
 find_bootmap_location (unsigned long start, unsigned long end, void *arg)
 {
@@ -165,7 +169,7 @@
 
 	for (i = 0; i < num_rsvd_regions; i++) {
 		range_start = MAX(start, free_start);
-		range_end   = MIN(end, rsvd_region[i].start);
+		range_end   = MIN(end, rsvd_region[i].start & PAGE_MASK);
 
 		if (range_end <= range_start) continue;	/* skip over empty range */
 
@@ -177,7 +181,7 @@
 		/* nothing more available in this segment */
 		if (range_end == end) return 0;
 
-		free_start = rsvd_region[i].end;
+		free_start = PAGE_ALIGN(rsvd_region[i].end);
 	}
 	return 0;
 }
@@ -306,6 +310,10 @@
 	/* process SAL system table: */
 	ia64_sal_init(efi.sal_systab);
 
+#ifdef CONFIG_IA64_GENERIC
+	machvec_init(acpi_get_sysname());
+#endif
+
 	/*
 	 *  Set `iobase' to the appropriate address in region 6
 	 *    (uncached access range)
@@ -332,10 +340,6 @@
 
 	cpu_init();	/* initialize the bootstrap CPU */
 
-#ifdef CONFIG_IA64_GENERIC
-	machvec_init(acpi_get_sysname());
-#endif
-
 	if (efi.acpi20) {
 		/* Parse the ACPI 2.0 tables */
 		acpi20_parse(efi.acpi20);
@@ -343,6 +347,10 @@
 		/* Parse the ACPI tables */
 		acpi_parse(efi.acpi);
 	}
+	if (efi.hcdp) {
+		/* Setup the serial ports described by HCDP */
+		setup_serial_hcdp(efi.hcdp);
+	}
 
 #ifdef CONFIG_VT
 # if defined(CONFIG_VGA_CONSOLE)
@@ -371,17 +379,14 @@
 {
 #ifdef CONFIG_SMP
 #	define lpj	c->loops_per_jiffy
+#	define cpu	c->processor
 #else
 #	define lpj	loops_per_jiffy
+#	define cpu	0
 #endif
 	char family[32], features[128], *cp;
 	struct cpuinfo_ia64 *c = v;
-	unsigned long mask, cpu = c - cpu_data(0);
-
-#ifdef CONFIG_SMP
-	if (!(cpu_online_map & (1 << cpu)))
-		return 0;
-#endif
+	unsigned long mask;
 
 	mask = c->features;
 
@@ -403,7 +408,7 @@
 		sprintf(cp, " 0x%lx", mask);
 
 	seq_printf(m,
-		   "processor  : %lu\n"
+		   "processor  : %d\n"
 		   "vendor     : %s\n"
 		   "arch       : IA-64\n"
 		   "family     : %s\n"
@@ -427,6 +432,10 @@
 static void *
 c_start (struct seq_file *m, loff_t *pos)
 {
+#ifdef CONFIG_SMP
+	while (*pos < NR_CPUS && !(cpu_online_map & (1 << *pos)))
+		++*pos;
+#endif
 	return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
 }
 
@@ -483,6 +492,9 @@
 		cpuid.bits[i] = ia64_get_cpuid(i);
 
 	memcpy(c->vendor, cpuid.field.vendor, 16);
+#ifdef CONFIG_SMP
+	c->processor = smp_processor_id();
+#endif
 	c->ppn = cpuid.field.ppn;
 	c->number = cpuid.field.number;
 	c->revision = cpuid.field.revision;
@@ -534,7 +546,7 @@
 				= alloc_bootmem_pages_node(NODE_DATA(numa_node_id()),
 							   sizeof(struct cpuinfo_ia64));
 		for (cpu = 1; cpu < NR_CPUS; ++cpu)
-			memcpy(my_cpu_data->cpu_data[cpu]->cpu_data_ptrs,
+			memcpy(my_cpu_data->cpu_data[cpu]->cpu_data,
 			       my_cpu_data->cpu_data, sizeof(my_cpu_data->cpu_data));
 	} else {
 		order = get_order(sizeof(struct cpuinfo_ia64));
@@ -616,4 +628,6 @@
 		num_phys_stacked = 96;
 	}
 	local_cpu_data->phys_stacked_size_p8 = num_phys_stacked*8 + 8;
+
+	platform_cpu_init();
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/signal.c linux/arch/ia64/kernel/signal.c
--- linux.orig/arch/ia64/kernel/signal.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/signal.c	2002-08-01 06:42:29.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * Architecture-specific signal handling support.
  *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Derived from i386 and Alpha versions.
@@ -160,6 +160,7 @@
 		err |= __put_user((short)from->si_code, &to->si_code);
 		switch (from->si_code >> 16) {
 		      case __SI_FAULT >> 16:
+			err |= __put_user(from->si_flags, &to->si_flags);
 			err |= __put_user(from->si_isr, &to->si_isr);
 		      case __SI_POLL >> 16:
 			err |= __put_user(from->si_addr, &to->si_addr);
@@ -172,7 +173,12 @@
 		      case __SI_PROF >> 16:
 			err |= __put_user(from->si_uid, &to->si_uid);
 			err |= __put_user(from->si_pid, &to->si_pid);
-			err |= __put_user(from->si_pfm_ovfl, &to->si_pfm_ovfl);
+			if (from->si_code == PROF_OVFL) {
+				err |= __put_user(from->si_pfm_ovfl[0], &to->si_pfm_ovfl[0]);
+				err |= __put_user(from->si_pfm_ovfl[1], &to->si_pfm_ovfl[1]);
+				err |= __put_user(from->si_pfm_ovfl[2], &to->si_pfm_ovfl[2]);
+				err |= __put_user(from->si_pfm_ovfl[3], &to->si_pfm_ovfl[3]);
+			}
 			break;
 		      default:
 			err |= __put_user(from->si_uid, &to->si_uid);
@@ -578,10 +584,7 @@
 				/* FALLTHRU */
 
 			      default:
-				sigaddset(&current->pending.signal, signr);
-				recalc_sigpending(current);
-				current->flags |= PF_SIGNALED;
-				do_exit(exit_code);
+				sig_exit(signr, exit_code, &info);
 				/* NOTREACHED */
 			}
 		}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/smpboot.c linux/arch/ia64/kernel/smpboot.c
--- linux.orig/arch/ia64/kernel/smpboot.c	2001-11-21 18:31:09.000000000 +0000
+++ linux/arch/ia64/kernel/smpboot.c	2002-08-01 06:42:36.000000000 +0000
@@ -416,9 +416,9 @@
 	if (!idle)
 		panic("No idle process for CPU %d", cpu);
 
-	idle->processor = cpu;
+	task_set_cpu(idle, cpu);	/* we schedule the first task manually */
+
 	ia64_cpu_to_sapicid[cpu] = sapicid;
-	idle->cpus_runnable = 1 << cpu; /* we schedule the first task manually */
 
 	del_from_runqueue(idle);
 	unhash_process(idle);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/traps.c linux/arch/ia64/kernel/traps.c
--- linux.orig/arch/ia64/kernel/traps.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/traps.c	2002-08-01 06:42:48.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * Architecture-specific trap handling.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 05/12/00 grao <goutham.rao@intel.com> : added isr in siginfo for SIGFPE
@@ -133,6 +133,8 @@
 	/* SIGILL, SIGFPE, SIGSEGV, and SIGBUS want these field initialized: */
 	siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
 	siginfo.si_imm = break_num;
+	siginfo.si_flags = 0;		/* clear __ISR_VALID */
+	siginfo.si_isr = 0;
 
 	switch (break_num) {
 	      case 0: /* unknown error */
@@ -352,6 +354,8 @@
 				siginfo.si_code = FPE_FLTDIV;
 			}
 			siginfo.si_isr = isr;
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_imm = 0;
 			force_sig_info(SIGFPE, &siginfo, current);
 		}
 	} else {
@@ -372,6 +376,8 @@
 				siginfo.si_code = FPE_FLTRES;
 			}
 			siginfo.si_isr = isr;
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_imm = 0;
 			force_sig_info(SIGFPE, &siginfo, current);
 		}
 	}
@@ -490,6 +496,8 @@
 			siginfo.si_errno = 0;
 			siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
 			siginfo.si_imm = vector;
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_isr = isr;
 			force_sig_info(SIGILL, &siginfo, current);
 			return;
 		}
@@ -517,6 +525,10 @@
 		}
 		siginfo.si_signo = SIGTRAP;
 		siginfo.si_errno = 0;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_addr = 0;
+		siginfo.si_imm = 0;
 		force_sig_info(SIGTRAP, &siginfo, current);
 		return;
 
@@ -528,6 +540,9 @@
 			siginfo.si_errno = 0;
 			siginfo.si_code = FPE_FLTINV;
 			siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_isr = isr;
+			siginfo.si_imm = 0;
 			force_sig_info(SIGFPE, &siginfo, current);
 		}
 		return;
@@ -537,6 +552,9 @@
 			siginfo.si_signo = SIGILL;
 			siginfo.si_code = ILL_BADIADDR;
 			siginfo.si_errno = 0;
+			siginfo.si_flags = 0;
+			siginfo.si_isr = 0;
+			siginfo.si_imm = 0;
 			siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
 			force_sig_info(SIGILL, &siginfo, current);
 			return;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/unaligned.c linux/arch/ia64/kernel/unaligned.c
--- linux.orig/arch/ia64/kernel/unaligned.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/unaligned.c	2002-08-01 06:42:47.000000000 +0000
@@ -1,9 +1,9 @@
 /*
  * Architecture-specific unaligned trap handling.
  *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999-2000 Stephane Eranian <eranian@hpl.hp.com>
- * Copyright (C) 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 2001/10/11	Fix unaligned access to rotating registers in s/w pipelined loops.
  * 2001/08/13	Correct size of extended floats (float_fsz) from 16 to 10 bytes.
@@ -23,7 +23,7 @@
 #undef DEBUG_UNALIGNED_TRAP
 
 #ifdef DEBUG_UNALIGNED_TRAP
-# define DPRINT(a...)	do { printk("%s.%u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
+# define DPRINT(a...)	do { printk("%s %u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
 # define DDUMP(str,vp,len)	dump(str, vp, len)
 
 static void
@@ -650,7 +650,7 @@
 	 * just in case.
 	 */
 	if (ld.x6_op == 1 || ld.x6_op == 3) {
-		printk(KERN_ERR __FUNCTION__": register update on speculative load, error\n");
+		printk("%s %s: register update on speculative load, error\n", KERN_ERR, __FUNCTION__);
 		die_if_kernel("unaligned reference on specualtive load with register update\n",
 			      regs, 30);
 	}
@@ -1080,8 +1080,8 @@
 		 * For this reason we keep this sanity check
 		 */
 		if (ld.x6_op == 1 || ld.x6_op == 3)
-			printk(KERN_ERR __FUNCTION__": register update on speculative load pair, "
-			       "error\n");
+			printk("%s %s: register update on speculative load pair, "
+			       "error\n",KERN_ERR, __FUNCTION__);
 
 		setreg(ld.r3, ifa, 0, regs);
 	}
@@ -1488,6 +1488,9 @@
 	si.si_errno = 0;
 	si.si_code = BUS_ADRALN;
 	si.si_addr = (void *) ifa;
+	si.si_flags = 0;
+	si.si_isr = 0;
+	si.si_imm = 0;
 	force_sig_info(SIGBUS, &si, current);
 	goto done;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/unwind.c linux/arch/ia64/kernel/unwind.c
--- linux.orig/arch/ia64/kernel/unwind.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/kernel/unwind.c	2002-08-01 06:42:45.000000000 +0000
@@ -1,6 +1,6 @@
 /*
- * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 /*
  * This file implements call frame unwind support for the Linux
@@ -72,6 +72,8 @@
 
 #define alloc_reg_state()	kmalloc(sizeof(struct unw_state_record), GFP_ATOMIC)
 #define free_reg_state(usr)	kfree(usr)
+#define alloc_labeled_state()	kmalloc(sizeof(struct unw_labeled_state), GFP_ATOMIC)
+#define free_labeled_state(usr)	kfree(usr)
 
 typedef unsigned long unw_word;
 typedef unsigned char unw_hash_index_t;
@@ -521,7 +523,7 @@
 }
 
 
-/* Unwind decoder routines */
+/* Routines to manipulate the state stack.  */
 
 static inline void
 push (struct unw_state_record *sr)
@@ -534,24 +536,60 @@
 		return;
 	}
 	memcpy(rs, &sr->curr, sizeof(*rs));
-	rs->next = sr->stack;
-	sr->stack = rs;
+	sr->curr.next = rs;
 }
 
 static void
 pop (struct unw_state_record *sr)
 {
-	struct unw_reg_state *rs;
+	struct unw_reg_state *rs = sr->curr.next;
 
-	if (!sr->stack) {
-		printk ("unwind: stack underflow!\n");
+	if (!rs) {
+		printk("unwind: stack underflow!\n");
 		return;
 	}
-	rs = sr->stack;
-	sr->stack = rs->next;
+	memcpy(&sr->curr, rs, sizeof(*rs));
 	free_reg_state(rs);
 }
 
+/* Make a copy of the state stack.  Non-recursive to avoid stack overflows.  */
+static struct unw_reg_state *
+dup_state_stack (struct unw_reg_state *rs)
+{
+	struct unw_reg_state *copy, *prev = NULL, *first = NULL;
+
+	while (rs) {
+		copy = alloc_reg_state();
+		if (!copy) {
+			printk ("unwind.dup_state_stack: out of memory\n");
+			return NULL;
+		}
+		memcpy(copy, rs, sizeof(*copy));
+		if (first)
+			prev->next = copy;
+		else
+			first = copy;
+		rs = rs->next;
+		prev = copy;
+	}
+	return first;
+}
+
+/* Free all stacked register states (but not RS itself).  */
+static void
+free_state_stack (struct unw_reg_state *rs)
+{
+	struct unw_reg_state *p, *next;
+
+	for (p = rs->next; p != NULL; p = next) {
+		next = p->next;
+		free_reg_state(p);
+	}
+	rs->next = NULL;
+}
+
+/* Unwind decoder routines */
+
 static enum unw_register_index __attribute__((const))
 decode_abreg (unsigned char abreg, int memory)
 {
@@ -689,7 +727,7 @@
 	sr->first_region = 0;
 
 	/* check if we're done: */
-	if (body && sr->when_target < sr->region_start + sr->region_len) {
+	if (sr->when_target < sr->region_start + sr->region_len) {
 		sr->done = 1;
 		return;
 	}
@@ -902,31 +940,36 @@
 static inline void
 desc_copy_state (unw_word label, struct unw_state_record *sr)
 {
-	struct unw_reg_state *rs;
+	struct unw_labeled_state *ls;
 
-	for (rs = sr->reg_state_list; rs; rs = rs->next) {
-		if (rs->label == label) {
-			memcpy (&sr->curr, rs, sizeof(sr->curr));
+	for (ls = sr->labeled_states; ls; ls = ls->next) {
+		if (ls->label == label) {
+			free_state_stack(&sr->curr);
+			memcpy(&sr->curr, &ls->saved_state, sizeof(sr->curr));
+			sr->curr.next = dup_state_stack(ls->saved_state.next);
 			return;
 		}
 	}
-	printk("unwind: failed to find state labelled 0x%lx\n", label);
+	printk("unwind: failed to find state labeled 0x%lx\n", label);
 }
 
 static inline void
 desc_label_state (unw_word label, struct unw_state_record *sr)
 {
-	struct unw_reg_state *rs;
+	struct unw_labeled_state *ls;
 
-	rs = alloc_reg_state();
-	if (!rs) {
-		printk("unwind: cannot stack!\n");
+	ls = alloc_labeled_state();
+	if (!ls) {
+		printk("unwind.desc_label_state(): out of memory\n");
 		return;
 	}
-	memcpy(rs, &sr->curr, sizeof(*rs));
-	rs->label = label;
-	rs->next = sr->reg_state_list;
-	sr->reg_state_list = rs;
+	ls->label = label;
+	memcpy(&ls->saved_state, &sr->curr, sizeof(ls->saved_state));
+	ls->saved_state.next = dup_state_stack(sr->curr.next);
+
+	/* insert into list of labeled states: */
+	ls->next = sr->labeled_states;
+	sr->labeled_states = ls;
 }
 
 /*
@@ -1378,6 +1421,8 @@
 		else
 			break;
 	}
+	if (rel_ip < e->start_offset || rel_ip >= e->end_offset)
+		return NULL;
 	return e;
 }
 
@@ -1388,9 +1433,9 @@
 static inline struct unw_script *
 build_script (struct unw_frame_info *info)
 {
-	struct unw_reg_state *rs, *next;
 	const struct unw_table_entry *e = 0;
 	struct unw_script *script = 0;
+	struct unw_labeled_state *ls, *next;
 	unsigned long ip = info->ip;
 	struct unw_state_record sr;
 	struct unw_table *table;
@@ -1535,15 +1580,15 @@
 	for (i = UNW_REG_BSP; i < UNW_NUM_REGS; ++i)
 		compile_reg(&sr, i, script);
 
-	/* free labelled register states & stack: */
+	/* free labeled register states & stack: */
 
 	STAT(parse_start = ia64_get_itc());
-	for (rs = sr.reg_state_list; rs; rs = next) {
-		next = rs->next;
-		free_reg_state(rs);
+	for (ls = sr.labeled_states; ls; ls = next) {
+		next = ls->next;
+		free_state_stack(&ls->saved_state);
+		free_labeled_state(ls);
 	}
-	while (sr.stack)
-		pop(&sr);
+	free_state_stack(&sr.curr);
 	STAT(unw.stat.script.parse_time += ia64_get_itc() - parse_start);
 
 	script_finalize(script, &sr);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/kernel/unwind_i.h linux/arch/ia64/kernel/unwind_i.h
--- linux.orig/arch/ia64/kernel/unwind_i.h	2001-07-31 17:30:08.000000000 +0000
+++ linux/arch/ia64/kernel/unwind_i.h	2002-08-01 06:42:42.000000000 +0000
@@ -1,6 +1,6 @@
 /*
- * Copyright (C) 2000 Hewlett-Packard Co
- * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2000, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Kernel unwind support.
  */
@@ -85,6 +85,17 @@
 	int when;			/* when the register gets saved */
 };
 
+struct unw_reg_state {
+	struct unw_reg_state *next;		/* next (outer) element on state stack */
+	struct unw_reg_info reg[UNW_NUM_REGS];	/* register save locations */
+};
+
+struct unw_labeled_state {
+	struct unw_labeled_state *next;		/* next labeled state (or NULL) */
+	unsigned long label;			/* label for this state */
+	struct unw_reg_state saved_state;
+};
+
 struct unw_state_record {
 	unsigned int first_region : 1;	/* is this the first region? */
 	unsigned int done : 1;		/* are we done scanning descriptors? */
@@ -105,11 +116,8 @@
 	u8 gr_save_loc;			/* next general register to use for saving a register */
 	u8 return_link_reg;		/* branch register in which the return link is passed */
 
-	struct unw_reg_state {
-		struct unw_reg_state *next;
-		unsigned long label;		/* label of this state record */
-		struct unw_reg_info reg[UNW_NUM_REGS];
-	} curr, *stack, *reg_state_list;
+	struct unw_labeled_state *labeled_states;	/* list of all labeled states */
+	struct unw_reg_state curr;	/* current state */
 };
 
 enum unw_nat_type {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/lib/swiotlb.c linux/arch/ia64/lib/swiotlb.c
--- linux.orig/arch/ia64/lib/swiotlb.c	2001-11-13 17:01:16.000000000 +0000
+++ linux/arch/ia64/lib/swiotlb.c	2002-08-01 06:42:46.000000000 +0000
@@ -27,11 +27,21 @@
 #define ALIGN(val, align) ((unsigned long)	\
 	(((unsigned long) (val) + ((align) - 1)) & ~((align) - 1)))
 
+#define OFFSET(val,align) ((unsigned long)	\
+	                   ( (val) & ( (align) - 1)))
+
 #define SG_ENT_VIRT_ADDRESS(sg)	((sg)->address ? (sg)->address			\
 				 : page_address((sg)->page) + (sg)->offset)
 #define SG_ENT_PHYS_ADDRESS(SG)	virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
 
 /*
+ * Maximum allowable number of contiguous slabs to map,
+ * must be a power of 2.  What is the appropriate value ?
+ * The complexity of {map,unmap}_single is linearly dependent on this value.
+ */
+#define IO_TLB_SEGSIZE	128
+
+/*
  * log of the size of each IO TLB slab.  The number of slabs is command line controllable.
  */
 #define IO_TLB_SHIFT 11
@@ -69,10 +79,15 @@
 setup_io_tlb_npages (char *str)
 {
 	io_tlb_nslabs = simple_strtoul(str, NULL, 0) << (PAGE_SHIFT - IO_TLB_SHIFT);
+
+	/* avoid tail segment of size < IO_TLB_SEGSIZE */
+	io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
+
 	return 1;
 }
 __setup("swiotlb=", setup_io_tlb_npages);
 
+
 /*
  * Statically reserve bounce buffer space and initialize bounce buffer data structures for
  * the software IO TLB used to implement the PCI DMA API.
@@ -92,12 +107,12 @@
 
 	/*
 	 * Allocate and initialize the free list array.  This array is used
-	 * to find contiguous free memory regions of size 2^IO_TLB_SHIFT between
-	 * io_tlb_start and io_tlb_end.
+	 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
+	 * between io_tlb_start and io_tlb_end.
 	 */
 	io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int));
 	for (i = 0; i < io_tlb_nslabs; i++)
-		io_tlb_list[i] = io_tlb_nslabs - i;
+ 		io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
 	io_tlb_index = 0;
 	io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(char *));
 
@@ -124,7 +139,7 @@
 	if (size > (1 << PAGE_SHIFT))
 		stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
 	else
-		stride = nslots;
+		stride = 1;
 
 	if (!nslots)
 		BUG();
@@ -151,7 +166,8 @@
 
 				for (i = index; i < index + nslots; i++)
 					io_tlb_list[i] = 0;
-				for (i = index - 1; (i >= 0) && io_tlb_list[i]; i--)
+				for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1)
+				       && io_tlb_list[i]; i--)
 					io_tlb_list[i] = ++count;
 				dma_addr = io_tlb_start + (index << IO_TLB_SHIFT);
 
@@ -217,7 +233,8 @@
 	 */
 	spin_lock_irqsave(&io_tlb_lock, flags);
 	{
-		int count = ((index + nslots) < io_tlb_nslabs ? io_tlb_list[index + nslots] : 0);
+		int count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ?
+			     io_tlb_list[index + nslots] : 0);
 		/*
 		 * Step 1: return the slots to the free list, merging the slots with
 		 * superceeding slots
@@ -228,7 +245,8 @@
 		 * Step 2: merge the returned slots with the preceeding slots, if
 		 * available (non zero)
 		 */
-		for (i = index - 1; (i >= 0) && io_tlb_list[i]; i--)
+		for (i = index - 1;  (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) &&
+		       io_tlb_list[i]; i--)
 			io_tlb_list[i] = ++count;
 	}
 	spin_unlock_irqrestore(&io_tlb_lock, flags);
@@ -405,11 +423,13 @@
 	for (i = 0; i < nelems; i++, sg++) {
 		sg->orig_address = SG_ENT_VIRT_ADDRESS(sg);
 		if ((SG_ENT_PHYS_ADDRESS(sg) & ~hwdev->dma_mask) != 0) {
-			addr = map_single(hwdev, sg->address, sg->length, direction);
+			addr = map_single(hwdev, sg->orig_address, sg->length, direction);
 			if (sg->address)
 				sg->address = addr;
-			else
+			else {
 				sg->page = virt_to_page(addr);
+				sg->offset = (u64) addr & ~PAGE_MASK;
+			}
 		}
 	}
 	return nelems;
@@ -432,10 +452,12 @@
 			unmap_single(hwdev, SG_ENT_VIRT_ADDRESS(sg), sg->length, direction);
 			if (sg->address)
 				sg->address = sg->orig_address;
-			else
+			else {
 				sg->page = virt_to_page(sg->orig_address);
+				sg->offset = (u64) sg->orig_address & ~PAGE_MASK;
+			}
 		} else if (direction == PCI_DMA_FROMDEVICE)
-			mark_clean(sg->address, sg->length);
+			mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->length);
 }
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/mm/extable.c linux/arch/ia64/mm/extable.c
--- linux.orig/arch/ia64/mm/extable.c	2001-07-31 17:30:08.000000000 +0000
+++ linux/arch/ia64/mm/extable.c	2002-08-01 06:42:37.000000000 +0000
@@ -1,8 +1,8 @@
 /*
  * Kernel exception handling table support.  Derived from arch/alpha/mm/extable.c.
  *
- * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
- * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998, 1999, 2001-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/config.h>
@@ -55,10 +55,12 @@
 	struct module *mp;
 
 	/* The kernel is the last "module" -- no need to treat it special. */
-	for (mp = module_list; mp ; mp = mp->next) {
+	for (mp = module_list; mp; mp = mp->next) {
 		if (!mp->ex_table_start)
 			continue;
 		archdata = (struct archdata *) mp->archdata_start;
+		if (!archdata)
+			continue;
 		entry = search_one_table(mp->ex_table_start, mp->ex_table_end - 1,
 					 addr, (unsigned long) archdata->gp);
 		if (entry) {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/mm/fault.c linux/arch/ia64/mm/fault.c
--- linux.orig/arch/ia64/mm/fault.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/mm/fault.c	2002-08-01 06:42:48.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  * MMU fault handling support.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #include <linux/sched.h>
@@ -96,7 +96,7 @@
 	 * sure we exit gracefully rather than endlessly redo the
 	 * fault.
 	 */
-	switch (handle_mm_fault(mm, vma, address, mask)) {
+	switch (handle_mm_fault(mm, vma, address, (mask & VM_WRITE) != 0)) {
 	      case 1:
 		++current->min_flt;
 		break;
@@ -151,6 +151,8 @@
 		si.si_errno = 0;
 		si.si_code = code;
 		si.si_addr = (void *) address;
+		si.si_isr = isr;
+		si.si_flags = __ISR_VALID;
 		force_sig_info(signal, &si, current);
 		return;
 	}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/mm/init.c linux/arch/ia64/mm/init.c
--- linux.orig/arch/ia64/mm/init.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/mm/init.c	2002-08-01 06:42:42.000000000 +0000
@@ -99,7 +99,7 @@
 		free_page(addr);
 		++totalram_pages;
 	}
-	printk ("Freeing unused kernel memory: %ldkB freed\n",
+	printk (KERN_INFO "Freeing unused kernel memory: %ldkB freed\n",
 		(&__init_end - &__init_begin) >> 10);
 }
 
@@ -141,7 +141,7 @@
 	end = end & PAGE_MASK;
 
 	if (start < end)
-		printk ("Freeing initrd memory: %ldkB freed\n", (end - start) >> 10);
+		printk (KERN_INFO "Freeing initrd memory: %ldkB freed\n", (end - start) >> 10);
 
 	for (; start < end; start += PAGE_SIZE) {
 		if (!VALID_PAGE(virt_to_page(start)))
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/Makefile linux/arch/ia64/sn/Makefile
--- linux.orig/arch/ia64/sn/Makefile	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,19 +0,0 @@
-#
-# ia64/sn/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
-all: sn.a
-
-O_TARGET        = sn.a
-obj-y           = sn1/sn1.a
-
-clean::
-
-include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp linux/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,777 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_PIIX_TUNING is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+CONFIG_EEPRO100=y
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp linux/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,772 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_PIIX_TUNING is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+CONFIG_EEPRO100=y
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-dig-mp linux/arch/ia64/sn/configs/sn1/defconfig-dig-mp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-dig-mp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-dig-mp	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-dig-sp linux/arch/ia64/sn/configs/sn1/defconfig-dig-sp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-dig-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-dig-sp	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-generic-mp linux/arch/ia64/sn/configs/sn1/defconfig-generic-mp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-generic-mp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-generic-mp	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+CONFIG_IA64_GENERIC=y
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Simulated drivers
+#
+# CONFIG_SIMETH is not set
+# CONFIG_SIM_SERIAL is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-generic-sp linux/arch/ia64/sn/configs/sn1/defconfig-generic-sp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-generic-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-generic-sp	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+CONFIG_IA64_GENERIC=y
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Simulated drivers
+#
+# CONFIG_SIMETH is not set
+# CONFIG_SIM_SERIAL is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-hp-sp linux/arch/ia64/sn/configs/sn1/defconfig-hp-sp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-hp-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-hp-sp	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,334 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+CONFIG_IA64_HP_SIM=y
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_PRINTER is not set
+# CONFIG_PPDEV is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Simulated drivers
+#
+CONFIG_SIMETH=y
+CONFIG_SIM_SERIAL=y
+CONFIG_SCSI_SIM=y
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-prom-medusa linux/arch/ia64/sn/configs/sn1/defconfig-prom-medusa
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-prom-medusa	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-prom-medusa	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,529 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-mp linux/arch/ia64/sn/configs/sn1/defconfig-sn1-mp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-mp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-sn1-mp	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules linux/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,738 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0 linux/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-sp linux/arch/ia64/sn/configs/sn1/defconfig-sn1-sp
--- linux.orig/arch/ia64/sn/configs/sn1/defconfig-sn1-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn1/defconfig-sn1-sp	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-dig-numa linux/arch/ia64/sn/configs/sn2/defconfig-dig-numa
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-dig-numa	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-dig-numa	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_NUMA=y
+CONFIG_DISCONTIGMEM=y
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp linux/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp linux/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-mp linux/arch/ia64/sn/configs/sn2/defconfig-sn2-mp
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-mp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-sn2-mp	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,730 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules linux/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,732 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+# CONFIG_SERIAL_SGI_L1_PROTOCOL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa linux/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,537 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-sp linux/arch/ia64/sn/configs/sn2/defconfig-sn2-sp
--- linux.orig/arch/ia64/sn/configs/sn2/defconfig-sn2-sp	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/configs/sn2/defconfig-sn2-sp	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,730 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/Makefile linux/arch/ia64/sn/fakeprom/Makefile
--- linux.orig/arch/ia64/sn/fakeprom/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/Makefile	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,30 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+#  Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+#
+
+TOPDIR=../../../..
+HPATH           = $(TOPDIR)/include
+
+LIB     = ../../lib/lib.a
+
+OBJ=fpromasm.o main.o  fw-emu.o fpmem.o klgraph_init.o
+obj-y=fprom
+
+fprom: $(OBJ)
+	$(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB)
+
+.S.o:
+	$(CC)  -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+.c.o:
+	$(CC)  $(CFLAGS) $(CFLAGS_KERNEL) -c -o $*.o $<
+
+clean:
+	rm -f *.o fprom
+
+
+include $(TOPDIR)/Rules.make
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/README linux/arch/ia64/sn/fakeprom/README
--- linux.orig/arch/ia64/sn/fakeprom/README	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/README	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,85 @@
+This directory contains the files required to build
+the fake PROM image that is currently being used to
+boot IA64 kernels running under the SGI Medusa kernel.
+
+The FPROM currently provides the following functions:
+
+	- PAL emulation for all PAL calls we've made so far.
+	- SAL emulation for all SAL calls we've made so far.
+	- EFI emulation for all EFI calls we've made so far.
+	- builds the "ia64_bootparam" structure that is
+	  passed to the kernel from SAL. This structure 
+	  shows the cpu & memory configurations.
+	- supports medusa boottime options for changing
+	  the number of cpus present
+	- supports medusa boottime options for changing
+	  the memory configuration.
+
+
+
+At some point, this fake PROM will be replaced by the
+real PROM.
+
+
+
+
+To build a fake PROM, cd to this directory & type:
+
+	make
+
+This will (or should) build a fake PROM named "fprom".
+
+
+
+
+Use this fprom image when booting the Medusa simulator. The
+control file used to boot Medusa should include the 
+following lines:
+
+	load fprom
+	load vmlinux
+	sr pc 0x100000
+	sr g 9 <address of kernel _start function> #(currently 0xe000000000520000)
+
+NOTE: There is a script "runsim" in this directory that can be used to
+simplify setting up an environment for running under Medusa.
+
+
+
+
+The following parameters may be passed to the fake PROM to
+control the PAL/SAL/EFI parameters passed to the kernel:
+
+	GR[8] = # of cpus
+	GR[9] = address of primary entry point into the kernel
+	GR[20] = memory configuration for node 0
+	GR[21] = memory configuration for node 1
+	GR[22] = memory configuration for node 2
+	GR[23] = memory configuration for node 3
+
+
+Registers GR[20] - GR[23] contain information to specify the
+amount of memory present on nodes 0-3.
+
+  - if nothing is specified (all registers are 0), the configuration
+    defaults to 8 MB on node 0.
+
+  - a mem config entry for node N is passed in GR[20+N]
+
+  - a mem config entry consists of 8 hex digits. Each digit gives the
+    amount of physical memory available on the node starting at
+    1GB*<dn>, where dn is the digit number. The amount of memory
+    is 8MB*2**<d>. (If <d> = 0, the memory size is 0).
+
+    SN1 doesnt support dimms this small but small memory systems 
+    boot faster on Medusa.
+
+
+
+An example helps a lot. The following specifies that node 0 has
+physical memory 0 to 8MB and 1GB to 1GB+32MB, and that node 1 has
+64MB starting at address 0 of the node which is 8GB.
+
+      gr[20] = 0x21           # 0 to 8MB, 1GB to 1GB+32MB
+      gr[21] = 0x4            # 8GB to 8GB+64MB
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/fpmem.c linux/arch/ia64/sn/fakeprom/fpmem.c
--- linux.orig/arch/ia64/sn/fakeprom/fpmem.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/fpmem.c	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,266 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+/*
+ * FPROM EFI memory descriptor build routines
+ *
+ * 	- Routines to build the EFI memory descriptor map
+ * 	- Should also be usable by the SGI SN1 prom to convert
+ * 	  klconfig to efi_memmap
+ */
+
+#include <linux/config.h>
+#include <asm/efi.h>
+#include "fpmem.h"
+
+/*
+ * args points to a layout in memory like this
+ *
+ *		32 bit		32 bit
+ *
+ * 		numnodes	numcpus
+ *
+ *		16 bit   16 bit		   32 bit
+ *		nasid0	cpuconf		membankdesc0
+ *		nasid1	cpuconf		membankdesc1
+ *			   .
+ *			   .
+ *			   .
+ *			   .
+ *			   .
+ */
+
+sn_memmap_t	*sn_memmap ;
+sn_config_t	*sn_config ;
+
+/*
+ * There is a hole in the node 0 address space. Dont put it
+ * in the memory map
+ */
+#define NODE0_HOLE_SIZE         (20*MB)
+#define NODE0_HOLE_END          (4UL*GB)
+
+#define	MB			(1024*1024)
+#define GB			(1024*MB)
+#define KERNEL_SIZE		(4*MB)
+#define PROMRESERVED_SIZE	(1*MB)
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define PHYS_ADDRESS(_n, _x)		(((long)_n<<33L) | (long)_x)
+#define MD_BANK_SHFT 30
+#else
+#define PHYS_ADDRESS(_n, _x)		(((long)_n<<38L) | (long)_x | 0x3000000000UL)
+#define MD_BANK_SHFT 34
+#endif
+
+/*
+ * For SN, this may not take an arg and gets the numnodes from 
+ * the prom variable or by traversing klcfg or promcfg
+ */
+int
+GetNumNodes(void)
+{
+	return sn_config->nodes;
+}
+
+int
+GetNumCpus(void)
+{
+	return sn_config->cpus;
+}
+
+/* For SN1, get the index th nasid */
+
+int
+GetNasid(int index)
+{
+	return sn_memmap[index].nasid ;
+}
+
+node_memmap_t
+GetMemBankInfo(int index)
+{
+	return sn_memmap[index].node_memmap ;
+}
+
+int
+IsCpuPresent(int cnode, int cpu)
+{
+	return  sn_memmap[cnode].cpuconfig & (1<<cpu);
+}
+
+
+/*
+ * Made this into an explicit case statement so that
+ * we can assign specific properties to banks like bank0
+ * actually disabled etc.
+ */
+
+#ifdef CONFIG_IA64_SGI_SN1
+int
+IsBankPresent(int index, node_memmap_t nmemmap)
+{
+	switch (index) {
+		case 0:return nmemmap.b0;
+		case 1:return nmemmap.b1;
+		case 2:return nmemmap.b2;
+		case 3:return nmemmap.b3;
+		case 4:return nmemmap.b4;
+		case 5:return nmemmap.b5;
+		case 6:return nmemmap.b6;
+		case 7:return nmemmap.b7;
+		default:return -1 ;
+	}
+}
+
+int
+GetBankSize(int index, node_memmap_t nmemmap)
+{
+        switch (index) {
+                case 0:
+                case 1:return nmemmap.b01size;
+                case 2:
+                case 3:return nmemmap.b23size;
+                case 4:
+                case 5:return nmemmap.b45size;
+                case 6:
+                case 7:return nmemmap.b67size;
+                default:return -1 ;
+        }
+}
+
+#else
+int
+IsBankPresent(int index, node_memmap_t nmemmap)
+{
+	switch (index) {
+		case 0:return BankPresent(nmemmap.b0size);
+		case 1:return BankPresent(nmemmap.b1size);
+		case 2:return BankPresent(nmemmap.b2size);
+		case 3:return BankPresent(nmemmap.b3size);
+		default:return -1 ;
+	}
+}
+
+int
+GetBankSize(int index, node_memmap_t nmemmap)
+{
+	/*
+	 * Add 2 because there are 4 dimms per bank.
+	 */
+        switch (index) {
+                case 0:return 2 + ((long)nmemmap.b0size + nmemmap.b0dou);
+                case 1:return 2 + ((long)nmemmap.b1size + nmemmap.b1dou);
+                case 2:return 2 + ((long)nmemmap.b2size + nmemmap.b2dou);
+                case 3:return 2 + ((long)nmemmap.b3size + nmemmap.b3dou);
+                default:return -1 ;
+        }
+}
+
+#endif
+
+void
+build_mem_desc(efi_memory_desc_t *md, int type, long paddr, long numbytes)
+{
+        md->type = type;
+        md->phys_addr = paddr;
+        md->virt_addr = 0;
+        md->num_pages = numbytes >> 12;
+        md->attribute = EFI_MEMORY_WB;
+}
+
+int
+build_efi_memmap(void *md, int mdsize)
+{
+	int		numnodes = GetNumNodes() ;
+	int		cnode,bank ;
+	int		nasid ;
+	node_memmap_t	membank_info ;
+	int		bsize;
+	int		count = 0 ;
+	long		paddr, hole, numbytes;
+
+
+	for (cnode=0;cnode<numnodes;cnode++) {
+		nasid = GetNasid(cnode) ;
+		membank_info = GetMemBankInfo(cnode) ;
+		for (bank=0;bank<PLAT_CLUMPS_PER_NODE;bank++) {
+			if (IsBankPresent(bank, membank_info)) {
+				bsize = GetBankSize(bank, membank_info) ;
+                                paddr = PHYS_ADDRESS(nasid, (long)bank<<MD_BANK_SHFT);
+                                numbytes = BankSizeBytes(bsize);
+#ifdef CONFIG_IA64_SGI_SN2
+				/* 
+				 * Ignore directory.
+				 * Shorten memory chunk by 1 page - makes a better
+				 * testcase & is more like the real PROM.
+				 */
+				numbytes = numbytes * 31 / 32;
+#endif
+				numbytes -= 1000;
+
+                                /*
+                                 * Check for the node 0 hole. Since banks cant
+                                 * span the hole, we only need to check if the end of
+                                 * the range is the end of the hole.
+                                 */
+                                if (paddr+numbytes == NODE0_HOLE_END)
+                                        numbytes -= NODE0_HOLE_SIZE;
+                                /*
+                                 * UGLY hack - we must skip overr the kernel and
+                                 * PROM runtime services but we dont exactly where it is.
+                                 * So lets just reserve:
+				 *	node 0
+				 *		0-1MB for PAL
+				 *		1-4MB for SAL
+				 *	node 1-N
+				 *		0-1 for SAL
+                                 */
+                                if (bank == 0) {
+					if (cnode == 0) {
+						hole = 1*1024*1024;
+						build_mem_desc(md, EFI_PAL_CODE, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+						hole = 3*1024*1024;
+						build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+					} else {
+						hole = PROMRESERVED_SIZE;
+                                        	build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+					}
+                                }
+                                build_mem_desc(md, EFI_CONVENTIONAL_MEMORY, paddr, numbytes);
+
+			        md += mdsize ;
+			        count++ ;
+			}
+		}
+	}
+	return count ;
+}
+
+void
+build_init(unsigned long args)
+{
+	sn_config = (sn_config_t *) (args);	
+	sn_memmap = (sn_memmap_t *)(args + 8) ; /* SN equiv for this is */
+						/* init to klconfig start */
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/fpmem.h linux/arch/ia64/sn/fakeprom/fpmem.h
--- linux.orig/arch/ia64/sn/fakeprom/fpmem.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/fpmem.h	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,99 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Structure of the mem config of the node as a SN1 MI reg
+ * Medusa supports this reg config.
+ *
+ * BankSize nibble to bank size mapping
+ *
+ *      1 - 64 MB
+ *      2 - 128 MB
+ *      3 - 256 MB
+ *      4 - 512 MB
+ *      5 - 1024 MB (1GB)
+ */
+
+#define MBSHIFT				20
+
+#ifdef CONFIG_IA64_SGI_SN1
+typedef struct node_memmap_s
+{
+        unsigned int    b0      :1,     /* 0 bank 0 present */
+                        b1      :1,     /* 1 bank 1 present */
+                        r01     :2,     /* 2-3 reserved */
+                        b01size :4,     /* 4-7 Size of bank 0 and 1 */
+                        b2      :1,     /* 8 bank 2 present */
+                        b3      :1,     /* 9 bank 3 present */
+                        r23     :2,     /* 10-11 reserved */
+                        b23size :4,     /* 12-15 Size of bank 2 and 3 */
+                        b4      :1,     /* 16 bank 4 present */
+                        b5      :1,     /* 17 bank 5 present */
+                        r45     :2,     /* 18-19 reserved */
+                        b45size :4,     /* 20-23 Size of bank 4 and 5 */
+                        b6      :1,     /* 24 bank 6 present */
+                        b7      :1,     /* 25 bank 7 present */
+                        r67     :2,     /* 26-27 reserved */
+                        b67size :4;     /* 28-31 Size of bank 6 and 7 */
+} node_memmap_t ;
+
+/* Support the medusa hack for 8M/16M/32M nodes */
+#define SN1_BANK_SIZE_SHIFT		(MBSHIFT+6)     /* 64 MB */
+#define BankSizeBytes(bsize)            ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
+                                         (1<<((bsize-9)+MBSHIFT)))
+#else
+typedef struct node_memmap_s
+{
+        unsigned int    b0size  :3,     /* 0-2   bank 0 size */
+                        b0dou   :1,     /* 3     bank 0 is 2-sided */
+                        ena0    :1,     /* 4     bank 0 enabled */
+                        r0      :3,     /* 5-7   reserved */
+        		b1size  :3,     /* 8-10  bank 1 size */
+                        b1dou   :1,     /* 11    bank 1 is 2-sided */
+                        ena1    :1,     /* 12    bank 1 enabled */
+                        r1      :3,     /* 13-15 reserved */
+        		b2size  :3,     /* 16-18 bank 2 size */
+                        b2dou   :1,     /* 19    bank 1 is 2-sided */
+                        ena2    :1,     /* 20    bank 2 enabled */
+                        r2      :3,     /* 21-23 reserved */
+        		b3size  :3,     /* 24-26 bank 3 size */
+                        b3dou   :1,     /* 27    bank 3 is 2-sided */
+                        ena3    :1,     /* 28    bank 3 enabled */
+                        r3      :3;     /* 29-31 reserved */
+} node_memmap_t ;
+
+#define SN2_BANK_SIZE_SHIFT		(MBSHIFT+6)     /* 64 MB */
+#define BankPresent(bsize)		(bsize<6)
+#define BankSizeBytes(bsize)            (BankPresent(bsize) ? 1UL<<((bsize)+SN2_BANK_SIZE_SHIFT) : 0)
+#endif
+
+typedef struct sn_memmap_s
+{
+	short		nasid ;
+	short		cpuconfig;
+	node_memmap_t 	node_memmap ;
+} sn_memmap_t ;
+
+typedef struct sn_config_s
+{
+	int		cpus;
+	int		nodes;
+	sn_memmap_t	memmap[1];		/* start of array */
+} sn_config_t;
+
+
+
+extern void build_init(unsigned long);
+extern int build_efi_memmap(void *, int);
+extern int GetNumNodes(void);
+extern int GetNumCpus(void);
+extern int IsCpuPresent(int, int);
+extern int GetNasid(int);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/fprom.lds linux/arch/ia64/sn/fakeprom/fprom.lds
--- linux.orig/arch/ia64/sn/fakeprom/fprom.lds	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/fprom.lds	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,96 @@
+
+OUTPUT_FORMAT("elf64-ia64-little")
+OUTPUT_ARCH(ia64)
+ENTRY(_start)
+SECTIONS
+{
+  v = 0x0000000000000000 ;	/* this symbol is here to make debugging with kdb easier... */
+
+  . = (0x000000000000000  + 0x100000) ;
+
+  _text = .;
+  .text : AT(ADDR(.text) - 0x0000000000000000 )
+    {
+	*(__ivt_section)
+	/* these are not really text pages, but the zero page needs to be in a fixed location: */
+	*(__special_page_section)
+	__start_gate_section = .;
+	*(__gate_section)
+	__stop_gate_section = .;
+	*(.text)
+    }
+
+  /* Global data */
+  _data = .;
+
+  .rodata : AT(ADDR(.rodata) - 0x0000000000000000 )
+	{ *(.rodata) *(.rodata.*) }
+  .opd : AT(ADDR(.opd) - 0x0000000000000000 )
+	{ *(.opd) }
+  .data : AT(ADDR(.data) - 0x0000000000000000 )
+	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
+
+  __gp = ALIGN (8) + 0x200000;
+
+  .got : AT(ADDR(.got) - 0x0000000000000000 )
+	{ *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata : AT(ADDR(.sdata) - 0x0000000000000000 )
+	{ *(.sdata) }
+  _edata  =  .;
+  _bss = .;
+  .sbss : AT(ADDR(.sbss) - 0x0000000000000000 )
+	{ *(.sbss) *(.scommon) }
+  .bss : AT(ADDR(.bss) - 0x0000000000000000 )
+	{ *(.bss) *(COMMON) }
+  . = ALIGN(64 / 8);
+  _end = .;
+
+  /* Sections to be discarded */
+  /DISCARD/ : {
+	*(.text.exit)
+	*(.data.exit)
+	}
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* These must appear regardless of  .  */
+  /* Discard them for now since Intel SoftSDV cannot handle them.
+  .comment 0 : { *(.comment) }
+  .note 0 : { *(.note) }
+  */
+  /DISCARD/ : { *(.comment) }
+  /DISCARD/ : { *(.note) }
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/fpromasm.S linux/arch/ia64/sn/fakeprom/fpromasm.S
--- linux.orig/arch/ia64/sn/fakeprom/fpromasm.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/fpromasm.S	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,403 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *   (Code copied from or=ther files)
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+
+#define __ASSEMBLY__ 1
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+
+/*
+ * This file contains additional set up code that is needed to get going on
+ * Medusa.  This code should disappear once real hw is available.
+ *
+ * On entry to this routine, the following register values are assumed:
+ *
+ *	gr[8]	- BSP cpu
+ *	pr[9]	- kernel entry address
+ *	pr[10]	- cpu number on the node
+ *
+ * NOTE:
+ *   This FPROM may be loaded/executed at an address different from the
+ *   address that it was linked at. The FPROM is linked to run on node 0
+ *   at address 0x100000. If the code in loaded into another node, it
+ *   must be loaded at offset 0x100000 of the node. In addition, the
+ *   FPROM does the following things:
+ *		- determine the base address of the node it is loaded on
+ *		- add the node base to _gp.
+ *		- add the node base to all addresses derived from "movl" 
+ *		  instructions. (I couldnt get GPREL addressing to work)
+ *		  (maybe newer versions of the tools will support this)
+ *		- scan the .got section and add the node base to all
+ *		  pointers in this section.
+ *		- add the node base to all physical addresses in the
+ *		  SAL/PAL/EFI table built by the C code. (This is done
+ *		  in the C code - not here)
+ *		- add the node base to the TLB entries for vmlinux
+ */
+
+#define KERNEL_BASE	0xe000000000000000
+#define BOOT_PARAM_ADDR 0x40000
+
+
+/* 
+ * ar.k0 gets set to IOPB_PA value, on 460gx chipset it should 
+ * be 0x00000ffffc000000, but on snia we use the (inverse swizzled)
+ * IOSPEC_BASE value
+ */
+#ifdef CONFIG_IA64_SGI_SN1
+#define IOPB_PA		0xc0000FFFFC000000
+#else
+#define IOPB_PA		0xc000000fcc000000
+#endif
+
+#define RR_RID		8
+
+
+
+// ====================================================================================	
+        .text
+        .align 16
+	.global _start
+	.proc _start
+_start:
+
+// Setup psr and rse for system init
+	mov		psr.l = r0;;
+	srlz.d;;
+	invala
+	mov		ar.rsc = r0;;
+	loadrs
+	;;
+
+// Isolate node number we are running on.
+	mov		r6 = ip;;
+#ifdef CONFIG_IA64_SGI_SN1
+	shr		r5 = r6,33;;			// r5 = node number
+	shl		r6 = r5,33			// r6 = base memory address of node
+#else
+	shr		r5 = r6,38			// r5 = node number
+	dep		r6 = 0,r6,0,36			// r6 = base memory address of node
+
+#endif
+
+
+// Set & relocate gp.
+	movl		r1= __gp;;			// Add base memory address
+	or 		r1 = r1,r6			// Relocate to boot node
+
+// Lets figure out who we are & put it in the LID register.
+#ifdef CONFIG_IA64_SGI_SN2
+// On SN2, we (currently) pass the cpu number in r10 at boot
+	and		r25=3,r10;;
+	movl		r16=0x8000008110000400		// Allow IPIs
+	mov		r17=-1;;
+	st8		[r16]=r17
+	movl		r16=0x8000008110060580;;	// SHUB_ID
+	ld8		r27=[r16];;
+	extr.u		r27=r27,32,11;;
+	shl 		r26=r25,28;;			// Align local cpu# to lid.eid
+	shl 		r27=r27,16;;			// Align NASID to lid.id
+	or  		r26=r26,r27;;			// build the LID
+#else
+// The BR_PI_SELF_CPU_NUM register gives us a value of 0-3.
+// This identifies the cpu on the node. 
+// Merge the cpu number with the NASID to generate the LID.
+	movl		r24=0x80000a0001000020;;	// BR_PI_SELF_CPU_NUM
+	ld8 		r25=[r24]			// Fetch PI_SELF
+	movl		r27=0x80000a0001600000;;	// Fetch REVID to get local NASID
+	ld8 		r27=[r27];;
+	extr.u		r27=r27,32,8;;
+	shl 		r26=r25,16;;			// Align local cpu# to lid.eid
+	shl 		r27=r27,24;;			// Align NASID to lid.id
+	or  		r26=r26,r27;;			// build the LID
+#endif
+	mov 		cr.lid=r26			// Now put in in the LID register
+
+	movl		r2=FPSR_DEFAULT;;
+	mov 		ar.fpsr=r2
+	movl		sp = bootstacke-16;;
+	or 		sp = sp,r6			// Relocate to boot node			
+
+// Save the NASID that we are loaded on.
+	movl		r2=base_nasid;;			// Save base_nasid for C code
+	or 		r2 = r2,r6;;			// Relocate to boot node
+  	st8 		[r2]=r5				// Uncond st8 - same on all cpus
+
+// Save the kernel entry address. It is passed in r9 on one of
+// the cpus.
+	movl		r2=bsp_entry_pc
+	cmp.ne		p6,p0=r9,r0;;
+	or 		r2 = r2,r6;;			// Relocate to boot node
+(p6)  	st8 		[r2]=r9				// Uncond st8 - same on all cpus
+
+
+// The following can ONLY be done by 1 cpu. Lets set a lock - the
+// cpu that gets it does the initilization. The rest just spin waiting
+// til initilization is complete.
+	movl		r22 = initlock;;
+	or		r22 = r22,r6			// Relocate to boot node
+	mov		r23 = 1;;
+	xchg8		r23 = [r22],r23;;
+	cmp.eq 		p6,p0 = 0,r23
+(p6)	br.cond.spnt.few init
+1:	ld4		r23 = [r22];;
+	cmp.eq		p6,p0 = 1,r23
+(p6)	br.cond.sptk	1b
+	br		initx
+
+// Add base address of node memory to each pointer in the .got section.
+init:	movl		r16 = _GLOBAL_OFFSET_TABLE_;;
+	or		r16 = r16,r6;;			// Relocate to boot node
+1: 	ld8		r17 = [r16];;
+	cmp.eq		p6,p7=0,r17
+(p6)	br.cond.sptk.few.clr 2f;;
+	or		r17 = r17,r6;;			// Relocate to boot node
+	st8		[r16] = r17,8
+	br		1b
+2:
+	mov		r23 = 2;;			// All done, release the spinning cpus
+	st4		[r22] = r23
+initx:
+
+//
+//	I/O-port space base address:
+//
+	movl		r2 = IOPB_PA;;
+	mov		ar.k0 = r2
+
+
+// Now call main & pass it the current LID value.
+	alloc 		r0=ar.pfs,0,0,2,0
+	mov    		r32=r26
+	mov   		r33=r8;;
+	br.call.sptk.few rp=fmain
+	
+// Initialize Region Registers
+//
+        mov             r10 = r0
+        mov             r2 = (13<<2)
+        mov             r3 = r0;;
+1:      cmp4.gtu        p6,p7 = 7, r3
+        dep             r10 = r3, r10, 61, 3
+        dep             r2 = r3, r2, RR_RID, 4;;
+(p7)    dep             r2 = 0, r2, 0, 1;;
+(p6)    dep             r2 = -1, r2, 0, 1;;
+        mov             rr[r10] = r2
+        add             r3 = 1, r3;;
+        srlz.d;;
+        cmp4.gtu        p6,p0 = 8, r3
+(p6)    br.cond.sptk.few.clr 1b
+
+//
+// Return value indicates if we are the BSP or AP.
+// 	   1 = BSP, 0 = AP
+	mov             cr.tpr=r0;;
+	cmp.eq		p6,p0=r8,r0
+(p6)	br.cond.spnt	slave
+
+//
+// Go to kernel C startup routines
+//	Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
+//	This is the only way to set them.
+
+	movl		r28=BOOT_PARAM_ADDR
+	movl		r2=bsp_entry_pc;;
+	or 		r28 = r28,r6;;			// Relocate to boot node
+	or 		r2 = r2,r6;;			// Relocate to boot node
+	ld8		r2=[r2];;
+	or		r2=r2,r6;;
+	dep		r2=0,r2,61,3;;			// convert to phys mode
+
+//
+// Turn on address translation, interrupt collection, psr.ed, protection key.
+// Interrupts (PSR.i) are still off here.
+//
+
+        movl            r3 = (  IA64_PSR_BN | \
+                                IA64_PSR_AC | \
+                                IA64_PSR_DB | \
+                                IA64_PSR_DA | \
+                                IA64_PSR_IC   \
+                             )
+        ;;
+        mov             cr.ipsr = r3
+
+//
+// Go to kernel C startup routines
+//      Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
+//      This is the only way to set them.
+
+	mov		r8=r28;;
+	bsw.1		;;
+	mov		r28=r8;;
+	bsw.0		;;
+        mov             cr.iip = r2
+        srlz.d;;
+        rfi;;
+
+	.endp		_start
+
+
+
+// Slave processors come here to spin til they get an interrupt. Then they launch themselves to
+// the place ap_entry points. No initialization is necessary - the kernel makes no
+// assumptions about state on this entry.
+//	Note: should verify that the interrupt we got was really the ap_wakeup
+//	      interrupt but this should not be an issue on medusa
+slave:
+	nop.i		0x8beef				// Medusa - put cpu to sleep til interrupt occurs
+	mov		r8=cr.irr0;;			// Check for interrupt pending.
+	cmp.eq		p6,p0=r8,r0
+(p6)	br.cond.sptk	slave;;
+
+	mov		r8=cr.ivr;;			// Got one. Must read ivr to accept it
+	srlz.d;;
+	mov		cr.eoi=r0;;			// must write eoi to clear
+	movl		r8=ap_entry;;			// now jump to kernel entry
+	or 		r8 = r8,r6;;			// Relocate to boot node
+	ld8		r9=[r8],8;;
+	ld8		r1=[r8]
+	mov		b0=r9;;
+	br		b0
+
+// Here is the kernel stack used for the fake PROM
+	.bss
+	.align		16384
+bootstack:
+	.skip		16384
+bootstacke:
+initlock:
+	data4
+
+
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////
+// This code emulates the PAL. Only essential interfaces are emulated.
+
+
+	.text
+	.global	pal_emulator
+	.proc	pal_emulator
+pal_emulator:
+	mov	r8=-1
+
+	mov	r9=256
+	;;
+	cmp.gtu p6,p7=r9,r28		/* r28 <= 255? */
+(p6)	br.cond.sptk.few static
+	;;
+	mov	r9=512
+	;;
+	cmp.gtu p6,p7=r9,r28
+(p6)	br.cond.sptk.few stacked
+	;;
+
+static:	cmp.eq	p6,p7=6,r28		/* PAL_PTCE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9=0x100000000			/* tc.base */
+	movl	r10=0x0000000200000003		/* count[0], count[1] */
+	movl	r11=0x1000000000002000		/* stride[0], stride[1] */
+	;;
+
+1:	cmp.eq	p6,p7=14,r28		/* PAL_FREQ_RATIOS */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9 =0x100000064			/* proc_ratio (1/100) */
+	movl	r10=0x100000100			/* bus_ratio<<32 (1/256) */
+	movl	r11=0x10000000a			/* itc_ratio<<32 (1/100) */
+	;;
+
+1:	cmp.eq	p6,p7=8,r28		/* PAL_VM_SUMMARY */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+#ifdef CONFIG_IA64_SGI_SN1
+	movl	r9=0x0203083001151059
+	movl	r10=0x1232
+#else
+	movl	r9=0x0203083001151065
+	movl	r10=0x183f
+#endif
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=19,r28		/* PAL_RSE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+	movl	r9=0x60
+	movl	r10=0x0
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=15,r28		/* PAL_PERF_MON_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+	movl	r9=0x08122004
+	movl	r10=0x0
+	movl	r11=0
+	mov	r2=ar.lc
+	mov	r3=16;;
+	mov	ar.lc=r3
+	mov	r3=r29;;
+5:	st8	[r3]=r0,8
+	br.cloop.sptk.few 5b;;
+	mov	ar.lc=r2
+	mov	r3=r29
+	movl	r2=0x1fff;;			/* PMC regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0x3ffff;;			/* PMD regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0xf0;;			/* cycle regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0x10;;			/* retired regs */
+	st8	[r3]=r2
+	;;
+
+1:	cmp.eq	p6,p7=19,r28		/* PAL_RSE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9=96				/* num phys stacked */
+	movl	r10=0				/* hints */
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=1,r28		/* PAL_CACHE_FLUSH */
+(p7)	br.cond.sptk.few 1f
+	mov	r9=ar.lc
+	movl	r8=524288				/* flush 512k million cache lines (16MB) */
+	;;
+	mov	ar.lc=r8
+	movl	r8=0xe000000000000000
+	;;
+.loop:	fc	r8
+	add	r8=32,r8
+	br.cloop.sptk.few .loop
+	sync.i
+	;;
+	srlz.i
+	;;
+	mov	ar.lc=r9
+	mov	r8=r0
+1:	br.cond.sptk.few rp
+
+stacked:
+	br.ret.sptk.few rp
+
+	.endp pal_emulator
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/fw-emu.c linux/arch/ia64/sn/fakeprom/fw-emu.c
--- linux.orig/arch/ia64/sn/fakeprom/fw-emu.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/fw-emu.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,836 @@
+/*
+ * PAL & SAL emulation.
+ *
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+#include <linux/config.h>
+#include <asm/efi.h>
+#include <asm/pal.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/processor.h>
+#include <asm/sn/sn_cpuid.h>
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+#endif
+#include <asm/acpi-ext.h>
+#include "fpmem.h"
+
+#define zzACPI_1_0	1		/* Include ACPI 1.0 tables */
+
+#define OEMID			"SGI"
+#ifdef CONFIG_IA64_SGI_SN1
+#define PRODUCT			"SN1"
+#define PROXIMITY_DOMAIN(nasid)	(nasid)
+#else
+#define PRODUCT			"SN2"
+#define PROXIMITY_DOMAIN(nasid)	(((nasid)>>1) & 255)
+#endif
+
+#define MB	(1024*1024UL)
+#define GB	(MB*1024UL)
+#define BOOT_PARAM_ADDR 0x40000
+#define MAX(i,j)		((i) > (j) ? (i) : (j))
+#define MIN(i,j)		((i) < (j) ? (i) : (j))
+#define ABS(i)			((i) > 0   ? (i) : -(i))
+#define ALIGN8(p)		(((long)(p) +7) & ~7)
+
+#define FPROM_BUG()		do {while (1);} while (0)
+#define MAX_SN_NODES		128
+#define MAX_LSAPICS		512
+#define MAX_CPUS		512
+#define MAX_CPUS_NODE		4
+#define CPUS_PER_NODE		4
+#define CPUS_PER_FSB		2
+#define CPUS_PER_FSB_MASK	(CPUS_PER_FSB-1)
+
+#ifdef ACPI_1_0
+#define NUM_EFI_DESCS		3
+#else
+#define NUM_EFI_DESCS		2
+#endif
+
+#define RSDP_CHECKSUM_LENGTH	20
+
+typedef union ia64_nasid_va {
+        struct {
+#if defined(CONFIG_IA64_SGI_SN1)
+                unsigned long off   : 33;       /* intra-region offset */
+		unsigned long nasid :  7;	/* NASID */
+		unsigned long off2  : 21;	/* fill */
+                unsigned long reg   :  3;       /* region number */
+#elif defined(CONFIG_IA64_SGI_SN2)
+                unsigned long off   : 36;       /* intra-region offset */
+		unsigned long attr  :  2;
+		unsigned long nasid : 11;	/* NASID */
+		unsigned long off2  : 12;	/* fill */
+                unsigned long reg   :  3;       /* region number */
+#endif
+        } f;
+        unsigned long l;
+        void *p;
+} ia64_nasid_va;
+
+typedef struct {
+	unsigned long	pc;
+	unsigned long	gp;
+} func_ptr_t;
+ 
+#define IS_VIRTUAL_MODE() 	 ({struct ia64_psr psr; asm("mov %0=psr" : "=r"(psr)); psr.dt;})
+#define ADDR_OF(p)		(IS_VIRTUAL_MODE() ? ((void*)((long)(p)+PAGE_OFFSET)) : ((void*) (p)))
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.l;})
+#elif defined(CONFIG_IA64_SGI_SN2)
+#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.f.attr = 3; _v.l;})
+#endif
+
+/*
+ * The following variables are passed thru registersfrom the configuration file and
+ * are set via the _start function.
+ */
+long		base_nasid;
+long		num_cpus;
+long		bsp_entry_pc=0;
+long		num_nodes;
+long		app_entry_pc;
+int		bsp_lid;
+func_ptr_t	ap_entry;
+
+
+extern void pal_emulator(void);
+static efi_runtime_services_t    *efi_runtime_p;
+static char fw_mem[(  sizeof(efi_system_table_t)
+		    + sizeof(efi_runtime_services_t)
+		    + NUM_EFI_DESCS*sizeof(efi_config_table_t)
+		    + sizeof(struct ia64_sal_systab)
+		    + sizeof(struct ia64_sal_desc_entry_point)
+		    + sizeof(struct ia64_sal_desc_ap_wakeup)
+#ifdef ACPI_1_0
+		    + sizeof(acpi_rsdp_t)
+		    + sizeof(acpi_rsdt_t)
+		    + sizeof(acpi_sapic_t)
+		    + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t))
+#endif
+		    + sizeof(acpi20_rsdp_t)
+		    + sizeof(acpi_xsdt_t)
+		    + sizeof(acpi_slit_t)
+		    +   MAX_SN_NODES*MAX_SN_NODES+8
+		    + sizeof(acpi_madt_t)
+		    +   16*MAX_CPUS
+		    + (1+8*MAX_SN_NODES)*(sizeof(efi_memory_desc_t))
+		    + sizeof(acpi_srat_t)
+		    +   MAX_CPUS*sizeof(srat_cpu_affinity_t)
+		    +   MAX_SN_NODES*sizeof(srat_memory_affinity_t)
+		    + sizeof(ia64_sal_desc_ptc_t) +
+		    + MAX_SN_NODES*sizeof(ia64_sal_ptc_domain_info_t) +
+		    + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) +
+		    + 1024)] __attribute__ ((aligned (8)));
+
+
+static efi_status_t
+efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
+{
+	if (tm) {
+		memset(tm, 0, sizeof(*tm));
+		tm->year = 2000;
+		tm->month = 2;
+		tm->day = 13;
+		tm->hour = 10;
+		tm->minute = 11;
+		tm->second = 12;
+	}
+
+	if (tc) {
+		tc->resolution = 10;
+		tc->accuracy = 12;
+		tc->sets_to_zero = 1;
+	}
+
+	return EFI_SUCCESS;
+}
+
+static void
+efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
+{
+	while(1);	/* Is there a pseudo-op to stop medusa */
+}
+
+static efi_status_t
+efi_success (void)
+{
+	return EFI_SUCCESS;
+}
+
+static efi_status_t
+efi_unimplemented (void)
+{
+	return EFI_UNSUPPORTED;
+}
+
+#ifdef CONFIG_IA64_SGI_SN2
+
+#undef cpu_physical_id
+#define cpu_physical_id(cpuid)                  ((ia64_get_lid() >> 16) & 0xffff)
+
+void
+fprom_send_cpei(void) {
+        long            *p, val;
+        long            physid;
+        long            nasid, slice;
+
+        physid = cpu_physical_id(0);
+        nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+        p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT);
+        val =   (1UL<<SH_IPI_INT_SEND_SHFT) |
+                (physid<<SH_IPI_INT_PID_SHFT) |
+                ((long)0<<SH_IPI_INT_TYPE_SHFT) |
+                ((long)0x1e<<SH_IPI_INT_IDX_SHFT) |
+                (0x000feeUL<<SH_IPI_INT_BASE_SHFT);
+        *p = val;
+
+}
+#endif
+
+
+static long
+sal_emulator (long index, unsigned long in1, unsigned long in2,
+	      unsigned long in3, unsigned long in4, unsigned long in5,
+	      unsigned long in6, unsigned long in7)
+{
+	register long r9 asm ("r9") = 0;
+	register long r10 asm ("r10") = 0;
+	register long r11 asm ("r11") = 0;
+	long status;
+
+	/*
+	 * Don't do a "switch" here since that gives us code that
+	 * isn't self-relocatable.
+	 */
+	status = 0;
+	if (index == SAL_FREQ_BASE) {
+		switch (in1) {
+		      case SAL_FREQ_BASE_PLATFORM:
+			r9 = 500000000;
+			break;
+
+		      case SAL_FREQ_BASE_INTERVAL_TIMER:
+			/*
+			 * Is this supposed to be the cr.itc frequency
+			 * or something platform specific?  The SAL
+			 * doc ain't exactly clear on this...
+			 */
+			r9 = 700000000;
+			break;
+
+		      case SAL_FREQ_BASE_REALTIME_CLOCK:
+			r9 = 50000000;
+			break;
+
+		      default:
+			status = -1;
+			break;
+		}
+	} else if (index == SAL_SET_VECTORS) {
+		if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
+			func_ptr_t	*fp;
+			fp = ADDR_OF(&ap_entry);
+			fp->pc = in2;
+			fp->gp = in3;
+		} else if (in1 == SAL_VECTOR_OS_MCA || in1 == SAL_VECTOR_OS_INIT) {
+		} else {
+			status = -1;
+		}
+		;
+	} else if (index == SAL_GET_STATE_INFO) {
+		;
+	} else if (index == SAL_GET_STATE_INFO_SIZE) {
+		;
+	} else if (index == SAL_CLEAR_STATE_INFO) {
+		;
+	} else if (index == SAL_MC_RENDEZ) {
+		;
+	} else if (index == SAL_MC_SET_PARAMS) {
+		;
+	} else if (index == SAL_CACHE_FLUSH) {
+		;
+	} else if (index == SAL_CACHE_INIT) {
+		;
+	} else if (index == SAL_UPDATE_PAL) {
+		;
+#ifdef CONFIG_IA64_SGI_SN2
+	} else if (index == SN_SAL_LOG_CE) {
+#ifdef ajmtestcpei
+		fprom_send_cpei();
+#else /* ajmtestcpei */
+		;
+#endif /* ajmtestcpei */
+#endif
+	} else if (index == SN_SAL_PROBE) {
+		r9 = 0UL;
+		if (in2 == 4) {
+			r9 = *(unsigned *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 2) {
+			r9 = *(unsigned short *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 1) {
+			r9 = *(unsigned char *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 8) {
+			r9 = *(unsigned long *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else {
+			status = 2;
+		}
+	} else if (index == SN_SAL_GET_KLCONFIG_ADDR) {
+		r9 = 0x30000;
+	} else if (index == SN_SAL_CONSOLE_PUTC) {
+		status = -1;
+	} else if (index == SN_SAL_CONSOLE_GETC) {
+		status = -1;
+	} else if (index == SN_SAL_CONSOLE_POLL) {
+		status = -1;
+	} else {
+		status = -1;
+	}
+
+	asm volatile ("" :: "r"(r9), "r"(r10), "r"(r11));
+	return status;
+}
+
+
+/*
+ * This is here to work around a bug in egcs-1.1.1b that causes the
+ * compiler to crash (seems like a bug in the new alias analysis code.
+ */
+void *
+id (long addr)
+{
+	return (void *) addr;
+}
+
+
+/*
+ * Fix the addresses in a function pointer by adding base node address
+ * to pc & gp.
+ */
+void
+fix_function_pointer(void *fp)
+{
+	func_ptr_t	*_fp;
+
+	_fp = fp;
+	_fp->pc = __fwtab_pa(base_nasid, _fp->pc);
+	_fp->gp = __fwtab_pa(base_nasid, _fp->gp);
+}
+
+void
+fix_virt_function_pointer(void **fptr)
+{
+        func_ptr_t      *fp;
+	long		*p;
+
+	p = (long*)fptr;
+        fp = *fptr;
+        fp->pc = fp->pc | PAGE_OFFSET;
+        fp->gp = fp->gp | PAGE_OFFSET;
+	*p |= PAGE_OFFSET;
+}
+
+
+int
+efi_set_virtual_address_map(void)
+{
+        efi_runtime_services_t            *runtime;
+
+        runtime = efi_runtime_p;
+        fix_virt_function_pointer((void**)&runtime->get_time);
+        fix_virt_function_pointer((void**)&runtime->set_time);
+        fix_virt_function_pointer((void**)&runtime->get_wakeup_time);
+        fix_virt_function_pointer((void**)&runtime->set_wakeup_time);
+        fix_virt_function_pointer((void**)&runtime->set_virtual_address_map);
+        fix_virt_function_pointer((void**)&runtime->get_variable);
+        fix_virt_function_pointer((void**)&runtime->get_next_variable);
+        fix_virt_function_pointer((void**)&runtime->set_variable);
+        fix_virt_function_pointer((void**)&runtime->get_next_high_mono_count);
+        fix_virt_function_pointer((void**)&runtime->reset_system);
+        return EFI_SUCCESS;;
+}
+
+void
+acpi_table_init(acpi_desc_table_hdr_t *p, char *sig, int siglen, int revision, int oem_revision)
+{
+	memcpy(p->signature, sig, siglen);
+	memcpy(p->oem_id, OEMID, 6);
+	memcpy(p->oem_table_id, sig, 4);
+	memcpy(p->oem_table_id+4, PRODUCT, 4);
+	p->revision = revision;
+	p->oem_revision = (revision<<16) + oem_revision;
+	p->creator_id = 1;
+	p->creator_revision = 1;
+}
+
+void
+acpi_checksum(acpi_desc_table_hdr_t *p, int length)
+{
+	u8	*cp, *cpe, checksum;
+
+	p->checksum = 0;
+	p->length = length;
+	checksum = 0;
+	for (cp=(u8*)p, cpe=cp+p->length; cp<cpe; cp++)
+		checksum += *cp;
+	p->checksum = -checksum;
+}
+
+void
+acpi_checksum_rsdp20(acpi20_rsdp_t *p, int length)
+{
+	u8	*cp, *cpe, checksum;
+
+	p->checksum = 0;
+	p->length = length;
+	checksum = 0;
+	for (cp=(u8*)p, cpe=cp+RSDP_CHECKSUM_LENGTH; cp<cpe; cp++)
+		checksum += *cp;
+	p->checksum = -checksum;
+}
+
+int
+nasid_present(int nasid)
+{
+	int	cnode;
+	for (cnode=0; cnode<num_nodes; cnode++)
+		if (GetNasid(cnode) == nasid)
+			return 1;
+	return 0;
+}
+
+void
+sys_fw_init (const char *args, int arglen, int bsp)
+{
+	/*
+	 * Use static variables to keep from overflowing the RSE stack
+	 */
+	static efi_system_table_t *efi_systab;
+	static efi_runtime_services_t *efi_runtime;
+	static efi_config_table_t *efi_tables;
+	static ia64_sal_desc_ptc_t *sal_ptc;
+	static ia64_sal_ptc_domain_info_t *sal_ptcdi;
+	static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid;
+#ifdef ACPI_1_0
+	static acpi_rsdp_t *acpi_rsdp;
+	static acpi_rsdt_t *acpi_rsdt;
+	static acpi_sapic_t *acpi_sapic;
+	static acpi_entry_lsapic_t *acpi_lsapic;
+#endif
+	static acpi20_rsdp_t *acpi20_rsdp;
+	static acpi_xsdt_t *acpi_xsdt;
+	static acpi_slit_t *acpi_slit;
+	static acpi_madt_t *acpi_madt;
+	static acpi20_entry_lsapic_t *lsapic20;
+	static struct ia64_sal_systab *sal_systab;
+	static acpi_srat_t *acpi_srat;
+	static srat_cpu_affinity_t *srat_cpu_affinity;
+	static srat_memory_affinity_t *srat_memory_affinity;
+	static efi_memory_desc_t *efi_memmap, *md;
+	static unsigned long *pal_desc, *sal_desc;
+	static struct ia64_sal_desc_entry_point *sal_ed;
+	static struct ia64_boot_param *bp;
+	static struct ia64_sal_desc_ap_wakeup *sal_apwake;
+	static unsigned char checksum;
+	static char *cp, *cmd_line, *vendor;
+	static void *ptr;
+	static int mdsize, domain, last_domain ;
+	static int i, j, cnode, max_nasid, nasid, cpu, num_memmd, cpus_found;
+
+	/*
+	 * Pass the parameter base address to the build_efi_xxx routines.
+	 */
+#if defined(CONFIG_IA64_SGI_SN1)
+	build_init(8LL*GB*base_nasid);
+#else
+	build_init(0x3000000000UL | ((long)base_nasid<<38));
+#endif
+
+	num_nodes = GetNumNodes();
+	num_cpus = GetNumCpus();
+	for (max_nasid=0, cnode=0; cnode<num_nodes; cnode++)
+		max_nasid = MAX(max_nasid, GetNasid(cnode));
+
+
+	memset(fw_mem, 0, sizeof(fw_mem));
+
+	pal_desc = (unsigned long *) &pal_emulator;
+	sal_desc = (unsigned long *) &sal_emulator;
+	fix_function_pointer(&pal_emulator);
+	fix_function_pointer(&sal_emulator);
+
+	/* Align this to 16 bytes, probably EFI does this  */
+	mdsize = (sizeof(efi_memory_desc_t) + 15) & ~15 ;
+
+	cp = fw_mem;
+	efi_systab  = (void *) cp; cp += ALIGN8(sizeof(*efi_systab));
+	efi_runtime_p = efi_runtime = (void *) cp; cp += ALIGN8(sizeof(*efi_runtime));
+	efi_tables  = (void *) cp; cp += ALIGN8(NUM_EFI_DESCS*sizeof(*efi_tables));
+	sal_systab  = (void *) cp; cp += ALIGN8(sizeof(*sal_systab));
+	sal_ed      = (void *) cp; cp += ALIGN8(sizeof(*sal_ed));
+	sal_ptc     = (void *) cp; cp += ALIGN8(sizeof(*sal_ptc));
+	sal_apwake  = (void *) cp; cp += ALIGN8(sizeof(*sal_apwake));
+	acpi20_rsdp = (void *) cp; cp += ALIGN8(sizeof(*acpi20_rsdp));
+	acpi_xsdt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_xsdt) + 64); 
+			/* save space for more OS defined table pointers. */
+
+#ifdef ACPI_1_0
+	acpi_rsdp   = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdp));
+	acpi_rsdt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdt));
+	acpi_sapic  = (void *) cp; cp += sizeof(*acpi_sapic);
+	acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic);
+#endif
+	acpi_slit   = (void *) cp; cp += ALIGN8(sizeof(*acpi_slit) + 8 + (max_nasid+1)*(max_nasid+1));
+	acpi_madt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_madt) + 8 * num_cpus+ 8);
+	acpi_srat   = (void *) cp; cp += ALIGN8(sizeof(acpi_srat_t));
+	cp         += sizeof(srat_cpu_affinity_t)*num_cpus + sizeof(srat_memory_affinity_t)*num_nodes;
+	vendor 	    = (char *) cp; cp += ALIGN8(40);
+	efi_memmap  = (void *) cp; cp += ALIGN8(8*32*sizeof(*efi_memmap));
+	sal_ptcdi   = (void *) cp; cp += ALIGN8(CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi));
+	sal_ptclid  = (void *) cp; cp += ALIGN8(((3+num_cpus)*sizeof(*sal_ptclid)+7)/8*8);
+	cmd_line    = (void *) cp;
+
+	if (args) {
+		if (arglen >= 1024)
+			arglen = 1023;
+		memcpy(cmd_line, args, arglen);
+	} else {
+		arglen = 0;
+	}
+	cmd_line[arglen] = '\0';
+	/* 
+	 * For now, just bring up bash.
+	 * If you want to execute all the startup scripts, delete the "init=..".
+	 * You can also edit this line to pass other arguments to the kernel.
+	 *    Note: disable kernel text replication.
+	 */
+	strcpy(cmd_line, "init=/bin/bash ktreplicate=0");
+
+	memset(efi_systab, 0, sizeof(efi_systab));
+	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
+	efi_systab->hdr.revision  = EFI_SYSTEM_TABLE_REVISION;
+	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
+	efi_systab->fw_vendor = __fwtab_pa(base_nasid, vendor);
+	efi_systab->fw_revision = 1;
+	efi_systab->runtime = __fwtab_pa(base_nasid, efi_runtime);
+	efi_systab->nr_tables = 2;
+	efi_systab->tables = __fwtab_pa(base_nasid, efi_tables);
+	memcpy(vendor, "S\0i\0l\0i\0c\0o\0n\0-\0G\0r\0a\0p\0h\0i\0c\0s\0\0", 40);
+
+	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
+	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
+	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
+	efi_runtime->get_time = __fwtab_pa(base_nasid, &efi_get_time);
+	efi_runtime->set_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_virtual_address_map = __fwtab_pa(base_nasid, &efi_set_virtual_address_map);
+	efi_runtime->get_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_next_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_next_high_mono_count = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->reset_system = __fwtab_pa(base_nasid, &efi_reset_system);
+
+	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, sal_systab);
+	efi_tables++;
+#ifdef ACPI_1_0
+	efi_tables->guid = ACPI_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, acpi_rsdp);
+	efi_tables++;
+#endif
+	efi_tables->guid = ACPI_20_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, acpi20_rsdp);
+	efi_tables++;
+
+	fix_function_pointer(&efi_unimplemented);
+	fix_function_pointer(&efi_get_time);
+	fix_function_pointer(&efi_success);
+	fix_function_pointer(&efi_reset_system);
+	fix_function_pointer(&efi_set_virtual_address_map);
+
+#ifdef ACPI_1_0
+	/* fill in the ACPI system table - has a pointer to the ACPI table header */
+	memcpy(acpi_rsdp->signature, "RSD PTR ", 8);
+	acpi_rsdp->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt);
+
+	acpi_table_init(&acpi_rsdt->header, ACPI_RSDT_SIG, ACPI_RSDT_SIG_LEN, 1, 1);
+	acpi_rsdt->header.length = sizeof(acpi_rsdt_t);
+	acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic);
+
+	memcpy(acpi_sapic->header.signature, "SPIC ", 4);
+	acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t);
+
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			acpi_lsapic->type = ACPI_ENTRY_LOCAL_SAPIC;
+			acpi_lsapic->length = sizeof(acpi_entry_lsapic_t);
+			acpi_lsapic->acpi_processor_id = cnode*4+cpu;
+			acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
+#if defined(CONFIG_IA64_SGI_SN1)
+			acpi_lsapic->eid = cpu;
+			acpi_lsapic->id = nasid;
+#else
+			acpi_lsapic->eid = nasid&0xffff;
+			acpi_lsapic->id = (cpu<<4) | (nasid>>16);
+#endif
+			acpi_lsapic++;
+		}
+	}
+#endif
+
+
+	/* fill in the ACPI20 system table - has a pointer to the ACPI table header */
+	memcpy(acpi20_rsdp->signature, "RSD PTR ", 8);
+	acpi20_rsdp->xsdt = (struct acpi_xsdt*)__fwtab_pa(base_nasid, acpi_xsdt);
+	acpi20_rsdp->revision = 2;
+	acpi_checksum_rsdp20(acpi20_rsdp, sizeof(acpi20_rsdp_t));
+
+	/* Set up the XSDT table  - contains pointers to the other ACPI tables */
+	acpi_table_init(&acpi_xsdt->header, ACPI_XSDT_SIG, ACPI_XSDT_SIG_LEN, 1, 1);
+	acpi_xsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_madt);
+	acpi_xsdt->entry_ptrs[1] = __fwtab_pa(base_nasid, acpi_slit);
+	acpi_xsdt->entry_ptrs[2] = __fwtab_pa(base_nasid, acpi_srat);
+	acpi_checksum(&acpi_xsdt->header, sizeof(acpi_xsdt_t) + 16);
+
+	/* Set up the MADT table */
+	acpi_table_init(&acpi_madt->header, ACPI_MADT_SIG, ACPI_MADT_SIG_LEN, 1, 1);
+	lsapic20 = (acpi20_entry_lsapic_t*) (acpi_madt + 1);
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			lsapic20->type = ACPI20_ENTRY_LOCAL_SAPIC;
+			lsapic20->length = sizeof(acpi_entry_lsapic_t);
+			lsapic20->acpi_processor_id = cnode*4+cpu;
+			lsapic20->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
+#if defined(CONFIG_IA64_SGI_SN1)
+			lsapic20->eid = cpu;
+			lsapic20->id = nasid;
+#else
+			lsapic20->eid = nasid&0xffff;
+			lsapic20->id = (cpu<<4) | (nasid>>16);
+#endif
+			lsapic20 = (acpi20_entry_lsapic_t*) ((long)lsapic20+sizeof(acpi_entry_lsapic_t));
+		}
+	}
+	acpi_checksum(&acpi_madt->header, (char*)lsapic20 - (char*)acpi_madt);
+
+	/* Set up the SRAT table */
+	acpi_table_init(&acpi_srat->header, ACPI_SRAT_SIG, ACPI_SRAT_SIG_LEN, ACPI_SRAT_REVISION, 1);
+	ptr = acpi_srat+1;
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		srat_memory_affinity = ptr;
+		ptr = srat_memory_affinity+1;
+		srat_memory_affinity->type = SRAT_MEMORY_STRUCTURE;
+		srat_memory_affinity->length = sizeof(srat_memory_affinity_t);
+		srat_memory_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid);
+		srat_memory_affinity->base_addr_lo = 0;
+		srat_memory_affinity->length_lo = 0;
+#if defined(CONFIG_IA64_SGI_SN1)
+		srat_memory_affinity->base_addr_hi = nasid<<1;
+		srat_memory_affinity->length_hi = SN1_NODE_SIZE>>32;
+#else
+		srat_memory_affinity->base_addr_hi = (nasid<<6) | (3<<4);
+		srat_memory_affinity->length_hi = SN2_NODE_SIZE>>32;
+#endif
+		srat_memory_affinity->memory_type = ACPI_ADDRESS_RANGE_MEMORY;
+		srat_memory_affinity->flags = SRAT_MEMORY_FLAGS_ENABLED;
+	}
+
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			srat_cpu_affinity = ptr;
+			ptr = srat_cpu_affinity + 1;
+			srat_cpu_affinity->type = SRAT_CPU_STRUCTURE;
+			srat_cpu_affinity->length = sizeof(srat_cpu_affinity_t);
+			srat_cpu_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid);
+			srat_cpu_affinity->flags = SRAT_CPU_FLAGS_ENABLED;
+#if defined(CONFIG_IA64_SGI_SN1)
+			srat_cpu_affinity->apic_id = nasid;
+			srat_cpu_affinity->local_sapic_eid = cpu;
+#else
+			srat_cpu_affinity->local_sapic_eid = nasid&0xffff;
+			srat_cpu_affinity->apic_id = (cpu<<4) | (nasid>>16);
+#endif
+		}
+	}
+	acpi_checksum(&acpi_srat->header, (char*)ptr - (char*)acpi_srat);
+
+
+	/* Set up the SLIT table */
+	acpi_table_init(&acpi_slit->header, ACPI_SLIT_SIG, ACPI_SLIT_SIG_LEN, ACPI_SLIT_REVISION, 1);
+	acpi_slit->localities = PROXIMITY_DOMAIN(max_nasid)+1;
+	cp=acpi_slit->entries;
+	memset(cp, 255, acpi_slit->localities*acpi_slit->localities);
+
+	for (i=0; i<=max_nasid; i++)
+		for (j=0; j<=max_nasid; j++)
+			if (nasid_present(i) && nasid_present(j))
+				*(cp+PROXIMITY_DOMAIN(i)*acpi_slit->localities+PROXIMITY_DOMAIN(j)) = 10 + MIN(254, 5*ABS(i-j));
+
+	cp = acpi_slit->entries + acpi_slit->localities*acpi_slit->localities;
+	acpi_checksum(&acpi_slit->header, cp - (char*)acpi_slit);
+
+
+	/* fill in the SAL system table: */
+	memcpy(sal_systab->signature, "SST_", 4);
+	sal_systab->size = sizeof(*sal_systab);
+	sal_systab->sal_rev_minor = 1;
+	sal_systab->sal_rev_major = 0;
+	sal_systab->entry_count = 3;
+
+	strcpy(sal_systab->oem_id, "SGI");
+	strcpy(sal_systab->product_id, "SN1");
+
+	/* fill in an entry point: */	
+	sal_ed->type = SAL_DESC_ENTRY_POINT;
+	sal_ed->pal_proc = __fwtab_pa(base_nasid, pal_desc[0]);
+	sal_ed->sal_proc = __fwtab_pa(base_nasid, sal_desc[0]);
+	sal_ed->gp = __fwtab_pa(base_nasid, sal_desc[1]);
+
+	/* kludge the PTC domain info */
+	sal_ptc->type = SAL_DESC_PTC;
+	sal_ptc->num_domains = 0;
+	sal_ptc->domain_info = __fwtab_pa(base_nasid, sal_ptcdi);
+	cpus_found = 0;
+	last_domain = -1;
+	sal_ptcdi--;
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (IsCpuPresent(cnode, cpu)) {
+				domain = cnode*CPUS_PER_NODE + cpu/CPUS_PER_FSB;
+				if (domain != last_domain) {
+					sal_ptc->num_domains++;
+					sal_ptcdi++;
+					sal_ptcdi->proc_count = 0;
+					sal_ptcdi->proc_list = __fwtab_pa(base_nasid, sal_ptclid);
+					last_domain = domain;
+				}
+				sal_ptcdi->proc_count++;
+				sal_ptclid->id = nasid;
+				sal_ptclid->eid = cpu;
+				sal_ptclid++;
+				cpus_found++;
+			}
+		}
+	}
+
+	if (cpus_found != num_cpus)
+		FPROM_BUG();
+
+	/* Make the AP WAKEUP entry */
+	sal_apwake->type = SAL_DESC_AP_WAKEUP;
+	sal_apwake->mechanism = IA64_SAL_AP_EXTERNAL_INT;
+	sal_apwake->vector = 18;
+
+	for (checksum=0, cp=(char*)sal_systab; cp < (char *)efi_memmap; ++cp)
+		checksum += *cp;
+	sal_systab->checksum = -checksum;
+
+	/* If the checksum is correct, the kernel tries to use the
+	 * table. We dont build enough table & the kernel aborts.
+	 * Note that the PROM hasd thhhe same problem!!
+	 */
+#ifdef DOESNT_WORK
+	for (checksum=0, cp=(char*)acpi_rsdp, cpe=cp+RSDP_CHECKSUM_LENGTH; cp<cpe; ++cp)
+		checksum += *cp;
+	acpi_rsdp->checksum = -checksum;
+#endif
+
+	md = &efi_memmap[0];
+	num_memmd = build_efi_memmap((void *)md, mdsize) ;
+
+	bp = (struct ia64_boot_param*) __fwtab_pa(base_nasid, BOOT_PARAM_ADDR);
+	bp->efi_systab = __fwtab_pa(base_nasid, &fw_mem);
+	bp->efi_memmap = __fwtab_pa(base_nasid, efi_memmap);
+	bp->efi_memmap_size = num_memmd*mdsize;
+	bp->efi_memdesc_size = mdsize;
+	bp->efi_memdesc_version = 0x101;
+	bp->command_line = __fwtab_pa(base_nasid, cmd_line);
+	bp->console_info.num_cols = 80;
+	bp->console_info.num_rows = 25;
+	bp->console_info.orig_x = 0;
+	bp->console_info.orig_y = 24;
+	bp->fpswa = 0;
+
+	/*
+	 * Now pick the BSP & store it LID value in
+	 * a global variable. Note if BSP is greater than last cpu,
+	 * pick the last cpu.
+	 */
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+#ifdef CONFIG_IA64_SGI_SN1
+			bsp_lid = (GetNasid(cnode)<<24) | (cpu<<16);
+#else
+			bsp_lid = (GetNasid(cnode)<<16) | (cpu<<28);
+#endif
+			if (bsp-- > 0)
+				continue;
+			return;
+		}
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/klgraph_init.c linux/arch/ia64/sn/fakeprom/klgraph_init.c
--- linux.orig/arch/ia64/sn/fakeprom/klgraph_init.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/klgraph_init.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,287 @@
+/* $Id: klgraph_init.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+
+/*
+ * This is a temporary file that statically initializes the expected 
+ * initial klgraph information that is normally provided by prom.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+
+#define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
+#define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
+#define HUBREG                  ((char *)0xc0000a0001e00000)
+#define WIDGET0                 ((char *)0xc0000a0000000000)
+#define WIDGET4                 ((char *)0xc0000a0000000004)
+
+#define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
+#define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
+#define HUBREG                  ((char *)0xc0000a0001e00000)
+#define WIDGET0                 ((char *)0xc0000a0000000000)
+
+#define convert(a,b,c) temp = (u64 *)a; *temp = b; temp++; *temp = c
+void
+klgraph_init(void)
+{
+
+	u64	*temp;
+
+	/*
+	 * Initialize some hub/xbow registers that allows access to 
+	 * Xbridge etc.  These are normally done in PROM.
+	 */
+
+        /* Write IOERR clear to clear the CRAZY bit in the status */
+#ifdef CONFIG_IA64_SGI_SN1
+        *(volatile uint64_t *)0xc0000a0001c001f8 = (uint64_t)0xffffffff;
+
+        /* set widget control register...setting bedrock widget id to b */
+        *(volatile uint64_t *)0xc0000a0001c00020 = (uint64_t)0x801b;
+
+        /* set io outbound widget access...allow all */
+        *(volatile uint64_t *)0xc0000a0001c00110 = (uint64_t)0xff01;
+
+        /* set io inbound widget access...allow all */
+        *(volatile uint64_t *)0xc0000a0001c00118 = (uint64_t)0xff01;
+
+        /* set io crb timeout to max */
+        *(volatile uint64_t *)0xc0000a0001c003c0 = (uint64_t)0xffffff;
+        *(volatile uint64_t *)0xc0000a0001c003c0 = (uint64_t)0xffffff;
+
+        /* set local block io permission...allow all */
+        *(volatile uint64_t *)0xc0000a0001e04010 = (uint64_t)0xfffffffffffffff;
+
+        /* clear any errors */
+        /* clear_ii_error(); medusa should have cleared these */
+
+        /* set default read response buffers in bridge */
+        *(volatile u32 *)0xc0000a000f000280L = 0xba98;
+        *(volatile u32 *)0xc0000a000f000288L = 0xba98;
+#elif CONFIG_IA64_SGI_SN2
+        *(volatile uint64_t *)0xc000000801c001f8 = (uint64_t)0xffffffff;
+
+        /* set widget control register...setting bedrock widget id to a */
+        *(volatile uint64_t *)0xc000000801c00020 = (uint64_t)0x801a;
+
+        /* set io outbound widget access...allow all */
+        *(volatile uint64_t *)0xc000000801c00110 = (uint64_t)0xff01;
+
+        /* set io inbound widget access...allow all */
+        *(volatile uint64_t *)0xc000000801c00118 = (uint64_t)0xff01;
+
+        /* set io crb timeout to max */
+        *(volatile uint64_t *)0xc000000801c003c0 = (uint64_t)0xffffff;
+        *(volatile uint64_t *)0xc000000801c003c0 = (uint64_t)0xffffff;
+
+        /* set local block io permission...allow all */
+// [LB]        *(volatile uint64_t *)0xc000000801e04010 = (uint64_t)0xfffffffffffffff;
+
+        /* clear any errors */
+        /* clear_ii_error(); medusa should have cleared these */
+
+        /* set default read response buffers in bridge */
+// [PI]       *(volatile u32 *)0xc00000080f000280L = 0xba98;
+// [PI]       *(volatile u32 *)0xc00000080f000288L = 0xba98;
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+	/*
+	 * kldir entries initialization - mankato
+	 */
+	convert(0x8000000000002000, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002010, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002020, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002030, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002040, 0x434d5f53505f5357, 0x0000000000030000);
+	convert(0x8000000000002050, 0x0000000000000000, 0x0000000000010000);
+	convert(0x8000000000002060, 0x0000000000000001, 0x0000000000000000);
+	convert(0x8000000000002070, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002080, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002090, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020a0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020b0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020c0, 0x434d5f53505f5357, 0x0000000000000000);
+	convert(0x80000000000020d0, 0x0000000000002400, 0x0000000000000400);
+	convert(0x80000000000020e0, 0x0000000000000001, 0x0000000000000000);
+	convert(0x80000000000020f0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002100, 0x434d5f53505f5357, 0x0000000000040000);
+	convert(0x8000000000002110, 0x0000000000000000, 0xffffffffffffffff);
+	convert(0x8000000000002120, 0x0000000000000001, 0x0000000000000000);
+	convert(0x8000000000002130, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002140, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002150, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002160, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002170, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002180, 0x434d5f53505f5357, 0x0000000000020000);
+	convert(0x8000000000002190, 0x0000000000000000, 0x0000000000010000);
+	convert(0x80000000000021a0, 0x0000000000000001, 0x0000000000000000); 
+
+	/*
+	 * klconfig entries initialization - mankato
+	 */
+	convert(0x0000000000030000, 0x00000000beedbabe, 0x0000004800000000);
+	convert(0x0000000000030010, 0x0003007000000018, 0x800002000f820178);
+	convert(0x0000000000030020, 0x80000a000f024000, 0x800002000f800000);
+	convert(0x0000000000030030, 0x0300fafa00012580, 0x00000000040f0000);
+	convert(0x0000000000030040, 0x0000000000000000, 0x0003097000030070);
+	convert(0x0000000000030050, 0x00030970000303b0, 0x0003181000033f70);
+	convert(0x0000000000030060, 0x0003d51000037570, 0x0000000000038330);
+	convert(0x0000000000030070, 0x0203110100030140, 0x0001000000000101);
+	convert(0x0000000000030080, 0x0900000000000000, 0x000000004e465e67);
+	convert(0x0000000000030090, 0x0003097000000000, 0x00030b1000030a40);
+	convert(0x00000000000300a0, 0x00030cb000030be0, 0x000315a0000314d0);
+	convert(0x00000000000300b0, 0x0003174000031670, 0x0000000000000000);
+	convert(0x0000000000030100, 0x000000000000001a, 0x3350490000000000);
+	convert(0x0000000000030110, 0x0000000000000037, 0x0000000000000000);
+	convert(0x0000000000030140, 0x0002420100030210, 0x0001000000000101);
+	convert(0x0000000000030150, 0x0100000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030160, 0x00030d8000000000, 0x0000000000030e50);
+	convert(0x00000000000301c0, 0x0000000000000000, 0x0000000000030070);
+	convert(0x00000000000301d0, 0x0000000000000025, 0x424f490000000000);
+	convert(0x00000000000301e0, 0x000000004b434952, 0x0000000000000000);
+	convert(0x0000000000030210, 0x00027101000302e0, 0x00010000000e4101);
+	convert(0x0000000000030220, 0x0200000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030230, 0x00030f2000000000, 0x0000000000030ff0);
+	convert(0x0000000000030290, 0x0000000000000000, 0x0000000000030140);
+	convert(0x00000000000302a0, 0x0000000000000026, 0x7262490000000000);
+	convert(0x00000000000302b0, 0x00000000006b6369, 0x0000000000000000);
+	convert(0x00000000000302e0, 0x0002710100000000, 0x00010000000f3101);
+	convert(0x00000000000302f0, 0x0500000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030300, 0x000310c000000000, 0x0003126000031190);
+	convert(0x0000000000030310, 0x0003140000031330, 0x0000000000000000);
+	convert(0x0000000000030360, 0x0000000000000000, 0x0000000000030140);
+	convert(0x0000000000030370, 0x0000000000000029, 0x7262490000000000);
+	convert(0x0000000000030380, 0x00000000006b6369, 0x0000000000000000);
+	convert(0x0000000000030970, 0x0000000002010102, 0x0000000000000000);
+	convert(0x0000000000030980, 0x000000004e465e67, 0xffffffff00000000);
+	/* convert(0x00000000000309a0, 0x0000000000037570, 0x0000000100000000); */
+	convert(0x00000000000309a0, 0x0000000000037570, 0xffffffff00000000);
+	convert(0x00000000000309b0, 0x0000000000030070, 0x0000000000000000);
+	convert(0x00000000000309c0, 0x000000000003f420, 0x0000000000000000);
+	convert(0x0000000000030a40, 0x0000000002010125, 0x0000000000000000);
+	convert(0x0000000000030a50, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000030a70, 0x0000000000037b78, 0x0000000000000000);
+	convert(0x0000000000030b10, 0x0000000002010125, 0x0000000000000000);
+	convert(0x0000000000030b20, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000030b40, 0x0000000000037d30, 0x0000000000000001);
+	convert(0x0000000000030be0, 0x00000000ff010203, 0x0000000000000000);
+	convert(0x0000000000030bf0, 0xffffffffffffffff, 0xffffffff000000ff);
+	convert(0x0000000000030c10, 0x0000000000037ee8, 0x0100010000000200);
+	convert(0x0000000000030cb0, 0x00000000ff310111, 0x0000000000000000);
+	convert(0x0000000000030cc0, 0xffffffffffffffff, 0x0000000000000000);
+	convert(0x0000000000030d80, 0x0000000002010104, 0x0000000000000000);
+	convert(0x0000000000030d90, 0xffffffffffffffff, 0x00000000000000ff);
+	convert(0x0000000000030db0, 0x0000000000037f18, 0x0000000000000000);
+	convert(0x0000000000030dc0, 0x0000000000000000, 0x0003007000060000);
+	convert(0x0000000000030de0, 0x0000000000000000, 0x0003021000050000);
+	convert(0x0000000000030df0, 0x000302e000050000, 0x0000000000000000);
+	convert(0x0000000000030e30, 0x0000000000000000, 0x000000000000000a);
+	convert(0x0000000000030e50, 0x00000000ff00011a, 0x0000000000000000);
+	convert(0x0000000000030e60, 0xffffffffffffffff, 0x0000000000000000);
+	convert(0x0000000000030e80, 0x0000000000037fe0, 0x9e6e9e9e9e9e9e9e);
+	convert(0x0000000000030e90, 0x000000000000bc6e, 0x0000000000000000);
+	convert(0x0000000000030f20, 0x0000000002010205, 0x00000000d0020000);
+	convert(0x0000000000030f30, 0xffffffffffffffff, 0x0000000e0000000e);
+	convert(0x0000000000030f40, 0x000000000000000e, 0x0000000000000000);
+	convert(0x0000000000030f50, 0x0000000000038010, 0x00000000000007ff);
+	convert(0x0000000000030f70, 0x0000000000000000, 0x0000000022001077);
+	convert(0x0000000000030fa0, 0x0000000000000000, 0x000000000003f4a8);
+	convert(0x0000000000030ff0, 0x0000000000310120, 0x0000000000000000);
+	convert(0x0000000000031000, 0xffffffffffffffff, 0xffffffff00000002);
+	convert(0x0000000000031010, 0x000000000000000e, 0x0000000000000000);
+	convert(0x0000000000031020, 0x0000000000038088, 0x0000000000000000);
+	convert(0x00000000000310c0, 0x0000000002010205, 0x00000000d0020000);
+	convert(0x00000000000310d0, 0xffffffffffffffff, 0x0000000f0000000f);
+	convert(0x00000000000310e0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000310f0, 0x00000000000380b8, 0x00000000000007ff);
+	convert(0x0000000000031120, 0x0000000022001077, 0x00000000000310a9);
+	convert(0x0000000000031130, 0x00000000580211c1, 0x000000008009104c);
+	convert(0x0000000000031140, 0x0000000000000000, 0x000000000003f4c0);
+	convert(0x0000000000031190, 0x0000000000310120, 0x0000000000000000);
+	convert(0x00000000000311a0, 0xffffffffffffffff, 0xffffffff00000003);
+	convert(0x00000000000311b0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000311c0, 0x0000000000038130, 0x0000000000000000);
+	convert(0x0000000000031260, 0x0000000000110106, 0x0000000000000000);
+	convert(0x0000000000031270, 0xffffffffffffffff, 0xffffffff00000004);
+	convert(0x0000000000031280, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000312a0, 0x00000000ff110013, 0x0000000000000000);
+	convert(0x00000000000312b0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x00000000000312c0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000312e0, 0x0000000000110012, 0x0000000000000000);
+	convert(0x00000000000312f0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000031300, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031310, 0x0000000000038160, 0x0000000000000000);
+	convert(0x0000000000031330, 0x00000000ff310122, 0x0000000000000000);
+	convert(0x0000000000031340, 0xffffffffffffffff, 0xffffffff00000005);
+	convert(0x0000000000031350, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031360, 0x0000000000038190, 0x0000000000000000);
+	convert(0x0000000000031400, 0x0000000000310121, 0x0000000000000000);
+	convert(0x0000000000031400, 0x0000000000310121, 0x0000000000000000);
+	convert(0x0000000000031410, 0xffffffffffffffff, 0xffffffff00000006);
+	convert(0x0000000000031420, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031430, 0x00000000000381c0, 0x0000000000000000);
+	convert(0x00000000000314d0, 0x00000000ff010201, 0x0000000000000000);
+	convert(0x00000000000314e0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000031500, 0x00000000000381f0, 0x000030430000ffff);
+	convert(0x0000000000031510, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x00000000000315a0, 0x00000020ff000201, 0x0000000000000000);
+	convert(0x00000000000315b0, 0xffffffffffffffff, 0xffffffff00000001);
+	convert(0x00000000000315d0, 0x0000000000038240, 0x00003f3f0000ffff);
+	convert(0x00000000000315e0, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x0000000000031670, 0x00000000ff010201, 0x0000000000000000);
+	convert(0x0000000000031680, 0xffffffffffffffff, 0x0000000100000002);
+	convert(0x00000000000316a0, 0x0000000000038290, 0x000030430000ffff);
+	convert(0x00000000000316b0, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x0000000000031740, 0x00000020ff000201, 0x0000000000000000);
+	convert(0x0000000000031750, 0xffffffffffffffff, 0x0000000500000003);
+	convert(0x0000000000031770, 0x00000000000382e0, 0x00003f3f0000ffff);
+	convert(0x0000000000031780, 0x000000000000ffff, 0x0000000000000000);
+
+	/*
+	 * GDA initialization - mankato
+	 */
+	convert(0x8000000000002400, 0x0000000258464552, 0x000000000ead0000);
+	convert(0x8000000000002480, 0xffffffff00010000, 0xffffffffffffffff);
+	convert(0x8000000000002490, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024a0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024b0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024c0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024d0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024e0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024f0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002500, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002510, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002520, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002530, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002540, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002550, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002560, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002570, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002580, 0x000000000000ffff, 0x0000000000000000);
+	
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/main.c linux/arch/ia64/sn/fakeprom/main.c
--- linux.orig/arch/ia64/sn/fakeprom/main.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/main.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,125 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/bitops.h>
+
+extern void klgraph_init(void);
+void bedrock_init(int);
+void synergy_init(int, int);
+void sys_fw_init (const char *args, int arglen, int bsp);
+
+volatile int	bootmaster=0;		/* Used to pick bootmaster */
+volatile int	nasidmaster[128]={0};	/* Used to pick node/synergy masters */
+int		init_done=0;
+extern int	bsp_lid;
+
+#define get_bit(b,p)	(((*p)>>(b))&1)
+
+int
+fmain(int lid, int bsp) {
+	int	syn, nasid, cpu;
+
+	/*
+	 * First lets figure out who we are. This is done from the
+	 * LID passed to us.
+	 */
+
+#ifdef CONFIG_IA64_SGI_SN1
+	nasid = (lid>>24);
+	syn = (lid>>17)&1;
+	cpu = (lid>>16)&1;
+
+	/*
+	 * Now pick a synergy master to initialize synergy registers.
+	 */
+	if (test_and_set_bit(syn, &nasidmaster[nasid]) == 0) {
+		synergy_init(nasid, syn);
+		test_and_set_bit(syn+2, &nasidmaster[nasid]);
+	} else
+		while (get_bit(syn+2, &nasidmaster[nasid]) == 0);
+#else
+	nasid = (lid>>16)&0xfff;
+	cpu = (lid>>28)&3;
+	syn = 0;
+#endif
+	
+	/*
+	 * Now pick a nasid master to initialize Bedrock registers.
+	 */
+	if (test_and_set_bit(8, &nasidmaster[nasid]) == 0) {
+		bedrock_init(nasid);
+		test_and_set_bit(9, &nasidmaster[nasid]);
+	} else
+		while (get_bit(9, &nasidmaster[nasid]) == 0);
+	
+
+	/*
+	 * Now pick a BSP & finish init.
+	 */
+	if (test_and_set_bit(0, &bootmaster) == 0) {
+		sys_fw_init(0, 0, bsp);
+		test_and_set_bit(1, &bootmaster);
+	} else
+		while (get_bit(1, &bootmaster) == 0);
+
+	return (lid == bsp_lid);
+}
+
+
+void
+bedrock_init(int nasid)
+{
+	nasid = nasid;		/* to quiet gcc */
+#if 0
+	/*
+	 * Undef if you need fprom to generate a 1 node klgraph
+	 * information .. only works for 1 node for nasid 0.
+	 */
+	klgraph_init();
+#endif
+}
+
+
+void
+synergy_init(int nasid, int syn)
+{
+	long	*base;
+	long	off;
+
+	/*
+	 * Enable all FSB flashed interrupts.
+	 * ZZZ - I'd really like defines for this......
+	 */
+	base = (long*)0x80000e0000000000LL;		/* base of synergy regs */
+	for (off = 0x2a0; off < 0x2e0; off+=8)		/* offset for VEC_MASK_{0-3}_A/B */
+		*(base+off/8) = -1LL;
+
+	/*
+	 * Set the NASID in the FSB_CONFIG register.
+	 */
+	base = (long*)0x80000e0000000450LL;
+	*base = (long)((nasid<<16)|(syn<<9));
+}
+
+
+/* Why isnt there a bcopy/memcpy in lib64.a */
+
+void* 
+memcpy(void * dest, const void *src, size_t count)
+{
+	char *s, *se, *d;
+
+	for(d=dest, s=(char*)src, se=s+count; s<se; s++, d++)
+		*d = *s;
+	return dest;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fakeprom/runsim linux/arch/ia64/sn/fakeprom/runsim
--- linux.orig/arch/ia64/sn/fakeprom/runsim	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/fakeprom/runsim	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,387 @@
+#!/bin/sh
+
+# Script for running PROMs and LINUX kernwls on medusa. 
+# Type "sim -H" for instructions.
+
+MEDUSA=${MEDUSA:-/home/rickc/official_medusa/medusa}
+
+# ------------------ err -----------------------
+err() {
+	echo "ERROR - $1"
+	exit 1
+}
+
+# ----------------  help ----------------------
+help() {
+cat <<END
+Script for running a PROM or LINUX kernel under medusa.
+This script creates a control file, creates links to the appropriate
+linux/prom files, and/or calls medusa to make simulation runs.
+
+Usage:  
+   Initial setup:
+   	sim [-c <config_file>] <-p> | <-k>  [<work_dir>]
+		-p	Create PROM control file & links
+		-k	Create LINUX control file & links
+		-c<cf>	Control file name				[Default: cf]
+		<work_dir> Path to directory that contains the linux or PROM files.
+		    The directory can be any of the following:
+		       (linux simulations)
+		       		worktree
+				worktree/linux
+				any directory with vmlinux, vmlinux.sym & fprom files
+			(prom simulations)
+				worktree
+				worktree/stand/arcs/IP37prom/dev
+				any directory with fw.bin & fw.sim files
+
+    Simulations:
+	sim  [-X <n>] [-o <output>] [-M] [<config_file>]
+		-c<cf>	Control file name				[Default: cf]
+		-M	Pipe output thru fmtmedusa
+		-o	Output filename (copy of all commands/output)	[Default: simout]
+		-X	Specifies number of instructions to execute	[Default: 0]
+			(Used only in auto test mode - not described here)
+
+Examples:
+	sim -p <promtree>	# create control file (cf) & links for prom simulations
+	sim -k <linuxtree>	# create control file (cf) & links for linux simulations
+	sim -p -c cfprom	# create a prom control file (cfprom) only. No links are made.
+
+	sim			# run medusa using previously created links &
+				#   control file (cf).
+END
+exit 1
+}
+
+# ----------------------- create control file header --------------------
+create_cf_header() {
+cat <<END >>$CF
+#
+# Template for a control file for running linux kernels under medusa. 
+# You probably want to make mods here but this is a good starting point.
+#
+
+# Preferences
+setenv cpu_stepping A
+setenv exceptionPrint off
+setenv interrupt_messages off
+setenv lastPCsize 100000
+setenv low_power_mode on
+setenv partialIntelChipSet on
+setenv printIntelMessages off
+setenv prom_write_action halt
+setenv prom_write_messages on
+setenv step_quantum 100
+setenv swizzling on
+setenv tsconsole on
+setenv uart_echo on
+symbols on
+
+# IDE disk params
+setenv diskCylinders 611
+setenv bootDrive C
+setenv diskHeads 16
+setenv diskPath idedisk
+setenv diskPresent 1
+setenv diskSpt 63
+
+# Hardware config
+setenv coherency_type nasid
+setenv cpu_cache_type default
+setenv synergy_cache_type syn_cac_64m_8w
+setenv l4_uc_snoop off
+
+# Numalink config
+setenv route_enable on
+setenv network_type router		# Select [xbar|router]
+setenv network_warning 0xff
+
+END
+}
+
+
+# ------------------ create control file entries for linux simulations -------------
+create_cf_linux() {
+cat <<END >>$CF
+# Kernel specific options
+setenv calias_size 0
+setenv mca_on_memory_failure off
+setenv LOADPC 0x00100000		# FPROM load address/entry point (8 digits!)
+setenv symbol_table vmlinux.sym
+load fprom
+load vmlinux
+
+# Useful breakpoints to always have set. Add more if desired.
+break 0xe000000000505e00	all	# dispatch_to_fault_handler
+break panic			all	# stop on panic
+break die_if_kernel		all	# may as well stop
+
+END
+}
+
+# ------------------ create control file entries for prom simulations ---------------
+create_cf_prom() {
+	SYM2=""
+	ADDR="0x80000000ff800000"
+	[ "$EMBEDDED_LINUX" != "0" ] || SYM2="setenv symbol_table2 vmlinux.sym"
+	[ "$SIZE" = "8MB" ] || ADDR="0x80000000ffc00000"
+	cat <<END >>$CF
+# PROM specific options
+setenv mca_on_memory_failure on
+setenv LOADPC 0x80000000ffffffb0
+setenv promFile fw.bin
+setenv promAddr $ADDR
+setenv symbol_table fw.sym
+$SYM2
+
+# Useful breakpoints to always have set. Add more if desired.
+break ivt_gexx 		all
+break ivt_brk		all
+break PROM_Panic_Spin	all
+break PROM_Panic	all
+break PROM_C_Panic	all
+break fled_die		all
+break ResetNow		all
+break zzzbkpt		all
+
+END
+}
+
+
+# ------------------ create control file entries for memory configuration -------------
+create_cf_memory() {
+cat <<END >>$CF
+# CPU/Memory map format:
+#	setenv nodeN_memory_config 0xBSBSBSBS
+#		B=banksize (0=unused, 1=64M, 2=128M, .., 5-1G, c=8M, d=16M, e=32M)
+#		S=bank enable (0=both disable, 3=both enable, 2=bank1 enable, 1=bank0 enable)
+#		  rightmost digits are for bank 0, the lowest address.
+#	setenv nodeN_nasid <nasid>
+#		specifies the NASID for the node. This is used ONLY if booting the kernel.
+#		On PROM configurations, set to 0 - PROM will change it later.
+#	setenv nodeN_cpu_config <cpu_mask>
+#		Set bit number N to 1 to enable cpu N. Ex., a value of 5 enables cpu 0 & 2.
+#
+# Repeat the above 3 commands for each node.
+#
+# For kernel, default to 32MB. Although this is not a valid hardware configuration,
+# it runs faster on medusa. For PROM, 64MB is smallest allowed value.
+
+setenv node0_cpu_config		0x1	# Enable only cpu 0 on the node
+END
+
+if [ $LINUX -eq 1 ] ; then
+cat <<END >>$CF
+setenv node0_nasid		0	# cnode 0 has NASID 0
+setenv node0_memory_config 	0xe1	# 32MB
+END
+else
+cat <<END >>$CF
+setenv node0_memory_config 	0x31	# 256MB
+END
+fi
+}
+
+# -------------------- set links to linux files -------------------------
+set_linux_links() {
+	if [ -d $D/linux/arch ] ; then
+		D=$D/linux
+	elif [ -d $D/arch -o -e vmlinux.sym -o -e $D/vmlinux ] ; then
+		D=$D
+	else
+		err "cant determine directory for linux binaries"
+	fi
+	rm -rf vmlinux vmlinux.sym fprom
+	ln -s $D/vmlinux vmlinux
+	if [ -f $D/vmlinux.sym ] ; then
+		ln -s $D/vmlinux.sym vmlinux.sym
+	elif  [ -f $D/System.map ] ; then
+		ln -s $D/System.map vmlinux.sym
+	fi
+	if [ -d $D/arch ] ; then
+		ln -s $D/arch/ia64/sn/fprom/fprom fprom
+	else
+		ln -s $D/fprom fprom
+	fi
+	echo "  .. Created links to linux files"	
+}
+
+# -------------------- set links to prom files -------------------------
+set_prom_links() {
+	if [ -d $D/stand ] ; then
+		D=$D/stand/arcs/IP37prom/dev
+	elif [ -d $D/sal ] ; then
+		D=$D
+	else
+		err "cant determine directory for PROM binaries"
+	fi
+	SETUP="/tmp/tmp.$$"
+	rm -r -f $SETUP
+	sed 's/export/setenv/' < $D/../../../../.setup | sed 's/=/ /' >$SETUP
+	egrep -q '^ *setenv *PROMSIZE *8MB|^ *export' $SETUP
+	if [ $? -eq 0 ] ; then
+		SIZE="8MB"
+	else
+		SIZE="4MB"
+	fi
+	grep -q '^ *setenv *LAUNCH_VMLINUX' $SETUP
+	EMBEDDED_LINUX=$?
+	PRODUCT=`grep '^ *setenv *PRODUCT' $SETUP | cut -d" " -f3`
+	rm -f fw.bin fw.map fw.sym vmlinux vmlinux.sym fprom $SETUP
+	SDIR="${PRODUCT}${SIZE}.O"
+	BIN="${PRODUCT}ip37prom${SIZE}"
+	ln -s $D/$SDIR/$BIN.bin fw.bin
+	ln -s $D/$SDIR/$BIN.map fw.map
+	ln -s $D/$SDIR/$BIN.sym fw.sym
+	echo "  .. Created links to $SIZE prom files"
+	if [ $EMBEDDED_LINUX -eq 0 ] ; then
+		ln -s $D/linux/vmlinux vmlinux
+		ln -s $D/linux/vmlinux.sym vmlinux.sym
+		if [ -d linux/arch ] ; then
+			ln -s $D/linux/arch/ia64/sn/fprom/fprom fprom
+		else
+			ln -s $D/linux/fprom fprom
+		fi
+		echo "  .. Created links to embedded linux files in prom tree"
+	fi
+}
+
+# --------------- start of shell script --------------------------------
+OUT="simout"
+FMTMED=0
+STEPCNT=0
+PROM=0
+LINUX=0
+NCF="cf"
+while getopts "HMX:c:o:pk" c ; do
+        case ${c} in
+                H) help;;
+		M) FMTMED=1;;
+		X) STEPCNT=${OPTARG};;
+		c) NCF=${OPTARG};;
+		k) PROM=0;LINUX=1;;
+		p) PROM=1;LINUX=0;;
+		o) OUT=${OPTARG};;
+                \?) exit 1;;
+        esac
+done
+shift `expr ${OPTIND} - 1`
+
+# Check if command is for creating control file and/or links to images.
+if [ $PROM -eq 1 -o $LINUX -eq 1 ] ; then
+	CF=$NCF
+	[ ! -f $CF ] || err "wont overwrite an existing control file ($CF)"
+	if [ $# -gt 0 ] ; then
+		D=$1
+		[ -d $D ] || err "cannot find directory $D"
+		[ $PROM -eq 0 ]  || set_prom_links
+		[ $LINUX -eq 0 ] || set_linux_links
+	fi
+	create_cf_header
+	[ $PROM -eq 0 ]  || create_cf_prom
+	[ $LINUX -eq 0 ] || create_cf_linux
+	[ ! -f ../idedisk ] || ln -s ../idedisk .
+	create_cf_memory
+	echo "  .. Basic control file created (in $CF). You might want to edit"
+	echo "     this file (at least, look at it)."
+	exit 0
+fi
+
+# Verify that the control file exists
+CF=${1:-$NCF}
+[ -f $CF ] || err "No control file exists. For help, type: $0 -H"
+
+# Build the .cf files from the user control file. The .cf file is
+# identical except that the actual start & load addresses are inserted
+# into the file. In addition, the FPROM commands for configuring memory
+# and LIDs are generated. 
+
+rm -f .cf .cf1 .cf2
+awk '
+function strtonum(n) {
+	 if (substr(n,1,2) != "0x")
+	 	return int(n)
+	 n = substr(n,3)
+	 r=0
+	 while (length(n) > 0) {
+	 	r = r*16+(index("0123456789abcdef", substr(n,1,1))-1)
+		n = substr(n,2)
+	 }
+	 return r
+	}
+/^#/   	{next}
+/^$/	{next}
+/^setenv *LOADPC/               {loadpc = $3; next}
+/^setenv *node.._cpu_config/	{n=int(substr($2,5,2)); cpuconf[n] = strtonum($3); print; next}
+/^setenv *node.._memory_config/	{n=int(substr($2,5,2)); memconf[n] = strtonum($3); print; next}
+/^setenv *node.._nasid/		{n=int(substr($2,5,2)); nasid[n] = strtonum($3); print; next}
+/^setenv *node._cpu_config/	{n=int(substr($2,5,1)); cpuconf[n] = strtonum($3); print; next}
+/^setenv *node._memory_config/	{n=int(substr($2,5,1)); memconf[n] = strtonum($3); print; next}
+/^setenv *node._nasid/		{n=int(substr($2,5,1)); nasid[n] = strtonum($3); print; next}
+		{print}
+END	{
+	 # Generate the memmap info that starts at the beginning of
+	 # the node the kernel was loaded on.
+	 loadnasid = nasid[0]
+	 cnode = 0
+	 for (i=0; i<128; i++) {
+		if (memconf[i] != "") {
+			printf "sm 0x%x%08x 0x%x%04x%04x\n", 
+				2*loadnasid, 8*cnodes+8, memconf[i], cpuconf[i], nasid[i]
+			cnodes++
+			cpus += substr("0112122312232334", cpuconf[i]+1,1)
+		}
+	 }
+	 printf "sm 0x%x00000000 0x%x%08x\n", 2*loadnasid, cnodes, cpus
+	 printf "setenv number_of_nodes %d\n", cnodes
+
+	 # Now set the starting PC for each cpu.
+	 cnode = 0
+	 lowcpu=-1
+	 for (i=0; i<128; i++) {
+		if (memconf[i] != "") {
+			printf "setnode %d\n", cnode
+			conf = cpuconf[i]
+			for (j=0; j<4; j++) {
+				if (conf != int(conf/2)*2) {
+	 				printf "setcpu %d\n", j
+					if (length(loadpc) == 18)
+						printf "sr pc %s\n", loadpc
+					else
+						printf "sr pc 0x%x%s\n", 2*loadnasid, substr(loadpc,3)
+					if (lowcpu == -1)
+						lowcpu = j
+				}
+				conf = int(conf/2)
+			}
+			cnode++
+		}
+	 }
+	 printf "setnode 0\n"
+	 printf "setcpu %d\n", lowcpu
+	}
+' <$CF >.cf
+
+# Now build the .cf1 & .cf2 control files.
+CF2_LINES="^sm |^break |^run |^si |^quit |^symbols "
+egrep  "$CF2_LINES" .cf >.cf2
+egrep -v "$CF2_LINES" .cf >.cf1
+if [ $STEPCNT -ne 0 ] ; then
+	echo "s $STEPCNT" >>.cf2
+	echo "lastpc 1000" >>.cf2
+	echo "q" >>.cf2
+fi
+if [ -f vmlinux.sym ] ; then
+	awk '/ _start$/ {print "sr g 9 0x" $3}' < vmlinux.sym >> .cf2
+fi
+echo "script-on $OUT" >>.cf2
+
+# Now start medusa....
+if [ $FMTMED -ne 0 ] ; then
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 |  fmtmedusa
+elif [ $STEPCNT -eq 0 ] ; then
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 
+else
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 2>&1 
+fi
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/Makefile linux/arch/ia64/sn/fprom/Makefile
--- linux.orig/arch/ia64/sn/fprom/Makefile	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/ia64/sn/fprom/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,33 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2000 Silicon Graphics, Inc.
-# Copyright (C) Jack Steiner (steiner@sgi.com)
-#
-
-TOPDIR=../../../..
-HPATH           = $(TOPDIR)/include
-
-LIB     = ../../lib/lib.a
-
-OBJ=fpromasm.o main.o  fw-emu.o fpmem.o
-obj-y=fprom
-
-fprom: $(OBJ)
-	$(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB)
-
-comma	:= ,
-
-.S.o:
-	$(CC)  -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
-.c.o:
-	$(CC)  $(CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_KERNEL) -c -o $*.o $<
-
-clean:
-	rm -f *.o fprom
-
-
-include $(TOPDIR)/Rules.make
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/README linux/arch/ia64/sn/fprom/README
--- linux.orig/arch/ia64/sn/fprom/README	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/fprom/README	1970-01-01 00:00:00.000000000 +0000
@@ -1,85 +0,0 @@
-This directory contains the files required to build
-the fake PROM image that is currently being used to
-boot IA64 kernels running under the SGI Medusa kernel.
-
-The FPROM currently provides the following functions:
-
-	- PAL emulation for all PAL calls we've made so far.
-	- SAL emulation for all SAL calls we've made so far.
-	- EFI emulation for all EFI calls we've made so far.
-	- builds the "ia64_bootparam" structure that is
-	  passed to the kernel from SAL. This structure 
-	  shows the cpu & memory configurations.
-	- supports medusa boottime options for changing
-	  the number of cpus present
-	- supports medusa boottime options for changing
-	  the memory configuration.
-
-
-
-At some point, this fake PROM will be replaced by the
-real PROM.
-
-
-
-
-To build a fake PROM, cd to this directory & type:
-
-	make
-
-This will (or should) build a fake PROM named "fprom".
-
-
-
-
-Use this fprom image when booting the Medusa simulator. The
-control file used to boot Medusa should include the 
-following lines:
-
-	load fprom
-	load vmlinux
-	sr pc 0x100000
-	sr g 9 <address of kernel _start function> #(currently 0xe000000000520000)
-
-NOTE: There is a script "runsim" in this directory that can be used to
-simplify setting up an environment for running under Medusa.
-
-
-
-
-The following parameters may be passed to the fake PROM to
-control the PAL/SAL/EFI parameters passed to the kernel:
-
-	GR[8] = # of cpus
-	GR[9] = address of primary entry point into the kernel
-	GR[20] = memory configuration for node 0
-	GR[21] = memory configuration for node 1
-	GR[22] = memory configuration for node 2
-	GR[23] = memory configuration for node 3
-
-
-Registers GR[20] - GR[23] contain information to specify the
-amount of memory present on nodes 0-3.
-
-  - if nothing is specified (all registers are 0), the configuration
-    defaults to 8 MB on node 0.
-
-  - a mem config entry for node N is passed in GR[20+N]
-
-  - a mem config entry consists of 8 hex digits. Each digit gives the
-    amount of physical memory available on the node starting at
-    1GB*<dn>, where dn is the digit number. The amount of memory
-    is 8MB*2**<d>. (If <d> = 0, the memory size is 0).
-
-    SN1 doesnt support dimms this small but small memory systems 
-    boot faster on Medusa.
-
-
-
-An example helps a lot. The following specifies that node 0 has
-physical memory 0 to 8MB and 1GB to 1GB+32MB, and that node 1 has
-64MB starting at address 0 of the node which is 8GB.
-
-      gr[20] = 0x21           # 0 to 8MB, 1GB to 1GB+32MB
-      gr[21] = 0x4            # 8GB to 8GB+64MB
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/fpmem.c linux/arch/ia64/sn/fprom/fpmem.c
--- linux.orig/arch/ia64/sn/fprom/fpmem.c	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/fprom/fpmem.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,200 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-/*
- * FPROM EFI memory descriptor build routines
- *
- * 	- Routines to build the EFI memory descriptor map
- * 	- Should also be usable by the SGI SN1 prom to convert
- * 	  klconfig to efi_memmap
- */
-
-#include <asm/efi.h>
-#include "fpmem.h"
-
-/*
- * args points to a layout in memory like this
- *
- *		32 bit		32 bit
- *
- * 		numnodes	numcpus
- *
- *		16 bit   16 bit		   32 bit
- *		nasid0	cpuconf		membankdesc0
- *		nasid1	cpuconf		membankdesc1
- *			   .
- *			   .
- *			   .
- *			   .
- *			   .
- */
-
-sn_memmap_t	*sn_memmap ;
-sn_config_t	*sn_config ;
-
-/*
- * There is a hole in the node 0 address space. Dont put it
- * in the memory map
- */
-#define NODE0_HOLE_SIZE         (20*MB)
-#define NODE0_HOLE_END          (4UL*GB)
-
-#define	MB			(1024*1024)
-#define GB			(1024*MB)
-#define KERNEL_SIZE		(4*MB)
-#define PROMRESERVED_SIZE	(1*MB)
-#define MD_BANK_SHFT 30
-
-#define TO_NODE(_n, _x)		(((long)_n<<33L) | (long)_x)
-
-/*
- * For SN, this may not take an arg and gets the numnodes from 
- * the prom variable or by traversing klcfg or promcfg
- */
-int
-GetNumNodes(void)
-{
-	return sn_config->nodes;
-}
-
-int
-GetNumCpus(void)
-{
-	return sn_config->cpus;
-}
-
-/* For SN1, get the index th nasid */
-
-int
-GetNasid(int index)
-{
-	return sn_memmap[index].nasid ;
-}
-
-node_memmap_t
-GetMemBankInfo(int index)
-{
-	return sn_memmap[index].node_memmap ;
-}
-
-int
-IsCpuPresent(int cnode, int cpu)
-{
-	return  sn_memmap[cnode].cpuconfig & (1<<cpu);
-}
-
-
-/*
- * Made this into an explicit case statement so that
- * we can assign specific properties to banks like bank0
- * actually disabled etc.
- */
-
-int
-IsBankPresent(int index, node_memmap_t nmemmap)
-{
-	switch (index) {
-		case 0:return nmemmap.b0;
-		case 1:return nmemmap.b1;
-		case 2:return nmemmap.b2;
-		case 3:return nmemmap.b3;
-		case 4:return nmemmap.b4;
-		case 5:return nmemmap.b5;
-		case 6:return nmemmap.b6;
-		case 7:return nmemmap.b7;
-		default:return -1 ;
-	}
-}
-
-int
-GetBankSize(int index, node_memmap_t nmemmap)
-{
-        switch (index) {
-                case 0:
-                case 1:return nmemmap.b01size;
-                case 2:
-                case 3:return nmemmap.b23size;
-                case 4:
-                case 5:return nmemmap.b45size;
-                case 6:
-                case 7:return nmemmap.b67size;
-                default:return -1 ;
-        }
-}
-
-void
-build_mem_desc(efi_memory_desc_t *md, int type, long paddr, long numbytes)
-{
-        md->type = type;
-        md->phys_addr = paddr;
-        md->virt_addr = 0;
-        md->num_pages = numbytes >> 12;
-        md->attribute = EFI_MEMORY_WB;
-}
-
-int
-build_efi_memmap(void *md, int mdsize)
-{
-	int		numnodes = GetNumNodes() ;
-	int		cnode,bank ;
-	int		nasid ;
-	node_memmap_t	membank_info ;
-	int		bsize;
-	int		count = 0 ;
-	long		paddr, hole, numbytes;
-
-
-	for (cnode=0;cnode<numnodes;cnode++) {
-		nasid = GetNasid(cnode) ;
-		membank_info = GetMemBankInfo(cnode) ;
-		for (bank=0;bank<SN1_MAX_BANK_PER_NODE;bank++) {
-			if (IsBankPresent(bank, membank_info)) {
-				bsize = GetBankSize(bank, membank_info) ;
-                                paddr = TO_NODE(nasid, (long)bank<<MD_BANK_SHFT);
-                                numbytes = BankSizeBytes(bsize);
-
-                                /*
-                                 * Check for the node 0 hole. Since banks cant
-                                 * span the hole, we only need to check if the end of
-                                 * the range is the end of the hole.
-                                 */
-                                if (paddr+numbytes == NODE0_HOLE_END)
-                                        numbytes -= NODE0_HOLE_SIZE;
-                                /*
-                                 * UGLY hack - we must skip overr the kernel and
-                                 * PROM runtime services but we dont exactly where it is.
-                                 * So lets just reserve 0-12MB.
-                                 */
-                                if (bank == 0) {
-					hole = (cnode == 0) ? KERNEL_SIZE : PROMRESERVED_SIZE;
-					numbytes -= hole;
-                                        build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
-                                        paddr += hole;
-			        	count++ ;
-                                        md += mdsize;
-                                }
-                                build_mem_desc(md, EFI_CONVENTIONAL_MEMORY, paddr, numbytes);
-
-			        md += mdsize ;
-			        count++ ;
-			}
-		}
-	}
-	return count ;
-}
-
-void
-build_init(unsigned long args)
-{
-	sn_config = (sn_config_t *) (args);	
-	sn_memmap = (sn_memmap_t *)(args + 8) ; /* SN equiv for this is */
-						/* init to klconfig start */
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/fpmem.h linux/arch/ia64/sn/fprom/fpmem.h
--- linux.orig/arch/ia64/sn/fprom/fpmem.h	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/fprom/fpmem.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,35 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#include <asm/sn/mmzone_sn1.h>
-
-typedef struct sn_memmap_s
-{
-	short		nasid ;
-	short		cpuconfig;
-	node_memmap_t 	node_memmap ;
-} sn_memmap_t ;
-
-typedef struct sn_config_s
-{
-	int		cpus;
-	int		nodes;
-	sn_memmap_t	memmap[1];		/* start of array */
-} sn_config_t;
-
-
-extern void build_init(unsigned long);
-extern int build_efi_memmap(void *, int);
-extern int GetNumNodes(void);
-extern int GetNumCpus(void);
-extern int IsCpuPresent(int, int);
-extern int GetNasid(int);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/fprom.lds linux/arch/ia64/sn/fprom/fprom.lds
--- linux.orig/arch/ia64/sn/fprom/fprom.lds	2001-07-02 21:40:14.000000000 +0000
+++ linux/arch/ia64/sn/fprom/fprom.lds	1970-01-01 00:00:00.000000000 +0000
@@ -1,96 +0,0 @@
-
-OUTPUT_FORMAT("elf64-ia64-little")
-OUTPUT_ARCH(ia64)
-ENTRY(_start)
-SECTIONS
-{
-  v = 0x0000000000000000 ;	/* this symbol is here to make debugging with kdb easier... */
-
-  . = (0x000000000000000  + 0x100000) ;
-
-  _text = .;
-  .text : AT(ADDR(.text) - 0x0000000000000000 )
-    {
-	*(__ivt_section)
-	/* these are not really text pages, but the zero page needs to be in a fixed location: */
-	*(__special_page_section)
-	__start_gate_section = .;
-	*(__gate_section)
-	__stop_gate_section = .;
-	*(.text)
-    }
-
-  /* Global data */
-  _data = .;
-
-  .rodata : AT(ADDR(.rodata) - 0x0000000000000000 )
-	{ *(.rodata) *(.rodata.*) }
-  .opd : AT(ADDR(.opd) - 0x0000000000000000 )
-	{ *(.opd) }
-  .data : AT(ADDR(.data) - 0x0000000000000000 )
-	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
-
-  __gp = ALIGN (8) + 0x200000;
-
-  .got : AT(ADDR(.got) - 0x0000000000000000 )
-	{ *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata : AT(ADDR(.sdata) - 0x0000000000000000 )
-	{ *(.sdata) }
-  _edata  =  .;
-  _bss = .;
-  .sbss : AT(ADDR(.sbss) - 0x0000000000000000 )
-	{ *(.sbss) *(.scommon) }
-  .bss : AT(ADDR(.bss) - 0x0000000000000000 )
-	{ *(.bss) *(COMMON) }
-  . = ALIGN(64 / 8);
-  _end = .;
-
-  /* Sections to be discarded */
-  /DISCARD/ : {
-	*(.text.exit)
-	*(.data.exit)
-	}
-
-  /* Stabs debugging sections.  */
-  .stab 0 : { *(.stab) }
-  .stabstr 0 : { *(.stabstr) }
-  .stab.excl 0 : { *(.stab.excl) }
-  .stab.exclstr 0 : { *(.stab.exclstr) }
-  .stab.index 0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* These must appear regardless of  .  */
-  /* Discard them for now since Intel SoftSDV cannot handle them.
-  .comment 0 : { *(.comment) }
-  .note 0 : { *(.note) }
-  */
-  /DISCARD/ : { *(.comment) }
-  /DISCARD/ : { *(.note) }
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/fpromasm.S linux/arch/ia64/sn/fprom/fpromasm.S
--- linux.orig/arch/ia64/sn/fprom/fpromasm.S	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/fprom/fpromasm.S	1970-01-01 00:00:00.000000000 +0000
@@ -1,314 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- *   (Code copied from or=ther files)
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#define __ASSEMBLY__ 1
-#include "asm/processor.h"
-
-/*
- * This file contains additional set up code that is needed to get going on
- * Medusa.  This code should disappear once real hw is available.
- *
- * On entry to this routine, the following register values are assumed:
- *
- *	gr[8]	- BSP cpu
- *	pr[9]	- kernel entry address
- *
- * NOTE:
- *   This FPROM may be loaded/executed at an address different from the
- *   address that it was linked at. The FPROM is linked to run on node 0
- *   at address 0x100000. If the code in loaded into another node, it
- *   must be loaded at offset 0x100000 of the node. In addition, the
- *   FPROM does the following things:
- *		- determine the base address of the node it is loaded on
- *		- add the node base to _gp.
- *		- add the node base to all addresses derived from "movl" 
- *		  instructions. (I couldnt get GPREL addressing to work)
- *		  (maybe newer versions of the tools will support this)
- *		- scan the .got section and add the node base to all
- *		  pointers in this section.
- *		- add the node base to all physical addresses in the
- *		  SAL/PAL/EFI table built by the C code. (This is done
- *		  in the C code - not here)
- *		- add the node base to the TLB entries for vmlinux
- */
-
-#define KERNEL_BASE	0xe000000000000000
-#define PAGESIZE_256M	28
-
-/* 
- * ar.k0 gets set to IOPB_PA value, on 460gx chipset it should 
- * be 0x00000ffffc000000, but on snia we use the (inverse swizzled)
- * IOSPEC_BASE value
- */
-#define IOPB_PA		0x00000a0000000000 /* inv swizzle IOSPEC_BASE */
-
-#define RR_RID		8
-
-
-
-// ====================================================================================	
-        .text
-        .align 16
-	.global _start
-	.proc _start
-_start:
-
-// Setup psr and rse for system init
-	mov		psr.l = r0;;
-	srlz.d;;
-	invala
-	mov		ar.rsc = r0;;
-	loadrs
-	;;
-
-// Set CALIAS size to zero. We dont use it.
-	movl		r24=0x80000a0001000028;;	// BR_PI_CALIAS_SIZE
-	st8 		[r24]=r0
-
-// Isolate node number we are running on.
-	mov		r6 = ip;;
-	shr		r5 = r6,33;;			// r5 = node number
-	shl		r6 = r5,33			// r6 = base memory address of node
-
-// Set & relocate gp.
-	movl		r1= __gp;;			// Add base memory address
-	add 		r1 = r1,r6			// Relocate to boot node
-
-// Lets figure out who we are & put it in the LID register.
-// The BR_PI_SELF_CPU_NUM register gives us a value of 0-3.
-// This identifies the cpu on the node. 
-// Merge the cpu number with the NASID to generate the LID.
-	movl		r24=0x80000a0001000020;;	// BR_PI_SELF_CPU_NUM
-	ld8 		r25=[r24]			// Fetch PI_SELF
-	movl		r27=0x80000a0001600000;;	// Fetch REVID to get local NASID
-	ld8 		r27=[r27];;
-	extr.u		r27=r27,32,8
-	shl 		r26=r25,16;;			// Align local cpu# to lid.eid
-	shl 		r27=r27,24;;			// Align NASID to lid.id
-	or  		r26=r26,r27;;			// build the LID
-	mov 		cr.lid=r26			// Now put in in the LID register
-	
-	movl		r2=FPSR_DEFAULT;;
-	mov 		ar.fpsr=r2
-	movl		sp = bootstacke-16;;
-	add 		sp = sp,r6			// Relocate to boot node			
-
-// Save the NASID that we are loaded on.
-	movl		r2=base_nasid;;			// Save base_nasid for C code
-	add 		r2 = r2,r6;;			// Relocate to boot node
-  	st8 		[r2]=r5				// Uncond st8 - same on all cpus
-
-// Save the kernel entry address. It is passed in r9 on one of
-// the cpus.
-	movl		r2=bsp_entry_pc
-	cmp.ne		p6,p0=r9,r0;;
-	add 		r2 = r2,r6;;			// Relocate to boot node
-(p6)  	st8 		[r2]=r9				// Uncond st8 - same on all cpus
-
-
-// The following can ONLY be done by 1 cpu. Lets set a lock - the
-// cpu that gets it does the initilization. The rest just spin waiting
-// til initilization is complete.
-	movl		r22 = initlock;;
-	add		r22 = r22,r6			// Relocate to boot node
-	mov		r23 = 1;;
-	xchg8		r23 = [r22],r23;;
-	cmp.eq 		p6,p0 = 0,r23
-(p6)	br.cond.spnt.few init
-1:	ld4		r23 = [r22];;
-	cmp.eq		p6,p0 = 1,r23
-(p6)	br.cond.sptk	1b
-	br		initx
-
-// Add base address of node memory to each pointer in the .got section.
-init:	movl		r16 = _GLOBAL_OFFSET_TABLE_;;
-	add		r16 = r16,r6;;			// Relocate to boot node
-1: 	ld8		r17 = [r16];;
-	cmp.eq		p6,p7=0,r17
-(p6)	br.cond.sptk.few.clr 2f;;
-	add		r17 = r17,r6;;			// Relocate to boot node
-	st8		[r16] = r17,8
-	br		1b
-2:
-	mov		r23 = 2;;			// All done, release the spinning cpus
-	st4		[r22] = r23
-initx:
-
-//
-//	I/O-port space base address:
-//
-	movl		r2 = IOPB_PA;;
-	mov		ar.k0 = r2
-
-
-// Now call main & pass it the current LID value.
-	alloc 		r0=ar.pfs,0,0,2,0
-	mov    		r32=r26
-	mov   		r33=r8;;
-	br.call.sptk.few rp=fmain
-	
-// Initialize Region Registers
-//
-	mov		r10 = r0
-	mov		r2 = (13<<2) 
-	mov		r3 = r0;;
-1:	cmp4.gtu	p6,p7 = 7, r3
-	dep		r10 = r3, r10, 61, 3
-	dep		r2 = r3, r2, RR_RID, 4;;
-(p7)	dep		r2 = 0, r2, 0, 1;;
-(p6)	dep		r2 = -1, r2, 0, 1;;
-	mov		rr[r10] = r2
-	add		r3 = 1, r3;;
-	srlz.d;;
-	cmp4.gtu	p6,p0 = 8, r3
-(p6)	br.cond.sptk.few.clr 1b
-
-//
-// Return value indicates if we are the BSP or AP.
-// 	   1 = BSP, 0 = AP
-	mov             cr.tpr=r0;;
-	cmp.eq		p6,p0=r8,r0
-(p6)	br.cond.spnt	slave
-
-//
-// Initialize the protection key registers with only pkr[0] = valid.
-//
-// Should be initialized in accordance with the OS.
-//
-	mov		r2 = 1
-	mov		r3 = r0;;
-	mov		pkr[r3] = r2;;
-	srlz.d;;
-	mov		r2 = r0
-
-1:	add		r3 = r3, r0, 1;;		// increment PKR
-	cmp.gtu		p6, p0 = 16, r3;;
-(p6)	mov		pkr[r3] = r2
-(p6)	br.cond.sptk.few.clr 1b
-
-	mov		ar.rnat = r0			// clear RNAT register
-
-//
-// Setup system address translation for kernel
-//
-// Note: The setup of Kernel Virtual address space can be done by the
-// C code of the boot loader.
-//
-//
-
-#define LINUX_PAGE_OFFSET       0xe000000000000000
-#define ITIR(key, ps)           ((key<<8) | (ps<<2))
-#define ITRGR(ed,ar,ma)         ((ed<<52) | (ar<<9) | (ma<<2) | 0x61)
-
-#define AR_RX                   1                       // RX permission
-#define AR_RW                   4                       // RW permission
-#define MA_WB                   0                       // WRITEBACK memory attribute
-
-#define TLB_PAGESIZE		28			// Use 256MB pages for now.
-	mov		r16=r5
-
-//
-//     text section
-//
-        movl            r2 = LINUX_PAGE_OFFSET;;        // Set up IFA with VPN of linux
-        mov             cr.ifa = r2
-        movl            r3 = ITIR(0,TLB_PAGESIZE);;     // Set ITIR to default pagesize
-        mov             cr.itir = r3
-
-        shl             r4 = r16,33;;                   // physical addr of start of node
-        movl            r5 = ITRGR(1,AR_RX,MA_WB);;     // TLB attributes
-        or              r10=r4,r5;;
-
-        itr.i           itr[r0] = r10;;                   // Dropin ITR entry
-	srlz.i;;
-
-//
-//     data section
-//
-        movl            r2 = LINUX_PAGE_OFFSET;;        // Set up IFA with VPN of linux
-        mov             cr.ifa = r2
-        movl            r3 = ITIR(0,TLB_PAGESIZE);;     // Set ITIR to default pagesize
-        mov             cr.itir = r3
-
-        shl             r4 = r16,33;;                   // physical addr of start of node
-        movl            r5 = ITRGR(1,AR_RW,MA_WB);;     // TLB attributes
-        or              r10=r4,r5;;
-
-        itr.d           dtr[r0] = r10;;                 // Dropin DTR entry
-	srlz.d;;
-
-
-
-
-//
-// Turn on address translation, interrupt collection, psr.ed, protection key.
-// Interrupts (PSR.i) are still off here.
-//
-
-	movl		r3 = (	IA64_PSR_BN | \
-				IA64_PSR_AC | \
-				IA64_PSR_IT | \
-				IA64_PSR_DB | \
-				IA64_PSR_DA | \
-				IA64_PSR_RT | \
-				IA64_PSR_DT | \
-				IA64_PSR_IC   \
-			     )
-	;;
-	mov		cr.ipsr = r3
-
-//
-// Go to kernel C startup routines
-//	Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
-//	This is the only way to set them.
-
-	movl		r2=bsp_entry_pc;;
-	add 		r2 = r2,r6;;			// Relocate to boot node
-	ld8		r2=[r2];;
-	mov		cr.iip = r2
-	srlz.d;;
-	rfi;;
-	.endp		_start
-
-// Slave processors come here to spin til they get an interrupt. Then they launch themselves to
-// the place ap_entry points. No initialization is necessary - the kernel makes no
-// assumptions about state on this entry.
-//	Note: should verify that the interrupt we got was really the ap_wakeup
-//	      interrupt but this should not be an issue on medusa
-slave:
-	nop.i		0x8beef				// Medusa - put cpu to sleep til interrupt occurs
-	mov		r8=cr.irr0;;			// Check for interrupt pending.
-	cmp.eq		p6,p0=r8,r0
-(p6)	br.cond.sptk	slave;;
-
-	mov		r8=cr.ivr;;			// Got one. Must read ivr to accept it
-	srlz.d;;
-	mov		cr.eoi=r0;;			// must write eoi to clear
-	movl		r8=ap_entry;;			// now jump to kernel entry
-	add 		r8 = r8,r6;;			// Relocate to boot node
-	ld8		r9=[r8],8;;
-	ld8		r1=[r8]
-	mov		b0=r9;;
-	br		b0
-
-// Here is the kernel stack used for the fake PROM
-	.bss
-	.align		16384
-bootstack:
-	.skip		16384
-bootstacke:
-initlock:
-	data4
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/fw-emu.c linux/arch/ia64/sn/fprom/fw-emu.c
--- linux.orig/arch/ia64/sn/fprom/fw-emu.c	2001-07-31 17:30:09.000000000 +0000
+++ linux/arch/ia64/sn/fprom/fw-emu.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,524 +0,0 @@
-/*
- * PAL & SAL emulation.
- *
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-#include <asm/efi.h>
-#include <asm/pal.h>
-#include <asm/sal.h>
-#include <asm/processor.h>
-#include <asm/acpi-ext.h>
-#include "fpmem.h"
-
-#define MB	(1024*1024UL)
-#define GB	(MB*1024UL)
-
-#define FPROM_BUG()		do {while (1);} while (0)
-#define MAX_NODES		128
-#define MAX_LSAPICS		512
-#define MAX_CPUS		512
-#define MAX_CPUS_NODE		4
-#define CPUS_PER_NODE		4
-#define CPUS_PER_FSB		2
-#define CPUS_PER_FSB_MASK	(CPUS_PER_FSB-1)
-
-#define NUM_EFI_DESCS		2
-
-typedef union ia64_nasid_va {
-        struct {
-                unsigned long off   : 33;       /* intra-region offset */
-		unsigned long nasid :  7;	/* NASID */
-		unsigned long off2  : 21;	/* fill */
-                unsigned long reg   :  3;       /* region number */
-        } f;
-        unsigned long l;
-        void *p;
-} ia64_nasid_va;
-
-typedef struct {
-	unsigned long	pc;
-	unsigned long	gp;
-} func_ptr_t;
- 
-#define IS_VIRTUAL_MODE() 	 ({struct ia64_psr psr; asm("mov %0=psr" : "=r"(psr)); psr.dt;})
-#define ADDR_OF(p)		(IS_VIRTUAL_MODE() ? ((void*)((long)(p)+PAGE_OFFSET)) : ((void*) (p)))
-#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.l;})
-
-/*
- * The following variables are passed thru registersfrom the configuration file and
- * are set via the _start function.
- */
-long		base_nasid;
-long		num_cpus;
-long		bsp_entry_pc=0;
-long		num_nodes;
-long		app_entry_pc;
-int		bsp_lid;
-func_ptr_t	ap_entry;
-
-
-static efi_runtime_services_t    *efi_runtime_p;
-static char fw_mem[(  sizeof(efi_system_table_t)
-		    + sizeof(efi_runtime_services_t)
-		    + NUM_EFI_DESCS*sizeof(efi_config_table_t)
-		    + sizeof(struct ia64_sal_systab)
-		    + sizeof(struct ia64_sal_desc_entry_point)
-		    + sizeof(struct ia64_sal_desc_ap_wakeup)
-		    + sizeof(acpi_rsdp_t)
-		    + sizeof(acpi_rsdt_t)
-		    + sizeof(acpi_sapic_t)
-		    + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t))
-		    + (1+8*MAX_NODES)*(sizeof(efi_memory_desc_t))
-		    + sizeof(ia64_sal_desc_ptc_t) +
-		    + MAX_NODES*sizeof(ia64_sal_ptc_domain_info_t) +
-		    + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) +
-		    + 1024)] __attribute__ ((aligned (8)));
-
-/*
- * Very ugly, but we need this in the simulator only.  Once we run on
- * real hw, this can all go away.
- */
-extern void pal_emulator_static (void);
-
-asm ("
-	.text
-	.proc pal_emulator_static
-pal_emulator_static:
-	mov r8=-1;;
-	cmp.eq p6,p7=6,r28;;		/* PAL_PTCE_INFO */
-(p7)	br.cond.sptk.few 1f
-	;;
-	mov r8=0			/* status = 0 */
-	movl r9=0x500000000		/* tc.base */
-	movl r10=0x0000000200000003	/* count[0], count[1] */
-	movl r11=0x1000000000002000	/* stride[0], stride[1] */
-	br.cond.sptk.few rp
-
-1:	cmp.eq p6,p7=14,r28;;		/* PAL_FREQ_RATIOS */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0			/* status = 0 */
-	movl r9 =0x100000064		/* proc_ratio (1/100) */
-	movl r10=0x100000100		/* bus_ratio<<32 (1/256) */
-	movl r11=0x10000000a		/* itc_ratio<<32 (1/100) */
-
-1:	cmp.eq p6,p7=22,r28;;		/* PAL_MC_DRAIN */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0
-	br.cond.sptk.few rp
-
-1:	cmp.eq p6,p7=23,r28;;		/* PAL_MC_EXPECTED */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0
-	br.cond.sptk.few rp
-
-1:	br.cond.sptk.few rp
-	.endp pal_emulator_static\n");
-
-
-static efi_status_t
-efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
-{
-	if (tm) {
-		memset(tm, 0, sizeof(*tm));
-		tm->year = 2000;
-		tm->month = 2;
-		tm->day = 13;
-		tm->hour = 10;
-		tm->minute = 11;
-		tm->second = 12;
-	}
-
-	if (tc) {
-		tc->resolution = 10;
-		tc->accuracy = 12;
-		tc->sets_to_zero = 1;
-	}
-
-	return EFI_SUCCESS;
-}
-
-static void
-efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
-{
-	while(1);	/* Is there a pseudo-op to stop medusa */
-}
-
-static efi_status_t
-efi_success (void)
-{
-	return EFI_SUCCESS;
-}
-
-static efi_status_t
-efi_unimplemented (void)
-{
-	return EFI_UNSUPPORTED;
-}
-
-static long
-sal_emulator (long index, unsigned long in1, unsigned long in2,
-	      unsigned long in3, unsigned long in4, unsigned long in5,
-	      unsigned long in6, unsigned long in7)
-{
-	register long r9 asm ("r9") = 0;
-	register long r10 asm ("r10") = 0;
-	register long r11 asm ("r11") = 0;
-	long status;
-
-	/*
-	 * Don't do a "switch" here since that gives us code that
-	 * isn't self-relocatable.
-	 */
-	status = 0;
-	if (index == SAL_FREQ_BASE) {
-		switch (in1) {
-		      case SAL_FREQ_BASE_PLATFORM:
-			r9 = 500000000;
-			break;
-
-		      case SAL_FREQ_BASE_INTERVAL_TIMER:
-			/*
-			 * Is this supposed to be the cr.itc frequency
-			 * or something platform specific?  The SAL
-			 * doc ain't exactly clear on this...
-			 */
-			r9 = 700000000;
-			break;
-
-		      case SAL_FREQ_BASE_REALTIME_CLOCK:
-			r9 = 1;
-			break;
-
-		      default:
-			status = -1;
-			break;
-		}
-	} else if (index == SAL_SET_VECTORS) {
-		if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
-			func_ptr_t	*fp;
-			fp = ADDR_OF(&ap_entry);
-			fp->pc = in2;
-			fp->gp = in3;
-		} else {
-			status = -1;
-		}
-		;
-	} else if (index == SAL_GET_STATE_INFO) {
-		;
-	} else if (index == SAL_GET_STATE_INFO_SIZE) {
-		;
-	} else if (index == SAL_CLEAR_STATE_INFO) {
-		;
-	} else if (index == SAL_MC_RENDEZ) {
-		;
-	} else if (index == SAL_MC_SET_PARAMS) {
-		;
-	} else if (index == SAL_CACHE_FLUSH) {
-		;
-	} else if (index == SAL_CACHE_INIT) {
-		;
-	} else if (index == SAL_UPDATE_PAL) {
-		;
-	} else {
-		status = -1;
-	}
-	asm volatile ("" :: "r"(r9), "r"(r10), "r"(r11));
-	return status;
-}
-
-
-/*
- * This is here to work around a bug in egcs-1.1.1b that causes the
- * compiler to crash (seems like a bug in the new alias analysis code.
- */
-void *
-id (long addr)
-{
-	return (void *) addr;
-}
-
-
-/*
- * Fix the addresses in a function pointer by adding base node address
- * to pc & gp.
- */
-void
-fix_function_pointer(void *fp)
-{
-	func_ptr_t	*_fp;
-
-	_fp = fp;
-	_fp->pc = __fwtab_pa(base_nasid, _fp->pc);
-	_fp->gp = __fwtab_pa(base_nasid, _fp->gp);
-}
-
-void
-fix_virt_function_pointer(void *fptr)
-{
-        func_ptr_t      *fp;
-
-        fp = fptr;
-        fp->pc = fp->pc | PAGE_OFFSET;
-        fp->gp = fp->gp | PAGE_OFFSET;
-}
-
-
-int
-efi_set_virtual_address_map(void)
-{
-        efi_runtime_services_t            *runtime;
-
-        runtime = efi_runtime_p;
-        fix_virt_function_pointer((void*)runtime->get_time);
-        fix_virt_function_pointer((void*)runtime->set_time);
-        fix_virt_function_pointer((void*)runtime->get_wakeup_time);
-        fix_virt_function_pointer((void*)runtime->set_wakeup_time);
-        fix_virt_function_pointer((void*)runtime->set_virtual_address_map);
-        fix_virt_function_pointer((void*)runtime->get_variable);
-        fix_virt_function_pointer((void*)runtime->get_next_variable);
-        fix_virt_function_pointer((void*)runtime->set_variable);
-        fix_virt_function_pointer((void*)runtime->get_next_high_mono_count);
-        fix_virt_function_pointer((void*)runtime->reset_system);
-        return EFI_SUCCESS;;
-}
-
-
-void
-sys_fw_init (const char *args, int arglen, int bsp)
-{
-	/*
-	 * Use static variables to keep from overflowing the RSE stack
-	 */
-	static efi_system_table_t *efi_systab;
-	static efi_runtime_services_t *efi_runtime;
-	static efi_config_table_t *efi_tables;
-	static ia64_sal_desc_ptc_t *sal_ptc;
-	static ia64_sal_ptc_domain_info_t *sal_ptcdi;
-	static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid;
-	static acpi_rsdp_t *acpi_systab;
-	static acpi_rsdt_t *acpi_rsdt;
-	static acpi_sapic_t *acpi_sapic;
-	static acpi_entry_lsapic_t *acpi_lsapic;
-	static struct ia64_sal_systab *sal_systab;
-	static efi_memory_desc_t *efi_memmap, *md;
-	static unsigned long *pal_desc, *sal_desc;
-	static struct ia64_sal_desc_entry_point *sal_ed;
-	static struct ia64_boot_param *bp;
-	static struct ia64_sal_desc_ap_wakeup *sal_apwake;
-	static unsigned char checksum = 0;
-	static char *cp, *cmd_line, *vendor;
-	static int mdsize, domain, last_domain ;
-	static int cnode, nasid, cpu, num_memmd, cpus_found;
-
-	/*
-	 * Pass the parameter base address to the build_efi_xxx routines.
-	 */
-	build_init(8LL*GB*base_nasid);
-
-	num_nodes = GetNumNodes();
-	num_cpus = GetNumCpus();
-
-
-	memset(fw_mem, 0, sizeof(fw_mem));
-
-	pal_desc = (unsigned long *) &pal_emulator_static;
-	sal_desc = (unsigned long *) &sal_emulator;
-	fix_function_pointer(&pal_emulator_static);
-	fix_function_pointer(&sal_emulator);
-
-	/* Align this to 16 bytes, probably EFI does this  */
-	mdsize = (sizeof(efi_memory_desc_t) + 15) & ~15 ;
-
-	cp = fw_mem;
-	efi_systab  = (void *) cp; cp += sizeof(*efi_systab);
-	efi_runtime_p = efi_runtime = (void *) cp; cp += sizeof(*efi_runtime);
-	efi_tables  = (void *) cp; cp += NUM_EFI_DESCS*sizeof(*efi_tables);
-	sal_systab  = (void *) cp; cp += sizeof(*sal_systab);
-	sal_ed      = (void *) cp; cp += sizeof(*sal_ed);
-	sal_ptc     = (void *) cp; cp += sizeof(*sal_ptc);
-	sal_apwake  = (void *) cp; cp += sizeof(*sal_apwake);
-	acpi_systab = (void *) cp; cp += sizeof(*acpi_systab);
-	acpi_rsdt   = (void *) cp; cp += sizeof(*acpi_rsdt);
-	acpi_sapic  = (void *) cp; cp += sizeof(*acpi_sapic);
-	acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic);
-	vendor 	    = (char *) cp; cp += 32;
-	efi_memmap  = (void *) cp; cp += 8*32*sizeof(*efi_memmap);
-	sal_ptcdi   = (void *) cp; cp += CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi);
-	sal_ptclid  = (void *) cp; cp += ((3+num_cpus)*sizeof(*sal_ptclid)+7)/8*8;
-	cmd_line    = (void *) cp;
-
-	if (args) {
-		if (arglen >= 1024)
-			arglen = 1023;
-		memcpy(cmd_line, args, arglen);
-	} else {
-		arglen = 0;
-	}
-	cmd_line[arglen] = '\0';
-#ifdef BRINGUP
-	/* for now, just bring up bash */
-	strcpy(cmd_line, "init=/bin/bash");
-#else
-	strcpy(cmd_line, "");
-#endif
-
-	memset(efi_systab, 0, sizeof(efi_systab));
-	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
-	efi_systab->hdr.revision  = EFI_SYSTEM_TABLE_REVISION;
-	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
-	efi_systab->fw_vendor = __fwtab_pa(base_nasid, vendor);
-	efi_systab->fw_revision = 1;
-	efi_systab->runtime = __fwtab_pa(base_nasid, efi_runtime);
-	efi_systab->nr_tables = 2;
-	efi_systab->tables = __fwtab_pa(base_nasid, efi_tables);
-	memcpy(vendor, "S\0i\0l\0i\0c\0o\0n\0-\0G\0r\0a\0p\0h\0i\0c\0s\0\0", 32);
-
-	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
-	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
-	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
-	efi_runtime->get_time = __fwtab_pa(base_nasid, &efi_get_time);
-	efi_runtime->set_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_virtual_address_map = __fwtab_pa(base_nasid, &efi_set_virtual_address_map);
-	efi_runtime->get_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_next_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_next_high_mono_count = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->reset_system = __fwtab_pa(base_nasid, &efi_reset_system);
-
-	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
-	efi_tables->table = __fwtab_pa(base_nasid, sal_systab);
-	efi_tables++;
-	efi_tables->guid = ACPI_TABLE_GUID;
-	efi_tables->table = __fwtab_pa(base_nasid, acpi_systab);
-	fix_function_pointer(&efi_unimplemented);
-	fix_function_pointer(&efi_get_time);
-	fix_function_pointer(&efi_success);
-	fix_function_pointer(&efi_reset_system);
-	fix_function_pointer(&efi_set_virtual_address_map);
-
-	/* fill in the ACPI system table: */
-	memcpy(acpi_systab->signature, "RSD PTR ", 8);
-	acpi_systab->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt);
-
-	memcpy(acpi_rsdt->header.signature, "RSDT",4);
-	acpi_rsdt->header.length = sizeof(acpi_rsdt_t);
-	memcpy(acpi_rsdt->header.oem_id, "SGI", 3);
-	memcpy(acpi_rsdt->header.oem_table_id, "SN1", 3);
-	acpi_rsdt->header.oem_revision = 0x00010001;
-	acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic);
-
-	memcpy(acpi_sapic->header.signature, "SPIC ", 4);
-	acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t);
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		nasid = GetNasid(cnode);
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (!IsCpuPresent(cnode, cpu))
-				continue;
-			acpi_lsapic->type = ACPI_ENTRY_LOCAL_SAPIC;
-			acpi_lsapic->length = sizeof(acpi_entry_lsapic_t);
-			acpi_lsapic->acpi_processor_id = cnode*4+cpu;
-			acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
-			acpi_lsapic->eid = cpu;
-			acpi_lsapic->id = nasid;
-			acpi_lsapic++;
-		}
-	}
-
-
-	/* fill in the SAL system table: */
-	memcpy(sal_systab->signature, "SST_", 4);
-	sal_systab->size = sizeof(*sal_systab);
-	sal_systab->sal_rev_minor = 1;
-	sal_systab->sal_rev_major = 0;
-	sal_systab->entry_count = 3;
-
-	strcpy(sal_systab->oem_id, "SGI");
-	strcpy(sal_systab->product_id, "SN1");
-
-	/* fill in an entry point: */	
-	sal_ed->type = SAL_DESC_ENTRY_POINT;
-	sal_ed->pal_proc = __fwtab_pa(base_nasid, pal_desc[0]);
-	sal_ed->sal_proc = __fwtab_pa(base_nasid, sal_desc[0]);
-	sal_ed->gp = __fwtab_pa(base_nasid, sal_desc[1]);
-
-	/* kludge the PTC domain info */
-	sal_ptc->type = SAL_DESC_PTC;
-	sal_ptc->num_domains = 0;
-	sal_ptc->domain_info = __fwtab_pa(base_nasid, sal_ptcdi);
-	cpus_found = 0;
-	last_domain = -1;
-	sal_ptcdi--;
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		nasid = GetNasid(cnode);
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (IsCpuPresent(cnode, cpu)) {
-				domain = cnode*CPUS_PER_NODE + cpu/CPUS_PER_FSB;
-				if (domain != last_domain) {
-					sal_ptc->num_domains++;
-					sal_ptcdi++;
-					sal_ptcdi->proc_count = 0;
-					sal_ptcdi->proc_list = __fwtab_pa(base_nasid, sal_ptclid);
-					last_domain = domain;
-				}
-				sal_ptcdi->proc_count++;
-				sal_ptclid->id = nasid;
-				sal_ptclid->eid = cpu;
-				sal_ptclid++;
-				cpus_found++;
-			}
-		}
-	}
-
-	if (cpus_found != num_cpus)
-		FPROM_BUG();
-
-	/* Make the AP WAKEUP entry */
-	sal_apwake->type = SAL_DESC_AP_WAKEUP;
-	sal_apwake->mechanism = IA64_SAL_AP_EXTERNAL_INT;
-	sal_apwake->vector = 18;
-
-	for (cp = (char *) sal_systab; cp < (char *) efi_memmap; ++cp)
-		checksum += *cp;
-
-	sal_systab->checksum = -checksum;
-
-	md = &efi_memmap[0];
-	num_memmd = build_efi_memmap((void *)md, mdsize) ;
-
-	bp = id(ZERO_PAGE_ADDR + (((long)base_nasid)<<33));
-	bp->efi_systab = __fwtab_pa(base_nasid, &fw_mem);
-	bp->efi_memmap = __fwtab_pa(base_nasid, efi_memmap);
-	bp->efi_memmap_size = num_memmd*mdsize;
-	bp->efi_memdesc_size = mdsize;
-	bp->efi_memdesc_version = 0x101;
-	bp->command_line = __fwtab_pa(base_nasid, cmd_line);
-	bp->console_info.num_cols = 80;
-	bp->console_info.num_rows = 25;
-	bp->console_info.orig_x = 0;
-	bp->console_info.orig_y = 24;
-	bp->num_pci_vectors = 0;
-	bp->fpswa = 0;
-
-	/*
-	 * Now pick the BSP & store it LID value in
-	 * a global variable. Note if BSP is greater than last cpu,
-	 * pick the last cpu.
-	 */
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (!IsCpuPresent(cnode, cpu))
-				continue;
-			bsp_lid = (GetNasid(cnode)<<24) | (cpu<<16);
-			if (bsp-- > 0)
-				continue;
-			return;
-		}
-	}
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/main.c linux/arch/ia64/sn/fprom/main.c
--- linux.orig/arch/ia64/sn/fprom/main.c	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/fprom/main.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,110 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#include <linux/types.h>
-#include <asm/bitops.h>
-
-void bedrock_init(int);
-void synergy_init(int, int);
-void sys_fw_init (const char *args, int arglen, int bsp);
-
-volatile int	bootmaster=0;		/* Used to pick bootmaster */
-volatile int	nasidmaster[128]={0};	/* Used to pick node/synergy masters */
-int		init_done=0;
-extern int	bsp_lid;
-
-#define get_bit(b,p)	(((*p)>>(b))&1)
-
-int
-fmain(int lid, int bsp) {
-	int	syn, nasid, cpu;
-
-	/*
-	 * First lets figure out who we are. This is done from the
-	 * LID passed to us.
-	 */
-	nasid = (lid>>24);
-	syn = (lid>>17)&1;
-	cpu = (lid>>16)&1;
-
-	/*
-	 * Now pick a synergy master to initialize synergy registers.
-	 */
-	if (test_and_set_bit(syn, &nasidmaster[nasid]) == 0) {
-		synergy_init(nasid, syn);
-		test_and_set_bit(syn+2, &nasidmaster[nasid]);
-	} else
-		while (get_bit(syn+2, &nasidmaster[nasid]) == 0);
-	
-	/*
-	 * Now pick a nasid master to initialize Bedrock registers.
-	 */
-	if (test_and_set_bit(8, &nasidmaster[nasid]) == 0) {
-		bedrock_init(nasid);
-		test_and_set_bit(9, &nasidmaster[nasid]);
-	} else
-		while (get_bit(9, &nasidmaster[nasid]) == 0);
-	
-
-	/*
-	 * Now pick a BSP & finish init.
-	 */
-	if (test_and_set_bit(0, &bootmaster) == 0) {
-		sys_fw_init(0, 0, bsp);
-		test_and_set_bit(1, &bootmaster);
-	} else
-		while (get_bit(1, &bootmaster) == 0);
-
-	return (lid == bsp_lid);
-}
-
-
-void
-bedrock_init(int nasid)
-{
-	nasid = nasid;		/* to quiet gcc */
-}
-
-
-void
-synergy_init(int nasid, int syn)
-{
-	long	*base;
-	long	off;
-
-	/*
-	 * Enable all FSB flashed interrupts.
-	 * ZZZ - I'd really like defines for this......
-	 */
-	base = (long*)0x80000e0000000000LL;		/* base of synergy regs */
-	for (off = 0x2a0; off < 0x2e0; off+=8)		/* offset for VEC_MASK_{0-3}_A/B */
-		*(base+off/8) = -1LL;
-
-	/*
-	 * Set the NASID in the FSB_CONFIG register.
-	 */
-	base = (long*)0x80000e0000000450LL;
-	*base = (long)((nasid<<16)|(syn<<9));
-}
-
-
-/* Why isnt there a bcopy/memcpy in lib64.a */
-
-void* 
-memcpy(void * dest, const void *src, size_t count)
-{
-	char *s, *se, *d;
-
-	for(d=dest, s=(char*)src, se=s+count; s<se; s++, d++)
-		*d = *s;
-	return dest;
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/fprom/runsim linux/arch/ia64/sn/fprom/runsim
--- linux.orig/arch/ia64/sn/fprom/runsim	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/fprom/runsim	1970-01-01 00:00:00.000000000 +0000
@@ -1,372 +0,0 @@
-#!/bin/sh
-
-# Script for running PROMs and LINUX kernwls on medusa. 
-# Type "sim -H" for instructions.
-
-MEDUSA=${MEDUSA:-/home/rickc/official_medusa/medusa}
-
-# ------------------ err -----------------------
-err() {
-	echo "ERROR - $1"
-	exit 1
-}
-
-# ----------------  help ----------------------
-help() {
-cat <<END
-Script for running a PROM or LINUX kernel under medusa.
-This script creates a control file, creates links to the appropriate
-linux/prom files, and/or calls medusa to make simulation runs.
-
-Usage:  
-   Initial setup:
-   	sim [-c <config_file>] <-p> | <-k>  [<work_dir>]
-		-p	Create PROM control file & links
-		-k	Create LINUX control file & links
-		-c<cf>	Control file name				[Default: cf]
-		<work_dir> Path to directory that contains the linux or PROM files.
-		    The directory can be any of the following:
-		       (linux simulations)
-		       		worktree
-				worktree/linux
-				any directory with vmlinux, vmlinux.sym & fprom files
-			(prom simulations)
-				worktree
-				worktree/stand/arcs/IP37prom/dev
-				any directory with fw.bin & fw.sim files
-
-    Simulations:
-	sim  [-X <n>] [-o <output>] [-M] [<config_file>]
-		-c<cf>	Control file name				[Default: cf]
-		-M	Pipe output thru fmtmedusa
-		-o	Output filename (copy of all commands/output)	[Default: simout]
-		-X	Specifies number of instructions to execute	[Default: 0]
-			(Used only in auto test mode - not described here)
-
-Examples:
-	sim -p <promtree>	# create control file (cf) & links for prom simulations
-	sim -k <linuxtree>	# create control file (cf) & links for linux simulations
-	sim -p -c cfprom	# create a prom control file (cfprom) only. No links are made.
-
-	sim			# run medusa using previously created links &
-				#   control file (cf).
-END
-exit 1
-}
-
-# ----------------------- create control file header --------------------
-create_cf_header() {
-cat <<END >>$CF
-#
-# Template for a control file for running linux kernels under medusa. 
-# You probably want to make mods here but this is a good starting point.
-#
-
-# Preferences
-setenv cpu_stepping A
-setenv exceptionPrint off
-setenv interrupt_messages off
-setenv lastPCsize 100000
-setenv low_power_mode on
-setenv partialIntelChipSet on
-setenv printIntelMessages off
-setenv prom_write_action halt
-setenv prom_write_messages on
-setenv step_quantum 100
-setenv swizzling on
-setenv tsconsole on
-setenv uart_echo on
-symbols on
-
-# IDE disk params
-setenv diskCylinders 611
-setenv bootDrive C
-setenv diskHeads 16
-setenv diskPath idedisk
-setenv diskPresent 1
-setenv diskSpt 63
-
-# Hardware config
-setenv coherency_type nasid
-setenv cpu_cache_type default
-setenv synergy_cache_type syn_cac_64m_8w
-
-# Numalink config
-setenv route_enable on
-setenv network_type xbar		# Select [xbar|router]
-setenv network_warning 0xff
-
-END
-}
-
-
-# ------------------ create control file entries for linux simulations -------------
-create_cf_linux() {
-cat <<END >>$CF
-# Kernel specific options
-setenv mca_on_memory_failure off
-setenv LOADPC 0x00100000		# FPROM load address/entry point (8 digits!)
-sr g 9 0xe000000000520000		# Kernel entry point
-setenv symbol_table vmlinux.sym
-load fprom
-load vmlinux
-
-# Useful breakpoints to always have set. Add more if desired.
-break 0xe000000000505e00	all	# dispatch_to_fault_handler
-break panic			all	# stop on panic
-break die_if_kernel		all	# may as well stop
-
-END
-}
-
-# ------------------ create control file entries for prom simulations ---------------
-create_cf_prom() {
-	SYM2=""
-	ADDR="0x80000000ff800000"
-	[ "$EMBEDDED_LINUX" != "0" ] || SYM2="setenv symbol_table2 vmlinux.sym"
-	[ "$SIZE" = "8MB" ] || ADDR="0x80000000ffc00000"
-	cat <<END >>$CF
-# PROM specific options
-setenv mca_on_memory_failure on
-setenv LOADPC 0x80000000ffffffb0
-setenv promFile fw.bin
-setenv promAddr $ADDR
-setenv symbol_table fw.sym
-$SYM2
-
-# Useful breakpoints to always have set. Add more if desired.
-break Pr_ivt_gexx 		all
-break Pr_ivt_brk		all
-break Pr_PROM_Panic_Spin	all
-break Pr_PROM_Panic		all
-break Pr_PROM_C_Panic		all
-break Pr_fled_die		all
-break Pr_ResetNow		all
-break Pr_zzzbkpt		all
-
-END
-}
-
-
-# ------------------ create control file entries for memory configuration -------------
-create_cf_memory() {
-cat <<END >>$CF
-# CPU/Memory map format:
-#	setenv nodeN_memory_config 0xBSBSBSBS
-#		B=banksize (0=unused, 1=64M, 2=128M, .., 5-1G, c=8M, d=16M, e=32M)
-#		S=bank enable (0=both disable, 3=both enable, 2=bank1 enable, 1=bank0 enable)
-#		  rightmost digits are for bank 0, the lowest address.
-#	setenv nodeN_nasid <nasid>
-#		specifies the NASID for the node. This is used ONLY if booting the kernel.
-#		On PROM configurations, set to 0 - PROM will change it later.
-#	setenv nodeN_cpu_config <cpu_mask>
-#		Set bit number N to 1 to enable cpu N. Ex., a value of 5 enables cpu 0 & 2.
-#
-# Repeat the above 3 commands for each node.
-#
-# For kernel, default to 32MB. Although this is not a valid hardware configuration,
-# it runs faster on medusa. For PROM, 64MB is smallest allowed value.
-
-setenv node0_cpu_config		0x1	# Enable only cpu 0 on the node
-END
-
-if [ $LINUX -eq 1 ] ; then
-cat <<END >>$CF
-setenv node0_nasid		0	# cnode 0 has NASID 0
-setenv node0_memory_config 	0xe1	# 32MB
-END
-else
-cat <<END >>$CF
-setenv node0_memory_config 	0x11	# 64MB
-END
-fi
-}
-
-# -------------------- set links to linux files -------------------------
-set_linux_links() {
-	if [ -d $D/linux/arch ] ; then
-		D=$D/linux
-	elif [ -d $D/arch -o -e vmlinux.sym ] ; then
-		D=$D
-	else
-		err "cant determine directory for linux binaries"
-	fi
-	rm -rf vmlinux vmlinux.sym fprom
-	ln -s $D/vmlinux vmlinux
-	ln -s $D/vmlinux.sym vmlinux.sym
-	if [ -d $D/arch ] ; then
-		ln -s $D/arch/ia64/sn/fprom/fprom fprom
-	else
-		ln -s $D/fprom fprom
-	fi
-	echo "  .. Created links to linux files"	
-}
-
-# -------------------- set links to prom files -------------------------
-set_prom_links() {
-	if [ -d $D/stand ] ; then
-		D=$D/stand/arcs/IP37prom/dev
-	elif [ -d $D/sal ] ; then
-		D=$D
-	else
-		err "cant determine directory for PROM binaries"
-	fi
-	SETUP="$D/../../../../.setup"
-	grep -q '^ *setenv *PROMSIZE *8MB' $SETUP
-	if [ $? -eq 0 ] ; then
-		SIZE="8MB"
-	else
-		SIZE="4MB"
-	fi
-	grep -q '^ *setenv *LAUNCH_VMLINUX' $SETUP
-	EMBEDDED_LINUX=$?
-	rm -f fw.bin fw.map fw.sym vmlinux vmlinux.sym fprom
-	SDIR="SN1IA${SIZE}.O"
-	BIN="SN1IAip37prom${SIZE}"
-	ln -s $D/$SDIR/$BIN.bin fw.bin
-	ln -s $D/$SDIR/$BIN.map fw.map
-	ln -s $D/$SDIR/$BIN.sym fw.sym
-	echo "  .. Created links to $SIZE prom files"
-	if [ $EMBEDDED_LINUX -eq 0 ] ; then
-		ln -s $D/linux/vmlinux vmlinux
-		ln -s $D/linux/vmlinux.sym vmlinux.sym
-		if [ -d linux/arch ] ; then
-			ln -s $D/linux/arch/ia64/sn/fprom/fprom fprom
-		else
-			ln -s $D/linux/fprom fprom
-		fi
-		echo "  .. Created links to embedded linux files in prom tree"
-	fi
-}
-
-# --------------- start of shell script --------------------------------
-OUT="simout"
-FMTMED=0
-STEPCNT=0
-PROM=0
-LINUX=0
-NCF="cf"
-while getopts "HMX:c:o:pk" c ; do
-        case ${c} in
-                H) help;;
-		M) FMTMED=1;;
-		X) STEPCNT=${OPTARG};;
-		c) NCF=${OPTARG};;
-		k) PROM=0;LINUX=1;;
-		p) PROM=1;LINUX=0;;
-		o) OUT=${OPTARG};;
-                \?) exit 1;;
-        esac
-done
-shift `expr ${OPTIND} - 1`
-
-# Check if command is for creating control file and/or links to images.
-if [ $PROM -eq 1 -o $LINUX -eq 1 ] ; then
-	CF=$NCF
-	[ ! -f $CF ] || err "wont overwrite an existing control file ($CF)"
-	if [ $# -gt 0 ] ; then
-		D=$1
-		[ -d $D ] || err "cannot find directory $D"
-		[ $PROM -eq 0 ]  || set_prom_links
-		[ $LINUX -eq 0 ] || set_linux_links
-	fi
-	create_cf_header
-	[ $PROM -eq 0 ]  || create_cf_prom
-	[ $LINUX -eq 0 ] || create_cf_linux
-	create_cf_memory
-	echo "  .. Basic control file created (in $CF). You might want to edit"
-	echo "     this file (at least, look at it)."
-	exit 0
-fi
-
-# Verify that the control file exists
-CF=${1:-$NCF}
-[ -f $CF ] || err "No control file exists. For help, type: $0 -H"
-
-# Build the .cf files from the user control file. The .cf file is
-# identical except that the actual start & load addresses are inserted
-# into the file. In addition, the FPROM commands for configuring memory
-# and LIDs are generated. 
-
-rm -f .cf .cf1 .cf2
-awk '
-function strtonum(n) {
-	 if (substr(n,1,2) != "0x")
-	 	return int(n)
-	 n = substr(n,3)
-	 r=0
-	 while (length(n) > 0) {
-	 	r = r*16+(index("0123456789abcdef", substr(n,1,1))-1)
-		n = substr(n,2)
-	 }
-	 return r
-	}
-/^#/   	{next}
-/^$/	{next}
-/^setenv *LOADPC/               {loadpc = $3; next}
-/^setenv *node._cpu_config/	{n=int(substr($2,5,1)); cpuconf[n] = strtonum($3); print; next}
-/^setenv *node._memory_config/	{n=int(substr($2,5,1)); memconf[n] = strtonum($3); print; next}
-/^setenv *node._nasid/		{n=int(substr($2,5,1)); nasid[n] = strtonum($3); print; next}
-		{print}
-END	{
-	 # Generate the memmap info that starts at the beginning of
-	 # the node the kernel was loaded on.
-	 loadnasid = nasid[0]
-	 cnode = 0
-	 for (i=0; i<128; i++) {
-		if (memconf[i] != "") {
-			printf "sm 0x%x%08x 0x%x%04x%04x\n", 
-				2*loadnasid, 8*cnodes+8, memconf[i], cpuconf[i], nasid[i]
-			cnodes++
-			cpus += substr("0112122312232334", cpuconf[i]+1,1)
-		}
-	 }
-	 printf "sm 0x%x00000000 0x%x%08x\n", 2*loadnasid, cnodes, cpus
-	 printf "setenv number_of_nodes %d\n", cnodes
-
-	 # Now set the starting PC for each cpu.
-	 cnode = 0
-	 lowcpu=-1
-	 for (i=0; i<128; i++) {
-		if (memconf[i] != "") {
-			printf "setnode %d\n", cnode
-			conf = cpuconf[i]
-			for (j=0; j<4; j++) {
-				if (conf != int(conf/2)*2) {
-	 				printf "setcpu %d\n", j
-					if (length(loadpc) == 18)
-						printf "sr pc %s\n", loadpc
-					else
-						printf "sr pc 0x%x%s\n", 2*loadnasid, substr(loadpc,3)
-					if (lowcpu == -1)
-						lowcpu = j
-				}
-				conf = int(conf/2)
-			}
-			cnode++
-		}
-	 }
-	 printf "setnode 0\n"
-	 printf "setcpu %d\n", lowcpu
-	}
-' <$CF >.cf
-
-# Now build the .cf1 & .cf2 control files.
-CF2_LINES="^sm |^break |^run |^si |^quit |^symbols "
-egrep  "$CF2_LINES" .cf >.cf2
-egrep -v "$CF2_LINES" .cf >.cf1
-if [ $STEPCNT -ne 0 ] ; then
-	echo "s $STEPCNT" >>.cf2
-	echo "lastpc 1000" >>.cf2
-	echo "q" >>.cf2
-fi
-echo "script-on $OUT" >>.cf2
-
-# Now start medusa....
-if [ $FMTMED -ne 0 ] ; then
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 |  fmtmedusa
-elif [ $STEPCNT -eq 0 ] ; then
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 
-else
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 2>&1 
-fi
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/Makefile linux/arch/ia64/sn/io/Makefile
--- linux.orig/arch/ia64/sn/io/Makefile	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/Makefile	2002-08-01 06:42:36.000000000 +0000
@@ -3,8 +3,7 @@
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
-# Copyright (C) 2000 Silicon Graphics, Inc.
-# Copyright (C) Jack Steiner (steiner@sgi.com)
+# Copyright (C) 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
 #
 #
 # Makefile for the linux kernel.
@@ -13,20 +12,34 @@
 # removes any old dependencies. DON'T put your own dependencies here
 # unless it's something special (ie not a .c file).
 #
-# Note 2! The CFLAGS definitions are now in the main makefile...
 
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
 O_TARGET := sgiio.o
-obj-y   := stubs.o sgi_if.o pciio.o pcibr.o xtalk.o xbow.o xswitch.o hubspc.o \
-		klgraph_hack.o io.o hubdev.o huberror.o \
+
+ifeq ($(CONFIG_MODULES),y)
+export-objs = pciio.o hcl.o
+endif
+
+obj-y  := stubs.o sgi_if.o pciio.o xtalk.o xbow.o xswitch.o klgraph_hack.o \
 		hcl.o labelcl.o invent.o klgraph.o klconflib.o sgi_io_sim.o \
 		module.o sgi_io_init.o klgraph_hack.o ml_SN_init.o \
-		ml_SN_intr.o ip37.o pciba.o \
-		ml_iograph.o hcl_util.o cdl.o \
-		mem_refcnt.o devsupport.o alenlist.o pci_bus_cvlink.o \
-		eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o
+		ml_iograph.o hcl_util.o cdl.o hubdev.o hubspc.o \
+		alenlist.o pci_bus_cvlink.o \
+		eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o \
+		ifconfig_net.o efi-rtc.o io.o
+
+obj-$(CONFIG_IA64_SGI_SN1)   += sn1/ml_SN_intr.o sn1/mem_refcnt.o sn1/hubcounters.o \
+				sn1/ip37.o sn1/huberror.o sn1/hub_intr.o sn1/pcibr.o
+
+obj-$(CONFIG_IA64_SGI_SN2)   += sn2/ml_SN_intr.o sn2/shub_intr.o sn2/shuberror.o \
+				sn2/bte_error.o \
+				sn2/pcibr/pcibr_dvr.o sn2/pcibr/pcibr_ate.o \
+				sn2/pcibr/pcibr_config.o sn2/pcibr/pcibr_dvr.o \
+				sn2/pcibr/pcibr_hints.o \
+				sn2/pcibr/pcibr_idbg.o sn2/pcibr/pcibr_intr.o \
+				sn2/pcibr/pcibr_rrb.o sn2/pcibr/pcibr_slot.o 
+
+obj-$(CONFIG_PCIBA) += pciba.o
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/alenlist.c linux/arch/ia64/sn/io/alenlist.c
--- linux.orig/arch/ia64/sn/io/alenlist.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/alenlist.c	2002-08-01 06:42:44.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /* Implementation of Address/Length Lists. */
@@ -13,9 +12,9 @@
 
 #include <linux/types.h>
 #include <linux/slab.h>
+#include <linux/mmzone.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/alenlist.h>
-#include <asm/sn/mmzone_sn1.h>
 
 /*
  * Logically, an Address/Length List is a list of Pairs, where each pair
@@ -218,9 +217,9 @@
 void
 alenlist_init(void)
 {
-	alenlist_zone = kmem_zone_init(sizeof(struct alenlist_s), "alenlist");
-	alenlist_chunk_zone = kmem_zone_init(sizeof(struct alenlist_chunk_s), "alchunk");
-	alenlist_cursor_zone = kmem_zone_init(sizeof(struct alenlist_cursor_s), "alcursor");
+	alenlist_zone = snia_kmem_zone_init(sizeof(struct alenlist_s), "alenlist");
+	alenlist_chunk_zone = snia_kmem_zone_init(sizeof(struct alenlist_chunk_s), "alchunk");
+	alenlist_cursor_zone = snia_kmem_zone_init(sizeof(struct alenlist_cursor_s), "alcursor");
 #if DEBUG
 	idbg_addfunc("alenshow", alenlist_show);
 #endif /* DEBUG */
@@ -250,7 +249,7 @@
 {
 	alenlist_t alenlist;
 
-	alenlist = kmem_zone_alloc(alenlist_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
+	alenlist = snia_kmem_zone_alloc(alenlist_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 	if (alenlist) {
 		INCR_COUNT(&alenlist_count);
 
@@ -334,7 +333,7 @@
 		while (chunk) {
 			freechunk = chunk;
 			chunk = chunk->alc_next;
-			kmem_zone_free(alenlist_chunk_zone, freechunk);
+			snia_kmem_zone_free(alenlist_chunk_zone, freechunk);
 			DECR_COUNT(&alenlist_chunk_count);
 		}
 		alenlist->al_actual_size = ALEN_CHUNK_SZ;
@@ -407,7 +406,7 @@
 		alenlist_clear(alenlist);
 
 	/* Now, free the alenlist itself */
-	kmem_zone_free(alenlist_zone, alenlist);
+	snia_kmem_zone_free(alenlist_zone, alenlist);
 	DECR_COUNT(&alenlist_count);
 }
 
@@ -473,7 +472,7 @@
 			} else {
 				alenlist_chunk_t new_chunk;
 
-				new_chunk = kmem_zone_alloc(alenlist_chunk_zone, 
+				new_chunk = snia_kmem_zone_alloc(alenlist_chunk_zone, 
 							flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 
 				if (new_chunk == NULL)
@@ -656,7 +655,7 @@
 	alenlist_cursor_t cursorp;
 
 	ASSERT(alenlist != NULL);
-	cursorp = kmem_zone_alloc(alenlist_cursor_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
+	cursorp = snia_kmem_zone_alloc(alenlist_cursor_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 	if (cursorp) {
 		INCR_COUNT(&alenlist_cursor_count);
 		alenlist_cursor_init(alenlist, 0, cursorp);
@@ -671,7 +670,7 @@
 alenlist_cursor_destroy(alenlist_cursor_t cursorp)
 {
 	DECR_COUNT(&alenlist_cursor_count);
-	kmem_zone_free(alenlist_cursor_zone, cursorp);
+	snia_kmem_zone_free(alenlist_cursor_zone, cursorp);
 }
 
 
@@ -752,7 +751,7 @@
 			maxlength -= 
 			   ((alenp->al_addr + cursorp->al_bcount) & maxlen1);
 
-		length = MIN(maxlength, length);
+		length = min(maxlength, length);
 	}
 
 	/* Update the cursor, if desired. */
@@ -842,7 +841,7 @@
 	offset = poff(kvaddr);
 
 	/* Handle first page */
-	piece_length = MIN(NBPP - offset, length);
+	piece_length = min((size_t)(NBPP - offset), length);
 	if (alenlist_append(alenlist, paddr, piece_length, flags) == ALENLIST_FAILURE)
 		goto failure;
 	length -= piece_length;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/ate_utils.c linux/arch/ia64/sn/io/ate_utils.c
--- linux.orig/arch/ia64/sn/io/ate_utils.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/ate_utils.c	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,205 @@
+/* $Id: ate_utils.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/io.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/ioerror_handling.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/sn_private.h>
+
+#include <asm/sn/ate_utils.h>
+
+/*
+ * Allocate the map needed to allocate the ATE entries.
+ */
+struct map *
+atemapalloc(ulong_t mapsiz)
+{
+	struct map *mp;
+	ulong_t size;
+	struct a {
+		spinlock_t lock;
+		sv_t 	sema;
+	} *sync;
+
+	if (mapsiz == 0)
+		return(NULL);
+	size = sizeof(struct map) * (mapsiz + 2);
+	if ((mp = (struct map *) kmalloc(size, GFP_KERNEL)) == NULL)
+		return(NULL);
+	memset(mp, 0x0, size);
+
+	sync = kmalloc(sizeof(struct a), GFP_KERNEL);
+	if (sync == NULL) {
+		kfree(mp);
+		return(NULL);
+	}
+	memset(sync, 0x0, sizeof(struct a));
+
+	mutex_spinlock_init(&sync->lock);
+	sv_init( &(sync->sema), &(sync->lock), SV_MON_SPIN | SV_ORDER_FIFO /*| SV_INTS*/);
+	mp[1].m_size = (unsigned long) &sync->lock;
+	mp[1].m_addr = (unsigned long) &sync->sema;
+	mapsize(mp) = mapsiz - 1;
+	return(mp);
+}
+
+/*
+ * free a map structure previously allocated via rmallocmap().
+ */
+void
+atemapfree(struct map *mp)
+{
+	struct a {
+		spinlock_t lock;
+		sv_t 	sema;
+	};
+	/* ASSERT(sv_waitq(mapout(mp)) == 0); */
+	/* sv_destroy(mapout(mp)); */
+	spin_lock_destroy(maplock(mp));
+	kfree((void *)mp[1].m_size);
+	kfree(mp);
+}
+
+/*
+ * Allocate 'size' units from the given map.
+ * Return the base of the allocated space.
+ * In a map, the addresses are increasing and the
+ * list is terminated by a 0 size.
+ * Algorithm is first-fit.
+ */
+
+ulong_t
+atealloc(
+	struct map *mp,
+	size_t size)
+{
+	register unsigned int a;
+	register struct map *bp;
+	register unsigned long s;
+
+	ASSERT(size >= 0);
+
+	if (size == 0)
+		return((ulong_t) NULL);
+
+	s = mutex_spinlock(maplock(mp));
+
+	for (bp = mapstart(mp); bp->m_size; bp++) {
+		if (bp->m_size >= size) {
+			a = bp->m_addr;
+			bp->m_addr += size;
+			if ((bp->m_size -= size) == 0) {
+				do {
+					bp++;
+					(bp-1)->m_addr = bp->m_addr;
+				} while ((((bp-1)->m_size) = (bp->m_size)));
+				mapsize(mp)++;
+			}
+
+			ASSERT(bp->m_size < 0x80000000);
+			mutex_spinunlock(maplock(mp), s);
+			return(a);
+		}
+	}
+
+	/*
+	 * We did not get what we need .. we cannot sleep .. 
+	 */
+	mutex_spinunlock(maplock(mp), s);
+	return(0);
+}
+
+/*
+ * Free the previously allocated space a of size units into the specified map.
+ * Sort ``a'' into map and combine on one or both ends if possible.
+ * Returns 0 on success, 1 on failure.
+ */
+void
+atefree(struct map *mp, size_t size, ulong_t a)
+{
+	register struct map *bp;
+	register unsigned int t;
+	register unsigned long s;
+
+	ASSERT(size >= 0);
+
+	if (size == 0)
+		return;
+
+	bp = mapstart(mp);
+	s = mutex_spinlock(maplock(mp));
+
+	for ( ; bp->m_addr<=a && bp->m_size!=0; bp++)
+		;
+	if (bp>mapstart(mp) && (bp-1)->m_addr+(bp-1)->m_size == a) {
+		(bp-1)->m_size += size;
+		if (bp->m_addr) {	
+			/* m_addr==0 end of map table */
+			ASSERT(a+size <= bp->m_addr);
+			if (a+size == bp->m_addr) { 
+
+				/* compress adjacent map addr entries */
+				(bp-1)->m_size += bp->m_size;
+				while (bp->m_size) {
+					bp++;
+					(bp-1)->m_addr = bp->m_addr;
+					(bp-1)->m_size = bp->m_size;
+				}
+				mapsize(mp)++;
+			}
+		}
+	} else {
+		if (a+size == bp->m_addr && bp->m_size) {
+			bp->m_addr -= size;
+			bp->m_size += size;
+		} else {
+			ASSERT(size);
+			if (mapsize(mp) == 0) {
+				mutex_spinunlock(maplock(mp), s);
+				printk("atefree : map overflow 0x%p Lost 0x%lx items at 0x%lx",
+						(void *)mp, size, a) ;
+				return ;
+			}
+			do {
+				t = bp->m_addr;
+				bp->m_addr = a;
+				a = t;
+				t = bp->m_size;
+				bp->m_size = size;
+				bp++;
+			} while ((size = t));
+			mapsize(mp)--;
+		}
+	}
+	mutex_spinunlock(maplock(mp), s);
+	/*
+	 * wake up everyone waiting for space
+	 */
+	if (mapout(mp))
+		;
+		/* sv_broadcast(mapout(mp)); */
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/cdl.c linux/arch/ia64/sn/io/cdl.c
--- linux.orig/arch/ia64/sn/io/cdl.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/cdl.c	2002-08-01 06:42:37.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -17,11 +16,9 @@
 #include "asm/sn/ioerror_handling.h"
 #include <asm/sn/xtalk/xbow.h>
 
-#ifdef BRINGUP
 /* these get called directly in cdl_add_connpt in fops bypass hack */
 extern int pcibr_attach(devfs_handle_t);
 extern int xbow_attach(devfs_handle_t);
-#endif /* BRINGUP */
 
 /*
  *    cdl: Connection and Driver List
@@ -38,8 +35,6 @@
     int (*attach) (devfs_handle_t);
 } dummy_reg;
 
-typedef struct cdl     *cdl_p;
-
 #define MAX_SGI_IO_INFRA_DRVR 4
 struct cdl sgi_infrastructure_drivers[MAX_SGI_IO_INFRA_DRVR] =
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/devsupport.c linux/arch/ia64/sn/io/devsupport.c
--- linux.orig/arch/ia64/sn/io/devsupport.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/devsupport.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,1289 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/iobus.h>
-#include <asm/sn/iograph.h>
-
-/* 
- * Interfaces in this file are all platform-independent AND IObus-independent.
- * Be aware that there may be macro equivalents to each of these hiding in
- * header files which supercede these functions.
- */
-
-/* =====Generic iobus support===== */
-
-/* String table to hold names of interrupts. */
-#ifdef LATER
-static struct string_table device_desc_string_table;
-#endif
-
-/* One time initialization for device descriptor support. */
-static void
-device_desc_init(void)
-{
-#ifdef LATER
-	string_table_init(&device_desc_string_table);
-#endif
-	FIXME("device_desc_init");
-}
-
-
-/* Drivers use these interfaces to manage device descriptors */
-static device_desc_t
-device_desc_alloc(void)
-{
-#ifdef LATER
-	device_desc_t device_desc;
-
-	device_desc = (device_desc_t)kmem_zalloc(sizeof(struct device_desc_s), 0);
-	device_desc->intr_target = GRAPH_VERTEX_NONE;
-
-	ASSERT(device_desc->intr_policy == 0);
-	device_desc->intr_swlevel = -1;
-	ASSERT(device_desc->intr_name == NULL);
-	ASSERT(device_desc->flags == 0);
-
-	ASSERT(!(device_desc->flags & D_IS_ASSOC));
-	return(device_desc);
-#else
-	FIXME("device_desc_alloc");
-	return((device_desc_t)0);
-#endif
-}
-
-void
-device_desc_free(device_desc_t device_desc)
-{
-#ifdef LATER
-	if (!(device_desc->flags & D_IS_ASSOC)) /* sanity */
-		kfree(device_desc);
-#endif
-	FIXME("device_desc_free");
-}
-
-device_desc_t
-device_desc_dup(devfs_handle_t dev)
-{
-#ifdef LATER
-	device_desc_t orig_device_desc, new_device_desc;
-
-
-	new_device_desc = device_desc_alloc();
-	orig_device_desc = device_desc_default_get(dev);
-	if (orig_device_desc)
-		*new_device_desc = *orig_device_desc;/* small structure copy */
-	else {
-		device_driver_t		driver;
-		ilvl_t			pri;		
-		/* 
-		 * Use the driver's thread priority in 
-		 * case the device thread priority has not
-		 * been given.
-		 */
-		if (driver = device_driver_getbydev(dev)) {
-			pri = device_driver_thread_pri_get(driver);
-			device_desc_intr_swlevel_set(new_device_desc,pri);
-		}
-	}		
-	new_device_desc->flags &= ~D_IS_ASSOC;
-	return(new_device_desc);
-#else
-	FIXME("device_desc_dup");
-	return((device_desc_t)0);
-#endif
-}
-
-device_desc_t	
-device_desc_default_get(devfs_handle_t dev)
-{
-#ifdef LATER
-	graph_error_t rc;
-	device_desc_t device_desc;
-
-	rc = hwgraph_info_get_LBL(dev, INFO_LBL_DEVICE_DESC, (arbitrary_info_t *)&device_desc);
-
-	if (rc == GRAPH_SUCCESS)
-		return(device_desc);
-	else
-		return(NULL);
-#else
-	FIXME("device_desc_default_get");
-	return((device_desc_t)0);
-#endif
-}
-
-void		
-device_desc_default_set(devfs_handle_t dev, device_desc_t new_device_desc)
-{
-#ifdef LATER
-	graph_error_t rc;
-	device_desc_t old_device_desc = NULL;
-
-	if (new_device_desc) {
-		new_device_desc->flags |= D_IS_ASSOC;
-		rc = hwgraph_info_add_LBL(dev, INFO_LBL_DEVICE_DESC, 
-						(arbitrary_info_t)new_device_desc);
-		if (rc == GRAPH_DUP) {
-			rc = hwgraph_info_replace_LBL(dev, INFO_LBL_DEVICE_DESC, 
-				(arbitrary_info_t)new_device_desc, 
-				(arbitrary_info_t *)&old_device_desc);
-
-			ASSERT(rc == GRAPH_SUCCESS);
-		}
-		hwgraph_info_export_LBL(dev, INFO_LBL_DEVICE_DESC,
-					sizeof(struct device_desc_s));
-	} else {
-		rc = hwgraph_info_remove_LBL(dev, INFO_LBL_DEVICE_DESC,
-					(arbitrary_info_t *)&old_device_desc);
-	}
-
-	if (old_device_desc) {
-		ASSERT(old_device_desc->flags & D_IS_ASSOC);
-		old_device_desc->flags &= ~D_IS_ASSOC;
-		device_desc_free(old_device_desc);
-	}
-#endif
-	FIXME("device_desc_default_set");
-}
-
-devfs_handle_t
-device_desc_intr_target_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_target);
-#else
-	FIXME("device_desc_intr_target_get");
-	return((devfs_handle_t)0);
-#endif
-}
-
-int
-device_desc_intr_policy_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_policy);
-#else
-	FIXME("device_desc_intr_policy_get");
-	return(0);
-#endif
-}
-
-ilvl_t
-device_desc_intr_swlevel_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_swlevel);
-#else
-	FIXME("device_desc_intr_swlevel_get");
-	return((ilvl_t)0);
-#endif
-}
-
-char *
-device_desc_intr_name_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_name);
-#else
-	FIXME("device_desc_intr_name_get");
-	return(NULL);
-#endif
-}
-
-int
-device_desc_flags_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->flags);
-#else
-	FIXME("device_desc_flags_get");
-	return(0);
-#endif
-}
-
-void
-device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_target = target;
-}
-
-void
-device_desc_intr_policy_set(device_desc_t device_desc, int policy)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_policy = policy;
-}
-
-void
-device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_swlevel = swlevel;
-}
-
-void
-device_desc_intr_name_set(device_desc_t device_desc, char *name)
-{
-#ifdef LATER
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_name = string_table_insert(&device_desc_string_table, name);
-#else
-	FIXME("device_desc_intr_name_set");
-#endif
-}
-
-void
-device_desc_flags_set(device_desc_t device_desc, int flags)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->flags = flags;
-}
-
-
-
-/*============= device admin registry routines ===================== */
-
-/* Linked list of <admin-name,admin-val> pairs */
-typedef struct dev_admin_list_s {
-	struct dev_admin_list_s		*admin_next; 	/* next entry in the
-							 * list 
-							 */
-	char				*admin_name;	/* info label */
-	char				*admin_val;	/* actual info */
-} dev_admin_list_t;
-
-/* Device/Driver administration registry */
-typedef struct dev_admin_registry_s {
-	mrlock_t			reg_lock;	/* To allow
-							 * exclusive
-							 * access
-							 */
-	dev_admin_list_t		*reg_first;	/* first entry in 
-							 * the list
-							 */
-	dev_admin_list_t		**reg_last;	/* pointer to the
-							 * next to last entry
-							 * in the last which 
-							 * is also the place
-							 * where the new
-							 * entry gets
-							 * inserted
-							 */
-} dev_admin_registry_t;
-
-/*
-** device_driver_s associates a device driver prefix with device switch entries.
-*/
-struct device_driver_s {
-	struct device_driver_s	*dd_next;	/* next element on hash chain */
-	struct device_driver_s	*dd_prev;	/* previous element on hash chain */
-	char			*dd_prefix;	/* driver prefix string */
-	struct bdevsw		*dd_bdevsw;	/* driver's bdevsw */
-	struct cdevsw		*dd_cdevsw;	/* driver's cdevsw */
-	
-	/* driver administration specific data structures need to
-	 * maintain the list of <driver-paramater,value> pairs
-	 */
-	dev_admin_registry_t	dd_dev_admin_registry;
-	ilvl_t			dd_thread_pri;	/* default thread priority for
-						 *  all this driver's
-						 * threads.
-						 */
-
-};
-
-#define	NEW(_p)		(_p = kmalloc(sizeof(*_p), GFP_KERNEL))
-#define FREE(_p)	(kmem_free(_p))
-	
-/*
- * helpful lock macros
- */
-
-#define DEV_ADMIN_REGISTRY_INITLOCK(lockp,name)	mrinit(lockp,name)
-#define DEV_ADMIN_REGISTRY_RDLOCK(lockp)	mraccess(lockp)	       
-#define DEV_ADMIN_REGISTRY_WRLOCK(lockp)	mrupdate(lockp)	       
-#define DEV_ADMIN_REGISTRY_UNLOCK(lockp)	mrunlock(lockp)
-
-/* Initialize the registry 
- */
-static void
-dev_admin_registry_init(dev_admin_registry_t *registry)
-{
-#ifdef LATER
-	if ( registry != (dev_admin_registry_t *)0 )
-		DEV_ADMIN_REGISTRY_INITLOCK(&registry->reg_lock,
-				    "dev_admin_registry_lock");
-		registry->reg_first = NULL;
-		registry->reg_last = &registry->reg_first;
-	}
-#else
-	FIXME("dev_admin_registry_init");
-#endif
-}
-
-/*
- * add an <name , value > entry to the dev admin registry.
- * if the name already exists in the registry then change the
- * value iff the new value differs from the old value.
- * if the name doesn't exist a new list entry is created and put
- * at the end.
- */
-static void
-dev_admin_registry_add(dev_admin_registry_t	*registry,
-		       char			*name,
-		       char			*val)
-{
-#ifdef LATER
-	dev_admin_list_t	*reg_entry;
-	dev_admin_list_t	*scan = 0;
-
-	DEV_ADMIN_REGISTRY_WRLOCK(&registry->reg_lock);
-
-	/* check if the name already exists in the registry */
-	scan = registry->reg_first;
-
-	while (scan) {
-		if (strcmp(scan->admin_name,name) == 0) {
-			/* name is there in the registry */
-			if (strcmp(scan->admin_val,val)) {
-				/* old value != new value 
-				 * reallocate  memory and copy the new value
-				 */
-				FREE(scan->admin_val);
-				scan->admin_val = 
-					(char *)kern_calloc(1,strlen(val)+1);
-				strcpy(scan->admin_val,val);
-				goto out;
-			}
-			goto out;	/* old value == new value */
-		}
-		scan = scan->admin_next;
-	}
-
-	/* name is not there in the registry.
-	 * allocate memory for the new registry entry 
-	 */
-	NEW(reg_entry);
-	
-	reg_entry->admin_next   	= 0;
-	reg_entry->admin_name	= (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(reg_entry->admin_name,name);
-	reg_entry->admin_val	= (char *)kern_calloc(1,strlen(val)+1);
-	strcpy(reg_entry->admin_val,val);
-
-	/* add the entry at the end of the registry */
-
-	*(registry->reg_last)	= reg_entry;
-	registry->reg_last	= &reg_entry->admin_next;
-
-out:	DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-#endif
-	FIXME("dev_admin_registry_add");
-}
-/*
- * check if there is an info corr. to a particular
- * name starting from the cursor position in the 
- * registry
- */
-static char *
-dev_admin_registry_find(dev_admin_registry_t *registry,char *name)
-{
-#ifdef LATER
-	dev_admin_list_t	*scan = 0;
-	
-	DEV_ADMIN_REGISTRY_RDLOCK(&registry->reg_lock);
-	scan = registry->reg_first;
-
-	while (scan) {
-		if (strcmp(scan->admin_name,name) == 0) {
-			DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-			return scan->admin_val;
-		}
-		scan = scan->admin_next;
-	}
-	DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-	return 0;
-#else
-	FIXME("dev_admin_registry_find");
-	return(NULL);
-#endif
-}
-/*============= MAIN DEVICE/ DRIVER ADMINISTRATION INTERFACE================ */
-/*
- * return any labelled info associated with a device.
- * called by any kernel code including device drivers.
- */
-char *
-device_admin_info_get(devfs_handle_t	dev_vhdl,
-		      char		*info_lbl)
-{
-#ifdef LATER
-	char		*info = 0;
-
-	/* return value need not be GRAPH_SUCCESS as the labelled
-	 * info may not be present
-	 */
-	(void)hwgraph_info_get_LBL(dev_vhdl,info_lbl,
-				   (arbitrary_info_t *)&info);
-
-	
-	return info;
-#else
-	FIXME("device_admin_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * set labelled info associated with a device.
- * called by hwgraph infrastructure . may also be called
- * by device drivers etc.
- */
-int
-device_admin_info_set(devfs_handle_t	dev_vhdl,
-		      char		*dev_info_lbl,
-		      char		*dev_info_val)
-{
-#ifdef LATER
-	graph_error_t		rv;
-	arbitrary_info_t	old_info;
-
-	/* Handle the labelled info
-	 *		intr_target
-	 *		sw_level 
-	 * in a special way. These are part of device_desc_t
-	 * Right now this is the only case where we have 
-	 * a set of related device_admin attributes which 
-	 * are grouped together.
-	 * In case there is a need for another set we need to
-	 * take a more generic approach to solving this.
-	 * Basically a registry should be implemented. This
-	 * registry is initialized with the callbacks for the
-	 * attributes which need to handled in a special way
-	 * For example:
-	 * Consider
-	 * 		device_desc
-	 *			intr_target
-	 *			intr_swlevel
-	 * register "do_intr_target" for intr_target
-	 * register "do_intr_swlevel" for intr_swlevel.
-	 * When the device_admin interface layer gets an <attr,val> pair
-	 * it looks in the registry to see if there is a function registered to
-	 * handle "attr. If not follow the default path of setting the <attr,val>
-	 * as labelled information hanging off the vertex.
-	 * In the above example:
-	 * "do_intr_target" does what is being done below for the ADMIN_LBL_INTR_TARGET
-	 * case
-	 */		
-	if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_TARGET) ||
-	    !strcmp(dev_info_lbl,ADMIN_LBL_INTR_SWLEVEL)) {
-
-		device_desc_t	device_desc;
-		
-		/* Check if there is a default device descriptor
-		 * information for this vertex. If not dup one .
-		 */
-		if (!(device_desc = device_desc_default_get(dev_vhdl))) {
-			device_desc = device_desc_dup(dev_vhdl);
-			device_desc_default_set(dev_vhdl,device_desc);
-
-		}
-		if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_TARGET)) {
-			/* Check if a target cpu has been specified
-			 * for this device by a device administration
-			 * directive
-			 */
-#ifdef DEBUG	
-			printf(ADMIN_LBL_INTR_TARGET
-			       " dev = 0x%x "
-			       "dev_admin_info = %s"
-			       " target = 0x%x\n",
-			       dev_vhdl,
-			       dev_info_lbl,
-			       hwgraph_path_to_vertex(dev_info_val));
-#endif	
-
-			device_desc->intr_target = 
-				hwgraph_path_to_vertex(dev_info_val);
-		} else if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_SWLEVEL)) {
-			/* Check if the ithread priority level  has been 
-			 * specified for this device by a device administration
-			 * directive
-			 */
-#ifdef DEBUG	
-			printf(ADMIN_LBL_INTR_SWLEVEL
-			       " dev = 0x%x "
-			       "dev_admin_info = %s"
-			       " sw level = 0x%x\n",
-			       dev_vhdl,
-			       dev_info_lbl,
-			       atoi(dev_info_val));
-#endif	
-			device_desc->intr_swlevel = atoi(dev_info_val);
-		}
-
-	}
-	if (!dev_info_val)
-		rv = hwgraph_info_remove_LBL(dev_vhdl,
-					     dev_info_lbl,
-					     &old_info);
-	else {
-
-		rv = hwgraph_info_add_LBL(dev_vhdl,
-					  dev_info_lbl,
-					  (arbitrary_info_t)dev_info_val);
-	
-		if (rv == GRAPH_DUP)  {
-			rv = hwgraph_info_replace_LBL(dev_vhdl,
-					      dev_info_lbl,
-					      (arbitrary_info_t)dev_info_val,
-					      &old_info);
-		}
-	}
-	ASSERT(rv == GRAPH_SUCCESS);
-#endif
-	FIXME("device_admin_info_set");
-	return 0;
-}
-
-/*
- * return labelled info associated with a device driver
- * called by kernel code including device drivers
- */
-char *
-device_driver_admin_info_get(char		*driver_prefix,
-			     char		*driver_info_lbl)
-{
-#ifdef LATER
-	device_driver_t driver;
-
-	driver = device_driver_get(driver_prefix);
-	return (dev_admin_registry_find(&driver->dd_dev_admin_registry,
-					driver_info_lbl));
-#else
-	FIXME("device_driver_admin_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * set labelled info associated with a device driver.
- * called by hwgraph infrastructure . may also be called
- * from drivers etc.
- */
-int
-device_driver_admin_info_set(char		*driver_prefix,
-			     char		*driver_info_lbl,
-			     char		*driver_info_val)
-{
-#ifdef LATER
-	device_driver_t driver;
-
-	driver = device_driver_get(driver_prefix);
-	dev_admin_registry_add(&driver->dd_dev_admin_registry,	
-			       driver_info_lbl,
-			       driver_info_val);
-#endif
-	FIXME("device_driver_admin_info_set");
-	return 0;
-}
-/*================== device / driver  admin support routines================*/
-
-/* static tables created by lboot */
-extern dev_admin_info_t	dev_admin_table[];
-extern dev_admin_info_t	drv_admin_table[];
-extern int		dev_admin_table_size;
-extern int		drv_admin_table_size;
-
-/* Extend the device admin table to allow the kernel startup code to 
- * provide some device specific administrative hints
- */
-#define ADMIN_TABLE_CHUNK	100
-static dev_admin_info_t extended_dev_admin_table[ADMIN_TABLE_CHUNK];	
-static int		extended_dev_admin_table_size = 0;
-static mrlock_t		extended_dev_admin_table_lock;
-
-/* Initialize the extended device admin table */
-void
-device_admin_table_init(void)
-{
-#ifdef LATER
-	extended_dev_admin_table_size = 0;
-	mrinit(&extended_dev_admin_table_lock,
-	       "extended_dev_admin_table_lock");
-#endif
-	FIXME("device_admin_table_init");
-}
-/* Add <device-name , parameter-name , parameter-value> triple to
- * the extended device administration info table. This is helpful
- * for kernel startup code to put some hints before the hwgraph
- * is setup 
- */
-void
-device_admin_table_update(char *name,char *label,char *value)
-{
-#ifdef LATER
-	dev_admin_info_t	*p;
-
-	mrupdate(&extended_dev_admin_table_lock);
-
-	/* Safety check that we haven't exceeded array limits */
-	ASSERT(extended_dev_admin_table_size < ADMIN_TABLE_CHUNK);
-
-	if (extended_dev_admin_table_size == ADMIN_TABLE_CHUNK)
-		goto out;
-	
-	/* Get the pointer to the entry in the table where we are
-	 * going to put the new information 
-	 */
-	p = &extended_dev_admin_table[extended_dev_admin_table_size++];
-
-	/* Allocate memory for the strings and copy them in */
-	p->dai_name = (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(p->dai_name,name);
-	p->dai_param_name = (char *)kern_calloc(1,strlen(label)+1);
-	strcpy(p->dai_param_name,label);
-	p->dai_param_val = (char *)kern_calloc(1,strlen(value)+1);
-	strcpy(p->dai_param_val,value);
-
-out:	mrunlock(&extended_dev_admin_table_lock);
-#endif
-	FIXME("device_admin_table_update");
-}
-/* Extend the device driver  admin table to allow the kernel startup code to 
- * provide some device driver specific administrative hints
- */
-
-static dev_admin_info_t extended_drv_admin_table[ADMIN_TABLE_CHUNK];	
-static int		extended_drv_admin_table_size = 0;
-mrlock_t		extended_drv_admin_table_lock;
-
-/* Initialize the extended device driver admin table */
-void
-device_driver_admin_table_init(void)
-{
-#ifdef LATER
-	extended_drv_admin_table_size = 0;
-	mrinit(&extended_drv_admin_table_lock,
-	       "extended_drv_admin_table_lock");
-#endif
-	FIXME("device_driver_admin_table_init");
-}
-/* Add <device-driver prefix , parameter-name , parameter-value> triple to
- * the extended device administration info table. This is helpful
- * for kernel startup code to put some hints before the hwgraph
- * is setup 
- */
-void
-device_driver_admin_table_update(char *name,char *label,char *value)
-{
-#ifdef LATER
-	dev_admin_info_t	*p;
-
-	mrupdate(&extended_dev_admin_table_lock);
-
-	/* Safety check that we haven't exceeded array limits */
-	ASSERT(extended_drv_admin_table_size < ADMIN_TABLE_CHUNK);
-
-	if (extended_drv_admin_table_size == ADMIN_TABLE_CHUNK)
-		goto out;
-	
-	/* Get the pointer to the entry in the table where we are
-	 * going to put the new information 
-	 */
-	p = &extended_drv_admin_table[extended_drv_admin_table_size++];
-
-	/* Allocate memory for the strings and copy them in */
-	p->dai_name = (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(p->dai_name,name);
-	p->dai_param_name = (char *)kern_calloc(1,strlen(label)+1);
-	strcpy(p->dai_param_name,label);
-	p->dai_param_val = (char *)kern_calloc(1,strlen(value)+1);
-	strcpy(p->dai_param_val,value);
-
-out:	mrunlock(&extended_drv_admin_table_lock);
-#endif
-	FIXME("device_driver_admin_table_update");
-}
-/*
- * keeps on adding the labelled info for each new (lbl,value) pair
- * that it finds in the static dev admin table (  created by lboot)
- * and the extended dev admin table ( created if at all by the kernel startup
- *  code) corresponding to a device in the hardware graph.
- */
-void
-device_admin_info_update(devfs_handle_t	dev_vhdl)
-{
-#ifdef LATER
-	int			i = 0;
-	dev_admin_info_t	*scan;
-	devfs_handle_t		scan_vhdl;
-	
-	/* Check the static device administration info table */
-	scan = dev_admin_table;
-	while (i < dev_admin_table_size) {
-		
-		scan_vhdl = hwgraph_path_to_dev(scan->dai_name);
-		if (scan_vhdl == dev_vhdl) {
-			device_admin_info_set(dev_vhdl,
-					      scan->dai_param_name,
-					      scan->dai_param_val);
-		}
-		if (scan_vhdl != NODEV)
-			hwgraph_vertex_unref(scan_vhdl);
-		scan++;i++;
-
-	}
-	i = 0;
-	/* Check the extended device administration info table */
-	scan = extended_dev_admin_table;
-	while (i < extended_dev_admin_table_size) {
-		scan_vhdl = hwgraph_path_to_dev(scan->dai_name);
-		if (scan_vhdl == dev_vhdl) {
-			device_admin_info_set(dev_vhdl,
-					      scan->dai_param_name,
-					      scan->dai_param_val);
-		}
-		if (scan_vhdl != NODEV)
-			hwgraph_vertex_unref(scan_vhdl);
-		scan++;i++;
-
-	}
-
-
-#endif
-	FIXME("device_admin_info_update");
-}
-
-/* looks up the static drv admin table ( created by the lboot) and the extended
- * drv admin table (created if at all by the kernel startup code) 
- * for this driver specific administration info and adds it to the admin info 
- * associated with this device driver's object
- */
-void
-device_driver_admin_info_update(device_driver_t	driver)
-{
-#ifdef LATER
-	int			i = 0;
-	dev_admin_info_t	*scan;
-
-	/* Check the static device driver administration info table */
-	scan = drv_admin_table;
-	while (i < drv_admin_table_size) {
-
-		if (strcmp(scan->dai_name,driver->dd_prefix) == 0) {
-			dev_admin_registry_add(&driver->dd_dev_admin_registry,
-						scan->dai_param_name,
-					 	scan->dai_param_val);
-		}
-		scan++;i++;
-	}
-	i = 0;
-	/* Check the extended device driver administration info table */
-	scan = extended_drv_admin_table;
-	while (i < extended_drv_admin_table_size) {
-
-		if (strcmp(scan->dai_name,driver->dd_prefix) == 0) {
-			dev_admin_registry_add(&driver->dd_dev_admin_registry,
-						scan->dai_param_name,
-					 	scan->dai_param_val);
-		}
-		scan++;i++;
-	}
-#endif
-	FIXME("device_driver_admin_info_update");
-}
-
-/* =====Device Driver Support===== */
-
-
-
-/*
-** Generic device driver support routines for use by kernel modules that
-** deal with device drivers (but NOT for use by the drivers themselves).
-** EVERY registered driver currently in the system -- static or loadable --
-** has an entry in the device_driver_hash table.  A pointer to such an entry
-** serves as a generic device driver handle.
-*/
-
-#define DEVICE_DRIVER_HASH_SIZE 32
-#ifdef LATER
-lock_t device_driver_lock[DEVICE_DRIVER_HASH_SIZE];
-device_driver_t device_driver_hash[DEVICE_DRIVER_HASH_SIZE];
-static struct string_table driver_prefix_string_table;
-#endif
-
-/*
-** Initialize device driver infrastructure.
-*/
-void
-device_driver_init(void)
-{
-#ifdef LATER
-	int i;
-	extern void alenlist_init(void);
-	extern void hwgraph_init(void);
-	extern void device_desc_init(void);
-
-	ASSERT(DEVICE_DRIVER_NONE == NULL);
-	alenlist_init();
-	hwgraph_init();
-	device_desc_init();
-
-	string_table_init(&driver_prefix_string_table);
-
-	for (i=0; i<DEVICE_DRIVER_HASH_SIZE; i++) {
-		spin_lock_init(&device_driver_lock[i]);
-		device_driver_hash[i] = NULL;
-	}
-
-	/* Initialize static drivers from master.c table */
-	for (i=0; i<static_devsw_count; i++) {
-		device_driver_t driver;
-		static_device_driver_desc_t desc;
-		int pri;
-
-		desc = &static_device_driver_table[i];
-		driver = device_driver_get(desc->sdd_prefix);
-		if (!driver)
-			driver = device_driver_alloc(desc->sdd_prefix);
-		pri = device_driver_sysgen_thread_pri_get(desc->sdd_prefix);
-		device_driver_thread_pri_set(driver, pri);
-		device_driver_devsw_put(driver, desc->sdd_bdevsw, desc->sdd_cdevsw);
-	}
-#endif
-	FIXME("device_driver_init");
-}
-
-/*
-** Hash a prefix string into a hash table chain.
-*/
-static int
-driver_prefix_hash(char *prefix)
-{
-#ifdef LATER
-	int accum = 0;
-	char nextchar;
-
-	while (nextchar = *prefix++)
-		accum = accum ^ nextchar;
-
-	return(accum % DEVICE_DRIVER_HASH_SIZE);
-#else
-	FIXME("driver_prefix_hash");
-	return(0);
-#endif
-}
-
-
-/*
-** Allocate a driver handle.
-** Returns the driver handle, or NULL if the driver prefix 
-** already has a handle.
-** 
-** Upper layers prevent races among device_driver_alloc,
-** device_driver_free, and device_driver_get*.
-*/
-device_driver_t
-device_driver_alloc(char *prefix)
-{
-#ifdef LATER
-	int which_hash;
-	device_driver_t new_driver;
-	unsigned long s;
-		
-	which_hash = driver_prefix_hash(prefix);
-
-	new_driver = kern_calloc(1, sizeof(*new_driver));
-	ASSERT(new_driver != NULL);
-	new_driver->dd_prev = NULL;
-	new_driver->dd_prefix = string_table_insert(&driver_prefix_string_table, prefix);
-	new_driver->dd_bdevsw = NULL;
-	new_driver->dd_cdevsw = NULL;
-
-	dev_admin_registry_init(&new_driver->dd_dev_admin_registry);
-	device_driver_admin_info_update(new_driver);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-#if DEBUG
-	{
-		device_driver_t drvscan;
-
-		/* Make sure we haven't already added a driver with this prefix */
-		drvscan = device_driver_hash[which_hash];
-		while (drvscan && 
-		        strcmp(drvscan->dd_prefix, prefix)) {
-			drvscan = drvscan->dd_next;
-		}
-
-		ASSERT(!drvscan);
-	}
-#endif /* DEBUG */
-
-
-	/* Add new_driver to front of hash chain. */
-	new_driver->dd_next = device_driver_hash[which_hash];
-	if (new_driver->dd_next)
-		new_driver->dd_next->dd_prev = new_driver;
-	device_driver_hash[which_hash] = new_driver;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	return(new_driver);
-#else
-	FIXME("device_driver_alloc");
-	return((device_driver_t)0);
-#endif
-}
-
-/*
-** Free a driver handle.
-**
-** Statically loaded drivers should never device_driver_free.
-** Dynamically loaded drivers device_driver_free when either an
-** unloaded driver is unregistered, or when an unregistered driver
-** is unloaded.
-*/
-void
-device_driver_free(device_driver_t driver)
-{
-#ifdef LATER
-	int which_hash;
-	unsigned long s;
-
-	if (!driver)
-		return;
-
-	which_hash = driver_prefix_hash(driver->dd_prefix);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-#if DEBUG
-	{
-		device_driver_t drvscan;
-
-		/* Make sure we're dealing with the right list */
-		drvscan = device_driver_hash[which_hash];
-		while (drvscan && (drvscan != driver))
-			drvscan = drvscan->dd_next;
-
-		ASSERT(drvscan);
-	}
-#endif /* DEBUG */
-
-	if (driver->dd_next)
-		driver->dd_next->dd_prev = driver->dd_prev;
-
-	if (driver->dd_prev)
-		driver->dd_prev->dd_next = driver->dd_next;
-	else
-		device_driver_hash[which_hash] = driver->dd_next;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	driver->dd_next = NULL;		/* sanity */
-	driver->dd_prev = NULL;		/* sanity */
-	driver->dd_prefix = NULL;	/* sanity */
-
-	if (driver->dd_bdevsw) {
-		driver->dd_bdevsw->d_driver = NULL;
-		driver->dd_bdevsw = NULL;
-	}
-
-	if (driver->dd_cdevsw) {
-		if (driver->dd_cdevsw->d_str) {
-			str_free_mux_node(driver);
-		}
-		driver->dd_cdevsw->d_driver = NULL;
-		driver->dd_cdevsw = NULL;
-	}
-
-	kern_free(driver);
-#endif
-	FIXME("device_driver_free");
-}
-
-
-/*
-** Given a device driver prefix, return a handle to the caller.
-*/
-device_driver_t
-device_driver_get(char *prefix)
-{
-#ifdef LATER
-	int which_hash;
-	device_driver_t drvscan;
-	unsigned long s;
-
-	if (prefix == NULL)
-		return(NULL);
-		
-	which_hash = driver_prefix_hash(prefix);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-	drvscan = device_driver_hash[which_hash];
-	while (drvscan && strcmp(drvscan->dd_prefix, prefix))
-		drvscan = drvscan->dd_next;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	return(drvscan);
-#else
-	FIXME("device_driver_get");
-	return((device_driver_t)0);
-#endif
-}
-
-
-/*
-** Given a block or char special file devfs_handle_t, find the 
-** device driver that controls it.
-*/
-device_driver_t
-device_driver_getbydev(devfs_handle_t device)
-{
-#ifdef LATER
-	struct bdevsw *my_bdevsw;
-	struct cdevsw *my_cdevsw;
-
-	my_cdevsw = get_cdevsw(device);
-	if (my_cdevsw != NULL)
-		return(my_cdevsw->d_driver);
-
-	my_bdevsw = get_bdevsw(device);
-	if (my_bdevsw != NULL)
-		return(my_bdevsw->d_driver);
-
-#endif
-	FIXME("device_driver_getbydev");
-	return((device_driver_t)0);
-}
-
-
-/*
-** Associate a driver with bdevsw/cdevsw pointers.
-**
-** Statically loaded drivers are permanently and automatically associated
-** with the proper bdevsw/cdevsw.  Dynamically loaded drivers associate
-** themselves when the driver is registered, and disassociate when the
-** driver unregisters.
-**
-** Returns 0 on success, -1 on failure (devsw already associated with driver)
-*/
-int
-device_driver_devsw_put(device_driver_t driver,
-			struct bdevsw *my_bdevsw,
-			struct cdevsw *my_cdevsw)
-{
-#ifdef LATER
-	int i;
-
-	if (!driver)
-		return(-1);
-
-	/* Trying to re-register data?  */
-	if (((my_bdevsw != NULL) && (driver->dd_bdevsw != NULL)) ||
-	    ((my_cdevsw != NULL) && (driver->dd_cdevsw != NULL)))
-		return(-1);
-
-	if (my_bdevsw != NULL) {
-		driver->dd_bdevsw = my_bdevsw;
-		my_bdevsw->d_driver = driver;
-		for (i = 0; i < bdevmax; i++) {
-			if (driver->dd_bdevsw->d_flags == bdevsw[i].d_flags) {
-				bdevsw[i].d_driver = driver;
-				break;
-			}
-		}
-	}
-
-	if (my_cdevsw != NULL) {
-		driver->dd_cdevsw = my_cdevsw;
-		my_cdevsw->d_driver = driver;
-		for (i = 0; i < cdevmax; i++) {
-			if (driver->dd_cdevsw->d_flags == cdevsw[i].d_flags) {
-				cdevsw[i].d_driver = driver;
-				break;
-			}
-		}
-	}
-#endif
-	FIXME("device_driver_devsw_put");
-	return(0);
-}
-
-
-/*
-** Given a driver, return the corresponding bdevsw and cdevsw pointers.
-*/
-void
-device_driver_devsw_get(	device_driver_t driver, 
-				struct bdevsw **bdevswp,
-				struct cdevsw **cdevswp)
-{
-	if (!driver) {
-		*bdevswp = NULL;
-		*cdevswp = NULL;
-	} else {
-		*bdevswp = driver->dd_bdevsw;
-		*cdevswp = driver->dd_cdevsw;
-	}
-}
-
-/*
- * device_driver_thread_pri_set
- *	Given a driver try to set its thread priority.
- *	Returns 0 on success , -1 on failure.
- */ 
-int
-device_driver_thread_pri_set(device_driver_t driver,ilvl_t pri)
-{
-	if (!driver)
-		return(-1);
-	driver->dd_thread_pri = pri;
-	return(0);
-}
-/*
- * device_driver_thread_pri_get
- * 	Given a driver return the driver thread priority.
- * 	If the driver is NULL return invalid driver thread
- * 	priority.
- */
-ilvl_t
-device_driver_thread_pri_get(device_driver_t driver)
-{
-	if (driver)
-		return(driver->dd_thread_pri);
-	else
-		return(DRIVER_THREAD_PRI_INVALID);
-}
-/*
-** Given a device driver, return it's handle (prefix).
-*/
-void
-device_driver_name_get(device_driver_t driver, char *buffer, int length)
-{
-	if (driver == NULL)
-		return;
-
-	strncpy(buffer, driver->dd_prefix, length);
-}
-
-
-/*
-** Associate a pointer-sized piece of information with a device.
-*/
-void 
-device_info_set(devfs_handle_t device, void *info)
-{
-#ifdef LATER
-	hwgraph_fastinfo_set(device, (arbitrary_info_t)info);
-#endif
-	FIXME("device_info_set");
-}
-
-
-/*
-** Retrieve a pointer-sized piece of information associated with a device.
-*/
-void *
-device_info_get(devfs_handle_t device)
-{
-#ifdef LATER
-	return((void *)hwgraph_fastinfo_get(device));
-#else
-	FIXME("device_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * Find the thread priority for a device, from the various
- * sysgen files.
- */
-int
-device_driver_sysgen_thread_pri_get(char *dev_prefix)
-{
-#ifdef LATER
-	int pri;
-	char *pri_s;
-	char *class;
-
-	extern default_intr_pri;
-	extern disk_intr_pri;
-	extern serial_intr_pri;
-	extern parallel_intr_pri;
-	extern tape_intr_pri;
-	extern graphics_intr_pri;
-	extern network_intr_pri;
-	extern scsi_intr_pri;
-	extern audio_intr_pri;
-	extern video_intr_pri;
-	extern external_intr_pri;
-	extern tserialio_intr_pri;
-
-	/* Check if there is a thread priority specified for
-	 * this driver's thread thru admin hints. If so 
-	 * use that value. Otherwise set it to its default
-	 * class value, otherwise set it to the default
-	 * value.
-	 */
-
-	if (pri_s = device_driver_admin_info_get(dev_prefix,
-						ADMIN_LBL_THREAD_PRI)) {
-		pri = atoi(pri_s);
-	} else if (class = device_driver_admin_info_get(dev_prefix,
-						ADMIN_LBL_THREAD_CLASS)) {
-		if (strcmp(class, "disk") == 0)
-			pri = disk_intr_pri;
-		else if (strcmp(class, "serial") == 0)
-			pri = serial_intr_pri;
-		else if (strcmp(class, "parallel") == 0)
-			pri = parallel_intr_pri;
-		else if (strcmp(class, "tape") == 0)
-			pri = tape_intr_pri;
-		else if (strcmp(class, "graphics") == 0)
-			pri = graphics_intr_pri;
-		else if (strcmp(class, "network") == 0)
-			pri = network_intr_pri;
-		else if (strcmp(class, "scsi") == 0)
-			pri = scsi_intr_pri;
-		else if (strcmp(class, "audio") == 0)
-			pri = audio_intr_pri;
-		else if (strcmp(class, "video") == 0)
-			pri = video_intr_pri;
-		else if (strcmp(class, "external") == 0)
-			pri = external_intr_pri;
-		else if (strcmp(class, "tserialio") == 0)
-			pri = tserialio_intr_pri;
-		else
-			pri = default_intr_pri;
-	} else
-		pri = default_intr_pri;
-
-	if (pri > 255)
-		pri = 255;
-	else if (pri < 0)
-		pri = 0;
-	return pri;
-#else
-	FIXME("device_driver_sysgen_thread_pri_get");
-	return(-1);
-#endif
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/eeprom.c linux/arch/ia64/sn/io/eeprom.c
--- linux.orig/arch/ia64/sn/io/eeprom.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/eeprom.c	2002-08-01 06:42:30.000000000 +0000
@@ -1,14 +1,11 @@
 /*
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 1999-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-
 /*
  * WARNING:     There is more than one copy of this file in different isms.
  *              All copies must be kept exactly in sync.
@@ -28,37 +25,24 @@
  *
  */
 
-/**************************************************************************
- *                                                                        *
- *  Copyright (C) 1999 Silicon Graphics, Inc.                             *
- *                                                                        *
- *  These coded instructions, statements, and computer programs  contain  *
- *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
- *  are protected by Federal copyright law.  They  may  not be disclosed  *
- *  to  third  parties  or copied or duplicated in any form, in whole or  *
- *  in part, without the prior written consent of Silicon Graphics, Inc.  *
- *                                                                        *
- **************************************************************************
- */
-
-
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
-/* #include <sys/SN/SN1/ip27log.h> */
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/clksupport.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/simulator.h>
 
 #if defined(EEPROM_DEBUG)
 #define db_printf(x) printk x
@@ -384,9 +368,6 @@
 
 int cbrick_uid_get( nasid_t nasid, uint64_t *uid )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     char uid_str[32];
     char msg[BRL1_QSIZE];
     int subch, len;
@@ -421,7 +402,7 @@
     }
     else {
 	scp = &sc;
-	sc_init( &sc, nasid, BRL1_LOCALUART );
+	sc_init( &sc, nasid, BRL1_LOCALHUB_UART );
     }
 
     /* fill in msg with the opcode & params */
@@ -455,15 +436,11 @@
     *uid = generate_unique_id( uid_str, strlen( uid_str ) );
 
     return EEP_OK;
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 
 int rbrick_uid_get( nasid_t nasid, net_vec_t path, uint64_t *uid )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     char uid_str[32];
     char msg[BRL1_QSIZE];
     int subch, len;
@@ -472,14 +449,12 @@
     if ( IS_RUNNING_ON_SIMULATOR() )
 	return EEP_L1;
 
-#ifdef BRINGUP
 #define FAIL								\
     {									\
 	*uid = rtc_time();						\
 	printk( "rbrick_uid_get failed; using current time as uid\n" );	\
 	return EEP_OK;							\
     }
-#endif /* BRINGUP */
 
     ROUTER_LOCK(path);
     sc_init( &sc, nasid, path );
@@ -520,7 +495,6 @@
     *uid = generate_unique_id( uid_str, strlen( uid_str ) );
 
     return EEP_OK;
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 int iobrick_uid_get( nasid_t nasid, uint64_t *uid )
@@ -593,12 +567,10 @@
 
 extern char *nic_vertex_info_get( devfs_handle_t );
 extern void nic_vmc_check( devfs_handle_t, char * );
-#ifdef BRINGUP
 /* the following were lifted from nic.c - change later? */
 #define MAX_INFO 2048
 #define NEWSZ(ptr,sz)   ((ptr) = kern_malloc((sz)))
 #define DEL(ptr) (kern_free((ptr)))
-#endif /* BRINGUP */
 
 char *eeprom_vertex_info_set( int component, int nasid, devfs_handle_t v,
                               net_vec_t path )
@@ -884,9 +856,6 @@
 int read_ia( l1sc_t *sc, int subch, int l1_compt, 
 	     int ia_code, char *eep_record )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     char msg[BRL1_QSIZE]; 	   /* message buffer */
     int len;              	   /* number of bytes used in message buffer */
     int ia_len = EEPROM_CHUNKSIZE; /* remaining bytes in info area */
@@ -936,16 +905,12 @@
     }
 
     return EEP_OK;
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 
 int read_spd( l1sc_t *sc, int subch, int l1_compt,
 	      eeprom_spd_u *spd )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     char msg[BRL1_QSIZE]; 	    /* message buffer */
     int len;              	    /* number of bytes used in message buffer */
     int resp;                       /* l1 response code */
@@ -1010,7 +975,6 @@
 	offset += EEPROM_CHUNKSIZE;
     }
     return EEP_OK;
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 
@@ -1068,7 +1032,7 @@
     if( (checksum & 0xff) != 0 )
     {
 	db_printf(( "read_chassis_ia: bad checksum\n" ));
-	db_printf(( "read_chassis_ia: target 0x%x  uart 0x%x\n",
+	db_printf(( "read_chassis_ia: target 0x%x  uart 0x%lx\n",
 			   sc->subch[subch].target, sc->uart ));
 	return EEP_BAD_CHECKSUM;
     }
@@ -1199,7 +1163,7 @@
     if( (checksum & 0xff) != 0 )
     {
 	db_printf(( "read_board_ia: bad checksum\n" ));
-	db_printf(( "read_board_ia: target 0x%x  uart 0x%x\n",
+	db_printf(( "read_board_ia: target 0x%x  uart 0x%lx\n",
 		    sc->subch[subch].target, sc->uart ));
 	return EEP_BAD_CHECKSUM;
     }
@@ -1211,9 +1175,6 @@
 int _cbrick_eeprom_read( eeprom_brd_record_t *buf, l1sc_t *scp,
 			 int component )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     int r;
     uint64_t uid = 0;
 #ifdef LOG_GETENV
@@ -1290,16 +1251,12 @@
 	return fake_an_eeprom_record( buf, component, uid );
     }
     return EEP_OK;
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 
 int cbrick_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid,
     		        int component )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     l1sc_t *scp;
     int local = (nasid == get_nasid());
 
@@ -1318,16 +1275,12 @@
     }
 
     return _cbrick_eeprom_read( buf, scp, component );
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 
 int iobrick_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid,
 			 int component )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     int r;
     int l1_compt, subch;
     l1sc_t *scp;
@@ -1391,16 +1344,12 @@
 	return r;
     }
     return EEP_OK;
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */    
 }
 
 
 int vector_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid,
 			net_vec_t path, int component )
 {
-#if !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-    return EEP_L1;
-#else
     int r;
     uint64_t uid = 0;
     int l1_compt, subch;
@@ -1470,5 +1419,4 @@
 	/* unsupported brick type */
 	return EEP_PARAM;
     }
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/efi-rtc.c linux/arch/ia64/sn/io/efi-rtc.c
--- linux.orig/arch/ia64/sn/io/efi-rtc.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/efi-rtc.c	2002-08-01 06:42:30.000000000 +0000
@@ -0,0 +1,185 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2001 by Ralf Baechle
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/errno.h>
+#include <asm/efi.h>
+#include <asm/sn/klclock.h>
+
+/*
+ * No locking necessary when this is called from efirtc which protects us
+ * from racing by efi_rtc_lock.
+ */
+#define __swizzle(addr) ((u8 *)((unsigned long)(addr) ^ 3))
+#define read_io_port(addr) (*(volatile u8 *) __swizzle(addr))
+#define write_io_port(addr, data) (*(volatile u8 *) __swizzle(addr) = (data))
+
+#define TOD_SGS_M48T35		1
+#define TOD_DALLAS_DS1386	2
+
+static unsigned long nvram_base = 0;
+static int tod_chip_type;
+
+static int
+get_tod_chip_type(void)
+{
+	unsigned char testval;
+
+	write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+	write_io_port(RTC_DAL_DAY_ADDR, 0xff);
+	write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+
+	testval = read_io_port(RTC_DAL_DAY_ADDR);
+	if (testval == 0xff)
+		return TOD_SGS_M48T35;
+
+	return TOD_DALLAS_DS1386;
+}
+
+efi_status_t
+ioc3_get_time(efi_time_t *time, efi_time_cap_t *caps)
+{
+	if (!nvram_base) {
+		printk(KERN_CRIT "nvram_base is zero\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	memset(time, 0, sizeof(*time));
+
+	switch (tod_chip_type) {
+	case TOD_SGS_M48T35:
+		write_io_port(RTC_SGS_CONTROL_ADDR, RTC_SGS_READ_PROTECT);
+
+		time->year = BCD_TO_INT(read_io_port(RTC_SGS_YEAR_ADDR)) + YRREF;
+		time->month = BCD_TO_INT(read_io_port(RTC_SGS_MONTH_ADDR));
+		time->day = BCD_TO_INT(read_io_port(RTC_SGS_DATE_ADDR));
+		time->hour = BCD_TO_INT(read_io_port(RTC_SGS_HOUR_ADDR));
+		time->minute = BCD_TO_INT(read_io_port(RTC_SGS_MIN_ADDR));
+		time->second = BCD_TO_INT(read_io_port(RTC_SGS_SEC_ADDR));
+		time->nanosecond = 0;
+
+		write_io_port(RTC_SGS_CONTROL_ADDR, 0);
+		break;
+
+	case TOD_DALLAS_DS1386:
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+
+		time->nanosecond = 0;
+		time->second = BCD_TO_INT(read_io_port(RTC_DAL_SEC_ADDR));
+		time->minute = BCD_TO_INT(read_io_port(RTC_DAL_MIN_ADDR));
+		time->hour = BCD_TO_INT(read_io_port(RTC_DAL_HOUR_ADDR));
+		time->day = BCD_TO_INT(read_io_port(RTC_DAL_DATE_ADDR));
+		time->month = BCD_TO_INT(read_io_port(RTC_DAL_MONTH_ADDR));
+		time->year = BCD_TO_INT(read_io_port(RTC_DAL_YEAR_ADDR)) + YRREF;
+
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+		break;
+
+	default:
+		break;
+	}
+
+	if (caps) {
+		caps->resolution = 50000000;	/*  50PPM */
+		caps->accuracy = 1000;		/*  1ms */
+		caps->sets_to_zero = 0;
+	}
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t ioc3_set_time (efi_time_t *t)
+{
+	if (!nvram_base) {
+		printk(KERN_CRIT "nvram_base is zero\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	switch (tod_chip_type) {
+	case TOD_SGS_M48T35:
+		write_io_port(RTC_SGS_CONTROL_ADDR, RTC_SGS_WRITE_ENABLE);
+        	write_io_port(RTC_SGS_YEAR_ADDR, INT_TO_BCD((t->year - YRREF)));
+		write_io_port(RTC_SGS_MONTH_ADDR,INT_TO_BCD(t->month));
+		write_io_port(RTC_SGS_DATE_ADDR, INT_TO_BCD(t->day));
+		write_io_port(RTC_SGS_HOUR_ADDR, INT_TO_BCD(t->hour));
+		write_io_port(RTC_SGS_MIN_ADDR,  INT_TO_BCD(t->minute));
+		write_io_port(RTC_SGS_SEC_ADDR,  INT_TO_BCD(t->second));
+		write_io_port(RTC_SGS_CONTROL_ADDR, 0);
+		break;
+
+	case TOD_DALLAS_DS1386:
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+		write_io_port(RTC_DAL_SEC_ADDR,  INT_TO_BCD(t->second));
+		write_io_port(RTC_DAL_MIN_ADDR,  INT_TO_BCD(t->minute));
+		write_io_port(RTC_DAL_HOUR_ADDR, INT_TO_BCD(t->hour));
+		write_io_port(RTC_DAL_DATE_ADDR, INT_TO_BCD(t->day));
+		write_io_port(RTC_DAL_MONTH_ADDR,INT_TO_BCD(t->month));
+		write_io_port(RTC_DAL_YEAR_ADDR, INT_TO_BCD((t->year - YRREF)));
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+		break;
+
+	default:
+		break;
+	}
+
+	return EFI_SUCCESS;
+}
+
+/* The following two are not supported atm.  */
+static efi_status_t
+ioc3_get_wakeup_time (efi_bool_t *enabled, efi_bool_t *pending, efi_time_t *tm)
+{
+	return EFI_UNSUPPORTED;
+}
+
+static efi_status_t
+ioc3_set_wakeup_time (efi_bool_t enabled, efi_time_t *tm)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/*
+ * It looks like the master IOC3 is usually on bus 0, device 4.  Hope
+ * that's right
+ */
+static __init int efi_ioc3_time_init(void)
+{
+	struct pci_dev *dev;
+	static struct ioc3 *ioc3;
+
+	dev = pci_find_slot(0, PCI_DEVFN(4, 0));
+	if (!dev) {
+		printk(KERN_CRIT "Couldn't find master IOC3\n");
+
+		return -ENODEV;
+	}
+
+	ioc3 = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
+	nvram_base = (unsigned long) ioc3 + IOC3_BYTEBUS_DEV0;
+
+	tod_chip_type = get_tod_chip_type();
+	if (tod_chip_type == 1)
+		printk(KERN_NOTICE "TOD type is SGS M48T35\n");
+	else if (tod_chip_type == 2)
+		printk(KERN_NOTICE "TOD type is Dallas DS1386\n");
+	else
+		printk(KERN_CRIT "No or unknown TOD\n");
+
+	efi.get_time = ioc3_get_time;
+	efi.set_time = ioc3_set_time;
+	efi.get_wakeup_time = ioc3_get_wakeup_time;
+	efi.set_wakeup_time = ioc3_set_wakeup_time;
+
+	return 0;
+}
+
+module_init(efi_ioc3_time_init);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/hcl.c linux/arch/ia64/sn/io/hcl.c
--- linux.orig/arch/ia64/sn/io/hcl.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/ia64/sn/io/hcl.c	2002-08-01 06:42:36.000000000 +0000
@@ -6,8 +6,7 @@
  *
  *  hcl - SGI's Hardware Graph compatibility layer.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -49,7 +48,6 @@
 /*
  * Some Global definitions.
  */
-spinlock_t hcl_spinlock;
 devfs_handle_t hcl_handle = NULL;
 
 invplace_t invplace_none = {
@@ -142,6 +140,7 @@
 {
 	extern void string_table_init(struct string_table *);
 	extern struct string_table label_string_table;
+	extern int init_ifconfig_net(void);
 	int rv = 0;
 
 #if defined(CONFIG_HCL_DEBUG) && !defined(MODULE)
@@ -153,8 +152,6 @@
 	printk ("\n%s: boot_options: 0x%0x\n", HCL_NAME, boot_options);
 #endif
 
-	spin_lock_init(&hcl_spinlock);
-
 	/*
 	 * Create the hwgraph_root on devfs.
 	 */
@@ -192,6 +189,12 @@
 		return(0);
 	}
 
+	/*
+	 * Initialize the ifconfgi_net driver that does network devices 
+	 * Persistent Naming.
+	 */
+	init_ifconfig_net();
+
 	return(0);
 
 }
@@ -238,8 +241,7 @@
 {
 
 	if (hcl_debug) {
-		printk("HCL: hwgraph_fastinfo_set handle 0x%p fastinfo %ld\n",
-			de, fastinfo);
+		printk("HCL: hwgraph_fastinfo_set handle 0x%p fastinfo %ld\n", (void *)de, fastinfo);
 	}
 		
 	labelcl_info_replace_IDX(de, HWGRAPH_FASTINFO, fastinfo, NULL);
@@ -466,7 +468,7 @@
 		 * We need to clean up!
 		 */
 		printk(KERN_WARNING "HCL: Unable to set the connect point to it's parent 0x%p\n",
-			new_devfs_handle);
+			(void *)new_devfs_handle);
 	}
 
         /*
@@ -1044,30 +1046,6 @@
 }
 
 /*
- * hwgraph_cdevsw_get - returns the fops of the given devfs entry.
- */
-struct file_operations *
-hwgraph_cdevsw_get(devfs_handle_t de)
-{
-	struct file_operations *fops = devfs_get_ops(de);
-
-	devfs_put_ops(de); /*  FIXME: this may need to be moved to callers  */
-	return(fops);
-}
-
-/*
- * hwgraph_bdevsw_get - returns the fops of the given devfs entry.
-*/
-struct file_operations *    /*  FIXME: shouldn't this be a blkdev?  */
-hwgraph_bdevsw_get(devfs_handle_t de)
-{
-	struct file_operations *fops = devfs_get_ops(de);
-
-	devfs_put_ops(de); /*  FIXME: this may need to be moved to callers  */
-	return(fops);
-}
-
-/*
 ** Inventory is now associated with a vertex in the graph.  For items that
 ** belong in the inventory but have no vertex 
 ** (e.g. old non-graph-aware drivers), we create a bogus vertex under the 
@@ -1550,6 +1528,4 @@
 EXPORT_SYMBOL(hwgraph_path_to_dev);
 EXPORT_SYMBOL(hwgraph_block_device_get);
 EXPORT_SYMBOL(hwgraph_char_device_get);
-EXPORT_SYMBOL(hwgraph_cdevsw_get);
-EXPORT_SYMBOL(hwgraph_bdevsw_get);
 EXPORT_SYMBOL(hwgraph_vertex_name_get);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/hcl_util.c linux/arch/ia64/sn/io/hcl_util.c
--- linux.orig/arch/ia64/sn/io/hcl_util.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/hcl_util.c	2002-08-01 06:42:46.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -14,6 +13,7 @@
 #include <linux/devfs_fs_kernel.h>
 #include <asm/sn/sgi.h>
 #include <asm/io.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/hubdev.c linux/arch/ia64/sn/io/hubdev.c
--- linux.orig/arch/ia64/sn/io/hubdev.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/hubdev.c	2002-08-01 06:42:46.000000000 +0000
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/sn1/hubdev.h>
 #include <asm/sn/sn_private.h>
@@ -42,7 +43,7 @@
         
         ASSERT(attach_method);
 
-        callout =  (hubdev_callout_t *)kmem_zalloc(sizeof(hubdev_callout_t), KM_SLEEP);
+        callout =  (hubdev_callout_t *)snia_kmem_zalloc(sizeof(hubdev_callout_t), KM_SLEEP);
         ASSERT(callout);
         
 	mutex_lock(&hubdev_callout_mutex);
@@ -104,6 +105,9 @@
  * Given a hub vertex, return the base address of the Hspec space
  * for that hub.
  */
+
+#if defined(CONFIG_IA64_SGI_SN1)
+
 caddr_t
 hubdev_prombase_get(devfs_handle_t hub)
 {
@@ -124,3 +128,5 @@
 
 	return hinfo->h_cnodeid;
 }
+
+#endif	/* CONFIG_IA64_SGI_SN1 */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/huberror.c linux/arch/ia64/sn/io/huberror.c
--- linux.orig/arch/ia64/sn/io/huberror.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/huberror.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,475 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Alan Mayer
- */
-
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <asm/smp.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
-#include <asm/sn/sn_private.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/synergy.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/xtalk/xtalk.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/intr.h>
-
-extern void hubni_eint_init(cnodeid_t cnode);
-extern void hubii_eint_init(cnodeid_t cnode);
-extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
-extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
-
-extern int maxcpus;
-
-#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
-
-
-void
-hub_error_clear(nasid_t nasid)
-{
-	int i;
-	hubreg_t idsr;
-	int sn;
-
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_PEND, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_A_CLR, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_B_CLR, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_0, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_1, 0);
-	}
-
-	REMOTE_HUB_L(nasid, MD_DIR_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_MEM_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_MISC1_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_PROTOCOL_ERR_CLR);
-
-    /*
-     * Make sure spurious write response errors are cleared
-     * (values are from hub_set_prb())
-     */
-    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
-        iprb_t prb;
-
-	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
-
-        /* Clear out some fields */
-        prb.iprb_ovflow = 1;
-        prb.iprb_bnakctr = 0;
-        prb.iprb_anakctr = 0;
-
-	/*
-	 * PIO reads in fire-and-forget mode on bedrock 1.0 don't
-	 * frob the credit count properly, making the responses appear
-	 * spurious.  So don't use fire-and-forget mode.  Bug 761802.
-	 */
-        prb.iprb_ff = 0;        /* disable fire-and-forget mode by default */
-
-        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
-
-        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
-    }
-
-    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
-    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
-    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
-
-    REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
-    /* No need to clear NI_PORT_HEADER regs; they are continually overwritten*/
-
-    REMOTE_HUB_S(nasid, LB_ERROR_MASK_CLR, -1);
-    REMOTE_HUB_S(nasid, LB_ERROR_HDR1, 0);
-
-    /* Clear XB error regs, in order */
-    for (i = 0;
-         i <= XB_FIRST_ERROR_CLEAR - XB_POQ0_ERROR_CLEAR;
-         i += sizeof(hubreg_t)) {
-        REMOTE_HUB_S(nasid, XB_POQ0_ERROR_CLEAR + i, 0);
-    }
-}
-
-
-/*
- * Function	: hub_error_init
- * Purpose	: initialize the error handling requirements for a given hub.
- * Parameters	: cnode, the compact nodeid.
- * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
- *			remote cpu, when this hub is headless.(cpuless)
- * Returns	: None
- */
-
-void
-hub_error_init(cnodeid_t cnode)
-{
-	nasid_t nasid;
-
-    nasid = cnodeid_to_nasid(cnode);
-    hub_error_clear(nasid);
-
-#ifdef ajm
-    if (cnode == 0) {
-	/*
-	 * Allocate log for storing the node specific error info
-	 */
-	for (i = 0; i < numnodes; i++) {
-	    kl_error_log[i]  = kmem_zalloc_node(sizeof(sn0_error_log_t), 
-						KM_NOSLEEP, i);
-	    hub_err_count[i] = kmem_zalloc_node(sizeof(hub_errcnt_t),
-						VM_DIRECT | KM_NOSLEEP, i);
-	    ASSERT_ALWAYS(kl_error_log[i] && hub_err_count[i]);
-	}
-    }
-
-    /*
-     * Assumption: There will be only one cpu who will initialize
-     * a hub. we need to setup the ii and each pi error interrupts.
-     * The SN1 hub (bedrock) has two PI, one for up to two processors.
-     */
-
-    if (cpuid_to_cnodeid(smp_processor_id()) == cnode) { 
-	int generic_intr_mask = PI_ERR_GENERIC; /* These interrupts are sent to only 1 CPU per NODE */
-
-	ASSERT_ALWAYS(kl_error_log[cnode]);
-	ASSERT_ALWAYS(hub_err_count[cnode]);
-	MD_ERR_LOG_INIT(kl_error_log[cnode]);
-
-	/* One for each CPU */
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 0));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 1));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 2));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 3));
-
-	/*
-	 * Setup error intr masks.
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		int cpuA_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_A);
-		int cpuB_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_B);
-
-		if (cpuA_present) {
-			if (cpuB_present) {		/* A && B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
-					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_A|generic_intr_mask));
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
-					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_B));
-
-			} else {			/* A && !B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
-					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_A|generic_intr_mask));
-			}
-			generic_intr_mask = 0;
-		} else {
-			if (cpuB_present) {		/* !A && B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
-					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_B|generic_intr_mask));
-				generic_intr_mask = 0;
-
-			} else {			/* !A && !B */
-				/* nothing to set up */
-			}
-		}
-	}
-
-	/*
-	 * Turn off UNCAC_UNCORR interrupt in the masks. Anyone interested
-	 * in these errors will peek at the int pend register to see if its
-	 * set.
-	 */ 
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_A);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, (misc & ~PI_ERR_UNCAC_UNCORR_A));
-		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_B);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, (misc & ~PI_ERR_UNCAC_UNCORR_B));
-	}
-
-	/*
-	 * enable all error indicators to turn on, in case of errors.
-	 *
-	 * This is not good on single cpu node boards.
-	 **** LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL);
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_A_CLR, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_B_CLR, 0);
-	}
-
-	/* Set up stack for each present processor */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_A)) {
-	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[0] =
-			SN0_ERROR_LOG(cnode)->el_spool_last_addr[0] =
-		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
-		}
-	    
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
-	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
-			SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
-		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-		}
-	}
-
-
-	PI_SPOOL_SIZE_BYTES = 
-	    ERR_STACK_SIZE_BYTES(REMOTE_HUB_L(nasid, PI_ERR_STACK_SIZE));
-
-#ifdef BRINGUP
-/* BRINGUP: The following code looks like a check to make sure
-the prom set up the error spool correctly for 2 processors.  I
-don't think it is needed.  */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
-			__psunsigned_t addr_a = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
-			__psunsigned_t addr_b = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-			if ((addr_a & ~0xff) == (addr_b & ~0xff)) {
-			    REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STACK_ADDR_B, 	
-					addr_b + PI_SPOOL_SIZE_BYTES);
-	
-			    SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
-				SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
-				    REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-	
-		    }
-		}
-	}
-#endif /* BRINGUP */
-
-	/* programming our own hub. Enable error_int_pend intr.
-	 * If both present, CPU A takes CPU b's error interrupts and any
-	 * generic ones. CPU B takes CPU A error ints.
-	 */
-	if (cause_intr_connect (SRB_ERR_IDX,
-				(intr_func_t)(hubpi_eint_handler),
-				SR_ALL_MASK|SR_IE)) {
-	    cmn_err(ERR_WARN, 
-		    "hub_error_init: cause_intr_connect failed on %d", cnode);
-	}
-    }
-    else {
-	/* programming remote hub. The only valid reason that this
-	 * is called will be on headless hubs. No interrupts 
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, 0); /* not necessary */
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, 0); /* not necessary */
-	}
-    }
-#endif /* ajm */
-    /*
-     * Now setup the hub ii and ni error interrupt handler.
-     */
-
-    hubii_eint_init(cnode);
-    hubni_eint_init(cnode);
-
-#ifdef ajm
-    /*** XXX FIXME XXX resolve the following***/
-    /* INT_PEND1 bits set up for one hub only:
-     *	SHUTDOWN_INTR
-     *	MD_COR_ERR_INTR
-     *  COR_ERR_INTR_A and COR_ERR_INTR_B should be sent to the
-     *  appropriate CPU only.
-     */
-
-    if (cnode == 0) {
-	    error_consistency_check.eps_state = 0;
-	    error_consistency_check.eps_cpuid = -1;
-	    spinlock_init(&error_consistency_check.eps_lock, "error_dump_lock");
-    }
-#endif
-
-    nodepda->huberror_ticks = HUB_ERROR_PERIOD;
-    return;
-}
-
-/*
- * Function	: hubii_eint_init
- * Parameters	: cnode
- * Purpose	: to initialize the hub iio error interrupt.
- * Assumptions	: Called once per hub, by the cpu which will ultimately
- *			handle this interrupt.
- * Returns	: None.
- */
-
-
-void
-hubii_eint_init(cnodeid_t cnode)
-{
-    int			bit, rv;
-    ii_iidsr_u_t    	hubio_eint;
-    hubinfo_t		hinfo; 
-    cpuid_t		intr_cpu;
-    devfs_handle_t 	hub_v;
-    ii_ilcsr_u_t	ilcsr;
-
-    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
-    ASSERT_ALWAYS(hub_v);
-    hubinfo_get(hub_v, &hinfo);
-
-    ASSERT(hinfo);
-    ASSERT(hinfo->h_cnodeid == cnode);
-
-    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
-
-    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
-	/* 
-	 * HUB II link is not up. 
-	 * Just disable LLP, and don't connect any interrupts.
-	 */
-	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
-	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
-	return;
-    }
-    /* Select a possible interrupt target where there is a free interrupt
-     * bit and also reserve the interrupt bit for this IO error interrupt
-     */
-    intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
-			      "HUB IO error interrupt",&bit);
-    if (intr_cpu == CPU_NONE) {
-	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
-	return;
-    }
-	
-    rv = intr_connect_level(intr_cpu, bit, 0,(intr_func_t)(NULL),
-			    (void *)(long)hub_v, NULL);
-    synergy_intr_connect(bit, intr_cpu);
-    request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, NULL, (void *)hub_v);
-    ASSERT_ALWAYS(rv >= 0);
-    hubio_eint.ii_iidsr_regval = 0;
-    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
-    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
-    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
-    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
-
-}
-
-void
-hubni_eint_init(cnodeid_t cnode)
-{
-    int intr_bit;
-    cpuid_t targ;
-
-
-    if ((targ = cnodeid_to_cpuid(cnode)) == CPU_NONE)
-	return;
-
-	/* The prom chooses which cpu gets these interrupts, but we
-	*  don't know which one it chose.  We will register all of the 
-	*  cpus to be sure.  This only costs us an irqaction per cpu.
-	*/
-    for (; targ < CPUS_PER_NODE; targ++) {
-	if (!cpu_enabled(targ) ) continue;
-	/* connect the INTEND1 bits. */
-	for (intr_bit = XB_ERROR; intr_bit <= MSC_PANIC_INTR; intr_bit++) {
-		intr_connect_level(targ, intr_bit, II_ERRORINT, NULL, NULL, NULL);
-	}
-	request_irq(SGI_HUB_ERROR_IRQ + (targ << 8), snia_error_intr_handler, 0, NULL, NULL);
-	/* synergy masks are initialized in the prom to enable all interrupts. */
-	/* We'll just leave them that way, here, for these interrupts. */
-    }
-}
-
-
-/*ARGSUSED*/
-void
-hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
-{
-    devfs_handle_t	hub_v;
-    hubinfo_t		hinfo; 
-    ii_wstat_u_t	wstat;
-    hubreg_t		idsr;
-
-	panic("Hubii interrupt\n");
-#ifdef ajm
-    /*
-     * If the NI has a problem, everyone has a problem.  We shouldn't
-     * even attempt to handle other errors when an NI error is present.
-     */
-    if (check_ni_errors()) {
-	hubni_error_handler("II interrupt", 1);
-	/* NOTREACHED */
-    }
-
-    /* two levels of casting avoids compiler warning.!! */
-    hub_v = (devfs_handle_t)(long)(arg); 
-    ASSERT(hub_v);
-
-    hubinfo_get(hub_v, &hinfo);
-    
-    /* 
-     * Identify the reason for error. 
-     */
-    wstat.ii_wstat_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_WSTAT);
-
-    if (wstat.ii_wstat_fld_s.w_crazy) {
-	char	*reason;
-	/*
-	 * We can do a couple of things here. 
-	 * Look at the fields TX_MX_RTY/XT_TAIL_TO/XT_CRD_TO to check
-	 * which of these caused the CRAZY bit to be set. 
-	 * You may be able to check if the Link is up really.
-	 */
-	if (wstat.ii_wstat_fld_s.w_tx_mx_rty)
-		reason = "Micro Packet Retry Timeout";
-	else if (wstat.ii_wstat_fld_s.w_xt_tail_to)
-		reason = "Crosstalk Tail Timeout";
-	else if (wstat.ii_wstat_fld_s.w_xt_crd_to)
-		reason = "Crosstalk Credit Timeout";
-	else {
-		hubreg_t	hubii_imem;
-		/*
-		 * Check if widget 0 has been marked as shutdown, or
-		 * if BTE 0/1 has been marked.
-		 */
-		hubii_imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
-		if (hubii_imem & IIO_IMEM_W0ESD)
-			reason = "Hub Widget 0 has been Shutdown";
-		else if (hubii_imem & IIO_IMEM_B0ESD)
-			reason = "BTE 0 has been shutdown";
-		else if (hubii_imem & IIO_IMEM_B1ESD)
-			reason = "BTE 1 has been shutdown";
-		else	reason = "Unknown";
-	
-	}
-	/*
-	 * Note: we may never be able to print this, if the II talking
-	 * to Xbow which hosts the console is dead. 
-	 */
-	printk("Hub %d to Xtalk Link failed (II_ECRAZY) Reason: %s", 
-		hinfo->h_cnodeid, reason);
-    }
-
-    /* 
-     * It's a toss as to which one among PRB/CRB to check first. 
-     * Current decision is based on the severity of the errors. 
-     * IO CRB errors tend to be more severe than PRB errors.
-     *
-     * It is possible for BTE errors to have been handled already, so we
-     * may not see any errors handled here. 
-     */
-    (void)hubiio_crb_error_handler(hub_v, hinfo);
-    (void)hubiio_prb_error_handler(hub_v, hinfo);
-    /*
-     * If we reach here, it indicates crb/prb handlers successfully
-     * handled the error. So, re-enable II to send more interrupt
-     * and return.
-     */
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, 0xffffff);
-    idsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR) & ~IIO_IIDSR_SENT_MASK;
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, idsr);
-#endif /* ajm */
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/hubspc.c linux/arch/ia64/sn/io/hubspc.c
--- linux.orig/arch/ia64/sn/io/hubspc.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/ia64/sn/io/hubspc.c	2002-08-01 06:42:29.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /*
@@ -19,6 +18,8 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <linux/devfs_fs.h>
 #include <linux/devfs_fs_kernel.h>
 #include <asm/io.h>
@@ -26,18 +27,12 @@
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-#include <asm/sn/mem_refcnt.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/sn1/mem_refcnt.h>
 #include <asm/sn/addrs.h>
-
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/ip27config.h>
-#include <asm/sn/sn1/hubdev.h>
+#include <asm/sn/snconfig.h>
+#include <asm/sn/sn1/hubspc.h>
 #include <asm/sn/ksys/elsc.h>
-#endif
-
-#include <asm/sn/hubspc.h>
+#include <asm/sn/simulator.h>
 
 
 /* Uncomment the following line for tracing */
@@ -45,10 +40,6 @@
 
 int hubspc_devflag = D_MP;
 
-extern void *device_info_get(devfs_handle_t device);
-extern void device_info_set(devfs_handle_t device, void *info);
-
-
 
 /***********************************************************************/
 /* CPU Prom Space 						       */
@@ -127,9 +118,8 @@
 	return 0;
 }
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1)
 #define	SN_PROMVERSION		INV_IP35PROM
-#endif
 
 /* Add "detailed" labelled inventory information to the
  * prom vertex 
@@ -159,7 +149,6 @@
 	cpuprom_inventory_info->im_rev = IP27CONFIG.pvers_rev;
 	cpuprom_inventory_info->im_version = IP27CONFIG.pvers_vers;
 
-
 	/* Store this info as labelled information hanging off the
 	 * prom device vertex
 	 */
@@ -172,41 +161,17 @@
 				sizeof(invent_miscinfo_t));
 }
 
-int
-cpuprom_attach(devfs_handle_t node)
-{
-        devfs_handle_t prom_dev;
-
-        hwgraph_char_device_add(node, EDGE_LBL_PROM, "hubspc_", &prom_dev);
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc: prom_attach hub: 0x%x prom: 0x%x\n", node, prom_dev);
-#endif	/* HUBSPC_DEBUG */
-	device_inventory_add(prom_dev, INV_PROM, SN_PROMVERSION,
-				(major_t)0, (minor_t)0, 0);
-
-	/* Add additional inventory info about the cpu prom like
-	 * revision & version numbers etc.
-	 */
-	cpuprom_detailed_inventory_info_add(prom_dev,node);
-        device_info_set(prom_dev, (void*)(ulong)HUBSPC_PROM);
-	prominfo_add(node, prom_dev);
-
-        return (0);
-}
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #define FPROM_CONFIG_ADDR	MD_JUNK_BUS_TIMING
 #define FPROM_ENABLE_MASK	MJT_FPROM_ENABLE_MASK
 #define FPROM_ENABLE_SHFT	MJT_FPROM_ENABLE_SHFT
 #define FPROM_SETUP_MASK	MJT_FPROM_SETUP_MASK
 #define FPROM_SETUP_SHFT	MJT_FPROM_SETUP_SHFT
-#endif
 
 /*ARGSUSED*/
 int
 cpuprom_map(devfs_handle_t dev, vhandl_t *vt, off_t addr, size_t len)
 {
-        int 		errcode;
+        int 		errcode = 0;
 	caddr_t 	kvaddr;
 	devfs_handle_t		node;
 	cnodeid_t 	cnode;
@@ -220,7 +185,7 @@
 	kvaddr = hubdev_prombase_get(node);
 	cnode  = hubdev_cnodeid_get(node);
 #ifdef	HUBSPC_DEBUG
-	printf("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr);
+	printk("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr);
 #endif
 
 	if (len > RBOOT_SIZE)
@@ -251,6 +216,7 @@
 	}
         return (errcode);
 }
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 /*ARGSUSED*/
 int
@@ -263,8 +229,6 @@
 /* Base Hub Space Driver                                               */
 /***********************************************************************/
 
-// extern int l1_attach( devfs_handle_t );
-
 /*
  * hubspc_init
  * Registration of the hubspc devices with the hub manager
@@ -277,24 +241,19 @@
          */
 
         /* The reference counters */
+#if defined(CONFIG_IA64_SGI_SN1)
         hubdev_register(mem_refcnt_attach);
+#endif
 
-	/* Prom space */
-	hubdev_register(cpuprom_attach);
-
-#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
 	/* L1 system controller link */
 	if ( !IS_RUNNING_ON_SIMULATOR() ) {
 		/* initialize the L1 link */
-		void l1_cons_init( l1sc_t *sc );
-		elsc_t *get_elsc(void);
-
-		l1_cons_init((l1sc_t *)get_elsc());
+		extern void l1_init(void);
+		l1_init();
 	}
-#endif
 
 #ifdef	HUBSPC_DEBUG
-	printf("hubspc_init: Completed\n");
+	printk("hubspc_init: Completed\n");
 #endif	/* HUBSPC_DEBUG */
 	/* Initialize spinlocks */
 	mutex_spinlock_init(&cpuprom_spinlock);
@@ -304,26 +263,7 @@
 int
 hubspc_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(*devp)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_open(devp, oflag, otyp, crp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_open: Completed open for type %d\n",
-               (hubspc_subdevice_t)(ulong)device_info_get(*devp));
-#endif	/* HUBSPC_DEBUG */
-
-        return (errcode);
+        return (0);
 }
 
 
@@ -331,25 +271,7 @@
 int
 hubspc_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_close(dev, oflag, otyp, crp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_close: Completed close for type %d\n",
-               (hubspc_subdevice_t)(ulong)device_info_get(dev));
-#endif	/* HUBSPC_DEBUG */
-
-        return (errcode);
+        return (0);
 }
 
 /* ARGSUSED */
@@ -357,7 +279,6 @@
 hubspc_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
 {
 	/*REFERENCED*/
-        hubspc_subdevice_t subdevice;
         int errcode = 0;
 
 	/* check validity of request */
@@ -365,30 +286,6 @@
 		return ENXIO;
         }
 
-        subdevice = (hubspc_subdevice_t)(ulong)device_info_get(dev);
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_map: subdevice: %d vaddr: 0x%x phyaddr: 0x%x len: 0x%x\n",
-	       subdevice, v_getaddr(vt), off, len);
-#endif /* HUBSPC_DEBUG */
-
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_mmap(dev, vt, off, len, prot);
-                break;
-
-        case HUBSPC_PROM:
-		errcode = cpuprom_map(dev, vt, off, len);
-                break;
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_map finished: spctype: %d vaddr: 0x%x len: 0x%x\n",
-	       (hubspc_subdevice_t)(ulong)device_info_get(dev), v_getaddr(vt), len);
-#endif /* HUBSPC_DEBUG */
-
 	return errcode;
 }
 
@@ -396,21 +293,7 @@
 int
 hubspc_unmap(devfs_handle_t dev, vhandl_t *vt)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_unmap(dev, vt);
-                break;
-
-        case HUBSPC_PROM:
-                errcode = cpuprom_unmap(dev, vt);
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-	return errcode;
+	return (0);
 
 }
 
@@ -423,19 +306,6 @@
              cred_t *cred_p,
              int *rvalp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_ioctl(dev, cmd, arg, mode, cred_p, rvalp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-	return errcode;
+	return (0);
 
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/ifconfig_net.c linux/arch/ia64/sn/io/ifconfig_net.c
--- linux.orig/arch/ia64/sn/io/ifconfig_net.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/ifconfig_net.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,298 @@
+/* $Id: ifconfig_net.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *  ifconfig_net - SGI's Persistent Network Device names.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <asm/sn/sgi.h>
+#include <linux/devfs_fs.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/ifconfig_net.h>
+
+#define SGI_IFCONFIG_NET "SGI-PERSISTENT NETWORK DEVICE NAME DRIVER"
+#define SGI_IFCONFIG_NET_VERSION "1.0"
+
+/*
+ * Some Global definitions.
+ */
+devfs_handle_t ifconfig_net_handle = NULL;
+unsigned long ifconfig_net_debug = 0;
+
+/*
+ * ifconfig_net_open - Opens the special device node "/devhw/.ifconfig_net".
+ */
+static int ifconfig_net_open(struct inode * inode, struct file * filp)
+{
+	if (ifconfig_net_debug) {
+        	printk("ifconfig_net_open called.\n");
+	}
+
+        return(0);
+
+}
+
+/*
+ * ifconfig_net_close - Closes the special device node "/devhw/.ifconfig_net".
+ */
+static int ifconfig_net_close(struct inode * inode, struct file * filp)
+{
+
+	if (ifconfig_net_debug) {
+        	printk("ifconfig_net_close called.\n");
+	}
+
+        return(0);
+}
+
+/*
+ * assign_ifname - Assign the next available interface name from the persistent list.
+ */
+void
+assign_ifname(struct net_device *dev,
+		  struct ifname_num *ifname_num)
+
+{
+
+	/*
+	 * Handle eth devices.
+	 */
+        if ( (memcmp(dev->name, "eth", 3) == 0) ) {
+		if (ifname_num->next_eth != -1) {
+			/*
+			 * Assign it the next available eth interface number. 
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "eth%d", (int)ifname_num->next_eth);
+			ifname_num->next_eth++;
+		} 
+
+                return;
+        }
+
+	/*
+	 * Handle fddi devices.
+	 */
+	if ( (memcmp(dev->name, "fddi", 4) == 0) ) {
+		if (ifname_num->next_fddi != -1) {
+			/*
+			 * Assign it the next available fddi interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "fddi%d", (int)ifname_num->next_fddi);
+			ifname_num->next_fddi++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle hip devices.
+	 */
+	if ( (memcmp(dev->name, "hip", 3) == 0) ) {
+		if (ifname_num->next_hip != -1) {
+			/*
+			 * Assign it the next available hip interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "hip%d", (int)ifname_num->next_hip);
+			ifname_num->next_hip++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle tr devices.
+	 */
+	if ( (memcmp(dev->name, "tr", 2) == 0) ) {
+		if (ifname_num->next_tr != -1) {
+			/*
+			 * Assign it the next available tr interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "tr%d", (int)ifname_num->next_tr);
+			ifname_num->next_tr++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle fc devices.
+	 */
+	if ( (memcmp(dev->name, "fc", 2) == 0) ) {
+		if (ifname_num->next_fc != -1) {
+			/*
+			 * Assign it the next available fc interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "fc%d", (int)ifname_num->next_fc);
+			ifname_num->next_fc++;
+		}
+
+		return;
+	}
+}
+
+/*
+ * find_persistent_ifname: Returns the entry that was seen in previous boot.
+ */
+struct ifname_MAC *
+find_persistent_ifname(struct net_device *dev,
+	struct ifname_MAC *ifname_MAC)
+
+{
+
+	while (ifname_MAC->addr_len) {
+		if (memcmp(dev->dev_addr, ifname_MAC->dev_addr, dev->addr_len) == 0)
+			return(ifname_MAC);
+
+		ifname_MAC++;
+	}
+
+	return(NULL);
+}
+
+/*
+ * ifconfig_net_ioctl: ifconfig_net driver ioctl interface.
+ */
+static int ifconfig_net_ioctl(struct inode * inode, struct file * file,
+        unsigned int cmd, unsigned long arg)
+{
+
+	extern struct net_device *__dev_get_by_name(const char *);
+#ifdef CONFIG_NET
+	struct net_device *dev;
+	struct ifname_MAC *found;
+	char temp[64];
+#endif
+	struct ifname_MAC *ifname_MAC;
+	struct ifname_MAC *new_devices, *temp_new_devices;
+	struct ifname_num *ifname_num;
+	unsigned long size;
+
+
+	if (ifconfig_net_debug) {
+		printk("HCL: hcl_ioctl called.\n");
+	}
+
+	/*
+	 * Read in the header and see how big of a buffer we really need to 
+	 * allocate.
+	 */
+	ifname_num = (struct ifname_num *) kmalloc(sizeof(struct ifname_num), 
+			GFP_KERNEL);
+	copy_from_user( ifname_num, (char *) arg, sizeof(struct ifname_num));
+	size = ifname_num->size;
+	kfree(ifname_num);
+	ifname_num = (struct ifname_num *) kmalloc(size, GFP_KERNEL);
+	ifname_MAC = (struct ifname_MAC *) ((char *)ifname_num + (sizeof(struct ifname_num)) );
+
+	copy_from_user( ifname_num, (char *) arg, size);
+	new_devices =  kmalloc(size - sizeof(struct ifname_num), GFP_KERNEL);
+	temp_new_devices = new_devices;
+
+	memset(new_devices, 0, size - sizeof(struct ifname_num));
+
+#ifdef CONFIG_NET
+	/*
+	 * Go through the net device entries and make them persistent!
+	 */
+	for (dev = dev_base; dev != NULL; dev = dev->next) {
+		/*
+		 * Skip NULL entries or "lo"
+		 */
+		if ( (dev->addr_len == 0) || ( !strncmp(dev->name, "lo", strlen(dev->name))) ){
+			continue;
+		}
+
+		/*
+		 * See if we have a persistent interface name for this device.
+		 */
+		found = NULL;
+		found = find_persistent_ifname(dev, ifname_MAC);
+		if (found) {
+			strcpy(dev->name, found->name);
+		} else {
+			/* Never seen this before .. */
+			assign_ifname(dev, ifname_num);
+
+			/* 
+			 * Save the information for the next boot.
+			 */
+ 			sprintf(temp,"%s %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
+				dev->dev_addr[0],  dev->dev_addr[1],  dev->dev_addr[2],
+				dev->dev_addr[3],  dev->dev_addr[4],  dev->dev_addr[5]);
+			strcpy(temp_new_devices->name, dev->name);
+			temp_new_devices->addr_len = dev->addr_len;
+			memcpy(temp_new_devices->dev_addr, dev->dev_addr, dev->addr_len);
+			temp_new_devices++;
+		}
+		
+	}
+#endif
+
+	/*
+	 * Copy back to the User Buffer area any new devices encountered.
+	 */
+	copy_to_user((char *)arg + (sizeof(struct ifname_num)), new_devices, 
+			size - sizeof(struct ifname_num));
+
+	return(0);
+
+}
+
+struct file_operations ifconfig_net_fops = {
+	ioctl:ifconfig_net_ioctl,	/* ioctl */
+	open:ifconfig_net_open,		/* open */
+	release:ifconfig_net_close	/* release */
+};
+
+
+/*
+ * init_ifconfig_net() - Boot time initialization.  Ensure that it is called 
+ *	after devfs has been initialized.
+ *
+ */
+#ifdef MODULE
+int init_module (void)
+#else
+int __init init_ifconfig_net(void)
+#endif
+{
+	ifconfig_net_handle = NULL;
+	ifconfig_net_handle = hwgraph_register(hwgraph_root, ".ifconfig_net",
+			0, DEVFS_FL_AUTO_DEVNUM,
+			0, 0,
+			S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+			&ifconfig_net_fops, NULL);
+
+	if (ifconfig_net_handle == NULL) {
+		panic("Unable to create SGI PERSISTENT NETWORK DEVICE Name Driver.\n");
+	}
+
+	return(0);
+
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/invent.c linux/arch/ia64/sn/io/invent.c
--- linux.orig/arch/ia64/sn/io/invent.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/invent.c	2002-08-01 06:42:44.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/io.c linux/arch/ia64/sn/io/io.c
--- linux.orig/arch/ia64/sn/io/io.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/io.c	2002-08-01 06:42:42.000000000 +0000
@@ -1,36 +1,50 @@
-/* $Id$
+/* $Id: io.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 
 #include <linux/types.h>
-#include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
 #include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
-#include <asm/sn/agent.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 #include <asm/sn/klconfig.h>
-#include <asm/sn/io.h>
 #include <asm/sn/sn_cpuid.h>
 
 extern xtalk_provider_t hub_provider;
+extern void hub_intr_init(devfs_handle_t hubv);
+
+
+/*      
+ * hub_device_desc_update               
+ *      Update the passed in device descriptor with the actual the
+ *      target cpu number and interrupt priority level.
+ *      NOTE : These might be the same as the ones passed in thru
+ *      the descriptor.
+ */     
+void
+hub_device_desc_update(device_desc_t    dev_desc,
+                       ilvl_t           intr_swlevel, 
+                       cpuid_t          cpu)
+{       
+}
+
 
 /*
  * Perform any initializations needed to support hub-based I/O.
@@ -63,7 +77,7 @@
 /*
  * Setup pio structures needed for a particular hub.
  */
-static void
+void
 hub_pio_init(devfs_handle_t hubv)
 {
 	xwidgetnum_t widget;
@@ -386,7 +400,7 @@
 
 
 /* ARGSUSED */
-static void
+void
 hub_dma_init(devfs_handle_t hubv)
 {
 }
@@ -411,7 +425,7 @@
 	xwidgetnum_t widget = xwidget_info_id_get(widget_info);
 	devfs_handle_t hubv = xwidget_info_master_get(widget_info);
 
-	dmamap = kern_malloc(sizeof(struct hub_dmamap_s));
+	dmamap = kmalloc(sizeof(struct hub_dmamap_s), GFP_ATOMIC);
 	dmamap->hdma_xtalk_info.xd_dev = dev;
 	dmamap->hdma_xtalk_info.xd_target = widget;
 	dmamap->hdma_hub = hubv;
@@ -454,9 +468,9 @@
 	    if (!(dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_addr re-uses dmamap.\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_addr re-uses dmamap.\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_addr re-uses dmamap.\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_addr re-uses dmamap.\n", (void *)vhdl);
 #endif
 	    }
 	} else {
@@ -487,9 +501,9 @@
 	    if (!(hub_dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = hub_dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_list re-uses dmamap\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_list re-uses dmamap\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_list re-uses dmamap\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_list re-uses dmamap\n", (void *)vhdl);
 #endif
 	    }
 	} else {
@@ -516,9 +530,9 @@
 	    if (!(hub_dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = hub_dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_done already done with dmamap\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_done already done with dmamap\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_done already done with dmamap\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_done already done with dmamap\n", (void *)vhdl);
 #endif
 	    }
 	}
@@ -581,329 +595,6 @@
 
 
 
-/* INTERRUPT MANAGEMENT */
-
-/* ARGSUSED */
-static void
-hub_intr_init(devfs_handle_t hubv)
-{
-}
-
-/*
- * hub_device_desc_update
- *	Update the passed in device descriptor with the actual the
- * 	target cpu number and interrupt priority level.
- *	NOTE : These might be the same as the ones passed in thru
- *	the descriptor.
- */
-static void
-hub_device_desc_update(device_desc_t 	dev_desc, 
-		       ilvl_t 		intr_swlevel,
-		       cpuid_t		cpu)
-{
-	char	cpuname[40];
-	
-	/* Store the interrupt priority level in the device descriptor */
-	device_desc_intr_swlevel_set(dev_desc, intr_swlevel);
-
-	/* Convert the cpuid to the vertex handle in the hwgraph and
-	 * save it in the device descriptor.
-	 */
-	sprintf(cpuname,"/hw/cpunum/%ld",cpu);
-	device_desc_intr_target_set(dev_desc, 
-				    hwgraph_path_to_dev(cpuname));
-}
-
-int allocate_my_bit = INTRCONNECT_ANYBIT;
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-static hub_intr_t
-do_hub_intr_alloc(devfs_handle_t dev,		/* which crosstalk device */
-		  device_desc_t dev_desc,	/* device descriptor */
-		  devfs_handle_t owner_dev,	/* owner of this interrupt, if known */
-		  int uncond_nothread)		/* unconditionally non-threaded */
-{
-	cpuid_t cpu = (cpuid_t)0;			/* cpu to receive interrupt */
-        int cpupicked = 0;
-	int bit;			/* interrupt vector */
-	/*REFERENCED*/
-	int intr_resflags = 0;
-	hub_intr_t intr_hdl;
-	cnodeid_t nodeid;		/* node to receive interrupt */
-	/*REFERENCED*/
-	nasid_t nasid;			/* nasid to receive interrupt */
-	struct xtalk_intr_s *xtalk_info;
-	iopaddr_t xtalk_addr;		/* xtalk addr on hub to set intr */
-	xwidget_info_t xwidget_info;	/* standard crosstalk widget info handle */
-	char *intr_name = NULL;
-	ilvl_t intr_swlevel;
-	extern int default_intr_pri;
-#ifdef CONFIG_IA64_SGI_SN1 
-	extern void synergy_intr_alloc(int, int);
-#endif
-	
-	/*
-	 * If caller didn't explicily specify a device descriptor, see if there's
-	 * a default descriptor associated with the device.
-	 */
-	if (!dev_desc) 
-		dev_desc = device_desc_default_get(dev);
-
-	if (dev_desc) {
-		intr_name = device_desc_intr_name_get(dev_desc);
-		intr_swlevel = device_desc_intr_swlevel_get(dev_desc);
-		if (dev_desc->flags & D_INTR_ISERR) {
-			intr_resflags = II_ERRORINT;
-		} else if (!uncond_nothread && !(dev_desc->flags & D_INTR_NOTHREAD)) {
-			intr_resflags = II_THREADED;
-		} else {
-			/* Neither an error nor a thread. */
-			intr_resflags = 0;
-		}
-	} else {
-		intr_swlevel = default_intr_pri;
-		if (!uncond_nothread)
-			intr_resflags = II_THREADED;
-	}
-
-	/* XXX - Need to determine if the interrupt should be threaded. */
-
-	/* If the cpu has not been picked already then choose a candidate 
-	 * interrupt target and reserve the interrupt bit 
-	 */
-#if defined(NEW_INTERRUPTS)
-	if (!cpupicked) {
-		cpu = intr_heuristic(dev,dev_desc,allocate_my_bit,
-				     intr_resflags,owner_dev,
-				     intr_name,&bit);
-	}
-#endif
-
-	/* At this point we SHOULD have a valid cpu */
-	if (cpu == CPU_NONE) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v hub_intr_alloc could not allocate interrupt\n",
-			owner_dev);
-#else
-		PRINT_WARNING("0x%x hub_intr_alloc could not allocate interrupt\n",
-			owner_dev);
-#endif
-		return(0);
-
-	}
-
-	/* If the cpu has been picked already (due to the bridge data 
-	 * corruption bug) then try to reserve an interrupt bit .
-	 */
-#if defined(NEW_INTERRUPTS)
-	if (cpupicked) {
-		bit = intr_reserve_level(cpu, allocate_my_bit, 
-					 intr_resflags, 
-					 owner_dev, intr_name);
-		if (bit < 0) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Could not reserve an interrupt bit for cpu "
-				" %d and dev %v\n",
-				cpu,owner_dev);
-#else
-			PRINT_WARNING("Could not reserve an interrupt bit for cpu "
-				" %d and dev 0x%x\n",
-				cpu, owner_dev);
-#endif
-				
-			return(0);
-		}
-	}
-#endif	/* NEW_INTERRUPTS */
-
-	nodeid = cpuid_to_cnodeid(cpu);
-	nasid = cpuid_to_nasid(cpu);
-	xtalk_addr = HUBREG_AS_XTALKADDR(nasid, PIREG(PI_INT_PEND_MOD, cpuid_to_subnode(cpu)));
-
-	/*
-	 * Allocate an interrupt handle, and fill it in.  There are two
-	 * pieces to an interrupt handle: the piece needed by generic
-	 * xtalk code which is used by crosstalk device drivers, and
-	 * the piece needed by low-level IP27 hardware code.
-	 */
-	intr_hdl = kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, nodeid);
-	ASSERT_ALWAYS(intr_hdl);
-
-	/* 
-	 * Fill in xtalk information for generic xtalk interfaces that
-	 * operate on xtalk_intr_hdl's.
-	 */
-	xtalk_info = &intr_hdl->i_xtalk_info;
-	xtalk_info->xi_dev = dev;
-	xtalk_info->xi_vector = bit;
-	xtalk_info->xi_addr = xtalk_addr;
-
-	/*
-	 * Regardless of which CPU we ultimately interrupt, a given crosstalk
-	 * widget always handles interrupts (and PIO and DMA) through its 
-	 * designated "master" crosstalk provider.
-	 */
-	xwidget_info = xwidget_info_get(dev);
-	if (xwidget_info)
-		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
-
-	/* Fill in low level hub information for hub_* interrupt interface */
-	intr_hdl->i_swlevel = intr_swlevel;
-	intr_hdl->i_cpuid = cpu;
-	intr_hdl->i_bit = bit;
-	intr_hdl->i_flags = HUB_INTR_IS_ALLOCED;
-
-	/* Store the actual interrupt priority level & interrupt target
-	 * cpu back in the device descriptor.
-	 */
-	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
-#ifdef CONFIG_IA64_SGI_SN1
-	synergy_intr_alloc((int)bit, (int)cpu);
-#endif
-	return(intr_hdl);
-}
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-hub_intr_t
-hub_intr_alloc(	devfs_handle_t dev,		/* which crosstalk device */
-		device_desc_t dev_desc,		/* device descriptor */
-		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
-{
-	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
-}
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Uncondtionally request non-threaded, regardless of what the device
- * descriptor might say.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-hub_intr_t
-hub_intr_alloc_nothd(devfs_handle_t dev,		/* which crosstalk device */
-		device_desc_t dev_desc,		/* device descriptor */
-		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
-{
-	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
-}
-
-/*
- * Free resources consumed by intr_alloc.
- */
-void
-hub_intr_free(hub_intr_t intr_hdl)
-{
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-	xtalk_intr_t xtalk_info;
-
-	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
-		/* Setting the following fields in the xtalk interrupt info
-	 	 * clears the interrupt target register in the xtalk user
-	 	 */
-		xtalk_info = &intr_hdl->i_xtalk_info;
-		xtalk_info->xi_dev = NODEV;
-		xtalk_info->xi_vector = 0;
-		xtalk_info->xi_addr = 0;
-		hub_intr_disconnect(intr_hdl);
-	}
-
-	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED)
-		kfree(intr_hdl);
-
-#if defined(NEW_INTERRUPTS)
-	intr_unreserve_level(cpu, bit);
-#endif
-}
-
-
-/*
- * Associate resources allocated with a previous hub_intr_alloc call with the
- * described handler, arg, name, etc.
- */
-/*ARGSUSED*/
-int
-hub_intr_connect(	hub_intr_t intr_hdl,		/* xtalk intr resource handle */
-			intr_func_t intr_func,		/* xtalk intr handler */
-			void *intr_arg,			/* arg to intr handler */
-			xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
-			void *setfunc_arg,		/* arg to setfunc */
-			void *thread)			/* intr thread to use */
-{
-	int rv;
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-#ifdef CONFIG_IA64_SGI_SN1
-	extern int synergy_intr_connect(int, int);
-#endif
-
-	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
-
-#if defined(NEW_INTERRUPTS)
-	rv = intr_connect_level(cpu, bit, intr_hdl->i_swlevel, 
-					intr_func, intr_arg, NULL);
-	if (rv < 0)
-		return(rv);
-
-#endif
-	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
-	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
-
-	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
-
-	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
-#ifdef CONFIG_IA64_SGI_SN1
-	return(synergy_intr_connect((int)bit, (int)cpu));
-#endif
-}
-
-
-/*
- * Disassociate handler with the specified interrupt.
- */
-void
-hub_intr_disconnect(hub_intr_t intr_hdl)
-{
-	/*REFERENCED*/
-	int rv;
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-	xtalk_intr_setfunc_t setfunc;
-
-	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
-
-	/* TBD: send disconnected interrupts somewhere harmless */
-	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
-
-#if defined(NEW_INTERRUPTS)
-	rv = intr_disconnect_level(cpu, bit);
-	ASSERT(rv == 0);
-#endif
-
-	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
-}
-
-
-/*
- * Return a hwgraph vertex that represents the CPU currently
- * targeted by an interrupt.
- */
-devfs_handle_t
-hub_intr_cpu_get(hub_intr_t intr_hdl)
-{
-	cpuid_t cpuid = intr_hdl->i_cpuid;
-	ASSERT(cpuid != CPU_NONE);
-
-	return(cpuid_to_vertex(cpuid));
-}
-
-
-
 /* CONFIGURATION MANAGEMENT */
 
 /*
@@ -912,6 +603,9 @@
 void
 hub_provider_startup(devfs_handle_t hubv)
 {
+	extern void hub_dma_init(devfs_handle_t hubv);
+	extern void hub_pio_init(devfs_handle_t hubv);
+
 	hub_pio_init(hubv);
 	hub_dma_init(hubv);
 	hub_intr_init(hubv);
@@ -1170,58 +864,6 @@
 	return rv;
 }
 
-#if ((defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP))
-/* BRINGUP:  This ought to be useful for IP27 too but, for now,
- * make it SN1 only because `ii_ixtt_u_t' is not in IP27/hubio.h
- * (or anywhere else :-).
- */
-int
-hubii_ixtt_set(devfs_handle_t widget_vhdl, ii_ixtt_u_t *ixtt)
-{
-	xwidget_info_t		widget_info = xwidget_info_get(widget_vhdl);
-	devfs_handle_t		hub_vhdl    = xwidget_info_master_get(widget_info);
-	hubinfo_t		hub_info = 0;
-	nasid_t			nasid;
-	unsigned long			s;
-
-	/* Use the nasid from the hub info hanging off the hub vertex
-	 * and widget number from the widget vertex
-	 */
-	hubinfo_get(hub_vhdl, &hub_info);
-	/* Being over cautious by grabbing a lock */
-	s 	= mutex_spinlock(&hub_info->h_bwlock);
-	nasid 	= hub_info->h_nasid;
-
-	REMOTE_HUB_S(nasid, IIO_IXTT, ixtt->ii_ixtt_regval);
-
-	mutex_spinunlock(&hub_info->h_bwlock, s);
-	return 0;
-}
-
-int
-hubii_ixtt_get(devfs_handle_t widget_vhdl, ii_ixtt_u_t *ixtt)
-{
-	xwidget_info_t		widget_info = xwidget_info_get(widget_vhdl);
-	devfs_handle_t		hub_vhdl    = xwidget_info_master_get(widget_info);
-	hubinfo_t		hub_info = 0;
-	nasid_t			nasid;
-	unsigned long		s;
-
-	/* Use the nasid from the hub info hanging off the hub vertex
-	 * and widget number from the widget vertex
-	 */
-	hubinfo_get(hub_vhdl, &hub_info);
-	/* Being over cautious by grabbing a lock */
-	s 	= mutex_spinlock(&hub_info->h_bwlock);
-	nasid 	= hub_info->h_nasid;
-
-	ixtt->ii_ixtt_regval = REMOTE_HUB_L(nasid, IIO_IXTT);
-
-	mutex_spinunlock(&hub_info->h_bwlock, s);
-	return 0;
-}
-#endif /* CONFIG_IA64_SGI_SN1 */
-
 /*
  * hub_device_inquiry
  *	Find out the xtalk widget related information stored in this 
@@ -1259,7 +901,7 @@
 #if defined(SUPPORT_PRINTING_V_FORMAT)
 	printk("Inquiry Info for %v\n", xconn);
 #else
-	printk("Inquiry Info for 0x%x\n", xconn);
+	printk("Inquiry Info for %p\n", (void *)xconn);
 #endif
 
 	printk("\tDevices shutdown [ ");
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/ip37.c linux/arch/ia64/sn/io/ip37.c
--- linux.orig/arch/ia64/sn/io/ip37.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/ip37.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,121 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-/*
- * ip37.c
- *	Support for IP35/IP37 machines
- */
-
-#include <linux/types.h>
-#include <linux/config.h>
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sgi.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/sn1/hubdev.h>
-#include <asm/sn/pci/bridge.h>     /* for bridge_t */
-
-
-xwidgetnum_t
-hub_widget_id(nasid_t nasid)
-{
-	hubii_wcr_t	ii_wcr;	/* the control status register */
-		
-	ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
-
-	return ii_wcr.wcr_fields_s.wcr_widget_id;
-}
-
-/*
- * get_nasid() returns the physical node id number of the caller.
- */
-nasid_t
-get_nasid(void)
-{
-	return (nasid_t)((LOCAL_HUB_L(LB_REV_ID) & LRI_NODEID_MASK) >> LRI_NODEID_SHFT);
-}
-
-int
-get_slice(void)
-{
-	return LOCAL_HUB_L(PI_CPU_NUM);
-}
-
-int
-is_fine_dirmode(void)
-{
-	return (((LOCAL_HUB_L(LB_REV_ID) & LRI_SYSTEM_SIZE_MASK)
-		>> LRI_SYSTEM_SIZE_SHFT) == SYSTEM_SIZE_SMALL);
-
-}
-
-hubreg_t
-get_hub_chiprev(nasid_t nasid)
-{
-
-	return ((REMOTE_HUB_L(nasid, LB_REV_ID) & LRI_REV_MASK)
-		                                         >> LRI_REV_SHFT);
-}
-
-int
-verify_snchip_rev(void)
-{
-	int hub_chip_rev;
-	int i;
-	static int min_hub_rev = 0;
-	nasid_t nasid;
-	static int first_time = 1;
-	extern int maxnodes;
-
-        
-	if (first_time) {
-	    for (i = 0; i < maxnodes; i++) {	
-		nasid = COMPACT_TO_NASID_NODEID(i);
-		hub_chip_rev = get_hub_chiprev(nasid);
-
-		if ((hub_chip_rev < min_hub_rev) || (i == 0))
-		    min_hub_rev = hub_chip_rev;
-	    }
-
-	
-	    first_time = 0;
-	}
-
-	return min_hub_rev;
-	
-}
-
-#ifdef SN1_USE_POISON_BITS
-int
-hub_bte_poison_ok(void)
-{
-	/*
-	 * For now, assume poisoning is ok. If it turns out there are chip
-	 * bugs that prevent its use in early revs, there is some neat code
-	 * to steal from the IP27 equivalent of this code.
-	 */
-
-#ifdef BRINGUP	/* temp disable BTE poisoning - might be sw bugs in this area */
-	return 0;
-#else
-	return 1;
-#endif
-}
-#endif /* SN1_USE_POISON_BITS */
-                
-
-void
-ni_reset_port(void)
-{
-	LOCAL_HUB_S(NI_RESET_ENABLE, NRE_RESETOK);
-	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
-}
-
-#endif	/* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/klconflib.c linux/arch/ia64/sn/io/klconflib.c
--- linux.orig/arch/ia64/sn/io/klconflib.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/klconflib.c	2002-08-01 06:42:38.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -13,12 +12,13 @@
 #include <linux/config.h>
 #include <linux/ctype.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-
-#include <asm/sn/agent.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/module.h>
@@ -40,6 +40,9 @@
 
 static void sort_nic_names(lboard_t *) ;
 
+u64 klgraph_addr[MAX_COMPACT_NODES];
+int module_number = 0;
+
 lboard_t *
 find_lboard(lboard_t *start, unsigned char brd_type)
 {
@@ -213,14 +216,13 @@
 {
 	lboard_t	*board;
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-/* BRINGUP: If this works then look for callers of is_master_baseio()
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+/* If this works then look for callers of is_master_baseio()
  * (e.g. iograph.c) and let them pass in a slot if they want
  */
 	board = find_lboard_module((lboard_t *)KL_CONFIG_INFO(nasid), module);
 #else
-	board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid),
-				    module, slot);
+	board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid), module, slot);
 #endif
 
 #ifndef _STANDALONE
@@ -228,7 +230,7 @@
 		cnodeid_t cnode = NASID_TO_COMPACT_NODEID(nasid);
 
 		if (!board && (NODEPDA(cnode)->xbow_peer != INVALID_NASID))
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 			board = find_lboard_module((lboard_t *)
 				    KL_CONFIG_INFO(NODEPDA(cnode)->xbow_peer),
 				    module);
@@ -300,16 +302,6 @@
 	return(brd);
 }
 
-int
-get_cpu_slice(cpuid_t cpu)
-{
-	klcpu_t *acpu;
-	if ((acpu = get_cpuinfo(cpu)) == NULL)
-	    return -1;
-	return acpu->cpu_info.physid;
-}
-
-
 /*
  * get_actual_nasid
  *
@@ -366,10 +358,6 @@
 {
 	moduleid_t modnum;
 	char *board_name;
-#if !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-	slotid_t slot;
-	char slot_name[SLOTNUM_MAXLENGTH];
-#endif
 
 	ASSERT(brd);
 
@@ -410,7 +398,10 @@
 			
 	modnum = brd->brd_module;
 
-	ASSERT(modnum != MODULE_UNKNOWN && modnum != INVALID_MODULE);
+	/* ASSERT(modnum != MODULE_UNKNOWN && modnum != INVALID_MODULE); */
+if ((modnum == MODULE_UNKNOWN) || (modnum == INVALID_MODULE)) {
+	modnum = ++module_number;
+}
 #ifdef __ia64
 	{
 		char	buffer[16];
@@ -431,7 +422,7 @@
 {
 	lboard_t *brd;
 
-	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27);
+	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 
 	if (!brd)
 		return INVALID_MODULE;
@@ -569,8 +560,8 @@
 		if (component_serial_number_get(board,
 						hub->hub_mfg_nic,
 						serial_number,
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-						"IP35"))
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+						"IP37"))
 #else
 						"IP27"))
 			/* Try with IP31 key if IP27 key fails */
@@ -578,7 +569,7 @@
 							hub->hub_mfg_nic,
 							serial_number,
 							"IP31"))
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 				return(1);
 		break;
 	}
@@ -875,10 +866,11 @@
 }
 
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 
 char brick_types[MAX_BRICK_TYPES + 1] = "crikxdp789012345";
 
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+
 /*
  * Format a module id for printing.
  */
@@ -1009,7 +1001,7 @@
 	return (int)(unsigned short)m;
 }
 
-#else /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#else /* CONFIG_IA64_SGI_SN1 */
 
 /*
  * Format a module id for printing.
@@ -1038,8 +1030,8 @@
     if (strstr(buffer, EDGE_LBL_MODULE "/") == buffer)
 	buffer += strlen(EDGE_LBL_MODULE "/");
 
-    m = 0;
-    while(c = *buffer++) {
+    for (m = 0; *buffer; buffer++) {
+	c = *buffer;
 	if (!isdigit(c))
 	    return -1;
 	m = 10 * m + (c - '0');
@@ -1049,6 +1041,6 @@
     return (int)(unsigned short)m;
 }
 
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/klgraph.c linux/arch/ia64/sn/io/klgraph.c
--- linux.orig/arch/ia64/sn/io/klgraph.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/klgraph.c	2002-08-01 06:42:32.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 /*
@@ -18,12 +17,12 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-
-#include <asm/sn/agent.h>
 #include <asm/sn/kldir.h>
 #include <asm/sn/gda.h> 
 #include <asm/sn/klconfig.h>
@@ -43,8 +42,7 @@
 #include <asm/sn/sn_private.h>
 
 extern char arg_maxnodes[];
-extern int maxnodes;
-
+extern u64 klgraph_addr[];
 
 /*
  * Support for verbose inventory via hardware graph. 
@@ -139,193 +137,63 @@
 void
 klhwg_add_hub(devfs_handle_t node_vertex, klhub_t *hub, cnodeid_t cnode)
 {
+#if defined(CONFIG_IA64_SGI_SN1)
 	devfs_handle_t myhubv;
+	devfs_handle_t hub_mon;
+	devfs_handle_t synergy;
+	devfs_handle_t fsb0;
+	devfs_handle_t fsb1;
 	int rc;
+	extern struct file_operations hub_mon_fops;
 
 	GRPRINTF(("klhwg_add_hub: adding %s\n", EDGE_LBL_HUB));
 
 	(void) hwgraph_path_add(node_vertex, EDGE_LBL_HUB, &myhubv);
 	rc = device_master_set(myhubv, node_vertex);
 
-#ifdef	LATER
 	/*
-	 * Activate when we support hub stats.
+	 * hub perf stats.
 	 */
 	rc = hwgraph_info_add_LBL(myhubv, INFO_LBL_HUB_INFO,
                         (arbitrary_info_t)(&NODEPDA(cnode)->hubstats));
-#endif
 
 	if (rc != GRAPH_SUCCESS) {
-		PRINT_WARNING("klhwg_add_hub: Can't add hub info label 0x%p, code %d",
-			myhubv, rc);
+		printk(KERN_WARNING  "klhwg_add_hub: Can't add hub info label 0x%p, code %d",
+			(void *)myhubv, rc);
 	}
 
 	klhwg_hub_invent_info(myhubv, cnode, hub);
 
-#ifndef BRINGUP
+	hub_mon = hwgraph_register(myhubv, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &hub_mon_fops,
+	    (void *)(long)cnode);
+
 	init_hub_stats(cnode, NODEPDA(cnode));
-	sndrv_attach(myhubv);
-#else
+
 	/*
-	 * Need to call our driver to do the attach?
+	 * synergy perf
 	 */
-	FIXME("klhwg_add_hub: Need to add code to do the attach.\n");
-#endif
-}
-
-#ifndef BRINGUP
-
-void
-klhwg_add_rps(devfs_handle_t node_vertex, cnodeid_t cnode, int flag)
-{
-	devfs_handle_t myrpsv;
-	invent_rpsinfo_t *rps_invent;
-	int rc;
-
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-	
-	GRPRINTF(("klhwg_add_rps: adding %s to vertex 0x%x\n", EDGE_LBL_RPS,
-		node_vertex));
-
-	rc = hwgraph_path_add(node_vertex, EDGE_LBL_RPS, &myrpsv);
-	if (rc != GRAPH_SUCCESS)
-		return;
-
-	device_master_set(myrpsv, node_vertex);
-
-        rps_invent = (invent_rpsinfo_t *)
-            klhwg_invent_alloc(cnode, INV_RPS, sizeof(invent_rpsinfo_t));
-
-        if (!rps_invent)
-            return;
-
-	rps_invent->ir_xbox = 0;	/* not an xbox RPS */
-
-        if (flag)
-            rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-        else
-            rps_invent->ir_gen.ig_flag = 0x0;                                  
-
-        hwgraph_info_add_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                             (arbitrary_info_t) rps_invent);
-        hwgraph_info_export_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                                sizeof(invent_rpsinfo_t));                     
-	
-}
-
-/*
- * klhwg_update_rps gets invoked when the system controller sends an 
- * interrupt indicating the power supply has lost/regained the redundancy.
- * It's responsible for updating the Hardware graph information.
- *	rps_state = 0 -> if the rps lost the redundancy
- *		  = 1 -> If it is redundant. 
- */
-void 
-klhwg_update_rps(cnodeid_t cnode, int rps_state)
-{
-        devfs_handle_t node_vertex;
-        devfs_handle_t rpsv;
-        invent_rpsinfo_t *rps_invent;                                          
-        int rc;
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-
-        node_vertex = cnodeid_to_vertex(cnode);                                
-	rc = hwgraph_edge_get(node_vertex, EDGE_LBL_RPS, &rpsv);
-        if (rc != GRAPH_SUCCESS)  {
-		return;
-	}
-
-	rc = hwgraph_info_get_LBL(rpsv, INFO_LBL_DETAIL_INVENT, 
-				  (arbitrary_info_t *)&rps_invent);
-        if (rc != GRAPH_SUCCESS)  {
-                return;
-        }                                                                      
-
-	if (rps_state == 0 ) 
-		rps_invent->ir_gen.ig_flag = 0;
-	else 
-		rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-}
-
-void
-klhwg_add_xbox_rps(devfs_handle_t node_vertex, cnodeid_t cnode, int flag)
-{
-	devfs_handle_t myrpsv;
-	invent_rpsinfo_t *rps_invent;
-	int rc;
-
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-	
-	GRPRINTF(("klhwg_add_rps: adding %s to vertex 0x%x\n", 
-		  EDGE_LBL_XBOX_RPS, node_vertex));
-
-	rc = hwgraph_path_add(node_vertex, EDGE_LBL_XBOX_RPS, &myrpsv);
-	if (rc != GRAPH_SUCCESS)
-		return;
-
-	device_master_set(myrpsv, node_vertex);
-
-        rps_invent = (invent_rpsinfo_t *)
-            klhwg_invent_alloc(cnode, INV_RPS, sizeof(invent_rpsinfo_t));
-
-        if (!rps_invent)
-            return;
-
-	rps_invent->ir_xbox = 1;	/* xbox RPS */
-
-        if (flag)
-            rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-        else
-            rps_invent->ir_gen.ig_flag = 0x0;                                  
-
-        hwgraph_info_add_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                             (arbitrary_info_t) rps_invent);
-        hwgraph_info_export_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                                sizeof(invent_rpsinfo_t));                     
-	
-}
-
-/*
- * klhwg_update_xbox_rps gets invoked when the xbox system controller
- * polls the status register and discovers that the power supply has 
- * lost/regained the redundancy.
- * It's responsible for updating the Hardware graph information.
- *	rps_state = 0 -> if the rps lost the redundancy
- *		  = 1 -> If it is redundant. 
- */
-void 
-klhwg_update_xbox_rps(cnodeid_t cnode, int rps_state)
-{
-        devfs_handle_t node_vertex;
-        devfs_handle_t rpsv;
-        invent_rpsinfo_t *rps_invent;                                          
-        int rc;
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-
-        node_vertex = cnodeid_to_vertex(cnode);                                
-	rc = hwgraph_edge_get(node_vertex, EDGE_LBL_XBOX_RPS, &rpsv);
-        if (rc != GRAPH_SUCCESS)  {
-		return;
-	}
-
-	rc = hwgraph_info_get_LBL(rpsv, INFO_LBL_DETAIL_INVENT, 
-				  (arbitrary_info_t *)&rps_invent);
-        if (rc != GRAPH_SUCCESS)  {
-                return;
-        }                                                                      
-
-	if (rps_state == 0 ) 
-		rps_invent->ir_gen.ig_flag = 0;
-	else 
-		rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
+	(void) hwgraph_path_add(myhubv, EDGE_LBL_SYNERGY, &synergy);
+	(void) hwgraph_path_add(synergy, "0", &fsb0);
+	(void) hwgraph_path_add(synergy, "1", &fsb1);
+
+	fsb0 = hwgraph_register(fsb0, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &synergy_mon_fops, (void *)SYNERGY_PERF_INFO(cnode, 0));
+
+	fsb1 = hwgraph_register(fsb1, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &synergy_mon_fops, (void *)SYNERGY_PERF_INFO(cnode, 1));
+#endif /* CONFIG_IA64_SGI_SN1 */
 }
 
-#endif /* BRINGUP */
-
 void
 klhwg_add_xbow(cnodeid_t cnode, nasid_t nasid)
 {
@@ -338,11 +206,8 @@
 	/*REFERENCED*/
 	graph_error_t err;
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || defined(CONFIG_IA64_GENERIC)
-	if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
-				KLTYPE_IOBRICK_XBOW)) == NULL)
+	if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IOBRICK_XBOW)) == NULL)
 			return;
-#endif
 
 	if (KL_CONFIG_DUPLICATE_BOARD(brd))
 	    return;
@@ -372,7 +237,7 @@
 
 		hub_nasid = XBOW_PORT_NASID(xbow_p, widgetnum);
 		if (hub_nasid == INVALID_NASID) {
-			PRINT_WARNING("hub widget %d, skipping xbow graph\n", widgetnum);
+			printk(KERN_WARNING  "hub widget %d, skipping xbow graph\n", widgetnum);
 			continue;
 		}
 
@@ -387,13 +252,13 @@
 		err = hwgraph_path_add(hubv, EDGE_LBL_XTALK, &xbow_v);
                 if (err != GRAPH_SUCCESS) {
                         if (err == GRAPH_DUP)
-                                PRINT_WARNING("klhwg_add_xbow: Check for "
+                                printk(KERN_WARNING  "klhwg_add_xbow: Check for "
                                         "working routers and router links!");
 
                         PRINT_PANIC("klhwg_add_xbow: Failed to add "
-                                "edge: vertex 0x%p (0x%p) to vertex 0x%p (0x%p),"
+                                "edge: vertex 0x%p to vertex 0x%p,"
                                 "error %d\n",
-                                hubv, hubv, xbow_v, xbow_v, err);
+                                (void *)hubv, (void *)xbow_v, err);
                 }
 		xswitch_vertex_init(xbow_v); 
 
@@ -416,7 +281,7 @@
 		err = hwgraph_edge_add(hubv, xbow_v, EDGE_LBL_XTALK);
 		if (err != GRAPH_SUCCESS) {
 			if (err == GRAPH_DUP)
-				PRINT_WARNING("klhwg_add_xbow: Check for "
+				printk(KERN_WARNING  "klhwg_add_xbow: Check for "
 					"working routers and router links!");
 
 			PRINT_PANIC("klhwg_add_xbow: Failed to add "
@@ -443,7 +308,7 @@
 	int board_disabled = 0;
 
 	nasid = COMPACT_TO_NASID_NODEID(cnode);
-	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27);
+	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 	GRPRINTF(("klhwg_add_node: Adding cnode %d, nasid %d, brd 0x%p\n",
                 cnode, nasid, brd));
 	ASSERT(brd);
@@ -495,7 +360,7 @@
 		
 		brd = KLCF_NEXT(brd);
 		if (brd)
-			brd = find_lboard(brd, KLTYPE_IP27);
+			brd = find_lboard(brd, KLTYPE_SNIA);
 		else
 			break;
 	} while(brd);
@@ -513,7 +378,7 @@
 	char path_buffer[100];
 	int rv;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_add_all_routers: adding router on cnode %d\n",
@@ -594,7 +459,7 @@
 			return;
 
 	if (rc != GRAPH_SUCCESS)
-		PRINT_WARNING("Can't find router: %s", path_buffer);
+		printk(KERN_WARNING  "Can't find router: %s", path_buffer);
 
 	/* We don't know what to do with multiple router components */
 	if (brd->brd_numcompts != 1) {
@@ -650,7 +515,7 @@
 
 		if (rc != GRAPH_SUCCESS && !is_specified(arg_maxnodes))
 			PRINT_PANIC("Can't create edge: %s/%s to vertex 0x%p error 0x%x\n",
-				path_buffer, dest_path, dest_hndl, rc);
+				path_buffer, dest_path, (void *)dest_hndl, rc);
 		
 	}
 }
@@ -663,7 +528,7 @@
 	cnodeid_t cnode;
 	lboard_t *brd;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_connect_routers: Connecting routers on cnode %d\n",
@@ -703,14 +568,13 @@
 	char dest_path[50];
 	graph_error_t rc;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_connect_hubs: Connecting hubs on cnode %d\n",
 			cnode));
 
-		brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
-				KLTYPE_IP27);
+		brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 		ASSERT(brd);
 
 		hub = (klhub_t *)find_first_component(brd, KLSTRUCT_HUB);
@@ -732,7 +596,7 @@
 		rc = hwgraph_traverse(hwgraph_root, path_buffer, &hub_hndl);
 
 		if (rc != GRAPH_SUCCESS)
-			PRINT_WARNING("Can't find hub: %s", path_buffer);
+			printk(KERN_WARNING  "Can't find hub: %s", path_buffer);
 
 		dest_brd = (lboard_t *)NODE_OFFSET_TO_K0(
 				hub->hub_port.port_nasid,
@@ -757,7 +621,7 @@
 
 			if (rc != GRAPH_SUCCESS)
 				PRINT_PANIC("Can't create edge: %s/%s to vertex 0x%p, error 0x%x\n",
-				path_buffer, dest_path, dest_hndl, rc);
+				path_buffer, dest_path, (void *)dest_hndl, rc);
 
 		}
 	}
@@ -896,23 +760,14 @@
 void
 klhwg_add_all_nodes(devfs_handle_t hwgraph_root)
 {
-	//gda_t		*gdap = GDA;
-	gda_t		*gdap;
 	cnodeid_t	cnode;
 
-	gdap = (gda_t *)0xe000000000002400;
-
-	FIXME("klhwg_add_all_nodes: FIX GDA\n");
-
 	for (cnode = 0; cnode < numnodes; cnode++) {
-		ASSERT(gdap->g_nasidtable[cnode] != INVALID_NASID);
-		klhwg_add_node(hwgraph_root, cnode, gdap);
+		klhwg_add_node(hwgraph_root, cnode, NULL);
 	}
 
 	for (cnode = 0; cnode < numnodes; cnode++) {
-		ASSERT(gdap->g_nasidtable[cnode] != INVALID_NASID);
-
-		klhwg_add_xbow(cnode, gdap->g_nasidtable[cnode]);
+		klhwg_add_xbow(cnode, cnodeid_to_nasid(cnode));
 	}
 
 	/*
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/klgraph_hack.c linux/arch/ia64/sn/io/klgraph_hack.c
--- linux.orig/arch/ia64/sn/io/klgraph_hack.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/klgraph_hack.c	2002-08-01 06:42:29.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -18,6 +17,7 @@
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/klconfig.h>
 
 void * real_port;
@@ -28,11 +28,11 @@
 
 kl_config_hdr_t *linux_klcfg;
 
-#ifdef BRINGUP
+#ifdef DEFINE_DUMP_RTNS
 /* forward declarations */
-extern void dump_ii(void), dump_lb(void), dump_crossbow(void);
-extern void clear_ii_error(void);
-#endif /* BRINGUP */
+static void dump_ii(void), dump_crossbow(void);
+static void clear_ii_error(void);
+#endif /* DEFINE_DUMP_RTNS */
 
 #define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
 #define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
@@ -45,115 +45,10 @@
 #define HUBREG                  ((char *)0xc0000a0001e00000)
 #define WIDGET0                 ((char *)0xc0000a0000000000)
 
-int test = 0;
-
-/*
- * Hack to loop for test.
- */
-void
-test_io_regs(void)
-{
-
-	uint32_t reg_32bits;
-	uint64_t reg_64bits;
-
-	while (test) {
-
-		reg_32bits = (uint32_t)(*(volatile uint32_t *) SYNERGY_WIDGET);
-		reg_64bits = (uint64_t) (*(volatile uint64_t *) SYNERGY_WIDGET);
-
-	}
-
-        printk("Synergy Widget Address = 0x%p, Value = 0x%lx\n", SYNERGY_WIDGET, (uint64_t)*(SYNERGY_WIDGET));
-
-        printk("Synergy swizzle Address = 0x%p, Value = 0x%lx\n", SYNERGY_SWIZZLE, (uint64_t)*(SYNERGY_SWIZZLE));
-        printk("HUBREG  Address = 0x%p, Value = 0x%lx\n",  HUBREG, (uint64_t)*(HUBREG));
-        printk("WIDGET0 Address = 0x%p, Value = 0x%lx\n", WIDGET0, (uint64_t)*(WIDGET0));
-        printk("WIDGET4 Address = 0x%p, Value = 0x%x\n", WIDGET4, (uint32_t)*(WIDGET4));
-
-}
-
 void
 klgraph_hack_init(void)
 {
 
-	kl_config_hdr_t *kl_hdr_ptr;
-	lboard_t	*lb_ptr;
-	lboard_t	*temp_ptr;
-	klhub_t		*klhub_ptr;
-	klioc3_t	*klioc3_ptr;
-	klbri_t		*klbri_ptr;
-	klxbow_t	*klxbow_ptr;
-	klinfo_t	*klinfo_ptr;
-	klcomp_t	*klcomp_ptr;
-#if 0
-	uint64_t	*tmp;
-	volatile u32	*tmp32;
-
-	/* Preset some values */
-	/* Write IOERR clear to clear the CRAZY bit in the status */
-	tmp = (uint64_t *)0xc0000a0001c001f8; *tmp = (uint64_t)0xffffffff;
-	/* set widget control register...setting bedrock widget id to b */
-	/* tmp = (uint64_t *)0xc0000a0001c00020; *tmp = (uint64_t)0x801b; */
-	/* set io outbound widget access...allow all */
-	tmp = (uint64_t *)0xc0000a0001c00110; *tmp = (uint64_t)0xff01;
-	/* set io inbound widget access...allow all */
-	tmp = (uint64_t *)0xc0000a0001c00118; *tmp = (uint64_t)0xff01;
-	/* set io crb timeout to max */
-	tmp = (uint64_t *)0xc0000a0001c003c0; *tmp = (uint64_t)0xffffff;
-	tmp = (uint64_t *)0xc0000a0001c003c0; *tmp = (uint64_t)0xffffff;
-	
-	/* set local block io permission...allow all */
-	tmp = (uint64_t *)0xc0000a0001e04010; *tmp = (uint64_t)0xfffffffffffffff;
-
-	/* clear any errors */
-	clear_ii_error();
-
-	/* set default read response buffers in bridge */
-	tmp32 = (volatile u32 *)0xc0000a000f000280L;
-	*tmp32 = 0xba98;
-	tmp32 = (volatile u32 *)0xc0000a000f000288L;
-	*tmp32 = 0xba98;
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001e00000, *( (volatile uint64_t *)0xc0000a0001e00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001c00000, *( (volatile uint64_t *)0xc0000a0001c00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc000020001e00000, *( (volatile uint64_t *)0xc000020001e00000) );
-
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc000020001c00000, *( (volatile uint64_t *)0xc000020001c00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001e00000, *( (volatile uint64_t *)0xc0000a0001e00000) );
-
-printk("Xbow ID Address 0x%p Value 0x%x\n", (uint64_t *)0xc0000a0000000000, *( (volatile uint32_t *)0xc0000a0000000000) );
-
-printk("Xbow ID Address 0x%p Value 0x%x\n", (uint64_t *)0xc000020000000004, *( (volatile uint32_t *)0xc000020000000004) );
-
-#endif
-
-	if ( test )
-		test_io_regs();
-	/*
-	 * Klconfig header.
-	 */
-	kl_hdr_ptr = kmalloc(sizeof(kl_config_hdr_t), GFP_KERNEL);
-        kl_hdr_ptr->ch_magic = 0xbeedbabe;
-        kl_hdr_ptr->ch_version = 0x0;
-        kl_hdr_ptr->ch_malloc_hdr_off = 0x48;
-        kl_hdr_ptr->ch_cons_off = 0x18;
-        kl_hdr_ptr->ch_board_info = 0x0;
-        kl_hdr_ptr->ch_cons_info.uart_base = 0x920000000f820178;
-        kl_hdr_ptr->ch_cons_info.config_base = 0x920000000f024000;
-        kl_hdr_ptr->ch_cons_info.memory_base = 0x920000000f800000;
-        kl_hdr_ptr->ch_cons_info.baud = 0x2580;
-        kl_hdr_ptr->ch_cons_info.flag = 0x1;
-        kl_hdr_ptr->ch_cons_info.type = 0x300fafa;
-        kl_hdr_ptr->ch_cons_info.nasid = 0x0;
-        kl_hdr_ptr->ch_cons_info.wid = 0xf;
-        kl_hdr_ptr->ch_cons_info.npci = 0x4;
-        kl_hdr_ptr->ch_cons_info.baseio_nic = 0x0;
-
 	/*
 	 * We need to know whether we are booting from PROM or 
 	 * boot from disk.
@@ -162,520 +57,44 @@
 	if (linux_klcfg->ch_magic == 0xbeedbabe) {
 		return;
 	} else {
-		linux_klcfg = kl_hdr_ptr;
+		panic("klgraph_hack_init: Unable to locate KLCONFIG TABLE\n");
 	}
 
-	/*
-	 * lboard KLTYPE_IP35
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	kl_hdr_ptr->ch_board_info = (klconf_off_t) lb_ptr;
-	temp_ptr = lb_ptr;
-	printk("First Lboard = %p\n", temp_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x11;
-        lb_ptr->brd_sversion = 0x3;
-        lb_ptr->brd_brevision = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_slot = 0x0;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x0;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x5;
-        lb_ptr->brd_nic = 0x2a0aed35;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = 0x0;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0x26;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-	/*
-	 * Hub Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klhub_ptr = (klhub_t *)klcomp_ptr;
-	klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-	printk("hub info = %p lboard = %p\n", klhub_ptr, lb_ptr);
-
-	klinfo_ptr = (klinfo_t *)klhub_ptr;
-        klinfo_ptr->struct_type = 0x2;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0x2a0aed35;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-        klhub_ptr->hub_flags = 0x0;
-        klhub_ptr->hub_port.port_nasid = (nasid_t)0x0ffffffff;
-        klhub_ptr->hub_port.port_flag = 0x0;
-        klhub_ptr->hub_port.port_offset = 0x0;
-        klhub_ptr->hub_box_nic = 0x0;
-        klhub_ptr->hub_mfg_nic = 0x3f420;
-        klhub_ptr->hub_speed = 0xbebc200;
-
-	/*
-	 * Memory Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[1] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x3;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0xff;
-        klinfo_ptr->virtid = 0xffffffff;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_HUB_UART Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[2] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x11;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_CPU Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[3] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x1;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_CPU Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[4] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x1;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x1;
-        klinfo_ptr->virtid = 0x1;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	lb_ptr->brd_compts[5] = 0; /* Set the next one to 0 .. end */
-	lb_ptr->brd_numcompts = 5; /* 0 to 4 */
-
-	/*
-	 * lboard(0x42) KLTYPE_PBRICK_XBOW
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Second Lboard = %p\n", temp_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x42;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_slot = 0x0;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x1;
-        lb_ptr->brd_nic = 0xffffffffffffffff;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030070;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-        memcpy(&lb_ptr->brd_name[0], "IOBRICK", 7);
-
-	/*
-	 * KLSTRUCT_XBOW Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	memset(klcomp_ptr, 0, sizeof(klcomp_t));
-        klxbow_ptr = (klxbow_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-	printk("xbow_p 0x%p\n", klcomp_ptr);
-
-        klinfo_ptr->struct_type = 0x4;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0xff;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-        klxbow_ptr->xbow_master_hub_link = 0xb;
-        klxbow_ptr->xbow_port_info[0].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[0].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[0].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[1].port_nasid = 0x401;
-        klxbow_ptr->xbow_port_info[1].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[1].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[2].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[2].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[2].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[3].port_nasid = 0x0; /* ffffffff */
-        klxbow_ptr->xbow_port_info[3].port_flag = 0x6;
-        klxbow_ptr->xbow_port_info[3].port_offset = 0x30070;
-
-        klxbow_ptr->xbow_port_info[4].port_nasid = 0x0; /* ffffff00; */
-        klxbow_ptr->xbow_port_info[4].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[4].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[5].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[5].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[5].port_offset = 0x0;
-        klxbow_ptr->xbow_port_info[6].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[6].port_flag = 0x5;
-        klxbow_ptr->xbow_port_info[6].port_offset = 0x30210;
-        klxbow_ptr->xbow_port_info[7].port_nasid = 0x3;
-        klxbow_ptr->xbow_port_info[7].port_flag = 0x5;
-        klxbow_ptr->xbow_port_info[7].port_offset = 0x302e0;
-	
-	lb_ptr->brd_compts[1] = 0;
-        lb_ptr->brd_numcompts = 1;
-
-
-	/*
-	 * lboard KLTYPE_PBRICK
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Third Lboard %p\n", lb_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x72;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x41;
-        lb_ptr->brd_slot = 0xe;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x1;
-        lb_ptr->brd_nic = 0x30e3fd;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030140;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-	/*
-	 * KLSTRUCT_BRI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klbri_ptr = (klbri_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x5;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0xd002;
-        klinfo_ptr->nic = 0x30e3fd;
-        klinfo_ptr->physid = 0xe;
-        klinfo_ptr->virtid = 0xe;
-        klinfo_ptr->widid = 0xe;
-        klinfo_ptr->nasid = 0x0;
-
-        klbri_ptr->bri_eprominfo = 0xff;
-        klbri_ptr->bri_bustype = 0x7;
-        klbri_ptr->bri_mfg_nic = 0x3f4a8;
-
-        lb_ptr->brd_compts[1] = 0;
-        lb_ptr->brd_numcompts = 1;
-
-	/*
-	 * lboard KLTYPE_PBRICK
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Fourth Lboard %p\n", lb_ptr);
-
-        lb_ptr->brd_next = 0x0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x72;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x31;
-        lb_ptr->brd_slot = 0xf;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x6;
-        lb_ptr->brd_nic = 0x30e3fd;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030140;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-
-	/*
-	 * KLSTRUCT_BRI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klbri_ptr = (klbri_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x5;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0xd002;
-        klinfo_ptr->nic = 0x30e3fd;
-        klinfo_ptr->physid = 0xf;
-        klinfo_ptr->virtid = 0xf;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-        klbri_ptr->bri_eprominfo = 0xff;
-        klbri_ptr->bri_bustype = 0x7;
-        klbri_ptr->bri_mfg_nic = 0x3f528;
-
-	/*
-	 * KLSTRUCT_SCSI component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[1] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0xb;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x5;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x1;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_IOC3 Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klioc3_ptr = (klioc3_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[2] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x6;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x4;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-        klioc3_ptr->ioc3_ssram = 0x0;
-        klioc3_ptr->ioc3_nvram = 0x0;
-
-	/*
-	 * KLSTRUCT_UNKNOWN Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[3] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x0;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x5;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_SCSI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[4] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0xb;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x6;
-        klinfo_ptr->virtid = 0x5;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_UNKNOWN
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[5] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x0;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x7;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	lb_ptr->brd_compts[6] = 0;
-	lb_ptr->brd_numcompts = 6;
-
 }
 
 
 
 
 	
-#ifdef BRINGUP
+#ifdef DEFINE_DUMP_RTNS
 /* 
  * these were useful for printing out registers etc
  * during bringup  
  */
 
-void
+static void
 xdump(long long *addr, int count)
 {
 	int ii;
 	volatile long long *xx = addr;
 
 	for ( ii = 0; ii < count; ii++, xx++ ) {
-		printk("0x%p : 0x%p\n", xx, *xx);
+		printk("0x%p : 0x%p\n", (void *)xx, (void *)*xx);
 	}
 }
 
-void
+static void
 xdump32(unsigned int *addr, int count)
 {
 	int ii;
 	volatile unsigned int *xx = addr;
 
 	for ( ii = 0; ii < count; ii++, xx++ ) {
-		printk("0x%p : 0x%0x\n", xx, *xx);
+		printk("0x%p : 0x%0x\n", (void *)xx, (int)*xx);
 	}
 }
 
-
-
-void
+static void
 clear_ii_error(void)
 {
 	volatile long long *tmp;
@@ -716,8 +135,8 @@
 }
 
 
-void
-dump_ii()
+static void
+dump_ii(void)
 {
 	printk("===== Dump the II regs =====\n");
 	xdump((long long *)0xc0000a0001c00000, 2);
@@ -746,23 +165,8 @@
 	xdump((long long *)0xc0000a000f000000, 1);
 }
 
-void
-dump_lb()
-{
-	printk("===== Dump the LB regs =====\n");
-	xdump((long long *)0xc0000a0001e00000, 1);
-	xdump((long long *)0xc0000a0001e04000, 13);
-	xdump((long long *)0xc0000a0001e04100, 2);
-	xdump((long long *)0xc0000a0001e04200, 2);
-	xdump((long long *)0xc0000a0001e08000, 5);
-	xdump((long long *)0xc0000a0001e08040, 2);
-	xdump((long long *)0xc0000a0001e08050, 3);
-	xdump((long long *)0xc0000a0001e0c000, 3);
-	xdump((long long *)0xc0000a0001e0c020, 4);
-}
-
-void
-dump_crossbow()
+static void
+dump_crossbow(void)
 {
 	printk("===== Dump the Crossbow regs =====\n");
 	clear_ii_error();
@@ -793,4 +197,4 @@
 
 
 }
-#endif /* BRINGUP */
+#endif /* DEFINE_DUMP_RTNS */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/l1.c linux/arch/ia64/sn/io/l1.c
--- linux.orig/arch/ia64/sn/io/l1.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/l1.c	2002-08-01 06:42:40.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /* In general, this file is organized in a hierarchy from lower-level
@@ -16,18 +15,12 @@
  *	System controller "message" interface (allows multiplexing
  *		of various kinds of requests and responses with
  *		console I/O)
- *	Console interfaces (there are two):
- *	  (1) "elscuart", used in the IP35prom and (maybe) some
- *		debugging situations elsewhere, and
- *	  (2) "l1_cons", the glue that allows the L1 to act
+ *	Console interface:
+ *	  "l1_cons", the glue that allows the L1 to act
  *		as the system console for the stdio libraries
  *
  * Routines making use of the system controller "message"-style interface
- * can be found in l1_command.c.  Their names are leftover from early SN0, 
- * when the "module system controller" (msc) was known as the "entry level
- * system controller" (elsc).  The names and signatures of those functions 
- * remain unchanged in order to keep the SN0 -> SN1 system controller
- * changes fairly localized.
+ * can be found in l1_command.c.
  */
 
 
@@ -35,45 +28,32 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/delay.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/clksupport.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/uart16550.h>
+#include <asm/sn/simulator.h>
 
-#include <asm/sn/sn1/uart16550.h>
-
-/*
- * Delete this when atomic_clear is part of atomic.h.
- */
-static __inline__ int
-atomic_clear (int i, atomic_t *v)
-{
-	__s32 old, new;
-
-	do {
-		old = atomic_read(v);
-		new = old & ~i;
-	} while (ia64_cmpxchg("acq", v, old, new, sizeof(atomic_t)) != old);
-	return new;
-}
-
-#if defined(EEPROM_DEBUG)
-#define db_printf(x) printk x
-#else
-#define db_printf(x)
+#if defined(CONFIG_IA64_SGI_SN2)
+#define USE_SAL_CONSOLE_IO	1	/* DON'T un-def this for the simulator... */
 #endif
 
-// From irix/kern/sys/SN/SN1/bdrkhspecregs.h
-#define    HSPEC_UART_0              0x00000080    /* UART Registers         */
+/* Make all console writes atomic */
+#define SYNC_CONSOLE_WRITE	1
+
 
 /*********************************************************************
  * Hardware-level (UART) driver routines.
@@ -81,28 +61,33 @@
 
 /* macros for reading/writing registers */
 
-#define LD(x)		(*(volatile uint64_t *)(x))
-#define SD(x, v)        (LD(x) = (uint64_t) (v))
+#define LD(x)			(*(volatile uint64_t *)(x))
+#define SD(x, v)        	(LD(x) = (uint64_t) (v))
 
 /* location of uart receive/xmit data register */
-#define L1_UART_BASE(n)	((ulong)REMOTE_HSPEC_ADDR((n), HSPEC_UART_0))
-#define LOCAL_HUB	LOCAL_HUB_ADDR
-#define LOCK_HUB	REMOTE_HUB_ADDR
-
-#define ADDR_L1_REG(n, r)	\
-    (L1_UART_BASE(n) | ( (r) << 3 ))
+#if defined(CONFIG_IA64_SGI_SN1)
+#define L1_UART_BASE(n)		((ulong)REMOTE_HSPEC_ADDR((n), 0x00000080))
+#define LOCK_HUB		REMOTE_HUB_ADDR
+#elif defined(CONFIG_IA64_SGI_SN2)
+#define L1_UART_BASE(n)		((ulong)REMOTE_HUB((n), SH_JUNK_BUS_UART0))
+#define LOCK_HUB		REMOTE_HUB
+typedef u64 rtc_time_t;
+#endif
 
-#define READ_L1_UART_REG(n, r) \
-    ( LD(ADDR_L1_REG((n), (r))) )
 
-#define WRITE_L1_UART_REG(n, r, v) \
-    ( SD(ADDR_L1_REG((n), (r)), (v)) )
+#define ADDR_L1_REG(n, r)	( L1_UART_BASE(n) | ( (r) << 3 ) )
+#define READ_L1_UART_REG(n, r)	( LD(ADDR_L1_REG((n), (r))) )
+#define WRITE_L1_UART_REG(n, r, v) ( SD(ADDR_L1_REG((n), (r)), (v)) )
+
+/* upper layer interface calling methods */
+#define SERIAL_INTERRUPT_MODE	0
+#define SERIAL_POLLED_MODE	1
 
 
 /* UART-related #defines */
 
 #define UART_BAUD_RATE		57600
-#define UART_FIFO_DEPTH		0xf0
+#define UART_FIFO_DEPTH		16
 #define UART_DELAY_SPAN		10
 #define UART_PUTC_TIMEOUT	50000
 #define UART_INIT_TIMEOUT	100000
@@ -114,17 +99,32 @@
 #define UART_NO_CHAR		(-3)
 #define UART_VECTOR		(-4)
 
-#ifdef BRINGUP
-#define UART_DELAY(x)	{ int i; i = x * 1000; while (--i); }
-#else
-#define UART_DELAY(x)	us_delay(x)
-#endif
+#define UART_DELAY(x)		udelay(x)
+
+/* Some debug counters */
+#define L1C_INTERRUPTS		0
+#define L1C_OUR_R_INTERRUPTS	1
+#define L1C_OUR_X_INTERRUPTS	2
+#define L1C_SEND_CALLUPS	3
+#define L1C_RECEIVE_CALLUPS	4
+#define L1C_SET_BAUD		5
+#define L1C_ALREADY_LOCKED	L1C_SET_BAUD
+#define L1C_R_IRQ		6
+#define L1C_R_IRQ_RET		7
+#define L1C_LOCK_TIMEOUTS	8
+#define L1C_LOCK_COUNTER	9
+#define L1C_UNLOCK_COUNTER	10
+#define L1C_REC_STALLS		11
+#define L1C_CONNECT_CALLS	12
+#define L1C_SIZE		L1C_CONNECT_CALLS	/* Set to the last one */
+
+uint64_t L1_collectibles[L1C_SIZE + 1];
+
 
 /*
  *	Some macros for handling Endian-ness
  */
 
-#ifdef	LITTLE_ENDIAN
 #define COPY_INT_TO_BUFFER(_b, _i, _n)		\
 	{					\
 		_b[_i++] = (_n >> 24) & 0xff;	\
@@ -149,42 +149,64 @@
 	    _xyz[1] = _b[_i++];			\
 	    _xyz[0] = _b[_i++];			\
 	}
-#else	/* BIG_ENDIAN */
-
-extern char *bcopy(const char * src, char * dest, int count);
 
-#define COPY_INT_TO_BUFFER(_b, _i, _n)			\
-	{						\
-		bcopy((char *)&_n, _b, sizeof(_n));	\
-		_i += sizeof(_n);			\
-	}
+void snia_kmem_free(void *where, int size);
 
-#define COPY_BUFFER_TO_INT(_b, _i, _n)			\
-	{						\
-		bcopy(&_b[_i], &_n, sizeof(_n));	\
-		_i += sizeof(_n);			\
-	}
+#define ALREADY_LOCKED		1
+#define NOT_LOCKED		0
+static int early_l1_serial_out(nasid_t, char *, int, int /* defines above*/ );
 
-#define COPY_BUFFER_TO_BUFFER(_b, _i, _bn)		\
-	{						\
-            bcopy(&(_b[_i]), _bn, sizeof(int));		\
-            _i += sizeof(int);				\
-	}
-#endif	/* LITTLE_ENDIAN */
+#define BCOPY(x,y,z)	memcpy(y,x,z)
 
-void kmem_free(void *where, int size);
+uint8_t L1_interrupts_connected;		/* Non-zero when we are in interrupt mode */
 
-#define BCOPY(x,y,z)	memcpy(y,x,z)
 
 /*
  * Console locking defines and functions.
  *
  */
 
-#ifdef BRINGUP
-#define FORCE_CONSOLE_NASID
+uint8_t L1_cons_is_inited = 0;			/* non-zero when console is init'd */
+nasid_t Master_console_nasid = (nasid_t)-1;
+extern nasid_t console_nasid;
+
+#if defined(CONFIG_IA64_SGI_SN1)
+u64 ia64_sn_get_console_nasid(void);
 #endif
 
+inline nasid_t
+get_master_nasid(void)
+{
+#if defined(CONFIG_IA64_SGI_SN1)
+	nasid_t nasid = Master_console_nasid;
+
+	if ( nasid == (nasid_t)-1 ) {
+		nasid = (nasid_t)ia64_sn_get_console_nasid();
+		if ( (nasid < 0) || (nasid >= MAX_NASIDS) ) {
+			/* Out of bounds, use local */
+			console_nasid = nasid = get_nasid();
+		}
+		else {
+			/* Got a valid nasid, set the console_nasid */
+			char xx[100];
+/* zzzzzz - force nasid to 0 for now */
+			sprintf(xx, "Master console is set to nasid %d (%d)\n", 0, (int)nasid);
+nasid = 0;
+/* end zzzzzz */
+			xx[99] = (char)0;
+			early_l1_serial_out(nasid, xx, strlen(xx), NOT_LOCKED);
+			Master_console_nasid = console_nasid = nasid;
+		}
+	}
+	return(nasid);
+#else
+	return((nasid_t)0);
+#endif	/* CONFIG_IA64_SGI_SN1 */
+}
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
+
 #define HUB_LOCK		16
 
 #define PRIMARY_LOCK_TIMEOUT    10000000
@@ -199,7 +221,6 @@
 
 #define RTC_TIME_MAX		((rtc_time_t) ~0ULL)
 
-
 /*
  * primary_lock
  *
@@ -295,26 +316,37 @@
 
 #define LOCK_TIMEOUT	(0x1500000 * 1) /* 0x1500000 is ~30 sec */
 
-inline void
+void
 lock_console(nasid_t nasid)
 {
 	int ret;
 
+	/* If we already have it locked, just return */
+	L1_collectibles[L1C_LOCK_COUNTER]++;
+
 	ret = hub_lock_timeout(nasid, HUB_LOCK, (rtc_time_t)LOCK_TIMEOUT);
 	if ( ret != 0 ) {
+		L1_collectibles[L1C_LOCK_TIMEOUTS]++;
 		/* timeout */
 		hub_unlock(nasid, HUB_LOCK);
 		/* If the 2nd lock fails, just pile ahead.... */
 		hub_lock_timeout(nasid, HUB_LOCK, (rtc_time_t)LOCK_TIMEOUT);
+		L1_collectibles[L1C_LOCK_TIMEOUTS]++;
 	}
 }
 
 inline void
 unlock_console(nasid_t nasid)
 {
+	L1_collectibles[L1C_UNLOCK_COUNTER]++;
 	hub_unlock(nasid, HUB_LOCK);
 }
 
+#else /* SN2 */
+inline void lock_console(nasid_t n)	{}
+inline void unlock_console(nasid_t n)	{}
+
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 int 
 get_L1_baud(void)
@@ -325,27 +357,18 @@
 
 /* uart driver functions */
 
-static void
+static inline void
 uart_delay( rtc_time_t delay_span )
 {
     UART_DELAY( delay_span );
 }
 
-#define UART_PUTC_READY(n)      ( (READ_L1_UART_REG((n), REG_LSR) & LSR_XHRE) && (READ_L1_UART_REG((n), REG_MSR) & MSR_CTS) )
+#define UART_PUTC_READY(n)      (READ_L1_UART_REG((n), REG_LSR) & LSR_XHRE)
 
 static int
 uart_putc( l1sc_t *sc ) 
 {
-#ifdef BRINGUP
-    /* need a delay to avoid dropping chars */
-    UART_DELAY(57);
-#endif
-#ifdef FORCE_CONSOLE_NASID
-    /* We need this for the console write path _elscuart_flush() -> brl1_send() */
-    sc->nasid = 0;
-#endif
-    WRITE_L1_UART_REG( sc->nasid, REG_DAT,
-		       sc->send[sc->sent] );
+    WRITE_L1_UART_REG( sc->nasid, REG_DAT, sc->send[sc->sent] );
     return UART_SUCCESS;
 }
 
@@ -356,10 +379,6 @@
     u_char lsr_reg = 0;
     nasid_t nasid = sc->nasid;
 
-#ifdef FORCE_CONSOLE_NASID
-    nasid = sc->nasid = 0;
-#endif
-
     if( (lsr_reg = READ_L1_UART_REG( nasid, REG_LSR )) & 
 	(LSR_RCA | LSR_PARERR | LSR_FRMERR) ) 
     {
@@ -396,9 +415,10 @@
 	}
     }
 
-    if ( sc->uart == BRL1_LOCALUART )
+    if ( sc->uart == BRL1_LOCALHUB_UART )
 	lock_console(nasid);
 
+    /* Setup for the proper baud rate */
     WRITE_L1_UART_REG( nasid, REG_LCR, LCR_DLAB );
 	uart_delay( UART_DELAY_SPAN );
     WRITE_L1_UART_REG( nasid, REG_DLH, (clkdiv >> 8) & 0xff );
@@ -407,6 +427,8 @@
 	uart_delay( UART_DELAY_SPAN );
 
     /* set operating parameters and set DLAB to 0 */
+
+    /* 8bit, one stop, clear request to send, auto flow control */
     WRITE_L1_UART_REG( nasid, REG_LCR, LCR_BITS8 | LCR_STOP1 );
 	uart_delay( UART_DELAY_SPAN );
     WRITE_L1_UART_REG( nasid, REG_MCR, MCR_RTS | MCR_AFE );
@@ -416,23 +438,28 @@
     WRITE_L1_UART_REG( nasid, REG_ICR, 0x0 );
 	uart_delay( UART_DELAY_SPAN );
 
-    /* enable FIFO mode and reset both FIFOs */
+    /* enable FIFO mode and reset both FIFOs, trigger on 1 */
     WRITE_L1_UART_REG( nasid, REG_FCR, FCR_FIFOEN );
 	uart_delay( UART_DELAY_SPAN );
-    WRITE_L1_UART_REG( nasid, REG_FCR,
-	FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO );
+    WRITE_L1_UART_REG( nasid, REG_FCR, FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL0);
 
-    if ( sc->uart == BRL1_LOCALUART )
+    if ( sc->uart == BRL1_LOCALHUB_UART )
 	unlock_console(nasid);
 }
 
 /* This requires the console lock */
+
+#if	defined(CONFIG_IA64_SGI_SN1)
+
 static void
 uart_intr_enable( l1sc_t *sc, u_char mask )
 {
     u_char lcr_reg, icr_reg;
     nasid_t nasid = sc->nasid;
 
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(nasid);
+
     /* make sure that the DLAB bit in the LCR register is 0
      */
     lcr_reg = READ_L1_UART_REG( nasid, REG_LCR );
@@ -444,6 +471,9 @@
     icr_reg = READ_L1_UART_REG( nasid, REG_ICR );
     icr_reg |= mask;
     WRITE_L1_UART_REG( nasid, REG_ICR, icr_reg /*(ICR_RIEN | ICR_TIEN)*/ );
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(nasid);
 }
 
 /* This requires the console lock */
@@ -453,6 +483,9 @@
     u_char lcr_reg, icr_reg;
     nasid_t nasid = sc->nasid;
 
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(nasid);
+
     /* make sure that the DLAB bit in the LCR register is 0
      */
     lcr_reg = READ_L1_UART_REG( nasid, REG_LCR );
@@ -464,7 +497,11 @@
     icr_reg = READ_L1_UART_REG( nasid, REG_ICR );
     icr_reg &= mask;
     WRITE_L1_UART_REG( nasid, REG_ICR, icr_reg /*(ICR_RIEN | ICR_TIEN)*/ );
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(nasid);
 }
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 #define uart_enable_xmit_intr(sc) \
 	uart_intr_enable((sc), ICR_TIEN)
@@ -511,10 +548,6 @@
     net_vec_t path = sc->uart;
     rtc_time_t expire = rtc_time() + RTR_UART_PUTC_TIMEOUT;
 
-#ifdef FORCE_CONSOLE_NASID
-    /* We need this for the console write path _elscuart_flush() -> brl1_send() */
-    nasid = sc->nasid = 0;
-#endif
     c = (sc->send[sc->sent] & 0xffULL);
     
     while( 1 ) 
@@ -543,10 +576,6 @@
     nasid_t nasid = sc->nasid;
     net_vec_t path = sc->uart;
 
-#ifdef FORCE_CONSOLE_NASID
-    nasid = sc->nasid = 0;
-#endif
-
     READ_RTR_L1_UART_REG( path, nasid, REG_LSR, &regval );
     if( regval & (LSR_RCA | LSR_PARERR | LSR_FRMERR) )
     {
@@ -617,6 +646,15 @@
     return 0;
 }
 
+/*********************************************************************
+ * locking macros 
+ */
+
+#define L1SC_SEND_LOCK(l,p)   { if ((l)->uart == BRL1_LOCALHUB_UART) spin_lock_irqsave(&((l)->send_lock),p); }
+#define L1SC_SEND_UNLOCK(l,p) { if ((l)->uart == BRL1_LOCALHUB_UART) spin_unlock_irqrestore(&((l)->send_lock), p); }
+#define L1SC_RECV_LOCK(l,p)   { if ((l)->uart == BRL1_LOCALHUB_UART) spin_lock_irqsave(&((l)->recv_lock), p); } 
+#define L1SC_RECV_UNLOCK(l,p) { if ((l)->uart == BRL1_LOCALHUB_UART) spin_unlock_irqrestore(&((l)->recv_lock), p); }
+
 
 /*********************************************************************
  * subchannel manipulation 
@@ -626,31 +664,43 @@
  * associated with particular subchannels (e.g., receive queues).
  *
  */
-
-#ifdef SPINLOCKS_WORK
-#define SUBCH_LOCK(sc)			spin_lock_irq( &((sc)->subch_lock) )
-#define SUBCH_UNLOCK(sc)		spin_unlock_irq( &((sc)->subch_lock) )
-#define SUBCH_DATA_LOCK(sbch) 		spin_lock_irq( &((sbch)->data_lock) )
-#define SUBCH_DATA_UNLOCK(sbch)		spin_unlock_irq( &((sbch)->data_lock) )
-#else
-#define SUBCH_LOCK(sc)
-#define SUBCH_UNLOCK(sc)
-#define SUBCH_DATA_LOCK(sbch)
-#define SUBCH_DATA_UNLOCK(sbch)
-#endif
+#define SUBCH_LOCK(sc, p)		spin_lock_irqsave( &((sc)->subch_lock), p )
+#define SUBCH_UNLOCK(sc, p)		spin_unlock_irqrestore( &((sc)->subch_lock), p )
+#define SUBCH_DATA_LOCK(sbch, p) 	spin_lock_irqsave( &((sbch)->data_lock), p )
+#define SUBCH_DATA_UNLOCK(sbch, p)	spin_unlock_irqrestore( &((sbch)->data_lock), p )
 
 
-/* get_myid is an internal function that reads the PI_CPU_NUM
- * register of the local bedrock to determine which of the
- * four possible CPU's "this" one is
+/*
+ * set a function to be called for subchannel ch in the event of
+ * a transmission low-water interrupt from the uart
  */
-static int
-get_myid( void )
+void
+subch_set_tx_notify( l1sc_t *sc, int ch, brl1_notif_t func )
 {
-    return( LD(LOCAL_HUB(PI_CPU_NUM)) );
+    unsigned long pl = 0;
+
+    L1SC_SEND_LOCK( sc, pl );
+#if	!defined(SYNC_CONSOLE_WRITE)
+    if ( func && !sc->send_in_use )
+	uart_enable_xmit_intr( sc );
+#endif
+    sc->subch[ch].tx_notify = func;
+    L1SC_SEND_UNLOCK(sc, pl );
 }
 
+/*
+ * set a function to be called for subchannel ch when data is received
+ */
+void
+subch_set_rx_notify( l1sc_t *sc, int ch, brl1_notif_t func )
+{
+    unsigned long pl = 0;
+    brl1_sch_t *subch = &(sc->subch[ch]);
 
+    SUBCH_DATA_LOCK( subch, pl );
+    sc->subch[ch].rx_notify = func;
+    SUBCH_DATA_UNLOCK( subch, pl );
+}
 
 /*********************************************************************
  * Queue manipulation macros
@@ -767,14 +817,16 @@
  * brl1_discard_packet is a dummy "receive callback" used to get rid
  * of packets we don't want
  */
-void brl1_discard_packet( l1sc_t *sc, int ch )
+void brl1_discard_packet( int dummy0, void *dummy1, struct pt_regs *dummy2, l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
     brl1_sch_t *subch = &sc->subch[ch];
+
     sc_cq_t *q = subch->iqp;
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     q->opos = q->ipos;
-    atomic_clear( &(subch->packet_arrived), ~((unsigned)0) );
-    SUBCH_DATA_UNLOCK( subch );
+    atomic_set(&(subch->packet_arrived), 0);
+    SUBCH_DATA_UNLOCK( subch, pl );
 }
 
 
@@ -789,17 +841,15 @@
 static int
 brl1_send_chars( l1sc_t *sc )
 {
-    /* In the kernel, we track the depth of the C brick's UART's
+    /* We track the depth of the C brick's UART's
      * fifo in software, and only check if the UART is accepting
      * characters when our count indicates that the fifo should
      * be full.
      *
-     * For remote (router) UARTs, and also for the local (C brick)
-     * UART in the prom, we check with the UART before sending every
+     * For remote (router) UARTs, we check with the UART before sending every
      * character.
      */
-    if( sc->uart == BRL1_LOCALUART ) 
-    {
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
 	if( !(sc->fifo_space) && UART_PUTC_READY( sc->nasid ) )
 	    sc->fifo_space = UART_FIFO_DEPTH;
 	
@@ -809,16 +859,10 @@
 	    sc->sent++;
 	}
     }
+    else {
 
-    else
-
-    /* The following applies to all UARTs in the prom, and to remote
-     * (router) UARTs in the kernel...
-     */
-
-#define TIMEOUT_RETRIES	30
+	/* remote (router) UARTs */
 
-    {
 	int result;
 	int tries = 0;
 
@@ -831,7 +875,7 @@
 	    if( result == UART_TIMEOUT ) {
 		tries++;
 		/* send this character in TIMEOUT_RETRIES... */
-		if( tries < TIMEOUT_RETRIES ) {
+		if( tries < 30 /* TIMEOUT_RETRIES */ ) {
 		    continue;
 		}
 		/* ...or else... */
@@ -864,33 +908,39 @@
 static int
 brl1_send( l1sc_t *sc, char *msg, int len, u_char type_and_subch, int wait )
 {
+    unsigned long pl = 0;
     int index;
     int pkt_len = 0;
     unsigned short crc = INIT_CRC;
     char *send_ptr = sc->send;
 
-#ifdef BRINGUP
-    /* We want to be sure that we are sending the entire packet before returning */
-    wait = 1;
-#endif
-    if ( sc->uart == BRL1_LOCALUART )
-	lock_console(sc->nasid);
 
-    if( sc->send_in_use ) {
-	if( !wait ) {
-    	    if ( sc->uart == BRL1_LOCALUART )
-	    	unlock_console(sc->nasid);
-	    return 0; /* couldn't send anything; wait for buffer to drain */
-	}
-	else {
-	    /* buffer's in use, but we're synchronous I/O, so we're going
-	     * to send whatever's in there right now and take the buffer
-	     */
-	    while( sc->sent < sc->send_len )
+    if( sc->send_in_use && !(wait) ) {
+	/* We are in the middle of sending, but can wait until done */
+	return 0;
+    }
+    else if( sc->send_in_use ) {
+	/* buffer's in use, but we're synchronous I/O, so we're going
+	 * to send whatever's in there right now and take the buffer
+	 */
+	int counter = 0;
+
+	if ( sc->uart == BRL1_LOCALHUB_UART )
+		lock_console(sc->nasid);
+	L1SC_SEND_LOCK(sc, pl);
+	while( sc->sent < sc->send_len ) {
 		brl1_send_chars( sc );
+		if ( counter++ > 0xfffff ) {
+			char *str = "Looping waiting for uart to clear (1)\n";
+			early_l1_serial_out(sc->nasid, str, strlen(str), ALREADY_LOCKED);
+			break;
+		}
 	}
     }
     else {
+	if ( sc->uart == BRL1_LOCALHUB_UART )
+		lock_console(sc->nasid);
+	L1SC_SEND_LOCK(sc, pl);
 	sc->send_in_use = 1;
     }
     *send_ptr++ = BRL1_FLAG_CH;
@@ -948,23 +998,100 @@
     sc->send_len = pkt_len;
     sc->sent = 0;
 
-    do {
-	brl1_send_chars( sc );
-    } while( (sc->sent < sc->send_len) && wait );
+    {
+	int counter = 0;
+	do {
+		brl1_send_chars( sc );
+		if ( counter++ > 0xfffff ) {
+			char *str = "Looping waiting for uart to clear (2)\n";
+			early_l1_serial_out(sc->nasid, str, strlen(str), ALREADY_LOCKED);
+			break;
+		}
+	} while( (sc->sent < sc->send_len) && wait );
+    }
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(sc->nasid);
 
     if( sc->sent == sc->send_len ) {
-	/* success! release the send buffer */
+	/* success! release the send buffer and call the callup */
+#if	!defined(SYNC_CONSOLE_WRITE)
+	brl1_notif_t callup;
+#endif
+
 	sc->send_in_use = 0;
+	/* call any upper layer that's asked for notification */
+#if	defined(XX_SYNC_CONSOLE_WRITE)
+	/*
+	 * This is probably not a good idea - since the l1_ write func can be called multiple
+	 * time within the callup function.
+	 */
+	callup = subch->tx_notify;
+	if( callup && (SUBCH(type_and_subch) == SC_CONS_SYSTEM) ) {
+		L1_collectibles[L1C_SEND_CALLUPS]++;
+		(*callup)(sc->subch[SUBCH(type_and_subch)].irq_frame.bf_irq,
+				sc->subch[SUBCH(type_and_subch)].irq_frame.bf_dev_id,
+				sc->subch[SUBCH(type_and_subch)].irq_frame.bf_regs, sc, SUBCH(type_and_subch));
+	}
+#endif	/* SYNC_CONSOLE_WRITE */
     }
-    else if( !wait ) {
+#if	!defined(SYNC_CONSOLE_WRITE)
+    else if ( !wait ) {
 	/* enable low-water interrupts so buffer will be drained */
 	uart_enable_xmit_intr(sc);
     }
-    if ( sc->uart == BRL1_LOCALUART )
-	unlock_console(sc->nasid);
+#endif
+
+    L1SC_SEND_UNLOCK(sc, pl);
+
     return len;
 }
 
+/* brl1_send_cont is intended to be called as an interrupt service
+ * routine.  It sends until the UART won't accept any more characters,
+ * or until an error is encountered (in which case we surrender the
+ * send buffer and give up trying to send the packet).  Once the
+ * last character in the packet has been sent, this routine releases
+ * the send buffer and calls any previously-registered "low-water"
+ * output routines.
+ */
+
+#if	!defined(SYNC_CONSOLE_WRITE)
+
+int
+brl1_send_cont( l1sc_t *sc )
+{
+    unsigned long pl = 0;
+    int done = 0;
+    brl1_notif_t callups[BRL1_NUM_SUBCHANS];
+    brl1_notif_t *callup;
+    brl1_sch_t *subch;
+    int index;
+
+    /*
+     * I'm not sure how I think this is to be handled - whether the lock is held
+     * over the interrupt - but it seems like it is a bad idea....
+     */
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(sc->nasid);
+    L1SC_SEND_LOCK(sc, pl);
+    brl1_send_chars( sc );
+    done = (sc->sent == sc->send_len);
+    if( done ) {
+	sc->send_in_use = 0;
+#if	!defined(SYNC_CONSOLE_WRITE)
+	uart_disable_xmit_intr(sc);
+#endif
+    }
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(sc->nasid);
+    /* Release the lock */
+    L1SC_SEND_UNLOCK(sc, pl);
+
+    return 0;
+}
+#endif	/* SYNC_CONSOLE_WRITE */
 
 /* internal function -- used by brl1_receive to read a character 
  * from the uart and check whether errors occurred in the process.
@@ -1046,40 +1173,33 @@
  * error (parity error, bad header, bad CRC, etc.).
  */
 
-#define STATE_SET(l,s)	((l)->brl1_state = (s))
-#define STATE_GET(l)	((l)->brl1_state)
+#define STATE_SET(l,s)		((l)->brl1_state = (s))
+#define STATE_GET(l)		((l)->brl1_state)
 
 #define LAST_HDR_SET(l,h)	((l)->brl1_last_hdr = (h))
 #define LAST_HDR_GET(l)		((l)->brl1_last_hdr)
 
-#define SEQSTAMP_INCR(l)
-#define SEQSTAMP_GET(l)
-
 #define VALID_HDR(c)				\
     ( SUBCH((c)) <= SC_CONS_SYSTEM		\
 	? PKT_TYPE((c)) == BRL1_REQUEST		\
 	: ( PKT_TYPE((c)) == BRL1_RESPONSE ||	\
 	    PKT_TYPE((c)) == BRL1_EVENT ) )
 
-#define IS_TTY_PKT(l) \
-         ( SUBCH(LAST_HDR_GET(l)) <= SC_CONS_SYSTEM ? 1 : 0 )
+#define IS_TTY_PKT(l)		( SUBCH(LAST_HDR_GET(l)) <= SC_CONS_SYSTEM ? 1 : 0 )
 
 
 int
-brl1_receive( l1sc_t *sc )
+brl1_receive( l1sc_t *sc, int mode )
 {
     int result;		/* value to be returned by brl1_receive */
     int c;		/* most-recently-read character	     	*/
     int done;		/* set done to break out of recv loop	*/
+    unsigned long pl = 0, cpl = 0;
     sc_cq_t *q;		/* pointer to queue we're working with	*/
 
     result = BRL1_NO_MESSAGE;
 
-#ifdef FORCE_CONSOLE_NASID
-    sc->nasid = 0;
-#endif
-    if ( sc->uart == BRL1_LOCALUART )
-	lock_console(sc->nasid);
+    L1SC_RECV_LOCK(sc, cpl);
 
     done = 0;
     while( !done )
@@ -1210,8 +1330,7 @@
 		 * starting a new packet
 		 */
 		STATE_SET( sc, BRL1_FLAG );
-		SEQSTAMP_INCR(sc); /* bump the packet sequence counter */
-		
+
 		/* if the packet body has less than 2 characters,
 		 * it can't be a well-formed packet.  Discard it.
 		 */
@@ -1258,7 +1377,7 @@
 
 		/* get the subchannel and lock it */
 		subch = &(sc->subch[SUBCH( LAST_HDR_GET(sc) )]);
-		SUBCH_DATA_LOCK( subch );
+		SUBCH_DATA_LOCK( subch, pl );
 		
 		/* if this isn't a console packet, we need to record
 		 * a length byte
@@ -1276,14 +1395,16 @@
 		 */
 		atomic_inc(&(subch->packet_arrived));
 		callup = subch->rx_notify;
-		SUBCH_DATA_UNLOCK( subch );
+		SUBCH_DATA_UNLOCK( subch, pl );
 
-		if( callup ) {
-		    if ( sc->uart == BRL1_LOCALUART )
-			unlock_console(sc->nasid);
-		    (*callup)( sc, SUBCH(LAST_HDR_GET(sc)) );
-		    if ( sc->uart == BRL1_LOCALUART )
-			lock_console(sc->nasid);
+		if( callup && (mode == SERIAL_INTERRUPT_MODE) ) {
+		    L1SC_RECV_UNLOCK( sc, cpl );
+		    L1_collectibles[L1C_RECEIVE_CALLUPS]++;
+		    (*callup)( sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_irq,
+				sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_dev_id,
+				sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_regs,
+				sc, SUBCH(LAST_HDR_GET(sc)) );
+		    L1SC_RECV_LOCK( sc, cpl );
 		}
 		continue;	/* go back for more! */
 	    }
@@ -1351,9 +1472,8 @@
 
 	} /* end of switch( STATE_GET(sc) ) */
     } /* end of while(!done) */
-    
-    if ( sc->uart == BRL1_LOCALUART )
-	unlock_console(sc->nasid);
+
+    L1SC_RECV_UNLOCK( sc, cpl );
 
     return result;
 }	    
@@ -1370,13 +1490,10 @@
     brl1_sch_t *subch;
 
     bzero( sc, sizeof( *sc ) );
-#ifdef FORCE_CONSOLE_NASID
-    nasid = (nasid_t)0;
-#endif
     sc->nasid = nasid;
     sc->uart = uart;
-    sc->getc_f = (uart == BRL1_LOCALUART ? uart_getc : rtr_uart_getc);
-    sc->putc_f = (uart == BRL1_LOCALUART ? uart_putc : rtr_uart_putc);
+    sc->getc_f = (uart == BRL1_LOCALHUB_UART ? uart_getc : rtr_uart_getc);
+    sc->putc_f = (uart == BRL1_LOCALHUB_UART ? uart_putc : rtr_uart_putc);
     sc->sol = 1;
     subch = sc->subch;
 
@@ -1403,9 +1520,8 @@
     spin_lock_init( &(subch->data_lock) );
     sv_init( &(subch->arrive_sv), &subch->data_lock, SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */ );
     subch->tx_notify = NULL;
-    if( sc->uart == BRL1_LOCALUART ) {
-	subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
-				       NASID_TO_COMPACT_NODEID(nasid) );
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
+	subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP, NASID_TO_COMPACT_NODEID(nasid) );
 	ASSERT( subch->iqp );
 	cq_init( subch->iqp );
 	subch->rx_notify = NULL;
@@ -1440,8 +1556,10 @@
     /* initialize synchronization structures
      */
     spin_lock_init( &(sc->subch_lock) );
+    spin_lock_init( &(sc->send_lock) );
+    spin_lock_init( &(sc->recv_lock) );
 
-    if( sc->uart == BRL1_LOCALUART ) {
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
 	uart_init( sc, UART_BAUD_RATE );
     }
     else {
@@ -1461,93 +1579,574 @@
     }
 }
 
+/*********************************************************************
+ * These are interrupt-related functions used in the kernel to service
+ * the L1.
+ */
+
+/*
+ * brl1_intrd is the function which is called on a console interrupt.
+ */
 
-/* These are functions to use from serial_in/out when in protocol
- * mode to send and receive uart control regs. These are external
- * interfaces into the protocol driver.
+#if defined(CONFIG_IA64_SGI_SN1)
+
+static void
+brl1_intrd(int irq, void *dev_id, struct pt_regs *stuff)
+{
+    u_char isr_reg;
+    l1sc_t *sc = get_elsc();
+    int ret;
+
+    L1_collectibles[L1C_INTERRUPTS]++;
+    isr_reg = READ_L1_UART_REG(sc->nasid, REG_ISR);
+
+    /* Save for callup args in console */
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_irq = irq;
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_dev_id = dev_id;
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_regs = stuff;
+
+#if	defined(SYNC_CONSOLE_WRITE)
+    while( isr_reg & ISR_RxRDY )
+#else
+    while( isr_reg & (ISR_RxRDY | ISR_TxRDY) )
+#endif
+    {
+	if( isr_reg & ISR_RxRDY ) {
+	    L1_collectibles[L1C_OUR_R_INTERRUPTS]++;
+	    ret = brl1_receive(sc, SERIAL_INTERRUPT_MODE);
+	    if ( (ret != BRL1_VALID) && (ret != BRL1_NO_MESSAGE) && (ret != BRL1_PROTOCOL) && (ret != BRL1_CRC) )
+		L1_collectibles[L1C_REC_STALLS] = ret;
+	}
+#if	!defined(SYNC_CONSOLE_WRITE)
+	if( (isr_reg & ISR_TxRDY) || (sc->send_in_use && UART_PUTC_READY(sc->nasid)) ) {
+	    L1_collectibles[L1C_OUR_X_INTERRUPTS]++;
+	    brl1_send_cont(sc);
+	}
+#endif	/* SYNC_CONSOLE_WRITE */
+	isr_reg = READ_L1_UART_REG(sc->nasid, REG_ISR);
+    }
+}
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+
+/*
+ * Install a callback function for the system console subchannel 
+ * to allow an upper layer to be notified when the send buffer 
+ * has been emptied.
+ */
+static inline void
+l1_tx_notif( brl1_notif_t func )
+{
+	subch_set_tx_notify( &NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid()))->module->elsc,
+			SC_CONS_SYSTEM, func );
+}
+
+
+/*
+ * Install a callback function for the system console subchannel
+ * to allow an upper layer to be notified when a packet has been
+ * received.
+ */
+static inline void
+l1_rx_notif( brl1_notif_t func )
+{
+	subch_set_rx_notify( &NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid()))->module->elsc,
+				SC_CONS_SYSTEM, func );
+}
+
+
+/* brl1_intr is called directly from the uart interrupt; after it runs, the
+ * interrupt "daemon" xthread is signalled to continue.
  */
 void
-l1_control_out(int offset, int value)
+brl1_intr( void )
 {
-	nasid_t nasid = 0; //(get_elsc())->nasid;
-	WRITE_L1_UART_REG(nasid, offset, value); 
 }
 
+#define BRL1_INTERRUPT_LEVEL	65	/* linux request_irq() value */
+
+/* Return the current interrupt level */
+
+//#define CONSOLE_POLLING_ALSO
+
 int
-l1_control_in(int offset)
+l1_get_intr_value( void )
 {
-	nasid_t nasid = 0; //(get_elsc())->nasid;
-	return(READ_L1_UART_REG(nasid, offset)); 
+#if defined(USE_SAL_CONSOLE_IO)
+	return(0);
+#else
+#if defined(CONSOLE_POLLING_ALSO)
+	return(0);
+#else
+	return(BRL1_INTERRUPT_LEVEL);
+#endif /* CONSOLE_POLLING_ALSO */
+#endif /* USE_SAL_CONSOLE_IO */
 }
 
-#define PUTCHAR(ch) \
-    { \
-        while( (!(READ_L1_UART_REG( nasid, REG_LSR ) & LSR_XHRE)) || \
-                (!(READ_L1_UART_REG( nasid, REG_MSR ) & MSR_CTS)) ); \
-        WRITE_L1_UART_REG( nasid, REG_DAT, (ch) ); \
-    }
+/* Disconnect the callup functions - throw away interrupts */
 
-int
-l1_serial_out( char *str, int len )
+void
+l1_unconnect_intr(void)
 {
-    int sent = len;
-    char crc_char;
-    unsigned short crc = INIT_CRC;
-    nasid_t nasid = 0; //(get_elsc())->nasid;
+#if !defined(USE_SAL_CONSOLE_IO)
+	/* UnRegister the upper-level callup functions */
+	l1_rx_notif((brl1_notif_t)NULL);
+	l1_tx_notif((brl1_notif_t)NULL);
+	/* We do NOT unregister the interrupts */
+#endif /* !USE_SAL_CONSOLE_IO */
+}
 
-    lock_console(nasid);
+/* Set up uart interrupt handling for this node's uart */
 
-    PUTCHAR( BRL1_FLAG_CH );
-    PUTCHAR( BRL1_EVENT | SC_CONS_SYSTEM );
-    crc = crc16_calc( crc, (BRL1_EVENT | SC_CONS_SYSTEM) );
+void
+l1_connect_intr(void *rx_notify, void *tx_notify)
+{
+#if defined(USE_SAL_CONSOLE_IO)
+#if 0
+	// Will need code here for sn2 - something like this
+	console_nodepda = NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid());
+	intr_connect_level(console_nodepda->node_first_cpu,
+                                SGI_UART_VECTOR, INTPEND0_MAXMASK,
+                                dummy_intr_func);
+	request_irq(SGI_UART_VECTOR | (console_nodepda->node_first_cpu << 8),
+                                intr_func, SA_INTERRUPT | SA_SHIRQ,
+                                "l1_protocol_driver", (void *)sc);
+#endif
+#else
+	l1sc_t *sc;
+	nasid_t nasid;
+#if defined(CONFIG_IA64_SGI_SN1)
+	int tmp;
+#endif
+	nodepda_t *console_nodepda;
+	int intr_connect_level(cpuid_t, int, ilvl_t, intr_func_t);
 
-    while( len ) {
+	if ( L1_interrupts_connected ) {
+		/* Interrupts are connected, so just register the callups */
+		l1_rx_notif((brl1_notif_t)rx_notify);
+		l1_tx_notif((brl1_notif_t)tx_notify);
 
-	if( (*str == BRL1_FLAG_CH) || (*str == BRL1_ESC_CH) ) {
-	    PUTCHAR( BRL1_ESC_CH );
-	    PUTCHAR( (*str) ^ BRL1_XOR_CH );
+		L1_collectibles[L1C_CONNECT_CALLS]++;
+		return;
+	}
+	else
+		L1_interrupts_connected = 1;
+
+	nasid = get_master_nasid();
+	console_nodepda = NODEPDA(NASID_TO_COMPACT_NODEID(nasid));
+	sc = &console_nodepda->module->elsc;
+	sc->intr_cpu = console_nodepda->node_first_cpu;
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	if ( intr_connect_level(sc->intr_cpu, UART_INTR, INTPEND0_MAXMASK, (intr_func_t)brl1_intr) ) {
+		L1_interrupts_connected = 0; /* FAILS !! */
 	}
 	else {
-	    PUTCHAR( *str );
+		void synergy_intr_connect(int, int);
+
+		synergy_intr_connect(UART_INTR, sc->intr_cpu);
+		L1_collectibles[L1C_R_IRQ]++;
+		tmp = request_irq(BRL1_INTERRUPT_LEVEL, brl1_intrd, SA_INTERRUPT | SA_SHIRQ, "l1_protocol_driver", (void *)sc);
+		L1_collectibles[L1C_R_IRQ_RET] = (uint64_t)tmp;
+		if ( tmp ) {
+			L1_interrupts_connected = 0; /* FAILS !! */
+		}
+		else {
+			/* Register the upper-level callup functions */
+			l1_rx_notif((brl1_notif_t)rx_notify);
+			l1_tx_notif((brl1_notif_t)tx_notify);
+
+			/* Set the uarts the way we like it */
+			uart_enable_recv_intr( sc );
+			uart_disable_xmit_intr( sc );
+		}
 	}
-	
-	crc = crc16_calc( crc, *str );
+#endif	/* CONFIG_IA64_SGI_SN1 */
+#endif	/* USE_SAL_CONSOLE_IO */
+}
 
-	str++; len--;
-    }
-    
-    crc ^= 0xffff;
-    crc_char = crc & 0xff;
-    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
-	crc_char ^= BRL1_XOR_CH;
-	PUTCHAR( BRL1_ESC_CH );
-    }
-    PUTCHAR( crc_char );
-    crc_char = (crc >> 8) & 0xff;
-    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
-	crc_char ^= BRL1_XOR_CH;
-	PUTCHAR( BRL1_ESC_CH );
-    }
-    PUTCHAR( crc_char );
-    PUTCHAR( BRL1_FLAG_CH );
 
-    unlock_console(nasid);
-    return sent - len;
+/* These are functions to use from serial_in/out when in protocol
+ * mode to send and receive uart control regs. These are external
+ * interfaces into the protocol driver.
+ */
+
+void
+l1_control_out(int offset, int value)
+{
+#if defined(USE_SAL_CONSOLE_IO)
+	/* quietly ignore unless simulator */
+	if ( IS_RUNNING_ON_SIMULATOR() ) {
+		extern u64 master_node_bedrock_address;
+		if ( master_node_bedrock_address != (u64)0 ) {
+			writeb(value, (unsigned long)master_node_bedrock_address +
+				(offset<< 3));
+		}
+		return;
+	}
+#else
+	nasid_t nasid = get_master_nasid();
+	WRITE_L1_UART_REG(nasid, offset, value); 
+#endif
 }
 
+/* Console input exported interface. Return a register value.  */
+
 int
-l1_serial_in(void)
+l1_control_in_polled(int offset)
 {
-	static int l1_cons_getc( l1sc_t *sc );
+	static int l1_control_in_local(int, int);
 
-	return(l1_cons_getc(get_elsc()));
+	return(l1_control_in_local(offset, SERIAL_POLLED_MODE));
 }
 
+int
+l1_control_in(int offset)
+{
+	static int l1_control_in_local(int, int);
 
-/*********************************************************************
- * l1_cons functions
- *
- * These allow the L1 to act as the system console.  They're intended
+	return(l1_control_in_local(offset, SERIAL_INTERRUPT_MODE));
+}
+
+static int
+l1_control_in_local(int offset, int mode)
+{
+#if defined(USE_SAL_CONSOLE_IO)
+	int sal_call_status = 0, input;
+	int ret = 0;
+
+	if ( offset == REG_LSR ) {
+		ret = (LSR_XHRE | LSR_XSRE);	/* can send anytime */
+		sal_call_status = ia64_sn_console_check(&input);
+		if ( !sal_call_status && input ) {
+			/* input pending */
+			ret |= LSR_RCA;
+		}
+	}
+
+	/* If the sal call failed, do it the old-fashioned way */
+	if ( sal_call_status ) {
+		if ( IS_RUNNING_ON_SIMULATOR() ) {
+			extern u64 master_node_bedrock_address;
+			ret = readb((unsigned long)master_node_bedrock_address +
+					(offset<< 3));
+		}		
+		else {
+#endif	/* USE_SAL_CONSOLE_IO */
+			nasid_t nasid;
+			int ret, input;
+			static int l1_poll(l1sc_t *, int);
+
+			nasid = get_master_nasid();
+			ret = READ_L1_UART_REG(nasid, offset); 
+
+			if ( offset == REG_LSR ) {
+				ret |= (LSR_XHRE | LSR_XSRE);	/* can send anytime */
+				if ( L1_cons_is_inited ) {
+					if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 ) {
+						input = l1_poll(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, mode);
+						if ( input ) {
+							ret |= LSR_RCA;
+						}
+					}
+				}
+			}
+#if defined(USE_SAL_CONSOLE_IO)
+		}
+	}
+#endif
+	return(ret);
+}
+
+/*
+ * Console input exported interface. Return a character (if one is available)
+ */
+
+int
+l1_serial_in_polled(void)
+{
+	static int l1_serial_in_local(int mode);
+
+	return(l1_serial_in_local(SERIAL_POLLED_MODE));
+}
+
+int
+l1_serial_in(void)
+{
+	static int l1_serial_in_local(int mode);
+
+	return(l1_serial_in_local(SERIAL_INTERRUPT_MODE));
+}
+
+static int
+l1_serial_in_local(int mode)
+{
+#if defined(USE_SAL_CONSOLE_IO)
+	int sal_call_status;
+	int ch;
+
+	sal_call_status = ia64_sn_console_getc(&ch);
+	if ( !sal_call_status ) {
+		return(ch);
+	}
+	else {
+		/* If the sal called failed - do it the old-fashioned way */
+		if ( IS_RUNNING_ON_SIMULATOR() ) {
+			extern u64 master_node_bedrock_address;
+			return(readb((unsigned long)master_node_bedrock_address + (REG_DAT<< 3)));
+		}		
+		else {
+#endif	/* USE_SAL_CONSOLE_IO */
+			nasid_t nasid;
+			l1sc_t *sc;
+			int value;
+			static int l1_getc( l1sc_t *, int );
+			static inline l1sc_t *early_sc_init(nasid_t);
+
+			nasid = get_master_nasid();
+			sc = early_sc_init(nasid);
+			if ( L1_cons_is_inited ) {
+				if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 ) {
+					sc = &NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc;
+				}
+			}
+			value = l1_getc(sc, mode);
+			return(value);
+#if defined(USE_SAL_CONSOLE_IO)
+		}
+	}
+#endif
+}
+
+/* Console output exported interface. Write message to the console.  */
+
+int
+l1_serial_out( char *str, int len )
+{
+#if defined(USE_SAL_CONSOLE_IO)
+	int sal_call_status = 0;
+	int counter = len;
+
+	/* Attempt to write things out thru the sal */
+	while ( counter > 0 ) {
+		if ( (sal_call_status = ia64_sn_console_putc(*str)) ) {
+			break;
+		}
+		counter--;
+		str++;
+	}
+	if ( sal_call_status ) {
+		/* If the sal called failed - do it the old-fashioned way */
+		if ( IS_RUNNING_ON_SIMULATOR() ) {
+			extern u64 master_node_bedrock_address;
+                        if (!master_node_bedrock_address)
+                                early_sn_setup();
+			if ( master_node_bedrock_address != (u64)0 ) {
+#ifdef FLAG_DIRECT_CONSOLE_WRITES
+				/* This is an easy way to pre-pend the output to know whether the output
+				 * was done via sal or directly */
+				writeb('[', (unsigned long)master_node_bedrock_address + (REG_DAT<< 3));
+				writeb('+', (unsigned long)master_node_bedrock_address + (REG_DAT<< 3));
+				writeb(']', (unsigned long)master_node_bedrock_address + (REG_DAT<< 3));
+				writeb(' ', (unsigned long)master_node_bedrock_address + (REG_DAT<< 3));
+#endif	/* FLAG_DIRECT_CONSOLE_WRITES */
+				while ( counter > 0 ) {
+					writeb(*str, (unsigned long)master_node_bedrock_address + (REG_DAT<< 3));
+					counter--;
+					str++;
+				}
+			}
+		}
+		else {
+#endif	/* USE_SAL_CONSOLE_IO */
+			nasid_t nasid = get_master_nasid();
+			int l1_write(l1sc_t *, char *, int, int);
+
+			if ( L1_cons_is_inited ) {
+				if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 )
+					return(l1_write(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, str, len,
+#if	defined(SYNC_CONSOLE_WRITE)
+							1
+#else
+							!L1_interrupts_connected
+#endif
+									));
+			}
+			return(early_l1_serial_out(nasid, str, len, NOT_LOCKED));
+#if defined(USE_SAL_CONSOLE_IO)
+		}
+	}
+	return((counter <= 0) ? 0 : (len - counter));
+#endif
+}
+
+
+/*
+ * These are the 'early' functions - when we need to do things before we have
+ * all the structs setup.
+ */
+
+
+static l1sc_t Early_console;		/* fake l1sc_t */
+static int Early_console_inited = 0;
+
+static void
+early_brl1_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart )
+{
+    int i;
+    brl1_sch_t *subch;
+
+    bzero( sc, sizeof( *sc ) );
+    sc->nasid = nasid;
+    sc->uart = uart;
+    sc->getc_f = (uart == BRL1_LOCALHUB_UART ? uart_getc : rtr_uart_getc);
+    sc->putc_f = (uart == BRL1_LOCALHUB_UART ? uart_putc : rtr_uart_putc);
+    sc->sol = 1;
+    subch = sc->subch;
+
+    /* initialize L1 subchannels
+     */
+
+    /* assign processor TTY channels */
+    for( i = 0; i < CPUS_PER_NODE; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_RSVD;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+
+    /* assign system TTY channel (first free subchannel after each
+     * processor's individual TTY channel has been assigned)
+     */
+    subch->use = BRL1_SUBCH_RSVD;
+    subch->packet_arrived = ATOMIC_INIT(0);
+    subch->tx_notify = NULL;
+    subch->rx_notify = NULL;
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
+	static sc_cq_t x_iqp;
+
+	subch->iqp = &x_iqp;
+	ASSERT( subch->iqp );
+	cq_init( subch->iqp );
+    }
+    else {
+	/* we shouldn't be getting console input from remote UARTs */
+	subch->iqp = &sc->garbage_q;
+    }
+    subch++; i++;
+
+    /* "reserved" subchannels (0x05-0x0F); for now, throw away
+     * incoming packets
+     */
+    for( ; i < 0x10; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_FREE;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+
+    /* remaining subchannels are free */
+    for( ; i < BRL1_NUM_SUBCHANS; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_FREE;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+}
+
+static inline l1sc_t *
+early_sc_init(nasid_t nasid)
+{
+	/* This is for early I/O */
+	if ( Early_console_inited == 0 ) {
+    		early_brl1_init(&Early_console, nasid,  BRL1_LOCALHUB_UART);
+		Early_console_inited = 1;
+	}
+	return(&Early_console);
+}
+
+#define PUTCHAR(ch) \
+    { \
+        while( (!(READ_L1_UART_REG( nasid, REG_LSR ) & LSR_XHRE)) || \
+                (!(READ_L1_UART_REG( nasid, REG_MSR ) & MSR_CTS)) ); \
+        WRITE_L1_UART_REG( nasid, REG_DAT, (ch) ); \
+    }
+
+static int
+early_l1_serial_out( nasid_t nasid, char *str, int len, int lock_state )
+{
+	int ret, sent = 0;
+	char *msg = str;
+	static int early_l1_send( nasid_t nasid, char *str, int len, int lock_state );
+
+	while ( sent < len ) {
+		ret = early_l1_send(nasid, msg, len - sent, lock_state);
+		sent += ret;
+		msg += ret;
+	}
+	return(len);
+}
+
+static inline int
+early_l1_send( nasid_t nasid, char *str, int len, int lock_state )
+{
+    int sent;
+    char crc_char;
+    unsigned short crc = INIT_CRC;
+
+    if( len > (BRL1_QSIZE - 1) )
+	len = (BRL1_QSIZE - 1);
+
+    sent = len;
+    if ( lock_state == NOT_LOCKED )
+    	lock_console(nasid);
+
+    PUTCHAR( BRL1_FLAG_CH );
+    PUTCHAR( BRL1_EVENT | SC_CONS_SYSTEM );
+    crc = crc16_calc( crc, (BRL1_EVENT | SC_CONS_SYSTEM) );
+
+    while( len ) {
+
+	if( (*str == BRL1_FLAG_CH) || (*str == BRL1_ESC_CH) ) {
+	    PUTCHAR( BRL1_ESC_CH );
+	    PUTCHAR( (*str) ^ BRL1_XOR_CH );
+	}
+	else {
+	    PUTCHAR( *str );
+	}
+	
+	crc = crc16_calc( crc, *str );
+
+	str++; len--;
+    }
+    
+    crc ^= 0xffff;
+    crc_char = crc & 0xff;
+    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
+	crc_char ^= BRL1_XOR_CH;
+	PUTCHAR( BRL1_ESC_CH );
+    }
+    PUTCHAR( crc_char );
+    crc_char = (crc >> 8) & 0xff;
+    if( (crc_char == BRL1_ESC_CH) || (crc_char == BRL1_FLAG_CH) ) {
+	crc_char ^= BRL1_XOR_CH;
+	PUTCHAR( BRL1_ESC_CH );
+    }
+    PUTCHAR( crc_char );
+    PUTCHAR( BRL1_FLAG_CH );
+
+    if ( lock_state == NOT_LOCKED )
+    	unlock_console(nasid);
+    return sent;
+}
+
+/*********************************************************************
+ * l1_cons functions
+ *
+ * These allow the L1 to act as the system console.  They're intended
  * to abstract away most of the br/l1 internal details from the
  * _L1_cons_* functions (in the prom-- see "l1_console.c") and
  * l1_* functions (in the kernel-- see "sio_l1.c") that they support.
@@ -1555,12 +2154,16 @@
  */
 
 static int
-l1_cons_poll( l1sc_t *sc )
+l1_poll( l1sc_t *sc, int mode )
 {
+    int ret;
+
     /* in case this gets called before the l1sc_t structure for the module_t
      * struct for this node is initialized (i.e., if we're called with a
      * zero l1sc_t pointer)...
      */
+
+
     if( !sc ) {
 	return 0;
     }
@@ -1569,7 +2172,9 @@
 	return 1;
     }
 
-    brl1_receive( sc );
+    ret = brl1_receive( sc, mode );
+    if ( (ret != BRL1_VALID) && (ret != BRL1_NO_MESSAGE) && (ret != BRL1_PROTOCOL) && (ret != BRL1_CRC) )
+	L1_collectibles[L1C_REC_STALLS] = ret;
 
     if( atomic_read(&sc->subch[SC_CONS_SYSTEM].packet_arrived) ) {
 	return 1;
@@ -1581,43 +2186,65 @@
 /* pull a character off of the system console queue (if one is available)
  */
 static int
-l1_cons_getc( l1sc_t *sc )
+l1_getc( l1sc_t *sc, int mode )
 {
+    unsigned long pl = 0;
     int c;
 
     brl1_sch_t *subch = &(sc->subch[SC_CONS_SYSTEM]);
     sc_cq_t *q = subch->iqp;
 
-    if( !l1_cons_poll( sc ) ) {
+    if( !l1_poll( sc, mode ) ) {
 	return 0;
     }
 
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     if( cq_empty( q ) ) {
 	atomic_set(&subch->packet_arrived, 0);
-	SUBCH_DATA_UNLOCK( subch );
+	SUBCH_DATA_UNLOCK( subch, pl );
 	return 0;
     }
     cq_rem( q, c );
     if( cq_empty( q ) )
 	atomic_set(&subch->packet_arrived, 0);
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return c;
 }
 
+/*
+ * Write a message to the L1 on the system console subchannel.
+ *
+ * Danger: don't use a non-zero value for the wait parameter unless you're
+ * someone important (like a kernel error message).
+ */
+
+int
+l1_write( l1sc_t *sc, char *msg, int len, int wait )
+{
+	int sent = 0, ret = 0;
+
+	if ( wait ) {
+		while ( sent < len ) {
+			ret = brl1_send( sc, msg, len - sent, (SC_CONS_SYSTEM | BRL1_EVENT), wait );
+			sent += ret;
+			msg += ret;
+		}
+		ret = len;
+	}
+	else {
+		ret = brl1_send( sc, msg, len, (SC_CONS_SYSTEM | BRL1_EVENT), wait );
+	}
+	return(ret);
+}
 
 /* initialize the system console subchannel
  */
 void
-l1_cons_init( l1sc_t *sc )
+l1_init(void)
 {
-    brl1_sch_t *subch = &(sc->subch[SC_CONS_SYSTEM]);
-
-    SUBCH_DATA_LOCK( subch );
-    atomic_set(&subch->packet_arrived, 0);
-    cq_init( subch->iqp );
-    SUBCH_DATA_UNLOCK( subch );
+	/* All we do now is remember that we have been called */
+	L1_cons_is_inited = 1;
 }
 
 
@@ -1637,16 +2264,18 @@
 #define L1_DBG_PRF(x)
 #endif
 
-/* sc_data_ready is called to signal threads that are blocked on 
- * l1 input.
+/*
+ * sc_data_ready is called to signal threads that are blocked on l1 input.
  */
 void
-sc_data_ready( l1sc_t *sc, int ch )
+sc_data_ready( int dummy0, void *dummy1, struct pt_regs *dummy2, l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
+
     brl1_sch_t *subch = &(sc->subch[ch]);
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     sv_signal( &(subch->arrive_sv) );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 }
 
 /* sc_open reserves a subchannel to send a request to the L1 (the
@@ -1661,9 +2290,10 @@
      * subchannel assignment.
      */
     int ch;
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
 
     /* Look for a free subchannel. Subchannels 0-15 are reserved
      * for other purposes.
@@ -1676,12 +2306,12 @@
 
     if( ch == BRL1_NUM_SUBCHANS ) {
         /* there were no subchannels available! */
-        SUBCH_UNLOCK( sc );
+        SUBCH_UNLOCK( sc, pl );
         return SC_NSUBCH;
     }
 
     subch->use = BRL1_SUBCH_RSVD;
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     atomic_set(&subch->packet_arrived, 0);
     subch->target = target;
@@ -1689,7 +2319,7 @@
     sv_init( &(subch->arrive_sv), &(subch->data_lock), SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */);
     subch->tx_notify = NULL;
     subch->rx_notify = sc_data_ready;
-    subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
+    subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
 				   NASID_TO_COMPACT_NODEID(sc->nasid) );
     ASSERT( subch->iqp );
     cq_init( subch->iqp );
@@ -1703,29 +2333,31 @@
 int
 sc_close( l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
     subch = &(sc->subch[ch]);
     if( subch->use != BRL1_SUBCH_RSVD ) {
         /* we're trying to close a subchannel that's not open */
+	SUBCH_UNLOCK( sc, pl );
         return SC_NOPEN;
     }
 
     atomic_set(&subch->packet_arrived, 0);
     subch->use = BRL1_SUBCH_FREE;
 
-    SUBCH_DATA_LOCK( subch );
     sv_broadcast( &(subch->arrive_sv) );
     sv_destroy( &(subch->arrive_sv) );
-    SUBCH_DATA_UNLOCK( subch );
     spin_lock_destroy( &(subch->data_lock) );
 
     ASSERT( subch->iqp && (subch->iqp != &sc->garbage_q) );
-    kmem_free( subch->iqp, sizeof(sc_cq_t) );
+    snia_kmem_free( subch->iqp, sizeof(sc_cq_t) );
     subch->iqp = &sc->garbage_q;
+    subch->tx_notify = NULL;
+    subch->rx_notify = brl1_discard_packet;
 
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     return SC_SUCCESS;
 }
@@ -2003,9 +2635,6 @@
     return 0;
 }
 
-
-
-
 /* sc_send takes as arguments a system controller struct, a
  * buffer which contains a Bedrock<->L1 "request" message,
  * the message length, and the subchannel (presumably obtained
@@ -2033,11 +2662,10 @@
 
     /* Verify that this is an open subchannel
      */
-    if( sc->subch[ch].use == BRL1_SUBCH_FREE )
-    {
+    if( sc->subch[ch].use == BRL1_SUBCH_FREE ) {
         return SC_NOPEN;
     }
-       
+
     type_and_subch = (BRL1_REQUEST | ((u_char)ch));
     result = brl1_send( sc, msg, len, type_and_subch, wait );
 
@@ -2058,8 +2686,6 @@
 	return( result );
 }
 
-
-
 /* subch_pull_msg pulls a message off the receive queue for subch
  * and places it the buffer pointed to by msg.  This routine should only
  * be called when the caller already knows a message is available on the
@@ -2115,6 +2741,7 @@
 sc_recv_poll( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block )
 {
     int is_msg = 0;
+    unsigned long pl = 0;
     brl1_sch_t *subch = &(sc->subch[ch]);
 
     rtc_time_t exp_time = rtc_time() + block;
@@ -2127,7 +2754,7 @@
 
         /* kick the next lower layer and see if it pulls anything in
          */
-	brl1_receive( sc );
+	brl1_receive( sc, SERIAL_POLLED_MODE );
 	is_msg = atomic_read(&subch->packet_arrived);
 
     } while( block && !is_msg && (rtc_time() < exp_time) );
@@ -2137,9 +2764,9 @@
 	return( SC_NMSG );
     }
 
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     subch_pull_msg( subch, msg, len );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return( SC_SUCCESS );
 }
@@ -2156,10 +2783,11 @@
 sc_recv_intr( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block )
 {
     int is_msg = 0;
+    unsigned long pl = 0;
     brl1_sch_t *subch = &(sc->subch[ch]);
 
     do {
-	SUBCH_DATA_LOCK(subch);
+	SUBCH_DATA_LOCK(subch, pl);
 	is_msg = atomic_read(&subch->packet_arrived);
 	if( !is_msg && block ) {
 	    /* wake me when you've got something */
@@ -2178,12 +2806,12 @@
 
     if( !is_msg ) {
 	/* no message and we didn't care to wait for one */
-	SUBCH_DATA_UNLOCK( subch );
+	SUBCH_DATA_UNLOCK( subch, pl );
 	return( SC_NMSG );
     }
 
     subch_pull_msg( subch, msg, len );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return( SC_SUCCESS );
 }
@@ -2206,16 +2834,13 @@
  * rewriting of the L1 command interface anyway.)
  */
 #define __RETRIES	50
-#define __WAIT_SEND	( sc->uart != BRL1_LOCALUART )
+#define __WAIT_SEND	1	// ( sc->uart != BRL1_LOCALHUB_UART )
 #define __WAIT_RECV	10000000
 
 
 int
 sc_command( l1sc_t *sc, int ch, char *cmd, char *resp, int *len )
 {
-#ifndef CONFIG_SERIAL_SGI_L1_PROTOCOL
-    return SC_NMSG;
-#else
     int result;
     int retries;
 
@@ -2237,16 +2862,12 @@
     }
     
     /* block on sc_recv_* */
-#ifdef LATER
-    if( sc->uart == BRL1_LOCALUART ) {
+    if( (sc->uart == BRL1_LOCALHUB_UART) && L1_interrupts_connected ) {
 	return( sc_recv_intr( sc, ch, resp, len, __WAIT_RECV ) );
     }
-    else
-#endif	/* LATER */
-    {
+    else {
 	return( sc_recv_poll( sc, ch, resp, len, __WAIT_RECV ) );
     }
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 /* sc_command_kern is a knuckle-dragging, no-patience version of sc_command
@@ -2254,12 +2875,10 @@
  * delayed until the send buffer clears.  sc_command should be used instead
  * under most circumstances.
  */
+
 int
 sc_command_kern( l1sc_t *sc, int ch, char *cmd, char *resp, int *len )
 {
-#ifndef CONFIG_SERIAL_SGI_L1_PROTOCOL
-    return SC_NMSG;
-#else
     int result;
 
     if ( IS_RUNNING_ON_SIMULATOR() )
@@ -2270,7 +2889,6 @@
     }
 
     return( sc_recv_poll( sc, ch, resp, len, __WAIT_RECV ) );
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
 }
 
 
@@ -2282,6 +2900,7 @@
  * Returns 1 if input is available on the given queue,
  * 0 otherwise.
  */
+
 int
 sc_poll( l1sc_t *sc, int ch )
 {
@@ -2290,7 +2909,7 @@
     if( atomic_read(&subch->packet_arrived) )
 	return 1;
 
-    brl1_receive( sc );
+    brl1_receive( sc, SERIAL_POLLED_MODE );
 
     if( atomic_read(&subch->packet_arrived) )
 	return 1;
@@ -2298,8 +2917,8 @@
     return 0;
 }
 
-/* for now, sc_init just calls brl1_init
- */
+/* for now, sc_init just calls brl1_init */
+
 void
 sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart )
 {
@@ -2311,7 +2930,7 @@
  * network's environmental monitor tasks.
  */
 
-#ifdef LINUX_KERNEL_THREADS
+#if	defined(LINUX_KERNEL_THREADS)
 
 static void
 sc_dispatch_env_event( uint code, int argc, char *args, int maxlen )
@@ -2366,14 +2985,12 @@
 	     i++ );
     }
 }
-#endif	/* LINUX_KERNEL_THREADS */
 
 
 /* sc_event waits for events to arrive from the system controller, and
  * prints appropriate messages to the syslog.
  */
 
-#ifdef LINUX_KERNEL_THREADS
 static void
 sc_event( l1sc_t *sc, int ch )
 {
@@ -2394,7 +3011,7 @@
 	 */
 	result = sc_recv_intr( sc, ch, event, &event_len, 1 );
 	if( result != SC_SUCCESS ) {
-	    PRINT_WARNING("Error receiving sysctl event on nasid %d\n",
+	    printk(KERN_WARNING  "Error receiving sysctl event on nasid %d\n",
 		     sc->nasid );
 	}
 	else {
@@ -2438,53 +3055,50 @@
 	
     }			
 }
-#endif	/* LINUX_KERNEL_THREADS */
 
 /* sc_listen sets up a service thread to listen for incoming events.
  */
+
 void
 sc_listen( l1sc_t *sc )
 {
     int result;
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
     char        msg[BRL1_QSIZE];
     int         len;    /* length of message being sent */
     int         ch;     /* system controller subchannel used */
 
-#ifdef LINUX_KERNEL_THREADS
     extern int msc_shutdown_pri;
-#endif
 
     /* grab the designated "event subchannel" */
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
     subch = &(sc->subch[BRL1_EVENT_SUBCH]);
     if( subch->use != BRL1_SUBCH_FREE ) {
-	SUBCH_UNLOCK( sc );
-	PRINT_WARNING("sysctl event subchannel in use! "
+	SUBCH_UNLOCK( sc, pl );
+	printk(KERN_WARNING  "sysctl event subchannel in use! "
 		 "Not monitoring sysctl events.\n" );
 	return;
     }
     subch->use = BRL1_SUBCH_RSVD;
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     atomic_set(&subch->packet_arrived, 0);
-    subch->target = BRL1_LOCALUART;
+    subch->target = BRL1_LOCALHUB_UART;
     spin_lock_init( &(subch->data_lock) );
     sv_init( &(subch->arrive_sv), &(subch->data_lock), SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */);
     subch->tx_notify = NULL;
     subch->rx_notify = sc_data_ready;
-    subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
+    subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
 				   NASID_TO_COMPACT_NODEID(sc->nasid) );
     ASSERT( subch->iqp );
     cq_init( subch->iqp );
 
-#ifdef LINUX_KERNEL_THREADS
     /* set up a thread to listen for events */
     sthread_create( "sysctl event handler", 0, 0, 0, msc_shutdown_pri,
 		    KT_PS, (st_func_t *) sc_event,
 		    (void *)sc, (void *)(uint64_t)BRL1_EVENT_SUBCH, 0, 0 );
-#endif
 
     /* signal the L1 to begin sending events */
     bzero( msg, BRL1_QSIZE );
@@ -2522,276 +3136,8 @@
 	
 err_return:
     /* there was a problem; complain */
-    PRINT_WARNING("failed to set sysctl event-monitoring subchannel.  "
+    printk(KERN_WARNING  "failed to set sysctl event-monitoring subchannel.  "
 	     "Sysctl events will not be monitored.\n" );
 }
 
-
-/*********************************************************************
- * elscuart functions.  These provide a uart-like interface to the
- * bedrock/l1 protocol console channels.  They are similar in form
- * and intent to the elscuart_* functions defined for SN0 in elsc.c.
- *
- */
-
-int _elscuart_flush( l1sc_t *sc );
-
-/* Leave room in queue for CR/LF */
-#define ELSCUART_LINE_MAX       (BRL1_QSIZE - 2)
-
-
-/*
- * _elscuart_putc provides an entry point to the L1 interface driver;
- * writes a single character to the output queue.  Flushes at the
- * end of each line, and translates newlines into CR/LF.
- *
- * The kernel should generally use l1_cons_write instead, since it assumes
- * buffering, translation, prefixing, etc. are done at a higher
- * level.
- *
- */
-int
-_elscuart_putc( l1sc_t *sc, int c )
-{
-    sc_cq_t *q;
-    
-    q = &(sc->oq[ MAP_OQ(L1_ELSCUART_SUBCH(get_myid())) ]);
-
-    if( c != '\n' && c != '\r' && cq_used(q) >= ELSCUART_LINE_MAX ) {
-        cq_add( q, '\r' );
-        cq_add( q, '\n' );
-         _elscuart_flush( sc );
-        sc->sol = 1;
-    }
-
-    if( sc->sol && c != '\r' ) {
-        char            prefix[16], *s;
-
-        if( cq_room( q ) < 8 && _elscuart_flush(sc) < 0 )
-        {
-            return -1;
-        }
-	
-	if( sc->verbose )
-	{
-#ifdef  SUPPORT_PRINTING_M_FORMAT
-	    sprintf( prefix,
-		     "%c %d%d%d %M:",
-		     'A' + get_myid(),
-		     sc->nasid / 100,
-		     (sc->nasid / 10) % 10,
-		     sc->nasid / 10,
-		     sc->modid );
-#else
-	    sprintf( prefix,
-		     "%c %d%d%d 0x%x:",
-		     'A' + get_myid(),
-		     sc->nasid / 100,
-		     (sc->nasid / 10) % 10,
-		     sc->nasid / 10,
-		     sc->modid );
-#endif
-	    
-	    for( s = prefix; *s; s++ )
-		cq_add( q, *s );
-	}	    
-	sc->sol = 0;
-
-    }
-
-    if( cq_room( q ) < 2 && _elscuart_flush(sc) < 0 )
-    {
-        return -1;
-    }
-
-    if( c == '\n' ) {
-        cq_add( q, '\r' );
-        sc->sol = 1;
-    }
-
-    cq_add( q, (u_char) c );
-
-    if( c == '\n' ) {
-        /* flush buffered line */
-        if( _elscuart_flush( sc ) < 0 )
-        {
-            return -1;
-        }
-    }
-
-    if( c== '\r' )
-    {
-        sc->sol = 1;
-    }
-
-    return 0;
-}
-
-
-/*
- * _elscuart_getc reads a character from the input queue.  This
- * routine blocks.
- */
-int
-_elscuart_getc( l1sc_t *sc )
-{
-    int r;
-
-    while( (r = _elscuart_poll( sc )) == 0 );
-
-    if( r < 0 ) {
-	/* some error occurred */
-	return r;
-    }
-
-    return _elscuart_readc( sc );
-}
-
-
-
-/*
- * _elscuart_poll returns 1 if characters are ready for the
- * calling processor, 0 if they are not
- */
-int
-_elscuart_poll( l1sc_t *sc )
-{
-    int result;
-
-    if( sc->cons_listen ) {
-        result = l1_cons_poll( sc );
-        if( result )
-            return result;
-    }
-
-    return sc_poll( sc, L1_ELSCUART_SUBCH(get_myid()) );
-}
-
-
-
-/* _elscuart_readc is to be used only when _elscuart_poll has
- * indicated that a character is waiting.  Pulls a character
- * of this processor's console queue and returns it.
- *
- */
-int
-_elscuart_readc( l1sc_t *sc )
-{
-    int c;
-    sc_cq_t *q;
-    brl1_sch_t *subch;
-
-    if( sc->cons_listen ) {
-	subch = &(sc->subch[ SC_CONS_SYSTEM ]);
-	q = subch->iqp;
-	
-	SUBCH_DATA_LOCK( subch );
-        if( !cq_empty( q ) ) {
-            cq_rem( q, c );
-	    if( cq_empty( q ) ) {
-		atomic_set(&subch->packet_arrived, 0);
-	    }
-	    SUBCH_DATA_UNLOCK( subch );
-            return c;
-        }
-	SUBCH_DATA_UNLOCK( subch );
-    }
-
-    subch = &(sc->subch[ L1_ELSCUART_SUBCH(get_myid()) ]);
-    q = subch->iqp;
-
-    SUBCH_DATA_LOCK( subch );
-    if( cq_empty( q ) ) {
-	SUBCH_DATA_UNLOCK( subch );
-        return -1;
-    }
-
-    cq_rem( q, c );
-    if( cq_empty ( q ) ) {
-	atomic_set(&subch->packet_arrived, 0);
-    }
-    SUBCH_DATA_UNLOCK( subch );
-
-    return c;
-}
-
-
-/*
- * _elscuart_flush flushes queued output to the L1.
- * This routine blocks until the queue is flushed.
- */
-int
-_elscuart_flush( l1sc_t *sc )
-{
-    int r, n;
-    char buf[BRL1_QSIZE];
-    sc_cq_t *q = &(sc->oq[ MAP_OQ(L1_ELSCUART_SUBCH(get_myid())) ]);
-
-    while( (n = cq_used(q)) ) {
-
-        /* buffer queue contents */
-        r = BRL1_QSIZE - q->opos;
-
-        if( n > r ) {
-            BCOPY( q->buf + q->opos, buf, r  );
-            BCOPY( q->buf, buf + r, n - r  );
-        } else {
-            BCOPY( q->buf + q->opos, buf, n  );
-        }
-
-        /* attempt to send buffer contents */
-        r = brl1_send( sc, buf, cq_used( q ), 
-		       (BRL1_EVENT | L1_ELSCUART_SUBCH(get_myid())), 1 );
-
-        /* if no error, dequeue the sent characters; otherwise,
-         * return the error
-         */
-        if( r >= SC_SUCCESS ) {
-            q->opos = (q->opos + r) % BRL1_QSIZE;
-        }
-        else {
-            return r;
-        }
-    }
-
-    return 0;
-}
-
-
-
-/* _elscuart_probe returns non-zero if the L1 (and
- * consequently the elscuart) can be accessed
- */
-int
-_elscuart_probe( l1sc_t *sc )
-{
-#ifndef CONFIG_SERIAL_SGI_L1_PROTOCOL
-    return 0;
-#else
-    char ver[BRL1_QSIZE];
-    extern int elsc_version( l1sc_t *, char * );
-
-    if ( IS_RUNNING_ON_SIMULATOR() )
-    	return 0;
-    return( elsc_version(sc, ver) >= 0 );
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
-}
-
-
-
-/* _elscuart_init zeroes out the l1sc_t console
- * queues for this processor's console subchannel.
- */
-void
-_elscuart_init( l1sc_t *sc )
-{
-    brl1_sch_t *subch = &sc->subch[L1_ELSCUART_SUBCH(get_myid())];
-
-    SUBCH_DATA_LOCK(subch);
-
-    atomic_set(&subch->packet_arrived, 0);
-    cq_init( subch->iqp );
-    cq_init( &sc->oq[MAP_OQ(L1_ELSCUART_SUBCH(get_myid()))] );
-
-    SUBCH_DATA_UNLOCK(subch);
-}
+#endif	/* LINUX_KERNEL_THREADS */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/l1_command.c linux/arch/ia64/sn/io/l1_command.c
--- linux.orig/arch/ia64/sn/io/l1_command.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/l1_command.c	2002-08-01 06:42:44.000000000 +0000
@@ -4,20 +4,20 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */ 
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
@@ -27,7 +27,6 @@
 #define ELSC_TIMEOUT	1000000		/* ELSC response timeout (usec) */
 #define LOCK_TIMEOUT	5000000		/* Hub lock timeout (usec) */
 
-#define LOCAL_HUB	LOCAL_HUB_ADDR
 #define LD(x)		(*(volatile uint64_t *)(x))
 #define SD(x, v)	(LD(x) = (uint64_t) (v))
 
@@ -75,7 +74,7 @@
 
 void elsc_init(elsc_t *e, nasid_t nasid)
 {
-    sc_init((l1sc_t *)e, nasid, BRL1_LOCALUART);
+    sc_init((l1sc_t *)e, nasid, BRL1_LOCALHUB_UART);
 }
 
 
@@ -1377,84 +1376,3 @@
 
     return 0;
 }
-
-
-
-/* elscuart routines 
- *
- * Most of the elscuart functionality is implemented in l1.c.  The following
- * is directly "recycled" from elsc.c.
- */
-
-
-/*
- * _elscuart_puts
- */
-
-int _elscuart_puts(elsc_t *e, char *s)
-{
-    int			c;
-
-    if (s == 0)
-	s = "<NULL>";
-
-    while ((c = LBYTE(s)) != 0) {
-	if (_elscuart_putc(e, c) < 0)
-	    return -1;
-	s++;
-    }
-
-    return 0;
-}
-
-
-/*
- * elscuart wrapper routines
- *
- *   The following routines are similar to their counterparts in l1.c,
- *   except instead of taking an elsc_t pointer directly, they call
- *   a global routine "get_elsc" to obtain the pointer.
- *   This is useful when the elsc is employed for stdio.
- */
-
-int elscuart_probe(void)
-{
-    return _elscuart_probe(get_elsc());
-}
-
-void elscuart_init(void *init_data)
-{
-    _elscuart_init(get_elsc());
-    /* dummy variable included for driver compatability */
-    init_data = init_data;
-}
-
-int elscuart_poll(void)
-{
-    return _elscuart_poll(get_elsc());
-}
-
-int elscuart_readc(void)
-{
-    return _elscuart_readc(get_elsc());
-}
-
-int elscuart_getc(void)
-{
-    return _elscuart_getc(get_elsc());
-}
-
-int elscuart_puts(char *s)
-{
-    return _elscuart_puts(get_elsc(), s);
-}
-
-int elscuart_putc(int c)
-{
-    return _elscuart_putc(get_elsc(), c);
-}
-
-int elscuart_flush(void)
-{
-    return _elscuart_flush(get_elsc());
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/labelcl.c linux/arch/ia64/sn/io/labelcl.c
--- linux.orig/arch/ia64/sn/io/labelcl.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/labelcl.c	2002-08-01 06:42:41.000000000 +0000
@@ -1,21 +1,10 @@
 /*  labelcl - SGI's Hwgraph Compatibility Layer.
-
-    This library is free software; you can redistribute it and/or
-    modify it under the terms of the GNU Library General Public
-    License as published by the Free Software Foundation; either
-    version 2 of the License, or (at your option) any later version.
-
-    This library is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-    Library General Public License for more details.
-
-    You should have received a copy of the GNU Library General Public
-    License along with this library; if not, write to the Free
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-    Colin Ngam may be reached by email at cngam@sgi.com
-
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
 */
 
 #include <linux/types.h>
@@ -286,7 +275,7 @@
 		if (!strcmp(info_name, old_label_list[i].name)) {
 			/* Not allowed to add duplicate labelled info names. */
 			kfree(new_label_list);
-			printk(KERN_WARNING "labelcl_info_add_LBL: Duplicate label name %s for vertex 0x%p\n", info_name, de);
+			printk(KERN_WARNING "labelcl_info_add_LBL: Duplicate label name %s for vertex 0x%p\n", info_name, (void *)de);
 			return(-1);
 		}
 		new_label_list[i] = old_label_list[i]; /* structure copy */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/mem_refcnt.c linux/arch/ia64/sn/io/mem_refcnt.c
--- linux.orig/arch/ia64/sn/io/mem_refcnt.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/mem_refcnt.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,222 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#include <linux/types.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/hcl_util.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/hubspc.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/mem_refcnt.h>
-#include <asm/sn/hwcntrs.h>
-// From numa_hw.h
-
-#define MIGR_COUNTER_MAX_GET(nodeid) \
-        (NODEPDA_MCD((nodeid))->migr_system_kparms.migr_threshold_reference)
-/*
- * Get the Absolute Theshold
- */
-#define MIGR_THRESHOLD_ABS_GET(nodeid) ( \
-        MD_MIG_VALUE_THRESH_GET(COMPACT_TO_NASID_NODEID(nodeid)))
-/*
- * Get the current Differential Threshold
- */
-#define MIGR_THRESHOLD_DIFF_GET(nodeid) \
-        (NODEPDA_MCD(nodeid)->migr_as_kparms.migr_base_threshold)
-
-#define NUM_OF_HW_PAGES_PER_SW_PAGE()   (NBPP / MD_PAGE_SIZE)
-
-// #include "migr_control.h"
-
-int
-mem_refcnt_attach(devfs_handle_t hub)
-{
-        devfs_handle_t refcnt_dev;
-        
-        hwgraph_char_device_add(hub,
-                                "refcnt",
-                                "hubspc_", 
-				&refcnt_dev);
-        device_info_set(refcnt_dev, (void*)(ulong)HUBSPC_REFCOUNTERS);
-
-        return (0);
-}
-
-
-/*ARGSUSED*/
-int
-mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
-{
-        cnodeid_t node;
-
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(*devp) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(*devp);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        if (NODEPDA(node)->migr_refcnt_counterbuffer == NULL) {
-                return (ENODEV);
-        }
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != (size_t)0 );
-
-        return (0);
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
-{
-        return 0;
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
-{
-        cnodeid_t node;
-        int errcode;
-        char* buffer;
-        size_t blen;
-        
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(dev) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(dev);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
-
-        /*
-         * XXXX deal with prot's somewhere around here....
-         */
-
-        buffer = NODEPDA(node)->migr_refcnt_counterbuffer;
-        blen = NODEPDA(node)->migr_refcnt_cbsize;
-
-        /*
-         * Force offset to be a multiple of sizeof(refcnt_t)
-         * We round up.
-         */
-
-        off = (((off - 1)/sizeof(refcnt_t)) + 1) * sizeof(refcnt_t);
-
-        if ( ((buffer + blen) - (buffer + off + len)) < 0 ) {
-                return (EPERM);
-        }
-
-        errcode = v_mapphys(vt,
-                            buffer + off,
-                            len);
-
-        return errcode;
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt)
-{
-        return 0;
-}
-
-/* ARGSUSED */
-int
-mem_refcnt_ioctl(devfs_handle_t dev,
-                 int cmd,
-                 void *arg,
-                 int mode,
-                 cred_t *cred_p,
-                 int *rvalp)
-{
-        cnodeid_t node;
-        int errcode;
-	extern int numnodes;
-        
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(dev) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(dev);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
-
-        errcode = 0;
-        
-        switch (cmd) {
-        case RCB_INFO_GET:
-        {
-                rcb_info_t rcb;
-                
-                rcb.rcb_len = NODEPDA(node)->migr_refcnt_cbsize;
-                
-                rcb.rcb_sw_sets = NODEPDA(node)->migr_refcnt_numsets;
-                rcb.rcb_sw_counters_per_set = numnodes;
-                rcb.rcb_sw_counter_size = sizeof(refcnt_t);
-
-                rcb.rcb_base_pages = NODEPDA(node)->migr_refcnt_numsets /
-                                     NUM_OF_HW_PAGES_PER_SW_PAGE();  
-                rcb.rcb_base_page_size = NBPP;
-                rcb.rcb_base_paddr = ctob(slot_getbasepfn(node, 0));
-                
-                rcb.rcb_cnodeid = node;
-                rcb.rcb_granularity = MD_PAGE_SIZE;
-#ifdef LATER
-                rcb.rcb_hw_counter_max = MIGR_COUNTER_MAX_GET(node);
-                rcb.rcb_diff_threshold = MIGR_THRESHOLD_DIFF_GET(node);
-#endif
-                rcb.rcb_abs_threshold = MIGR_THRESHOLD_ABS_GET(node);
-                rcb.rcb_num_slots = node_getnumslots(node);
-
-                if (COPYOUT(&rcb, arg, sizeof(rcb_info_t))) {
-                        errcode = EFAULT;
-                }
-
-                break;
-        }
-        case RCB_SLOT_GET:
-        {
-                rcb_slot_t slot[MAX_MEM_SLOTS];
-                int s;
-                int nslots;
-
-                nslots = node_getnumslots(node);
-                ASSERT(nslots <= MAX_MEM_SLOTS);
-                for (s = 0; s < nslots; s++) {
-                        slot[s].base = (uint64_t)ctob(slot_getbasepfn(node, s));
-#ifdef LATER
-                        slot[s].size  = (uint64_t)ctob(slot_getsize(node, s));
-#else
-                        slot[s].size  = (uint64_t)1;
-#endif
-                }
-                if (COPYOUT(&slot[0], arg, nslots * sizeof(rcb_slot_t))) {
-                        errcode = EFAULT;
-                }
-                
-                *rvalp = nslots;
-                break;
-        }
-                
-        default:
-                errcode = EINVAL;
-                break;
-
-        }
-        
-        return errcode;
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/ml_SN_init.c linux/arch/ia64/sn/io/ml_SN_init.c
--- linux.orig/arch/ia64/sn/io/ml_SN_init.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/ml_SN_init.c	2002-08-01 06:42:32.000000000 +0000
@@ -4,37 +4,30 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
+#include <linux/bootmem.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_cpuid.h>
-#include <asm/sn/synergy.h>
-
-
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/ip27config.h>
-#include <asm/sn/sn1/hubdev.h>
-#include <asm/sn/sn1/sn1.h>
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
+#include <asm/sn/snconfig.h>
 
 extern int numcpus;
 extern char arg_maxnodes[];
 extern cpuid_t master_procid;
-extern void * kmem_alloc_node(register size_t, register int , cnodeid_t);
+#if defined(CONFIG_IA64_SGI_SN1)
 extern synergy_da_t    *Synergy_da_indr[];
+#endif
 
 extern int hasmetarouter;
 
@@ -45,18 +38,8 @@
 
 extern xwidgetnum_t hub_widget_id(nasid_t);
 
-static int	fine_mode = 0;
-
-static cnodemask_t	hub_init_mask;	/* Mask of cpu in a node doing init */
-static volatile cnodemask_t hub_init_done_mask;
-					/* Node mask where we wait for
-					 * per hub initialization
-					 */
-spinlock_t		hub_mask_lock;  /* Lock for hub_init_mask above. */
-
 extern int valid_icache_reasons;	/* Reasons to flush the icache */
 extern int valid_dcache_reasons;	/* Reasons to flush the dcache */
-extern int numnodes;
 extern u_char miniroot;
 extern volatile int	need_utlbmiss_patch;
 extern void iograph_early_init(void);
@@ -83,20 +66,6 @@
 		 */ 
 		master_nasid = get_nasid();
 		set_master_bridge_base();
-		FIXME("mlreset: Enable when we support ioc3 ..");
-#ifdef	LATER
-		if (get_console_nasid() == master_nasid) 
-			/* Set up the IOC3 */
-			ioc3_mlreset((ioc3_cfg_t *)KL_CONFIG_CH_CONS_INFO(master_nasid)->config_base,
-				     (ioc3_mem_t *)KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base);
-
-		/*
-		 * Initialize Master nvram base.
-		 */
-		nvram_baseinit();
-
-		fine_mode = is_fine_dirmode();
-#endif /* LATER */
 
 		/* We're the master processor */
 		master_procid = smp_processor_id();
@@ -108,75 +77,12 @@
 		 */
 		ASSERT_ALWAYS(master_nasid == get_nasid());
 
-#ifdef	LATER
-
-	/*
-	 * Activate when calias is implemented.
-	 */
-		/* Set all nodes' calias sizes to 8k */
-		for (i = 0; i < maxnodes; i++) {
-			nasid_t nasid;
-			int	sn;
-
-			nasid = COMPACT_TO_NASID_NODEID(i);
-
-			/*
-			 * Always have node 0 in the region mask, otherwise CALIAS accesses
-			 * get exceptions since the hub thinks it is a node 0 address.
-			 */
-			for (sn=0; sn<NUM_SUBNODES; sn++) {
-				REMOTE_HUB_PI_S(nasid, sn, PI_REGION_PRESENT, (region_mask | 1));
-				REMOTE_HUB_PI_S(nasid, sn, PI_CALIAS_SIZE, PI_CALIAS_SIZE_8K);
-			}
-
-			/*
-			 * Set up all hubs to havew a big window pointing at
-			 * widget 0.
-			 * Memory mode, widget 0, offset 0
-			 */
-			REMOTE_HUB_S(nasid, IIO_ITTE(SWIN0_BIGWIN),
-				((HUB_PIO_MAP_TO_MEM << IIO_ITTE_IOSP_SHIFT) |
-				(0 << IIO_ITTE_WIDGET_SHIFT)));
-		}
-#endif /* LATER */
-
-		/* Set up the hub initialization mask and init the lock */
-		CNODEMASK_CLRALL(hub_init_mask);
-		CNODEMASK_CLRALL(hub_init_done_mask);
-
-		spin_lock_init(&hub_mask_lock);
-
 		/* early initialization of iograph */
 		iograph_early_init();
 
 		/* Initialize Hub Pseudodriver Management */
 		hubdev_init();
 
-#ifdef	LATER
-		/*
-		 * Our IO system doesn't require cache writebacks.  Set some
-		 * variables appropriately.
-		 */
-		cachewrback = 0;
-		valid_icache_reasons &= ~(CACH_AVOID_VCES | CACH_IO_COHERENCY);
-		valid_dcache_reasons &= ~(CACH_AVOID_VCES | CACH_IO_COHERENCY);
-
-		/*
-		 * make sure we are running with the right rev of chips
-		 */
-		verify_snchip_rev();
-
-		/*
-                 * Since we've wiped out memory at this point, we
-                 * need to reset the ARCS vector table so that it
-                 * points to appropriate functions in the kernel
-                 * itself.  In this way, we can maintain the ARCS
-                 * vector table conventions without having to actually
-                 * keep redundant PROM code in memory.
-                 */
-		he_arcs_set_vectors();
-#endif /* LATER */
-
 	} else { /* slave != 0 */
 		/*
 		 * This code is performed ONLY by slave processors.
@@ -193,34 +99,17 @@
 void init_platform_nodepda(nodepda_t *npda, cnodeid_t node)
 {
 	hubinfo_t hubinfo;
+#ifdef CONFIG_IA64_SGI_SN1
 	int	  sn;
-	cnodeid_t i;
-	ushort *numcpus_p;
+#endif
 
 	extern void router_map_init(nodepda_t *);
 	extern void router_queue_init(nodepda_t *,cnodeid_t);
 	extern void intr_init_vecblk(nodepda_t *, cnodeid_t, int);
 
-#if defined(DEBUG)
-	extern spinlock_t	intr_dev_targ_map_lock;
-	extern uint64_t 	intr_dev_targ_map_size;
-
-	/* Initialize the lock to access the device - target cpu mapping
-	 * table. This table is explicitly for debugging purposes only and
-	 * to aid the "intrmap" idbg command
-	 */
-	if (node == 0) {
-		/* Make sure we do this only once .
-		 * There is always a cnode 0 present.
-		 */
-		intr_dev_targ_map_size = 0;
-		spin_lock_init(&intr_dev_targ_map_lock);
-	}
-#endif	/* DEBUG */
 	/* Allocate per-node platform-dependent data */
-	hubinfo = (hubinfo_t)kmem_alloc_node(sizeof(struct hubinfo_s), GFP_ATOMIC, node);
+	hubinfo = (hubinfo_t)alloc_bootmem_node(NODE_DATA(node), sizeof(struct hubinfo_s));
 
-	ASSERT_ALWAYS(hubinfo);
 	npda->pdinfo = (void *)hubinfo;
 	hubinfo->h_nodepda = npda;
 	hubinfo->h_cnodeid = node;
@@ -230,92 +119,37 @@
 
 	hubinfo->h_widgetid = hub_widget_id(hubinfo->h_nasid);
 	npda->xbow_peer = INVALID_NASID;
-	/* Initialize the linked list of
+
+	/* 
+	 * Initialize the linked list of
 	 * router info pointers to the dependent routers
 	 */
 	npda->npda_rip_first = NULL;
-	/* npda_rip_last always points to the place
+
+	/*
+	 * npda_rip_last always points to the place
 	 * where the next element is to be inserted
 	 * into the list 
 	 */
 	npda->npda_rip_last = &npda->npda_rip_first;
-	npda->dependent_routers = 0;
 	npda->module_id = INVALID_MODULE;
 
+#ifdef CONFIG_IA64_SGI_SN1
 	/*
-	 * Initialize the subnodePDA.
-	 */
+	* Initialize the interrupts.
+	* On sn2, this is done at pci init time,
+	* because sn2 needs the cpus checked in
+	* when it initializes interrupts.  This is
+	* so we don't see all the nodes as headless.
+	*/
 	for (sn=0; sn<NUM_SUBNODES; sn++) {
-		SNPDA(npda,sn)->prof_count = 0;
-		SNPDA(npda,sn)->next_prof_timeout = 0;
 		intr_init_vecblk(npda, node, sn);
 	}
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-	npda->vector_unit_busy = 0;
-
-	spin_lock_init(&npda->vector_lock);
 	mutex_init_locked(&npda->xbow_sema); /* init it locked? */
-	spin_lock_init(&npda->fprom_lock);
 
-	spin_lock_init(&npda->node_utlbswitchlock);
-	npda->ni_error_print = 0;
 #ifdef	LATER
-	if (need_utlbmiss_patch) {
-		npda->node_need_utlbmiss_patch = 1;
-		npda->node_utlbmiss_patched = 1;
-	}
-#endif
-
-	/*
-	 * Clear out the nasid mask.
-	 */
-	for (i = 0; i < NASID_MASK_BYTES; i++)
-		npda->nasid_mask[i] = 0;
-
-	for (i = 0; i < numnodes; i++) {
-		nasid_t nasid = COMPACT_TO_NASID_NODEID(i);
-
-		/* Set my mask bit */
-		npda->nasid_mask[nasid / 8] |= (1 << nasid % 8);
-	}
-
-#ifdef	LATER
-	npda->node_first_cpu = get_cnode_cpu(node);
-#endif
-
-	if (npda->node_first_cpu != CPU_NONE) {
-		/*
-		 * Count number of cpus only if first CPU is valid.
-		 */
-		numcpus_p = &npda->node_num_cpus;
-		*numcpus_p = 0;
-		for (i = npda->node_first_cpu; i < MAXCPUS; i++) {
-			if (CPUID_TO_COMPACT_NODEID(i) != node)
-			    break;
-			else
-			    (*numcpus_p)++;
-		}
-	} else {
-		npda->node_num_cpus = 0; 
-	}
-
-	/* Allocate memory for the dump stack on each node 
-	 * This is useful during nmi handling since we
-	 * may not be guaranteed shared memory at that time
-	 * which precludes depending on a global dump stack
-	 */
-#ifdef	LATER
-	npda->dump_stack = (uint64_t *)kmem_zalloc_node(DUMP_STACK_SIZE,VM_NOSLEEP,
-							  node);
-	ASSERT_ALWAYS(npda->dump_stack);
-	ASSERT(npda->dump_stack);
-#endif
-	/* Initialize the counter which prevents
-	 * both the cpus on a node to proceed with nmi
-	 * handling.
-	 */
-#ifdef	LATER
-	npda->dump_count = 0;
 
 	/* Setup the (module,slot) --> nic mapping for all the routers
 	 * in the system. This is useful during error handling when
@@ -325,17 +159,9 @@
 
 	/* Allocate memory for the per-node router traversal queue */
 	router_queue_init(npda,node);
-	npda->sbe_info = kmem_zalloc_node_hint(sizeof (sbe_info_t), 0, node);
+	npda->sbe_info = alloc_bootmem_node(NODE_DATA(node), sizeof (sbe_info_t));
 	ASSERT(npda->sbe_info);
 
-#ifdef CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-	/*
-	 * Initialize bte info pointers to NULL
-	 */
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		npda->node_bte_info[i] = (bteinfo_t *)NULL;
-	}
-#endif
 #endif /* LATER */
 }
 
@@ -345,260 +171,44 @@
  * Must be done _after_ init_platform_nodepda().
  * If we need a lock here, something else is wrong!
  */
-// void init_platform_pda(pda_t *ppda, cpuid_t cpu)
 void init_platform_pda(cpuid_t cpu)
 {
+#if defined(CONFIG_IA64_SGI_SN1)
 	hub_intmasks_t *intmasks;
-#ifdef	LATER
-	cpuinfo_t cpuinfo;
-#endif
-	int i;
+	int i, subnode;
 	cnodeid_t	cnode;
 	synergy_da_t	*sda;
 	int	which_synergy;
 
-#ifdef	LATER
-	/* Allocate per-cpu platform-dependent data */
-	cpuinfo = (cpuinfo_t)kmem_alloc_node(sizeof(struct cpuinfo_s), GFP_ATOMIC, cputocnode(cpu));
-	ASSERT_ALWAYS(cpuinfo);
-	ppda->pdinfo = (void *)cpuinfo;
-	cpuinfo->ci_cpupda = ppda;
-	cpuinfo->ci_cpuid = cpu;
-#endif
 
 	cnode = cpuid_to_cnodeid(cpu);
 	which_synergy = cpuid_to_synergy(cpu);
+
 	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-	// intmasks = &ppda->p_intmasks;
 	intmasks = &sda->s_intmasks;
 
-#ifdef	LATER
-	ASSERT_ALWAYS(&ppda->p_nodepda);
-#endif
-
 	/* Clear INT_PEND0 masks. */
 	for (i = 0; i < N_INTPEND0_MASKS; i++)
 		intmasks->intpend0_masks[i] = 0;
 
 	/* Set up pointer to the vector block in the nodepda. */
 	/* (Cant use SUBNODEPDA - not working yet) */
-	intmasks->dispatch0 = &Nodepdaindr[cnode]->snpda[cpuid_to_subnode(cpu)].intr_dispatch0;
-	intmasks->dispatch1 = &Nodepdaindr[cnode]->snpda[cpuid_to_subnode(cpu)].intr_dispatch1;
+	subnode = cpuid_to_subnode(cpu);
+	intmasks->dispatch0 = &NODEPDA(cnode)->snpda[cpuid_to_subnode(cpu)].intr_dispatch0;
+	intmasks->dispatch1 = &NODEPDA(cnode)->snpda[cpuid_to_subnode(cpu)].intr_dispatch1;
+	if (intmasks->dispatch0 !=  &SUBNODEPDA(cnode, subnode)->intr_dispatch0 ||
+	   intmasks->dispatch1 !=  &SUBNODEPDA(cnode, subnode)->intr_dispatch1)
+	   	panic("xxx");
+	intmasks->dispatch0 = &SUBNODEPDA(cnode, subnode)->intr_dispatch0;
+	intmasks->dispatch1 = &SUBNODEPDA(cnode, subnode)->intr_dispatch1;
 
 	/* Clear INT_PEND1 masks. */
 	for (i = 0; i < N_INTPEND1_MASKS; i++)
 		intmasks->intpend1_masks[i] = 0;
-
-
-#ifdef	LATER
-	/* Don't read the routers unless we're the master. */
-	ppda->p_routertick = 0;
-#endif
-
+#endif	/* CONFIG_IA64_SGI_SN1 */
 }
 
-#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && !defined(BRINGUP)	/* protect low mem for IP35/7 */
-#error "need protect_hub_calias, protect_nmi_handler_data"
-#endif
-
-#ifdef	LATER
-/*
- * For now, just protect the first page (exception handlers). We
- * may want to protect more stuff later.
- */
 void
-protect_hub_calias(nasid_t nasid)
-{
-	paddr_t pa = NODE_OFFSET(nasid) + 0; /* page 0 on node nasid */
-	int i;
-
-	for (i = 0; i < MAX_REGIONS; i++) {
-		if (i == nasid_to_region(nasid))
-			continue;
-	}
-}
-
-/*
- * Protect the page of low memory used to communicate with the NMI handler.
- */
-void
-protect_nmi_handler_data(nasid_t nasid, int slice)
-{
-	paddr_t pa = NODE_OFFSET(nasid) + NMI_OFFSET(nasid, slice);
-	int i;
-
-	for (i = 0; i < MAX_REGIONS; i++) {
-		if (i == nasid_to_region(nasid))
-			continue;
-	}
-}
-#endif /* LATER */
-
-
-#ifdef LATER
-/*
- * Protect areas of memory that we access uncached by marking them as
- * poisoned so the T5 can't read them speculatively and erroneously
- * mark them dirty in its cache only to write them back with old data
- * later.
- */
-static void
-protect_low_memory(nasid_t nasid)
-{
-	/* Protect low memory directory */
-	poison_state_alter_range(KLDIR_ADDR(nasid), KLDIR_SIZE, 1);
-
-	/* Protect klconfig area */
-	poison_state_alter_range(KLCONFIG_ADDR(nasid), KLCONFIG_SIZE(nasid), 1);
-
-	/* Protect the PI error spool area. */
-	poison_state_alter_range(PI_ERROR_ADDR(nasid), PI_ERROR_SIZE(nasid), 1);
-
-	/* Protect CPU A's cache error eframe area. */
-	poison_state_alter_range(TO_NODE_UNCAC(nasid, CACHE_ERR_EFRAME),
-				CACHE_ERR_AREA_SIZE, 1);
-
-	/* Protect CPU B's area */
-	poison_state_alter_range(TO_NODE_UNCAC(nasid, CACHE_ERR_EFRAME)
-				^ UALIAS_FLIP_BIT,
-				CACHE_ERR_AREA_SIZE, 1);
-#error "SN1 not handled correctly"
-}
-#endif	/* LATER */
-
-/*
- * per_hub_init
- *
- * 	This code is executed once for each Hub chip.
- */
-void
-per_hub_init(cnodeid_t cnode)
-{
-	uint64_t	done;
-	nasid_t		nasid;
-	nodepda_t	*npdap;
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)	/* SN1 specific */
-	ii_icmr_u_t	ii_icmr;
-	ii_ibcr_u_t	ii_ibcr;
-#endif
-#ifdef	LATER
-	int i;
-#endif
-
-	nasid = COMPACT_TO_NASID_NODEID(cnode);
-
-	ASSERT(nasid != INVALID_NASID);
-	ASSERT(NASID_TO_COMPACT_NODEID(nasid) == cnode);
-
-	/* Grab the hub_mask lock. */
-	spin_lock(&hub_mask_lock);
-
-	/* Test our bit. */
-	if (!(done = CNODEMASK_TSTB(hub_init_mask, cnode))) {
-
-		/* Turn our bit on in the mask. */
-		CNODEMASK_SETB(hub_init_mask, cnode);
-	}
-
-#if defined(SN0_HWDEBUG)
-	hub_config_setup();
-#endif
-	/* Release the hub_mask lock. */
-	spin_unlock(&hub_mask_lock);
-
-	/*
-	 * Do the actual initialization if it hasn't been done yet.
-	 * We don't need to hold a lock for this work.
-	 */
-	if (!done) {
-		npdap = NODEPDA(cnode);
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-		/* initialize per-node synergy perf instrumentation */
-		npdap->synergy_perf_enabled = 0; /* off by default */
-		npdap->synergy_perf_lock = SPIN_LOCK_UNLOCKED;
-		npdap->synergy_perf_freq = SYNERGY_PERF_FREQ_DEFAULT;
-		npdap->synergy_inactive_intervals = 0;
-		npdap->synergy_active_intervals = 0;
-		npdap->synergy_perf_data = NULL;
-		npdap->synergy_perf_first = NULL;
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
-		npdap->hub_chip_rev = get_hub_chiprev(nasid);
-
-#ifdef	LATER
-		for (i = 0; i < CPUS_PER_NODE; i++) {
-			cpu = cnode_slice_to_cpuid(cnode, i);
-			if (!cpu_enabled(cpu))
-			    SET_CPU_LEDS(nasid, i, 0xf);
-		}
-#endif /* LATER */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) /* SN1 specific */
-
-		/*
-		 * Set the total number of CRBs that can be used.
-		 */
-		ii_icmr.ii_icmr_regval= 0x0;
-		ii_icmr.ii_icmr_fld_s.i_c_cnt = 0xF;
-		REMOTE_HUB_S(nasid, IIO_ICMR, ii_icmr.ii_icmr_regval);
-
-		/*
-		 * Set the number of CRBs that both of the BTEs combined
-		 * can use minus 1.
-		 */
-		ii_ibcr.ii_ibcr_regval= 0x0;
-		ii_ibcr.ii_ibcr_fld_s.i_count = 0x8;
-		REMOTE_HUB_S(nasid, IIO_IBCR, ii_ibcr.ii_ibcr_regval);
-
-		/*
-		 * Set CRB timeout to be 10ms.
-		 */
-		REMOTE_HUB_S(nasid, IIO_ICTP, 0x1000 );
-		REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
-
-#endif /* SN0_HWDEBUG */
-
-
-
-		/* Reserve all of the hardwired interrupt levels. */
-		intr_reserve_hardwired(cnode);
-
-		/* Initialize error interrupts for this hub. */
-		hub_error_init(cnode);
-
-#ifdef LATER
-		/* Set up correctable memory/directory ECC error interrupt. */
-		install_eccintr(cnode);
-
-		/* Protect our exception vectors from accidental corruption. */
-		protect_hub_calias(nasid);
-
-		/* Enable RT clock interrupts */
-		hub_rtc_init(cnode);
-		hub_migrintr_init(cnode); /* Enable migration interrupt */
-#endif	/* LATER */
-
-		spin_lock(&hub_mask_lock);
-		CNODEMASK_SETB(hub_init_done_mask, cnode);
-		spin_unlock(&hub_mask_lock);
-
-	} else {
-		/*
-		 * Wait for the other CPU to complete the initialization.
-		 */
-		while (CNODEMASK_TSTB(hub_init_done_mask, cnode) == 0) {
-			/*
-			 * On SNIA64 we should never get here ..
-			 */
-			printk("WARNING: per_hub_init: Should NEVER get here!\n");
-			/* LOOP */
-			;
-		}
-	}
-}
-
-extern void
 update_node_information(cnodeid_t cnodeid)
 {
 	nodepda_t *npda = NODEPDA(cnodeid);
@@ -623,22 +233,3 @@
 		npda_rip = npda_rip->router_next;
 	}
 }
-
-hubreg_t
-get_region(cnodeid_t cnode)
-{
-	if (fine_mode)
-		return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_FINEREG_SHFT;
-	else
-		return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_COARSEREG_SHFT;
-}
-
-hubreg_t
-nasid_to_region(nasid_t nasid)
-{
-	if (fine_mode)
-		return nasid >> NASID_TO_FINEREG_SHFT;
-	else
-		return nasid >> NASID_TO_COARSEREG_SHFT;
-}
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/ml_SN_intr.c linux/arch/ia64/sn/io/ml_SN_intr.c
--- linux.orig/arch/ia64/sn/io/ml_SN_intr.c	2001-07-31 17:30:09.000000000 +0000
+++ linux/arch/ia64/sn/io/ml_SN_intr.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,1728 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Alan Mayer
- */
-
-/*
- * intr.c-
- *	This file contains all of the routines necessary to set up and
- *	handle interrupts on an IP27 board.
- */
-
-#ident  "$Revision: 1.167 $"
-
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <asm/smp.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
-#include <asm/sn/sn_private.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/synergy.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/xtalk/xtalk.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/intr.h>
-
-#if DEBUG_INTR_TSTAMP_DEBUG
-#include <sys/debug.h>
-#include <sys/idbg.h>
-#include <sys/inst.h>
-void do_splx_log(int, int);
-void spldebug_log_event(int);
-#endif
-
-// FIXME - BRINGUP
-#ifdef CONFIG_SMP
-extern unsigned long cpu_online_map;
-#endif
-#define cpu_allows_intr(cpu)	(1)
-// If I understand what's going on with this, 32 should work.
-// physmem_maxradius seems to be the maximum number of router
-// hops to get from one end of the system to the other.  With
-// a maximally configured machine, with the dumbest possible
-// topology, we would make 32 router hops.  For what we're using
-// it for, the dumbest possible should suffice.
-#define physmem_maxradius()	32
-
-#define SUBNODE_ANY -1
-
-extern int	nmied;
-extern int	hub_intr_wakeup_cnt;
-extern synergy_da_t	*Synergy_da_indr[];
-extern cpuid_t         master_procid;
-
-extern cnodeid_t master_node_get(devfs_handle_t vhdl);
-
-extern snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
-
-
-#define INTR_LOCK(vecblk) \
-     (s = mutex_spinlock(&(vecblk)->vector_lock))
-#define INTR_UNLOCK(vecblk) \
-      mutex_spinunlock(&(vecblk)->vector_lock, s)
-
-/*
- * REACT/Pro
- */
-
-
-
-/* 
- * Find first bit set 
- * Used outside this file also 
- */
-int ms1bit(unsigned long x)
-{
-    int			b;
-
-    if (x >> 32)	b  = 32, x >>= 32;
-    else		b  =  0;
-    if (x >> 16)	b += 16, x >>= 16;
-    if (x >>  8)	b +=  8, x >>=  8;
-    if (x >>  4)	b +=  4, x >>=  4;
-    if (x >>  2)	b +=  2, x >>=  2;
-
-    return b + (int) (x >> 1);
-}
-
-/* ARGSUSED */
-void
-intr_stray(void *lvl)
-{
-    PRINT_WARNING("Stray Interrupt - level %ld to cpu %d", (long)lvl, cpuid());
-}
-
-#if defined(DEBUG)
-
-/* Infrastructure  to gather the device - target cpu mapping info */
-#define MAX_DEVICES	1000	/* Reasonable large number . Need not be 
-				 * the exact maximum # devices possible.
-				 */
-#define MAX_NAME	100	
-typedef struct {
-	dev_t		dev;	/* device */
-	cpuid_t		cpuid;	/* target cpu */
-	cnodeid_t	cnodeid;/* node on which the target cpu is present */
-	int		bit;	/* intr bit reserved */
-	char		intr_name[MAX_NAME]; /* name of the interrupt */
-} intr_dev_targ_map_t;
-
-intr_dev_targ_map_t 	intr_dev_targ_map[MAX_DEVICES];
-uint64_t		intr_dev_targ_map_size;
-spinlock_t		intr_dev_targ_map_lock;
-
-/* Print out the device - target cpu mapping.
- * This routine is used only in the idbg command
- * "intrmap" 
- */
-void
-intr_dev_targ_map_print(cnodeid_t cnodeid)
-{
-	int  i,j,size = 0;
-	int  print_flag = 0,verbose = 0;	
-	char node_name[10];
-	
-	if (cnodeid != CNODEID_NONE) {
-		nodepda_t 	*npda;
-
-		npda = NODEPDA(cnodeid);
-		for (j=0; j<NUM_SUBNODES; j++) {
-			qprintf("\n SUBNODE %d\n INT_PEND0: ", j);
-			for(i = 0 ; i < N_INTPEND_BITS ; i++)
-				qprintf("%d",SNPDA(npda,j)->intr_dispatch0.info[i].ii_flags);
-			qprintf("\n INT_PEND1: ");
-			for(i = 0 ; i < N_INTPEND_BITS ; i++)
-				qprintf("%d",SNPDA(npda,j)->intr_dispatch1.info[i].ii_flags);
-		}
-		verbose = 1;
-	}
-	qprintf("\n Device - Target Map [Interrupts: %s Node%s]\n\n",
-		(verbose ? "All" : "Non-hardwired"),
-		(cnodeid == CNODEID_NONE) ? "s: All" : node_name); 
-		
-	qprintf("Device\tCpu\tCnode\tIntr_bit\tIntr_name\n");
-	for (i = 0 ; i < intr_dev_targ_map_size ; i++) {
-
-		print_flag = 0;
-		if (verbose) {
-			if (cnodeid != CNODEID_NONE) {
-				if (cnodeid == intr_dev_targ_map[i].cnodeid)
-					print_flag = 1;
-			} else {
-				print_flag = 1;
-			}
-		} else {
-			if (intr_dev_targ_map[i].dev != 0) {
-				if (cnodeid != CNODEID_NONE) {
-					if (cnodeid == 
-					    intr_dev_targ_map[i].cnodeid)
-						print_flag = 1;
-				} else {
-					print_flag = 1;
-				}
-			}
-		}
-		if (print_flag) {
-			size++;
-			qprintf("%d\t%d\t%d\t%d\t%s\n",
-				intr_dev_targ_map[i].dev,
-				intr_dev_targ_map[i].cpuid,
-				intr_dev_targ_map[i].cnodeid,
-				intr_dev_targ_map[i].bit,
-				intr_dev_targ_map[i].intr_name);
-		}
-
-	}
-	qprintf("\nTotal : %d\n",size);
-}
-#endif /* DEBUG */
-
-/*
- * The spinlocks have already been initialized.  Now initialize the interrupt
- * vectors.  One processor on each hub does the work.
- */
-void
-intr_init_vecblk(nodepda_t *npda, cnodeid_t node, int sn)
-{
-    int			i, ip=0;
-    intr_vecblk_t	*vecblk;
-    subnode_pda_t	*snpda;
-
-
-    snpda = SNPDA(npda,sn);
-    do {
-	if (ip == 0) {
-	    vecblk = &snpda->intr_dispatch0;
-	} else {
-	    vecblk = &snpda->intr_dispatch1;
-	}
-
-	/* Initialize this vector. */
-	for (i = 0; i < N_INTPEND_BITS; i++) {
-		vecblk->vectors[i].iv_func = intr_stray;
-		vecblk->vectors[i].iv_prefunc = NULL;
-		vecblk->vectors[i].iv_arg = (void *)(__psint_t)(ip * N_INTPEND_BITS + i);
-
-		vecblk->info[i].ii_owner_dev = 0;
-		strcpy(vecblk->info[i].ii_name, "Unused");
-		vecblk->info[i].ii_flags = 0;	/* No flags */
-		vecblk->vectors[i].iv_mustruncpu = -1; /* No CPU yet. */
-
-	    }
-
-	mutex_spinlock_init(&vecblk->vector_lock);
-
-	vecblk->vector_count = 0;    
-	for (i = 0; i < CPUS_PER_SUBNODE; i++)
-		vecblk->cpu_count[i] = 0;
-
-	vecblk->vector_state = VECTOR_UNINITED;
-
-    } while (++ip < 2);
-
-}
-
-
-/*
- * do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
- *					devfs_handle_t owner_dev, char *name)
- *	Internal work routine to reserve or unreserve an interrupt level.
- *		cpu is the CPU to which the interrupt will be sent.
- *		bit is the level bit to reserve.  -1 means any level
- *		resflags should include II_ERRORINT if this is an
- *			error interrupt, II_THREADED if the interrupt handler
- *			will be threaded, or 0 otherwise.
- *		reserve should be set to II_RESERVE or II_UNRESERVE
- *			to get or clear a reservation.
- *		owner_dev is the device that "owns" this interrupt, if supplied
- *		name is a human-readable name for this interrupt, if supplied
- *	intr_reserve_level returns the bit reserved or -1 to indicate an error
- */
-static int
-do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
-					devfs_handle_t owner_dev, char *name)
-{
-    intr_vecblk_t	*vecblk;
-    hub_intmasks_t 	*hub_intmasks;
-    unsigned long s;
-    int rv = 0;
-    int ip;
-    synergy_da_t	*sda;
-    int		which_synergy;
-    cnodeid_t	cnode;
-
-    ASSERT(bit < N_INTPEND_BITS * 2);
-
-    cnode = cpuid_to_cnodeid(cpu);
-    which_synergy = cpuid_to_synergy(cpu);
-    sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-    hub_intmasks = &sda->s_intmasks;
-    // hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
-
-    // if (pdaindr[cpu].pda == NULL) return -1;
-    if ((bit < N_INTPEND_BITS) && !(resflags & II_ERRORINT)) {
-	vecblk = hub_intmasks->dispatch0;
-	ip = 0;
-    } else {
-	ASSERT((bit >= N_INTPEND_BITS) || (bit == -1));
-	bit -= N_INTPEND_BITS;	/* Get position relative to INT_PEND1 reg. */
-	vecblk = hub_intmasks->dispatch1;
-	ip = 1;
-    }
-
-    INTR_LOCK(vecblk);
-
-    if (bit <= -1) {
-	bit = 0;
-	ASSERT(reserve == II_RESERVE);
-	/* Choose any available level */
-	for (; bit < N_INTPEND_BITS; bit++) {
-	    if (!(vecblk->info[bit].ii_flags & II_RESERVE)) {
-		rv = bit;
-		break;
-	    }
-	}
-
-	/* Return -1 if all interrupt levels int this register are taken. */
-	if (bit == N_INTPEND_BITS)
-	    rv = -1;
-
-    } else {
-	/* Reserve a particular level if it's available. */
-	if ((vecblk->info[bit].ii_flags & II_RESERVE) == reserve) {
-	    /* Can't (un)reserve a level that's already (un)reserved. */
-	    rv = -1;
-	} else {
-	    rv = bit;
-	}
-    }
-
-    /* Reserve the level and bump the count. */
-    if (rv != -1) {
-	if (reserve) {
-	    int maxlen = sizeof(vecblk->info[bit].ii_name) - 1;
-	    int namelen;
-	    vecblk->info[bit].ii_flags |= (II_RESERVE | resflags);
-	    vecblk->info[bit].ii_owner_dev = owner_dev;
-	    /* Copy in the name. */
-	    namelen = name ? strlen(name) : 0;
-	    strncpy(vecblk->info[bit].ii_name, name, MIN(namelen, maxlen)); 
-	    vecblk->info[bit].ii_name[maxlen] = '\0';
-	    vecblk->vector_count++;
-	} else {
-	    vecblk->info[bit].ii_flags = 0;	/* Clear all the flags */
-	    vecblk->info[bit].ii_owner_dev = 0;
-	    /* Clear the name. */
-	    vecblk->info[bit].ii_name[0] = '\0';
-	    vecblk->vector_count--;
-	}
-    }
-
-    INTR_UNLOCK(vecblk);
-
-#if defined(DEBUG)
-    if (rv >= 0) {
-	    int namelen = name ? strlen(name) : 0;
-	    /* Gather this device - target cpu mapping information
-	     * in a table which can be used later by the idbg "intrmap"
-	     * command
-	     */
-	    s = mutex_spinlock(&intr_dev_targ_map_lock);
-	    if (intr_dev_targ_map_size < MAX_DEVICES) {
-		    intr_dev_targ_map_t	*p;
-
-		    p 		= &intr_dev_targ_map[intr_dev_targ_map_size];
-		    p->dev  	= owner_dev;
-		    p->cpuid 	= cpu; 
-		    p->cnodeid 	= cputocnode(cpu); 
-		    p->bit 	= ip * N_INTPEND_BITS + rv;
-		    strncpy(p->intr_name,
-			    name,
-			    MIN(MAX_NAME,namelen));
-		    intr_dev_targ_map_size++;
-	    }
-	    mutex_spinunlock(&intr_dev_targ_map_lock,s);
-    }
-#endif /* DEBUG */
-
-    return (((rv == -1) ? rv : (ip * N_INTPEND_BITS) + rv)) ;
-}
-
-
-/*
- * WARNING:  This routine should only be called from within ml/SN.
- *	Reserve an interrupt level.
- */
-int
-intr_reserve_level(cpuid_t cpu, int bit, int resflags, devfs_handle_t owner_dev, char *name)
-{
-	return(do_intr_reserve_level(cpu, bit, resflags, II_RESERVE, owner_dev, name));
-}
-
-
-/*
- * WARNING:  This routine should only be called from within ml/SN.
- *	Unreserve an interrupt level.
- */
-void
-intr_unreserve_level(cpuid_t cpu, int bit)
-{
-	(void)do_intr_reserve_level(cpu, bit, 0, II_UNRESERVE, 0, NULL);
-}
-
-/*
- * Get values that vary depending on which CPU and bit we're operating on
- */
-static hub_intmasks_t *
-intr_get_ptrs(cpuid_t cpu, int bit,
-	      int *new_bit,		/* Bit relative to the register */
-	      hubreg_t **intpend_masks, /* Masks for this register */
-	      intr_vecblk_t **vecblk,	/* Vecblock for this interrupt */
-	      int *ip)			/* Which intpend register */
-{
-	hub_intmasks_t *hub_intmasks;
-	synergy_da_t	*sda;
-	int		which_synergy;
-	cnodeid_t	cnode;
-
-	ASSERT(bit < N_INTPEND_BITS * 2);
-
-	cnode = cpuid_to_cnodeid(cpu);
-	which_synergy = cpuid_to_synergy(cpu);
-	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-	hub_intmasks = &sda->s_intmasks;
-
-	// hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
-
-	if (bit < N_INTPEND_BITS) {
-		*intpend_masks = hub_intmasks->intpend0_masks;
-		*vecblk = hub_intmasks->dispatch0;
-		*ip = 0;
-		*new_bit = bit;
-	} else {
-		*intpend_masks = hub_intmasks->intpend1_masks;
-		*vecblk = hub_intmasks->dispatch1;
-		*ip = 1;
-		*new_bit = bit - N_INTPEND_BITS;
-	}
-
-	return hub_intmasks;
-}
-
-
-/*
- * intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
- *		intr_func_t intr_func, void *intr_arg);
- *	This is the lowest-level interface to the interrupt code.  It shouldn't
- *	be called from outside the ml/SN directory.
- *	intr_connect_level hooks up an interrupt to a particular bit in
- *	the INT_PEND0/1 masks.  Returns 0 on success.
- *		cpu is the CPU to which the interrupt will be sent.
- *		bit is the level bit to connect to
- *		intr_swlevel tells which software level to use
- *		intr_func is the interrupt handler
- *		intr_arg is an arbitrary argument interpreted by the handler
- *		intr_prefunc is a prologue function, to be called
- *			with interrupts disabled, to disable
- *			the interrupt at source.  It is called
- *			with the same argument.  Should be NULL for
- *			typical interrupts, which can be masked
- *			by the infrastructure at the level bit.
- *	intr_connect_level returns 0 on success or nonzero on an error
- */
-/* ARGSUSED */
-int
-intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
-		intr_func_t intr_func, void *intr_arg,
-		intr_func_t intr_prefunc)
-{
-    intr_vecblk_t	*vecblk;
-    hubreg_t		*intpend_masks;
-    int rv = 0;
-    int ip;
-    unsigned long s;
-
-    ASSERT(bit < N_INTPEND_BITS * 2);
-
-    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
-				 &vecblk, &ip);
-
-    INTR_LOCK(vecblk);
-
-    if ((vecblk->info[bit].ii_flags & II_INUSE) ||
-	(!(vecblk->info[bit].ii_flags & II_RESERVE))) {
-	/* Can't assign to a level that's in use or isn't reserved. */
-	rv = -1;
-    } else {
-	/* Stuff parameters into vector and info */
-	vecblk->vectors[bit].iv_func = intr_func;
-	vecblk->vectors[bit].iv_prefunc = intr_prefunc;
-	vecblk->vectors[bit].iv_arg = intr_arg;
-	vecblk->info[bit].ii_flags |= II_INUSE;
-    }
-
-    /* Now stuff the masks if everything's okay. */
-    if (!rv) {
-	int lslice;
-	volatile hubreg_t *mask_reg;
-	// nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu));
-	nasid_t nasid = cpuid_to_nasid(cpu);
-	int	subnode = cpuid_to_subnode(cpu);
-
-	/* Make sure it's not already pending when we connect it. */
-	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit + ip * N_INTPEND_BITS);
-
-	intpend_masks[0] |= (1ULL << (uint64_t)bit);
-
-	lslice = cputolocalslice(cpu);
-	vecblk->cpu_count[lslice]++;
-#if SN1
-	/*
-	 * On SN1, there are 8 interrupt mask registers per node:
-	 * 	PI_0 MASK_0 A
-	 * 	PI_0 MASK_1 A
-	 * 	PI_0 MASK_0 B
-	 * 	PI_0 MASK_1 B
-	 * 	PI_1 MASK_0 A
-	 * 	PI_1 MASK_1 A
-	 * 	PI_1 MASK_0 B
-	 * 	PI_1 MASK_1 B
-	 */
-#endif
-	if (ip == 0) {
-		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode, 
-		        PI_INT_MASK0_A + PI_INT_MASK_OFFSET * lslice);
-	} else {
-		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode,
-			PI_INT_MASK1_A + PI_INT_MASK_OFFSET * lslice);
-	}
-
-	HUB_S(mask_reg, intpend_masks[0]);
-    }
-
-    INTR_UNLOCK(vecblk);
-
-    return rv;
-}
-
-
-/*
- * intr_disconnect_level(cpuid_t cpu, int bit)
- *
- *	This is the lowest-level interface to the interrupt code.  It should
- *	not be called from outside the ml/SN directory.
- *	intr_disconnect_level removes a particular bit from an interrupt in
- * 	the INT_PEND0/1 masks.  Returns 0 on success or nonzero on failure.
- */
-int
-intr_disconnect_level(cpuid_t cpu, int bit)
-{
-    intr_vecblk_t	*vecblk;
-    hubreg_t		*intpend_masks;
-    unsigned long s;
-    int rv = 0;
-    int ip;
-
-    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
-				 &vecblk, &ip);
-
-    INTR_LOCK(vecblk);
-
-    if ((vecblk->info[bit].ii_flags & (II_RESERVE | II_INUSE)) !=
-	((II_RESERVE | II_INUSE))) {
-	/* Can't remove a level that's not in use or isn't reserved. */
-	rv = -1;
-    } else {
-	/* Stuff parameters into vector and info */
-	vecblk->vectors[bit].iv_func = (intr_func_t)NULL;
-	vecblk->vectors[bit].iv_prefunc = (intr_func_t)NULL;
-	vecblk->vectors[bit].iv_arg = 0;
-	vecblk->info[bit].ii_flags &= ~II_INUSE;
-#ifdef BASE_ITHRTEAD
-	vecblk->vectors[bit].iv_mustruncpu = -1; /* No mustrun CPU any more. */
-#endif
-    }
-
-    /* Now clear the masks if everything's okay. */
-    if (!rv) {
-	int lslice;
-	volatile hubreg_t *mask_reg;
-
-	intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
-	lslice = cputolocalslice(cpu);
-	vecblk->cpu_count[lslice]--;
-	mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-				   cpuid_to_subnode(cpu),
-				   ip == 0 ? PI_INT_MASK0_A : PI_INT_MASK1_A);
-	mask_reg = (volatile hubreg_t *)((__psunsigned_t)mask_reg +
-					(PI_INT_MASK_OFFSET * lslice));
-	*mask_reg = intpend_masks[0];
-    }
-
-    INTR_UNLOCK(vecblk);
-
-    return rv;
-}
-
-/*
- * Actually block or unblock an interrupt
- */
-void
-do_intr_block_bit(cpuid_t cpu, int bit, int block)
-{
-	intr_vecblk_t *vecblk;
-	int ip;
-	unsigned long s;
-	hubreg_t *intpend_masks;
-	volatile hubreg_t mask_value;
-	volatile hubreg_t *mask_reg;
-
-	intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &vecblk, &ip);
-
-	INTR_LOCK(vecblk);
-
-	if (block)
-		/* Block */
-		intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
-	else
-		/* Unblock */
-		intpend_masks[0] |= (1ULL << (uint64_t)bit);
-
-	if (ip == 0) {
-		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-		        cpuid_to_subnode(cpu), PI_INT_MASK0_A);
-	} else {
-		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-			cpuid_to_subnode(cpu), PI_INT_MASK1_A);
-	}
-
-	HUB_S(mask_reg, intpend_masks[0]);
-
-	/*
-	 * Wait for it to take effect.  (One read should suffice.)
-	 * This is only necessary when blocking an interrupt
-	 */
-	if (block)
-		while ((mask_value = HUB_L(mask_reg)) != intpend_masks[0])
-			;
-
-	INTR_UNLOCK(vecblk);
-}
-
-
-/*
- * Block a particular interrupt (cpu/bit pair).
- */
-/* ARGSUSED */
-void
-intr_block_bit(cpuid_t cpu, int bit)
-{
-	do_intr_block_bit(cpu, bit, 1);
-}
-
-
-/*
- * Unblock a particular interrupt (cpu/bit pair).
- */
-/* ARGSUSED */
-void
-intr_unblock_bit(cpuid_t cpu, int bit)
-{
-	do_intr_block_bit(cpu, bit, 0);
-}
-
-
-/* verifies that the specified CPUID is on the specified SUBNODE (if any) */
-#define cpu_on_subnode(cpuid, which_subnode) \
-	   (((which_subnode) == SUBNODE_ANY) || (cpuid_to_subnode(cpuid) == (which_subnode)))
-
-
-/*
- * Choose one of the CPUs on a specified node or subnode to receive
- * interrupts. Don't pick a cpu which has been specified as a NOINTR cpu.
- *
- * Among all acceptable CPUs, the CPU that has the fewest total number
- * of interrupts targetted towards it is chosen.  Note that we never
- * consider how frequent each of these interrupts might occur, so a rare
- * hardware error interrupt is weighted equally with a disk interrupt.
- */
-static cpuid_t
-do_intr_cpu_choose(cnodeid_t cnode, int which_subnode)
-{
-	cpuid_t 	cpu, best_cpu = CPU_NONE;
-	int		slice, min_count=1000;
-
-	min_count = 1000;
-	for (slice=0; slice < CPUS_PER_NODE; slice++) {
-		intr_vecblk_t 	*vecblk0, *vecblk1;
-		int total_intrs_to_slice;
-		subnode_pda_t *snpda;
-		int local_cpu_num;
-
-		cpu = cnode_slice_to_cpuid(cnode, slice);
-		if (cpu == CPU_NONE)
-			continue;
-
-		/* If this cpu isn't enabled for interrupts, skip it */
-		if (!cpu_enabled(cpu) || !cpu_allows_intr(cpu))
-			continue;
-
-		/* If this isn't the right subnode, skip it */
-		if (!cpu_on_subnode(cpu, which_subnode))
-			continue;
-
-		/* OK, this one's a potential CPU for interrupts */
-		snpda = SUBNODEPDA(cnode,SUBNODE(slice));
-		vecblk0 = &snpda->intr_dispatch0;
-		vecblk1 = &snpda->intr_dispatch1;
-		local_cpu_num = LOCALCPU(slice);
-		total_intrs_to_slice = vecblk0->cpu_count[local_cpu_num] +
-		              vecblk1->cpu_count[local_cpu_num];
-
-		if (min_count > total_intrs_to_slice) {
-			min_count = total_intrs_to_slice;
-			best_cpu = cpu;
-		}
-	}
-	return best_cpu;
-}
-
-/*
- * Choose an appropriate interrupt target CPU on a specified node.
- * If which_subnode is SUBNODE_ANY, then subnode is not considered.
- * Otherwise, the chosen CPU must be on the specified subnode.
- */
-static cpuid_t
-intr_cpu_choose_from_node(cnodeid_t cnode, int which_subnode)
-{
-	return(do_intr_cpu_choose(cnode, which_subnode));
-}
-
-
-#ifdef	LATER
-/*
- * Convert a subnode vertex into a (cnodeid, which_subnode) pair.
- * Return 0 on success, non-zero on failure.
- */
-static int
-subnodevertex_to_subnode(devfs_handle_t vhdl, cnodeid_t *cnodeidp, int *which_subnodep)
-{
-	arbitrary_info_t which_subnode;
-	cnodeid_t cnodeid;
-
-	/* Try to grab subnode information */
-	if (hwgraph_info_get_LBL(vhdl, INFO_LBL_CPUBUS, &which_subnode) != GRAPH_SUCCESS)
-		return(-1);
-
-	/* On which node? */
-	cnodeid = master_node_get(vhdl);
-	if (cnodeid == CNODEID_NONE)
-		return(-1);
-
-	*which_subnodep = (int)which_subnode;
-	*cnodeidp = cnodeid;
-	return(0); /* success */
-}
-
-#endif /* LATER */
-
-/* Make it easy to identify subnode vertices in the hwgraph */
-void
-mark_subnodevertex_as_subnode(devfs_handle_t vhdl, int which_subnode)
-{
-	graph_error_t rv;
-
-	ASSERT(0 <= which_subnode);
-	ASSERT(which_subnode < NUM_SUBNODES);
-
-	rv = hwgraph_info_add_LBL(vhdl, INFO_LBL_CPUBUS, (arbitrary_info_t)which_subnode);
-	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
-
-	rv = hwgraph_info_export_LBL(vhdl, INFO_LBL_CPUBUS, sizeof(arbitrary_info_t));
-	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
-}
-
-
-/*
- * Given a device descriptor, extract interrupt target information and
- * choose an appropriate CPU.  Return CPU_NONE if we can't make sense
- * out of the target information.
- * TBD: Should this be considered platform-independent code?
- */
-
-#ifdef	LATER
-static cpuid_t
-intr_target_from_desc(device_desc_t dev_desc, int favor_subnode)
-{
-	cpuid_t cpuid = CPU_NONE;
-	cnodeid_t cnodeid;
-	int which_subnode;
-	devfs_handle_t intr_target_dev;
-
-	if ((intr_target_dev = device_desc_intr_target_get(dev_desc)) != GRAPH_VERTEX_NONE) {
-		/* 
-		 * A valid device was specified.  If it's a particular
-		 * CPU, then use that CPU as target.  
-		 */
-		cpuid = cpuvertex_to_cpuid(intr_target_dev);
-		if (cpuid != CPU_NONE)
-			goto cpuchosen;
-
-		/* If a subnode vertex was specified, pick a CPU on that subnode. */
-		if (subnodevertex_to_subnode(intr_target_dev, &cnodeid, &which_subnode) == 0) {
-			cpuid = intr_cpu_choose_from_node(cnodeid, which_subnode);
-			goto cpuchosen;
-		}
-
-		/*
-		 * Otherwise, pick a CPU on the node that owns the 
-		 * specified target.  Favor "favor_subnode", if specified.
-		 */
-		cnodeid = master_node_get(intr_target_dev);
-		if (cnodeid != CNODEID_NONE) {
-			cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
-			goto cpuchosen;
-		}
-	}
-
-cpuchosen:
-	return(cpuid);
-}
-#endif	/* LATER */
-
-
-#ifdef	LATER
-/*
- * Check if we had already visited this candidate cnode
- */
-static void *
-intr_cnode_seen(cnodeid_t 	candidate,
-		void 		*arg1,
-		void 		*arg2)
-{
-	int		i;
-	cnodeid_t	*visited_cnodes = (cnodeid_t *)arg1;
-	int		*num_visited_cnodes = (int *)arg2;
-
-	ASSERT(visited_cnodes);
-	ASSERT(*num_visited_cnodes <= numnodes);
-	for(i = 0 ; i < *num_visited_cnodes; i++) {
-		if (candidate == visited_cnodes[i])
-			return(NULL);
-	}
-	return(visited_cnodes);
-}
-
-#endif /* LATER */
-
-
-
-/*
- * intr_bit_reserve_test(cpuid,which_subnode,cnode,req_bit,intr_resflags,
- *		owner_dev,intr_name,*resp_bit)
- *	Either cpuid is not CPU_NONE or cnodeid not CNODE_NONE but
- * 	not both.
- * 1. 	If cpuid is specified, this routine tests if this cpu can be a valid
- * 	interrupt target candidate.
- * 2. 	If cnodeid is specified, this routine tests if there is a cpu on 
- *	this node which can be a valid interrupt target candidate.
- * 3.	If a valid interrupt target cpu candidate is found then an attempt at 
- * 	reserving an interrupt bit on the corresponding cnode is made.
- *
- * If steps 1 & 2 both fail or step 3 fails then we are not able to get a valid
- * interrupt target cpu then routine returns CPU_NONE (failure)
- * Otherwise routine returns cpuid of interrupt target (success)
- */
-static cpuid_t
-intr_bit_reserve_test(cpuid_t 		cpuid,
-		      int		favor_subnode,
-		      cnodeid_t 	cnodeid,
-		      int		req_bit,
-		      int 		intr_resflags,
-		      devfs_handle_t 	owner_dev,
-		      char		*intr_name,
-		      int		*resp_bit)
-{
-
-	ASSERT((cpuid==CPU_NONE) || (cnodeid==CNODEID_NONE));
-
-	if (cnodeid != CNODEID_NONE) {
-		/* Try to choose a interrupt cpu candidate */
-		cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
-	}
-
-	if (cpuid != CPU_NONE) {
-		/* Try to reserve an interrupt bit on the hub 
-		 * corresponding to the canidate cnode. If we
-		 * are successful then we got a cpu which can
-		 * act as an interrupt target for the io device.
-		 * Otherwise we need to continue the search
-		 * further.
-		 */
-		*resp_bit = do_intr_reserve_level(cpuid, 
-						  req_bit,
-						  intr_resflags,
-						  II_RESERVE,
-						  owner_dev, 
-						  intr_name);
-
-		if (*resp_bit >= 0)
-			/* The interrupt target  specified was fine */
-			return(cpuid);
-	}
-	return(CPU_NONE);
-}
-/*
- * intr_heuristic(dev_t dev,device_desc_t dev_desc,
- *		  int req_bit,int intr_resflags,dev_t owner_dev,
- *		  char *intr_name,int *resp_bit)
- *
- * Choose an interrupt destination for an interrupt.
- *	dev is the device for which the interrupt is being set up
- *	dev_desc is a description of hardware and policy that could
- *		help determine where this interrupt should go
- *	req_bit is the interrupt bit requested 
- *		(can be INTRCONNECT_ANY_BIT in which the first available
- * 		 interrupt bit is used)
- *	intr_resflags indicates whether we want to (un)reserve bit
- *	owner_dev is the owner device
- *	intr_name is the readable interrupt name	
- * 	resp_bit indicates whether we succeeded in getting the required
- *		 action  { (un)reservation} done	
- *		 negative value indicates failure
- *
- */
-/* ARGSUSED */
-cpuid_t
-intr_heuristic(devfs_handle_t 		dev,
-	       device_desc_t 	dev_desc,
-	       int		req_bit,
-	       int 		intr_resflags,
-	       devfs_handle_t 		owner_dev,
-	       char		*intr_name,
-	       int		*resp_bit)
-{
-	cpuid_t		cpuid;				/* possible intr targ*/
-	cnodeid_t 	candidate;			/* possible canidate */
-#ifdef LATER
-	cnodeid_t	visited_cnodes[MAX_NASIDS], 	/* nodes seen so far */
-		        center,				/* node we are on */
-		        candidate;			/* possible canidate */
-	int		num_visited_cnodes = 0;		/* # nodes seen */
-
-	int		radius = 1,			/* start looking at the
-							 * current node
-							 */
-		        maxradius = physmem_maxradius();
-	void		*rv;
-#endif /* LATER */
-	int		which_subnode = SUBNODE_ANY;
-
-/* SN1 + pcibr Addressing Limitation */
-	{
-	devfs_handle_t pconn_vhdl;
-	pcibr_soft_t pcibr_soft;
-
-	/*
-	 * This combination of SN1 and Bridge hardware has an odd "limitation".
-	 * Due to the choice of addresses for PI0 and PI1 registers on SN1
-	 * and historical limitations in Bridge, Bridge is unable to
-	 * send interrupts to both PI0 CPUs and PI1 CPUs -- we have
-	 * to choose one set or the other.  That choice is implicitly
-	 * made when Bridge first attaches its error interrupt.  After
-	 * that point, all subsequent interrupts are restricted to the
-	 * same PI number (though it's possible to send interrupts to
-	 * the same PI number on a different node).
-	 *
-	 * Since neither SN1 nor Bridge designers are willing to admit a
-	 * bug, we can't really call this a "workaround".  It's a permanent
-	 * solution for an SN1-specific and Bridge-specific hardware
-	 * limitation that won't ever be lifted.
-	 */
-        if ((hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
-	   ((pcibr_soft = pcibr_soft_get(pconn_vhdl)) != NULL)) {
-		/*
-		 * We "know" that the error interrupt is the first
-		 * interrupt set up by pcibr_attach.  Send all interrupts
-		 * on this bridge to the same subnode number.
-		 */
-		if (pcibr_soft->bsi_err_intr) {
-			which_subnode = cpuid_to_subnode(((hub_intr_t) pcibr_soft->bsi_err_intr)->i_cpuid);
-		}
-	}
-	}
-
-#ifdef	LATER
-	/* 
-	 * If an interrupt target was specified for this
-	 * interrupt allocation, try to use it.
-	 */
-	if (dev_desc) {
-
-		/* Try to see if the interrupt target specified in the
-		 * device descriptor is a legal candidate.
-		 */
-		cpuid = intr_bit_reserve_test(intr_target_from_desc(dev_desc, which_subnode),
-					      which_subnode,
-					      CNODEID_NONE,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-		if (cpuid != CPU_NONE) {
-			if (cpu_on_subnode(cpuid, which_subnode))
-				return(cpuid);	/* got a valid interrupt target */
-
-			printk("Override explicit interrupt targetting: %v (0x%x)\n",
-				owner_dev, owner_dev);
-
-			intr_unreserve_level(cpuid, *resp_bit);
-		}
-
-		/* Fall through on to the next step in the search for
-		 * the interrupt candidate.
-		 */
-
-	}
-#endif  /* LATER */
-	
-	/* Check if we can find a valid interrupt target candidate on
-	 * the master node for the device.
-	 */
-	cpuid = intr_bit_reserve_test(CPU_NONE,
-				      which_subnode,	
-				      master_node_get(dev),
-				      req_bit,
-				      intr_resflags,
-				      owner_dev,
-				      intr_name,
-				      resp_bit);
-
-	if (cpuid != CPU_NONE) {
-		if (cpu_on_subnode(cpuid, which_subnode))
-			return(cpuid);	/* got a valid interrupt target */
-		else
-			intr_unreserve_level(cpuid, *resp_bit);
-	}
-
-	PRINT_WARNING("Cannot target interrupts to closest node(%d): %ld (0x%lx)\n",
-		master_node_get(dev),(long) owner_dev, (unsigned long)owner_dev);
-
-	/* Fall through into the default algorithm
-	 * (exhaustive-search-for-the-nearest-possible-interrupt-target)
-	 * for finding the interrupt target
-	 */
-
-#ifndef BRINGUP
-	// Use of this algorithm is deferred until the supporting
-	// code has been implemented.
-	/* 
-	 * No valid interrupt specification exists.
-	 * Try to find a node which is closest to the current node
-	 * which can process interrupts from a device
-	 */
-
-	center = cpuid_to_cnodeid(smp_processor_id());
-	while (radius <= maxradius) {
-
-		/* Try to find a node at the given radius and which
-		 * we haven't seen already.
-		 */
-		rv = physmem_select_neighbor_node(center,radius,&candidate,
-						  intr_cnode_seen,
-						  (void *)visited_cnodes,
-						  (void *)&num_visited_cnodes);
-		if (!rv) {
-			/* We have seen all the nodes at this particular radius
-			 * Go on to the next radius level.
-			 */
-			radius++;
-			continue;
-		}			      
-		/* We are seeing this candidate  cnode for the first time
-		 */
-		visited_cnodes[num_visited_cnodes++] = candidate;
-
-		cpuid = intr_bit_reserve_test(CPU_NONE,
-					      which_subnode,
-					      candidate,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-		if (cpuid != CPU_NONE) {
-			if (cpu_on_subnode(cpuid, which_subnode))
-				return(cpuid);	/* got a valid interrupt target */
-			else
-				intr_unreserve_level(cpuid, *resp_bit);
-		}
-	}
-#else  /* BRINGUP */
-	{
-	// Do a stupid round-robin assignment of the node.
-		static cnodeid_t last_node = -1;
-
-		if (last_node >= numnodes) last_node = 0;
-		for (candidate = last_node + 1; candidate != last_node; candidate++) {
-			if (candidate == numnodes) candidate = 0;
-			cpuid = intr_bit_reserve_test(CPU_NONE,
-					      which_subnode,
-					      candidate,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-			if (cpuid != CPU_NONE) {
-				if (cpu_on_subnode(cpuid, which_subnode)) {
-					last_node = candidate;
-					return(cpuid);	/* got a valid interrupt target */
-				}
-				else
-					intr_unreserve_level(cpuid, *resp_bit);
-			}
-		}
-		last_node = candidate;
-	}
-#endif
-
-	PRINT_WARNING("Cannot target interrupts to any close node: %ld (0x%lx)\n",
-		(long)owner_dev, (unsigned long)owner_dev);
-
-	/* In the worst case try to allocate interrupt bits on the
-	 * master processor's node. We may get here during error interrupt
-	 * allocation phase when the topology matrix is not yet setup
-	 * and hence cannot do an exhaustive search.
-	 */
-	ASSERT(cpu_allows_intr(master_procid));
-	cpuid = intr_bit_reserve_test(master_procid,
-				      which_subnode,
-				      CNODEID_NONE,
-				      req_bit,
-				      intr_resflags,
-				      owner_dev,
-				      intr_name,
-				      resp_bit);
-
-	if (cpuid != CPU_NONE) {
-		if (cpu_on_subnode(cpuid, which_subnode))
-			return(cpuid);
-		else
-			intr_unreserve_level(cpuid, *resp_bit);
-	}
-
-	PRINT_WARNING("Cannot target interrupts: %ld (0x%lx)\n",
-		(long)owner_dev, (unsigned long)owner_dev);
-
-	return(CPU_NONE);	/* Should never get here */
-}
-
-
-
-
-#ifndef BRINGUP
-/*
- * Should never receive an exception while running on the idle 
- * stack.  It IS possible to handle *interrupts* while on the
- * idle stack, but a non-interrupt *exception* is a problem.
- */
-void
-idle_err(inst_t *epc, uint cause, void *fep, void *sp)
-{
-	eframe_t *ep = (eframe_t *)fep;
-
-    if ((cause & CAUSE_EXCMASK) == EXC_IBE ||
-	(cause & CAUSE_EXCMASK) == EXC_DBE) {
-	(void)dobuserre((eframe_t *)ep, epc, 0);
-    }
-
-    /* XXX - This will have to change to deal with various SN errors. */
-    panic( "exception on IDLE stack "
-	    "ep:0x%x epc:0x%x cause:0x%w32x sp:0x%x badvaddr:0x%x",
-	    ep, epc, cause, sp, getbadvaddr());
-    /* NOTREACHED */
-}
-
-
-/*
- * earlynofault - handle very early global faults - usually just while
- *      sizing memory
- * Returns: 1 if should do nofault
- *          0 if not
- */
-/* ARGSUSED */
-int
-earlynofault(eframe_t *ep, uint code)
-{
-	switch(code) {
-	case EXC_DBE:
-		return(1);
-	default:
-		return(0);
-	}
-}
-
-
-
-/* ARGSUSED */
-static void
-cpuintr(void *arg1, void *arg2)
-{
-#if RTE
-	static int rte_intrdebug = 1;
-#endif
-	/*
-	 * Frame Scheduler
-	 */
-	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_CPUINTR, NULL, NULL,
-			 NULL, NULL);
-
-	/*
-	 * Hardware clears the IO interrupts, but we need to clear software-
-	 * generated interrupts.
-	 */
-	LOCAL_HUB_CLR_INTR(CPU_ACTION_A + cputolocalslice(cpuid()));
-
-#if 0
-	/* XXX - Handle error interrupts. */
-	if (error_intr_reason)
-		error_intr();
-#endif /* 0 */
-
-	/*
-	 * If we're headed for panicspin and it is due to a NMI, save the
-	 * eframe in the NMI area
-	 */
-	if (private.p_va_panicspin && nmied) {
-		caddr_t	nmi_save_area;
-
-		nmi_save_area = (caddr_t) (TO_UNCAC(TO_NODE(
-			cputonasid(cpuid()), IP27_NMI_EFRAME_OFFSET)) + 
-			cputoslice(cpuid()) * IP27_NMI_EFRAME_SIZE);
-		bcopy((caddr_t) arg2, nmi_save_area, sizeof(eframe_t));
-	}
-
-	doacvec();
-#if RTE
-	if (private.p_flags & PDAF_ISOLATED && !rte_intrdebug)
-		goto end_cpuintr;
-#endif
-	doactions();
-#if RTE
-end_cpuintr:
-#endif
-	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_INTREXIT, TSTAMP_EV_CPUINTR, NULL, NULL, NULL);
-}
-
-void
-install_cpuintr(cpuid_t cpu)
-{
-	int		intr_bit = CPU_ACTION_A + cputolocalslice(cpu);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
-				(intr_func_t) cpuintr, NULL, NULL))
-		panic("install_cpuintr: Can't connect interrupt.");
-}
-#endif /* BRINGUP */
-
-#ifdef DEBUG_INTR_TSTAMP
-/* We allocate an array, but only use element number 64.  This guarantees that
- * the entry is in a cacheline by itself.
- */
-#define DINTR_CNTIDX	32
-#define DINTR_TSTAMP1	48
-#define	DINTR_TSTAMP2	64
-volatile long long dintr_tstamp_cnt[128];
-int dintr_debug_output=0;
-extern void idbg_tstamp_debug(void);
-#ifdef SPLDEBUG
-extern void idbg_splx_log(int);
-#endif
-#if DEBUG_INTR_TSTAMP_DEBUG
-int dintr_enter_symmon=1000;	/* 1000 microseconds is 1 millisecond */
-#endif
-
-#ifndef BRINGUP
-/* ARGSUSED */
-static void
-cpulatintr(void *arg)
-{
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(CPU_INTRLAT_A + cputolocalslice(cpuid()));
-
-#if DEBUG_INTR_TSTAMP_DEBUG
-	dintr_tstamp_cnt[DINTR_TSTAMP2] =  GET_LOCAL_RTC;
-	if ((dintr_tstamp_cnt[DINTR_TSTAMP2] - dintr_tstamp_cnt[DINTR_TSTAMP1])
-	    > dintr_enter_symmon) {
-#ifdef SPLDEBUG
-		extern int spldebug_log_off;
-
-		spldebug_log_off = 1;
-#endif /* SPLDEBUG */
-		debug("ring");
-#ifdef SPLDEBUG
-		spldebug_log_off = 0;
-#endif /* SPLDEBUG */
-	}
-#endif
-	dintr_tstamp_cnt[DINTR_CNTIDX]++;
-
-	return;
-}
-
-static int install_cpulat_first=0;
-
-void
-install_cpulatintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = CPU_INTRLAT_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, II_THREADED,
-					   cpuv, "intrlat"))
-		panic( "install_cpulatintr: Can't reserve interrupt.");
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
-				cpulatintr, NULL, NULL))
-		panic( "install_cpulatintr: Can't connect interrupt.");
-
-	if (!install_cpulat_first) {
-		install_cpulat_first++;
-		idbg_addfunc("tstamp_debug", (void (*)())idbg_tstamp_debug);
-#if defined(SPLDEBUG) || defined(SPLDEBUG_CPU_EVENTS)
-		idbg_addfunc("splx_log", (void (*)())idbg_splx_log);
-#endif /* SPLDEBUG || SPLDEBUG_CPU_EVENTS */
-	}
-}
-#endif /* BRINGUP */
-
-#endif /* DEBUG_INTR_TSTAMP */
-
-#ifndef BRINGUP
-/* ARGSUSED */
-static void
-dbgintr(void *arg)
-{
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + DEBUG_INTR_A + cputolocalslice(cpuid()));
-
-	debug("zing");
-	return;
-}
-
-
-void
-install_dbgintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = N_INTPEND_BITS + DEBUG_INTR_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
-		panic("install_dbgintr: Can't reserve interrupt. "
-			" intr_bit %d" ,intr_bit);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
-				dbgintr, NULL, NULL))
-		panic("install_dbgintr: Can't connect interrupt.");
-
-#ifdef DEBUG_INTR_TSTAMP
-	/* Set up my interrupt latency test interrupt */
-	install_cpulatintr(cpu);
-#endif
-}
-
-/* ARGSUSED */
-static void
-tlbintr(void *arg)
-{
-	extern void tlbflush_rand(void);
-
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + TLB_INTR_A + cputolocalslice(cpuid()));
-
-	tlbflush_rand();
-	return;
-}
-
-
-void
-install_tlbintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = N_INTPEND_BITS + TLB_INTR_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
-		panic("install_tlbintr: Can't reserve interrupt. "
-			" intr_bit %d" ,intr_bit);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
-				tlbintr, NULL, NULL))
-		panic("install_tlbintr: Can't connect interrupt.");
-
-}
-
-
-/*
- * Send an interrupt to all nodes.  Don't panic if we get an error.
- * Returns 1 if any exceptions occurred.
- */
-int
-protected_broadcast(hubreg_t intrbit)
-{
-	nodepda_t *npdap = private.p_nodepda;
-	int byte, bit, sn;
-	int error = 0;
-
-	extern int _wbadaddr_val(volatile void *, int, volatile int *);
-
-	/* Send rather than clear an interrupt. */
-	intrbit |= 0x100;
-	
-	for (byte = 0; byte < NASID_MASK_BYTES; byte++) {
-		for (bit = 0; bit < 8; bit++) {
-			if (npdap->nasid_mask[byte] & (1 << bit)) {
-				nasid_t nasid = byte * 8 + bit;
-				for (sn=0; sn<NUM_SUBNODES; sn++) {
-					error += _wbadaddr_val(REMOTE_HUB_PI_ADDR(nasid,
-					      sn, PI_INT_PEND_MOD),
-					      sizeof(hubreg_t),
-					      (volatile int *)&intrbit);
-				}
-			}
-		}
-	}
-
-	return error;
-}
-
-
-/*
- * Poll the interrupt register to see if another cpu has asked us
- * to drop into the debugger (without lowering spl).
- */
-void
-chkdebug(void)
-{
-	if (LOCAL_HUB_L(PI_INT_PEND1) & (1L << (DEBUG_INTR_A + cputolocalslice(cpuid()))))
-		dbgintr((void *)NULL);
-}
-
-
-/*
- * Install special graphics interrupt.
- */
-void
-install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg)
-{
-	int intr_bit = GFX_INTR_A + cputolocalslice(cpu);
-
-	if (intr_connect_level(cpu, intr_bit, swlevel,
-				intr_func, intr_arg, NULL))
-		panic("install_gfxintr: Can't connect interrupt.");
-}
-
-
-/*
- * Install page migration interrupt handler.
- */
-void
-hub_migrintr_init(cnodeid_t cnode)
-{
-	cpuid_t cpu = cnodetocpu(cnode);
-	int intr_bit = INT_PEND0_BASELVL + PG_MIG_INTR;
-
-	if (numnodes == 1){
-		/* 
-		 * No migration with just one node..
-		 */
-		return;
-	}
-	
-	if (cpu != -1) {
-		if (intr_connect_level(cpu, intr_bit, 0,
-			       (intr_func_t) migr_intr_handler, 0, (intr_func_t) migr_intr_prologue_handler))
-			panic( "hub_migrintr_init: Can't connect interrupt.");
-	}
-}
-
-
-/*
- * Cause all CPUs to stop by sending them each a DEBUG interrupt.
- * Parameter is actually a (cpumask_t *).
- */
-void
-debug_stop_all_cpus(void *stoplist)
-{
-	int cpu;
-	ulong level;
-
-	for (cpu=0; cpu<maxcpus; cpu++) {
-		if (cpu == cpuid())
-			continue;
-		if (!cpu_enabled(cpu))
-		        continue;
-		/* "-1" is the old style parameter OR could be the new style
-		 * if no-one is currently stopped.  We only stop the
-		 * requested cpus, the others are already stopped (probably
-		 * at a breakpoint).
-		 */
-
-		if (((cpumask_t *)stoplist != (cpumask_t *)-1LL) &&
-		    (!CPUMASK_TSTB(*(cpumask_t*)stoplist, cpu)))
-			continue;
-
-		/*
-		 * CPU lslice A gets level DEBUG_INTR_A
-		 * CPU lslice B gets level DEBUG_INTR_B
-		 */
-		level = DEBUG_INTR_A + LOCALCPU(get_cpu_slice(cpu));
-		/*
-		 * Convert the compact hub number to the NASID to get the
-		 * correct part of the address space.  Then set the interrupt
-		 * bit associated with the CPU we want to send the interrupt
-		 * to.
-		 */
-		REMOTE_CPU_SEND_INTR(cpu, N_INTPEND_BITS + level);
-
-	}
-}
-
-#endif /* BRINGUP */
-
-struct hardwired_intr_s {
-	signed char level;
-	int flags;
-	char *name;
-} const hardwired_intr[] = {
-	{ INT_PEND0_BASELVL + RESERVED_INTR,	0,	"Reserved" },
-	{ INT_PEND0_BASELVL + GFX_INTR_A,	0, 	"Gfx A" },
-	{ INT_PEND0_BASELVL + GFX_INTR_B,	0, 	"Gfx B" },
-	{ INT_PEND0_BASELVL + PG_MIG_INTR,	II_THREADED, "Migration" },
-	{ INT_PEND0_BASELVL + UART_INTR,	II_THREADED, "Bedrock/L1" },
-	{ INT_PEND0_BASELVL + CC_PEND_A,	0,	"Crosscall A" },
-	{ INT_PEND0_BASELVL + CC_PEND_B,	0,	"Crosscall B" },
-	{ INT_PEND1_BASELVL + CLK_ERR_INTR,	II_ERRORINT, "Clock Error" },
-	{ INT_PEND1_BASELVL + COR_ERR_INTR_A,	II_ERRORINT, "Correctable Error A" },
-	{ INT_PEND1_BASELVL + COR_ERR_INTR_B,	II_ERRORINT, "Correctable Error B" },
-	{ INT_PEND1_BASELVL + MD_COR_ERR_INTR,	II_ERRORINT, "MD Correct. Error" },
-	{ INT_PEND1_BASELVL + NI_ERROR_INTR,	II_ERRORINT, "NI Error" },
-	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_A,	II_ERRORINT, "Remote NI Error"},
-	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_B,	II_ERRORINT, "Remote NI Error"},
-	{ INT_PEND1_BASELVL + MSC_PANIC_INTR,	II_ERRORINT, "MSC Panic" },
-	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_A,	II_ERRORINT, "LLP Pfail WAR" },
-	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_B,	II_ERRORINT, "LLP Pfail WAR" },
-	{ INT_PEND1_BASELVL + NACK_INT_A,	0, "CPU A Nack count == NACK_CMP" },
-	{ INT_PEND1_BASELVL + NACK_INT_B,	0, "CPU B Nack count == NACK_CMP" },
-	{ INT_PEND1_BASELVL + LB_ERROR,		0, "Local Block Error" },
-	{ INT_PEND1_BASELVL + XB_ERROR,		0, "Local XBar Error" },
-	{ -1, 0, (char *)NULL},
-};
-
-/*
- * Reserve all of the hardwired interrupt levels so they're not used as
- * general purpose bits later.
- */
-void
-intr_reserve_hardwired(cnodeid_t cnode)
-{
-	cpuid_t cpu;
-	int level;
-	int i;
-	char subnode_done[NUM_SUBNODES];
-
-	// cpu = cnodetocpu(cnode);
-	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
-		if (cpuid_to_cnodeid(cpu) == cnode) {
-			break;
-		}
-	}
-	if (cpu == smp_num_cpus) cpu = CPU_NONE;
-	if (cpu == CPU_NONE) {
-		printk("Node %d has no CPUs", cnode);
-		return;
-	}
-
-	for (i=0; i<NUM_SUBNODES; i++)
-		subnode_done[i] = 0;
-
-	for (; cpu<smp_num_cpus && cpu_enabled(cpu) && cpuid_to_cnodeid(cpu) == cnode; cpu++) {
-		int which_subnode = cpuid_to_subnode(cpu);
-		if (subnode_done[which_subnode])
-			continue;
-		subnode_done[which_subnode] = 1;
-
-		for (i = 0; hardwired_intr[i].level != -1; i++) {
-			level = hardwired_intr[i].level;
-
-			if (level != intr_reserve_level(cpu, level,
-						hardwired_intr[i].flags,
-						(devfs_handle_t) NULL,
-						hardwired_intr[i].name))
-				panic("intr_reserve_hardwired: Can't reserve level %d.", level);
-		}
-	}
-}
-
-
-/*
- * Check and clear interrupts.
- */
-/*ARGSUSED*/
-static void
-intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level,
-		char *name)
-{
-	volatile hubreg_t bits;
-	int i;
-
-	/* Check pending interrupts */
-	if ((bits = HUB_L(pend)) != 0) {
-		for (i = 0; i < N_INTPEND_BITS; i++) {
-			if (bits & (1 << i)) {
-#ifdef INTRDEBUG
-				PRINT_WARNING("Nasid %d interrupt bit %d set in %s",
-					nasid, i, name);
-#endif
-				LOCAL_HUB_CLR_INTR(base_level + i);
-			}
-		}
-	}
-}
-
-/*
- * Clear out our interrupt registers.
- */
-void
-intr_clear_all(nasid_t nasid)
-{
-	int	sn;
-
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_A, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_B, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_A, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_B, 0);
-	
-		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND0),
-				INT_PEND0_BASELVL, "INT_PEND0");
-		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND1),
-				INT_PEND1_BASELVL, "INT_PEND1");
-	}
-}
-
-/* 
- * Dump information about a particular interrupt vector.
- */
-static void
-dump_vector(intr_info_t *info, intr_vector_t *vector, int bit, hubreg_t ip,
-		hubreg_t ima, hubreg_t imb, void (*pf)(char *, ...))
-{
-	hubreg_t value = 1LL << bit;
-
-	pf("  Bit %02d: %s: func 0x%x arg 0x%x prefunc 0x%x\n",
-		bit, info->ii_name,
-		vector->iv_func, vector->iv_arg, vector->iv_prefunc);
-	pf("   vertex 0x%x %s%s",
-		info->ii_owner_dev,
-		((info->ii_flags) & II_RESERVE) ? "R" : "U",
-		((info->ii_flags) & II_INUSE) ? "C" : "-");
-	pf("%s%s%s%s",
-		ip & value ? "P" : "-",
-		ima & value ? "A" : "-",
-		imb & value ? "B" : "-",
-		((info->ii_flags) & II_ERRORINT) ? "E" : "-");
-	pf("\n");
-}
-
-
-/*
- * Dump information about interrupt vector assignment.
- */
-void
-intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...))
-{
-	nodepda_t *npda;
-	int ip, sn, bit;
-	intr_vecblk_t *dispatch;
-	hubreg_t ipr, ima, imb;
-	nasid_t nasid;
-
-	if ((cnode < 0) || (cnode >= numnodes)) {
-		pf("intr_dumpvec: cnodeid out of range: %d\n", cnode);
-		return ;
-	}
-
-	nasid = COMPACT_TO_NASID_NODEID(cnode);
-
-	if (nasid == INVALID_NASID) {
-		pf("intr_dumpvec: Bad cnodeid: %d\n", cnode);
-		return ;
-	}
-		
-
-	npda = NODEPDA(cnode);
-
-	for (sn = 0; sn < NUM_SUBNODES; sn++) {
-		for (ip = 0; ip < 2; ip++) {
-			dispatch = ip ? &(SNPDA(npda,sn)->intr_dispatch1) : &(SNPDA(npda,sn)->intr_dispatch0);
-			ipr = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_PEND1 : PI_INT_PEND0);
-			ima = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_A : PI_INT_MASK0_A);
-			imb = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_B : PI_INT_MASK0_B);
-	
-			pf("Node %d INT_PEND%d:\n", cnode, ip);
-	
-			if (dispatch->ithreads_enabled)
-				pf(" Ithreads enabled\n");
-			else
-				pf(" Ithreads disabled\n");
-			pf(" vector_count = %d, vector_state = %d\n",
-				dispatch->vector_count,
-				dispatch->vector_state);
-			pf(" CPU A count %d, CPU B count %d\n",
- 		   	dispatch->cpu_count[0],
- 		   	dispatch->cpu_count[1]);
-			pf(" &vector_lock = 0x%x\n",
-				&(dispatch->vector_lock));
-			for (bit = 0; bit < N_INTPEND_BITS; bit++) {
-				if ((dispatch->info[bit].ii_flags & II_RESERVE) ||
-			    	(ipr & (1L << bit))) {
-					dump_vector(&(dispatch->info[bit]),
-					    	&(dispatch->vectors[bit]),
-					    	bit, ipr, ima, imb, pf);
-				}
-			}
-			pf("\n");
-		}
-	}
-}
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/ml_iograph.c linux/arch/ia64/sn/io/ml_iograph.c
--- linux.orig/arch/ia64/sn/io/ml_iograph.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/ml_iograph.c	2002-08-01 06:42:34.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -13,6 +12,9 @@
 #include <linux/slab.h>
 #include <linux/ctype.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
@@ -30,8 +32,6 @@
 #include <asm/sn/xtalk/xtalk_private.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 
-extern int maxnodes;
-
 /* #define IOGRAPH_DEBUG */
 #ifdef IOGRAPH_DEBUG
 #define DBG(x...) printk(x)
@@ -107,10 +107,10 @@
 #ifdef LATER
 	    if (!is_headless_node_vertex(master)) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("volunteer for widgets: vertex %v has no info label",
+		printk(KERN_WARNING  "volunteer for widgets: vertex %v has no info label",
 			xswitch);
 #else
-		PRINT_WARNING("volunteer for widgets: vertex 0x%x has no info label",
+		printk(KERN_WARNING  "volunteer for widgets: vertex 0x%x has no info label",
 			xswitch);
 #endif
 	    }
@@ -155,11 +155,11 @@
 #ifdef LATER
 	    if (!is_headless_node_vertex(hubv)) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("assign_widgets_to_volunteers:vertex %v has "
+		printk(KERN_WARNING  "assign_widgets_to_volunteers:vertex %v has "
 			" no info label",
 			xswitch);
 #else
-		PRINT_WARNING("assign_widgets_to_volunteers:vertex 0x%x has "
+		printk(KERN_WARNING  "assign_widgets_to_volunteers:vertex 0x%x has "
 			" no info label",
 			xswitch);
 #endif
@@ -184,9 +184,6 @@
 	 */
 	for (widgetnum=HUB_WIDGET_ID_MIN; widgetnum <= HUB_WIDGET_ID_MAX; widgetnum++) {
 
-#ifndef BRINGUP
-		int i;
-#endif
 		/*
 		 * Ignore disabled/empty ports.
 		 */
@@ -244,7 +241,7 @@
 	cnodeid_t cnode;
 	nasid_t nasid;
 	lboard_t *board;
-
+	
 	/*
 	 * Init. the board-to-hwgraph link early, so FRU analyzer
 	 * doesn't trip on leftover values if we panic early on.
@@ -267,55 +264,6 @@
 	hubio_init();
 }
 
-#ifdef LATER
-/* There is an identical definition of this in os/scheduler/runq.c */
-#define INIT_COOKIE(cookie) cookie.must_run = 0; cookie.cpu = PDA_RUNANYWHERE
-/*
- * These functions absolutely doesn't belong here.  It's  here, though, 
- * until the scheduler provides a platform-independent version
- * that works the way it should.  The interface will definitely change, 
- * too.  Currently used only in this file and by io/cdl.c in order to
- * bind various I/O threads to a CPU on the proper node.
- */
-cpu_cookie_t
-setnoderun(cnodeid_t cnodeid)
-{
-	int i;
-	cpuid_t cpunum;
-	cpu_cookie_t cookie;
-
-	INIT_COOKIE(cookie);
-	if (cnodeid == CNODEID_NONE)
-		return(cookie);
-
-	/*
-	 * Do a setmustrun to one of the CPUs on the specified
-	 * node.
-	 */
-	if ((cpunum = CNODE_TO_CPU_BASE(cnodeid)) == CPU_NONE) {
-		return(cookie);
-	}
-
-	cpunum += CNODE_NUM_CPUS(cnodeid) - 1;
-
-	for (i = 0; i < CNODE_NUM_CPUS(cnodeid); i++, cpunum--) {
-
-		if (cpu_enabled(cpunum)) {
-			cookie = setmustrun(cpunum);
-			break;
-		}
-	}
-
-	return(cookie);
-}
-
-void
-restorenoderun(cpu_cookie_t cookie)
-{
-	restoremustrun(cookie);
-}
-#endif	/* LATER */
-
 #ifdef LINUX_KERNEL_THREADS
 static struct semaphore io_init_sema;
 #endif
@@ -445,6 +393,7 @@
 	slotid_t		slot;
 	lboard_t		*board = NULL;
 	char			buffer[16];
+	slotid_t get_widget_slotnum(int xbow, int widget);
 	
 	DBG("\nio_xswitch_widget_init: hubv 0x%p, xswitchv 0x%p, widgetnum 0x%x\n", hubv, xswitchv, widgetnum);
 	/*
@@ -507,6 +456,7 @@
 {
 		lboard_t dummy;
 
+
 			if (board) {
 				DBG("io_xswitch_widget_init: Found KLTYPE_IOBRICK Board 0x%p brd_type 0x%x\n", board, board->brd_type);
 			} else {
@@ -517,7 +467,6 @@
 }
 
 			/*
-			 * BRINGUP
 	 		 * Make sure we really want to say xbrick, pbrick,
 			 * etc. rather than XIO, graphics, etc.
 	 		 */
@@ -534,14 +483,10 @@
 				"%cbrick" "/%s/%d",
 				buffer,
 #endif
-#ifdef BRINGUP
 
 				(board->brd_type == KLTYPE_IBRICK) ? 'I' :
 				(board->brd_type == KLTYPE_PBRICK) ? 'P' :
 				(board->brd_type == KLTYPE_XBRICK) ? 'X' : '?',
-#else
-				toupper(MODULE_GET_BTCHAR(NODEPDA(cnode)->module_id)),
-#endif /* BRINGUP */
 				EDGE_LBL_XTALK, widgetnum);
 		} 
 		
@@ -563,11 +508,7 @@
 		 */
 		if (is_master_baseio(nasid,
 				     NODEPDA(cnode)->module_id,
-#ifdef BRINGUP
  				     get_widget_slotnum(0,widgetnum))) {
-#else
-	<<< BOMB! >>> Need a new way to get slot numbers on IP35/IP37
-#endif
 			extern void klhwg_baseio_inventory_add(devfs_handle_t,
 							       cnodeid_t);
 			module 	= NODEPDA(cnode)->module_id;
@@ -582,7 +523,6 @@
 					(lboard_t *)KL_CONFIG_INFO(nasid),
 					module);
 				/*
-			 	 * BRINGUP
 				 * Change iobrick to correct i/o brick
 				 */
 #ifdef SUPPORT_PRINTING_M_FORMAT
@@ -594,11 +534,7 @@
 					NODEPDA(cnode)->module_id,
 					EDGE_LBL_XTALK, widgetnum);
 			} else {
-#ifdef BRINGUP
 				slot = get_widget_slotnum(0, widgetnum);
-#else
-	<<< BOMB! Need a new way to get slot numbers on IP35/IP37
-#endif
 				board = get_board_name(nasid, module, slot,
 								new_name);
 				/*
@@ -729,41 +665,25 @@
 		    GRAPH_SUCCESS)
 			continue;
 
-#if defined (CONFIG_SGI_IP35) || defined (CONFIG_IA64_SGI_SN1) || defined (CONFIG_IA64_GENERIC)
 		board = find_lboard_module((lboard_t *)KL_CONFIG_INFO(nasid),
 				NODEPDA(cnodeid)->module_id);
-#else
-		{
-		slotid_t	slot;
-		slot = get_widget_slotnum(xbow_num, widgetnum);
-		board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid),
-				    NODEPDA(cnodeid)->module_id, slot);
-		}
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
 		if (board == NULL && peer_nasid != INVALID_NASID) {
 			/*
 			 * Try to find the board on our peer
 			 */
-#if defined (CONFIG_SGI_IP35) || defined (CONFIG_IA64_SGI_SN1) || defined (CONFIG_IA64_GENERIC)
 			board = find_lboard_module(
 				(lboard_t *)KL_CONFIG_INFO(peer_nasid),
 				NODEPDA(cnodeid)->module_id);
-
-#else
-			board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(peer_nasid),
-						    NODEPDA(cnodeid)->module_id, slot);
-
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
 		}
 		if (board == NULL) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Could not find PROM info for vertex %v, "
+			printk(KERN_WARNING  "Could not find PROM info for vertex %v, "
 				"FRU analyzer may fail",
 				vhdl);
 #else
-			PRINT_WARNING("Could not find PROM info for vertex 0x%x, "
+			printk(KERN_WARNING  "Could not find PROM info for vertex 0x%p, "
 				"FRU analyzer may fail",
-				vhdl);
+				(void *)vhdl);
 #endif
 			return;
 		}
@@ -918,7 +838,6 @@
 		DBG("io_init_node: Found XBOW widget_partnum= 0x%x\n", widget_partnum);
 		npdap->basew_id = 0;
 
-#if defined(BRINGUP)
 	} else if (widget_partnum == XG_WIDGET_PART_NUM) {
 		/* 
 		 * OK, WTF do we do here if we have an XG direct connected to a HUB/Bedrock???
@@ -926,11 +845,10 @@
 		 */
 		npdap->basew_id = 0;
 		npdap->basew_id = (((*(volatile int32_t *)(NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0) + BRIDGE_WID_CONTROL))) & WIDGET_WIDGET_ID);
-#endif
 	} else { 
 		npdap->basew_id = (((*(volatile int32_t *)(NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0) + BRIDGE_WID_CONTROL))) & WIDGET_WIDGET_ID);
 
-		panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widgt ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, hubv);
+		panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widgt ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv);
 
 		/*NOTREACHED*/
 	}
@@ -1037,7 +955,7 @@
 #define __DEVSTR3 	"/lun/0/disk/partition/"
 #define	__DEVSTR4	"/../ef"
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1)
 /*
  * Currently, we need to allow for 5 IBrick slots with 1 FC each
  * plus an internal 1394.
@@ -1045,6 +963,8 @@
  * ioconfig starts numbering SCSI's at NUM_BASE_IO_SCSI_CTLR.
  */
 #define NUM_BASE_IO_SCSI_CTLR 6
+#else
+#define NUM_BASE_IO_SCSI_CTLR 6
 #endif
 /*
  * This tells ioconfig where it can start numbering scsi controllers.
@@ -1072,7 +992,6 @@
 		for (i=0; i<NUM_BASE_IO_SCSI_CTLR; i++)
 			base_io_scsi_ctlr_vhdl[i] = GRAPH_VERTEX_NONE;
 	}
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
 	{
 	/*
 	 * May want to consider changing the SN0 code, above, to work more like
@@ -1129,14 +1048,10 @@
 
 	hwgraph_vertex_unref(base_ibrick_xbridge_vhdl);
 	}
-#else
-#pragma error Bomb!
-#endif
 }
 
 
 #include <asm/sn/ioerror_handling.h>
-extern devfs_handle_t 	ioc3_console_vhdl_get(void);
 devfs_handle_t		sys_critical_graph_root = GRAPH_VERTEX_NONE;
 
 /* Define the system critical vertices and connect them through
@@ -1251,6 +1166,7 @@
 {
 	char 			name[MAXDEVNAME];
 	devfs_handle_t		console_vhdl, pci_vhdl, enet_vhdl;
+	devfs_handle_t		ioc3_console_vhdl_get(void);
 
 
 	DBG("baseio_ctlr_num_set; FIXME\n");
@@ -1335,7 +1251,7 @@
 		rtn_val = pcibr_alloc_all_rrbs(vhdl, 0, 4,1, 4,0, 0,0, 0,0);
 	}
 	if (rtn_val)
-		PRINT_WARNING("sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
+		printk(KERN_WARNING  "sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
 
 	if ((vendor_list[5] != PCIIO_VENDOR_ID_NONE) && 
 	    (vendor_list[7] != PCIIO_VENDOR_ID_NONE)) {
@@ -1355,7 +1271,7 @@
 		rtn_val = pcibr_alloc_all_rrbs(vhdl, 1, 4,1, 4,0, 0,0, 0,0);
 	}
 	if (rtn_val)
-		PRINT_WARNING("sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
+		printk(KERN_WARNING  "sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
 }
 
 
@@ -1379,7 +1295,7 @@
 #endif
 
 	active = 0;
-	for (cnodeid = 0; cnodeid < maxnodes; cnodeid++) {
+	for (cnodeid = 0; cnodeid < numnodes; cnodeid++) {
 #ifdef LINUX_KERNEL_THREADS
 		char thread_name[16];
 		extern int io_init_pri;
@@ -1428,7 +1344,7 @@
 
 #endif /* LINUX_KERNEL_THREADS */
 
-	for (cnodeid = 0; cnodeid < maxnodes; cnodeid++)
+	for (cnodeid = 0; cnodeid < numnodes; cnodeid++)
 		/*
 	 	 * Update information generated by IO init.
 		 */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/module.c linux/arch/ia64/sn/io/module.c
--- linux.orig/arch/ia64/sn/io/module.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/module.c	2002-08-01 06:42:41.000000000 +0000
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
@@ -25,7 +26,7 @@
 #include <asm/sn/sn_cpuid.h>
 
 
-/* #define LDEBUG	1	*/
+/* #define LDEBUG	1 */
 
 #ifdef LDEBUG
 #define DPRINTF		printk
@@ -173,9 +174,35 @@
     lboard_t	       *board;
     klmod_serial_num_t *comp;
     char * bcopy(const char * src, char * dest, int count);
+    char serial_number[16];
+
+    /*
+     * record brick serial number
+     */
+    board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
+
+    if (! board || KL_CONFIG_DUPLICATE_BOARD(board))
+    {
+#if	LDEBUG
+	printf ("module_probe_snum: no IP35 board found!\n");
+#endif
+	return 0;
+    }
+
+    board_serial_number_get( board, serial_number );
+    if( serial_number[0] != '\0' ) {
+	encode_str_serial( serial_number, m->snum.snum_str );
+	m->snum_valid = 1;
+    }
+#if	LDEBUG
+    else {
+	printf("module_probe_snum: brick serial number is null!\n");
+    }
+    printf("module_probe_snum: brick serial number == %s\n", serial_number);
+#endif /* DEBUG */
 
     board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid),
-			KLTYPE_MIDPLANE8);
+			KLTYPE_IOBRICK_XBOW);
 
     if (! board || KL_CONFIG_DUPLICATE_BOARD(board))
 	return 0;
@@ -196,13 +223,13 @@
 
 	    if (comp->snum.snum_str[0] != '\0') {
 		bcopy(comp->snum.snum_str,
-		      m->snum.snum_str,
+		      m->sys_snum,
 		      MAX_SERIAL_NUM_SIZE);
-		m->snum_valid = 1;
+		m->sys_snum_valid = 1;
 	    }
     }
 
-    if (m->snum_valid)
+    if (m->sys_snum_valid)
 	return 1;
     else {
 	DPRINTF("Invalid serial number for module %d, "
@@ -227,8 +254,7 @@
     for (node = 0; node < numnodes; node++) {
 	nasid = COMPACT_TO_NASID_NODEID(node);
 
-	board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid),
-			    KLTYPE_IP27);
+	board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 	ASSERT(board);
 
 	m = module_add_node(board->brd_module, node);
@@ -241,7 +267,7 @@
 	    nserial);
 
     if (nserial == 0)
-	PRINT_WARNING("io_module_init: No serial number found.\n");
+	printk(KERN_WARNING  "io_module_init: No serial number found.\n");
 }
 
 elsc_t *get_elsc(void)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/pci.c linux/arch/ia64/sn/io/pci.c
--- linux.orig/arch/ia64/sn/io/pci.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/pci.c	2002-08-01 06:42:37.000000000 +0000
@@ -1,12 +1,12 @@
 /* 
  *
+ * SNI64 specific PCI support for SNI IO.
+ *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * SNI64 specific PCI support for SNI IO.
- *
- * Copyright (C) 1997, 1998, 2000 Colin Ngam
+ * Copyright (c) 1997, 1998, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 #include <linux/init.h>
 #include <linux/types.h>
@@ -14,7 +14,8 @@
 #include <linux/pci.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
@@ -227,7 +228,7 @@
  * snia64_pci_find_bios - SNIA64 pci_find_bios() platform specific code.
  */
 void __init
-sn1_pci_find_bios(void)
+sn_pci_find_bios(void)
 {
 	extern struct pci_ops pci_conf;
 	/*
@@ -237,11 +238,7 @@
 
 	sgi_master_io_infr_init();
 
-#ifdef BRINGUP
-	if ( IS_RUNNING_ON_SIMULATOR() )
-		return;
-#endif
-	/* sn1_io_infrastructure_init(); */
+	/* sn_io_infrastructure_init(); */
 	pci_conf = snia64_pci_ops;
 }
 
@@ -251,8 +248,6 @@
         int 		i;
 	unsigned int 	size;
 
-	devfs_handle_t	bridge_vhdl = pci_bus_to_vertex(d->bus->number);
-
         /* IOC3 only decodes 0x20 bytes of the config space, reading
 	 * beyond that is relatively benign but writing beyond that
 	 * (especially the base address registers) will shut down the
@@ -295,4 +290,11 @@
 
 }
 
+#else
+void sn_pci_find_bios(void) {}
+void pci_fixup_ioc3(struct pci_dev *d) {}
+struct list_head pci_root_buses;
+struct list_head pci_root_buses;
+struct list_head pci_devices;
+
 #endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/pci_bus_cvlink.c linux/arch/ia64/sn/io/pci_bus_cvlink.c
--- linux.orig/arch/ia64/sn/io/pci_bus_cvlink.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/pci_bus_cvlink.c	2002-08-01 06:42:35.000000000 +0000
@@ -4,19 +4,21 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
+#include <linux/pci_ids.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <asm/sn/types.h>
 #include <asm/sn/hack.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
@@ -26,20 +28,19 @@
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
-#include <asm/sn/agent.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 #include <asm/sn/klconfig.h>
-#include <asm/sn/io.h>
-
+#include <asm/sn/nodepda.h>
 #include <asm/sn/pci/pciio.h>
-// #include <sys/ql.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>
-extern int bridge_rev_b_data_check_disable;
 #include <asm/sn/pci/pci_bus_cvlink.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern int bridge_rev_b_data_check_disable;
 
-#define MAX_PCI_XWIDGET 256
 devfs_handle_t busnum_to_pcibr_vhdl[MAX_PCI_XWIDGET];
 nasid_t busnum_to_nid[MAX_PCI_XWIDGET];
 void * busnum_to_atedmamaps[MAX_PCI_XWIDGET];
@@ -49,11 +50,13 @@
 static int pci_bus_map_create(devfs_handle_t xtalk);
 devfs_handle_t devfn_to_vertex(unsigned char busnum, unsigned int devfn);
 
-#define SN1_IOPORTS_UNIT 256
+#define SN_IOPORTS_UNIT 256
 #define MAX_IOPORTS 0xffff
-#define MAX_IOPORTS_CHUNKS (MAX_IOPORTS / SN1_IOPORTS_UNIT)
+#define MAX_IOPORTS_CHUNKS (MAX_IOPORTS / SN_IOPORTS_UNIT)
 struct ioports_to_tlbs_s ioports_to_tlbs[MAX_IOPORTS_CHUNKS];
-unsigned long sn1_allocate_ioports(unsigned long pci_address);
+unsigned long sn_allocate_ioports(unsigned long pci_address);
+
+extern void sn_init_irq_desc(void);
 
 
 
@@ -104,7 +107,7 @@
 	int func = 0;
 	char	name[16];
 	devfs_handle_t  pci_bus = NULL;
-	devfs_handle_t	device_vertex = NULL;
+	devfs_handle_t	device_vertex = (devfs_handle_t)NULL;
 
 	/*
 	 * Go get the pci bus vertex.
@@ -112,9 +115,9 @@
 	pci_bus = pci_bus_to_vertex(busnum);
 	if (!pci_bus) {
 		/*
-		 * During probing, the Linux pci code invents non existant
+		 * During probing, the Linux pci code invents non-existent
 		 * bus numbers and pci_dev structures and tries to access
-		 * them to determine existance. Don't crib during probing.
+		 * them to determine existence. Don't crib during probing.
 		 */
 		if (done_probing)
 			printk("devfn_to_vertex: Invalid bus number %d given.\n", busnum);
@@ -129,11 +132,25 @@
 	slot = PCI_SLOT(devfn);
 	func = PCI_FUNC(devfn);
 
-	if (func == 0)
+	/*
+	 * For a NON Multi-function card the name of the device looks like:
+	 * ../pci/1, ../pci/2 ..
+	 */
+	if (func == 0) {
         	sprintf(name, "%d", slot);
-	else
-		sprintf(name, "%d%c", slot, 'a'+func);
-
+		if (hwgraph_traverse(pci_bus, name, &device_vertex) == 
+			GRAPH_SUCCESS) {
+			if (device_vertex) {
+				return(device_vertex);
+			}
+		}
+	}
+			
+	/*
+	 * This maybe a multifunction card.  It's names look like:
+	 * ../pci/1a, ../pci/1b, etc.
+	 */
+	sprintf(name, "%d%c", slot, 'a'+func);
 	if (hwgraph_traverse(pci_bus, name, &device_vertex) != GRAPH_SUCCESS) {
 		if (!device_vertex) {
 			return(NULL);
@@ -144,12 +161,42 @@
 }
 
 /*
+ * For the given device, initialize the addresses for both the Device(x) Flush 
+ * Write Buffer register and the Xbow Flush Register for the port the PCI bus 
+ * is connected.
+ */
+static void
+set_flush_addresses(struct pci_dev *device_dev, 
+	struct sn_device_sysdata *device_sysdata)
+{
+	pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
+	pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info);
+	pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	device_sysdata->dma_buf_sync = (volatile unsigned int *) 
+		&(bridge->b_wr_req_buf[pciio_slot].reg);
+	device_sysdata->xbow_buf_sync = (volatile unsigned int *)
+		XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(get_nasid(), 0), 
+		pcibr_soft->bs_xid);
+#ifdef DEBUG
+
+	printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n", 
+		device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync);
+
+	while((volatile unsigned int )*device_sysdata->dma_buf_sync);
+	while((volatile unsigned int )*device_sysdata->xbow_buf_sync);
+#endif
+
+}
+
+/*
  * Most drivers currently do not properly tell the arch specific pci dma
  * interfaces whether they can handle A64. Here is where we privately
  * keep track of this.
  */
 static void __init
-set_sn1_pci64(struct pci_dev *dev)
+set_sn_pci64(struct pci_dev *dev)
 {
 	unsigned short vendor = dev->vendor;
 	unsigned short device = dev->device;
@@ -172,7 +219,7 @@
 }
 
 /*
- * sn1_allocate_ioports() - This routine provides the allocation and 
+ * sn_allocate_ioports() - This routine provides the allocation and 
  *	mappings between Linux style IOPORTs management.
  *
  *	For simplicity sake, SN1 will allocate IOPORTs in chunks of 
@@ -189,9 +236,9 @@
  *	Address.  This address via the tlb entries generates the PCI Address 
  *	allocated by the SN1 IO Infrastructure Layer.
  */
-static unsigned long sn1_ioport_num = 0x100; /* Reserve room for Legacy stuff */
+static unsigned long sn_ioport_num = 0x1000; /* Reserve room for Legacy stuff */
 unsigned long
-sn1_allocate_ioports(unsigned long pci_address)
+sn_allocate_ioports(unsigned long pci_address)
 {
 	
 	unsigned long ioport_index;
@@ -199,8 +246,8 @@
 	/*
 	 * Just some idiot checking ..
 	 */
-	if ( sn1_ioport_num > 0xffff ) {
-		printk("sn1_allocate_ioports: No more IO PORTS available\n");
+	if ( sn_ioport_num > 0xffff ) {
+		printk("sn_allocate_ioports: No more IO PORTS available\n");
 		return(-1);
 	}
 
@@ -208,51 +255,64 @@
 	 * See Section 4.1.1.5 of Intel IA-64 Acrchitecture Software Developer's
 	 * Manual for details.
 	 */
-	ioport_index = sn1_ioport_num / SN1_IOPORTS_UNIT;
-	ioports_to_tlbs[ioport_index].ppn = pci_address;
+	ioport_index = sn_ioport_num / SN_IOPORTS_UNIT;
+
 	ioports_to_tlbs[ioport_index].p = 1; /* Present Bit */
-	ioports_to_tlbs[ioport_index].ma = 5; /* Memory Attributes */
-	ioports_to_tlbs[ioport_index].a = 0; /* Set Data Access Bit Fault */
-	ioports_to_tlbs[ioport_index].d = 0; /* Dirty Bit */
-	ioports_to_tlbs[ioport_index].pl = 3;/* Privilege Level - All levels can R/W*/
-	ioports_to_tlbs[ioport_index].ar = 2; /* Access Rights - R/W only*/
+	ioports_to_tlbs[ioport_index].rv_1 = 0; /* 1 Bit */
+	ioports_to_tlbs[ioport_index].ma = 4; /* Memory Attributes 3 bits*/
+	ioports_to_tlbs[ioport_index].a = 1; /* Set Data Access Bit Fault 1 Bit*/
+	ioports_to_tlbs[ioport_index].d = 1; /* Dirty Bit */
+	ioports_to_tlbs[ioport_index].pl = 0;/* Privilege Level - All levels can R/W*/
+	ioports_to_tlbs[ioport_index].ar = 3; /* Access Rights - R/W only*/
+	ioports_to_tlbs[ioport_index].ppn = pci_address >> 12; /* 4K page size */
 	ioports_to_tlbs[ioport_index].ed = 0; /* Exception Deferral Bit */
 	ioports_to_tlbs[ioport_index].ig = 0; /* Ignored */
 
-	printk("sn1_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index].ppn);
+	/* printk("sn_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index]); */
 	
-	sn1_ioport_num += SN1_IOPORTS_UNIT;
+	sn_ioport_num += SN_IOPORTS_UNIT;
 
-	return(sn1_ioport_num - SN1_IOPORTS_UNIT);
+	return(sn_ioport_num - SN_IOPORTS_UNIT);
 }
 
 /*
- * sn1_pci_fixup() - This routine is called when platform_pci_fixup() is 
+ * sn_pci_fixup() - This routine is called when platform_pci_fixup() is 
  *	invoked at the end of pcibios_init() to link the Linux pci 
  *	infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c
  *
  *	Other platform specific fixup can also be done here.
  */
 void
-sn1_pci_fixup(int arg)
+sn_pci_fixup(int arg)
 {
 	struct list_head *ln;
 	struct pci_bus *pci_bus = NULL;
 	struct pci_dev *device_dev = NULL;
-	struct sn1_widget_sysdata *widget_sysdata;
-	struct sn1_device_sysdata *device_sysdata;
+	struct sn_widget_sysdata *widget_sysdata;
+	struct sn_device_sysdata *device_sysdata;
+#ifdef SN_IOPORTS
 	unsigned long ioport;
+#endif
 	pciio_intr_t intr_handle;
 	int cpuid, bit;
-	devfs_handle_t *device_vertex;
+	devfs_handle_t device_vertex;
 	pciio_intr_line_t lines;
-	extern void sn1_pci_find_bios(void);
-
+	extern void sn_pci_find_bios(void);
+#ifdef CONFIG_IA64_SGI_SN2
+	extern int numnodes;
+	int cnode;
+#endif /* CONFIG_IA64_SGI_SN2 */
 
-unsigned long   res;
 
 	if (arg == 0) {
-		sn1_pci_find_bios();
+		sn_init_irq_desc();
+		sn_pci_find_bios();
+#ifdef CONFIG_IA64_SGI_SN2
+		for (cnode = 0; cnode < numnodes; cnode++) {
+				extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
+				intr_init_vecblk(NODEPDA(cnode), cnode, 0);
+		} 
+#endif /* CONFIG_IA64_SGI_SN2 */
 		return;
 	}
 
@@ -274,19 +334,12 @@
 #endif
 	done_probing = 1;
 
-	if ( IS_RUNNING_ON_SIMULATOR() ) {
-		printk("sn1_pci_fixup not supported on simulator.\n");
-		return;
-	}
-
-#ifdef REAL_HARDWARE
-
 	/*
 	 * Initialize the pci bus vertex in the pci_bus struct.
 	 */
 	for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
 		pci_bus = pci_bus_b(ln);
-		widget_sysdata = kmalloc(sizeof(struct sn1_widget_sysdata), 
+		widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata), 
 					GFP_KERNEL);
 		widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number);
 		pci_bus->sysdata = (void *)widget_sysdata;
@@ -296,8 +349,35 @@
  	 * set the root start and end so that drivers calling check_region()
 	 * won't see a conflict
 	 */
-	ioport_resource.start |= IO_SWIZ_BASE;
-	ioport_resource.end |= (HSPEC_SWIZ_BASE-1);
+#ifdef SN_IOPORTS
+	ioport_resource.start  = sn_ioport_num;
+	ioport_resource.end = 0xffff;
+#else
+#if defined(CONFIG_IA64_SGI_SN1)
+	if ( IS_RUNNING_ON_SIMULATOR() ) {
+		/*
+		 * IDE legacy IO PORTs are supported in Medusa.
+		 * Just open up IO PORTs from 0 .. ioport_resource.end.
+		 */
+		ioport_resource.start = 0;
+	} else {
+		/*
+		 * We do not support Legacy IO PORT numbers.
+		 */
+		ioport_resource.start |= IO_SWIZ_BASE | __IA64_UNCACHED_OFFSET;
+	}
+	ioport_resource.end |= (HSPEC_SWIZ_BASE-1) | __IA64_UNCACHED_OFFSET;
+#else
+	// Need something here for sn2.... ZXZXZX
+#endif
+#endif
+
+	/*
+	 * Set the root start and end for Mem Resource.
+	 */
+	iomem_resource.start = 0;
+	iomem_resource.end = 0xffffffffffffffff;
+
 	/*
 	 * Initialize the device vertex in the pci_dev struct.
 	 */
@@ -307,6 +387,7 @@
 		u16 cmd;
 		devfs_handle_t vhdl;
 		unsigned long size;
+		extern int bit_pos_to_irq(int);
 
 		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 				device_dev->device == PCI_DEVICE_ID_SGI_IOC3) {
@@ -316,12 +397,18 @@
 
 		/* Set the device vertex */
 
-		device_sysdata = kmalloc(sizeof(struct sn1_device_sysdata),
+		device_sysdata = kmalloc(sizeof(struct sn_device_sysdata),
 					GFP_KERNEL);
 		device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
 		device_sysdata->isa64 = 0;
+		/*
+		 * Set the xbridge Device(X) Write Buffer Flush and Xbow Flush 
+		 * register addresses.
+		 */
+		(void) set_flush_addresses(device_dev, device_sysdata);
+
 		device_dev->sysdata = (void *) device_sysdata;
-		set_sn1_pci64(device_dev);
+		set_sn_pci64(device_dev);
 		pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
 
 		/*
@@ -336,11 +423,8 @@
 			size = device_dev->resource[idx].end -
 				device_dev->resource[idx].start;
 			if (size) {
-				res = 0;
-				res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
 				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM);
-
-/* printk("sn1_pci_fixup: Mapped Address = 0x%p size = 0x%x\n", device_dev->resource[idx].start, size); */
+				device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
 			}
 			else
 				continue;
@@ -348,6 +432,7 @@
 			device_dev->resource[idx].end = 
 				device_dev->resource[idx].start + size;
 
+#ifdef CONFIG_IA64_SGI_SN1
 			/*
 			 * Adjust the addresses to go to the SWIZZLE ..
 			 */
@@ -355,15 +440,25 @@
 				device_dev->resource[idx].start & 0xfffff7ffffffffff;
 			device_dev->resource[idx].end = 
 				device_dev->resource[idx].end & 0xfffff7ffffffffff;
-			res = 0;
-			res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
+#endif
+
 			if (device_dev->resource[idx].flags & IORESOURCE_IO) {
 				cmd |= PCI_COMMAND_IO;
-				ioport = sn1_allocate_ioports(device_dev->resource[idx].start);
-				/* device_dev->resource[idx].start = ioport; */
-				/* device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT */
+#ifdef SN_IOPORTS
+				ioport = sn_allocate_ioports(device_dev->resource[idx].start);
+				if (ioport < 0) {
+					printk("sn_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number);
+					continue;
+				}
+				pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff)));
+
+printk("sn_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff)));
+
+				device_dev->resource[idx].start = ioport;
+				device_dev->resource[idx].end = ioport + SN_IOPORTS_UNIT;
+#endif
 			}
-			else if (device_dev->resource[idx].flags & IORESOURCE_MEM)
+			if (device_dev->resource[idx].flags & IORESOURCE_MEM)
 				cmd |= PCI_COMMAND_MEMORY;
 		}
 		/*
@@ -371,17 +466,24 @@
 		 */
 		size = device_dev->resource[PCI_ROM_RESOURCE].end -
 			device_dev->resource[PCI_ROM_RESOURCE].start;
-		device_dev->resource[PCI_ROM_RESOURCE].start =
+
+		if (size) {
+			device_dev->resource[PCI_ROM_RESOURCE].start =
 			(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0, 
 				size, 0, PCIIO_BYTE_STREAM);
-		device_dev->resource[PCI_ROM_RESOURCE].end =
+			device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET;
+			device_dev->resource[PCI_ROM_RESOURCE].end =
 			device_dev->resource[PCI_ROM_RESOURCE].start + size;
 
-                /*
-                 * go through synergy swizzled space
-                 */
-		device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
-		device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
+#ifdef CONFIG_IA64_SGI_SN1
+                	/*
+                 	 * go through synergy swizzled space
+                 	 */
+			device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
+			device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
+#endif
+
+		}
 
 		/*
 		 * Update the Command Word on the Card.
@@ -390,29 +492,46 @@
 					   /* bit gets dropped .. no harm */
 		pci_write_config_word(device_dev, PCI_COMMAND, cmd);
 
-		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, &lines);
-#ifdef BRINGUP
+		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
 		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 			device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
 				lines = 1;
 		}
-
-#endif
  
-		device_sysdata = (struct sn1_device_sysdata *)device_dev->sysdata;
+		device_sysdata = (struct sn_device_sysdata *)device_dev->sysdata;
 		device_vertex = device_sysdata->vhdl;
  
 		intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex);
 
 		bit = intr_handle->pi_irq;
 		cpuid = intr_handle->pi_cpu;
+#ifdef CONFIG_IA64_SGI_SN1
 		irq = bit_pos_to_irq(bit);
+#else /* SN2 */
+		irq = bit;
+#endif
 		irq = irq + (cpuid << 8);
-		pciio_intr_connect(intr_handle, NULL, NULL, NULL);
+		pciio_intr_connect(intr_handle);
 		device_dev->irq = irq;
+#ifdef ajmtestintr
+		{
+			int slot = PCI_SLOT(device_dev->devfn);
+			static int timer_set = 0;
+			pcibr_intr_t	pcibr_intr = (pcibr_intr_t)intr_handle;
+			pcibr_soft_t	pcibr_soft = pcibr_intr->bi_soft;
+			extern void intr_test_handle_intr(int, void*, struct pt_regs *);
+
+			if (!timer_set) {
+				intr_test_set_timer();
+				timer_set = 1;
+			}
+			intr_test_register_irq(irq, pcibr_soft, slot);
+			request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
+		}
+#endif
 
 	}
-#endif	/* REAL_HARDWARE */
+
 #if 0
 
 {
@@ -430,6 +549,10 @@
         printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
         printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
 }
+
+printk("testing Big Window: 0xC0000200c0000000 %p\n", *( (volatile uint64_t *)0xc0000200a0000000));
+printk("testing Big Window: 0xC0000200c0000008 %p\n", *( (volatile uint64_t *)0xc0000200a0000008));
+
 #endif
 
 }
@@ -472,12 +595,14 @@
 	 * Loop throught this vertex and get the Xwidgets ..
 	 */
 	for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) {
+#if 0
         {
                 int pos;
                 char dname[256];
                 pos = devfs_generate_path(xtalk, dname, 256);
                 printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
         }
+#endif
 
 		sprintf(pathname, "%d", widgetnum);
 		xwidget = NULL;
@@ -512,12 +637,12 @@
 		 */
 		master_node_vertex = device_master_get(xwidget);
 		if (!master_node_vertex) {
-			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", xwidget);
+			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", (void *)xwidget);
 		}
 	
 		hubinfo_get(master_node_vertex, &hubinfo);
 		if (!hubinfo) {
-			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", master_node_vertex);
+			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", (void *)master_node_vertex);
 			return(1);
 		} else {
 			busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;
@@ -527,12 +652,12 @@
 		 * Pre assign DMA maps needed for 32 Bits Page Map DMA.
 		 */
 		busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc(
-			sizeof(struct sn1_dma_maps_s) * 512, GFP_KERNEL);
+			sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL);
 		if (!busnum_to_atedmamaps[num_bridges - 1])
-			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, xwidget);
+			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, (void *)xwidget);
 
 		memset(busnum_to_atedmamaps[num_bridges - 1], 0x0, 
-			sizeof(struct sn1_dma_maps_s) * 512);
+			sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS);
 
 	}
 
@@ -552,14 +677,10 @@
 {
 
 	devfs_handle_t devfs_hdl = NULL;
-	devfs_handle_t module_comp = NULL;
-	devfs_handle_t node = NULL;
 	devfs_handle_t xtalk = NULL;
-	graph_vertex_place_t placeptr = EDGE_PLACE_WANT_REAL_EDGES;
 	int rv = 0;
 	char name[256];
 	int master_iobrick;
-	moduleid_t iobrick_id;
 	int i;
 
 	/*
@@ -620,65 +741,3 @@
 
 	return(0);
 }
-
-/*
- * sgi_pci_intr_support -
- */
-int
-sgi_pci_intr_support (unsigned int requested_irq, device_desc_t *dev_desc,
-	devfs_handle_t *bus_vertex, pciio_intr_line_t *lines,
-	devfs_handle_t *device_vertex)
-
-{
-
-	unsigned int bus;
-	unsigned int devfn;
-	struct pci_dev *pci_dev;
-	unsigned char intr_pin = 0;
-	struct sn1_widget_sysdata *widget_sysdata;
-	struct sn1_device_sysdata *device_sysdata;
-
-	if (!dev_desc || !bus_vertex || !device_vertex) {
-		printk("WARNING: sgi_pci_intr_support: Invalid parameter dev_desc 0x%p, bus_vertex 0x%p, device_vertex 0x%p\n", dev_desc, bus_vertex, device_vertex);
-		return(-1);
-	}
-
-	devfn = (requested_irq >> 8) & 0xff;
-	bus = (requested_irq >> 16) & 0xffff;
-	pci_dev = pci_find_slot(bus, devfn);
-	widget_sysdata = (struct sn1_widget_sysdata *)pci_dev->bus->sysdata;
-	*bus_vertex = widget_sysdata->vhdl;
-	device_sysdata = (struct sn1_device_sysdata *)pci_dev->sysdata;
-	*device_vertex = device_sysdata->vhdl;
-#if 0
-	{
-		int pos;
-		char dname[256];
-		pos = devfs_generate_path(*device_vertex, dname, 256);
-		printk("%s : path= %s pos %d\n", __FUNCTION__, &dname[pos], pos);
-	}
-#endif /* BRINGUP */
-
-
-	/*
-	 * Get the Interrupt PIN.
-	 */
-	pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intr_pin);
-	*lines = (pciio_intr_line_t)intr_pin;
-
-#ifdef BRINGUP
-	/*
-	 * ioc3 can't decode the PCI_INTERRUPT_PIN field of its config
-	 * space so we have to set it here
-	 */
-	if (pci_dev->vendor == PCI_VENDOR_ID_SGI &&
-	    pci_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
-		*lines = 1;
-	}
-#endif /* BRINGUP */
-
-	/* Not supported currently */
-	*dev_desc = NULL;
-	return(0);
-
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/pci_dma.c linux/arch/ia64/sn/io/pci_dma.c
--- linux.orig/arch/ia64/sn/io/pci_dma.c	2001-10-12 22:35:53.000000000 +0000
+++ linux/arch/ia64/sn/io/pci_dma.c	2002-08-01 06:42:37.000000000 +0000
@@ -3,11 +3,9 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Leo Dagum
+ * Copyright (C) 2000,2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/mm.h>
 #include <linux/string.h>
@@ -15,37 +13,23 @@
 #include <linux/slab.h>
 #include <linux/devfs_fs_kernel.h>
 
-#ifndef LANGUAGE_C 
-#define LANGUAGE_C 99
-#endif
-#ifndef _LANGUAGE_C
-#define _LANGUAGE_C 99
-#endif
-
+#include <asm/delay.h>
 #include <asm/io.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/types.h>
 #include <asm/sn/alenlist.h>
 #include <asm/sn/pci/pci_bus_cvlink.h>
-
-/*
- * this is REALLY ugly, blame it on gcc's lame inlining that we
- * have to put procedures in header files
- */
-#if LANGUAGE_C == 99
-#undef LANGUAGE_C
-#endif
-#if CONFIG_IA64_SGI_IO == 99
-#undef CONFIG_IA64_SGI_IO
-#endif
+#include <asm/sn/nag.h>
 
 pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
-struct sn1_dma_maps_s *find_sn1_dma_map(dma_addr_t, unsigned char);
+void free_pciio_dmamap(pcibr_dmamap_t);
+struct sn_dma_maps_s *find_sn_dma_map(dma_addr_t, unsigned char);
 extern devfs_handle_t busnum_to_pcibr_vhdl[];
 extern nasid_t busnum_to_nid[];
 extern void * busnum_to_atedmamaps[];
@@ -57,48 +41,92 @@
 get_free_pciio_dmamap(devfs_handle_t pci_bus)
 {
 	int i;
-	struct sn1_dma_maps_s *sn1_dma_map = NULL;
+	struct sn_dma_maps_s *sn_dma_map = NULL;
 
 	/*
 	 * Darn, we need to get the maps allocated for this bus.
 	 */
-	for (i=0; i<512; i++) {
+	for (i=0; i<MAX_PCI_XWIDGET; i++) {
 		if (busnum_to_pcibr_vhdl[i] == pci_bus) {
-			sn1_dma_map = busnum_to_atedmamaps[i];
+			sn_dma_map = busnum_to_atedmamaps[i];
 		}
 	}
 
 	/*
 	 * Now get a free dmamap entry from this list.
 	 */
-	for (i=0; i<512; i++, sn1_dma_map++) {
-		if (!sn1_dma_map->dma_addr) {
-			sn1_dma_map->dma_addr = -1;
-			return( (pciio_dmamap_t) sn1_dma_map );
+	for (i=0; i<MAX_ATE_MAPS; i++, sn_dma_map++) {
+		if (!sn_dma_map->dma_addr) {
+			sn_dma_map->dma_addr = -1;
+			return( (pciio_dmamap_t) sn_dma_map );
 		}
 	}
 
-printk("get_pciio_dmamap: Unable to find a free dmamap\n");
 	return(NULL);
 
 }
 
-struct sn1_dma_maps_s *
-find_sn1_dma_map(dma_addr_t dma_addr, unsigned char busnum)
+/*
+ * Free pciio_dmamap_t entry.
+ */
+void
+free_pciio_dmamap(pcibr_dmamap_t dma_map)
+{
+	struct sn_dma_maps_s *sn_dma_map;
+
+	sn_dma_map = (struct sn_dma_maps_s *) dma_map;
+	sn_dma_map->dma_addr = 0;
+
+}
+
+/*
+ * sn_dma_sync: This routine flushes all DMA buffers for the device into the II.
+ *	This does not mean that the data is in the "Coherence Domain".  But it 
+ *	is very close.
+ */
+void
+sn_dma_sync( struct pci_dev *hwdev )
+{
+
+	struct sn_device_sysdata *device_sysdata;
+	volatile unsigned long dummy;
+
+	/*
+	 * It is expected that on IA64 platform, a DMA sync ensures that all 
+	 * the DMA (dma_handle) are complete and coherent.
+	 *	1. Flush Write Buffers from Bridge.
+	 *	2. Flush Xbow Port.
+	 */
+	device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
+	dummy = (volatile unsigned long ) *device_sysdata->dma_buf_sync;
+
+	/*
+	 * For the Xbow Port flush, we maybe denied the request because 
+	 * someone else may be flushing the Port .. try again.
+	 */
+	while((volatile unsigned long ) *device_sysdata->xbow_buf_sync) {
+		udelay(2);
+	}
+}
+
+
+struct sn_dma_maps_s *
+find_sn_dma_map(dma_addr_t dma_addr, unsigned char busnum)
 {
 
-	struct sn1_dma_maps_s *sn1_dma_map = NULL;
+	struct sn_dma_maps_s *sn_dma_map = NULL;
 	int i;
 
-	sn1_dma_map = busnum_to_atedmamaps[busnum];
+	sn_dma_map = busnum_to_atedmamaps[busnum];
 
-	for (i=0; i<512; i++, sn1_dma_map++) {
-		if (sn1_dma_map->dma_addr == dma_addr) {
-			return( sn1_dma_map );
+	for (i=0; i<MAX_ATE_MAPS; i++, sn_dma_map++) {
+		if (sn_dma_map->dma_addr == dma_addr) {
+			return( sn_dma_map );
 		}
 	}
 
 printk("find_pciio_dmamap: Unable find the corresponding dma map\n");
+
 	return(NULL);
 
 }
@@ -111,12 +139,12 @@
  * write gathering turned on, hence the PCIIO_DMA_CMD flag
  */
 void *
-sn1_pci_alloc_consistent (struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
+sn_pci_alloc_consistent (struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
 {
         void *ret;
         int gfp = GFP_ATOMIC;
 	devfs_handle_t    vhdl;
-	struct sn1_device_sysdata *device_sysdata;
+	struct sn_device_sysdata *device_sysdata;
 	paddr_t temp_ptr;
 
 	*dma_handle = (dma_addr_t) NULL;
@@ -124,7 +152,7 @@
 	/*
 	 * get vertex for the device
 	 */
-	device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata;
+	device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
 	vhdl = device_sysdata->vhdl;
 
         if ( (ret = (void *)__get_free_pages(gfp, get_order(size))) ) {
@@ -139,9 +167,15 @@
 		/*
 		 * This device supports 64bits DMA addresses.
 		 */
+#ifdef CONFIG_IA64_SGI_SN1
 		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
 			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD
 			| PCIIO_DMA_A64 );
+#else /* SN2 */
+		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
+			PCIBR_BARRIER | PCIIO_DMA_CMD | PCIIO_DMA_A64 );
+#endif
+
 		return (ret);
 	}
 
@@ -152,15 +186,21 @@
 	 * First try to get 32 Bit Direct Map Support.
 	 */
 	if (IS_PCI32G(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
 			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
+#else /* SN2 */
+		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
+			PCIBR_BARRIER | PCIIO_DMA_CMD);
+#endif
+
 		if (dma_handle) {
 			return (ret);
 		} else {
 			/*
 			 * We need to map this request by using ATEs.
 			 */
-			printk("sn1_pci_alloc_consistent: 32Bits DMA Page Map support not available yet!");
+			printk("sn_pci_alloc_consistent: 32Bits DMA Page Map support not available yet!");
 			BUG();
 		}
 	}
@@ -176,17 +216,17 @@
 }
 
 void
-sn1_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
+sn_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
 {
 	free_pages((unsigned long) vaddr, get_order(size));
 }
 
 /*
- * On sn1 we use the orig_address entry of the scatterlist to store
+ * On sn1 we use the page entry of the scatterlist to store
  * the physical address corresponding to the given virtual address
  */
 int
-sn1_pci_map_sg (struct pci_dev *hwdev,
+sn_pci_map_sg (struct pci_dev *hwdev,
                         struct scatterlist *sg, int nents, int direction)
 {
 
@@ -194,7 +234,7 @@
 	devfs_handle_t	vhdl;
 	dma_addr_t dma_addr;
 	paddr_t temp_ptr;
-	struct sn1_device_sysdata *device_sysdata;
+	struct sn_device_sysdata *device_sysdata;
 	pciio_dmamap_t dma_map;
 
 
@@ -205,21 +245,51 @@
 	/*
 	 * Handle 64 bit cards.
 	 */
-	device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata;
+	device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
 	vhdl = device_sysdata->vhdl;
 	for (i = 0; i < nents; i++, sg++) {
-		sg->orig_address = (char *)NULL;
+		/* this catches incorrectly written drivers that
+                   attempt to map scatterlists that they have
+                   previously mapped.  we print a warning and
+                   continue, but the driver should be fixed */
+		switch (((u64)sg->address) >> 60) {
+		case 0xa:
+		case 0xb:
+#ifdef DEBUG
+/* This needs to be cleaned up at some point. */
+			NAG("A PCI driver (for device at%8s) has attempted to "
+			    "map a scatterlist that was previously mapped at "
+			    "%p - this is currently being worked around.\n",
+			    hwdev->slot_name, (void *)sg->address);
+#endif
+			temp_ptr = (u64)sg->address & TO_PHYS_MASK;
+			break;
+		case 0xe: /* a good address, we now map it. */
+			temp_ptr = (paddr_t) __pa(sg->address);
+			break;
+		default:
+			printk(KERN_ERR
+			       "Very bad address (%p) passed to sn_pci_map_sg\n",
+			       (void *)sg->address);
+			BUG();
+		}
+		sg->page = (char *)NULL;
 		dma_addr = 0;
-		temp_ptr = (paddr_t) __pa(sg->address);
 
 		/*
 		 * Handle the most common case 64Bit cards.
 		 */
 		if (IS_PCIA64(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 				temp_ptr, sg->length,
-				PCIBR_BARRIER | PCIIO_BYTE_STREAM |
-				PCIIO_DMA_CMD | PCIIO_DMA_A64 );
+				PCIIO_BYTE_STREAM | PCIIO_DMA_DATA |
+				PCIIO_DMA_A64 );
+#else
+			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+				temp_ptr, sg->length,
+				PCIIO_DMA_DATA | PCIIO_DMA_A64 );
+#endif
 			sg->address = (char *)dma_addr;
 			continue;
 		}
@@ -228,10 +298,14 @@
 		 * Handle 32Bits and greater cards.
 		 */
 		if (IS_PCI32G(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 				temp_ptr, sg->length,
-				PCIBR_BARRIER | PCIIO_BYTE_STREAM |
-				PCIIO_DMA_CMD);
+				PCIIO_BYTE_STREAM | PCIIO_DMA_DATA);
+#else
+			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+				temp_ptr, sg->length, PCIIO_DMA_DATA);
+#endif
 			if (dma_addr) {
 				sg->address = (char *)dma_addr;
 				continue;
@@ -244,9 +318,12 @@
 		 * Let's 32Bit Page map the request.
 		 */
 		dma_map = NULL;
+#ifdef CONFIG_IA64_SGI_SN1
 		dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, 
-				PCIBR_BARRIER | PCIIO_BYTE_STREAM |
-				PCIIO_DMA_CMD);
+				PCIIO_BYTE_STREAM | PCIIO_DMA_DATA);
+#else
+		dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, PCIIO_DMA_DATA);
+#endif
 		if (!dma_map) {
 			printk("pci_map_sg: Unable to allocate anymore 32Bits Page Map entries.\n");
 			BUG();
@@ -254,7 +331,7 @@
 		dma_addr = (dma_addr_t)pciio_dmamap_addr(dma_map, temp_ptr, sg->length);
 		/* printk("pci_map_sg: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, temp_ptr, dma_addr); */
 		sg->address = (char *)dma_addr;
-		sg->orig_address = (char *)dma_map;
+		sg->page = (char *)dma_map;
 		
 	}
 
@@ -268,30 +345,31 @@
  * pci_unmap_single() above.
  */
 void
-sn1_pci_unmap_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction)
+sn_pci_unmap_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction)
 {
 	int i;
-	struct sn1_dma_maps_s *sn1_dma_map;
+	struct sn_dma_maps_s *sn_dma_map;
 
 
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
 	for (i = 0; i < nelems; i++, sg++)
-		if (sg->orig_address) {
+		if (sg->page) {
 			/*
-			 * We maintain the DMA Map pointer in sg->orig_address if 
+			 * We maintain the DMA Map pointer in sg->page if 
 			 * it is ever allocated.
 			 */
 			/* phys_to_virt((dma_addr_t)sg->address | ~0x80000000); */
-			/* sg->address = sg->orig_address; */
+			/* sg->address = sg->page; */
 			sg->address = (char *)-1;
-			sn1_dma_map = (struct sn1_dma_maps_s *)sg->orig_address;
-			pciio_dmamap_done((pciio_dmamap_t)sn1_dma_map);
-			pciio_dmamap_free((pciio_dmamap_t)sn1_dma_map);
-			sn1_dma_map->dma_addr = 0;
-			sg->orig_address = 0;
+			sn_dma_map = (struct sn_dma_maps_s *)sg->page;
+			pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
+			pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
+			sn_dma_map->dma_addr = 0;
+			sg->page = 0;
 		}
+
 }
 
 /*
@@ -304,15 +382,15 @@
  *       get rid of dev_desc and vhdl (seems redundant given a pci_dev);
  *       figure out how to save dmamap handle so can use two step.
  */
-dma_addr_t sn1_pci_map_single (struct pci_dev *hwdev,
+dma_addr_t sn_pci_map_single (struct pci_dev *hwdev,
 				void *ptr, size_t size, int direction)
 {
 	devfs_handle_t	vhdl;
 	dma_addr_t dma_addr;
 	paddr_t temp_ptr;
-	struct sn1_device_sysdata *device_sysdata;
+	struct sn_device_sysdata *device_sysdata;
 	pciio_dmamap_t dma_map = NULL;
-	struct sn1_dma_maps_s *sn1_dma_map;
+	struct sn_dma_maps_s *sn_dma_map;
 
 
 	if (direction == PCI_DMA_NONE)
@@ -322,7 +400,7 @@
 	/*
 	 * find vertex for the device
 	 */
-	device_sysdata = (struct sn1_device_sysdata *)hwdev->sysdata;
+	device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
 	vhdl = device_sysdata->vhdl;
 
 	/*
@@ -335,10 +413,14 @@
 		/*
 		 * This device supports 64bits DMA addresses.
 		 */
+#ifdef CONFIG_IA64_SGI_SN1
 		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 			temp_ptr, size,
-			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD
-			| PCIIO_DMA_A64 );
+			PCIIO_BYTE_STREAM | PCIIO_DMA_DATA | PCIIO_DMA_A64 );
+#else
+		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+			temp_ptr, size, PCIIO_DMA_DATA | PCIIO_DMA_A64 );
+#endif
 		return (dma_addr);
 	}
 
@@ -349,9 +431,14 @@
 	 * First try to get 32 Bit Direct Map Support.
 	 */
 	if (IS_PCI32G(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 			temp_ptr, size,
-			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
+			PCIIO_BYTE_STREAM | PCIIO_DMA_DATA);
+#else
+		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+			temp_ptr, size, PCIIO_DMA_DATA);
+#endif
 		if (dma_addr) {
 			return (dma_addr);
 		}
@@ -369,64 +456,72 @@
 	 * Let's 32Bit Page map the request.
 	 */
 	dma_map = NULL;
-	dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIBR_BARRIER | 
-			PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
+#ifdef CONFIG_IA64_SGI_SN1
+	dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_BYTE_STREAM | 
+				     PCIIO_DMA_DATA);
+#else
+	dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_DATA);
+#endif
 	if (!dma_map) {
 		printk("pci_map_single: Unable to allocate anymore 32Bits Page Map entries.\n");
 		BUG();
 	}
 
 	dma_addr = (dma_addr_t) pciio_dmamap_addr(dma_map, temp_ptr, size);
-	/* printk("pci_map_single: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, 
+	/* printk("pci_map_single: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map,
 		temp_ptr, dma_addr); */
-	sn1_dma_map = (struct sn1_dma_maps_s *)dma_map;
-	sn1_dma_map->dma_addr = dma_addr;
+	sn_dma_map = (struct sn_dma_maps_s *)dma_map;
+	sn_dma_map->dma_addr = dma_addr;
 
 	return ((dma_addr_t)dma_addr);
 }
 
 void
-sn1_pci_unmap_single (struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction)
+sn_pci_unmap_single (struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction)
 {
 
-	struct sn1_dma_maps_s *sn1_dma_map = NULL;
+	struct sn_dma_maps_s *sn_dma_map = NULL;
 
         if (direction == PCI_DMA_NONE)
 		BUG();
 
 	/*
-	 * Get the sn1_dma_map entry.
+	 * Get the sn_dma_map entry.
 	 */
 	if (IS_PCI32_MAPPED(dma_addr))
-		sn1_dma_map = find_sn1_dma_map(dma_addr, hwdev->bus->number);
+		sn_dma_map = find_sn_dma_map(dma_addr, hwdev->bus->number);
 
-	if (sn1_dma_map) {
-		pciio_dmamap_done((pciio_dmamap_t)sn1_dma_map);
-		pciio_dmamap_free((pciio_dmamap_t)sn1_dma_map);
-		sn1_dma_map->dma_addr = (dma_addr_t)NULL;
+	if (sn_dma_map) {
+		pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
+		pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
+		sn_dma_map->dma_addr = (dma_addr_t)NULL;
 	}
 
 }
 
 void
-sn1_pci_dma_sync_single (struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction)
+sn_pci_dma_sync_single (struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction)
 {
 	
         if (direction == PCI_DMA_NONE)
                 BUG();
-        /* Nothing to do */
+
+	sn_dma_sync(hwdev);
+
 }
 
 void
-sn1_pci_dma_sync_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction)
+sn_pci_dma_sync_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction)
 {
         if (direction == PCI_DMA_NONE)
                 BUG();
-        /* Nothing to do */
+
+	sn_dma_sync(hwdev);
+
 }
 
 unsigned long
-sn1_dma_address (struct scatterlist *sg)
+sn_dma_address (struct scatterlist *sg)
 {
 	return ((unsigned long)sg->address);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/pciba.c linux/arch/ia64/sn/io/pciba.c
--- linux.orig/arch/ia64/sn/io/pciba.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/pciba.c	2002-08-01 06:42:30.000000000 +0000
@@ -1,1716 +1,958 @@
-/* $Id$
+/*
+ * arch/ia64/sn/io/pciba.c
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * IRIX PCIBA-inspired user mode PCI interface
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * requires: devfs
+ *
+ * device nodes show up in /dev/pci/BB/SS.F (where BB is the bus the
+ * device is on, SS is the slot the device is in, and F is the
+ * device's function on a multi-function card).
+ *
+ * when compiled into the kernel, it will only be initialized by the
+ * sgi sn1 specific initialization code.  in this case, device nodes
+ * are under /dev/hw/..../
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * 03262001 - Initial version by Chad Talbott
  */
 
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/xtalk/xwidget.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/pci/pci_defs.h>
-#include <asm/sn/prio.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/xtalk/xbow.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/eeprom.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/sn_private.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/hubio.h>
-#include <asm/sn/sn1/hubio_next.h>
-#endif
 
-#define copyin(_a, _b, _c)	copy_from_user(_b, _a, _c)
+/* jesse's beefs:
+
+   register_pci_device should be documented
+   
+   grossness with do_swap should be documented
+   
+   big, gross union'ized node_data should be replaced with independent
+   structures
+
+   replace global list of nodes with global lists of resources.  could
+   use object oriented approach of allocating and cleaning up
+   resources.
+   
+*/
+
 
-#ifndef	DEBUG_PCIBA
-#define	DEBUG_PCIBA		0
+#include <linux/config.h>
+#ifndef CONFIG_DEVFS_FS
+#  error PCIBA requires devfs
 #endif
 
-/* v_mapphys does not percolate page offset back. */
-#define	PCIBA_ALIGN_CHECK	1
+#include <linux/module.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/pci.h>
+#include <linux/list.h>
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/mman.h>
+#include <linux/init.h>
+#include <linux/raw.h>
+#include <linux/capability.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/pgalloc.h>
+#include <asm/page.h>
 
 #include <asm/sn/pci/pciba.h>
 
-/* grab an unused space code for "User DMA" space */
-#ifndef	PCIBA_SPACE_UDMA
-#define	PCIBA_SPACE_UDMA	(14)
+
+MODULE_DESCRIPTION("User mode PCI interface");
+MODULE_AUTHOR("Chad Talbott");
+
+
+#undef DEBUG_PCIBA
+/* #define DEBUG_PCIBA */
+
+#undef TRACE_PCIBA
+/* #define TRACE_PCIBA */
+
+#if defined(DEBUG_PCIBA)
+#  define DPRINTF(x...) printk(KERN_DEBUG x)
+#else
+#  define DPRINTF(x...)
 #endif
 
-#if DEBUG_REFCT
-extern int		hwgraph_vertex_refct(vertex_hdl_t);
+#if defined(TRACE_PCIBA)
+#  if defined(__GNUC__)
+#    define TRACE()	printk(KERN_DEBUG "%s:%d:%s\n", \
+			       __FILE__, __LINE__, __FUNCTION__)
+#  else
+#    define TRACE()	printk(KERN_DEBUG "%s:%d\n", __LINE__, __FILE__)
+#  endif
+#else
+#  define TRACE()
 #endif
-extern int		pci_user_dma_max_pages;
 
-#define NEW(ptr)	(ptr = kmem_zalloc(sizeof (*(ptr)), KM_SLEEP))
-#define DEL(ptr)	(kfree(ptr))
 
-/* Oops -- no standard "pci address" type! */
-typedef uint64_t        pciaddr_t;
+typedef enum { failure, success } status;
+typedef enum { false, true } boolean;
 
-/* ================================================================
- *            driver types
- */
-typedef struct pciba_slot_s *pciba_slot_t;
-typedef struct pciba_comm_s *pciba_comm_t;
-typedef struct pciba_soft_s *pciba_soft_t;
-typedef struct pciba_map_s *pciba_map_t, **pciba_map_h;
-typedef struct pciba_dma_s *pciba_dma_t, **pciba_dma_h;
-typedef struct pciba_bus_s *pciba_bus_t;
-
-#define	TRACKED_SPACES	16
-struct pciba_comm_s {
-    devfs_handle_t	    conn;
-    pciba_bus_t             bus;
-    int			    refct;
-    pciba_soft_t	    soft[TRACKED_SPACES][2];
-    struct semaphore        lock;
-    pciba_dma_t             dmap;
+
+/* major data structures:
+
+   struct node_data -
+   
+   	one for each file registered with devfs.  contains everything
+   	that any file's fops would need to know about.
+
+   struct dma_allocation -
+
+   	a single DMA allocation.  only the 'dma' nodes care about
+   	these.  they are there primarily to allow the driver to look
+   	up the kernel virtual address of dma buffers allocated by
+   	pci_alloc_consistent, as the application is only given the
+   	physical address (to program the device's dma, presumably) and
+   	cannot supply the kernel virtual address when freeing the
+   	buffer.
+
+	it's also useful to maintain a list of buffers allocated
+	through a specific node to allow some sanity checking by this
+	driver.  this prevents (for example) a broken application from
+	freeing buffers that it didn't allocate, or buffers allocated
+	on another node.
+   
+   global_node_list -
+
+   	a list of all nodes allocated.  this allows the driver to free
+   	all the memory it has 'kmalloc'd in case of an error, or on
+   	module removal.
+
+   global_dma_list -
+
+        a list of all dma buffers allocated by this driver.  this
+	allows the driver to 'pci_free_consistent' all buffers on
+	module removal or error.
+
+*/
+
+
+struct node_data {
+	/* flat list of all the device nodes.  makes it easy to free
+	   them all when we're unregistered */
+	struct list_head global_node_list;
+	devfs_handle_t devfs_handle;
+
+	void (* cleanup)(struct node_data *);
+
+	union {
+		struct {
+			struct pci_dev * dev;
+			struct list_head dma_allocs;
+			boolean mmapped;
+		} dma;
+		struct {
+			struct pci_dev * dev;
+			u32 saved_rom_base_reg;
+			boolean mmapped;
+		} rom;
+		struct {
+			struct resource * res;
+		} base;
+		struct {
+			struct pci_dev * dev;
+		} config;
+	} u;
 };
 
-/* pciba_soft: device_info() for all openables */
-struct pciba_soft_s {
-    pciba_comm_t	    comm;
-    devfs_handle_t          vhdl;
-    int			    refct;
-    pciio_space_t           space;
-    size_t                  size;
-    pciio_space_t           iomem;
-    pciaddr_t               base;
-    unsigned		    flags;
+struct dma_allocation {
+	struct list_head list;
+
+	dma_addr_t handle;
+	void * va;
+	size_t size;
 };
 
-#define	pciba_soft_get(v)	(pciba_soft_t)hwgraph_fastinfo_get(v)
-#define	pciba_soft_set(v,i)	hwgraph_fastinfo_set(v,(arbitrary_info_t)(i))
 
-#define	pciba_soft_lock(soft)	down(&soft->comm->lock)
-#define	pciba_soft_unlock(soft)	up(&soft->comm->lock)
+static LIST_HEAD(global_node_list);
+static LIST_HEAD(global_dma_list);
 
-/* pciba_map: data describing a mapping.
- * (ie. a user mmap request)
- */
-struct pciba_map_s {
-    pciba_map_t             next;
-#ifdef LATER
-    uthread_t              *uthread;
-#endif
-    __psunsigned_t          handle;
-    uvaddr_t                uvaddr;
-    size_t                  size;
-    pciio_piomap_t          map;
-    pciio_space_t           space;
-    pciaddr_t               base;
-    unsigned		    flags;
-};
 
-/* pciba_dma: data describing a DMA mapping.
- */
-struct pciba_dma_s {
-    pciba_dma_t             next;
-    iopaddr_t               paddr;	/* starting phys addr */
-    caddr_t                 kaddr;	/* starting kern addr */
-    pciio_dmamap_t          map;	/* mapping resources (ugh!) */
-    pciaddr_t               daddr;	/* starting pci addr */
-    size_t                  pages;	/* size of block in pages */
-    size_t                  bytes;	/* size of block in bytes */
-    __psunsigned_t          handle;	/* mapping handle */
+/* module entry points */
+int __init pciba_init(void);
+void __exit pciba_exit(void);
+
+static status __init register_with_devfs(void);
+static void __exit unregister_with_devfs(void);
+
+static status __init register_pci_device(devfs_handle_t device_dir_handle,
+					 struct pci_dev * dev);
+
+/* file operations */
+static int generic_open(struct inode * inode, struct file * file);
+static int rom_mmap(struct file * file, struct vm_area_struct * vma);
+static int rom_release(struct inode * inode, struct file * file);
+static int base_mmap(struct file * file, struct vm_area_struct * vma);
+static int config_ioctl(struct inode * inode, struct file * file, 
+			unsigned int cmd, 
+			unsigned long arg);
+static int dma_ioctl(struct inode * inode, struct file * file, 
+		     unsigned int cmd, 
+		     unsigned long arg);
+static int dma_mmap(struct file * file, struct vm_area_struct * vma);
+
+/* support routines */
+static int mmap_pci_address(struct vm_area_struct * vma, unsigned long pci_va);
+static int mmap_kernel_address(struct vm_area_struct * vma, void * kernel_va);
+
+#ifdef DEBUG_PCIBA
+static void dump_nodes(struct list_head * nodes);
+static void dump_allocations(struct list_head * dalp);
+#endif
+
+/* file operations for each type of node */
+static struct file_operations rom_fops = {
+	owner:		THIS_MODULE,
+	mmap:		rom_mmap,
+	open:		generic_open,
+	release:	rom_release
 };
+ 
 
-/* pciba_bus: common bus info for all openables
- * descended from the same master vertex.
- */
-struct pciba_bus_s {
-    struct semaphore        lock;
-    pciba_map_t             maps;	/* stack of mappings */
-    int			    refct;
+static struct file_operations base_fops = {
+	owner:		THIS_MODULE,
+	mmap:		base_mmap,
+	open:		generic_open
 };
 
-#define	pciba_bus_lock(bus)	down(&bus->lock)
-#define	pciba_bus_unlock(bus)	up(&bus->lock)
 
-typedef union ioctl_arg_buffer_u {
-    char                    data[IOCPARM_MASK + 1];
-    uint8_t                 uc;
-    uint16_t                us;
-    uint32_t                ui;
-    uint64_t                ud;
-    caddr_t                 ca;
-#if ULI
-    struct uliargs          uli;
-    struct uliargs32	    uli32;
-#endif
-} ioctl_arg_buffer_t;
+static struct file_operations config_fops = {
+	owner:		THIS_MODULE,
+	ioctl:		config_ioctl,
+	open:		generic_open
+};	
 
-/* ================================================================
- *            driver variables
- */
-char                   *pciba_mversion = "mload version 7.0";
-int                     pciba_devflag = 0x1 |
-                                        0x200 |
-                                        0x400;
+static struct file_operations dma_fops = {
+	owner:		THIS_MODULE,
+	ioctl:		dma_ioctl,
+	mmap:		dma_mmap,
+	open:		generic_open
+};	
 
-/* this counts the reasons why we can not
- * currently unload this driver.
- */
-atomic_t                pciba_prevent_unload = ATOMIC_INIT(0);
 
-#if DEBUG_PCIBA
-static struct reg_values space_v[] =
-{
-    {PCIIO_SPACE_NONE, "none"},
-    {PCIIO_SPACE_ROM, "ROM"},
-    {PCIIO_SPACE_IO, "I/O"},
-    {PCIIO_SPACE_MEM, "MEM"},
-    {PCIIO_SPACE_MEM32, "MEM(32)"},
-    {PCIIO_SPACE_MEM64, "MEM(64)"},
-    {PCIIO_SPACE_CFG, "CFG"},
-    {PCIIO_SPACE_WIN(0), "WIN(0)"},
-    {PCIIO_SPACE_WIN(1), "WIN(1)"},
-    {PCIIO_SPACE_WIN(2), "WIN(2)"},
-    {PCIIO_SPACE_WIN(3), "WIN(3)"},
-    {PCIIO_SPACE_WIN(4), "WIN(4)"},
-    {PCIIO_SPACE_WIN(5), "WIN(5)"},
-    {PCIBA_SPACE_UDMA, "UDMA"},
-    {PCIIO_SPACE_BAD, "BAD"},
-    {0}
-};
+module_init(pciba_init);
+module_exit(pciba_exit);
+
 
-static struct reg_desc  space_desc[] =
+int __init
+pciba_init(void)
 {
-    {0xFF, 0, "space", 0, space_v},
-    {0}
-};
-#endif
+	TRACE();
 
-char                    pciba_edge_lbl_base[] = "base";
-char                    pciba_edge_lbl_cfg[] = "config";
-char                    pciba_edge_lbl_dma[] = "dma";
-char                    pciba_edge_lbl_intr[] = "intr";
-char                    pciba_edge_lbl_io[] = "io";
-char                    pciba_edge_lbl_mem[] = "mem";
-char                    pciba_edge_lbl_rom[] = "rom";
-char                   *pciba_edge_lbl_win[6] =
-{"0", "1", "2", "3", "4", "5"};
-
-#define	PCIBA_EDGE_LBL_BASE	pciba_edge_lbl_base
-#define	PCIBA_EDGE_LBL_CFG	pciba_edge_lbl_cfg
-#define	PCIBA_EDGE_LBL_DMA	pciba_edge_lbl_dma
-#define	PCIBA_EDGE_LBL_INTR	pciba_edge_lbl_intr
-#define	PCIBA_EDGE_LBL_IO	pciba_edge_lbl_io
-#define	PCIBA_EDGE_LBL_MEM	pciba_edge_lbl_mem
-#define	PCIBA_EDGE_LBL_ROM	pciba_edge_lbl_rom
-#define	PCIBA_EDGE_LBL_WIN(n)	pciba_edge_lbl_win[n]
-
-#define	PCIBA_EDGE_LBL_FLIP	pciba_edge_lbl_flip
-
-static char             pciba_info_lbl_bus[] = "pciba_bus";
-
-#define	PCIBA_INFO_LBL_BUS	pciba_info_lbl_bus
-
-struct file_operations pciba_fops = {
-	owner:	THIS_MODULE,
-	llseek: NULL,
-	read: NULL,
-	write: NULL,
-	readdir: NULL,
-	poll: NULL,
-	ioctl: NULL,
-	mmap: NULL,
-	open: NULL,
-	flush: NULL,
-	release: NULL,
-	fsync: NULL,
-	fasync: NULL,
-	lock: NULL,
-	readv: NULL,
-	writev: NULL
-};
-	
-/* ================================================================
- *            function table of contents
- */
+	if (register_with_devfs() == failure)
+		return 1; /* failure */
 
-void                    pciba_init(void);
-int                     pciba_attach(devfs_handle_t);
+	printk("PCIBA (a user mode PCI interface) initialized.\n");
 
-static void		pciba_sub_attach(pciba_comm_t,
-					 pciio_space_t, pciio_space_t, pciaddr_t,
-					 devfs_handle_t, devfs_handle_t, char *);
-
-static pciba_bus_t      pciba_find_bus(devfs_handle_t, int);
-#ifdef LATER
-static void             pciba_map_push(pciba_bus_t, pciba_map_t);
-static pciba_map_t      pciba_map_pop_hdl(pciba_bus_t, __psunsigned_t);
-static void             pciba_sub_detach(devfs_handle_t, char *);
-static pciio_iter_f     pciba_unload_me;
-#endif
+	return 0; /* success */
+}
 
-int                     pciba_unload(void);
-int                     pciba_unreg(void);
-int                     pciba_detach(devfs_handle_t);
-
-int                     pciba_open(dev_t *, int, int, struct cred *);
-int                     pciba_close(dev_t);
-int                     pciba_read(dev_t, cred_t *);
-int                     pciba_write(dev_t, cred_t *);
-int                     pciba_ioctl(dev_t, int, void *, int, cred_t *, int *);
-
-int                     pciba_map(dev_t, vhandl_t *, off_t, size_t, uint32_t);
-int                     pciba_unmap(dev_t, vhandl_t *);
-
-#if ULI
-void                    pciba_clearuli(struct uli *);
-static intr_func_f      pciba_intr;
-#endif /* Undef as it gets implemented */
 
-/* ================================================================
- *            driver load, register, and setup
- */
-void
-pciba_init(void)
+void __exit
+pciba_exit(void)
 {
+	TRACE();
 
-	/*
-	 * What do we need to do here?
-	 */
-#if DEBUG_PCIBA
-    printk("pciba_init()\n");
-#endif
+	/* FIXME: should also free all that memory that we allocated
+           ;) */
+	unregister_with_devfs();
 }
 
-#ifdef LATER
-#if HWG_PERF_CHECK && IP30 && !DEBUG
-void
-pciba_timeout(void *arg1, void *arg2)
-{
-    struct semaphore       *semap = (sema_t *) arg1;
-    unsigned long          *cvalp = (unsigned long *) arg2;
-
-    if (cvalp)
-	cvalp[0] = RAW_COUNT();
-    if (semap)
-	up(semap);
-}
-
-volatile unsigned long  cNval[1];
-struct semaphore        tsema;
-
-void
-pciba_timeout_test(void)
-{
-    unsigned long           c0val, cval;
-    toid_t                  tid;
-
-    extern void             hwg_hprint(unsigned long, char *);
-
-    sema_init(&tsema, 0);
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) 0, 1, (void *) cNval);
-    DELAY(1000000);
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_ALERT("pciba: one-tick timeout did not happen in a second\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(1)");
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) &tsema, 2, (void *) cNval);
-
-    /* FIXME : this probably needs to be down_interruptible() */
-
-    if (down(&tsema) < 0) {	/* wait for the pciba_timeout */
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(2) time check aborted\n");
-	return;
-    }
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(2) time not logged\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(2)");
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) &tsema, HZ, (void *) cNval);
-
-    /* FIXME : this probably needs to be down_interruptible() */
-
-    if (down(&tsema) < 0) {	/* wait for the pciba_timeout */
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(HZ) time check aborted\n");
-	return;
-    }
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(HZ) time not logged\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(HZ)");
-
-    printk("verifying untimeout() cancells ...\n");
-    cNval[0] = 0;
-    tid = timeout((void (*)()) pciba_timeout, (void *) 0, 2, (void *) cNval);
-    untimeout(tid);
-    DELAY(1000000);
-    cval = cNval[0];
-    if (cval != 0) {
-	PRINT_ALERT("pciba: unable to cancel two-tick timeout\n");
-	cval -= c0val;
-	hwg_hprint(cval, "CANCELLED timeout(2)");
-    }
-}
-#endif
 
-int
-pciba_reg(void)
+# if 0
+static void __exit
+free_nodes(void)
 {
-#if DEBUG_PCIBA
-    printk("pciba_reg()\n");
-#endif
-    pciio_driver_register(-1, -1, "pciba_", 0);
-
-#if HWG_PERF_CHECK && IP30 && !DEBUG
-    printk("%s %d\n", __FUNCTION__, __LINE__);
-pciba_timeout_test();
-#endif
+	struct node_data * nd;
+	
+	TRACE();
 
-#if DEBUG_REFCT
-    {
-	char	       *cname = "pciba";
-	char	       *dname = "ptv";
-	char           *cpath0 = "node/xtalk/15";
-	char           *uname0 = "0";
-	char           *cpath1 = "node/xtalk/13";
-	char           *uname1 = "1";
-	devfs_handle_t conn;
-	devfs_handle_t conv;
-	devfs_handle_t vhdl;
-	int		ret;
-
-	printk("pciba refct tests:\n");
-
-#define	SHOWREF(vhdl,func)	printk("ref=%d\t%s\t(%d) %v\n", hwgraph_vertex_refct(vhdl), #func, vhdl, vhdl);
-
-	if (GRAPH_SUCCESS != (ret = hwgraph_path_add(hwgraph_root, cname, &conv)))
-	    printk("\tunable to create conv (ret=%d)\n", ret);
-	else {						SHOWREF(conv, hwgraph_path_add);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath0, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath0, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_char_device_add(conn, dname, "pciba_", &vhdl)))
-		    printk("unable to create %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_char_device_add);
-		    hwgraph_chmod(vhdl, 0666);		SHOWREF(vhdl, hwgraph_chmod);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_add(conv, vhdl, uname0)))
-			printk("unable to create %v/%s (ret=%d)\n", conn, uname0, vhdl, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_add);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
- 
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath1, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath1, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_char_device_add(conn, dname, "pciba_", &vhdl)))
-		    printk("unable to create %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_char_device_add);
-		    hwgraph_chmod(vhdl, 0666);		SHOWREF(vhdl, hwgraph_chmod);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_add(conv, vhdl, uname1)))
-			printk("unable to create %v/%s (ret=%d)\n", conn, uname1, vhdl, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_add);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
- 
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath0, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath0, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_traverse(conn, dname, &vhdl)))
-		    printk("\tunable to find %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_traverse);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conv, uname0, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conv, uname0, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conn, dname, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conn, dname, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(vhdl)))
-			printk("\tvertex %d destroyed OK\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_destroy);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
-
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath1, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath1, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_traverse(conn, dname, &vhdl)))
-		    printk("\tunable to find %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_traverse);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conv, uname1, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conv, uname1, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conn, dname, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conn, dname, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(vhdl)))
-			printk("\tvertex %d destroyed OK\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_destroy);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
-
-	    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(hwgraph_root, cname, NULL)))
-		printk("\tunable to remove edge %v/%s (ret=%d)\n", hwgraph_root, cname, ret);
-	    else				SHOWREF(conv, hwgraph_edge_remove);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conv)))
-		printk("unable to unref %v\n", conv);
-	    else					SHOWREF(conv, hwgraph_vertex_unref);
-	    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(conv)))
-		printk("\tvertex %d destroyed OK\n", conv);
-	    else					SHOWREF(conv, hwgraph_vertex_destroy);
+	list_for_each(nd, &node_list) {
+		kfree(list_entry(nd, struct nd, node_list));
 	}
-    }
-#endif
-
-    return 0;
 }
-
-#endif
-int
-pciba_attach(devfs_handle_t hconn)
-{
-#if defined(PCIIO_SLOT_NONE)
-    pciio_info_t            info = pciio_info_get(hconn);
-    pciio_slot_t            slot = pciio_info_slot_get(info);
 #endif
-    pciba_comm_t	    comm;
-    pciba_bus_t             bus;
-    int                     ht;
-    devfs_handle_t	    hbase;
-    devfs_handle_t          gconn;
-    devfs_handle_t          gbase;
-    int                     win;
-    int                     wins;
-    pciio_space_t           space;
-    pciaddr_t               base;
 
-    int                     iwins;
-    int                     mwins;
 
-#if DEBUG_PCIBA
-    printk("pciba_attach(%p)\n", hconn);
-#endif
+static devfs_handle_t pciba_devfs_handle;
 
-    /* Pick up "dualslot guest" vertex,
-     * which gets all functionality except
-     * config space access.
-     */
-    if ((GRAPH_SUCCESS !=
-	 hwgraph_traverse(hconn, ".guest", &gconn)) ||
-	(hconn == gconn))
-	gconn = GRAPH_VERTEX_NONE;
-
-    bus = pciba_find_bus(hconn, 1);
-    bus->refct ++;
-
-    /* set up data common to all pciba openables
-     * on this connection point.
-     */
-    NEW(comm);
-    comm->conn = hconn;
-    comm->bus = bus;
-    comm->refct = 0;
-    sema_init(&comm->lock, 1);
 
-#if !defined(PCIIO_SLOT_NONE)
-    if (bus->refct == 1)
-#else
-    if (slot == PCIIO_SLOT_NONE)
-#endif
-    {
-	pciio_info_t            pciio_info;
-	devfs_handle_t          master;
-
-	pciio_info = pciio_info_get(hconn);
-	master = pciio_info_master_get(pciio_info);
-
-	pciba_sub_attach(comm, PCIIO_SPACE_IO, PCIIO_SPACE_IO, 0, master, master, PCIBA_EDGE_LBL_IO);
-	pciba_sub_attach(comm, PCIIO_SPACE_MEM, PCIIO_SPACE_MEM, 0, master, master, PCIBA_EDGE_LBL_MEM);
-#if defined(PCIIO_SLOT_NONE)
-	return 0;
-#endif
-    }
+#if !defined(CONFIG_IA64_SGI_SN1)
 
-    ht = 0x7F & pciio_config_get(hconn, PCI_CFG_HEADER_TYPE, 1);
+static status __init
+register_with_devfs(void)
+{
+	struct pci_dev * dev;
+	devfs_handle_t device_dir_handle;
+	char devfs_path[40];
 
-    wins = ((ht == 0x00) ? 6 :
-	    (ht == 0x01) ? 2 :
-	    0);
-
-    mwins = iwins = 0;
-
-    hbase = GRAPH_VERTEX_NONE;
-    gbase = GRAPH_VERTEX_NONE;
-
-    for (win = 0; win < wins; win++) {
-
-	base = pciio_config_get(hconn, PCI_CFG_BASE_ADDR(win), 4);
-	if (base & 1) {
-	    space = PCIIO_SPACE_IO;
-	    base &= 0xFFFFFFFC;
-	} else if ((base & 7) == 4) {
-	    space = PCIIO_SPACE_MEM;
-	    base &= 0xFFFFFFF0;
-	    base |= ((pciaddr_t) pciio_config_get(hconn, PCI_CFG_BASE_ADDR(win + 1), 4)) << 32;
-	} else {
-	    space = PCIIO_SPACE_MEM;
-	    base &= 0xFFFFFFF0;
-	}
+	TRACE();
 
-	if (!base)
-	    break;
+	pciba_devfs_handle = devfs_mk_dir(NULL, "pci", NULL);
+	if (pciba_devfs_handle == NULL)
+		return failure;
 
-#if PCIBA_ALIGN_CHECK
-	if (base & (_PAGESZ - 1)) {
-#if DEBUG_PCIBA
-	    PRINT_WARNING("%p pciba: BASE%d not page aligned!\n"
-		    "\tmmap this window at offset 0x%x via \".../pci/%s\"\n",
-		    hconn, win, base,
-		    (space == PCIIO_SPACE_IO) ? "io" : "mem");
-#endif
-	    continue;			/* next window */
-	}
-#endif
+	/* FIXME: don't forget /dev/pci/mem & /dev/pci/io */
+
+	pci_for_each_dev(dev) {
+		sprintf(devfs_path, "%02x/%02x.%x",
+			dev->bus->number,
+			PCI_SLOT(dev->devfn),
+			PCI_FUNC(dev->devfn));
+    
+		device_dir_handle =
+			devfs_mk_dir(pciba_devfs_handle, devfs_path, NULL);
+		if (device_dir_handle == NULL)
+			return failure;
 
-	if ((hbase == GRAPH_VERTEX_NONE) &&
-	    ((GRAPH_SUCCESS !=
-	      hwgraph_path_add(hconn, PCIBA_EDGE_LBL_BASE, &hbase)) ||
-	     (hbase == GRAPH_VERTEX_NONE)))
-	    break;			/* no base vertex, no more windows. */
-
-	if ((gconn != GRAPH_VERTEX_NONE) &&
-	    (gbase == GRAPH_VERTEX_NONE) &&
-	    ((GRAPH_SUCCESS !=
-	      hwgraph_path_add(gconn, PCIBA_EDGE_LBL_BASE, &gbase)) ||
-	     (gbase == GRAPH_VERTEX_NONE)))
-	    break;			/* no base vertex, no more windows. */
-
-	pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hbase, gbase, PCIBA_EDGE_LBL_WIN(win));
-
-	if (space == PCIIO_SPACE_IO) {
-	    if (!iwins++) {
-		pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hconn, gconn, PCIBA_EDGE_LBL_IO);
-	    }
-	} else {
-	    if (!mwins++) {
-		pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hconn, gconn, PCIBA_EDGE_LBL_MEM);
-	    }
+		if (register_pci_device(device_dir_handle, dev) == failure) {
+			devfs_unregister(pciba_devfs_handle);
+			return failure;
+		}
 	}
 
-	if ((base & 7) == 4)
-	    win++;
-    }
-
-    pciba_sub_attach(comm, PCIIO_SPACE_CFG, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_CFG);
-    pciba_sub_attach(comm, PCIBA_SPACE_UDMA, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_DMA);
-#if ULI
-    pciba_sub_attach(comm, PCIIO_SPACE_NONE, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_INTR);
-#endif
+	return success;
+}
 
-    /* XXX should ignore if device is an IOC3 */
-    if (ht == 0x01)
-	base = pciio_config_get(hconn, PCI_EXPANSION_ROM+8, 4);
-    else
-	base = pciio_config_get(hconn, PCI_EXPANSION_ROM, 4);
-
-    base &= 0xFFFFF000;
-
-    if (base) {
-	if (base & (_PAGESZ - 1))
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    PRINT_WARNING("%v pciba: ROM is 0x%x\n"
-		    "\tnot page aligned, mmap will be difficult\n",
-		    hconn, base);
 #else
-	    PRINT_WARNING("0x%x pciba: ROM is 0x%x\n"
-		    "\tnot page aligned, mmap will be difficult\n",
-		    hconn, base);
-#endif
-	pciba_sub_attach(comm, PCIIO_SPACE_ROM, PCIIO_SPACE_MEM, base, hconn, gconn, PCIBA_EDGE_LBL_ROM);
-    }
 
-#if !FICUS	/* FICUS shorts the refct by one on path_add */
-    if (hbase != GRAPH_VERTEX_NONE)
-	hwgraph_vertex_unref(hbase);
+extern devfs_handle_t
+devfn_to_vertex(unsigned char busnum, unsigned int devfn);
 
-    if (gbase != GRAPH_VERTEX_NONE)
-	hwgraph_vertex_unref(gbase);
-#endif
+static status __init
+register_with_devfs(void)
+{
+	struct pci_dev * dev;
+	devfs_handle_t device_dir_handle;
 
-    return 0;
-}
+	TRACE();
 
-static void
-pciba_sub_attach2(pciba_comm_t comm,
-		  pciio_space_t space,
-		  pciio_space_t iomem,
-		  pciaddr_t base,
-		  devfs_handle_t from,
-		  char *name,
-		  char *suf,
-		  unsigned bigend)
-{
-    char		nbuf[128];
-    pciba_soft_t            soft;
-    devfs_handle_t	handle = NULL;
-
-    if (suf && *suf) {
-	strcpy(nbuf, name);
-	name = nbuf;
-	strcat(name, suf);
-    }
-
-#if DEBUG_PCIBA
-    printk("pciba_sub_attach2 %p/%s %p at %p[%x]\n",
-	   from, name, space, space_desc, iomem, space_desc, base, from, name);
-#endif
+	/* FIXME: don't forget /dev/.../pci/mem & /dev/.../pci/io */
 
-    if (space < TRACKED_SPACES)
-	if ((soft = comm->soft[space][bigend]) != NULL) {
-	    soft->refct ++;
-	    hwgraph_edge_add(from, soft->vhdl, name);
-	    return;
+	pci_for_each_dev(dev) {
+		device_dir_handle = devfn_to_vertex(dev->bus->number,
+						    dev->devfn);
+		if (device_dir_handle == NULL)
+			return failure;
+	
+		if (register_pci_device(device_dir_handle, dev) == failure) {
+			devfs_unregister(pciba_devfs_handle);
+			return failure;
+		}
 	}
 
-    NEW(soft);
-    if (!soft)
-	return;
-
-    soft->comm = comm;
-    soft->space = space;
-    soft->size = 0;
-    soft->iomem = iomem;
-    soft->base = base;
-    soft->refct = 1;
-
-    if (space == PCIIO_SPACE_NONE)
-	soft->flags = 0;
-    else if (bigend)
-	soft->flags = PCIIO_BYTE_STREAM;
-    else
-	soft->flags = PCIIO_WORD_VALUES;
-
-    handle = hwgraph_register(from, name,
-		0, DEVFS_FL_AUTO_DEVNUM,
-		0, 0,
-		S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-		&pciba_fops, NULL);
-    soft->vhdl = handle;
-    pciba_soft_set(soft->vhdl, soft);
-    if (space < TRACKED_SPACES)
-	comm->soft[space][bigend] = soft;
-    comm->refct ++;
+	return success;
 }
 
-static void
-pciba_sub_attach1(pciba_comm_t comm,
-		  pciio_space_t space,
-		  pciio_space_t iomem,
-		  pciaddr_t base,
-		  devfs_handle_t hfrom,
-		  devfs_handle_t gfrom,
-		  char *name,
-		  char *suf,
-		  unsigned bigend)
-{
-    pciba_sub_attach2(comm, space, iomem, base, hfrom, name, suf, bigend);
-    if ((gfrom != GRAPH_VERTEX_NONE) && (gfrom != hfrom))
-	pciba_sub_attach2(comm, space, iomem, base, gfrom, name, suf, bigend);
-}
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
+static void __exit
+unregister_with_devfs(void)
+{
+	struct list_head * lhp;
+	struct node_data * nd;
+	
+	TRACE();
+
+	list_for_each(lhp, &global_node_list) {
+		nd = list_entry(lhp, struct node_data, global_node_list);
+		devfs_unregister(nd->devfs_handle);
+	}
 
-static void
-pciba_sub_attach(pciba_comm_t comm,
-		 pciio_space_t space,
-		 pciio_space_t iomem,
-		 pciaddr_t base,
-		 devfs_handle_t hfrom,
-		 devfs_handle_t gfrom,
-		 char *name)
-{
-    pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, NULL, 0);
-    if (iomem != PCIIO_SPACE_NONE) {
-	pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, "_le", 0);
-	pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, "_be", 1);
-    }
 }
 
-#ifdef LATER
-static void
-pciba_reload_me(devfs_handle_t pconn_vhdl)
+
+struct node_data * new_node(void)
 {
-    devfs_handle_t            vhdl;
+	struct node_data * node;
+	
+	TRACE();
+	
+	node = kmalloc(sizeof(struct node_data), GFP_KERNEL);
+	if (node == NULL)
+		return NULL;
+	list_add(&node->global_node_list, &global_node_list);
+	return node;
+}
 
-#if DEBUG_PCIBA
-    printf("pciba_reload_me(%v)\n", pconn_vhdl);
-#endif
 
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, PCIBA_EDGE_LBL_CFG, &vhdl))
-	return;
+void dma_cleanup(struct node_data * dma_node)
+{
+	TRACE();
 
-    hwgraph_vertex_unref(vhdl);
+	/* FIXME: should free these allocations */
+#ifdef DEBUG_PCIBA
+	dump_allocations(&dma_node->u.dma.dma_allocs);
+#endif
+	devfs_unregister(dma_node->devfs_handle);
 }
-#endif	/* LATER */
 
-static                  pciba_bus_t
-pciba_find_bus(devfs_handle_t pconn, int cflag)
+
+void init_dma_node(struct node_data * node,
+		   struct pci_dev * dev, devfs_handle_t dh)
 {
-    pciio_info_t            pciio_info;
-    devfs_handle_t          master;
-    arbitrary_info_t        ainfo;
-    pciba_bus_t             bus;
+	TRACE();
 
-    pciio_info = pciio_info_get(pconn);
-    master = pciio_info_master_get(pciio_info);
+	node->devfs_handle = dh;
+	node->u.dma.dev = dev;
+	node->cleanup = dma_cleanup;
+	INIT_LIST_HEAD(&node->u.dma.dma_allocs);
+}
 
-    if (GRAPH_SUCCESS ==
-	hwgraph_info_get_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo))
-	return (pciba_bus_t) ainfo;
 
-    if (!cflag)
-	return 0;
+void rom_cleanup(struct node_data * rom_node)
+{
+	TRACE();
 
-    NEW(bus);
-    if (!bus)
-	return 0;
+	if (rom_node->u.rom.mmapped)
+		pci_write_config_dword(rom_node->u.rom.dev,
+				       PCI_ROM_ADDRESS,
+				       rom_node->u.rom.saved_rom_base_reg);
+	devfs_unregister(rom_node->devfs_handle);
+}
 
-    sema_init(&bus->lock, 1);
 
-    ainfo = (arbitrary_info_t) bus;
-    hwgraph_info_add_LBL(master, PCIBA_INFO_LBL_BUS, ainfo);
-    hwgraph_info_get_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo);
-    if ((pciba_bus_t) ainfo != bus)
-	DEL(bus);
-#if DEBUG_PCIBA
-    else
-	printk("pcbia_find_bus: new bus at %p\n", master);
-#endif
+void init_rom_node(struct node_data * node,
+		   struct pci_dev * dev, devfs_handle_t dh)
+{
+	TRACE();
 
-    return (pciba_bus_t) ainfo;
+	node->devfs_handle = dh;
+	node->u.rom.dev = dev;
+	node->cleanup = rom_cleanup;
+	node->u.rom.mmapped = false;
 }
 
-#ifdef LATER
-static void
-pciba_map_push(pciba_bus_t bus, pciba_map_t map)
+
+static status __init
+register_pci_device(devfs_handle_t device_dir_handle, struct pci_dev * dev)
 {
-#if DEBUG_PCIBA
-    printk("pciba_map_push(bus=0x%x, map=0x%x, hdl=0x%x\n",
-	   bus, map, map->handle);
-#endif
-    pciba_bus_lock(bus);
-    map->next = bus->maps;
-    bus->maps = map;
-    pciba_bus_unlock(bus);
-}
-
-static                  pciba_map_t
-pciba_map_pop_hdl(pciba_bus_t bus, __psunsigned_t handle)
-{
-    pciba_map_h             hdl;
-    pciba_map_t             map;
-
-    pciba_bus_lock(bus);
-    for (hdl = &bus->maps; map = *hdl; hdl = &map->next)
-	if (map->handle == handle) {
-	    *hdl = map->next;
-	    break;
+	struct node_data * nd;
+	char devfs_path[20];
+	devfs_handle_t node_devfs_handle;
+	int ri;
+
+	TRACE();
+
+
+	/* register nodes for all the device's base address registers */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (pci_resource_len(dev, ri) != 0) {
+			sprintf(devfs_path, "base/%d", ri);
+			if (devfs_register(device_dir_handle, devfs_path,
+					   DEVFS_FL_NONE,
+					   0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+		}
 	}
-    pciba_bus_unlock(bus);
-#if DEBUG_PCIBA
-    printk("pciba_map_pop_va(bus=0x%x, handle=0x%x) returns map=0x%x\n",
-	   bus, handle, map);
+	
+	/* register a node corresponding to the first MEM resource on
+           the device */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (dev->resource[ri].flags & IORESOURCE_MEM &&
+		    pci_resource_len(dev, ri) != 0) {
+			if (devfs_register(device_dir_handle, "mem",
+					   DEVFS_FL_NONE, 0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+			break;
+		}
+	}
+
+	/* also register a node corresponding to the first IO resource
+           on the device */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (dev->resource[ri].flags & IORESOURCE_IO &&
+		    pci_resource_len(dev, ri) != 0) {
+			if (devfs_register(device_dir_handle, "io",
+					   DEVFS_FL_NONE, 0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+			break;
+		}
+	}
+
+	/* register a node corresponding to the device's ROM resource,
+           if present */
+	if (pci_resource_len(dev, PCI_ROM_RESOURCE) != 0) {
+		nd = new_node();
+		if (nd == NULL)
+			return failure;
+		node_devfs_handle = devfs_register(device_dir_handle, "rom",
+						   DEVFS_FL_NONE, 0, 0,
+						   S_IFREG | S_IRUSR,
+						   &rom_fops, nd);
+		if (node_devfs_handle == NULL)
+			return failure;
+		init_rom_node(nd, dev, node_devfs_handle);
+	}
+
+	/* register a node that allows ioctl's to read and write to
+           the device's config space */
+	if (devfs_register(device_dir_handle, "config", DEVFS_FL_NONE,
+			   0, 0, S_IFREG | S_IRUSR | S_IWUSR,
+			   &config_fops, dev) == NULL)
+		return failure;
+
+
+	/* finally, register a node that allows ioctl's to allocate
+           and free DMA buffers, as well as memory map those
+           buffers. */
+	nd = new_node();
+	if (nd == NULL)
+		return failure;
+	node_devfs_handle =
+		devfs_register(device_dir_handle, "dma", DEVFS_FL_NONE,
+			       0, 0, S_IFREG | S_IRUSR | S_IWUSR,
+			       &dma_fops, nd);
+	if (node_devfs_handle == NULL)
+		return failure;
+	init_dma_node(nd, dev, node_devfs_handle);
+
+#ifdef DEBUG_PCIBA
+	dump_nodes(&global_node_list);
 #endif
-    return map;
+	
+	return success;
 }
 
-/* ================================================================
- *            driver teardown, unregister and unload
- */
-int
-pciba_unload(void)
-{
-#if DEBUG_PCIBA
-    printk("pciba_unload()\n");
-#endif
 
-    if (atomic_read(&pciba_prevent_unload))
-	return -1;
+static int
+generic_open(struct inode * inode, struct file * file)
+{
+	TRACE();
 
-    pciio_iterate("pciba_", pciba_unload_me);
+	/* FIXME: should check that they're not trying to open the ROM
+           writable */
 
-    return 0;
+	return 0; /* success */
 }
 
-int
-pciba_unreg(void)
+
+static int
+rom_mmap(struct file * file, struct vm_area_struct * vma)
 {
+	unsigned long pci_pa;
+	struct node_data * nd;
 
-#if DEBUG_PCIBA
-    printf("pciba_unreg()\n");
-#endif
+	TRACE();
 
-    if (atomic_read(&pciba_prevent_unload))
-	return -1;
+	nd = (struct node_data * )file->private_data;
 
-    pciio_driver_unregister("pciba_");
-    return 0;
+	pci_pa = pci_resource_start(nd->u.rom.dev, PCI_ROM_RESOURCE);
+
+	if (!nd->u.rom.mmapped) {
+		nd->u.rom.mmapped = true;
+		DPRINTF("Enabling ROM address decoder.\n");
+		DPRINTF(
+"rom_mmap: FIXME: some cards do not allow both ROM and memory addresses to\n"
+"rom_mmap: FIXME: be enabled simultaneously, as they share a decoder.\n");
+		pci_read_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				      &nd->u.rom.saved_rom_base_reg);
+		DPRINTF("ROM base address contains %x\n",
+			nd->u.rom.saved_rom_base_reg);
+		pci_write_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				       nd->u.rom.saved_rom_base_reg |
+				       PCI_ROM_ADDRESS_ENABLE);
+	}
+	
+	return mmap_pci_address(vma, pci_pa);
 }
 
-int
-pciba_detach(devfs_handle_t conn)
+
+static int
+rom_release(struct inode * inode, struct file * file)
 {
-    devfs_handle_t          base;
-    pciba_bus_t             bus;
-    devfs_handle_t          gconn;
-    devfs_handle_t          gbase;
+	struct node_data * nd;
 
-    pciio_info_t            pciio_info;
-    devfs_handle_t          master;
-    arbitrary_info_t        ainfo;
-    int			    ret;
+	TRACE();
 
-#if DEBUG_PCIBA
-    printf("pciba_detach(%v)\n", conn);
-#endif
+	nd = (struct node_data * )file->private_data;
 
-    if ((GRAPH_SUCCESS !=
-	 hwgraph_traverse(conn, ".guest", &gconn)) ||
-	(conn == gconn))
-	gconn = GRAPH_VERTEX_NONE;
-
-    if (gconn != GRAPH_VERTEX_NONE) {
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_CFG);
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_DMA);
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_ROM);
-#if ULI
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_INTR);
-#endif
-	if (GRAPH_SUCCESS == hwgraph_edge_remove(conn, PCIBA_EDGE_LBL_BASE, &gbase)) {
-	    pciba_sub_detach(gconn, PCIBA_EDGE_LBL_MEM);
-	    pciba_sub_detach(gconn, PCIBA_EDGE_LBL_IO);
-	    pciba_sub_detach(gbase, "0");
-	    pciba_sub_detach(gbase, "1");
-	    pciba_sub_detach(gbase, "2");
-	    pciba_sub_detach(gbase, "3");
-	    pciba_sub_detach(gbase, "4");
-	    pciba_sub_detach(gbase, "5");
-	    hwgraph_vertex_unref(gbase);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(gbase))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(%v/base) failed (%d)",
-			conn, ret);
-#else
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(0x%x/base) failed (%d)",
-			conn, ret);
-#endif
-#if DEBUG_REFCT
-		printk("\tretained refct %d\n", hwgraph_vertex_refct(gbase));
-#endif
-	    }
+	if (nd->u.rom.mmapped) {
+		nd->u.rom.mmapped = false;
+		DPRINTF("Disabling ROM address decoder.\n");
+		pci_write_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				       nd->u.rom.saved_rom_base_reg);
 	}
-    }
+	return 0; /* indicate success */
+}
 
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_CFG);
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_DMA);
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_ROM);
-#if ULI
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_INTR);
-#endif
 
-    if (GRAPH_SUCCESS == hwgraph_edge_remove(conn, PCIBA_EDGE_LBL_BASE, &base)) {
-	pciba_sub_detach(conn, PCIBA_EDGE_LBL_MEM);
-	pciba_sub_detach(conn, PCIBA_EDGE_LBL_IO);
-	pciba_sub_detach(base, "0");
-	pciba_sub_detach(base, "1");
-	pciba_sub_detach(base, "2");
-	pciba_sub_detach(base, "3");
-	pciba_sub_detach(base, "4");
-	pciba_sub_detach(base, "5");
-	hwgraph_vertex_unref(base);
-	if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(base))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    PRINT_WARNING(CE_WARN, "pciba: hwgraph_vertex_destroy(%v/base) failed (%d)",
-		    conn, ret);
-#else
-	    PRINT_WARNING(CE_WARN, "pciba: hwgraph_vertex_destroy(0x%x/base) failed (%d)",
-		    conn, ret);
-#endif
-#if DEBUG_REFCT
-	    printk("\tretained refct %d\n", hwgraph_vertex_refct(base));
-#endif
-	}
-    }
+static int
+base_mmap(struct file * file, struct vm_area_struct * vma)
+{
+	struct resource * resource;
 
-    bus = pciba_find_bus(conn, 0);
-    if (bus && !--(bus->refct)) {
+	TRACE();
 
-	pciio_info = pciio_info_get(conn);
+	resource = (struct resource *)file->private_data;
 
-	master = pciio_info_master_get(pciio_info);
+	return mmap_pci_address(vma, resource->start);
+}
 
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_IO);
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_MEM);
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_CFG);
-	hwgraph_info_remove_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo);
 
-#if DEBUG_PCIBA
-	printf("pcbia_detach: DEL(bus) at %v\n", master);
-#endif
-	DEL(bus);
-    } 
+static int
+config_ioctl(struct inode * inode, struct file * file, 
+	     unsigned int cmd, 
+	     unsigned long arg)
+{
+	struct pci_dev * dev;
 
-    return 0;
-}
+	union cfg_data {
+		uint8_t byte;
+		uint16_t word;
+		uint32_t dword;
+	} read_data, write_data;
 
-static void
-pciba_sub_detach1(devfs_handle_t conn,
-		  char *name,
-		  char *suf)
-{
-    devfs_handle_t         vhdl;
-    pciba_soft_t            soft;
-    pciba_comm_t	    comm;
-    int			    ret;
-    char		nbuf[128];
-
-    if (suf && *suf) {
-	strcpy(nbuf, name);
-	name = nbuf;
-	strcat(name, suf);
-    }
-
-    if ((GRAPH_SUCCESS == hwgraph_edge_remove(conn, name, &vhdl)) &&
-	((soft = pciba_soft_get(vhdl)) != NULL)) {
-#if DEBUG_PCIBA
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	prink("pciba_sub_detach(%v,%s)\n", conn, name);
-#else
-	prink("pciba_sub_detach(0x%x,%s)\n", conn, name);
-#endif
-#endif
+	int dir, size, offset;
 
-	hwgraph_vertex_unref(soft->vhdl);
-#if DEBUG_REFCT
-	printk("\tadjusted refct %d (soft ref: %d)\n",
-		hwgraph_vertex_refct(vhdl),
-		soft->refct);
-#endif
-	if (!--(soft->refct)) {
-	    comm = soft->comm;
-	    if (!--(comm->refct)) {
-		DEL(comm);
-	    }
-	    pciba_soft_set(vhdl, 0);
-	    DEL(soft);
-
-	    hwgraph_vertex_unref(vhdl);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(vhdl))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(0x%x/%s) failed (%d)",
-			conn, name, ret);
-#else
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(%v/%s) failed (%d)",
-			conn, name, ret);
-#endif
-#if DEBUG_REFCT
-		printk("\tretained refct %d\n", hwgraph_vertex_refct(vhdl));
-#endif
-	    }
-	}
-    }
-}
+	TRACE();
 
-static void
-pciba_sub_detach(devfs_handle_t conn,
-		 char *name)
-{
-    pciba_sub_detach1(conn, name, "");
-    pciba_sub_detach1(conn, name, "_le");
-    pciba_sub_detach1(conn, name, "_be");
-}
+	DPRINTF("cmd = %x (DIR = %x, TYPE = %x, NR = %x, SIZE = %x)\n", 
+		cmd, 
+		_IOC_DIR(cmd), _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
+	DPRINTF("arg = %lx\n", arg);
 
-static void
-pciba_unload_me(devfs_handle_t pconn_vhdl)
-{
-    devfs_handle_t         c_vhdl;
+	dev = (struct pci_dev *)file->private_data;
 
-#if DEBUG_PCIBA
-    printf("pciba_unload_me(%v)\n", pconn_vhdl);
-#endif
+	/* PCIIOCCFG{RD,WR}: read and/or write PCI configuration
+	   space. If both, the read happens first (this becomes a swap
+	   operation, atomic with respect to other updates through
+	   this path).  */
 
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, PCIBA_EDGE_LBL_CFG, &c_vhdl))
-	return;
+	dir = _IOC_DIR(cmd);
 
-    hwgraph_vertex_unref(c_vhdl);
-}
+#define do_swap(suffix, type)	 					\
+	do {								\
+		if (dir & _IOC_READ) {					\
+			pci_read_config_##suffix(dev, _IOC_NR(cmd), 	\
+						 &read_data.suffix);	\
+		}							\
+		if (dir & _IOC_WRITE) {					\
+			get_user(write_data.suffix, (type)arg);		\
+			pci_write_config_##suffix(dev, _IOC_NR(cmd), 	\
+						  write_data.suffix);	\
+		}							\
+		if (dir & _IOC_READ) {					\
+			put_user(read_data.suffix, (type)arg);		\
+		}							\
+	} while (0)
 
-/* ================================================================
- *            standard unix entry points
- */
+	size = _IOC_SIZE(cmd);
+	offset = _IOC_NR(cmd);
 
-/*ARGSUSED */
-int
-pciba_open(dev_t *devp, int flag, int otyp, struct cred *crp)
-{
+	DPRINTF("sanity check\n");
+	if (((size > 0) || (size <= 4)) &&
+	    ((offset + size) <= 256) &&
+	    (dir & (_IOC_READ | _IOC_WRITE))) {
 
-#if DEBUG_PCIBA
-    printf("pciba_open(%V)\n", *devp);
-#endif
-    return 0;
+		switch (size)
+		{
+		case 1:
+			do_swap(byte, uint8_t *);
+			break;
+		case 2:
+			do_swap(word, uint16_t *);
+			break;
+		case 4:
+			do_swap(dword, uint32_t *);
+			break;
+		default:
+			DPRINTF("invalid ioctl\n");
+			return -EINVAL;
+		}
+	} else
+		return -EINVAL;
+		
+	return 0;
 }
 
-/*ARGSUSED */
-int
-pciba_close(dev_t dev)
-{
-    devfs_handle_t         vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-
-#if DEBUG_PCIBA
-    printf("pciba_close(%V)\n", dev);
-#endif
 
-    /* if there is pending DMA for this device, hit the
-     * device over the head with a baseball bat and
-     * release the system memory resources.
-     */
-    if (soft && soft->comm->dmap) {
-	pciba_dma_t             next;
-	pciba_dma_t             dmap;
-
-	pciba_soft_lock(soft);
-	if (dmap = soft->comm->dmap) {
-	    soft->comm->dmap = 0;
-
-	    pciio_reset(soft->comm->conn);
-
-	    do {
-		if (!dmap->kaddr)
-		    break;
-		if (!dmap->paddr)
-		    break;
-		if (dmap->bytes < NBPP)
-		    break;
-		next = dmap->next;
-		kvpfree(dmap->kaddr, dmap->bytes / NBPP);
-		dmap->paddr = 0;
-		dmap->bytes = 0;
-		DEL(dmap);
-	    } while (dmap = next);
+#ifdef DEBUG_PCIBA
+static void
+dump_allocations(struct list_head * dalp)
+{
+	struct dma_allocation * dap;
+	struct list_head * p;
+	
+	printk("{\n");
+	list_for_each(p, dalp) {
+		dap = list_entry(p, struct dma_allocation, 
+				 list);
+		printk("  handle = %lx, va = %p\n",
+		       dap->handle, dap->va);
 	}
-	pciba_soft_unlock(soft);
-    }
-    return 0;
+	printk("}\n");
 }
 
-/* ARGSUSED */
-int
-pciba_read(dev_t dev, cred_t *crp)
+static void
+dump_nodes(struct list_head * nodes)
 {
-#if DEBUG_PCIBA
-    printf("pciba_read(%V)\n", dev);
-#endif
-
-    return EINVAL;
+	struct node_data * ndp;
+	struct list_head * p;
+	
+	printk("{\n");
+	list_for_each(p, nodes) {
+		ndp = list_entry(p, struct node_data, 
+				 global_node_list);
+		printk("  %p\n", (void *)ndp);
+	}
+	printk("}\n");
 }
 
-/* ARGSUSED */
-int
-pciba_write(dev_t dev, cred_t *crp)
+
+#if 0
+#define NEW(ptr) (ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
+
+static void
+test_list(void)
 {
-#if DEBUG_PCIBA
-    printf("pciba_write(%V)\n", dev);
-#endif
+	u64 i;
+	LIST_HEAD(the_list);
 
-    return EINVAL;
+	for (i = 0; i < 5; i++) {
+		struct dma_allocation * new_alloc;
+		NEW(new_alloc);
+		new_alloc->va = (void *)i;
+		new_alloc->handle = 5*i;
+		printk("%d - the_list->next = %lx\n", i, the_list.next);
+		list_add(&new_alloc->list, &the_list);
+	}
+	dump_allocations(&the_list);
 }
-
-/*ARGSUSED */
-int
-pciba_ioctl(dev_t dev, int cmd, void *uarg, int mode, cred_t *crp, int *rvalp)
-{
-    devfs_handle_t          vhdl;
-    pciba_soft_t            soft;
-    pciio_space_t           space;
-    ioctl_arg_buffer_t      arg;
-    int                     psize;
-    int                     err = 0;
-
-#if ULI
-    char		    abi = get_current_abi();
-    pciio_intr_t            intr=0;
-    device_desc_t           desc;
-    cpuid_t                 intrcpu;
-    unsigned                lines;
-    struct uli             *uli = 0;
 #endif
-    unsigned                flags;
-    void                   *kaddr = 0;
-    iopaddr_t               paddr;
-    pciba_dma_h             dmah;
-    pciba_dma_t             dmap = 0;
-    pciio_dmamap_t          dmamap = 0;
-    size_t                  bytes;
-    int                     pages;
-    pciaddr_t               daddr;
-
-#if DEBUG_PCIBA
-    printf("pciba_ioctl(%V,0x%x)\n", dev, cmd);
 #endif
 
-    psize = (cmd >> 16) & IOCPARM_MASK;
-
-#if ULI
-    ASSERT(sizeof(struct uliargs) > 8);	/* prevent CFG access conflict */
-    ASSERT(sizeof(struct uliargs) <= IOCPARM_MASK);
-#endif
 
-    arg.ca = uarg;
+static LIST_HEAD(dma_buffer_list);
 
-    if ((psize > 0) && (cmd & (IOC_OUT | IOC_IN))) {
-	if (psize > sizeof(arg))
-	    err = EINVAL;		/* "bad parameter size */
-	else {
-	    if (cmd & IOC_OUT)
-		bzero(arg.data, psize);
-	    if ((cmd & IOC_IN) &&
-		(copyin(uarg, arg.data, psize) < 0))
-		err = EFAULT;		/* "parameter copyin failed" */
-	}
-    }
-    vhdl = dev_to_vhdl(dev);
-    soft = pciba_soft_get(vhdl);
-    space = soft->space;
-
-    if (err == 0) {
-	err = EINVAL;			/* "invalid ioctl for this vertex" */
-	switch (space) {
-#if ULI
-	case PCIIO_SPACE_NONE:		/* the "intr" vertex */
-	    /* PCIIOCSETULI: set up user interrupts.
-	     */
-	    lines = cmd & 15;
-	    if (ABI_IS_64BIT(abi)) {
-		if (cmd != PCIIOCSETULI(lines)) {
-		    err = EINVAL;		/* "invalid ioctl for this vertex" */
-		    break;
-		}
-	    }
-	    else {
-		struct uliargs uliargs;
-
-		if (cmd != PCIIOCSETULI32(lines)) {
-		    err = EINVAL;		/* "invalid ioctl for this vertex" */
-		    break;
-		}
-		
-		uliargs32_to_uliargs(&arg.uli32, &uliargs);
-		arg.uli = uliargs;
-	    }
-	    desc = device_desc_dup(soft->comm->conn);
-	    device_desc_flags_set(desc, (device_desc_flags_get(desc) |
-					 D_INTR_NOTHREAD));
-	    device_desc_intr_swlevel_set(desc, INTR_SWLEVEL_NOTHREAD_DEFAULT);
-	    device_desc_intr_name_set(desc, "PCIBA");
-	    device_desc_default_set(soft->comm->conn, desc);
-
-	    /* When designating interrupts, the slot number
-	     * is taken from the connection point.
-	     * Bits 0..3 are used to select INTA..INTD; more
-	     * than one bit can be specified. These should
-	     * be constructed using PCIIO_INTR_LINE_[ABCD].
-	     */
-	    intr = pciio_intr_alloc
-		(soft->comm->conn, desc, lines, soft->vhdl);
-	    if (intr == 0) {
-		err = ENOMEM;		/* "insufficient resources" */
-		break;
-	    }
-	    intrcpu = cpuvertex_to_cpuid(pciio_intr_cpu_get(intr));
 
-	    if (err = new_uli(&arg.uli, &uli, intrcpu)) {
-		break;			/* "unable to set up ULI" */
-	    }
-	    atomic_inc(&pciba_prevent_unload);
-
-	    pciio_intr_connect(intr, pciba_intr, uli, (void *) 0);
-
-	    /* NOTE: don't set the teardown function
-	     * until the interrupt is connected.
-	     */
-	    uli->teardownarg1 = (__psint_t) intr;
-	    uli->teardown = pciba_clearuli;
-
-	    arg.uli.id = uli->index;
-
-	    if (!ABI_IS_64BIT(abi)) {
-		struct uliargs32 uliargs32;
-		uliargs_to_uliargs32(&arg.uli, &uliargs32);
-		arg.uli32 = uliargs32;
-	    }
+static int
+dma_ioctl(struct inode * inode, struct file * file, 
+	  unsigned int cmd, 
+	  unsigned long arg)
+{
+	struct node_data * nd;
+	uint64_t argv;
+	int result;
+	struct dma_allocation * dma_alloc;
+	struct list_head * iterp;
 
-	    err = 0;
-	    break;
-#endif
+	TRACE();
 
-	case PCIBA_SPACE_UDMA:		/* the "dma" vertex */
+	DPRINTF("cmd = %x\n", cmd);
+	DPRINTF("arg = %lx\n", arg);
 
-	    switch (cmd) {
+	nd = (struct node_data *)file->private_data;
 
-	    case PCIIOCDMAALLOC:
-		/* PCIIOCDMAALLOC: allocate a chunk of physical
-		 * memory and set it up for DMA. Return the
-		 * PCI address that gets to it.
-		 * NOTE: this allocates memory local to the
-		 * CPU doing the ioctl, not local to the
-		 * device that will be doing the DMA.
-		 */
-
-		if (!_CAP_ABLE(CAP_DEVICE_MGT)) {
-		    err = EPERM;
-		    break;
-		}
-		/* separate the halves of the incoming parameter */
-		flags = arg.ud >> 32;
-		bytes = arg.ud & 0xFFFFFFFF;
-
-#if DEBUG_PCIBA
-		printf("pciba: user wants 0x%x bytes of DMA, flags 0x%x\n",
-		       bytes, flags);
+#ifdef DEBUG_PCIBA
+	DPRINTF("at dma_ioctl entry\n");
+	dump_allocations(&nd->u.dma.dma_allocs);
 #endif
 
-		/* round up the requested size to the next highest page */
-		pages = (bytes + NBPP - 1) / NBPP;
-
-		/* make sure the requested size is something reasonable */
-		if (pages > pci_user_dma_max_pages) {
-#if DEBUG_PCIBA
-		    printf("pciba: request for too much buffer space\n");
+	switch (cmd) {
+	case PCIIOCDMAALLOC:
+		/* PCIIOCDMAALLOC: allocate a chunk of physical memory
+		   and set it up for DMA. Return the PCI address that
+		   gets to it.  */
+		DPRINTF("case PCIIOCDMAALLOC (%lx)\n", PCIIOCDMAALLOC);
+		
+		if ( (result = get_user(argv, (uint64_t *)arg)) )
+			return result;
+		DPRINTF("argv (size of buffer) = %lx\n", argv);
+
+		dma_alloc = (struct dma_allocation *)
+			kmalloc(sizeof(struct dma_allocation), GFP_KERNEL);
+		if (dma_alloc == NULL)
+			return -ENOMEM;
+
+		dma_alloc->size = (size_t)argv;
+		dma_alloc->va = pci_alloc_consistent(nd->u.dma.dev,
+						     dma_alloc->size,
+						     &dma_alloc->handle);
+		DPRINTF("dma_alloc->va = %p, dma_alloc->handle = %lx\n",
+			dma_alloc->va, dma_alloc->handle);
+		if (dma_alloc->va == NULL) {
+			kfree(dma_alloc);
+			return -ENOMEM;
+		}
+
+		list_add(&dma_alloc->list, &nd->u.dma.dma_allocs);
+		if ( (result = put_user((uint64_t)dma_alloc->handle, 
+				      (uint64_t *)arg)) ) {
+			DPRINTF("put_user failed\n");
+			pci_free_consistent(nd->u.dma.dev, (size_t)argv,
+					    dma_alloc->va, dma_alloc->handle);
+			kfree(dma_alloc);
+			return result;
+		}
+
+#ifdef DEBUG_PCIBA
+		DPRINTF("after insertion\n");
+		dump_allocations(&nd->u.dma.dma_allocs);
 #endif
-		    err = EINVAL;
-		    break;		/* "request for too much buffer space" */
-		}
-		/* "correct" number of bytes */
-		bytes = pages * NBPP;
+		break;
 
-		/* allocate the space */
-		/* XXX- force to same node as the device? */
-		/* XXX- someday, we want to handle user buffers,
-		 *    and noncontiguous pages, but this will
-		 *      require either fancy mapping or handing
-		 *      a list of blocks back to the user. For
-		 *      now, just tell users to allocate a lot of
-		 *      individual single-pages and manage their
-		 *      scatter-gather manually.
-		 */
-		kaddr = kvpalloc(pages, VM_DIRECT | KM_NOSLEEP, 0);
-		if (kaddr == 0) {
-#if DEBUG_PCIBA
-		    printf("pciba: unable to get %d contiguous pages\n", pages);
-#endif
-		    err = EAGAIN;	/* "insufficient resources, try again later" */
-		    break;
-		}
-#if DEBUG_PCIBA
-		printf("pciba: kaddr is 0x%x\n", kaddr);
-#endif
-		paddr = kvtophys(kaddr);
+	case PCIIOCDMAFREE:
+		DPRINTF("case PCIIOCDMAFREE (%lx)\n", PCIIOCDMAFREE);
 
-		daddr = pciio_dmatrans_addr
-		    (soft->comm->conn, 0, paddr, bytes, flags);
-		if (daddr == 0) {	/* "no direct path available" */
-#if DEBUG_PCIBA
-		    printf("pciba: dmatrans failed, trying dmamap\n");
-#endif
-		    dmamap = pciio_dmamap_alloc
-			(soft->comm->conn, 0, bytes, flags);
-		    if (dmamap == 0) {
-#if DEBUG_PCIBA
-			printf("pciba: unable to allocate dmamap\n");
-#endif
-			err = ENOMEM;
-			break;		/* "out of mapping resources" */
-		    }
-		    daddr = pciio_dmamap_addr
-			(dmamap, paddr, bytes);
-		    if (daddr == 0) {
-#if DEBUG_PCIBA
-			printf("pciba: dmamap_addr failed\n");
-#endif
-			err = EINVAL;
-			break;		/* "can't get there from here" */
-		    }
-		}
-#if DEBUG_PCIBA
-		printf("pciba: daddr is 0x%x\n", daddr);
+		if ( (result = get_user(argv, (uint64_t *)arg)) ) {
+			DPRINTF("get_user failed\n");
+			return result;
+		}
+
+		DPRINTF("argv (physical address of DMA buffer) = %lx\n", argv);
+		list_for_each(iterp, &nd->u.dma.dma_allocs) {
+			struct dma_allocation * da =
+				list_entry(iterp, struct dma_allocation, list);
+			if (da->handle == argv) {
+				pci_free_consistent(nd->u.dma.dev, da->size,
+						    da->va, da->handle);
+				list_del(&da->list);
+				kfree(da);
+#ifdef DEBUG_PCIBA
+				DPRINTF("after deletion\n");
+				dump_allocations(&nd->u.dma.dma_allocs);
 #endif
-		NEW(dmap);
-		if (!dmap) {
-		    err = ENOMEM;
-		    break;		/* "no memory available" */
+				return 0; /* success */
+			}
 		}
-		dmap->bytes = bytes;
-		dmap->pages = pages;
-		dmap->paddr = paddr;
-		dmap->kaddr = kaddr;
-		dmap->map = dmamap;
-		dmap->daddr = daddr;
-		dmap->handle = 0;
-
-#if DEBUG_PCIBA
-		printf("pciba: dmap 0x%x contains va 0x%x bytes 0x%x pa 0x%x pages 0x%x daddr 0x%x\n",
-		       dmap, kaddr, bytes, paddr, pages, daddr);
-#endif
+		/* previously allocated dma buffer wasn't found */
+		DPRINTF("attempt to free invalid dma handle\n");
+		return -EINVAL;
 
-		arg.ud = dmap->daddr;
+	default:
+		DPRINTF("undefined ioctl\n");
+		return -EINVAL;
+	}
 
-		err = 0;
-		break;
+	DPRINTF("success\n");
+	return 0;
+}
+		
 
-	    case PCIIOCDMAFREE:
-		/* PCIIOCDMAFREE: Find the chunk of
-		 * User DMA memory, and release its
-		 * resources back to the system.
-		 */
-
-		if (!_CAP_ABLE(CAP_DEVICE_MGT)) {
-		    err = EPERM;	/* "you can't do that" */
-		    break;
-		}
-		if (soft->comm->dmap == NULL) {
-		    err = EINVAL;	/* "no User DMA to free" */
-		    break;
-		}
-		/* find the request. */
-		daddr = arg.ud;
-		err = EINVAL;		/* "block not found" */
-		pciba_soft_lock(soft);
-		for (dmah = &soft->comm->dmap; dmap = *dmah; dmah = &dmap->next) {
-		    if (dmap->daddr == daddr) {
-			if (dmap->handle != 0) {
-			    dmap = 0;	/* don't DEL this dmap! */
-			    err = EINVAL;	/* "please unmap first" */
-			    break;		/* break outa for loop. */
-			}
-			*dmah = dmap->next;
+static int
+dma_mmap(struct file * file, struct vm_area_struct * vma)
+{
+	struct node_data * nd;
+	struct list_head * iterp;
+	int result;
+	
+	TRACE();
 
-			if (dmamap = dmap->map) {
-			    pciio_dmamap_free(dmamap);
-			    dmamap = 0;	/* don't free it twice! */
+	nd = (struct node_data *)file->private_data;
+	
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
+	DPRINTF("offset = %lx\n", vma->vm_pgoff);
+
+	/* get kernel virtual address for the dma buffer (necessary
+	 * for the mmap). */
+	list_for_each(iterp, &nd->u.dma.dma_allocs) {
+		struct dma_allocation * da =
+			list_entry(iterp, struct dma_allocation, list);
+		/* why does mmap shift its offset argument? */
+		if (da->handle == vma->vm_pgoff << PAGE_SHIFT) {
+			DPRINTF("found dma handle\n");
+			if ( (result = mmap_kernel_address(vma,
+							   da->va)) ) {
+				return result; /* failure */
+			} else {
+				/* it seems like at least one of these
+				   should show up in user land....
+				   I'm missing something */
+				*(char *)da->va = 0xaa;
+				strncpy(da->va, "        Toastie!", da->size);
+				if (put_user(0x18badbeeful,
+					     (u64 *)vma->vm_start))
+					DPRINTF("put_user failed?!\n");
+				return 0; /* success */
 			}
-			kvpfree(dmap->kaddr, dmap->bytes / NBPP);
-			DEL(dmap);
-			dmap = 0;	/* don't link this back into the list! */
-			err = 0;	/* "all done" */
-			break;		/* break outa for loop. */
-		    }
-		}
-		pciba_soft_unlock(soft);
-		break;		/* break outa case PCIIOCDMAFREE: */
-	    }
-	    break;		/* break outa case PCIBA_SPACE_UDMA: */
-
-	case PCIIO_SPACE_CFG:
-
-	    /* PCIIOCCFG{RD,WR}: read and/or write
-	     * PCI configuration space. If both,
-	     * the read happens first (this becomes
-	     * a swap operation, atomic with respect
-	     * to other updates through this path).
-	     *
-	     * Should be *last* IOCTl command checked,
-	     * so other patterns can nip useless codes
-	     * out of the space this decodes.
-	     */
-	    err = EINVAL;
-	    if ((psize > 0) || (psize <= 8) &&
-		(((cmd & 0xFF) + psize) <= 256) &&
-		(cmd & (IOC_IN | IOC_OUT))) {
-
-		uint64_t                rdata;
-		uint64_t                wdata;
-		int                     shft;
-
-		shft = 64 - (8 * psize);
-
-		wdata = arg.ud >> shft;
-
-		pciba_soft_lock(soft);
-
-		if (cmd & IOC_OUT)
-		    rdata = pciio_config_get(soft->comm->conn, cmd & 0xFFFF, psize);
-		if (cmd & IOC_IN)
-		    pciio_config_set(soft->comm->conn, cmd & 0xFFFF, psize, wdata);
-
-		pciba_soft_unlock(soft);
 
-		arg.ud = rdata << shft;
-		err = 0;
-		break;
-	    }
-	    break;
-	}
-    }
-    /* done: come here if all went OK.
-     */
-    if ((err == 0) &&
-	((cmd & IOC_OUT) && (psize > 0)) &&
-	copyout(arg.data, uarg, psize))
-	err = EFAULT;
-
-    /* This gets delayed until after the copyout so we
-     * do not free the dmap on a copyout error, or
-     * alternately end up with a dangling allocated
-     * buffer that the user never got back.
-     */
-    if ((err == 0) && dmap) {
-	pciba_soft_lock(soft);
-	dmap->next = soft->comm->dmap;
-	soft->comm->dmap = dmap;
-	pciba_soft_unlock(soft);
-    }
-    if (err) {
-	/* Things went badly. Clean up.
-	 */
-#if ULI
-	if (intr) {
-	    pciio_intr_disconnect(intr);
-	    pciio_intr_free(intr);
-	}
-	if (uli)
-	    free_uli(uli);
-#endif
-	if (dmap) {
-	    if (dmap->map && (dmap->map != dmamap))
-		pciio_dmamap_free(dmap->map);
-	    DEL(dmap);
+		}
 	}
-	if (dmamap)
-	    pciio_dmamap_free(dmamap);
-	if (kaddr)
-	    kvpfree(kaddr, pages);
-    }
-    return *rvalp = err;
+	DPRINTF("attempt to mmap an invalid dma handle\n");
+	return -EINVAL;
 }
 
-/* ================================================================
- *            mapping support
- */
-
-/*ARGSUSED */
-int
-pciba_map(dev_t dev, vhandl_t *vt,
-	  off_t off, size_t len, uint32_t prot)
-{
-    devfs_handle_t          vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-    devfs_handle_t          conn = soft->comm->conn;
-    pciio_space_t           space = soft->space;
-    size_t                  pages = (len + NBPP - 1) / NBPP;
-    pciio_piomap_t          pciio_piomap = 0;
-    caddr_t                 kaddr;
-    pciba_map_t             map;
-    pciba_dma_t             dmap;
 
-#if DEBUG_PCIBA
-    printf("pciba_map(%V,vt=0x%x)\n", dev, vt);
-#endif
+static int
+mmap_pci_address(struct vm_area_struct * vma, unsigned long pci_va)
+{
+	unsigned long pci_pa;
 
-    if (space == PCIBA_SPACE_UDMA) {
-	pciba_soft_lock(soft);
+	TRACE();
 
-	for (dmap = soft->comm->dmap; dmap != NULL; dmap = dmap->next) {
-	    if (off == dmap->daddr) {
-		if (pages != dmap->pages) {
-		    pciba_soft_unlock(soft);
-		    return EINVAL;	/* "size mismatch" */
-		}
-		v_mapphys(vt, dmap->kaddr, dmap->bytes);
-		dmap->handle = v_gethandle(vt);
-		pciba_soft_unlock(soft);
-#if DEBUG_PCIBA
-		printf("pciba: mapped dma at kaddr 0x%x via handle 0x%x\n",
-		       dmap->kaddr, dmap->handle);
-#endif
-		return 0;
-	    }
-	}
-	pciba_soft_unlock(soft);
-	return EINVAL;			/* "block not found" */
-    }
-    if (soft->iomem == PCIIO_SPACE_NONE)
-	return EINVAL;			/* "mmap not supported" */
-
-    kaddr = (caddr_t) pciio_pio_addr
-	(conn, 0, space, off, len, &pciio_piomap, soft->flags | PCIIO_FIXED );
-
-#if DEBUG_PCIBA
-    printf("pciba: mapped %R[0x%x..0x%x] via map 0x%x to kaddr 0x%x\n",
-	   space, space_desc, off, off + len - 1, pciio_piomap, kaddr);
-#endif
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
 
-    if (kaddr == NULL)
-	return EINVAL;			/* "you can't get there from here" */
+	/* the size of the vma doesn't necessarily correspond to the
+           size specified in the mmap call.  So we can't really do any
+           kind of sanity check here.  This is a dangerous driver, and
+           it's very easy for a user process to kill the machine.  */
 
-    NEW(map);
-    if (map == NULL) {
-	if (pciio_piomap)
-	    pciio_piomap_free(pciio_piomap);
-	return ENOMEM;			/* "unable to get memory resources */
-    }
-#ifdef LATER
-    map->uthread = curuthread;
-#endif
-    map->handle = v_gethandle(vt);
-    map->uvaddr = v_getaddr(vt);
-    map->map = pciio_piomap;
-    map->space = soft->iomem;
-    map->base = soft->base + off;
-    map->size = len;
-    pciba_map_push(soft->comm->bus, map);
-
-    /* Inform the system of the correct
-     * kvaddr corresponding to the thing
-     * that is being mapped.
-     */
-    v_mapphys(vt, kaddr, len);
-
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pciba_unmap(dev_t dev, vhandl_t *vt)
-{
-    devfs_handle_t         vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-    pciba_bus_t             bus = soft->comm->bus;
-    pciba_map_t             map;
-    __psunsigned_t          handle = v_gethandle(vt);
+	DPRINTF("PCI base at virtual address %lx\n", pci_va);
+	/* the __pa macro is intended for region 7 on IA64, so it
+	   doesn't work for region 6 */
+  	/* pci_pa = __pa(pci_va); */
+	/* should be replaced by __tpa or equivalent (preferably a
+	   generic equivalent) */
+	pci_pa = pci_va & ~0xe000000000000000ul;
+	DPRINTF("PCI base at physical address %lx\n", pci_pa);
 
-#if DEBUG_PCIBA
-    printf("pciba_unmap(%V,vt=%x)\n", dev, vt);
-#endif
+	/* there are various arch-specific versions of this function
+           defined in linux/drivers/char/mem.c, but it would be nice
+           if all architectures put it in pgtable.h.  it's defined
+           there for ia64.... */
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
-    /* If this is a userDMA buffer,
-     * make a note that it has been unmapped
-     * so it can be released.
-     */
-    if (soft->comm->dmap) {
-	pciba_dma_t             dmap;
-
-	pciba_soft_lock(soft);
-	for (dmap = soft->comm->dmap; dmap != NULL; dmap = dmap->next)
-	    if (handle == dmap->handle) {
-		dmap->handle = 0;
-		pciba_soft_unlock(soft);
-#if DEBUG_PCIBA
-		printf("pciba: unmapped dma at kaddr 0x%x via handle 0x%x\n",
-		       dmap->kaddr, handle);
-#endif
-		return 0;		/* found userPCI */
-	    }
-	pciba_soft_unlock(soft);
-    }
-    map = pciba_map_pop_hdl(bus, handle);
-    if (map == NULL)
-	return EINVAL;			/* no match */
+	vma->vm_flags |= VM_NONCACHED | VM_RESERVED | VM_IO;
 
-    if (map->map)
-	pciio_piomap_free(map->map);
-    DEL(map);
-
-    return (0);				/* all done OK */
+	return io_remap_page_range(vma->vm_start, pci_pa, 
+				   vma->vm_end-vma->vm_start,
+				   vma->vm_page_prot);
 }
 
-#if ULI
-void
-pciba_clearuli(struct uli *uli)
+
+static int
+mmap_kernel_address(struct vm_area_struct * vma, void * kernel_va)
 {
-    pciio_intr_t            intr = (pciio_intr_t) uli->teardownarg1;
+	unsigned long kernel_pa;
 
-#if DEBUG_PCIBA
-    printf("pciba_clearuli(0x%x)\n", uli);
-#endif
+	TRACE();
 
-    pciio_intr_disconnect(intr);
-    pciio_intr_free(intr);
-    atomic_dec(&pciba_prevent_unload);
-}
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
 
-void
-pciba_intr(intr_arg_t arg)
-{
-    struct uli             *uli = (struct uli *) arg;
-    int                     ulinum = uli->index;
+	/* the size of the vma doesn't necessarily correspond to the
+           size specified in the mmap call.  So we can't really do any
+           kind of sanity check here.  This is a dangerous driver, and
+           it's very easy for a user process to kill the machine.  */
 
-    extern void frs_handle_uli(void);
+	DPRINTF("mapping virtual address %p\n", kernel_va);
+	kernel_pa = __pa(kernel_va);
+	DPRINTF("mapping physical address %lx\n", kernel_pa);
 
-    if (ulinum >= 0 && ulinum < MAX_ULIS) {
-	    uli_callup(ulinum);
+	vma->vm_flags |= VM_NONCACHED | VM_RESERVED | VM_IO;
 
-	    if (private.p_frs_flags)
-		    frs_handle_uli();
-    }
-}
-#endif
-#endif /* LATER - undef as we implement each routine */
+	return remap_page_range(vma->vm_start, kernel_pa, 
+				vma->vm_end-vma->vm_start,
+				vma->vm_page_prot);
+}	
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/pcibr.c linux/arch/ia64/sn/io/pcibr.c
--- linux.orig/arch/ia64/sn/io/pcibr.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/pcibr.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,9824 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifdef BRINGUP
-int NeedXbridgeSwap = 0;
-#endif
-
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/xtalk/xwidget.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/pci/pci_defs.h>
-#include <asm/sn/prio.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/xtalk/xbow.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/eeprom.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/sn_private.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/hubio.h>
-#include <asm/sn/sn1/hubio_next.h>
-#endif
-
-#ifdef __ia64
-#define rmallocmap atemapalloc
-#define rmfreemap atemapfree
-#define rmfree atefree
-#define rmalloc atealloc
-#endif
-
-#undef PCIBR_ATE_DEBUG
-#if defined(BRINGUP)
-#if 0
-#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */
-#endif
-#define PCI_DEBUG 1
-#define ATTACH_DEBUG 1
-#define PCIBR_SOFT_LIST 1
-#endif
-
-#ifndef	LOCAL
-#define	LOCAL		static
-#endif
-
-/*
- * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
- * appears that if the lucent part can get into a retry loop if it sees a
- * DAC on the bus during a pio read retry.  The loop is broken after about
- * 1ms, so we need to set up bridges holding this part to allow at least
- * 1ms for pio.
- */
-
-#define USS302_TIMEOUT_WAR
-
-#ifdef USS302_TIMEOUT_WAR
-#include <asm/sn/io.h>
-#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
-#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
-#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
-#define USS302_BRIDGE_TIMEOUT_HLD	4
-#endif
-
-#define PCIBR_LLP_CONTROL_WAR
-#if defined (PCIBR_LLP_CONTROL_WAR)
-int                     pcibr_llp_control_war_cnt;
-#endif				/* PCIBR_LLP_CONTROL_WAR */
-
-#define	NEWAf(ptr,n,f)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP))
-#define NEWA(ptr,n)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP))
-#define DELA(ptr,n)	(kfree(ptr))
-
-#define NEWf(ptr,f)	NEWAf(ptr,1,f)
-#define NEW(ptr)	NEWA(ptr,1)
-#define DEL(ptr)	DELA(ptr,1)
-
-int                     pcibr_devflag = D_MP;
-
-#ifdef LATER
-#define F(s,n)		{ 1l<<(s),-(s), n }
-
-struct reg_desc         bridge_int_status_desc[] =
-{
-    F(31, "MULTI_ERR"),
-    F(30, "PMU_ESIZE_EFAULT"),
-    F(29, "UNEXPECTED_RESP"),
-    F(28, "BAD_XRESP_PACKET"),
-    F(27, "BAD_XREQ_PACKET"),
-    F(26, "RESP_XTALK_ERROR"),
-    F(25, "REQ_XTALK_ERROR"),
-    F(24, "INVALID_ADDRESS"),
-    F(23, "UNSUPPORTED_XOP"),
-    F(22, "XREQ_FIFO_OFLOW"),
-    F(21, "LLP_REC_SNERROR"),
-    F(20, "LLP_REC_CBERROR"),
-    F(19, "LLP_RCTY"),
-    F(18, "LLP_TX_RETRY"),
-    F(17, "LLP_TCTY"),
-    F(16, "SSRAM_PERR"),
-    F(15, "PCI_ABORT"),
-    F(14, "PCI_PARITY"),
-    F(13, "PCI_SERR"),
-    F(12, "PCI_PERR"),
-    F(11, "PCI_MASTER_TOUT"),
-    F(10, "PCI_RETRY_CNT"),
-    F(9, "XREAD_REQ_TOUT"),
-    F(8, "GIO_BENABLE_ERR"),
-    F(7, "INT7"),
-    F(6, "INT6"),
-    F(5, "INT5"),
-    F(4, "INT4"),
-    F(3, "INT3"),
-    F(2, "INT2"),
-    F(1, "INT1"),
-    F(0, "INT0"),
-    {0}
-};
-
-struct reg_values       space_v[] =
-{
-    {PCIIO_SPACE_NONE, "none"},
-    {PCIIO_SPACE_ROM, "ROM"},
-    {PCIIO_SPACE_IO, "I/O"},
-    {PCIIO_SPACE_MEM, "MEM"},
-    {PCIIO_SPACE_MEM32, "MEM(32)"},
-    {PCIIO_SPACE_MEM64, "MEM(64)"},
-    {PCIIO_SPACE_CFG, "CFG"},
-    {PCIIO_SPACE_WIN(0), "WIN(0)"},
-    {PCIIO_SPACE_WIN(1), "WIN(1)"},
-    {PCIIO_SPACE_WIN(2), "WIN(2)"},
-    {PCIIO_SPACE_WIN(3), "WIN(3)"},
-    {PCIIO_SPACE_WIN(4), "WIN(4)"},
-    {PCIIO_SPACE_WIN(5), "WIN(5)"},
-    {PCIIO_SPACE_BAD, "BAD"},
-    {0}
-};
-
-struct reg_desc         space_desc[] =
-{
-    {0xFF, 0, "space", 0, space_v},
-    {0}
-};
-
-#if DEBUG
-#define	device_desc	device_bits
-LOCAL struct reg_desc   device_bits[] =
-{
-    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
-    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
-    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
-    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
-    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
-    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
-    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
-    {BRIDGE_DEV_RT, 0, "RT"},
-    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
-    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
-    {BRIDGE_DEV_PREF, 0, "PREF"},
-    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
-    {BRIDGE_DEV_COH, 0, "COH"},
-    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
-    {BRIDGE_DEV_GBR, 0, "GBR"},
-    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
-    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
-    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
-    {0}
-};
-#endif	/* DEBUG */
-
-#ifdef SUPPORT_PRINTING_R_FORMAT
-LOCAL struct reg_values xio_cmd_pactyp[] =
-{
-    {0x0, "RdReq"},
-    {0x1, "RdResp"},
-    {0x2, "WrReqWithResp"},
-    {0x3, "WrResp"},
-    {0x4, "WrReqNoResp"},
-    {0x5, "Reserved(5)"},
-    {0x6, "FetchAndOp"},
-    {0x7, "Reserved(7)"},
-    {0x8, "StoreAndOp"},
-    {0x9, "Reserved(9)"},
-    {0xa, "Reserved(a)"},
-    {0xb, "Reserved(b)"},
-    {0xc, "Reserved(c)"},
-    {0xd, "Reserved(d)"},
-    {0xe, "SpecialReq"},
-    {0xf, "SpecialResp"},
-    {0}
-};
-
-LOCAL struct reg_desc   xio_cmd_bits[] =
-{
-    {WIDGET_DIDN, -28, "DIDN", "%x"},
-    {WIDGET_SIDN, -24, "SIDN", "%x"},
-    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
-    {WIDGET_TNUM, -15, "TNUM", "%x"},
-    {WIDGET_COHERENT, 0, "COHERENT"},
-    {WIDGET_DS, 0, "DS"},
-    {WIDGET_GBR, 0, "GBR"},
-    {WIDGET_VBPM, 0, "VBPM"},
-    {WIDGET_ERROR, 0, "ERROR"},
-    {WIDGET_BARRIER, 0, "BARRIER"},
-    {0}
-};
-#endif	/* SUPPORT_PRINTING_R_FORMAT */
-
-#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUG
-LOCAL struct reg_desc   ate_bits[] =
-{
-    {0xFFFF000000000000ull, -48, "RMF", "%x"},
-    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
-     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
-    {0x0000000000000F00ull, -8, "port", "%x"},
-    {0x0000000000000010ull, 0, "Barrier"},
-    {0x0000000000000008ull, 0, "Prefetch"},
-    {0x0000000000000004ull, 0, "Precise"},
-    {0x0000000000000002ull, 0, "Coherent"},
-    {0x0000000000000001ull, 0, "Valid"},
-    {0}
-};
-#endif
-
-#if PCIBR_ATE_DEBUG
-LOCAL struct reg_values ssram_sizes[] =
-{
-    {BRIDGE_CTRL_SSRAM_512K, "512k"},
-    {BRIDGE_CTRL_SSRAM_128K, "128k"},
-    {BRIDGE_CTRL_SSRAM_64K, "64k"},
-    {BRIDGE_CTRL_SSRAM_1K, "1k"},
-    {0}
-};
-
-LOCAL struct reg_desc   control_bits[] =
-{
-    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
-    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
-    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
-    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
-    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
-    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
-    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
-    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
-    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
-    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
-    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
-    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
-    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
-    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
-    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
-    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
-    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},
-    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
-    {0}
-};
-#endif
-#endif	/* LATER */
-
-/* kbrick widgetnum-to-bus layout */
-int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
-        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
-        2,                                      /* 0x8          */
-        1,                                      /* 0x9          */
-        0, 0,                                   /* 0xa - 0xb    */
-        5,                                      /* 0xc          */
-        6,                                      /* 0xd          */
-        4,                                      /* 0xe          */
-        3,                                      /* 0xf          */
-};
-
-/*
- * Additional PIO spaces per slot are
- * recorded in this structure.
- */
-struct pciio_piospace_s {
-    pciio_piospace_t        next;	/* another space for this device */
-    char                    free;	/* 1 if free, 0 if in use               */
-    pciio_space_t           space;	/* Which space is in use                */
-    iopaddr_t               start;	/* Starting address of the PIO space    */
-    size_t                  count;	/* size of PIO space                    */
-};
-
-/* Use io spin locks. This ensures that all the PIO writes from a particular
- * CPU to a particular IO device are synched before the start of the next
- * set of PIO operations to the same device.
- */
-#define pcibr_lock(pcibr_soft)		io_splock(&pcibr_soft->bs_lock)
-#define pcibr_unlock(pcibr_soft,s)	io_spunlock(&pcibr_soft->bs_lock,s)
-
-#if PCIBR_SOFT_LIST
-typedef struct pcibr_list_s *pcibr_list_p;
-struct pcibr_list_s {
-    pcibr_list_p            bl_next;
-    pcibr_soft_t            bl_soft;
-    devfs_handle_t            bl_vhdl;
-};
-pcibr_list_p            pcibr_list = 0;
-#endif
-
-typedef volatile unsigned *cfg_p;
-typedef volatile bridgereg_t *reg_p;
-
-#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"
-
-#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)
-#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)
-
-#define PCIBR_VALID_SLOT(s)	(s < 8)
-
-#ifdef SN_XXX
-extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
-                                     hub_widget_flags_t flags);
-#endif
-extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
-
-/*
- * This is the file operation table for the pcibr driver.
- * As each of the functions are implemented, put the 
- * appropriate function name below.
- */
-struct file_operations pcibr_fops = {
-        owner:  THIS_MODULE,
-        llseek: NULL,
-        read: NULL,
-        write: NULL,
-        readdir: NULL,
-        poll: NULL,
-        ioctl: NULL,
-        mmap: NULL,
-        open: NULL,
-        flush: NULL,
-        release: NULL,
-        fsync: NULL,
-        fasync: NULL,
-        lock: NULL,
-        readv: NULL,
-        writev: NULL
-};
-
-extern devfs_handle_t hwgraph_root;
-extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);
-extern int cap_able(uint64_t x);
-extern uint64_t rmalloc(struct map *mp, size_t size);
-extern void rmfree(struct map *mp, size_t size, uint64_t a);
-extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
-extern long atoi(register char *p);
-extern void *swap_ptr(void **loc, void *new);
-extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
-extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);
-extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);
-extern struct map *rmallocmap(uint64_t mapsiz);
-extern void rmfreemap(struct map *mp);
-extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);
-extern int io_path_map_widget(devfs_handle_t vertex);
-
-
-
-/* =====================================================================
- *    Function Table of Contents
- *
- *      The order of functions in this file has stopped
- *      making much sense. We might want to take a look
- *      at it some time and bring back some sanity, or
- *      perhaps bust this file into smaller chunks.
- */
-
-LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);
-LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);
-LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
-LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
-LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
-LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
-
-LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
-
-int			pcibr_wrb_flush(devfs_handle_t);
-int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);
-int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
-int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
-void                    pcibr_rrb_flush(devfs_handle_t);
-
-LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
-void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
-
-LOCAL void              pcibr_clearwidint(bridge_t *);
-LOCAL void              pcibr_setwidint(xtalk_intr_t);
-LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);
-
-void                    pcibr_init(void);
-int                     pcibr_attach(devfs_handle_t);
-int			pcibr_detach(devfs_handle_t);
-int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);
-int                     pcibr_close(devfs_handle_t, int, int, cred_t *);
-int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
-int                     pcibr_unmap(devfs_handle_t, vhandl_t *);
-int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
-
-void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
-
-LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);
-LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);
-LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);
-
-LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);
-LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
-LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
-LOCAL iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-
-pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
-void                    pcibr_piomap_free(pcibr_piomap_t);
-caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
-void                    pcibr_piomap_done(pcibr_piomap_t);
-caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
-void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
-
-LOCAL iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
-LOCAL bridge_ate_t      pcibr_flags_to_ate(unsigned);
-
-pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
-void                    pcibr_dmamap_free(pcibr_dmamap_t);
-LOCAL bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
-LOCAL iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
-iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
-alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
-void                    pcibr_dmamap_done(pcibr_dmamap_t);
-cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
-iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
-alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
-void                    pcibr_dmamap_drain(pcibr_dmamap_t);
-void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
-void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
-iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
-
-static unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
-pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
-void                    pcibr_intr_free(pcibr_intr_t);
-LOCAL void              pcibr_setpciint(xtalk_intr_t);
-int                     pcibr_intr_connect(pcibr_intr_t, intr_func_t, intr_arg_t, void *);
-void                    pcibr_intr_disconnect(pcibr_intr_t);
-
-devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
-void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
-void                    pcibr_intr_func(intr_arg_t);
-
-LOCAL void              print_bridge_errcmd(uint32_t, char *);
-
-void                    pcibr_error_dump(pcibr_soft_t);
-uint32_t              pcibr_errintr_group(uint32_t);
-LOCAL void		pcibr_pioerr_check(pcibr_soft_t);
-LOCAL void              pcibr_error_intr_handler(intr_arg_t);
-
-LOCAL int               pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *);
-LOCAL void              pcibr_error_cleanup(pcibr_soft_t, int);
-void                    pcibr_device_disable(pcibr_soft_t, int);
-LOCAL int               pcibr_pioerror(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-LOCAL int               pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_error_devenable(devfs_handle_t, int);
-
-void                    pcibr_provider_startup(devfs_handle_t);
-void                    pcibr_provider_shutdown(devfs_handle_t);
-
-int                     pcibr_reset(devfs_handle_t);
-pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
-int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
-pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
-int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
-
-LOCAL cfg_p             pcibr_config_addr(devfs_handle_t, unsigned);
-uint64_t                pcibr_config_get(devfs_handle_t, unsigned, unsigned);
-LOCAL uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
-void                    pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
-LOCAL void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
-
-LOCAL pcibr_hints_t     pcibr_hints_get(devfs_handle_t, int);
-void                    pcibr_hints_fix_rrbs(devfs_handle_t);
-void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
-void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
-void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
-void                    pcibr_hints_handsoff(devfs_handle_t);
-void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
-
-LOCAL int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
-
-#ifdef LATER
-LOCAL int	        pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t,
-                                               pcibr_slot_info_resp_t);
-LOCAL void       	pcibr_slot_func_info_return(pcibr_info_h, int,
-                                                    pcibr_slot_func_info_resp_t);
-#endif	/* LATER */
-
-LOCAL int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
-LOCAL int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_call_device_attach(devfs_handle_t,
-						      pciio_slot_t, int);
-LOCAL int		pcibr_slot_call_device_detach(devfs_handle_t,
-						      pciio_slot_t, int);
-
-LOCAL int               pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
-LOCAL int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
-#ifdef LATER
-LOCAL int		pcibr_slot_query(devfs_handle_t, pcibr_slot_info_req_t);
-#endif
-
-/* =====================================================================
- *    RRB management
- */
-
-#define LSBIT(word)		((word) &~ ((word)-1))
-
-#define PCIBR_RRB_SLOT_VIRTUAL	8
-
-LOCAL void
-do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
-{
-    bridgereg_t             status;
-
-    /* bridge_lock must be held;
-     * this RRB must be disabled.
-     */
-
-    /* wait until RRB has no outstanduing XIO packets. */
-    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
-	;				/* XXX- beats on bridge. bad idea? */
-    }
-
-    /* if the RRB has data, drain it. */
-    if (status & BRIDGE_RRB_VALID(rrb)) {
-	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
-
-	/* wait until RRB is no longer valid. */
-	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
-	    ;				/* XXX- beats on bridge. bad idea? */
-	}
-    }
-}
-
-LOCAL void
-do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
-{
-    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
-    bridgereg_t             rrbv;
-    int                     shft = 4 * (rrbn >> 1);
-    unsigned                ebit = BRIDGE_RRB_EN << shft;
-
-    rrbv = *rrbp;
-    if (rrbv & ebit)
-	*rrbp = rrbv & ~ebit;
-
-    do_pcibr_rrb_clear(bridge, rrbn);
-
-    if (rrbv & ebit)
-	*rrbp = rrbv;
-}
-
-/*
- *    pcibr_rrb_count_valid: count how many RRBs are
- *      marked valid for the specified PCI slot on this
- *      bridge.
- *
- *      NOTE: The "slot" parameter for all pcibr_rrb
- *      management routines must include the "virtual"
- *      bit; when manageing both the normal and the
- *      virtual channel, separate calls to these
- *      routines must be made. To denote the virtual
- *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
- *      number.
- *
- *      IMPL NOTE: The obvious algorithm is to iterate
- *      through the RRB fields, incrementing a count if
- *      the RRB is valid and matches the slot. However,
- *      it is much simpler to use an algorithm derived
- *      from the "partitioned add" idea. First, XOR in a
- *      pattern such that the fields that match this
- *      slot come up "all ones" and all other fields
- *      have zeros in the mismatching bits. Then AND
- *      together the bits in the field, so we end up
- *      with one bit turned on for each field that
- *      matched. Now we need to count these bits. This
- *      can be done either with a series of shift/add
- *      instructions or by using "tmp % 15"; I expect
- *      that the cascaded shift/add will be faster.
- */
-
-LOCAL int
-do_pcibr_rrb_count_valid(bridge_t *bridge,
-			 pciio_slot_t slot)
-{
-    bridgereg_t             tmp;
-
-    tmp = bridge->b_rrb_map[slot & 1].reg;
-    tmp ^= 0x11111111 * (7 - slot / 2);
-    tmp &= (0xCCCCCCCC & tmp) >> 2;
-    tmp &= (0x22222222 & tmp) >> 1;
-    tmp += tmp >> 4;
-    tmp += tmp >> 8;
-    tmp += tmp >> 16;
-    return tmp & 15;
-}
-
-/*
- *    do_pcibr_rrb_count_avail: count how many RRBs are
- *      available to be allocated for the specified slot.
- *
- *      IMPL NOTE: similar to the above, except we are
- *      just counting how many fields have the valid bit
- *      turned off.
- */
-LOCAL int
-do_pcibr_rrb_count_avail(bridge_t *bridge,
-			 pciio_slot_t slot)
-{
-    bridgereg_t             tmp;
-
-    tmp = bridge->b_rrb_map[slot & 1].reg;
-    tmp = (0x88888888 & ~tmp) >> 3;
-    tmp += tmp >> 4;
-    tmp += tmp >> 8;
-    tmp += tmp >> 16;
-    return tmp & 15;
-}
-
-/*
- *    do_pcibr_rrb_alloc: allocate some additional RRBs
- *      for the specified slot. Returns -1 if there were
- *      insufficient free RRBs to satisfy the request,
- *      or 0 if the request was fulfilled.
- *
- *      Note that if a request can be partially filled,
- *      it will be, even if we return failure.
- *
- *      IMPL NOTE: again we avoid iterating across all
- *      the RRBs; instead, we form up a word containing
- *      one bit for each free RRB, then peel the bits
- *      off from the low end.
- */
-LOCAL int
-do_pcibr_rrb_alloc(bridge_t *bridge,
-		   pciio_slot_t slot,
-		   int more)
-{
-    int                     rv = 0;
-    bridgereg_t             reg, tmp, bit;
-
-    reg = bridge->b_rrb_map[slot & 1].reg;
-    tmp = (0x88888888 & ~reg) >> 3;
-    while (more-- > 0) {
-	bit = LSBIT(tmp);
-	if (!bit) {
-	    rv = -1;
-	    break;
-	}
-	tmp &= ~bit;
-	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
-    }
-    bridge->b_rrb_map[slot & 1].reg = reg;
-    return rv;
-}
-
-/*
- *    do_pcibr_rrb_free: release some of the RRBs that
- *      have been allocated for the specified
- *      slot. Returns zero for success, or negative if
- *      it was unable to free that many RRBs.
- *
- *      IMPL NOTE: We form up a bit for each RRB
- *      allocated to the slot, aligned with the VALID
- *      bitfield this time; then we peel bits off one at
- *      a time, releasing the corresponding RRB.
- */
-LOCAL int
-do_pcibr_rrb_free(bridge_t *bridge,
-		  pciio_slot_t slot,
-		  int less)
-{
-    int                     rv = 0;
-    bridgereg_t             reg, tmp, clr, bit;
-    int                     i;
-
-    clr = 0;
-    reg = bridge->b_rrb_map[slot & 1].reg;
-
-    /* This needs to be done otherwise the rrb's on the virtual channel
-     * for this slot won't be freed !!
-     */
-    tmp = reg & 0xbbbbbbbb;
-
-    tmp ^= (0x11111111 * (7 - slot / 2));
-    tmp &= (0x33333333 & tmp) << 2;
-    tmp &= (0x44444444 & tmp) << 1;
-    while (less-- > 0) {
-	bit = LSBIT(tmp);
-	if (!bit) {
-	    rv = -1;
-	    break;
-	}
-	tmp &= ~bit;
-	reg &= ~bit;
-	clr |= bit;
-    }
-    bridge->b_rrb_map[slot & 1].reg = reg;
-
-    for (i = 0; i < 8; i++)
-	if (clr & (8 << (4 * i)))
-	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
-
-    return rv;
-}
-
-LOCAL void
-do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
-		       int slot,
-		       int more_rrbs)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     got;
-
-    for (got = 0; got < more_rrbs; ++got) {
-	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
-	    pcibr_soft->bs_rrb_res[slot & 7]--;
-	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
-	    pcibr_soft->bs_rrb_avail[slot & 1]--;
-	else
-	    break;
-	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
-	    break;
-#if PCIBR_RRB_DEBUG
-	printk( "do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
-		slot & 7, slot & 8 ? "v" : "");
-#endif
-	pcibr_soft->bs_rrb_valid[slot]++;
-    }
-#if PCIBR_RRB_DEBUG
-    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
-	    pcibr_soft->bs_rrb_avail[0],
-	    pcibr_soft->bs_rrb_avail[1]);
-    for (slot = 0; slot < 8; ++slot)
-	printk("\t%d+%d+%d",
-		0xFFF & pcibr_soft->bs_rrb_valid[slot],
-		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-		pcibr_soft->bs_rrb_res[slot]);
-	printk("\n");
-#endif
-}
-
-/*
- * Device driver interface to flush the write buffers for a specified
- * device hanging off the bridge.
- */
-int
-pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    volatile bridgereg_t   *wrb_flush;
-
-    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
-    while (*wrb_flush);
-
-    return(0);
-}
-/*
- * Device driver interface to request RRBs for a specified device
- * hanging off a Bridge.  The driver requests the total number of
- * RRBs it would like for the normal channel (vchan0) and for the
- * "virtual channel" (vchan1).  The actual number allocated to each
- * channel is returned.
- *
- * If we cannot allocate at least one RRB to a channel that needs
- * at least one, return -1 (failure).  Otherwise, satisfy the request
- * as best we can and return 0.
- */
-int
-pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
-		int *count_vchan0,
-		int *count_vchan1)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     desired_vchan0;
-    int                     desired_vchan1;
-    int                     orig_vchan0;
-    int                     orig_vchan1;
-    int                     delta_vchan0;
-    int                     delta_vchan1;
-    int                     final_vchan0;
-    int                     final_vchan1;
-    int                     avail_rrbs;
-    unsigned long           s;
-    int                     error;
-
-    /*
-     * TBD: temper request with admin info about RRB allocation,
-     * and according to demand from other devices on this Bridge.
-     *
-     * One way of doing this would be to allocate two RRBs
-     * for each device on the bus, before any drivers start
-     * asking for extras. This has the weakness that one
-     * driver might not give back an "extra" RRB until after
-     * another driver has already failed to get one that
-     * it wanted.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-
-    /* How many RRBs do we own? */
-    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
-    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
-
-    /* How many RRBs do we want? */
-    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
-    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
-
-    /* How many RRBs are free? */
-    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
-	+ pcibr_soft->bs_rrb_res[pciio_slot];
-
-    /* Figure desired deltas */
-    delta_vchan0 = desired_vchan0 - orig_vchan0;
-    delta_vchan1 = desired_vchan1 - orig_vchan1;
-
-    /* Trim back deltas to something
-     * that we can actually meet, by
-     * decreasing the ending allocation
-     * for whichever channel wants
-     * more RRBs. If both want the same
-     * number, cut the second channel.
-     * NOTE: do not change the allocation for
-     * a channel that was passed as NULL.
-     */
-    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
-	if (count_vchan0 &&
-	    (!count_vchan1 ||
-	     ((orig_vchan0 + delta_vchan0) >
-	      (orig_vchan1 + delta_vchan1))))
-	    delta_vchan0--;
-	else
-	    delta_vchan1--;
-    }
-
-    /* Figure final RRB allocations
-     */
-    final_vchan0 = orig_vchan0 + delta_vchan0;
-    final_vchan1 = orig_vchan1 + delta_vchan1;
-
-    /* If either channel wants RRBs but our actions
-     * would leave it with none, declare an error,
-     * but DO NOT change any RRB allocations.
-     */
-    if ((desired_vchan0 && !final_vchan0) ||
-	(desired_vchan1 && !final_vchan1)) {
-
-	error = -1;
-
-    } else {
-
-	/* Commit the allocations: free, then alloc.
-	 */
-	if (delta_vchan0 < 0)
-	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
-	if (delta_vchan1 < 0)
-	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
-
-	if (delta_vchan0 > 0)
-	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
-	if (delta_vchan1 > 0)
-	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
-
-	/* Return final values to caller.
-	 */
-	if (count_vchan0)
-	    *count_vchan0 = final_vchan0;
-	if (count_vchan1)
-	    *count_vchan1 = final_vchan1;
-
-	/* prevent automatic changes to this slot's RRBs
-	 */
-	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
-
-	/* Track the actual allocations, release
-	 * any further reservations, and update the
-	 * number of available RRBs.
-	 */
-
-	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
-	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
-	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
-	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
-	    + pcibr_soft->bs_rrb_res[pciio_slot]
-	    - delta_vchan0
-	    - delta_vchan1;
-	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
-
-#if PCIBR_RRB_DEBUG
-	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
-		pciio_slot, final_vchan0, final_vchan1,
-		pcibr_soft->bs_rrb_avail[0],
-		pcibr_soft->bs_rrb_avail[1]);
-	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
-	    printk("\t%d+%d+%d",
-		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
-		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
-		    pcibr_soft->bs_rrb_res[pciio_slot]);
-	printk("\n");
-#endif
-
-	error = 0;
-    }
-
-    pcibr_unlock(pcibr_soft, s);
-    return error;
-}
-
-/*
- * Device driver interface to check the current state
- * of the RRB allocations.
- *
- *   pconn_vhdl is your PCI connection point (specifies which
- *      PCI bus and which slot).
- *
- *   count_vchan0 points to where to return the number of RRBs
- *      assigned to the primary DMA channel, used by all DMA
- *      that does not explicitly ask for the alternate virtual
- *      channel.
- *
- *   count_vchan1 points to where to return the number of RRBs
- *      assigned to the secondary DMA channel, used when
- *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
- *
- *   count_reserved points to where to return the number of RRBs
- *      that have been automatically reserved for your device at
- *      startup, but which have not been assigned to a
- *      channel. RRBs must be assigned to a channel to be used;
- *      this can be done either with an explicit pcibr_rrb_alloc
- *      call, or automatically by the infrastructure when a DMA
- *      translation is constructed. Any call to pcibr_rrb_alloc
- *      will release any unassigned reserved RRBs back to the
- *      free pool.
- *
- *   count_pool points to where to return the number of RRBs
- *      that are currently unassigned and unreserved. This
- *      number can (and will) change as other drivers make calls
- *      to pcibr_rrb_alloc, or automatically allocate RRBs for
- *      DMA beyond their initial reservation.
- *
- * NULL may be passed for any of the return value pointers
- * the caller is not interested in.
- *
- * The return value is "0" if all went well, or "-1" if
- * there is a problem. Additionally, if the wrong vertex
- * is passed in, one of the subsidiary support functions
- * could panic with a "bad pciio fingerprint."
- */
-
-int
-pcibr_rrb_check(devfs_handle_t pconn_vhdl,
-		int *count_vchan0,
-		int *count_vchan1,
-		int *count_reserved,
-		int *count_pool)
-{
-    pciio_info_t            pciio_info;
-    pciio_slot_t            pciio_slot;
-    pcibr_soft_t            pcibr_soft;
-    unsigned long           s;
-    int                     error = -1;
-
-    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
-	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
-	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
-
-	s = pcibr_lock(pcibr_soft);
-
-	if (count_vchan0)
-	    *count_vchan0 =
-		pcibr_soft->bs_rrb_valid[pciio_slot];
-
-	if (count_vchan1)
-	    *count_vchan1 =
-		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
-
-	if (count_reserved)
-	    *count_reserved =
-		pcibr_soft->bs_rrb_res[pciio_slot];
-
-	if (count_pool)
-	    *count_pool =
-		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
-
-	error = 0;
-
-	pcibr_unlock(pcibr_soft, s);
-    }
-    return error;
-}
-
-/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
- * requested for each of the devies.  The evn_odd argument indicates whether
- * allcoation for the odd or even rrbs is requested and next group of four pairse
- * are the amount to assign to each device (they should sum to <= 8) and
- * whether to set the viritual bit for that device (1 indictaes yes, 0 indicates no)
- * the devices in order are either 0, 2, 4, 6 or 1, 3, 5, 7
- * if even_odd is even we alloc even rrbs else we allocate odd rrbs
- * returns 0 if no errors else returns -1
- */
-
-int
-pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
-		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
-		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
-{
-    devfs_handle_t            pcibr_vhdl;
-    pcibr_soft_t            pcibr_soft = NULL;
-    bridge_t               *bridge = NULL;
-
-    uint32_t              rrb_setting = 0;
-    int                     rrb_shift = 7;
-    uint32_t              cur_rrb;
-    int                     dev_rrbs[4];
-    int                     virt[4];
-    int                     i, j;
-    unsigned long           s;
-
-    if (GRAPH_SUCCESS ==
-	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
-	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-	if (pcibr_soft)
-	    bridge = pcibr_soft->bs_base;
-	hwgraph_vertex_unref(pcibr_vhdl);
-    }
-    if (bridge == NULL)
-	bridge = (bridge_t *) xtalk_piotrans_addr
-	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
-
-    even_odd &= 1;
-
-    dev_rrbs[0] = dev_1_rrbs;
-    dev_rrbs[1] = dev_2_rrbs;
-    dev_rrbs[2] = dev_3_rrbs;
-    dev_rrbs[3] = dev_4_rrbs;
-
-    virt[0] = virt1;
-    virt[1] = virt2;
-    virt[2] = virt3;
-    virt[3] = virt4;
-
-    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
-	return -1;
-    }
-    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
-	return -1;
-    }
-    /* walk through rrbs */
-    for (i = 0; i < 4; i++) {
-	if (virt[i]) {
-	    cur_rrb = i | 0xc;
-	    cur_rrb = cur_rrb << (rrb_shift * 4);
-	    rrb_shift--;
-	    rrb_setting = rrb_setting | cur_rrb;
-	    dev_rrbs[i] = dev_rrbs[i] - 1;
-	}
-	for (j = 0; j < dev_rrbs[i]; j++) {
-	    cur_rrb = i | 0x8;
-	    cur_rrb = cur_rrb << (rrb_shift * 4);
-	    rrb_shift--;
-	    rrb_setting = rrb_setting | cur_rrb;
-	}
-    }
-
-    if (pcibr_soft)
-	s = pcibr_lock(pcibr_soft);
-
-    bridge->b_rrb_map[even_odd].reg = rrb_setting;
-
-    if (pcibr_soft) {
-
-	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
-
-	/* since we've "FIXED" the allocations
-	 * for these slots, we probably can dispense
-	 * with tracking avail/res/valid data, but
-	 * keeping it up to date helps debugging.
-	 */
-
-	pcibr_soft->bs_rrb_avail[even_odd] =
-	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
-
-	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
-
-	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
-	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
-	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
-	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
-
-	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
-	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
-	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
-	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
-
-	pcibr_unlock(pcibr_soft, s);
-    }
-    return 0;
-}
-
-/*
- *    pcibr_rrb_flush: chase down all the RRBs assigned
- *      to the specified connection point, and flush
- *      them.
- */
-void
-pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned long           s;
-    reg_p                   rrbp;
-    unsigned                rrbm;
-    int                     i;
-    int                     rrbn;
-    unsigned                sval;
-    unsigned                mask;
-
-    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
-    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
-    rrbn = pciio_slot & 1;
-    rrbp = &bridge->b_rrb_map[rrbn].reg;
-
-    s = pcibr_lock(pcibr_soft);
-    rrbm = *rrbp;
-    for (i = 0; i < 8; ++i) {
-	if ((rrbm & mask) == sval)
-	    do_pcibr_rrb_flush(bridge, rrbn);
-	rrbm >>= 4;
-	rrbn += 2;
-    }
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/* =====================================================================
- *    Device(x) register management
- */
-
-/* pcibr_try_set_device: attempt to modify Device(x)
- * for the specified slot on the specified bridge
- * as requested in flags, limited to the specified
- * bits. Returns which BRIDGE bits were in conflict,
- * or ZERO if everything went OK.
- *
- * Caller MUST hold pcibr_lock when calling this function.
- */
-LOCAL int
-pcibr_try_set_device(pcibr_soft_t pcibr_soft,
-		     pciio_slot_t slot,
-		     unsigned flags,
-		     bridgereg_t mask)
-{
-    bridge_t               *bridge;
-    pcibr_soft_slot_t       slotp;
-    bridgereg_t             old;
-    bridgereg_t             new;
-    bridgereg_t             chg;
-    bridgereg_t             bad;
-    bridgereg_t             badpmu;
-    bridgereg_t             badd32;
-    bridgereg_t             badd64;
-    bridgereg_t             fix;
-    unsigned long           s;
-    bridgereg_t             xmask;
-
-    xmask = mask;
-    if (pcibr_soft->bs_xbridge) {
-    	if (mask == BRIDGE_DEV_PMU_BITS)
-		xmask = XBRIDGE_DEV_PMU_BITS;
-	if (mask == BRIDGE_DEV_D64_BITS)
-		xmask = XBRIDGE_DEV_D64_BITS;
-    }
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    s = pcibr_lock(pcibr_soft);
-
-    bridge = pcibr_soft->bs_base;
-
-    old = slotp->bss_device;
-
-    /* figure out what the desired
-     * Device(x) bits are based on
-     * the flags specified.
-     */
-
-    new = old;
-
-    /* Currently, we inherit anything that
-     * the new caller has not specified in
-     * one way or another, unless we take
-     * action here to not inherit.
-     *
-     * This is needed for the "swap" stuff,
-     * since it could have been set via
-     * pcibr_endian_set -- altho note that
-     * any explicit PCIBR_BYTE_STREAM or
-     * PCIBR_WORD_VALUES will freely override
-     * the effect of that call (and vice
-     * versa, no protection either way).
-     *
-     * I want to get rid of pcibr_endian_set
-     * in favor of tracking DMA endianness
-     * using the flags specified when DMA
-     * channels are created.
-     */
-
-#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
-#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
-
-    /* Do not use Barrier, Write Gather,
-     * or Prefetch unless asked.
-     * Leave everything else as it
-     * was from the last time.
-     */
-    new = new
-	& ~BRIDGE_DEV_BARRIER
-	& ~BRIDGE_DEV_WRGA_BITS
-	& ~BRIDGE_DEV_PREF
-	;
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {
-	new = (new
-            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
-            | BRIDGE_DEV_PREF;          /* prefetch on */
-
-    }
-    if (flags & PCIIO_DMA_CMD) {
-        new = ((new
-            & ~BRIDGE_DEV_PREF)         /* prefetch off */
-            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
-            | BRIDGE_DEV_BARRIER;       /* barrier on */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_WRITE_GATHER)
-	new |= BRIDGE_DEV_WRGA_BITS;
-    if (flags & PCIIO_NOWRITE_GATHER)
-	new &= ~BRIDGE_DEV_WRGA_BITS;
-
-    if (flags & PCIIO_PREFETCH)
-	new |= BRIDGE_DEV_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	new &= ~BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_WRITE_GATHER)
-	new |= BRIDGE_DEV_WRGA_BITS;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	new &= ~BRIDGE_DEV_WRGA_BITS;
-
-    if (flags & PCIIO_BYTE_STREAM)
-	new |= (pcibr_soft->bs_xbridge) ? 
-			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
-    if (flags & PCIIO_WORD_VALUES)
-	new &= (pcibr_soft->bs_xbridge) ? 
-			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_PREFETCH)
-	new |= BRIDGE_DEV_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	new &= ~BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	new |= BRIDGE_DEV_PRECISE;
-    if (flags & PCIBR_NOPRECISE)
-	new &= ~BRIDGE_DEV_PRECISE;
-
-    if (flags & PCIBR_BARRIER)
-	new |= BRIDGE_DEV_BARRIER;
-    if (flags & PCIBR_NOBARRIER)
-	new &= ~BRIDGE_DEV_BARRIER;
-
-    if (flags & PCIBR_64BIT)
-	new |= BRIDGE_DEV_DEV_SIZE;
-    if (flags & PCIBR_NO64BIT)
-	new &= ~BRIDGE_DEV_DEV_SIZE;
-
-    chg = old ^ new;				/* what are we changing, */
-    chg &= xmask;				/* of the interesting bits */
-
-    if (chg) {
-
-	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
-	if (pcibr_soft->bs_xbridge) {
-		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
-	} else {
-		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
-	}
-	bad = badpmu | badd32 | badd64;
-
-	if (bad) {
-
-	    /* some conflicts can be resolved by
-	     * forcing the bit on. this may cause
-	     * some performance degredation in
-	     * the stream(s) that want the bit off,
-	     * but the alternative is not allowing
-	     * the new stream at all.
-	     */
-            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
-                             BRIDGE_DEV_BARRIER)) ){
-		bad &= ~fix;
-		/* don't change these bits if
-		 * they are already set in "old"
-		 */
-		chg &= ~(fix & old);
-	    }
-	    /* some conflicts can be resolved by
-	     * forcing the bit off. this may cause
-	     * some performance degredation in
-	     * the stream(s) that want the bit on,
-	     * but the alternative is not allowing
-	     * the new stream at all.
-	     */
-	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
-			     BRIDGE_DEV_PREF)) ) {
-		bad &= ~fix;
-		/* don't change these bits if
-		 * we wanted to turn them on.
-		 */
-		chg &= ~(fix & new);
-	    }
-	    /* conflicts in other bits mean
-	     * we can not establish this DMA
-	     * channel while the other(s) are
-	     * still present.
-	     */
-	    if (bad) {
-		pcibr_unlock(pcibr_soft, s);
-#if (DEBUG && PCIBR_DEV_DEBUG)
-		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
-#endif
-		return bad;
-	    }
-	}
-    }
-    if (mask == BRIDGE_DEV_PMU_BITS)
-	slotp->bss_pmu_uctr++;
-    if (mask == BRIDGE_DEV_D32_BITS)
-	slotp->bss_d32_uctr++;
-    if (mask == BRIDGE_DEV_D64_BITS)
-	slotp->bss_d64_uctr++;
-
-    /* the value we want to write is the
-     * original value, with the bits for
-     * our selected changes flipped, and
-     * with any disabled features turned off.
-     */
-    new = old ^ chg;			/* only change what we want to change */
-
-    if (slotp->bss_device == new) {
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-    bridge->b_device[slot].reg = new;
-    slotp->bss_device = new;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-#if DEBUG && PCIBR_DEV_DEBUG
-    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
-#endif
-
-    return 0;
-}
-
-void
-pcibr_release_device(pcibr_soft_t pcibr_soft,
-		     pciio_slot_t slot,
-		     bridgereg_t mask)
-{
-    pcibr_soft_slot_t       slotp;
-    unsigned long           s;
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    s = pcibr_lock(pcibr_soft);
-
-    if (mask == BRIDGE_DEV_PMU_BITS)
-	slotp->bss_pmu_uctr--;
-    if (mask == BRIDGE_DEV_D32_BITS)
-	slotp->bss_d32_uctr--;
-    if (mask == BRIDGE_DEV_D64_BITS)
-	slotp->bss_d64_uctr--;
-
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/*
- * flush write gather buffer for slot
- */
-LOCAL void
-pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
-              pciio_slot_t slot)
-{
-    bridge_t               *bridge;
-    unsigned long          s;
-    volatile uint32_t     wrf;
-    s = pcibr_lock(pcibr_soft);
-    bridge = pcibr_soft->bs_base;
-    wrf = bridge->b_wr_req_buf[slot].reg;
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/* =====================================================================
- *    Bridge (pcibr) "Device Driver" entry points
- */
-
-/*
- * pcibr_probe_slot: read a config space word
- * while trapping any errors; reutrn zero if
- * all went OK, or nonzero if there was an error.
- * The value read, if any, is passed back
- * through the valp parameter.
- */
-LOCAL int
-pcibr_probe_slot(bridge_t *bridge,
-		 cfg_p cfg,
-		 unsigned *valp)
-{
-    int                     rv;
-    bridgereg_t             old_enable, new_enable;
-    int badaddr_val(volatile void *, int, volatile void *);
-
-
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-
-    bridge->b_int_enable = new_enable;
-
-	/*
-	 * The xbridge doesn't clear b_err_int_view unless
-	 * multi-err is cleared...
-	 */
-	if (is_xbridge(bridge))
-	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
-		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
-	    }
-
-    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
-	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
-	(void) bridge->b_wid_tflush;	/* flushbus */
-    }
-    rv = badaddr_val((void *) cfg, 4, valp);
-
-	/*
-	 * The xbridge doesn't set master timeout in b_int_status
-	 * here.  Fortunately it's in error_interrupt_view.
-	 */
-	if (is_xbridge(bridge))
-	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
-		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
-		rv = 1;		/* unoccupied slot */
-	    }
-
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    return rv;
-}
-
-/*
- *    pcibr_init: called once during system startup or
- *      when a loadable driver is loaded.
- *
- *      The driver_register function should normally
- *      be in _reg, not _init.  But the pcibr driver is
- *      required by devinit before the _reg routines
- *      are called, so this is an exception.
- */
-void
-pcibr_init(void)
-{
-#if DEBUG && ATTACH_DEBUG
-    printk("pcibr_init\n");
-#endif
-
-    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
-			    XBRIDGE_WIDGET_MFGR_NUM,
-			    "pcibr_",
-			    0);
-    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
-			    BRIDGE_WIDGET_MFGR_NUM,
-			    "pcibr_",
-			    0);
-}
-
-/*
- * open/close mmap/munmap interface would be used by processes
- * that plan to map the PCI bridge, and muck around with the
- * registers. This is dangerous to do, and will be allowed
- * to a select brand of programs. Typically these are
- * diagnostics programs, or some user level commands we may
- * write to do some weird things.
- * To start with expect them to have root priveleges.
- * We will ask for more later.
- */
-/* ARGSUSED */
-int
-pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
-{
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
-{
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
-{
-    int                     error;
-    devfs_handle_t            vhdl = dev_to_vhdl(dev);
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    ASSERT(pcibr_soft);
-    len = ctob(btoc(len));		/* Make len page aligned */
-    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
-
-    /*
-     * If the offset being mapped corresponds to the flash prom
-     * base, and if the mapping succeeds, and if the user
-     * has requested the protections to be WRITE, enable the
-     * flash prom to be written.
-     *
-     * XXX- deprecate this in favor of using the
-     * real flash driver ...
-     */
-    if (!error &&
-	((off == BRIDGE_EXTERNAL_FLASH) ||
-	 (len > BRIDGE_EXTERNAL_FLASH))) {
-	int                     s;
-
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	s = splhi();
-	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(s);
-    }
-    return error;
-}
-
-/*ARGSUSED */
-int
-pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
-{
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    /*
-     * If flashprom write was enabled, disable it, as
-     * this is the last unmap.
-     */
-    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
-	int                     s;
-
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	s = splhi();
-	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(s);
-    }
-    return 0;
-}
-
-/* This is special case code used by grio. There are plans to make
- * this a bit more general in the future, but till then this should
- * be sufficient.
- */
-pciio_slot_t
-pcibr_device_slot_get(devfs_handle_t dev_vhdl)
-{
-    char                    devname[MAXDEVNAME];
-    devfs_handle_t            tdev;
-    pciio_info_t            pciio_info;
-    pciio_slot_t            slot = PCIIO_SLOT_NONE;
-
-    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
-
-    /* run back along the canonical path
-     * until we find a PCI connection point.
-     */
-    tdev = hwgraph_connectpt_get(dev_vhdl);
-    while (tdev != GRAPH_VERTEX_NONE) {
-	pciio_info = pciio_info_chk(tdev);
-	if (pciio_info) {
-	    slot = pciio_info_slot_get(pciio_info);
-	    break;
-	}
-	hwgraph_vertex_unref(tdev);
-	tdev = hwgraph_connectpt_get(tdev);
-    }
-    hwgraph_vertex_unref(tdev);
-
-    return slot;
-}
-
-/*==========================================================================
- *	BRIDGE PCI SLOT RELATED IOCTLs
- */
-char *pci_space_name[] = {"NONE", 
-			  "ROM",
-			  "IO",
-			  "",
-			  "MEM",
-			  "MEM32",
-			  "MEM64",
-			  "CFG",
-			  "WIN0",
-			  "WIN1",
-			  "WIN2",
-			  "WIN3",
-			  "WIN4",
-			  "WIN5",
-			  "",
-			  "BAD"};
-
-
-#ifdef LATER
-
-void
-pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
-                            int func,
-                            pcibr_slot_func_info_resp_t funcp)
-{
-    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
-    int                          win;
-
-    funcp->resp_f_status = 0;
-
-    if (!pcibr_info) {
-        return;
-    }
-
-    funcp->resp_f_status |= FUNC_IS_VALID;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
-#else
-    sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex);
-#endif
-
-    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
-        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
-    }
-
-    funcp->resp_f_bus = pcibr_info->f_bus;
-    funcp->resp_f_slot = pcibr_info->f_slot;
-    funcp->resp_f_func = pcibr_info->f_func;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
-#else
-    sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master);
-#endif
-    funcp->resp_f_pops = pcibr_info->f_pops;
-    funcp->resp_f_efunc = pcibr_info->f_efunc;
-    funcp->resp_f_einfo = pcibr_info->f_einfo;
-
-    funcp->resp_f_vendor = pcibr_info->f_vendor;
-    funcp->resp_f_device = pcibr_info->f_device;
-
-    for(win = 0 ; win < 6 ; win++) {
-        funcp->resp_f_window[win].resp_w_base =
-                                  pcibr_info->f_window[win].w_base;
-        funcp->resp_f_window[win].resp_w_size =
-                                  pcibr_info->f_window[win].w_size;
-        sprintf(funcp->resp_f_window[win].resp_w_space,
-                "%s",
-                pci_space_name[pcibr_info->f_window[win].w_space]);
-    }
-
-    funcp->resp_f_rbase = pcibr_info->f_rbase;
-    funcp->resp_f_rsize = pcibr_info->f_rsize;
-
-    for (win = 0 ; win < 4; win++) {
-        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
-    }
-
-    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
-
-}
-
-int
-pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
-                       pciio_slot_t             slot,
-                       pcibr_slot_info_resp_t   respp)
-{
-    pcibr_soft_slot_t            pss;
-    int                          func;
-    bridge_t                    *bridge = pcibr_soft->bs_base;
-    reg_p                        b_respp;
-    pcibr_slot_info_resp_t       slotp;
-    pcibr_slot_func_info_resp_t  funcp;
-
-    slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP);
-    if (slotp == NULL) {
-        return(ENOMEM);
-    }
-
-    pss = &pcibr_soft->bs_slot[slot];
-    
-    printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot);
-
-    slotp->resp_has_host = pss->has_host;
-    slotp->resp_host_slot = pss->host_slot;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
-#else
-    sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn);
-#endif
-    slotp->resp_slot_status = pss->slot_status;
-    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
-
-    if (is_sys_critical_vertex(pss->slot_conn)) {
-        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
-    }
-
-    slotp->resp_bss_ninfo = pss->bss_ninfo;
-
-    for (func = 0; func < pss->bss_ninfo; func++) {
-        funcp = &(slotp->resp_func[func]);
-        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
-    }
-
-    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
-            pci_space_name[pss->bss_devio.bssd_space]);
-    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
-    slotp->resp_bss_device = pss->bss_device;
-
-    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
-    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
-    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
-
-    slotp->resp_bss_d64_base = pss->bss_d64_base;
-    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
-    slotp->resp_bss_d32_base = pss->bss_d32_base;
-    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
-
-    slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active);
-
-    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
-    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
-
-    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
-    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
-                                                      PCIBR_RRB_SLOT_VIRTUAL];
-    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
-
-    if (slot & 1) {
-        b_respp = &bridge->b_odd_resp;
-    } else {
-        b_respp = &bridge->b_even_resp;
-    }
-
-    slotp->resp_b_resp = *b_respp;
-
-    slotp->resp_b_int_device = bridge->b_int_device;
-    slotp->resp_b_int_enable = bridge->b_int_enable;
-    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
-
-    if (COPYOUT(slotp, respp, sizeof(*respp))) {
-        return(EFAULT);
-    }
-
-    kmem_free(slotp, sizeof(*slotp));
-
-    return(0);
-}
-
-/*
- * pcibr_slot_query
- *	Return information about the PCI slot maintained by the infrastructure.
- *	Information is requested in the request structure.
- *
- *      Information returned in the response structure:
- *		Slot hwgraph name
- *		Vendor/Device info
- *		Base register info
- *		Interrupt mapping from device pins to the bridge pins
- *		Devio register
- *		Software RRB info
- *		RRB register info
- *		Host/Gues info
- *		PCI Bus #,slot #, function #
- *		Slot provider hwgraph name
- *		Provider Functions
- *		Error handler
- *		DMA mapping usage counters
- *		DMA direct translation info
- *		External SSRAM workaround info
- */
-int
-pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    pciio_slot_t            slot = reqp->req_slot;
-    pciio_slot_t            tmp_slot;
-    pcibr_slot_info_resp_t  respp = (pcibr_slot_info_resp_t) reqp->req_respp;
-    int                     size = reqp->req_size;
-    int                     error;
-
-    /* Make sure that we are dealing with a bridge device vertex */
-    if (!pcibr_soft) {
-        return(EINVAL);
-    }
-
-    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
-    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
-        return(EINVAL);
-    }
-
-#ifdef LATER
-    /* Do not allow a query of a slot in a shoehorn */
-    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
-       return(EPERM);
-    }
-#endif
-
-    /* Return information for the requested PCI slot */
-    if (slot != PCIIO_SLOT_NONE) {
-        if (size < sizeof(*respp)) {
-            return(EINVAL);
-        }
-
-        /* Acquire read access to the slot */
-        mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO);
-
-        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
-
-        /* Release the slot lock */
-        mrunlock(pcibr_soft->bs_slot[slot].slot_lock);
-
-        return(error);
-    }
-
-    /* Return information for all the slots */
-    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
-
-        if (size < sizeof(*respp)) {
-            return(EINVAL);
-        }
-
-        /* Acquire read access to the slot */
-        mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO);
-
-        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
-
-        /* Release the slot lock */
-        mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock);
-
-        if (error) {
-            return(error);
-        }
-
-        ++respp;
-        size -= sizeof(*respp);
-    }
-
-    return(error);
-}
-#endif	/* LATER */
-
-
-/*ARGSUSED */
-int
-pcibr_ioctl(devfs_handle_t dev,
-	    int cmd,
-	    void *arg,
-	    int flag,
-	    struct cred *cr,
-	    int *rvalp)
-{
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
-#ifdef LATER
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-#endif
-    int                     error = 0;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    switch (cmd) {
-#ifdef LATER
-    case GIOCSETBW:
-	{
-	    grio_ioctl_info_t       info;
-	    pciio_slot_t            slot = 0;
-
-	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
-		error = EFAULT;
-		break;
-	    }
-#ifdef GRIO_DEBUG
-	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
-		    info.prev_vhdl, info.reqbw);
-#endif				/* GRIO_DEBUG */
-
-	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
-		PCIIO_SLOT_NONE) {
-		error = EIO;
-		break;
-	    }
-	    if (info.reqbw)
-		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
-	    break;
-	}
-
-    case GIOCRELEASEBW:
-	{
-	    grio_ioctl_info_t       info;
-	    pciio_slot_t            slot = 0;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
-		error = EFAULT;
-		break;
-	    }
-#ifdef GRIO_DEBUG
-	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
-		    info.prev_vhdl, info.reqbw);
-#endif				/* GRIO_DEBUG */
-
-	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
-		PCIIO_SLOT_NONE) {
-		error = EIO;
-		break;
-	    }
-	    if (info.reqbw)
-		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
-	    break;
-	}
-
-    case PCIBR_SLOT_POWERUP:
-	{
-	    pciio_slot_t	slot;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-	    slot = (pciio_slot_t)(uint64_t)arg;
-	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
-	    break;
-	}
-    case PCIBR_SLOT_SHUTDOWN:
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-	    slot = (pciio_slot_t)(uint64_t)arg;
-	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
-	    break;
-	}
-    case PCIBR_SLOT_QUERY:
-	{
-	    struct pcibr_slot_info_req_s        req;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-            if (COPYIN(arg, &req, sizeof(req))) {
-                error = EFAULT;
-                break;
-            }
-
-            error = pcibr_slot_query(pcibr_vhdl, &req);
-	    break;
-	}
-#endif	/* LATER */
-    default:
-	break;
-
-    }
-
-    return error;
-}
-
-void
-pcibr_freeblock_sub(iopaddr_t *free_basep,
-		    iopaddr_t *free_lastp,
-		    iopaddr_t base,
-		    size_t size)
-{
-    iopaddr_t               free_base = *free_basep;
-    iopaddr_t               free_last = *free_lastp;
-    iopaddr_t               last = base + size - 1;
-
-    if ((last < free_base) || (base > free_last));	/* free block outside arena */
-
-    else if ((base <= free_base) && (last >= free_last))
-	/* free block contains entire arena */
-	*free_basep = *free_lastp = 0;
-
-    else if (base <= free_base)
-	/* free block is head of arena */
-	*free_basep = last + 1;
-
-    else if (last >= free_last)
-	/* free block is tail of arena */
-	*free_lastp = base - 1;
-
-    /*
-     * We are left with two regions: the free area
-     * in the arena "below" the block, and the free
-     * area in the arena "above" the block. Keep
-     * the one that is bigger.
-     */
-
-    else if ((base - free_base) > (free_last - last))
-	*free_lastp = base - 1;		/* keep lower chunk */
-    else
-	*free_basep = last + 1;		/* keep upper chunk */
-}
-
-/* Convert from ssram_bits in control register to number of SSRAM entries */
-#define ATE_NUM_ENTRIES(n) _ate_info[n]
-
-/* Possible choices for number of ATE entries in Bridge's SSRAM */
-LOCAL int               _ate_info[] =
-{
-    0,					/* 0 entries */
-    8 * 1024,				/* 8K entries */
-    16 * 1024,				/* 16K entries */
-    64 * 1024				/* 64K entries */
-};
-
-#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
-#define ATE_PROBE_VALUE 0x0123456789abcdefULL
-
-/*
- * Determine the size of this bridge's external mapping SSRAM, and set
- * the control register appropriately to reflect this size, and initialize
- * the external SSRAM.
- */
-LOCAL int
-pcibr_init_ext_ate_ram(bridge_t *bridge)
-{
-    int                     largest_working_size = 0;
-    int                     num_entries, entry;
-    int                     i, j;
-    bridgereg_t             old_enable, new_enable;
-    int                     s;
-
-    /* Probe SSRAM to determine its size. */
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-    bridge->b_int_enable = new_enable;
-
-    for (i = 1; i < ATE_NUM_SIZES; i++) {
-	/* Try writing a value */
-	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
-
-	/* Guard against wrap */
-	for (j = 1; j < i; j++)
-	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
-
-	/* See if value was written */
-	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
-	    largest_working_size = i;
-    }
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    /*
-     * ensure that we write and read without any interruption.
-     * The read following the write is required for the Bridge war
-     */
-
-    s = splhi();
-    bridge->b_wid_control = (bridge->b_wid_control
-	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
-	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
-    bridge->b_wid_control;		/* inval addr bug war */
-    splx(s);
-
-    num_entries = ATE_NUM_ENTRIES(largest_working_size);
-
-#if PCIBR_ATE_DEBUG
-    if (num_entries)
-	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
-    else
-	printk("bridge at 0x%x: no externa9422l ATE RAM found\n", bridge);
-#endif
-
-    /* Initialize external mapping entries */
-    for (entry = 0; entry < num_entries; entry++)
-	bridge->b_ext_ate_ram[entry] = 0;
-
-    return (num_entries);
-}
-
-/*
- * Allocate "count" contiguous Bridge Address Translation Entries
- * on the specified bridge to be used for PCI to XTALK mappings.
- * Indices in rm map range from 1..num_entries.  Indicies returned
- * to caller range from 0..num_entries-1.
- *
- * Return the start index on success, -1 on failure.
- */
-LOCAL int
-pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
-{
-    int                     index = 0;
-
-    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
-/* printk("Colin: pcibr_ate_alloc - index %d count %d \n", index, count); */
-
-    if (!index && pcibr_soft->bs_ext_ate_map)
-	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
-
-    /* rmalloc manages resources in the 1..n
-     * range, with 0 being failure.
-     * pcibr_ate_alloc manages resources
-     * in the 0..n-1 range, with -1 being failure.
-     */
-    return index - 1;
-}
-
-LOCAL void
-pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
-/* Who says there's no such thing as a free meal? :-) */
-{
-    /* note the "+1" since rmalloc handles 1..n but
-     * we start counting ATEs at zero.
-     */
-/* printk("Colin: pcibr_ate_free - index %d count %d\n", index, count); */
-
-    rmfree((index < pcibr_soft->bs_int_ate_size)
-	   ? pcibr_soft->bs_int_ate_map
-	   : pcibr_soft->bs_ext_ate_map,
-	   count, index + 1);
-}
-
-LOCAL pcibr_info_t
-pcibr_info_get(devfs_handle_t vhdl)
-{
-    return (pcibr_info_t) pciio_info_get(vhdl);
-}
-
-pcibr_info_t
-pcibr_device_info_new(
-			 pcibr_soft_t pcibr_soft,
-			 pciio_slot_t slot,
-			 pciio_function_t rfunc,
-			 pciio_vendor_id_t vendor,
-			 pciio_device_id_t device)
-{
-    pcibr_info_t            pcibr_info;
-    pciio_function_t        func;
-    int                     ibit;
-
-    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
-
-    NEW(pcibr_info);
-    pciio_device_info_new(&pcibr_info->f_c,
-			  pcibr_soft->bs_vhdl,
-			  slot, rfunc,
-			  vendor, device);
-
-    if (slot != PCIIO_SLOT_NONE) {
-
-	/*
-	 * Currently favored mapping from PCI
-	 * slot number and INTA/B/C/D to Bridge
-	 * PCI Interrupt Bit Number:
-	 *
-	 *     SLOT     A B C D
-	 *      0       0 4 0 4
-	 *      1       1 5 1 5
-	 *      2       2 6 2 6
-	 *      3       3 7 3 7
-	 *      4       4 0 4 0
-	 *      5       5 1 5 1
-	 *      6       6 2 6 2
-	 *      7       7 3 7 3
-	 *
-	 * XXX- allow pcibr_hints to override default
-	 * XXX- allow ADMIN to override pcibr_hints
-	 */
-	for (ibit = 0; ibit < 4; ++ibit)
-	    pcibr_info->f_ibit[ibit] =
-		(slot + 4 * ibit) & 7;
-
-	/*
-	 * Record the info in the sparse func info space.
-	 */
-	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
-	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
-    }
-    return pcibr_info;
-}
-
-void
-pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    pcibr_info_t	pcibr_info;
-    pciio_function_t	func;
-    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
-    int			nfunc = slotp->bss_ninfo;
-
-
-    for (func = 0; func < nfunc; func++) {
-	pcibr_info = slotp->bss_infos[func];
-
-	if (!pcibr_info) 
-	    continue;
-
-	slotp->bss_infos[func] = 0;
-	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
-	pciio_device_info_free(&pcibr_info->f_c);
-	DEL(pcibr_info);
-    }
-
-    /* Clear the DEVIO(x) for this slot */
-    slotp->bss_devio.bssd_space = PCIIO_SPACE_NONE;
-    slotp->bss_devio.bssd_base = PCIBR_D32_BASE_UNSET;
-    slotp->bss_device  = 0;
-
-    
-    /* Reset the mapping usage counters */
-    slotp->bss_pmu_uctr = 0;
-    slotp->bss_d32_uctr = 0;
-    slotp->bss_d64_uctr = 0;
-
-    /* Clear the Direct translation info */
-    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
-    slotp->bss_d64_flags = 0;
-    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
-    slotp->bss_d32_flags = 0;
-
-    /* Clear out shadow info necessary for the external SSRAM workaround */
-    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
-    slotp->bss_cmd_pointer = 0;
-    slotp->bss_cmd_shadow = 0;
-
-}
-
-/* 
- * PCI_ADDR_SPACE_LIMITS_LOAD
- *	Gets the current values of 
- *		pci io base, 
- *		pci io last,
- *		pci low memory base,
- *		pci low memory last,
- *		pci high memory base,
- * 		pci high memory last
- */
-#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
-    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
-    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
-    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
-    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
-    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
-    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
-/*
- * PCI_ADDR_SPACE_LIMITS_STORE
- *	Sets the current values of
- *		pci io base, 
- *		pci io last,
- *		pci low memory base,
- *		pci low memory last,
- *		pci high memory base,
- * 		pci high memory last
- */
-#define PCI_ADDR_SPACE_LIMITS_STORE()			\
-    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
-    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
-    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
-    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
-    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
-    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
-
-#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
-    printf("+++++++++++++++++++++++\n"			\
-	   "IO base 0x%x last 0x%x\n"			\
-	   "SWIN base 0x%x last 0x%x\n"			\
-	   "MEM base 0x%x last 0x%x\n"			\
-	   "+++++++++++++++++++++++\n",			\
-	   pcibr_soft->bs_spinfo.pci_io_base,		\
-	   pcibr_soft->bs_spinfo.pci_io_last,		\
-	   pcibr_soft->bs_spinfo.pci_swin_base,		\
-	   pcibr_soft->bs_spinfo.pci_swin_last,		\
-	   pcibr_soft->bs_spinfo.pci_mem_base,		\
-	   pcibr_soft->bs_spinfo.pci_mem_last);
-
-/*
- * pcibr_slot_info_init
- *	Probe for this slot and see if it is populated.
- *	If it is populated initialize the generic PCI infrastructural
- * 	information associated with this particular PCI device.
- */
-int
-pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
-		     pciio_slot_t 	slot)
-{
-    pcibr_soft_t	    pcibr_soft;
-    pcibr_info_h	    pcibr_infoh;
-    pcibr_info_t	    pcibr_info;
-    bridge_t		   *bridge;
-    cfg_p                   cfgw;
-    unsigned                idword;
-    unsigned                pfail;
-    unsigned                idwords[8];
-    pciio_vendor_id_t       vendor;
-    pciio_device_id_t       device;
-    unsigned                htype;
-#if !defined(CONFIG_IA64_SGI_SN1)
-    int			    nbars;
-#endif
-    cfg_p                   wptr;
-    int                     win;
-    pciio_space_t           space;
-    iopaddr_t		    pci_io_fb,	pci_io_fl;
-    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
-    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
-    int			    nfunc;
-    pciio_function_t	    rfunc;
-    int			    func;
-    devfs_handle_t	    conn_vhdl;
-    pcibr_soft_slot_t	    slotp;
-    
-    /* Get the basic software information required to proceed */
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (!pcibr_soft)
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-    if (!PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
-     * is done by the host slot then we are done.
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	return(0);    
-    }
-
-    /* Check for a slot with any system critical functions */
-    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
-        return(EPERM);
-
-    /* Load the current values of allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_LOAD();
-    
-    /* Try to read the device-id/vendor-id from the config space */
-    cfgw = bridge->b_type0_cfg_dev[slot].l;
-
-    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
-	return(ENODEV);
-
-    slotp = &pcibr_soft->bs_slot[slot];
-    slotp->slot_status |= SLOT_POWER_UP;
-
-    vendor = 0xFFFF & idword;
-    /* If the vendor id is not valid then the slot is not populated
-     * and we are done.
-     */
-    if (vendor == 0xFFFF) 
-	return(ENODEV);			
-    
-    device = 0xFFFF & (idword >> 16);
-    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
-
-    nfunc = 1;
-    rfunc = PCIIO_FUNC_NONE;
-    pfail = 0;
-
-    /* NOTE: if a card claims to be multifunction
-     * but only responds to config space 0, treat
-     * it as a unifunction card.
-     */
-
-    if (htype & 0x80) {		/* MULTIFUNCTION */
-	for (func = 1; func < 8; ++func) {
-	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
-		pfail |= 1 << func;
-		continue;
-	    }
-	    vendor = 0xFFFF & idwords[func];
-	    if (vendor == 0xFFFF) {
-		pfail |= 1 << func;
-		continue;
-	    }
-	    nfunc = func + 1;
-	    rfunc = 0;
-	}
-	cfgw = bridge->b_type0_cfg_dev[slot].l;
-    }
-    NEWA(pcibr_infoh, nfunc);
-    
-    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
-    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
-
-    for (func = 0; func < nfunc; ++func) {
-	unsigned                cmd_reg;
-	
-	if (func) {
-	    if (pfail & (1 << func))
-		continue;
-	    
-	    idword = idwords[func];
-	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	    
-	    device = 0xFFFF & (idword >> 16);
-	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
-	    rfunc = func;
-	}
-	htype &= 0x7f;
-	if (htype != 0x00) {
-	    PRINT_WARNING("%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
-		    pcibr_soft->bs_name, slot, func, htype);
-#if defined(CONFIG_IA64_SGI_SN1)
-	    continue;
-#else
-	    nbars = 2;
-	} else {
-	    nbars = PCI_CFG_BASE_ADDRS;
-#endif
-	}
-#if DEBUG && ATTACH_DEBUG
-	PRINT_NOTICE( 
-		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
-		pcibr_soft->bs_name, slot, func, vendor, device);
-#endif	
-
-	pcibr_info = pcibr_device_info_new
-	    (pcibr_soft, slot, rfunc, vendor, device);
-	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
-	if (func == 0)
-	    slotp->slot_conn = conn_vhdl;
-
-	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
-	
-	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-
-#if defined(CONFIG_IA64_SGI_SN1)
-	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win)
-#else
-	for (win = 0; win < nbars; ++win)
-#endif
-	{
-	    iopaddr_t               base, mask, code;
-	    size_t                  size;
-
-	    /*
-	     * GET THE BASE & SIZE OF THIS WINDOW:
-	     *
-	     * The low two or four bits of the BASE register
-	     * determines which address space we are in; the
-	     * rest is a base address. BASE registers
-	     * determine windows that are power-of-two sized
-	     * and naturally aligned, so we can get the size
-	     * of a window by writing all-ones to the
-	     * register, reading it back, and seeing which
-	     * bits are used for decode; the least
-	     * significant nonzero bit is also the size of
-	     * the window.
-	     *
-	     * WARNING: someone may already have allocated
-	     * some PCI space to this window, and in fact
-	     * PIO may be in process at this very moment
-	     * from another processor (or even from this
-	     * one, if we get interrupted)! So, if the BASE
-	     * already has a nonzero address, be generous
-	     * and use the LSBit of that address as the
-	     * size; this could overstate the window size.
-	     * Usually, when one card is set up, all are set
-	     * up; so, since we don't bitch about
-	     * overlapping windows, we are ok.
-	     *
-	     * UNFORTUNATELY, some cards do not clear their
-	     * BASE registers on reset. I have two heuristics
-	     * that can detect such cards: first, if the
-	     * decode enable is turned off for the space
-	     * that the window uses, we can disregard the
-	     * initial value. second, if the address is
-	     * outside the range that we use, we can disregard
-	     * it as well.
-	     *
-	     * This is looking very PCI generic. Except for
-	     * knowing how many slots and where their config
-	     * spaces are, this window loop and the next one
-	     * could probably be shared with other PCI host
-	     * adapters. It would be interesting to see if
-	     * this could be pushed up into pciio, when we
-	     * start supporting more PCI providers.
-	     */
-#ifdef LITTLE_ENDIAN
-	    base = wptr[((win*4)^4)/4];
-#else
-	    base = wptr[win];
-#endif
-
-	    if (base & PCI_BA_IO_SPACE) {
-		/* BASE is in I/O space. */
-		space = PCIIO_SPACE_IO;
-		mask = -4;
-		code = base & 3;
-		base = base & mask;
-		if (base == 0) {
-		    ;		/* not assigned */
-		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
-		    base = 0;	/* decode not enabled */
-		}
-	    } else {
-		/* BASE is in MEM space. */
-		space = PCIIO_SPACE_MEM;
-		mask = -16;
-		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
-		base = base & mask;
-		if (base == 0) {
-		    ;		/* not assigned */
-		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
-		    base = 0;	/* decode not enabled */
-		} else if (base & 0xC0000000) {
-		    base = 0;	/* outside permissable range */
-		} else if ((code == PCI_BA_MEM_64BIT) &&
-#ifdef LITTLE_ENDIAN
-			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
-#else 
-			   (wptr[win + 1] != 0)) {
-#endif /* LITTLE_ENDIAN */
-		    base = 0;	/* outside permissable range */
-		}
-	    }
-
-	    if (base != 0) {	/* estimate size */
-		size = base & -base;
-	    } else {		/* calculate size */
-#ifdef LITTLE_ENDIAN
-		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
-		size = wptr[((win*4)^4)/4];	/* get stored bits */
-#else 
-		wptr[win] = ~0;	/* turn on all bits */
-		size = wptr[win];	/* get stored bits */
-#endif /* LITTLE_ENDIAN */
-		size &= mask;	/* keep addr */
-		size &= -size;	/* keep lsbit */
-		if (size == 0)
-		    continue;
-	    }	
-
-	    pcibr_info->f_window[win].w_space = space;
-	    pcibr_info->f_window[win].w_base = base;
-	    pcibr_info->f_window[win].w_size = size;
-
-	    /*
-	     * If this window already has PCI space
-	     * allocated for it, "subtract" that space from
-	     * our running freeblocks. Don't worry about
-	     * overlaps in existing allocated windows; we
-	     * may be overstating their sizes anyway.
-	     */
-
-	    if (base && size) {
-		if (space == PCIIO_SPACE_IO) {
-		    pcibr_freeblock_sub(&pci_io_fb,
-					&pci_io_fl,
-					base, size);
-		} else {
-		    pcibr_freeblock_sub(&pci_lo_fb,
-					&pci_lo_fl,
-					base, size);
-		    pcibr_freeblock_sub(&pci_hi_fb,
-					&pci_hi_fl,
-					base, size);
-		}	
-	    }
-#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
-	    /*
-	     * IOC3 BASE_ADDR* BUG WORKAROUND
-	     *
-	     
-	     * If we write to BASE1 on the IOC3, the
-	     * data in BASE0 is replaced. The
-	     * original workaround was to remember
-	     * the value of BASE0 and restore it
-	     * when we ran off the end of the BASE
-	     * registers; however, a later
-	     * workaround was added (I think it was
-	     * rev 1.44) to avoid setting up
-	     * anything but BASE0, with the comment
-	     * that writing all ones to BASE1 set
-	     * the enable-parity-error test feature
-	     * in IOC3's SCR bit 14.
-	     *
-	     * So, unless we defer doing any PCI
-	     * space allocation until drivers
-	     * attach, and set up a way for drivers
-	     * (the IOC3 in paricular) to tell us
-	     * generically to keep our hands off
-	     * BASE registers, we gotta "know" about
-	     * the IOC3 here.
-	     *
-	     * Too bad the PCI folks didn't reserve the
-	     * all-zero value for 'no BASE here' (it is a
-	     * valid code for an uninitialized BASE in
-	     * 32-bit PCI memory space).
-	     */
-	    
-	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
-		(device == IOC3_DEVICE_ID_NUM))
-		break;
-#endif
-	    if (code == PCI_BA_MEM_64BIT) {
-		win++;		/* skip upper half */
-#ifdef LITTLE_ENDIAN
-		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
-#else 
-		wptr[win] = 0;	/* which must be zero */
-#endif /* LITTLE_ENDIAN */
-	    }
-	}				/* next win */
-    }				/* next func */
-
-    /* Store back the values for allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_STORE();
-    return(0);
-}					
-
-/*
- * pcibr_slot_info_free
- *	Remove all the PCI infrastructural information associated
- * 	with a particular PCI device.
- */
-int
-pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
-                     pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    int			nfunc;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-#if !defined(CONFIG_IA64_SGI_SN1)
-    /* Clean out all the base registers */
-    bridge = pcibr_soft->bs_base;
-    cfgw = bridge->b_type0_cfg_dev[slot].l;
-    wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-    
-    for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) 
-#ifdef LITTLE_ENDIAN
-	wptr[((win*4)^4)/4] = 0;
-#else
-	wptr[win] = 0;
-#endif  /* LITTLE_ENDIAN */
-#endif	/* !CONFIG_IA64_SGI_SN1 */
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-
-    pcibr_device_info_free(pcibr_vhdl, slot);
-
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    DELA(pcibr_infoh,nfunc);
-    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
-
-    return(0);
-}
-
-int as_debug = 0;
-/*
- * pcibr_slot_addr_space_init
- *	Reserve chunks of PCI address space as required by 
- * 	the base registers in the card.
- */
-int
-pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
-			   pciio_slot_t	slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    bridge_t		*bridge;
-    iopaddr_t		pci_io_fb, pci_io_fl;
-    iopaddr_t		pci_lo_fb, pci_lo_fl;
-    iopaddr_t		pci_hi_fb, pci_hi_fl;
-    size_t              align;
-    iopaddr_t           mask;
-    int		    	nbars;
-    int		       	nfunc;
-    int			func;
-    int			win;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /* Get the current values for the allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_LOAD();
-
-    if (as_debug)
-#ifdef LATER
-    PCI_ADDR_SPACE_LIMITS_PRINT();
-#endif
-    /* allocate address space,
-     * for windows that have not been
-     * previously assigned.
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	return(0);
-    }
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    if (nfunc < 1)
-	return(EINVAL);
-
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    if (!pcibr_infoh)
-	return(EINVAL);
-
-    /*
-     * Try to make the DevIO windows not
-     * overlap by pushing the "io" and "hi"
-     * allocation areas up to the next one
-     * or two megabyte bound. This also
-     * keeps them from being zero.
-     *
-     * DO NOT do this with "pci_lo" since
-     * the entire "lo" area is only a
-     * megabyte, total ...
-     */
-    align = (slot < 2) ? 0x200000 : 0x100000;
-    mask = -align;
-    pci_io_fb = (pci_io_fb + align - 1) & mask;
-    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
-
-    for (func = 0; func < nfunc; ++func) {
-	cfg_p                   cfgw;
-	cfg_p                   wptr;
-	pciio_space_t           space;
-	iopaddr_t               base;
-	size_t                  size;
-	cfg_p                   pci_cfg_cmd_reg_p;
-	unsigned                pci_cfg_cmd_reg;
-	unsigned                pci_cfg_cmd_reg_add = 0;
-
-	pcibr_info = pcibr_infoh[func];
-
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-	
-	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-
-#if defined(CONFIG_IA64_SGI_SN1)
-	nbars = PCI_CFG_BASE_ADDRS;
-#else
-	if ((do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1) & 0x7f) != 0)
-	    nbars = 2;
-	else
-	    nbars = PCI_CFG_BASE_ADDRS;
-#endif
-
-	for (win = 0; win < nbars; ++win) {
-
-	    space = pcibr_info->f_window[win].w_space;
-	    base = pcibr_info->f_window[win].w_base;
-	    size = pcibr_info->f_window[win].w_size;
-	    
-	    if (size < 1)
-		continue;
-
-	    if (base >= size) {
-#if DEBUG && PCI_DEBUG
-		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
-			slot, func, win, space, base, base + size - 1);
-#endif
-		continue;		/* already allocated */
-	    }
-	    align = size;		/* ie. 0x00001000 */
-	    if (align < _PAGESZ)
-		align = _PAGESZ;	/* ie. 0x00004000 */
-	    mask = -align;		/* ie. 0xFFFFC000 */
-
-	    switch (space) {
-	    case PCIIO_SPACE_IO:
-		base = (pci_io_fb + align - 1) & mask;
-		if ((base + size) > pci_io_fl) {
-		    base = 0;
-		    break;
-		}
-		pci_io_fb = base + size;
-		break;
-		
-	    case PCIIO_SPACE_MEM:
-#ifdef LITTLE_ENDIAN
-		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
-#else
-		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
-#endif  /* LITTLE_ENDIAN */
-		    PCI_BA_MEM_1MEG) {
-		    /* allocate from 20-bit PCI space */
-		    base = (pci_lo_fb + align - 1) & mask;
-		    if ((base + size) > pci_lo_fl) {
-			base = 0;
-			break;
-		    }
-		    pci_lo_fb = base + size;
-		} else {
-		    /* allocate from 32-bit or 64-bit PCI space */
-		    base = (pci_hi_fb + align - 1) & mask;
-		    if ((base + size) > pci_hi_fl) {
-			base = 0;
-			break;
-		    }
-		    pci_hi_fb = base + size;
-		}
-		break;
-		
-	    default:
-		base = 0;
-#if DEBUG && PCI_DEBUG
-		printk("pcibr: slot %d window %d had bad space code %d\n",
-			slot, win, space);
-#endif
-	    }
-	    pcibr_info->f_window[win].w_base = base;
-#ifdef LITTLE_ENDIAN
-	    wptr[((win*4)^4)/4] = base;
-#if DEBUG && PCI_DEBUG
-		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
-#endif
-#else
-	    wptr[win] = base;
-#endif  /* LITTLE_ENDIAN */
-
-#if DEBUG && PCI_DEBUG
-	    if (base >= size)
-		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
-			slot, func, win, space, base, base + size - 1);
-	    else
-		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
-			slot, func, win, size, space);
-#endif
-	}				/* next base */
-
-	/*
-	 * Allocate space for the EXPANSION ROM
-	 * NOTE: DO NOT DO THIS ON AN IOC3,
-	 * as it blows the system away.
-	 */
-	base = size = 0;
-	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
-	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
-
-	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
-#ifdef LITTLE_ENDIAN
-	    wptr[1] = 0xFFFFF000;
-	    mask = wptr[1];
-#else
-	    *wptr = 0xFFFFF000;
-	    mask = *wptr;
-#endif  /* LITTLE_ENDIAN */
-	    if (mask & 0xFFFFF000) {
-		size = mask & -mask;
-		align = size;
-		if (align < _PAGESZ)
-		    align = _PAGESZ;
-		mask = -align;
-		base = (pci_hi_fb + align - 1) & mask;
-		if ((base + size) > pci_hi_fl)
-		    base = size = 0;
-		else {
-		    pci_hi_fb = base + size;
-#ifdef LITTLE_ENDIAN
-		    wptr[1] = base;
-#else
-		    *wptr = base;
-#endif  /* LITTLE_ENDIAN */
-#if DEBUG && PCI_DEBUG
-		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
-			    pcibr_soft->bs_name, slot,
-			    base, base + size - 1);
-#endif
-		}
-	    }
-	}
-	pcibr_info->f_rbase = base;
-	pcibr_info->f_rsize = size;
-	
-	/*
-	 * if necessary, update the board's
-	 * command register to enable decoding
-	 * in the windows we added.
-	 *
-	 * There are some bits we always want to
-	 * be sure are set.
-	 */
-	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
-
-	/*
-	 * The Adaptec 1160 FC Controller WAR #767995:
-	 * The part incorrectly ignores the upper 32 bits of a 64 bit
-	 * address when decoding references to it's registers so to
-	 * keep it from responding to a bus cycle that it shouldn't
-	 * we only use I/O space to get at it's registers.  Don't
-	 * enable memory space accesses on that PCI device.
-	 */
-	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
-	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
-
-	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
-	    (pcibr_info->f_device != FCADP_DEVID))
-	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
-
-	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
-
-	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
-	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
-#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
-	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
-	    fast_back_to_back_enable = 0;
-#endif
-	pci_cfg_cmd_reg &= 0xFFFF;
-	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
-	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
-	
-    }				/* next func */
-
-    /* Now that we have allocated new chunks of PCI address spaces to this
-     * card we need to update the bookkeeping values which indicate
-     * the current PCI address space allocations.
-     */
-    PCI_ADDR_SPACE_LIMITS_STORE();
-    return(0);
-}
-
-/*
- * pcibr_slot_device_init
- * 	Setup the device register in the bridge for this PCI slot.
- */
-int
-pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
-		       pciio_slot_t slot)
-{
-    pcibr_soft_t	 pcibr_soft;
-    bridge_t		*bridge;
-    bridgereg_t		 devreg;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /*
-     * Adjustments to Device(x)
-     * and init of bss_device shadow
-     */
-    devreg = bridge->b_device[slot].reg;
-    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
-    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
-#ifdef LITTLE_ENDIAN
-    devreg |= BRIDGE_DEV_DEV_SWAP;
-#endif
-    pcibr_soft->bs_slot[slot].bss_device = devreg;
-    bridge->b_device[slot].reg = devreg;
-
-#if DEBUG && PCI_DEBUG
-	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
-#endif
-
-#if DEBUG && PCI_DEBUG
-    printk("pcibr: PCI space allocation done.\n");
-#endif
-
-    return(0);
-}
-
-/*
- * pcibr_slot_guest_info_init
- *	Setup the host/guest relations for a PCI slot.
- */
-int
-pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
-			   pciio_slot_t	slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    pcibr_soft_slot_t	slotp;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    /* create info and verticies for guest slots;
-     * for compatibilitiy macros, create info
-     * for even unpopulated slots (but do not
-     * build verticies for them).
-     */
-    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
-	NEWA(pcibr_infoh, 1);
-	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
-	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
-
-	pcibr_info = pcibr_device_info_new
-	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
-	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
-
-	if (pcibr_soft->bs_slot[slot].has_host) {
-	    slotp->slot_conn = pciio_device_info_register
-		(pcibr_vhdl, &pcibr_info->f_c);
-	}
-    }
-
-    /* generate host/guest relations
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	int  host = pcibr_soft->bs_slot[slot].host_slot;
-	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
-
-	hwgraph_edge_add(slotp->slot_conn,
-			 host_slotp->slot_conn,
-			 EDGE_LBL_HOST);
-
-	/* XXX- only gives us one guest edge per
-	 * host. If/when we have a host with more than
-	 * one guest, we will need to figure out how
-	 * the host finds all its guests, and sorts
-	 * out which one is which.
-	 */
-	hwgraph_edge_add(host_slotp->slot_conn,
-			 slotp->slot_conn,
-			 EDGE_LBL_GUEST);
-    }
-
-    return(0);
-}
-
-/*
- * pcibr_slot_initial_rrb_alloc
- *	Allocate a default number of rrbs for this slot on 
- * 	the two channels.  This is dictated by the rrb allocation
- * 	strategy routine defined per platform.
- */
-
-int
-pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
-			     pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    bridge_t		*bridge;
-    int                 c0, c1;
-    int			r;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /* How may RRBs are on this slot?
-     */
-    c0 = do_pcibr_rrb_count_valid(bridge, slot);
-    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
-
-#if PCIBR_RRB_DEBUG
-    printk("pcibr_attach: slot %d started with %d+%d\n", slot, c0, c1);
-#endif
-
-    /* Do we really need any?
-     */
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    pcibr_info = pcibr_infoh[0];
-    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
-	!pcibr_soft->bs_slot[slot].has_host) {
-	if (c0 > 0)
-	    do_pcibr_rrb_free(bridge, slot, c0);
-	if (c1 > 0)
-	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
-	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
-	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
-	return(ENODEV);
-    }
-
-    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
-    pcibr_soft->bs_rrb_valid[slot] = c0;
-    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
-
-    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
-    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
-
-    r = 3 - (c0 + c1);
-
-    if (r > 0) {
-	pcibr_soft->bs_rrb_res[slot] = r;
-	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
-    }
-
-#if PCIBR_RRB_DEBUG
-    printk("\t%d+%d+%d",
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-    printk("\n");
-#endif
-
-    return(0);
-}
-
-/*
- * pcibr_slot_call_device_attach
- *	This calls the associated driver attach routine for the PCI
- * 	card in this slot.
- */
-int
-pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
-			      pciio_slot_t slot,
-			      int          drv_flags)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    async_attach_t	aa = NULL;
-    int			func;
-    devfs_handle_t	xconn_vhdl,conn_vhdl;
-    int			nfunc;
-    int                 error_func;
-    int                 error_slot = 0;
-    int                 error = ENODEV;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-
-    if (pcibr_soft->bs_slot[slot].has_host) {
-        return(EPERM);
-    }
-    
-    xconn_vhdl = pcibr_soft->bs_conn;
-    aa = async_attach_get_info(xconn_vhdl);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-	pcibr_info = pcibr_infoh[func];
-	
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-
-	conn_vhdl = pcibr_info->f_vertex;
-
-	/* If the PCI device has been disabled in the prom,
-	 * do not set it up for driver attach. NOTE: usrpci
-	 * and pciba will not "see" this connection point!
-	 */
-	if (device_admin_info_get(conn_vhdl, ADMIN_LBL_DISABLED)) {
-#ifdef SUPPORT_PRINTING_V_FORMAT
-	    PRINT_WARNING("pcibr_slot_call_device_attach: %v disabled\n", 
-		    conn_vhdl);
-#endif
-	    continue;
-	}
-#ifdef LATER
-	/*
-	 * Activate if and when we support cdl.
-	 */
-	if (aa)
-	    async_attach_add_info(conn_vhdl, aa);
-#endif	/* LATER */
-
-	error_func = pciio_device_attach(conn_vhdl, drv_flags);
-
-        pcibr_info->f_att_det_error = error_func;
-
-	if (error_func)
-	    error_slot = error_func;
-
-        error = error_slot;
-
-    }				/* next func */
-
-    if (error) {
-	if ((error != ENODEV) && (error != EUNATCH))
-	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
-    } else {
-        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
-    }
-        
-    return(error);
-}
-
-/*
- * pcibr_slot_call_device_detach
- *	This calls the associated driver detach routine for the PCI
- * 	card in this slot.
- */
-int
-pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
-			      pciio_slot_t slot,
-			      int          drv_flags)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    int			func;
-    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
-    int			nfunc;
-    int                 error_func;
-    int                 error_slot = 0;
-    int                 error = ENODEV;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    if (pcibr_soft->bs_slot[slot].has_host)
-        return(EPERM);
-
-    /* Make sure that we do not detach a system critical function vertex */
-    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
-        return(EPERM);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-	pcibr_info = pcibr_infoh[func];
-	
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-
-	conn_vhdl = pcibr_info->f_vertex;
-
-	error_func = pciio_device_detach(conn_vhdl, drv_flags);
-
-        pcibr_info->f_att_det_error = error_func;
-
-	if (error_func)
-	    error_slot = error_func;
-
-	error = error_slot;
-
-    }				/* next func */
-
-    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
-
-    if (error) {
-	if ((error != ENODEV) && (error != EUNATCH))
-            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
-    } else {
-        if (conn_vhdl != GRAPH_VERTEX_NONE) 
-            pcibr_device_unregister(conn_vhdl);
-        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
-    }
-        
-    return(error);
-}
-
-/*
- * pcibr_slot_detach
- *	This is a place holder routine to keep track of all the
- *	slot-specific freeing that needs to be done.
- */
-int
-pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
-		  pciio_slot_t slot,
-		  int          drv_flags)
-{
-    int		  error;
-    
-    /* Call the device detach function */
-    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
-    return (error);
-
-}
-
-/*
- * pcibr_is_slot_sys_critical
- *      Check slot for any functions that are system critical.
- *      Return 1 if any are system critical or 0 otherwise.
- *
- *      This function will always return 0 when called by 
- *      pcibr_attach() because the system critical vertices 
- *      have not yet been set in the hwgraph.
- */
-int
-pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
-                      pciio_slot_t slot)
-{
-    pcibr_soft_t        pcibr_soft;
-    pcibr_info_h        pcibr_infoh;
-    pcibr_info_t        pcibr_info;
-    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
-    int                 nfunc;
-    int                 func;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-        return(0);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-        pcibr_info = pcibr_infoh[func];
-        if (!pcibr_info)
-            continue;
-
-        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-            continue;
-
-        conn_vhdl = pcibr_info->f_vertex;
-        if (is_sys_critical_vertex(conn_vhdl)) { 
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-            PRINT_WARNING("%v is a system critical device vertex\n", conn_vhdl);
-#else
-            PRINT_WARNING("%p is a system critical device vertex\n", conn_vhdl);
-#endif
-            return(1); 
-        }
-
-    }
-
-    return(0);
-}
-
-/*
- * pcibr_device_unregister
- *	This frees up any hardware resources reserved for this PCI device
- * 	and removes any PCI infrastructural information setup for it.
- *	This is usually used at the time of shutting down of the PCI card.
- */
-int
-pcibr_device_unregister(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t	 pciio_info;
-    devfs_handle_t	 pcibr_vhdl;
-    pciio_slot_t	 slot;
-    pcibr_soft_t	 pcibr_soft;
-    bridge_t		*bridge;
-    int			 error_call;
-    int			 error = 0;
-
-    pciio_info = pciio_info_get(pconn_vhdl);
-
-    pcibr_vhdl = pciio_info_master_get(pciio_info);
-    slot = pciio_info_slot_get(pciio_info);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge = pcibr_soft->bs_base;
-
-    /* Clear all the hardware xtalk resources for this device */
-    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
-
-    /* Flush all the rrbs */
-    pcibr_rrb_flush(pconn_vhdl);
-
-    /* Free the rrbs allocated to this slot */
-    error_call = do_pcibr_rrb_free(bridge, slot, 
-		                   pcibr_soft->bs_rrb_valid[slot] +
-		                   pcibr_soft->bs_rrb_valid[slot + 
-                                   PCIBR_RRB_SLOT_VIRTUAL]);
-
-    if (error_call)
-        error = ERANGE;
-
-    pcibr_soft->bs_rrb_valid[slot] = 0;
-    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0;
-    pcibr_soft->bs_rrb_res[slot] = 0;
-
-    /* Flush the write buffers !! */
-    error_call = pcibr_wrb_flush(pconn_vhdl);
-
-    if (error_call)
-        error = error_call;
-
-    /* Clear the information specific to the slot */
-    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
-
-    if (error_call)
-        error = error_call;
-
-    return(error);
-    
-}
-
-/* 
- * build a convenience link path in the
- * form of ".../<iobrick>/bus/<busnum>"
- * 
- * returns 1 on success, 0 otherwise
- *
- * depends on hwgraph separator == '/'
- */
-int
-pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
-{
-        char dst[MAXDEVNAME];
-	char *dp = dst;
-        char *cp, *xp;
-        int widgetnum;
-        char pcibus[8];
-	devfs_handle_t nvtx, svtx;
-	int rv;
-
-#if DEBUG
-	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
-		slot, f_c);
-	{
-		int pos;
-		char dname[256];
-		pos = devfs_generate_path(f_c, dname, 256);
-		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
-	}
-#endif
-
-	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
-		return 0;
-
-	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
-
-	/* find the widget number */
-	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
-	if (xp == NULL)
-		return 0;
-	widgetnum = atoi(xp+7);
-	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
-		return 0;
-
-	/* remove "/pci/direct" from path */
-	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
-	if (cp == NULL)
-		return 0;
-	*cp = (char)NULL;
-
-	/* get the vertex for the widget */
-	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
-		return 0;
-
-	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
-
-	/* dst example now == /hw/module/001c02/Pbrick */
-
-	/* get the bus number */
-        strcat(dst, "/bus");
-        sprintf(pcibus, "%d", p_busnum[widgetnum]);
-
-	/* link to bus to widget */
-	rv = hwgraph_path_add(NULL, dp, &nvtx);
-	if (GRAPH_SUCCESS == rv)
-		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
-
-	return (rv == GRAPH_SUCCESS);
-}
-
-
-/*
- *    pcibr_attach: called every time the crosstalk
- *      infrastructure is asked to initialize a widget
- *      that matches the part number we handed to the
- *      registration routine above.
- */
-/*ARGSUSED */
-int
-pcibr_attach(devfs_handle_t xconn_vhdl)
-{
-    /* REFERENCED */
-    graph_error_t           rc;
-    devfs_handle_t            pcibr_vhdl;
-    devfs_handle_t            ctlr_vhdl;
-    bridge_t               *bridge = NULL;
-    bridgereg_t             id;
-    int                     rev;
-    pcibr_soft_t            pcibr_soft;
-    pcibr_info_t            pcibr_info;
-    xwidget_info_t          info;
-    xtalk_intr_t            xtalk_intr;
-    device_desc_t           dev_desc;
-    int                     slot;
-    int                     ibit;
-    devfs_handle_t            noslot_conn;
-    char                    devnm[MAXDEVNAME], *s;
-    pcibr_hints_t           pcibr_hints;
-    bridgereg_t             b_int_enable;
-    unsigned                rrb_fixed = 0;
-
-    iopaddr_t               pci_io_fb, pci_io_fl;
-    iopaddr_t               pci_lo_fb, pci_lo_fl;
-    iopaddr_t               pci_hi_fb, pci_hi_fl;
-
-    int                     spl_level;
-#ifdef LATER
-    char		    *nicinfo = (char *)0;
-#endif
-
-#if PCI_FBBE
-    int                     fast_back_to_back_enable;
-#endif
-    l1sc_t		    *scp;
-    nasid_t		    nasid;
-
-    async_attach_t          aa = NULL;
-
-    aa = async_attach_get_info(xconn_vhdl);
-
-#if DEBUG && ATTACH_DEBUG
-    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
-    {
-	int pos;
-	char dname[256];
-	pos = devfs_generate_path(xconn_vhdl, dname, 256);
-	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
-    }
-#endif
-
-    /* Setup the PRB for the bridge in CONVEYOR BELT
-     * mode. PRBs are setup in default FIRE-AND-FORGET
-     * mode during the initialization.
-     */
-    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
-
-    bridge = (bridge_t *)
-	xtalk_piotrans_addr(xconn_vhdl, NULL,
-			    0, sizeof(bridge_t), 0);
-
-#ifndef MEDUSA_HACK
-    if ((bridge->b_wid_stat & BRIDGE_STAT_PCI_GIO_N) == 0)
-	return -1;			/* someone else handles GIO bridges. */
-#endif
-
-#ifdef BRINGUP
-    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
-	NeedXbridgeSwap = 1;
-#endif
-
-    /*
-     * Create the vertex for the PCI bus, which we
-     * will also use to hold the pcibr_soft and
-     * which will be the "master" vertex for all the
-     * pciio connection points we will hang off it.
-     * This needs to happen before we call nic_bridge_vertex_info
-     * as we are some of the *_vmc functions need access to the edges.
-     *
-     * Opening this vertex will provide access to
-     * the Bridge registers themselves.
-     */
-    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
-    ASSERT(rc == GRAPH_SUCCESS);
-
-    ctlr_vhdl = NULL;
-    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
-                0, DEVFS_FL_AUTO_DEVNUM,
-                0, 0,
-                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-                &pcibr_fops, NULL);
-
-    ASSERT(ctlr_vhdl != NULL);
-
-    /*
-     * decode the nic, and hang its stuff off our
-     * connection point where other drivers can get
-     * at it.
-     */
-#ifdef LATER
-    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
-#endif
-
-    /*
-     * Get the hint structure; if some NIC callback
-     * marked this vertex as "hands-off" then we
-     * just return here, before doing anything else.
-     */
-    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
-
-    if (pcibr_hints && pcibr_hints->ph_hands_off)
-	return -1;			/* generic operations disabled */
-
-    id = bridge->b_wid_id;
-    rev = XWIDGET_PART_REV_NUM(id);
-
-    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
-
-    /*
-     * allocate soft state structure, fill in some
-     * fields, and hook it up to our vertex.
-     */
-    NEW(pcibr_soft);
-    BZERO(pcibr_soft, sizeof *pcibr_soft);
-    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
-
-    pcibr_soft->bs_conn = xconn_vhdl;
-    pcibr_soft->bs_vhdl = pcibr_vhdl;
-    pcibr_soft->bs_base = bridge;
-    pcibr_soft->bs_rev_num = rev;
-    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
-    if (is_xbridge(bridge)) {
-	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
-	pcibr_soft->bs_xbridge = 1;
-    } else {
-	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
-	pcibr_soft->bs_xbridge = 0;
-    }
-
-    nasid = NASID_GET(bridge);
-    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
-    pcibr_soft->bs_l1sc = scp;
-    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
-    pcibr_soft->bsi_err_intr = 0;
-
-    /* Bridges up through REV C
-     * are unable to set the direct
-     * byteswappers to BYTE_STREAM.
-     */
-    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
-	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
-	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
-    }
-#if PCIBR_SOFT_LIST
-    {
-	pcibr_list_p            self;
-
-	NEW(self);
-	self->bl_soft = pcibr_soft;
-	self->bl_vhdl = pcibr_vhdl;
-	self->bl_next = pcibr_list;
-	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
-    }
-#endif
-
-    /*
-     * get the name of this bridge vertex and keep the info. Use this
-     * only where it is really needed now: like error interrupts.
-     */
-    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
-    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
-    strcpy(pcibr_soft->bs_name, s);
-
-#if SHOW_REVS || DEBUG
-#if !DEBUG
-    if (kdebug)
-#endif
-	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
-		is_xbridge(bridge) ? "X" : "",
-		(rev == BRIDGE_PART_REV_A) ? "A" :
-		(rev == BRIDGE_PART_REV_B) ? "B" :
-		(rev == BRIDGE_PART_REV_C) ? "C" :
-		(rev == BRIDGE_PART_REV_D) ? "D" :
-		(rev == XBRIDGE_PART_REV_A) ? "A" :
-		(rev == XBRIDGE_PART_REV_B) ? "B" :
-		"unknown",
-		rev, pcibr_soft->bs_name);
-#endif
-
-    info = xwidget_info_get(xconn_vhdl);
-    pcibr_soft->bs_xid = xwidget_info_id_get(info);
-    pcibr_soft->bs_master = xwidget_info_master_get(info);
-    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
-
-    /*
-     * Init bridge lock.
-     */
-    spin_lock_init(&pcibr_soft->bs_lock);
-
-    /*
-     * If we have one, process the hints structure.
-     */
-    if (pcibr_hints) {
-	rrb_fixed = pcibr_hints->ph_rrb_fixed;
-
-	pcibr_soft->bs_rrb_fixed = rrb_fixed;
-
-	if (pcibr_hints->ph_intr_bits)
-	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
-
-	for (slot = 0; slot < 8; ++slot) {
-	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
-
-	    if (hslot < 0) {
-		pcibr_soft->bs_slot[slot].host_slot = slot;
-	    } else {
-		pcibr_soft->bs_slot[slot].has_host = 1;
-		pcibr_soft->bs_slot[slot].host_slot = hslot;
-	    }
-	}
-    }
-    /*
-     * set up initial values for state fields
-     */
-    for (slot = 0; slot < 8; ++slot) {
-	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
-	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
-	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
-	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
-    }
-
-    for (ibit = 0; ibit < 8; ++ibit) {
-	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
-							&(bridge->b_int_status);
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
-    }
-
-    /*
-     * connect up our error handler
-     */
-    xwidget_error_register(xconn_vhdl, pcibr_error_handler, pcibr_soft);
-
-    /*
-     * Initialize various Bridge registers.
-     */
-
-    /*
-     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
-     * to zero to avoid dropping stores. (#475347)
-     */
-    if (rev < BRIDGE_PART_REV_D)
-	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
-
-    /*
-     * Clear all pending interrupts.
-     */
-    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
-
-    /*
-     * Until otherwise set up,
-     * assume all interrupts are
-     * from slot 7.
-     */
-    bridge->b_int_device = (uint32_t) 0xffffffff;
-
-    {
-	bridgereg_t             dirmap;
-	paddr_t                 paddr;
-	iopaddr_t               xbase;
-	xwidgetnum_t            xport;
-	iopaddr_t               offset;
-	int                     num_entries = 0;
-	int                     entry;
-	cnodeid_t		cnodeid;
-	nasid_t			nasid;
-	char		       *node_val;
-	devfs_handle_t		node_vhdl;
-	char			vname[MAXDEVNAME];
-
-	/* Set the Bridge's 32-bit PCI to XTalk
-	 * Direct Map register to the most useful
-	 * value we can determine.  Note that we
-	 * must use a single xid for all of:
-	 *      direct-mapped 32-bit DMA accesses
-	 *      direct-mapped 64-bit DMA accesses
-	 *      DMA accesses through the PMU
-	 *      interrupts
-	 * This is the only way to guarantee that
-	 * completion interrupts will reach a CPU
-	 * after all DMA data has reached memory.
-	 * (Of course, there may be a few special
-	 * drivers/controllers that explicitly manage
-	 * this ordering problem.)
-	 */
-
-	cnodeid = 0;  /* default node id */
-	/*
-	 * Determine the base address node id to be used for all 32-bit
-	 * Direct Mapping I/O. The default is node 0, but this can be changed
-	 * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE
-	 * attribute in the irix.sm config file. A device driver can obtain
-	 * this node value via a call to pcibr_get_dmatrans_node().
-	 */
-	node_val = device_admin_info_get(pcibr_vhdl, ADMIN_LBL_DMATRANS_NODE);
-	if (node_val != NULL) {
-	    node_vhdl = hwgraph_path_to_vertex(node_val);
-	    if (node_vhdl != GRAPH_VERTEX_NONE) {
-		cnodeid = nodevertex_to_cnodeid(node_vhdl);
-	    }
-	    if ((node_vhdl == GRAPH_VERTEX_NONE) || (cnodeid == CNODEID_NONE)) {
-		cnodeid = 0;
-		vertex_to_name(pcibr_vhdl, vname, sizeof(vname));
-		PRINT_WARNING( "Invalid hwgraph node path specified:\n     DEVICE_ADMIN: %s %s=%s\n",
-			vname, ADMIN_LBL_DMATRANS_NODE, node_val);
-	    }
-	}
-	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
-	paddr = NODE_OFFSET(nasid) + 0;
-
-	/* currently, we just assume that if we ask
-	 * for a DMA mapping to "zero" the XIO
-	 * host will transmute this into a request
-	 * for the lowest hunk of memory.
-	 */
-	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
-				    paddr, _PAGESZ, 0);
-
-	if (xbase != XIO_NOWHERE) {
-	    if (XIO_PACKED(xbase)) {
-		xport = XIO_PORT(xbase);
-		xbase = XIO_ADDR(xbase);
-	    } else
-		xport = pcibr_soft->bs_mxid;
-
-	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
-	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
-
-	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
-
-	    if (xbase)
-		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
-	    else if (offset >= (512 << 20))
-		dirmap |= BRIDGE_DIRMAP_ADD512;
-
-	    bridge->b_dir_map = dirmap;
-	}
-	/*
-	 * Set bridge's idea of page size according to the system's
-	 * idea of "IO page size".  TBD: The idea of IO page size
-	 * should really go away.
-	 */
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	spl_level = splhi();
-#if IOPGSIZE == 4096
-	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
-#elif IOPGSIZE == 16384
-	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
-#else
-	<<<Unable to deal with IOPGSIZE >>>;
-#endif
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(spl_level);
-
-	/* Initialize internal mapping entries */
-	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++)
-	    bridge->b_int_ate_ram[entry].wr = 0;
-
-	/*
-	 * Determine if there's external mapping SSRAM on this
-	 * bridge.  Set up Bridge control register appropriately,
-	 * inititlize SSRAM, and set software up to manage RAM
-	 * entries as an allocatable resource.
-	 *
-	 * Currently, we just use the rm* routines to manage ATE
-	 * allocation.  We should probably replace this with a
-	 * Best Fit allocator.
-	 *
-	 * For now, if we have external SSRAM, avoid using
-	 * the internal ssram: we can't turn PREFETCH on
-	 * when we use the internal SSRAM; and besides,
-	 * this also guarantees that no allocation will
-	 * straddle the internal/external line, so we
-	 * can increment ATE write addresses rather than
-	 * recomparing against BRIDGE_INTERNAL_ATES every
-	 * time.
-	 */
-	if (is_xbridge(bridge))
-		num_entries = 0;
-	else
-		num_entries = pcibr_init_ext_ate_ram(bridge);
-
-	/* we always have 128 ATEs (512 for Xbridge) inside the chip
-	 * even if disabled for debugging.
-	 */
-	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
-	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
-#endif
-
-	if (num_entries > pcibr_soft->bs_int_ate_size) {
-#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
-	    printk("pcibr_attach: disabling internal ATEs.\n");
-	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
-#endif
-	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
-	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
-			   num_entries - pcibr_soft->bs_int_ate_size);
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
-		    num_entries - pcibr_soft->bs_int_ate_size);
-#endif
-	}
-    }
-
-    {
-	bridgereg_t             dirmap;
-	iopaddr_t               xbase;
-
-	/*
-	 * now figure the *real* xtalk base address
-	 * that dirmap sends us to.
-	 */
-	dirmap = bridge->b_dir_map;
-	if (dirmap & BRIDGE_DIRMAP_OFF)
-	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
-			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
-	else if (dirmap & BRIDGE_DIRMAP_ADD512)
-	    xbase = 512 << 20;
-	else
-	    xbase = 0;
-
-	pcibr_soft->bs_dir_xbase = xbase;
-
-	/* it is entirely possible that we may, at this
-	 * point, have our dirmap pointing somewhere
-	 * other than our "master" port.
-	 */
-	pcibr_soft->bs_dir_xport =
-	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
-    }
-
-    /* pcibr sources an error interrupt;
-     * figure out where to send it.
-     *
-     * If any interrupts are enabled in bridge,
-     * then the prom set us up and our interrupt
-     * has already been reconnected in mlreset
-     * above.
-     *
-     * Need to set the D_INTR_ISERR flag
-     * in the dev_desc used for allocating the
-     * error interrupt, so our interrupt will
-     * be properly routed and prioritized.
-     *
-     * If our crosstalk provider wants to
-     * fix widget error interrupts to specific
-     * destinations, D_INTR_ISERR is how it
-     * knows to do this.
-     */
-
-    dev_desc = device_desc_dup(pcibr_vhdl);
-    device_desc_flags_set(dev_desc,
-			  device_desc_flags_get(dev_desc) | D_INTR_ISERR);
-    device_desc_intr_name_set(dev_desc, "Bridge error");
-
-    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
-    ASSERT(xtalk_intr != NULL);
-
-    device_desc_free(dev_desc);
-
-    pcibr_soft->bsi_err_intr = xtalk_intr;
-
-    /*
-     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
-     * in order to work around some addressing limitations.  In order
-     * for that fire wall to work properly, we need to make sure we
-     * start from a known clean state.
-     */
-    pcibr_clearwidint(bridge);
-
-    xtalk_intr_connect(xtalk_intr,
-		       (intr_func_t) pcibr_error_intr_handler,
-		       (intr_arg_t) pcibr_soft,
-		       (xtalk_intr_setfunc_t) pcibr_setwidint,
-		       (void *) bridge,
-		       (void *) 0);
-
-    /*
-     * now we can start handling error interrupts;
-     * enable all of them.
-     * NOTE: some PCI ints may already be enabled.
-     */
-    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
-
-
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
-
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    /*
-     * Depending on the rev of bridge, disable certain features.
-     * Easiest way seems to be to force the PCIBR_NOwhatever
-     * flag to be on for all DMA calls, which overrides any
-     * PCIBR_whatever flag or even the setting of whatever
-     * from the PCIIO_DMA_class flags (or even from the other
-     * PCIBR flags, since NO overrides YES).
-     */
-    pcibr_soft->bs_dma_flags = 0;
-
-    /* PREFETCH:
-     * Always completely disabled for REV.A;
-     * at "pcibr_prefetch_enable_rev", anyone
-     * asking for PCIIO_PREFETCH gets it.
-     * Between these two points, you have to ask
-     * for PCIBR_PREFETCH, which promises that
-     * your driver knows about known Bridge WARs.
-     */
-    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
-	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
-    else if (pcibr_soft->bs_rev_num < 
-		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
-	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
-
-    /* WRITE_GATHER:
-     * Disabled up to but not including the
-     * rev number in pcibr_wg_enable_rev. There
-     * is no "WAR range" as with prefetch.
-     */
-    if (pcibr_soft->bs_rev_num < 
-		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
-	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
-
-    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
-    pciio_provider_startup(pcibr_vhdl);
-
-    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
-    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
-
-    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
-    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
-
-    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
-    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
-
-
-    PCI_ADDR_SPACE_LIMITS_STORE();
-
-    /* build "no-slot" connection point
-     */
-    pcibr_info = pcibr_device_info_new
-	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
-	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
-    noslot_conn = pciio_device_info_register
-	(pcibr_vhdl, &pcibr_info->f_c);
-
-    /* Remember the no slot connection point info for tearing it
-     * down during detach.
-     */
-    pcibr_soft->bs_noslot_conn = noslot_conn;
-    pcibr_soft->bs_noslot_info = pcibr_info;
-#if PCI_FBBE
-    fast_back_to_back_enable = 1;
-#endif
-
-#if PCI_FBBE
-    if (fast_back_to_back_enable) {
-	/*
-	 * All devices on the bus are capable of fast back to back, so
-	 * we need to set the fast back to back bit in all devices on
-	 * the bus that are capable of doing such accesses.
-	 */
-    }
-#endif
-
-#ifdef LATER
-    /* If the bridge has been reset then there is no need to reset
-     * the individual PCI slots.
-     */
-    for (slot = 0; slot < 8; ++slot)  
-	/* Reset all the slots */
-	(void)pcibr_slot_reset(pcibr_vhdl, slot);
-#endif
-
-    for (slot = 0; slot < 8; ++slot)
-	/* Find out what is out there */
-	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Set up the address space for this slot in the pci land */
-	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Setup the device register */
-	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
-
-#ifndef __ia64
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-    for (slot = 0; slot < 8; ++slot)  
-	/* Set up convenience links */
-	if (is_xbridge(bridge))
-		if (pcibr_soft->bs_slot[slot].bss_ninfo > 0) /* if occupied */
-			pcibr_bus_cnvlink(pcibr_info->f_vertex, slot);
-#endif
-#endif
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Setup host/guest relations */
-	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Initial RRB management */
-	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
-
-    /* driver attach routines should be called out from generic linux code */
-    for (slot = 0; slot < 8; ++slot)  
-	/* Call the device attach */
-	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
-
-    /*
-     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
-     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
-     */
-    if (pcibr_soft->bs_moduleid > 0) {
-	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
-	case 'p':		/* Pbrick */
-		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
-		break;
-	case 'i':		/* Ibrick */
-	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
-		if (pcibr_soft->bs_xid == 0xe) {
-			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
-		}
-		else {
-		    	/* allocate one RRB for the serial port */
-			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
-		}
-		break;
-	} /* switch */
-    }
-
-#ifdef LATER
-    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
-	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-#if PCIBR_RRB_DEBUG
-	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
-
-	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
-		pcibr_vhdl,
-		pcibr_soft->bs_rrb_avail[0],
-		pcibr_soft->bs_rrb_avail[1]);
-
-	for (slot = 0; slot < 8; ++slot)
-	    printf("\t%d+%d+%d",
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-
-	printf("\n");
-#endif
-    }
-#else
-	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
-#endif
-
-    if (aa)
-	    async_attach_add_info(noslot_conn, aa);
-
-    pciio_device_attach(noslot_conn, 0);
-
-
-    /* 
-     * Tear down pointer to async attach info -- async threads for
-     * bridge's descendants may be running but the bridge's work is done.
-     */
-    if (aa)
-	    async_attach_del_info(xconn_vhdl);
-
-    return 0;
-}
-/*
- * pcibr_detach:
- *	Detach the bridge device from the hwgraph after cleaning out all the 
- *	underlying vertices.
- */
-int
-pcibr_detach(devfs_handle_t xconn)
-{
-    pciio_slot_t	slot;
-    devfs_handle_t	pcibr_vhdl;
-    pcibr_soft_t	pcibr_soft;
-    bridge_t		*bridge;
-
-    /* Get the bridge vertex from its xtalk connection point */
-    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
-	return(1);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge = pcibr_soft->bs_base;
-
-    /* Disable the interrupts from the bridge */
-    bridge->b_int_enable = 0;
-
-    /* Detach all the PCI devices talking to this bridge */
-    for(slot = 0; slot < 8; slot++) {
-#ifdef DEBUG
-	printk("pcibr_device_detach called for %p/%d\n",
-		pcibr_vhdl,slot);
-#endif
-	pcibr_slot_detach(pcibr_vhdl, slot, 0);
-    }
-
-    /* Unregister the no-slot connection point */
-    pciio_device_info_unregister(pcibr_vhdl,
-				 &(pcibr_soft->bs_noslot_info->f_c));
-
-    spin_lock_destroy(&pcibr_soft->bs_lock);
-    kfree(pcibr_soft->bs_name);
-    
-    /* Error handler gets unregistered when the widget info is 
-     * cleaned 
-     */
-    /* Free the soft ATE maps */
-    if (pcibr_soft->bs_int_ate_map)
-	rmfreemap(pcibr_soft->bs_int_ate_map);
-    if (pcibr_soft->bs_ext_ate_map)
-	rmfreemap(pcibr_soft->bs_ext_ate_map);
-
-    /* Disconnect the error interrupt and free the xtalk resources 
-     * associated with it.
-     */
-    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
-    xtalk_intr_free(pcibr_soft->bsi_err_intr);
-
-    /* Clear the software state maintained by the bridge driver for this
-     * bridge.
-     */
-    DEL(pcibr_soft);
-    /* Remove the Bridge revision labelled info */
-    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
-    /* Remove the character device associated with this bridge */
-    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
-    /* Remove the PCI bridge vertex */
-    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
-
-    return(0);
-}
-
-int
-pcibr_asic_rev(devfs_handle_t pconn_vhdl)
-{
-    devfs_handle_t            pcibr_vhdl;
-    arbitrary_info_t        ainfo;
-
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
-	return -1;
-
-    if (GRAPH_SUCCESS !=
-	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
-	return -1;
-
-    return (int) ainfo;
-}
-
-int
-pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    pciio_slot_t  slot;
-    slot = pciio_info_slot_get(pciio_info);
-    pcibr_device_write_gather_flush(pcibr_soft, slot);
-    return 0;
-}
-
-/* =====================================================================
- *    PIO MANAGEMENT
- */
-
-LOCAL iopaddr_t
-pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
-		      pciio_slot_t slot,
-		      pciio_space_t space,
-		      iopaddr_t pci_addr,
-		      size_t req_size,
-		      unsigned flags)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    unsigned                bar;	/* which BASE reg on device is decoding */
-    iopaddr_t               xio_addr = XIO_NOWHERE;
-
-    pciio_space_t           wspace;	/* which space device is decoding */
-    iopaddr_t               wbase;	/* base of device decode on PCI */
-    size_t                  wsize;	/* size of device decode on PCI */
-
-    int                     try;	/* DevIO(x) window scanning order control */
-    int                     win;	/* which DevIO(x) window is being used */
-    pciio_space_t           mspace;	/* target space for devio(x) register */
-    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
-    size_t                  msize;	/* size of devio(x) mapped area on PCI */
-    size_t                  mmask;	/* addr bits stored in Device(x) */
-
-    unsigned long           s;
-
-    s = pcibr_lock(pcibr_soft);
-
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	slot = pcibr_soft->bs_slot[slot].host_slot;
-	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
-    }
-    if (space == PCIIO_SPACE_NONE)
-	goto done;
-
-    if (space == PCIIO_SPACE_CFG) {
-	/*
-	 * Usually, the first mapping
-	 * established to a PCI device
-	 * is to its config space.
-	 *
-	 * In any case, we definitely
-	 * do NOT need to worry about
-	 * PCI BASE registers, and
-	 * MUST NOT attempt to point
-	 * the DevIO(x) window at
-	 * this access ...
-	 */
-	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
-	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
-	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
-
-	goto done;
-    }
-    if (space == PCIIO_SPACE_ROM) {
-	/* PIO to the Expansion Rom.
-	 * Driver is responsible for
-	 * enabling and disabling
-	 * decodes properly.
-	 */
-	wbase = pcibr_info->f_rbase;
-	wsize = pcibr_info->f_rsize;
-
-	/*
-	 * While the driver should know better
-	 * than to attempt to map more space
-	 * than the device is decoding, he might
-	 * do it; better to bail out here.
-	 */
-	if ((pci_addr + req_size) > wsize)
-	    goto done;
-
-	pci_addr += wbase;
-	space = PCIIO_SPACE_MEM;
-    }
-    /*
-     * reduce window mappings to raw
-     * space mappings (maybe allocating
-     * windows), and try for DevIO(x)
-     * usage (setting it if it is available).
-     */
-    bar = space - PCIIO_SPACE_WIN0;
-    if (bar < 6) {
-	wspace = pcibr_info->f_window[bar].w_space;
-	if (wspace == PCIIO_SPACE_NONE)
-	    goto done;
-
-	/* get PCI base and size */
-	wbase = pcibr_info->f_window[bar].w_base;
-	wsize = pcibr_info->f_window[bar].w_size;
-
-	/*
-	 * While the driver should know better
-	 * than to attempt to map more space
-	 * than the device is decoding, he might
-	 * do it; better to bail out here.
-	 */
-	if ((pci_addr + req_size) > wsize)
-	    goto done;
-
-	/* shift from window relative to
-	 * decoded space relative.
-	 */
-	pci_addr += wbase;
-	space = wspace;
-    } else
-	bar = -1;
-
-    /* Scan all the DevIO(x) windows twice looking for one
-     * that can satisfy our request. The first time through,
-     * only look at assigned windows; the second time, also
-     * look at PCIIO_SPACE_NONE windows. Arrange the order
-     * so we always look at our own window first.
-     *
-     * We will not attempt to satisfy a single request
-     * by concatinating multiple windows.
-     */
-    for (try = 0; try < 16; ++try) {
-	bridgereg_t             devreg;
-	unsigned                offset;
-
-	win = (try + slot) % 8;
-
-	/* If this DevIO(x) mapping area can provide
-	 * a mapping to this address, use it.
-	 */
-	msize = (win < 2) ? 0x200000 : 0x100000;
-	mmask = -msize;
-	if (space != PCIIO_SPACE_IO)
-	    mmask &= 0x3FFFFFFF;
-
-	offset = pci_addr & (msize - 1);
-
-	/* If this window can't possibly handle that request,
-	 * go on to the next window.
-	 */
-	if (((pci_addr & (msize - 1)) + req_size) > msize)
-	    continue;
-
-	devreg = pcibr_soft->bs_slot[win].bss_device;
-
-	/* Is this window "nailed down"?
-	 * If not, maybe we can use it.
-	 * (only check this the second time through)
-	 */
-	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
-	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
-
-	    /* If this is the primary DevIO(x) window
-	     * for some other device, skip it.
-	     */
-	    if ((win != slot) &&
-		(PCIIO_VENDOR_ID_NONE !=
-		 pcibr_soft->bs_slot[win].bss_vendor_id))
-		continue;
-
-	    /* It's a free window, and we fit in it.
-	     * Set up Device(win) to our taste.
-	     */
-	    mbase = pci_addr & mmask;
-
-	    /* check that we would really get from
-	     * here to there.
-	     */
-	    if ((mbase | offset) != pci_addr)
-		continue;
-
-	    devreg &= ~BRIDGE_DEV_OFF_MASK;
-	    if (space != PCIIO_SPACE_IO)
-		devreg |= BRIDGE_DEV_DEV_IO_MEM;
-	    else
-		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
-	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
-
-	    /* default is WORD_VALUES.
-	     * if you specify both,
-	     * operation is undefined.
-	     */
-	    if (flags & PCIIO_BYTE_STREAM)
-		devreg |= BRIDGE_DEV_DEV_SWAP;
-	    else
-		devreg &= ~BRIDGE_DEV_DEV_SWAP;
-
-	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
-		bridge->b_device[win].reg = devreg;
-		pcibr_soft->bs_slot[win].bss_device = devreg;
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-
-#if DEBUG && PCI_DEBUG
-		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
-#endif
-	    }
-	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
-	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
-	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
-
-#if DEBUG && PCI_DEBUG
-	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
-		    __FUNCTION__, __LINE__, space, space_desc,
-		    pci_addr, pci_addr + req_size - 1,
-		    slot, win, devreg);
-#endif
-
-	    goto done;
-	}				/* endif DevIO(x) not pointed */
-	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
-
-	/* Now check for request incompat with DevIO(x)
-	 */
-	if ((mspace != space) ||
-	    (pci_addr < mbase) ||
-	    ((pci_addr + req_size) > (mbase + msize)) ||
-	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
-	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
-	    continue;
-
-	/* DevIO(x) window is pointed at PCI space
-	 * that includes our target. Calculate the
-	 * final XIO address, release the lock and
-	 * return.
-	 */
-	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
-
-#if DEBUG && PCI_DEBUG
-	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
-		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
-#endif
-	goto done;
-    }
-
-    switch (space) {
-	/*
-	 * Accesses to device decode
-	 * areas that do a not fit
-	 * within the DevIO(x) space are
-	 * modified to be accesses via
-	 * the direct mapping areas.
-	 *
-	 * If necessary, drivers can
-	 * explicitly ask for mappings
-	 * into these address spaces,
-	 * but this should never be needed.
-	 */
-    case PCIIO_SPACE_MEM:		/* "mem space" */
-    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
-	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
-	    BRIDGE_PCI_MEM32_LIMIT)
-	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
-	break;
-
-    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
-	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
-	    BRIDGE_PCI_MEM64_LIMIT)
-	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
-	break;
-
-    case PCIIO_SPACE_IO:		/* "i/o space" */
-	/* Bridge Hardware Bug WAR #482741:
-	 * The 4G area that maps directly from
-	 * XIO space to PCI I/O space is busted
-	 * until Bridge Rev D.
-	 */
-	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
-	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
-	     BRIDGE_PCI_IO_LIMIT))
-	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
-	break;
-    }
-
-    /* Check that "Direct PIO" byteswapping matches,
-     * try to change it if it does not.
-     */
-    if (xio_addr != XIO_NOWHERE) {
-	unsigned                bst;	/* nonzero to set bytestream */
-	unsigned               *bfp;	/* addr of record of how swapper is set */
-	unsigned                swb;	/* which control bit to mung */
-	unsigned                bfo;	/* current swapper setting */
-	unsigned                bfn;	/* desired swapper setting */
-
-	bfp = ((space == PCIIO_SPACE_IO)
-	       ? (&pcibr_soft->bs_pio_end_io)
-	       : (&pcibr_soft->bs_pio_end_mem));
-
-	bfo = *bfp;
-
-	bst = flags & PCIIO_BYTE_STREAM;
-
-	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
-
-	if (bfn == bfo) {		/* we already match. */
-	    ;
-	} else if (bfo != 0) {		/* we have a conflict. */
-#if DEBUG && PCI_DEBUG
-	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
-		    space, 
-		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
-		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
-#endif
-	    xio_addr = XIO_NOWHERE;
-	} else {			/* OK to make the change. */
-	    bridgereg_t             octl, nctl;
-
-	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
-	    octl = bridge->b_wid_control;
-	    nctl = bst ? octl | swb : octl & ~swb;
-
-	    if (octl != nctl)		/* make the change if any */
-		bridge->b_wid_control = nctl;
-
-	    *bfp = bfn;			/* record the assignment */
-
-#if DEBUG && PCI_DEBUG
-	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
-		    space, 
-		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
-#endif
-	}
-    }
-  done:
-    pcibr_unlock(pcibr_soft, s);
-    return xio_addr;
-}
-
-/*ARGSUSED6 */
-pcibr_piomap_t
-pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
-		   device_desc_t dev_desc,
-		   pciio_space_t space,
-		   iopaddr_t pci_addr,
-		   size_t req_size,
-		   size_t req_size_max,
-		   unsigned flags)
-{
-    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    pcibr_piomap_t         *mapptr;
-    pcibr_piomap_t          maplist;
-    pcibr_piomap_t          pcibr_piomap;
-    iopaddr_t               xio_addr;
-    xtalk_piomap_t          xtalk_piomap;
-    unsigned long           s;
-
-    /* Make sure that the req sizes are non-zero */
-    if ((req_size < 1) || (req_size_max < 1))
-	return NULL;
-
-    /*
-     * Code to translate slot/space/addr
-     * into xio_addr is common between
-     * this routine and pcibr_piotrans_addr.
-     */
-    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
-
-    if (xio_addr == XIO_NOWHERE)
-	return NULL;
-
-    /* Check the piomap list to see if there is already an allocated
-     * piomap entry but not in use. If so use that one. Otherwise
-     * allocate a new piomap entry and add it to the piomap list
-     */
-    mapptr = &(pcibr_info->f_piomap);
-
-    s = pcibr_lock(pcibr_soft);
-    for (pcibr_piomap = *mapptr;
-	 pcibr_piomap != NULL;
-	 pcibr_piomap = pcibr_piomap->bp_next) {
-	if (pcibr_piomap->bp_mapsz == 0)
-	    break;
-    }
-
-    if (pcibr_piomap)
-	mapptr = NULL;
-    else {
-	pcibr_unlock(pcibr_soft, s);
-	NEW(pcibr_piomap);
-    }
-
-    pcibr_piomap->bp_dev = pconn_vhdl;
-    pcibr_piomap->bp_slot = pciio_slot;
-    pcibr_piomap->bp_flags = flags;
-    pcibr_piomap->bp_space = space;
-    pcibr_piomap->bp_pciaddr = pci_addr;
-    pcibr_piomap->bp_mapsz = req_size;
-    pcibr_piomap->bp_soft = pcibr_soft;
-    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
-
-    if (mapptr) {
-	s = pcibr_lock(pcibr_soft);
-	maplist = *mapptr;
-	pcibr_piomap->bp_next = maplist;
-	*mapptr = pcibr_piomap;
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-
-    if (pcibr_piomap) {
-	xtalk_piomap =
-	    xtalk_piomap_alloc(xconn_vhdl, 0,
-			       xio_addr,
-			       req_size, req_size_max,
-			       flags & PIOMAP_FLAGS);
-	if (xtalk_piomap) {
-	    pcibr_piomap->bp_xtalk_addr = xio_addr;
-	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
-	} else {
-	    pcibr_piomap->bp_mapsz = 0;
-	    pcibr_piomap = 0;
-	}
-    }
-    return pcibr_piomap;
-}
-
-/*ARGSUSED */
-void
-pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
-{
-    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
-    pcibr_piomap->bp_xtalk_pio = 0;
-    pcibr_piomap->bp_mapsz = 0;
-}
-
-/*ARGSUSED */
-caddr_t
-pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
-		  iopaddr_t pci_addr,
-		  size_t req_size)
-{
-    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
-			     pcibr_piomap->bp_xtalk_addr +
-			     pci_addr - pcibr_piomap->bp_pciaddr,
-			     req_size);
-}
-
-/*ARGSUSED */
-void
-pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
-{
-    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
-}
-
-/*ARGSUSED */
-caddr_t
-pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    pciio_space_t space,
-		    iopaddr_t pci_addr,
-		    size_t req_size,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    iopaddr_t               xio_addr;
-
-    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
-
-    if (xio_addr == XIO_NOWHERE)
-	return NULL;
-
-    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
-}
-
-/*
- * PIO Space allocation and management.
- *      Allocate and Manage the PCI PIO space (mem and io space)
- *      This routine is pretty simplistic at this time, and
- *      does pretty trivial management of allocation and freeing..
- *      The current scheme is prone for fragmentation..
- *      Change the scheme to use bitmaps.
- */
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
-		     device_desc_t dev_desc,
-		     pciio_space_t space,
-		     size_t req_size,
-		     size_t alignment)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    pciio_piospace_t        piosp;
-    unsigned long           s;
-
-    iopaddr_t              *pciaddr, *pcilast;
-    iopaddr_t               start_addr;
-    size_t                  align_mask;
-
-    /*
-     * Check for proper alignment
-     */
-    ASSERT(alignment >= NBPP);
-    ASSERT((alignment & (alignment - 1)) == 0);
-
-    align_mask = alignment - 1;
-    s = pcibr_lock(pcibr_soft);
-
-    /*
-     * First look if a previously allocated chunk exists.
-     */
-    if ((piosp = pcibr_info->f_piospace)) {
-	/*
-	 * Look through the list for a right sized free chunk.
-	 */
-	do {
-	    if (piosp->free &&
-		(piosp->space == space) &&
-		(piosp->count >= req_size) &&
-		!(piosp->start & align_mask)) {
-		piosp->free = 0;
-		pcibr_unlock(pcibr_soft, s);
-		return piosp->start;
-	    }
-	    piosp = piosp->next;
-	} while (piosp);
-    }
-    ASSERT(!piosp);
-
-    switch (space) {
-    case PCIIO_SPACE_IO:
-	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
-	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
-	break;
-    case PCIIO_SPACE_MEM:
-    case PCIIO_SPACE_MEM32:
-	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
-	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
-	break;
-    default:
-	ASSERT(0);
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-
-    start_addr = *pciaddr;
-
-    /*
-     * Align start_addr.
-     */
-    if (start_addr & align_mask)
-	start_addr = (start_addr + align_mask) & ~align_mask;
-
-    if ((start_addr + req_size) > *pcilast) {
-	/*
-	 * If too big a request, reject it.
-	 */
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-    *pciaddr = (start_addr + req_size);
-
-    NEW(piosp);
-    piosp->free = 0;
-    piosp->space = space;
-    piosp->start = start_addr;
-    piosp->count = req_size;
-    piosp->next = pcibr_info->f_piospace;
-    pcibr_info->f_piospace = piosp;
-
-    pcibr_unlock(pcibr_soft, s);
-    return start_addr;
-}
-
-/*ARGSUSED */
-void
-pcibr_piospace_free(devfs_handle_t pconn_vhdl,
-		    pciio_space_t space,
-		    iopaddr_t pciaddr,
-		    size_t req_size)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-
-    pciio_piospace_t        piosp;
-    unsigned long           s;
-    char                    name[1024];
-
-    /*
-     * Look through the bridge data structures for the pciio_piospace_t
-     * structure corresponding to  'pciaddr'
-     */
-    s = pcibr_lock(pcibr_soft);
-    piosp = pcibr_info->f_piospace;
-    while (piosp) {
-	/*
-	 * Piospace free can only be for the complete
-	 * chunk and not parts of it..
-	 */
-	if (piosp->start == pciaddr) {
-	    if (piosp->count == req_size)
-		break;
-	    /*
-	     * Improper size passed for freeing..
-	     * Print a message and break;
-	     */
-	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
-	    PRINT_WARNING("pcibr_piospace_free: error");
-	    PRINT_WARNING("Device %s freeing size (0x%lx) different than allocated (0x%lx)",
-					name, req_size, piosp->count);
-	    PRINT_WARNING("Freeing 0x%lx instead", piosp->count);
-	    break;
-	}
-	piosp = piosp->next;
-    }
-
-    if (!piosp) {
-	PRINT_WARNING(
-		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
-		pciaddr, req_size);
-	pcibr_unlock(pcibr_soft, s);
-	return;
-    }
-    piosp->free = 1;
-    pcibr_unlock(pcibr_soft, s);
-    return;
-}
-
-/* =====================================================================
- *    DMA MANAGEMENT
- *
- *      The Bridge ASIC provides three methods of doing
- *      DMA: via a "direct map" register available in
- *      32-bit PCI space (which selects a contiguous 2G
- *      address space on some other widget), via
- *      "direct" addressing via 64-bit PCI space (all
- *      destination information comes from the PCI
- *      address, including transfer attributes), and via
- *      a "mapped" region that allows a bunch of
- *      different small mappings to be established with
- *      the PMU.
- *
- *      For efficiency, we most prefer to use the 32-bit
- *      direct mapping facility, since it requires no
- *      resource allocations. The advantage of using the
- *      PMU over the 64-bit direct is that single-cycle
- *      PCI addressing can be used; the advantage of
- *      using 64-bit direct over PMU addressing is that
- *      we do not have to allocate entries in the PMU.
- */
-
-/*
- * Convert PCI-generic software flags and Bridge-specific software flags
- * into Bridge-specific Direct Map attribute bits.
- */
-LOCAL iopaddr_t
-pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
-{
-    iopaddr_t               attributes = 0;
-
-    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
-#ifdef LATER
-    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
-#endif
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
-	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
-	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
-    }
-    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
-	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
-	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_PREFETCH)
-	attributes |= PCI64_ATTR_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	attributes &= ~PCI64_ATTR_PREF;
-
-    /* the swap bit is in the address attributes for xbridge */
-    if (pcibr_soft->bs_xbridge) {
-    	if (flags & PCIIO_BYTE_STREAM)
-        	attributes |= PCI64_ATTR_SWAP;
-    	if (flags & PCIIO_WORD_VALUES)
-        	attributes &= ~PCI64_ATTR_SWAP;
-    }
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_BARRIER)
-	attributes |= PCI64_ATTR_BAR;
-    if (flags & PCIBR_NOBARRIER)
-	attributes &= ~PCI64_ATTR_BAR;
-
-    if (flags & PCIBR_PREFETCH)
-	attributes |= PCI64_ATTR_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	attributes &= ~PCI64_ATTR_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	attributes |= PCI64_ATTR_PREC;
-    if (flags & PCIBR_NOPRECISE)
-	attributes &= ~PCI64_ATTR_PREC;
-
-    if (flags & PCIBR_VCHAN1)
-	attributes |= PCI64_ATTR_VIRTUAL;
-    if (flags & PCIBR_VCHAN0)
-	attributes &= ~PCI64_ATTR_VIRTUAL;
-
-    return (attributes);
-}
-
-/*
- * Convert PCI-generic software flags and Bridge-specific software flags
- * into Bridge-specific Address Translation Entry attribute bits.
- */
-LOCAL bridge_ate_t
-pcibr_flags_to_ate(unsigned flags)
-{
-    bridge_ate_t            attributes;
-
-    /* default if nothing specified:
-     * NOBARRIER
-     * NOPREFETCH
-     * NOPRECISE
-     * COHERENT
-     * Plus the valid bit
-     */
-    attributes = ATE_CO | ATE_V;
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
-	attributes &= ~ATE_BAR;		/* no barrier */
-	attributes |= ATE_PREF;		/* prefetch on */
-    }
-    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
-	attributes |= ATE_BAR;		/* barrier bit on */
-	attributes &= ~ATE_PREF;	/* disable prefetch */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_PREFETCH)
-	attributes |= ATE_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	attributes &= ~ATE_PREF;
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_BARRIER)
-	attributes |= ATE_BAR;
-    if (flags & PCIBR_NOBARRIER)
-	attributes &= ~ATE_BAR;
-
-    if (flags & PCIBR_PREFETCH)
-	attributes |= ATE_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	attributes &= ~ATE_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	attributes |= ATE_PREC;
-    if (flags & PCIBR_NOPRECISE)
-	attributes &= ~ATE_PREC;
-
-    return (attributes);
-}
-
-/*ARGSUSED */
-pcibr_dmamap_t
-pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
-		   device_desc_t dev_desc,
-		   size_t req_size_max,
-		   unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            slot;
-    xwidgetnum_t            xio_port;
-
-    xtalk_dmamap_t          xtalk_dmamap;
-    pcibr_dmamap_t          pcibr_dmamap;
-    int                     ate_count;
-    int                     ate_index;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-#ifdef IRIX
-    NEWf(pcibr_dmamap, flags);
-#else
-    /*
-     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
-     * can be called within an interrupt thread.
-     */
-    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
-#endif
-
-    if (!pcibr_dmamap)
-	return 0;
-
-    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
-				      flags & DMAMAP_FLAGS);
-    if (!xtalk_dmamap) {
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
-#endif
-	DEL(pcibr_dmamap);
-	return 0;
-    }
-    xio_port = pcibr_soft->bs_mxid;
-    slot = pciio_info_slot_get(pciio_info);
-
-    pcibr_dmamap->bd_dev = pconn_vhdl;
-    pcibr_dmamap->bd_slot = slot;
-    pcibr_dmamap->bd_soft = pcibr_soft;
-    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
-    pcibr_dmamap->bd_max_size = req_size_max;
-    pcibr_dmamap->bd_xio_port = xio_port;
-
-    if (flags & PCIIO_DMA_A64) {
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
-	    iopaddr_t               pci_addr;
-	    int                     have_rrbs;
-	    int                     min_rrbs;
-
-	    /* Device is capable of A64 operations,
-	     * and the attributes of the DMA are
-	     * consistant with any previous DMA
-	     * mappings using shared resources.
-	     */
-
-	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
-
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_xio_addr = 0;
-	    pcibr_dmamap->bd_pci_addr = pci_addr;
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
-		if (flags & PCIBR_VCHAN1)
-		    slot += PCIBR_RRB_SLOT_VIRTUAL;
-		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
-		if (have_rrbs < 2) {
-		    if (pci_addr & PCI64_ATTR_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
-		}
-	    }
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using direct64\n");
-#endif
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use direct64\n");
-#endif
-	flags &= ~PCIIO_DMA_A64;
-    }
-    if (flags & PCIIO_FIXED) {
-	/* warning: mappings may fail later,
-	 * if direct32 can't get to the address.
-	 */
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
-	    /* User desires DIRECT A32 operations,
-	     * and the attributes of the DMA are
-	     * consistant with any previous DMA
-	     * mappings using shared resources.
-	     * Mapping calls may fail if target
-	     * is outside the direct32 range.
-	     */
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using direct32\n");
-#endif
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
-	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use direct32\n");
-#endif
-	/* If the user demands FIXED and we can't
-	 * give it to him, fail.
-	 */
-	xtalk_dmamap_free(xtalk_dmamap);
-	DEL(pcibr_dmamap);
-	return 0;
-    }
-    /*
-     * Allocate Address Translation Entries from the mapping RAM.
-     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
-     * the maximum number of ATEs is based on the worst-case
-     * scenario, where the requested target is in the
-     * last byte of an ATE; thus, mapping IOPGSIZE+2
-     * does end up requiring three ATEs.
-     */
-    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
-	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
-		     +req_size_max	/* max mapping bytes */
-		     - 1) + 1;		/* round UP */
-    } else {	/* assume requested target is page aligned */
-	ate_count = IOPG(req_size_max   /* max mapping bytes */
-		     - 1) + 1;		/* round UP */
-    }
-
-    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
-
-    if (ate_index != -1) {
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
-	    bridge_ate_t            ate_proto;
-	    int                     have_rrbs;
-	    int                     min_rrbs;
-
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using PMU\n");
-#endif
-
-	    ate_proto = pcibr_flags_to_ate(flags);
-
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_pci_addr =
-		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
-	    /*
-	     * for xbridge the byte-swap bit == bit 29 of PCI address
-	     */
-	    if (pcibr_soft->bs_xbridge) {
-		    if (flags & PCIIO_BYTE_STREAM)
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-		    /*
-		     * If swap was set in bss_device in pcibr_endian_set()
-		     * we need to change the address bit.
-		     */
-		    if (pcibr_soft->bs_slot[slot].bss_device & 
-							BRIDGE_DEV_SWAP_PMU)
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-		    if (flags & PCIIO_WORD_VALUES)
-			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
-	    }
-	    pcibr_dmamap->bd_xio_addr = 0;
-	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
-	    pcibr_dmamap->bd_ate_index = ate_index;
-	    pcibr_dmamap->bd_ate_count = ate_count;
-	    pcibr_dmamap->bd_ate_proto = ate_proto;
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
-		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
-		if (have_rrbs < 2) {
-		    if (ate_proto & ATE_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
-		}
-	    }
-	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
-				!pcibr_soft->bs_xbridge) {
-		bridge_t               *bridge = pcibr_soft->bs_base;
-		volatile unsigned      *cmd_regp;
-		unsigned                cmd_reg;
-		unsigned long           s;
-
-		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
-
-		s = pcibr_lock(pcibr_soft);
-		cmd_regp = &(bridge->
-			     b_type0_cfg_dev[slot].
-			     l[PCI_CFG_COMMAND / 4]);
-		cmd_reg = *cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
-		pcibr_unlock(pcibr_soft, s);
-	    }
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use PMU\n");
-#endif
-	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
-    }
-    /* total failure: sorry, you just can't
-     * get from here to there that way.
-     */
-#if PCIBR_ATE_DEBUG
-    printk("pcibr_dmamap_alloc: complete failure.\n");
-#endif
-    xtalk_dmamap_free(xtalk_dmamap);
-    DEL(pcibr_dmamap);
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
-
-    unsigned                flags = pcibr_dmamap->bd_flags;
-
-    /* Make sure that bss_ext_ates_active
-     * is properly kept up to date.
-     */
-
-    if (PCIBR_DMAMAP_BUSY & flags)
-	if (PCIBR_DMAMAP_SSRAM & flags)
-	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
-
-    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
-
-    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
-	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
-    }
-    if (pcibr_dmamap->bd_ate_count) {
-	pcibr_ate_free(pcibr_dmamap->bd_soft,
-		       pcibr_dmamap->bd_ate_index,
-		       pcibr_dmamap->bd_ate_count);
-	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
-    }
-#ifdef IRIX
-    DEL(pcibr_dmamap);
-#endif
-}
-
-/*
- * Setup an Address Translation Entry as specified.  Use either the Bridge
- * internal maps or the external map RAM, as appropriate.
- */
-LOCAL bridge_ate_p
-pcibr_ate_addr(pcibr_soft_t pcibr_soft,
-	       int ate_index)
-{
-    bridge_t *bridge = pcibr_soft->bs_base;
-
-    return (ate_index < pcibr_soft->bs_int_ate_size)
-	? &(bridge->b_int_ate_ram[ate_index].wr)
-	: &(bridge->b_ext_ate_ram[ate_index]);
-}
-
-/*
- *    pcibr_addr_xio_to_pci: given a PIO range, hand
- *      back the corresponding base PCI MEM address;
- *      this is used to short-circuit DMA requests that
- *      loop back onto this PCI bus.
- */
-LOCAL iopaddr_t
-pcibr_addr_xio_to_pci(pcibr_soft_t soft,
-		      iopaddr_t xio_addr,
-		      size_t req_size)
-{
-    iopaddr_t               xio_lim = xio_addr + req_size - 1;
-    iopaddr_t               pci_addr;
-    pciio_slot_t            slot;
-
-    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
-	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
-	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
-	return pci_addr;
-    }
-    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
-	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
-	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
-	return pci_addr;
-    }
-    for (slot = 0; slot < 8; ++slot)
-	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
-	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
-	    bridgereg_t             dev;
-
-	    dev = soft->bs_slot[slot].bss_device;
-	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
-	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
-	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
-	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
-	}
-    return 0;
-}
-
-/* We are starting to get more complexity
- * surrounding writing ATEs, so pull
- * the writing code into this new function.
- */
-
-#if PCIBR_FREEZE_TIME
-#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
-#else
-#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
-#endif
-
-LOCAL unsigned
-ate_freeze(pcibr_dmamap_t pcibr_dmamap,
-#if PCIBR_FREEZE_TIME
-	   unsigned *freeze_time_ptr,
-#endif
-	   unsigned *cmd_regs)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-#ifdef LATER
-    int                     dma_slot = pcibr_dmamap->bd_slot;
-#endif
-    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
-    int                     slot;
-
-    unsigned long           s;
-    unsigned                cmd_reg;
-    volatile unsigned      *cmd_lwa;
-    unsigned                cmd_lwd;
-
-    if (!ext_ates)
-	return 0;
-
-    /* Bridge Hardware Bug WAR #484930:
-     * Bridge can't handle updating External ATEs
-     * while DMA is occuring that uses External ATEs,
-     * even if the particular ATEs involved are disjoint.
-     */
-
-    /* need to prevent anyone else from
-     * unfreezing the grant while we
-     * are working; also need to prevent
-     * this thread from being interrupted
-     * to keep PCI grant freeze time
-     * at an absolute minimum.
-     */
-    s = pcibr_lock(pcibr_soft);
-
-#ifdef LATER
-    /* just in case pcibr_dmamap_done was not called */
-    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
-	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
-	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
-	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
-	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
-    }
-#endif	/* LATER */
-#if PCIBR_FREEZE_TIME
-    *freeze_time_ptr = get_timestamp();
-#endif
-
-    cmd_lwa = 0;
-    for (slot = 0; slot < 8; ++slot)
-	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
-	    cmd_reg = pcibr_soft->
-		bs_slot[slot].
-		bss_cmd_shadow;
-	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
-		cmd_lwa = pcibr_soft->
-		    bs_slot[slot].
-		    bss_cmd_pointer;
-		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
-		cmd_lwa[0] = cmd_lwd;
-	    }
-	    cmd_regs[slot] = cmd_reg;
-	} else
-	    cmd_regs[slot] = 0;
-
-    if (cmd_lwa) {
-	    bridge_t	*bridge = pcibr_soft->bs_base;
-
-	    /* Read the last master bit that has been cleared. This PIO read
-	     * on the PCI bus is to ensure the completion of any DMAs that
-	     * are due to bus requests issued by PCI devices before the
-	     * clearing of master bits.
-	     */
-	    cmd_lwa[0];
-
-	    /* Flush all the write buffers in the bridge */
-	    for (slot = 0; slot < 8; ++slot)
-		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
-			    /* Flush the write buffer associated with this
-			     * PCI device which might be using dma map RAM.
-			     */
-			    bridge->b_wr_req_buf[slot].reg;
-		    }
-    }
-    return s;
-}
-
-#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
-
-LOCAL void
-ate_write(bridge_ate_p ate_ptr,
-	  int ate_count,
-	  bridge_ate_t ate)
-{
-    while (ate_count-- > 0) {
-	*ate_ptr++ = ate;
-	ate += IOPGSIZE;
-    }
-}
-
-
-#if PCIBR_FREEZE_TIME
-#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
-#else
-#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
-#endif
-
-LOCAL void
-ate_thaw(pcibr_dmamap_t pcibr_dmamap,
-	 int ate_index,
-#if PCIBR_FREEZE_TIME
-	 bridge_ate_t ate,
-	 int ate_total,
-	 unsigned freeze_time_start,
-#endif
-	 unsigned *cmd_regs,
-	 unsigned s)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-    int                     dma_slot = pcibr_dmamap->bd_slot;
-    int                     slot;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
-
-    unsigned                cmd_reg;
-
-#if PCIBR_FREEZE_TIME
-    unsigned                freeze_time;
-    static unsigned         max_freeze_time = 0;
-    static unsigned         max_ate_total;
-#endif
-
-    if (!ext_ates)
-	return;
-
-    /* restore cmd regs */
-    for (slot = 0; slot < 8; ++slot)
-	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
-	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
-
-    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
-    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
-
-#if PCIBR_FREEZE_TIME
-    freeze_time = get_timestamp() - freeze_time_start;
-
-    if ((max_freeze_time < freeze_time) ||
-	(max_ate_total < ate_total)) {
-	if (max_freeze_time < freeze_time)
-	    max_freeze_time = freeze_time;
-	if (max_ate_total < ate_total)
-	    max_ate_total = ate_total;
-	pcibr_unlock(pcibr_soft, s);
-	printk("%s: pci freeze time %d usec for %d ATEs\n"
-		"\tfirst ate: %R\n",
-		pcibr_soft->bs_name,
-		freeze_time * 1000 / 1250,
-		ate_total,
-		ate, ate_bits);
-    } else
-#endif
-	pcibr_unlock(pcibr_soft, s);
-}
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
-		  paddr_t paddr,
-		  size_t req_size)
-{
-    pcibr_soft_t            pcibr_soft;
-    iopaddr_t               xio_addr;
-    xwidgetnum_t            xio_port;
-    iopaddr_t               pci_addr;
-    unsigned                flags;
-
-    ASSERT(pcibr_dmamap != NULL);
-    ASSERT(req_size > 0);
-    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
-
-    pcibr_soft = pcibr_dmamap->bd_soft;
-
-    flags = pcibr_dmamap->bd_flags;
-
-    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
-    if (XIO_PACKED(xio_addr)) {
-	xio_port = XIO_PORT(xio_addr);
-	xio_addr = XIO_ADDR(xio_addr);
-    } else
-	xio_port = pcibr_dmamap->bd_xio_port;
-
-    /* If this DMA is to an address that
-     * refers back to this Bridge chip,
-     * reduce it back to the correct
-     * PCI MEM address.
-     */
-    if (xio_port == pcibr_soft->bs_xid) {
-	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
-    } else if (flags & PCIIO_DMA_A64) {
-	/* A64 DMA:
-	 * always use 64-bit direct mapping,
-	 * which always works.
-	 * Device(x) was set up during
-	 * dmamap allocation.
-	 */
-
-	/* attributes are already bundled up into bd_pci_addr.
-	 */
-	pci_addr = pcibr_dmamap->bd_pci_addr
-	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
-	    | xio_addr;
-
-	/* Bridge Hardware WAR #482836:
-	 * If the transfer is not cache aligned
-	 * and the Bridge Rev is <= B, force
-	 * prefetch to be off.
-	 */
-	if (flags & PCIBR_NOPREFETCH)
-	    pci_addr &= ~PCI64_ATTR_PREF;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-	printk("pcibr_dmamap_addr (direct64):\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\tXIO port 0x%x offset 0x%x\n"
-		"\treturning PCI 0x%x\n",
-		paddr, paddr + req_size - 1,
-		xio_port, xio_addr, pci_addr);
-#endif
-    } else if (flags & PCIIO_FIXED) {
-	/* A32 direct DMA:
-	 * always use 32-bit direct mapping,
-	 * which may fail.
-	 * Device(x) was set up during
-	 * dmamap allocation.
-	 */
-
-	if (xio_port != pcibr_soft->bs_dir_xport)
-	    pci_addr = 0;		/* wrong DIDN */
-	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
-	    pci_addr = 0;		/* out of range */
-	else if ((xio_addr + req_size) >
-		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
-	    pci_addr = 0;		/* out of range */
-	else
-	    pci_addr = pcibr_dmamap->bd_pci_addr +
-		xio_addr - pcibr_dmamap->bd_xio_addr;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-	printk("pcibr_dmamap_addr (direct32):\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\tXIO port 0x%x offset 0x%x\n"
-		"\treturning PCI 0x%x\n",
-		paddr, paddr + req_size - 1,
-		xio_port, xio_addr, pci_addr);
-#endif
-    } else {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-	iopaddr_t               offset = IOPGOFF(xio_addr);
-	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
-	int                     ate_count = IOPG(offset + req_size - 1) + 1;
-
-	int                     ate_index = pcibr_dmamap->bd_ate_index;
-	unsigned                cmd_regs[8];
-	unsigned                s;
-
-#if PCIBR_FREEZE_TIME
-	int                     ate_total = ate_count;
-	unsigned                freeze_time;
-#endif
-
-#if PCIBR_ATE_DEBUG
-	bridge_ate_t            ate_cmp;
-	bridge_ate_p            ate_cptr;
-	unsigned                ate_lo, ate_hi;
-	int                     ate_bad = 0;
-	int                     ate_rbc = 0;
-#endif
-	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
-	bridge_ate_t            ate;
-
-	/* Bridge Hardware WAR #482836:
-	 * If the transfer is not cache aligned
-	 * and the Bridge Rev is <= B, force
-	 * prefetch to be off.
-	 */
-	if (flags & PCIBR_NOPREFETCH)
-	    ate_proto &= ~ATE_PREF;
-
-	ate = ate_proto
-	    | (xio_port << ATE_TIDSHIFT)
-	    | (xio_addr - offset);
-
-	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
-
-	/* Fill in our mapping registers
-	 * with the appropriate xtalk data,
-	 * and hand back the PCI address.
-	 */
-
-	ASSERT(ate_count > 0);
-	if (ate_count <= pcibr_dmamap->bd_ate_count) {
-		ATE_FREEZE();
-		ATE_WRITE();
-		ATE_THAW();
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	} else {
-		/* The number of ATE's required is greater than the number
-		 * allocated for this map. One way this can happen is if
-		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
-		 * flag, and then when that map is used (right now), the
-		 * target address tells us we really did need to roundup.
-		 * The other possibility is that the map is just plain too
-		 * small to handle the requested target area.
-		 */
-#if PCIBR_ATE_DEBUG
-		PRINT_WARNING( "pcibr_dmamap_addr :\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\tate_count 0x%x bd_ate_count 0x%x\n"
-			"\tATE's required > number allocated\n",
-			paddr, paddr + req_size - 1,
-			ate_count, pcibr_dmamap->bd_ate_count);
-#endif
-		pci_addr = 0;
-	}
-
-    }
-    return pci_addr;
-}
-
-/*ARGSUSED */
-alenlist_t
-pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
-		  alenlist_t palenlist,
-		  unsigned flags)
-{
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge=NULL;
-
-    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
-    int                     inplace = flags & PCIIO_INPLACE;
-
-    alenlist_t              pciio_alenlist = 0;
-    alenlist_t              xtalk_alenlist;
-    size_t                  length;
-    iopaddr_t               offset;
-    unsigned                direct64;
-    int                     ate_index = 0;
-    int                     ate_count = 0;
-    int                     ate_total = 0;
-    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
-    bridge_ate_t            ate_proto = (bridge_ate_t)0;
-    bridge_ate_t            ate_prev;
-    bridge_ate_t            ate;
-    alenaddr_t              xio_addr;
-    xwidgetnum_t            xio_port;
-    iopaddr_t               pci_addr;
-    alenaddr_t              new_addr;
-
-    unsigned                cmd_regs[8];
-    unsigned                s = 0;
-
-#if PCIBR_FREEZE_TIME
-    unsigned                freeze_time;
-#endif
-    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
-							 * with an ATE_FREEZE
-							 */
-
-    pcibr_soft = pcibr_dmamap->bd_soft;
-
-    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
-				       flags & DMAMAP_FLAGS);
-    if (!xtalk_alenlist)
-	goto fail;
-
-    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
-
-    if (inplace) {
-	pciio_alenlist = xtalk_alenlist;
-    } else {
-	pciio_alenlist = alenlist_create(al_flags);
-	if (!pciio_alenlist)
-	    goto fail;
-    }
-
-    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
-    if (!direct64) {
-	bridge = pcibr_soft->bs_base;
-	ate_ptr = pcibr_dmamap->bd_ate_ptr;
-	ate_index = pcibr_dmamap->bd_ate_index;
-	ate_proto = pcibr_dmamap->bd_ate_proto;
-	ATE_FREEZE();
-	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
-    }
-    pci_addr = pcibr_dmamap->bd_pci_addr;
-
-    ate_prev = 0;			/* matches no valid ATEs */
-    while (ALENLIST_SUCCESS ==
-	   alenlist_get(xtalk_alenlist, NULL, 0,
-			&xio_addr, &length, al_flags)) {
-	if (XIO_PACKED(xio_addr)) {
-	    xio_port = XIO_PORT(xio_addr);
-	    xio_addr = XIO_ADDR(xio_addr);
-	} else
-	    xio_port = pcibr_dmamap->bd_xio_port;
-
-	if (xio_port == pcibr_soft->bs_xid) {
-	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
-	    if (new_addr == PCI_NOWHERE)
-		goto fail;
-	} else if (direct64) {
-	    new_addr = pci_addr | xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-	    /* Bridge Hardware WAR #482836:
-	     * If the transfer is not cache aligned
-	     * and the Bridge Rev is <= B, force
-	     * prefetch to be off.
-	     */
-	    if (flags & PCIBR_NOPREFETCH)
-		new_addr &= ~PCI64_ATTR_PREF;
-
-	} else {
-	    /* calculate the ate value for
-	     * the first address. If it
-	     * matches the previous
-	     * ATE written (ie. we had
-	     * multiple blocks in the
-	     * same IOPG), then back up
-	     * and reuse that ATE.
-	     *
-	     * We are NOT going to
-	     * aggressively try to
-	     * reuse any other ATEs.
-	     */
-	    offset = IOPGOFF(xio_addr);
-	    ate = ate_proto
-		| (xio_port << ATE_TIDSHIFT)
-		| (xio_addr - offset);
-	    if (ate == ate_prev) {
-#if PCIBR_ATE_DEBUG
-		printk("pcibr_dmamap_list: ATE share\n");
-#endif
-		ate_ptr--;
-		ate_index--;
-		pci_addr -= IOPGSIZE;
-	    }
-	    new_addr = pci_addr + offset;
-
-	    /* Fill in the hardware ATEs
-	     * that contain this block.
-	     */
-	    ate_count = IOPG(offset + length - 1) + 1;
-	    ate_total += ate_count;
-
-	    /* Ensure that this map contains enough ATE's */
-	    if (ate_total > pcibr_dmamap->bd_ate_count) {
-#if PCIBR_ATE_DEBUG
-		PRINT_WARNING( "pcibr_dmamap_list :\n"
-			"\twanted xio_addr [0x%x..0x%x]\n"
-			"\tate_total 0x%x bd_ate_count 0x%x\n"
-			"\tATE's required > number allocated\n",
-			xio_addr, xio_addr + length - 1,
-			ate_total, pcibr_dmamap->bd_ate_count);
-#endif
-		goto fail;
-	    }
-
-	    ATE_WRITE();
-
-	    ate_index += ate_count;
-	    ate_ptr += ate_count;
-
-	    ate_count <<= IOPFNSHIFT;
-	    ate += ate_count;
-	    pci_addr += ate_count;
-	}
-
-	/* write the PCI DMA address
-	 * out to the scatter-gather list.
-	 */
-	if (inplace) {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_replace(pciio_alenlist, NULL,
-				 &new_addr, &length, al_flags))
-		goto fail;
-	} else {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_append(pciio_alenlist,
-				new_addr, length, al_flags))
-		goto fail;
-	}
-    }
-    if (!inplace)
-	alenlist_done(xtalk_alenlist);
-
-    /* Reset the internal cursor of the alenlist to be returned back
-     * to the caller.
-     */
-    alenlist_cursor_init(pciio_alenlist, 0, NULL);
-
-
-    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
-     * changes that ATE_FREEZE has done to implement the external SSRAM
-     * bug workaround.
-     */
-    if (ate_freeze_done) {
-	ATE_THAW();
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    return pciio_alenlist;
-
-  fail:
-    /* There are various points of failure after doing an ATE_FREEZE
-     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
-     * The decision to do an ATE_THAW needs to be based on whether a
-     * an ATE_FREEZE was done before.
-     */
-    if (ate_freeze_done) {
-	ATE_THAW();
-	bridge->b_wid_tflush;
-    }
-    if (pciio_alenlist && !inplace)
-	alenlist_destroy(pciio_alenlist);
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
-{
-    /*
-     * We could go through and invalidate ATEs here;
-     * for performance reasons, we don't.
-     * We also don't enforce the strict alternation
-     * between _addr/_list and _done, but Hub does.
-     */
-
-    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
-	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
-
-	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
-	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
-    }
-
-    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
-}
-
-
-/*
- * For each bridge, the DIR_OFF value in the Direct Mapping Register
- * determines the PCI to Crosstalk memory mapping to be used for all
- * 32-bit Direct Mapping memory accesses. This mapping can be to any
- * node in the system. This function will return that compact node id.
- */
-
-/*ARGSUSED */
-cnodeid_t
-pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
-{
-
-	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
-	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
-}
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    paddr_t paddr,
-		    size_t req_size,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
-
-    xwidgetnum_t            xio_port;
-    iopaddr_t               xio_addr;
-    iopaddr_t               pci_addr;
-
-    int                     have_rrbs;
-    int                     min_rrbs;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
-				   flags & DMAMAP_FLAGS);
-
-    if (!xio_addr) {
-#if PCIBR_DMA_DEBUG
-	printk("pcibr_dmatrans_addr:\n"
-		"\tpciio connection point %v\n"
-		"\txtalk connection point %v\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\txtalk_dmatrans_addr returned 0x%x\n",
-		pconn_vhdl, xconn_vhdl,
-		paddr, paddr + req_size - 1,
-		xio_addr);
-#endif
-	return 0;
-    }
-    /*
-     * find which XIO port this goes to.
-     */
-    if (XIO_PACKED(xio_addr)) {
-	if (xio_addr == XIO_NOWHERE) {
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	    return 0;
-	}
-	xio_port = XIO_PORT(xio_addr);
-	xio_addr = XIO_ADDR(xio_addr);
-
-    } else
-	xio_port = pcibr_soft->bs_mxid;
-
-    /*
-     * If this DMA comes back to us,
-     * return the PCI MEM address on
-     * which it would land, or NULL
-     * if the target is something
-     * on bridge other than PCI MEM.
-     */
-    if (xio_port == pcibr_soft->bs_xid) {
-	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
-	return pci_addr;
-    }
-    /* If the caller can use A64, try to
-     * satisfy the request with the 64-bit
-     * direct map. This can fail if the
-     * configuration bits in Device(x)
-     * conflict with our flags.
-     */
-
-    if (flags & PCIIO_DMA_A64) {
-	pci_addr = slotp->bss_d64_base;
-	if (!(flags & PCIBR_VCHAN1))
-	    flags |= PCIBR_VCHAN0;
-	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
-	    (flags == slotp->bss_d64_flags)) {
-
-	    pci_addr |= xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-#if DEBUG && PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-	    if (xio_addr != 0x20000000)
-#endif
-		printk("pcibr_dmatrans_addr: [reuse]\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tdirect 64bit address is 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, pci_addr);
-#endif
-	    return (pci_addr);
-	}
-	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
-	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
-	    slotp->bss_d64_flags = flags;
-	    slotp->bss_d64_base = pci_addr;
-	    pci_addr |= xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
-		if (flags & PCIBR_VCHAN1)
-		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
-		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
-		if (have_rrbs < 2) {
-		    if (pci_addr & PCI64_ATTR_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
-		}
-	    }
-#if PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-	    if (xio_addr != 0x20000000)
-#endif
-		printk("pcibr_dmatrans_addr:\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tdirect 64bit address is 0x%x\n"
-			"\tnew flags: 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, pci_addr, (uint64_t) flags);
-#endif
-	    return (pci_addr);
-	}
-	/* our flags conflict with Device(x).
-	 */
-	flags = flags
-	    & ~PCIIO_DMA_A64
-	    & ~PCIBR_VCHAN0
-	    ;
-
-#if PCIBR_DMA_DEBUG
-	printk("pcibr_dmatrans_addr:\n"
-		"\tpciio connection point %v\n"
-		"\txtalk connection point %v\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\txtalk_dmatrans_addr returned 0x%x\n"
-		"\tUnable to set Device(x) bits for Direct-64\n",
-		pconn_vhdl, xconn_vhdl,
-		paddr, paddr + req_size - 1,
-		xio_addr);
-#endif
-    }
-    /* Try to satisfy the request with the 32-bit direct
-     * map. This can fail if the configuration bits in
-     * Device(x) conflict with our flags, or if the
-     * target address is outside where DIR_OFF points.
-     */
-    {
-	size_t                  map_size = 1ULL << 31;
-	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
-	iopaddr_t               offset = xio_addr - xio_base;
-	iopaddr_t               endoff = req_size + offset;
-
-	if ((req_size > map_size) ||
-	    (xio_addr < xio_base) ||
-	    (xio_port != pcibr_soft->bs_dir_xport) ||
-	    (endoff > map_size)) {
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n"
-		    "\txio region outside direct32 target\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	} else {
-	    pci_addr = slotp->bss_d32_base;
-	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
-		(flags == slotp->bss_d32_flags)) {
-
-		pci_addr |= offset;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-		printk("pcibr_dmatrans_addr: [reuse]\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tmapped via direct32 offset 0x%x\n"
-			"\twill DMA via pci addr 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, offset, pci_addr);
-#endif
-		return (pci_addr);
-	    }
-	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
-
-		pci_addr = PCI32_DIRECT_BASE;
-		slotp->bss_d32_flags = flags;
-		slotp->bss_d32_base = pci_addr;
-		pci_addr |= offset;
-
-		/* Make sure we have an RRB (or two).
-		 */
-		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
-		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
-		    if (have_rrbs < 2) {
-			if (slotp->bss_device & BRIDGE_DEV_PREF)
-			    min_rrbs = 2;
-			else
-			    min_rrbs = 1;
-			if (have_rrbs < min_rrbs)
-			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
-		    }
-		}
-#if PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-		if (xio_addr != 0x20000000)
-#endif
-		    printk("pcibr_dmatrans_addr:\n"
-			    "\tpciio connection point %v\n"
-			    "\txtalk connection point %v\n"
-			    "\twanted paddr [0x%x..0x%x]\n"
-			    "\txtalk_dmatrans_addr returned 0x%x\n"
-			    "\tmapped via direct32 offset 0x%x\n"
-			    "\twill DMA via pci addr 0x%x\n"
-			    "\tnew flags: 0x%x\n",
-			    pconn_vhdl, xconn_vhdl,
-			    paddr, paddr + req_size - 1,
-			    xio_addr, offset, pci_addr, (uint64_t) flags);
-#endif
-		return (pci_addr);
-	    }
-	    /* our flags conflict with Device(x).
-	     */
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n"
-		    "\tUnable to set Device(x) bits for Direct-32\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	}
-    }
-
-#if PCIBR_DMA_DEBUG
-    printk("pcibr_dmatrans_addr:\n"
-	    "\tpciio connection point %v\n"
-	    "\txtalk connection point %v\n"
-	    "\twanted paddr [0x%x..0x%x]\n"
-	    "\txtalk_dmatrans_addr returned 0x%x\n"
-	    "\tno acceptable PCI address found or constructable\n",
-	    pconn_vhdl, xconn_vhdl,
-	    paddr, paddr + req_size - 1,
-	    xio_addr);
-#endif
-
-    return 0;
-}
-
-/*ARGSUSED */
-alenlist_t
-pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    alenlist_t palenlist,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
-    xwidgetnum_t            xio_port;
-
-    alenlist_t              pciio_alenlist = 0;
-    alenlist_t              xtalk_alenlist = 0;
-
-    int                     inplace;
-    unsigned                direct64;
-    unsigned                al_flags;
-
-    iopaddr_t               xio_base;
-    alenaddr_t              xio_addr;
-    size_t                  xio_size;
-
-    size_t                  map_size;
-    iopaddr_t               pci_base;
-    alenaddr_t              pci_addr;
-
-    unsigned                relbits = 0;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-    inplace = flags & PCIIO_INPLACE;
-    direct64 = flags & PCIIO_DMA_A64;
-    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
-
-    if (direct64) {
-	map_size = 1ull << 48;
-	xio_base = 0;
-	pci_base = slotp->bss_d64_base;
-	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
-	    (flags == slotp->bss_d64_flags)) {
-	    /* reuse previous base info */
-	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
-	    /* DMA configuration conflict */
-	    goto fail;
-	} else {
-	    relbits = BRIDGE_DEV_D64_BITS;
-	    pci_base =
-		pcibr_flags_to_d64(flags, pcibr_soft);
-	}
-    } else {
-	xio_base = pcibr_soft->bs_dir_xbase;
-	map_size = 1ull << 31;
-	pci_base = slotp->bss_d32_base;
-	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
-	    (flags == slotp->bss_d32_flags)) {
-	    /* reuse previous base info */
-	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
-	    /* DMA configuration conflict */
-	    goto fail;
-	} else {
-	    relbits = BRIDGE_DEV_D32_BITS;
-	    pci_base = PCI32_DIRECT_BASE;
-	}
-    }
-
-    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
-					 flags & DMAMAP_FLAGS);
-    if (!xtalk_alenlist)
-	goto fail;
-
-    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
-
-    if (inplace) {
-	pciio_alenlist = xtalk_alenlist;
-    } else {
-	pciio_alenlist = alenlist_create(al_flags);
-	if (!pciio_alenlist)
-	    goto fail;
-    }
-
-    while (ALENLIST_SUCCESS ==
-	   alenlist_get(xtalk_alenlist, NULL, 0,
-			&xio_addr, &xio_size, al_flags)) {
-
-	/*
-	 * find which XIO port this goes to.
-	 */
-	if (XIO_PACKED(xio_addr)) {
-	    if (xio_addr == XIO_NOWHERE) {
-#if PCIBR_DMA_DEBUG
-		printk("pcibr_dmatrans_addr:\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr);
-#endif
-		return 0;
-	    }
-	    xio_port = XIO_PORT(xio_addr);
-	    xio_addr = XIO_ADDR(xio_addr);
-	} else
-	    xio_port = pcibr_soft->bs_mxid;
-
-	/*
-	 * If this DMA comes back to us,
-	 * return the PCI MEM address on
-	 * which it would land, or NULL
-	 * if the target is something
-	 * on bridge other than PCI MEM.
-	 */
-	if (xio_port == pcibr_soft->bs_xid) {
-	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
-	    if ( (pci_addr == (alenaddr_t)NULL) )
-		goto fail;
-	} else if (direct64) {
-	    ASSERT(xio_port != 0);
-	    pci_addr = pci_base | xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-	} else {
-	    iopaddr_t               offset = xio_addr - xio_base;
-	    iopaddr_t               endoff = xio_size + offset;
-
-	    if ((xio_size > map_size) ||
-		(xio_addr < xio_base) ||
-		(xio_port != pcibr_soft->bs_dir_xport) ||
-		(endoff > map_size))
-		goto fail;
-
-	    pci_addr = pci_base + (xio_addr - xio_base);
-	}
-
-	/* write the PCI DMA address
-	 * out to the scatter-gather list.
-	 */
-	if (inplace) {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_replace(pciio_alenlist, NULL,
-				 &pci_addr, &xio_size, al_flags))
-		goto fail;
-	} else {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_append(pciio_alenlist,
-				pci_addr, xio_size, al_flags))
-		goto fail;
-	}
-    }
-
-    if (relbits) {
-	if (direct64) {
-	    slotp->bss_d64_flags = flags;
-	    slotp->bss_d64_base = pci_base;
-	} else {
-	    slotp->bss_d32_flags = flags;
-	    slotp->bss_d32_base = pci_base;
-	}
-    }
-    if (!inplace)
-	alenlist_done(xtalk_alenlist);
-
-    /* Reset the internal cursor of the alenlist to be returned back
-     * to the caller.
-     */
-    alenlist_cursor_init(pciio_alenlist, 0, NULL);
-    return pciio_alenlist;
-
-  fail:
-    if (relbits)
-	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
-    if (pciio_alenlist && !inplace)
-	alenlist_destroy(pciio_alenlist);
-    return 0;
-}
-
-void
-pcibr_dmamap_drain(pcibr_dmamap_t map)
-{
-    xtalk_dmamap_drain(map->bd_xtalk);
-}
-
-void
-pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
-		    paddr_t paddr,
-		    size_t bytes)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
-}
-
-void
-pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
-		    alenlist_t list)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    xtalk_dmalist_drain(xconn_vhdl, list);
-}
-
-/*
- * Get the starting PCIbus address out of the given DMA map.
- * This function is supposed to be used by a close friend of PCI bridge
- * since it relies on the fact that the starting address of the map is fixed at
- * the allocation time in the current implementation of PCI bridge.
- */
-iopaddr_t
-pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
-{
-    return (pcibr_dmamap->bd_pci_addr);
-}
-
-/* =====================================================================
- *    INTERRUPT MANAGEMENT
- */
-
-static unsigned
-pcibr_intr_bits(pciio_info_t info,
-		pciio_intr_line_t lines)
-{
-    pciio_slot_t            slot = pciio_info_slot_get(info);
-    unsigned		    bbits = 0;
-
-    /*
-     * Currently favored mapping from PCI
-     * slot number and INTA/B/C/D to Bridge
-     * PCI Interrupt Bit Number:
-     *
-     *     SLOT     A B C D
-     *      0       0 4 0 4
-     *      1       1 5 1 5
-     *      2       2 6 2 6
-     *      3       3 7 3 7
-     *      4       4 0 4 0
-     *      5       5 1 5 1
-     *      6       6 2 6 2
-     *      7       7 3 7 3
-     */
-
-    if (slot < 8) {
-	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
-	    bbits |= 1 << slot;
-	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
-	    bbits |= 1 << (slot ^ 4);
-    }
-    return bbits;
-}
-
-
-/*
- *	Get the next wrapper pointer queued in the interrupt circular buffer.
- */
-#ifdef KERNEL_THREADS
-pcibr_intr_wrap_t
-pcibr_wrap_get(pcibr_intr_cbuf_t cbuf)
-{
-    pcibr_intr_wrap_t	wrap;
-
-	if (cbuf->ib_in == cbuf->ib_out)
-	    PRINT_PANIC("pcibr intr circular buffer empty, cbuf=0x%x, ib_in=ib_out=%d\n",
-		cbuf, cbuf->ib_out);
-
-	wrap = cbuf->ib_cbuf[cbuf->ib_out++];
-	cbuf->ib_out = cbuf->ib_out % IBUFSIZE;
-	return(wrap);
-}
-
-/* 
- *	Queue a wrapper pointer in the interrupt circular buffer.
- */
-void
-pcibr_wrap_put(pcibr_intr_wrap_t wrap, pcibr_intr_cbuf_t cbuf)
-{
-	int	in;
-	unsigned long	s;
-
-	/*
-	 * Multiple CPUs could be executing this code simultaneously
-	 * if a handler has registered multiple interrupt lines and
-	 * the interrupts are directed to different CPUs.
-	 */
-	s = mutex_spinlock(&cbuf->ib_lock);
-	in = (cbuf->ib_in + 1) % IBUFSIZE;
-	if (in == cbuf->ib_out) 
-	    PRINT_PANIC("pcibr intr circular buffer full, cbuf=0x%x, ib_in=%d\n",
-		cbuf, cbuf->ib_in);
-
-	cbuf->ib_cbuf[cbuf->ib_in] = wrap;
-	cbuf->ib_in = in;
-	mutex_spinunlock(&cbuf->ib_lock, s);
-	return;
-}
-#endif	/* KERNEL_THREADS */
-
-/*
- *	There are end cases where a deadlock can occur if interrupt 
- *	processing completes and the Bridge b_int_status bit is still set.
- *
- *	One scenerio is if a second PCI interrupt occurs within 60ns of
- *	the previous interrupt being cleared. In this case the Bridge
- *	does not detect the transition, the Bridge b_int_status bit
- *	remains set, and because no transition was detected no interrupt
- *	packet is sent to the Hub/Heart.
- *
- *	A second scenerio is possible when a b_int_status bit is being
- *	shared by multiple devices:
- *						Device #1 generates interrupt
- *						Bridge b_int_status bit set
- *						Device #2 generates interrupt
- *		interrupt processing begins
- *		  ISR for device #1 runs and
- *			clears interrupt
- *						Device #1 generates interrupt
- *		  ISR for device #2 runs and
- *			clears interrupt
- *						(b_int_status bit still set)
- *		interrupt processing completes
- *		  
- *	Interrupt processing is now complete, but an interrupt is still
- *	outstanding for Device #1. But because there was no transition of
- *	the b_int_status bit, no interrupt packet will be generated and
- *	a deadlock will occur.
- *
- *	To avoid these deadlock situations, this function is used
- *	to check if a specific Bridge b_int_status bit is set, and if so,
- *	cause the setting of the corresponding interrupt bit.
- *
- *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
- *	Interrupt register.
- */
-void
-pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
-{
-	unsigned	bit;
-	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
-	bridge_t       *bridge = pcibr_soft->bs_base;
-	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
-
-	bit = wrap->iw_intr;
-
-	if (pcibr_soft->bs_xbridge) {
-	    bridge->b_force_pin[bit].intr = 1;
-	} else if ((1 << bit) & *wrap->iw_stat) {
-	    cpuid_t	    cpu;
-	    unsigned        intr_bit;
-	    xtalk_intr_t    xtalk_intr =
-				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
-
-	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
-	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
-	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
-	}
-}
-
-/* Wrapper for pcibr interrupt threads. */
-#ifdef KERNEL_THREADS
-static void
-pcibr_intrd(pcibr_intr_t intr)
-{
-    pcibr_intr_wrap_t	wrap;
-
-	/* Called on each restart */
-	ASSERT(cpuid() == intr->bi_mustruncpu);
-
-#ifdef ITHREAD_LATENCY
-	xthread_update_latstats(intr->bi_tinfo.thd_latstats);
-#endif /* ITHREAD_LATENCY */
-
-	ASSERT(intr->bi_func != NULL);
-	intr->bi_func(intr->bi_arg);		/* Invoke the interrupt handler */
-
-	/*
-	 * The pcibr_intrd thread needs access to the wrapper struct
-	 * specific to the current interrupt it is processing. Because
-	 * multiple calls/wakeups to the thread could be queued, each
-	 * potentially from a different interrupt line (PCIIO_INTR_LINE_A,
-	 * etc), multiple wrapper struct pointers need to be queued. This 
-	 * is done via a circular buffer of wrapper struct pointers. 
-	 */
-	wrap = pcibr_wrap_get(&intr->bi_ibuf);
-
-	/* 
-	 * The interrupt handler has completed. Now decrement the running
-	 * count tracking the number of handlers still running for this line.
-	 * If this was the last handler to complete (i.e., iw_hdlrcnt == 0),
-	 * avoid a potential deadlock condition and ensure that another
-	 * interrupt will occur if the Bridge b_int_status bit is still
-	 * set. 
-	 */
-	atomicAddInt(&(wrap->iw_hdlrcnt), -1);
-	if (wrap->iw_hdlrcnt == 0)
-		pcibr_force_interrupt(wrap);
-
-	ipsema(&intr->bi_tinfo.thd_isync);	/* Sleep 'till next interrupt */
-	/* NOTREACHED */
-}
-
-static void
-pcibr_intrd_start(pcibr_intr_t intr)
-{
-	ASSERT(intr->bi_mustruncpu >= 0);
-	setmustrun(intr->bi_mustruncpu);
-
-	xthread_set_func(KT_TO_XT(curthreadp), (xt_func_t *)pcibr_intrd, (void *)intr);
-	atomicSetInt(&intr->bi_tinfo.thd_flags, THD_INIT);
-	ipsema(&intr->bi_tinfo.thd_isync);  /* Comes out in pcibr_intrd */
-	/* NOTREACHED */
-}
-
-
-static void
-pcibr_thread_setup(pcibr_intr_t intr, int bridge_levels, ilvl_t intr_swlevel)
-{
-	char thread_name[32];
-
-	sprintf(thread_name, "pcibr_intrd[0x%x]", bridge_levels);
-	thread_name[IT_NAMELEN-1] = '\0';
-
-	/* XXX need to adjust priority whenever an interrupt is connected */
-	intr->bi_tinfo.thd_pri = intr_swlevel;
-	atomicSetInt(&intr->bi_tinfo.thd_flags, THD_ISTHREAD | THD_REG);
-	xthread_setup(thread_name, intr_swlevel, &intr->bi_tinfo,
-			(xt_func_t *)pcibr_intrd_start,
-			(void *)intr);
-}
-#endif	/* KERNEL_THREADS */
-
-
-
-/*ARGSUSED */
-pcibr_intr_t
-pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
-		 device_desc_t dev_desc,
-		 pciio_intr_line_t lines,
-		 devfs_handle_t owner_dev)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     is_threaded = 0;
-#ifdef KERNEL_THREADS
-    cpuid_t		    mustruncpu = CPU_NONE;
-    cpuid_t		    old_intrcpu = CPU_NONE;
-#endif
-    int                     thread_swlevel;
-
-    xtalk_intr_t           *xtalk_intr_p;
-    pcibr_intr_t           *pcibr_intr_p;
-    pcibr_intr_list_t      *intr_list_p;
-
-    unsigned                pcibr_int_bits;
-    unsigned                pcibr_int_bit;
-    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
-    hub_intr_t		    hub_intr;
-    pcibr_intr_t            pcibr_intr;
-    pcibr_intr_list_t       intr_entry;
-    pcibr_intr_list_t       intr_list;
-    bridgereg_t             int_dev;
-
-#if DEBUG && INTR_DEBUG
-    printk("%v: pcibr_intr_alloc\n"
-	    "%v:%s%s%s%s%s\n",
-	    owner_dev, pconn_vhdl,
-	    !(lines & 15) ? " No INTs?" : "",
-	    lines & 1 ? " INTA" : "",
-	    lines & 2 ? " INTB" : "",
-	    lines & 4 ? " INTC" : "",
-	    lines & 8 ? " INTD" : "");
-#endif
-
-    NEW(pcibr_intr);
-    if (!pcibr_intr)
-	return NULL;
-
-    if (dev_desc) {
-	cpuid_t intr_target_from_desc(device_desc_t, int);
-
-#ifdef KERNEL_THREADS
-	is_threaded = !(device_desc_flags_get(dev_desc) & D_INTR_NOTHREAD);
-	if (is_threaded) {
-	    /*
-	     * If the device descriptor contains interrupt target info,
-	     * save the CPU requested. This is the CPU the pcibr_intrd
-	     * thread will be set to run on. 
-	     *
-	     * We need to get the interrupt target info at this time, because
-	     * the original intr_target value can be overwritten, as part of
-	     * the xtalk_intr_alloc_nothd() call, with the actual interrupt CPU.
-	     * This can be different than the requested CPU if the lower layers
-	     * could not direct the hardware interrupt to the requested CPU. 
-	     * Regardless of which CPU processes the hardware interrupt, the 
-	     * ISR thread will still be setup to run on the CPU originally 
-	     * requested.
-	     */
-		mustruncpu = intr_target_from_desc(dev_desc, SUBNODE_ANY);
-		thread_swlevel = device_desc_intr_swlevel_get(dev_desc);
-	}
-#endif	/* KERNEL_THREADS */
-    } else {
-	extern int default_intr_pri;
-
-	is_threaded = 1; /* PCI interrupts are threaded, by default */
-	thread_swlevel = default_intr_pri;
-    }
-
-    pcibr_intr->bi_dev = pconn_vhdl;
-    pcibr_intr->bi_lines = lines;
-    pcibr_intr->bi_soft = pcibr_soft;
-    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
-    pcibr_intr->bi_func = 0;		/* unset until connect */
-    pcibr_intr->bi_arg = 0;		/* unset until connect */
-    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
-    pcibr_intr->bi_mustruncpu = CPU_NONE;
-#ifdef KERNEL_THREADS
-    pcibr_intr->bi_ibuf.ib_in = 0;
-    pcibr_intr->bi_ibuf.ib_out = 0;
-#endif
-    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
-
-    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
-
-
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and make sure there are xtalk resources
-     * allocated for it.
-     */
-#if DEBUG && INTR_DEBUG
-    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
-#endif 
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    xtalk_intr = *xtalk_intr_p;
-
-	    if (xtalk_intr == NULL) {
-		/*
-		 * This xtalk_intr_alloc is constrained for two reasons:
-		 * 1) Normal interrupts and error interrupts need to be delivered
-		 *    through a single xtalk target widget so that there aren't any
-		 *    ordering problems with DMA, completion interrupts, and error
-		 *    interrupts. (Use of xconn_vhdl forces this.)
-		 *
-		 * 2) On IP35, addressing constraints on IP35 and Bridge force
-		 *    us to use a single PI number for all interrupts from a
-		 *    single Bridge. (IP35-specific code forces this, and we
-		 *    verify in pcibr_setwidint.)
-		 */
-
-		/*
-		 * All code dealing with threaded PCI interrupt handlers
-		 * is located at the pcibr level. Because of this,
-		 * we always want the lower layers (hub/heart_intr_alloc, 
-		 * intr_level_connect) to treat us as non-threaded so we
-		 * don't set up a duplicate threaded environment. We make
-		 * this happen by calling a special xtalk interface.
-		 */
-		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
-			owner_dev);
-#if DEBUG && INTR_DEBUG
-		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
-#endif
-
-		/* both an assert and a runtime check on this:
-		 * we need to check in non-DEBUG kernels, and
-		 * the ASSERT gets us more information when
-		 * we use DEBUG kernels.
-		 */
-		ASSERT(xtalk_intr != NULL);
-		if (xtalk_intr == NULL) {
-		    /* it is quite possible that our
-		     * xtalk_intr_alloc failed because
-		     * someone else got there first,
-		     * and we can find their results
-		     * in xtalk_intr_p.
-		     */
-		    if (!*xtalk_intr_p) {
-#ifdef SUPPORT_PRINTING_V_FORMAT
-			PRINT_ALERT(
-				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
-				xconn_vhdl);
-#endif
-			/* yes, we leak resources here. */
-			return 0;
-		    }
-		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
-		    /*
-		     * now tell the bridge which slot is
-		     * using this interrupt line.
-		     */
-		    int_dev = bridge->b_int_device;
-		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
-		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
-		    bridge->b_int_device = int_dev;	/* XXXMP */
-
-#if DEBUG && INTR_DEBUG
-		    printk("%v: bridge intr bit %d clears my wrb\n",
-			    pconn_vhdl, pcibr_int_bit);
-#endif
-		} else {
-		    /* someone else got one allocated first;
-		     * free the one we just created, and
-		     * retrieve the one they allocated.
-		     */
-		    xtalk_intr_free(xtalk_intr);
-		    xtalk_intr = *xtalk_intr_p;
-#if PARANOID
-		    /* once xtalk_intr is set, we never clear it,
-		     * so if the CAS fails above, this condition
-		     * can "never happen" ...
-		     */
-		    if (!xtalk_intr) {
-			PRINT_ALERT(
-				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
-				xconn_vhdl);
-			/* yes, we leak resources here. */
-			return 0;
-		    }
-#endif
-		}
-	    }
-
-#ifdef KERNEL_THREADS
-	    if (is_threaded) {
-		cpuid_t intrcpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
-
-		/*
-		 * It is possible that 2 (or more) interrupts originating on a
-		 * single Bridge and used by a single device were assigned to
-		 * different CPUs. If this occurs issue a warning message for
-		 * this sub-optimal configuration. There are two ways this 
-		 * could happen:
-		 *
-		 *  - There were insufficient xtalk interrupt resources to
-		 *    allow all interrupts to be assigned to the same CPU.
-		 *    This is an unlikely case, but could happen if someone
-		 *    tries to target a lot of interrupts to a single CPU.
-		 *
-		 * - If there is no device descriptor associated with this
-		 *   device, the xtalk/hub/heart layers will not know to
-		 *   assign the same CPU to any additional interrupts this
-		 *   driver has specified, and will perform the normal load
-		 *   leveling of interrupts across CPUs.
-		 *   (The lower layers store the CPU assigned to the first
-		 *   interrupt in the device desc, if present, and then when
-		 *   called again for additional interrupts for the same device,
-		 *   use this information to assign the same CPU to these
-		 *   interrupts.)
-		 */
-		if ((old_intrcpu != CPU_NONE) && (old_intrcpu != intrcpu)) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Conflict on where to schedule interrupts for %v\n", pconn_vhdl);
-#else
-			PRINT_WARNING("Conflict on where to schedule interrupts for 0x%x\n", pconn_vhdl);
-#endif
-			PRINT_WARNING("(on cpu %d or on cpu %d), cpu %d used\n", old_intrcpu, intrcpu, intrcpu);
-		}
-		if (old_intrcpu == CPU_NONE)
-			old_intrcpu = intrcpu;
-	    /*
-	     * For threaded drivers, set the interrupt thread to run wherever
-	     * the interrupt is targeted, or where requested in the dev_desc.
-	     */
-		if (mustruncpu != CPU_NONE) {
-			pcibr_intr->bi_mustruncpu = mustruncpu;
-			if (mustruncpu != intrcpu) {
-				PRINT_WARNING("Request to target PCI interrupts to CPU %d could not\n"
-                		"      be satisfied, CPU %d used. However, interrupt thread\n"
-                		"      pcibr_intrd will run on CPU %d as requested.\n"
-                		"      %v (0x%x)\n",
-                		mustruncpu, intrcpu, mustruncpu, owner_dev,
-				owner_dev);
-			}
-		} else {
-			pcibr_intr->bi_mustruncpu = intrcpu;
-		}
-		ASSERT(pcibr_intr->bi_mustruncpu >= 0);
-
-	    }
-#endif	/* KERNEL_THREADS */
-
-	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
-
-	    NEW(intr_entry);
-	    intr_entry->il_next = NULL;
-	    intr_entry->il_intr = pcibr_intr;
-	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
-	    intr_list_p = 
-		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
-#if DEBUG && INTR_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
-		pconn_vhdl, pcibr_int_bit,
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
-#else
-	    printk("%v: Bridge bit %d wrap=0x%x\n",
-		pconn_vhdl, pcibr_int_bit,
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
-#endif
-#endif
-
-	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		/* we are the first interrupt on this bridge bit.
-		 */
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    intr_list = *intr_list_p;
-	    pcibr_intr_p = &intr_list->il_intr;
-	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
-		/* first entry on list was erased,
-		 * and we replaced it, so we
-		 * don't need our intr_entry.
-		 */
-		DEL(intr_entry);
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    intr_list_p = &intr_list->il_next;
-	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		/* we are the new second interrupt on this bit.
-		 */
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    while (1) {
-		pcibr_intr_p = &intr_list->il_intr;
-		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
-		    /* an entry on list was erased,
-		     * and we replaced it, so we
-		     * don't need our intr_entry.
-		     */
-		    DEL(intr_entry);
-#if DEBUG && INTR_DEBUG
-		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
-			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		    break;
-		}
-		intr_list_p = &intr_list->il_next;
-		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		    /* entry appended to share list
-		     */
-#if DEBUG && INTR_DEBUG
-		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
-			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		    break;
-		}
-		/* step to next record in chain
-		 */
-		intr_list = *intr_list_p;
-	    }
-	}
-    }
-
-#ifdef KERNEL_THREADS
-    if (is_threaded) {
-	/* Set pcibr_intr->bi_tinfo */
-	pcibr_thread_setup(pcibr_intr, pcibr_int_bits, thread_swlevel);
-	ASSERT(!(pcibr_intr->bi_flags & PCIIO_INTR_CONNECTED));
-    }
-#endif	/* KERNEL_THREADS */
-
-#if DEBUG && INTR_DEBUG
-    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
-#endif
-    hub_intr = (hub_intr_t)xtalk_intr;
-    pcibr_intr->bi_irq = hub_intr->i_bit;
-    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
-    return pcibr_intr;
-}
-
-/*ARGSUSED */
-void
-pcibr_intr_free(pcibr_intr_t pcibr_intr)
-{
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    unsigned                pcibr_int_bit;
-    pcibr_intr_list_t       intr_list;
-    int			    intr_shared;
-    xtalk_intr_t	    *xtalk_intrp;
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    for (intr_list = 
-		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
-		 intr_list != NULL;
-		 intr_list = intr_list->il_next)
-		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
-					 pcibr_intr, 
-					 NULL)) {
-#if DEBUG && INTR_DEBUG
-		    printk("%s: cleared a handler from bit %d\n",
-			    pcibr_soft->bs_name, pcibr_int_bit);
-#endif
-		}
-	    /* If this interrupt line is not being shared between multiple
-	     * devices release the xtalk interrupt resources.
-	     */
-	    intr_shared = 
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
-	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    if ((!intr_shared) && (*xtalk_intrp)) {
-
-		bridge_t 	*bridge = pcibr_soft->bs_base;
-		bridgereg_t	int_dev;
-
-		xtalk_intr_free(*xtalk_intrp);
-		*xtalk_intrp = 0;
-
-		/* Clear the PCI device interrupt to bridge interrupt pin
-		 * mapping.
-		 */
-		int_dev = bridge->b_int_device;
-		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
-		bridge->b_int_device = int_dev;
-
-	    }
-	}
-    }
-    DEL(pcibr_intr);
-}
-
-LOCAL void
-pcibr_setpciint(xtalk_intr_t xtalk_intr)
-{
-    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
-    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
-    bridgereg_t            *int_addr = (bridgereg_t *)
-    xtalk_intr_sfarg_get(xtalk_intr);
-
-    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
-		 (BRIDGE_INT_ADDR_FLD & vect));
-}
-
-/*ARGSUSED */
-int
-pcibr_intr_connect(pcibr_intr_t pcibr_intr,
-		   intr_func_t intr_func,
-		   intr_arg_t intr_arg,
-		   void *thread)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-    bridgereg_t             b_int_enable;
-    unsigned long           s;
-
-    if (pcibr_intr == NULL)
-	return -1;
-
-#if DEBUG && INTR_DEBUG
-    printk("%v: pcibr_intr_connect 0x%X(0x%X)\n",
-	    pcibr_intr->bi_dev, intr_func, intr_arg);
-#endif
-
-    pcibr_intr->bi_func = intr_func;
-    pcibr_intr->bi_arg = intr_arg;
-    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
-
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and make sure there are xtalk resources
-     * allocated for it.
-     */
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    pcibr_intr_wrap_t       intr_wrap;
-	    xtalk_intr_t            xtalk_intr;
-
-	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
-	    /*
-	     * If this interrupt line is being shared and the connect has
-	     * already been done, no need to do it again.
-	     */
-	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
-		continue;
-
-
-	    /*
-	     * Use the pcibr wrapper function to handle all Bridge interrupts
-	     * regardless of whether the interrupt line is shared or not.
-	     */
-	    xtalk_intr_connect(xtalk_intr,
-				pcibr_intr_func,
-			       (intr_arg_t) intr_wrap,
-			       (xtalk_intr_setfunc_t) pcibr_setpciint,
-			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr),
-			       0);
-	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
-
-#if DEBUG && INTR_DEBUG
-	    printk("%v bridge bit %d wrapper connected\n",
-		    pcibr_intr->bi_dev, pcibr_int_bit);
-#endif
-	}
-    s = pcibr_lock(pcibr_soft);
-    b_int_enable = bridge->b_int_enable;
-    b_int_enable |= pcibr_int_bits;
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-    pcibr_intr_wrap_t	    intr_wrap;
-    bridgereg_t             b_int_enable;
-    unsigned long           s;
-
-    /* Stop calling the function. Now.
-     */
-    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
-    pcibr_intr->bi_func = 0;
-    pcibr_intr->bi_arg = 0;
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and disconnect the interrupt.
-     */
-
-    /* don't disable interrupts for lines that
-     * are shared between devices.
-     */
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
-	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
-	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
-    if (!pcibr_int_bits)
-	return;
-
-    s = pcibr_lock(pcibr_soft);
-    b_int_enable = bridge->b_int_enable;
-    b_int_enable &= ~pcibr_int_bits;
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    /* if the interrupt line is now shared,
-	     * do not disconnect it.
-	     */
-	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
-		continue;
-
-	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
-	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
-
-#if DEBUG && INTR_DEBUG
-	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
-		pcibr_soft->bs_name, pcibr_int_bit);
-#endif
-
-	    /* if we are sharing the interrupt line,
-	     * connect us up; this closes the hole
-	     * where the another pcibr_intr_alloc()
-	     * was in progress as we disconnected.
-	     */
-	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
-	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
-		continue;
-
-
-	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
-			       pcibr_intr_func,
-			       (intr_arg_t) intr_wrap,
-			       (xtalk_intr_setfunc_t) pcibr_setpciint,
-			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr),
-			       0);
-	}
-}
-
-/*ARGSUSED */
-devfs_handle_t
-pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit))
-	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
-    return 0;
-}
-
-/* =====================================================================
- *    INTERRUPT HANDLING
- */
-LOCAL void
-pcibr_clearwidint(bridge_t *bridge)
-{
-    bridge->b_wid_int_upper = 0;
-    bridge->b_wid_int_lower = 0;
-}
-
-
-LOCAL void
-pcibr_setwidint(xtalk_intr_t intr)
-{
-    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
-    iopaddr_t               addr = xtalk_intr_addr_get(intr);
-    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
-    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
-    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
-
-    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
-
-    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
-			       XTALK_ADDR_TO_UPPER(addr));
-    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
-
-    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
-    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-    /* Verify that all interrupts from this Bridge are using a single PI */
-    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
-	/*
-	 * Once set, these registers shouldn't change; they should
-	 * be set multiple times with the same values.
-	 *
-	 * If we're attempting to change these registers, it means
-	 * that our heuristics for allocating interrupts in a way
-	 * appropriate for IP35 have failed, and the admin needs to
-	 * explicitly direct some interrupts (or we need to make the
-	 * heuristics more clever).
-	 *
-	 * In practice, we hope this doesn't happen very often, if
-	 * at all.
-	 */
-	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
-	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
-		PRINT_WARNING("Interrupt allocation is too complex.\n");
-		PRINT_WARNING("Use explicit administrative interrupt targetting.\n");
-		PRINT_WARNING("bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
-		PRINT_WARNING("NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
-			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
-			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
-		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
-	}
-    }
-#endif /* CONFIG_SGI_IP35 */
-
-    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
-    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
-    bridge->b_int_host_err = vect;
-}
-
-/*
- * pcibr_intr_preset: called during mlreset time
- * if the platform specific code needs to route
- * one of the Bridge's xtalk interrupts before the
- * xtalk infrastructure is available.
- */
-void
-pcibr_xintr_preset(void *which_widget,
-		   int which_widget_intr,
-		   xwidgetnum_t targ,
-		   iopaddr_t addr,
-		   xtalk_intr_vector_t vect)
-{
-    bridge_t               *bridge = (bridge_t *) which_widget;
-
-    if (which_widget_intr == -1) {
-	/* bridge widget error interrupt */
-	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
-				   XTALK_ADDR_TO_UPPER(addr));
-	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
-	bridge->b_int_host_err = vect;
-
-	/* turn on all interrupts except
-	 * the PCI interrupt requests,
-	 * at least at heart.
-	 */
-	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
-
-    } else {
-	/* routing a PCI device interrupt.
-	 * targ and low 38 bits of addr must
-	 * be the same as the already set
-	 * value for the widget error interrupt.
-	 */
-	bridge->b_int_addr[which_widget_intr].addr =
-	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
-	     (BRIDGE_INT_ADDR_FLD & vect));
-	/*
-	 * now bridge can let it through;
-	 * NB: still should be blocked at
-	 * xtalk provider end, until the service
-	 * function is set.
-	 */
-	bridge->b_int_enable |= 1 << vect;
-    }
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-}
-
-
-/*
- * pcibr_intr_func()
- *
- * This is the pcibr interrupt "wrapper" function that is called,
- * in interrupt context, to initiate the interrupt handler(s) registered
- * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
- * handlers will be called directly, and threaded handlers will have their 
- * thread woken up.
- */
-void
-pcibr_intr_func(intr_arg_t arg)
-{
-    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
-    reg_p                   wrbf;
-    intr_func_t             func;
-    pcibr_intr_t            intr;
-    pcibr_intr_list_t       list;
-    int                     clearit;
-#ifdef KERNEL_THREADS
-    int			    do_nonthreaded = 0;
-    int			    do_threaded = 1;
-    int			    is_threaded = 0;
-#else
-    int			    do_nonthreaded = 1;
-    int			    do_threaded = 0;
-    int			    is_threaded = 0;
-#endif
-    int			    nonthreaded_count = 0;
-    int			    x = 0;
-
-	/*
-	 * If any handler is still running from a previous interrupt
-	 * just return. If there's a need to call the handler(s) again,
-	 * another interrupt will be generated either by the device or by
-	 * pcibr_force_interrupt().
-	 */
-
-	if (wrap->iw_hdlrcnt) {
-		return;
-	}
-
-    /*
-     * Call all interrupt handlers registered.
-     * First, the pcibr_intrd threads for any threaded handlers will be
-     * awoken, then any non-threaded handlers will be called sequentially.
-     */
-	
-	clearit = 1;
-	while (do_threaded || do_nonthreaded) {
-	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
-		if ((intr = list->il_intr) &&
-		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
-
-		    ASSERT(intr->bi_func);
-
-		/*
-		 * This device may have initiated write
-		 * requests since the bridge last saw
-		 * an edge on this interrupt input; flushing
-		 * the buffer prior to invoking the handler
-		 * should help but may not be sufficient if we 
-		 * get more requests after the flush, followed
-		 * by the card deciding it wants service, before
-		 * the interrupt handler checks to see if things need
-		 * to be done.
-		 *
-		 * There is a similar race condition if
-		 * an interrupt handler loops around and
-		 * notices further service is requred.
-		 * Perhaps we need to have an explicit
-		 * call that interrupt handlers need to
-		 * do between noticing that DMA to memory
-		 * has completed, but before observing the
-		 * contents of memory?
-		 */
-
-#ifdef KERNEL_THREADS
-		    is_threaded = !(intr->bi_flags & PCIIO_INTR_NOTHREAD);
-		    if (!is_threaded) {
-			nonthreaded_count++;
-		    }
-
-		    if ((do_threaded) && (is_threaded)) {
-			/* Only need to flush write buffers if sharing */
-
-			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
-			    if (x = *wrbf)	/* write request buffer flush */
-#ifdef SUPPORT_PRINTING_V_FORMAT
-				PRINT_ALERT("pcibr_intr_func %v: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#else
-				PRINT_ALERT("pcibr_intr_func 0x%x: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#endif
-			}
-
-			/*
-			 * Keep a running count of the number of interrupt
-			 * handlers that have yet to complete. 
-			 */
-			atomicAddInt(&(wrap->iw_hdlrcnt), 1);
-
-			/* 
-			 * Prior to waking up pcibr_intrd, a pointer to the 
-			 * wrapper struct corresponding to the interrupt taken
-			 * needs to be queued in the interrupt circular buffer.
-			 * The pcibr_intrd thread needs the wrapper pointer in
-			 * order to decrement the handler count (iw_hdlrcnt).
-			 */
-			pcibr_wrap_put(wrap, &intr->bi_ibuf);
-#ifdef ITHREAD_LATENCY
-			xthread_set_istamp(intr->bi_tinfo.thd_latstats);
-#endif /* ITHREAD_LATENCY */
-		     	up(&intr->bi_tinfo.thd_isync); 
-		    } else
-#endif	/* KERNEL_THREADS */
-			if ((do_nonthreaded) && (!is_threaded)) {
-			/* Non-threaded. 
-			 * Call the interrupt handler at interrupt level
-			 */
-
-			/* Only need to flush write buffers if sharing */
-
-			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
-			    if ((x = *wrbf))	/* write request buffer flush */
-#ifdef SUPPORT_PRINTING_V_FORMAT
-				PRINT_ALERT("pcibr_intr_func %v: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#else
-				PRINT_ALERT("pcibr_intr_func %p: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#endif
-			}
-
-			func = intr->bi_func;
-			func(intr->bi_arg);
-		    }
-
-		    clearit = 0;
-		}
-	    }
-
-	    if (do_threaded) {
-		/* 
-		 * All threaded handlers have been called;
-		 * next do non-threaded, if any.
-		 */
-		do_threaded = 0;
-
-		if (nonthreaded_count)
-			do_nonthreaded = 1;
-	    } else {
-		do_nonthreaded = 0;
-		/*
-		 * If the non-threaded handler was the last to complete,
-		 * (i.e., no threaded handlers still running) force an
-		 * interrupt to avoid a potential deadlock situation.
-		 */
-		if (wrap->iw_hdlrcnt == 0) {
-			pcibr_force_interrupt(wrap);
-		}
-	    }
-	}
-
-	/* If there were no handlers,
-	 * disable the interrupt and return.
-	 * It will get enabled again after
-	 * a handler is connected.
-	 * If we don't do this, we would
-	 * sit here and spin through the
-	 * list forever.
-	 */
-	if (clearit) {
-	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
-	    bridge_t               *bridge = pcibr_soft->bs_base;
-	    bridgereg_t             b_int_enable;
-	    bridgereg_t		    mask = 1 << wrap->iw_intr;
-	    unsigned long           s;
-
-	    s = pcibr_lock(pcibr_soft);
-	    b_int_enable = bridge->b_int_enable;
-	    b_int_enable &= ~mask;
-	    bridge->b_int_enable = b_int_enable;
-	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	    pcibr_unlock(pcibr_soft, s);
-	    return;
-	}
-}
-
-/* =====================================================================
- *    ERROR HANDLING
- */
-
-#ifdef	DEBUG
-#ifdef	ERROR_DEBUG
-#define BRIDGE_PIOERR_TIMEOUT	100	/* Timeout with ERROR_DEBUG defined */
-#else
-#define BRIDGE_PIOERR_TIMEOUT	40	/* Timeout in debug mode  */
-#endif
-#else
-#define BRIDGE_PIOERR_TIMEOUT	1	/* Timeout in non-debug mode                            */
-#endif
-
-LOCAL void
-print_bridge_errcmd(uint32_t cmdword, char *errtype)
-{
-#ifdef SUPPORT_PRINTING_R_FORMAT
-    PRINT_WARNING(
-	    "	Bridge %s error command word register %R",
-	    errtype, cmdword, xio_cmd_bits);
-#else
-    PRINT_WARNING(
-	    "	Bridge %s error command word register 0x%x",
-	    errtype, cmdword);
-#endif
-}
-
-LOCAL char             *pcibr_isr_errs[] =
-{
-    "", "", "", "", "", "", "", "",
-    "08: GIO non-contiguous byte enable in crosstalk packet",
-    "09: PCI to Crosstalk read request timeout",
-    "10: PCI retry operation count exhausted.",
-    "11: PCI bus device select timeout",
-    "12: PCI device reported parity error",
-    "13: PCI Address/Cmd parity error ",
-    "14: PCI Bridge detected parity error",
-    "15: PCI abort condition",
-    "16: SSRAM parity error",
-    "17: LLP Transmitter Retry count wrapped",
-    "18: LLP Transmitter side required Retry",
-    "19: LLP Receiver retry count wrapped",
-    "20: LLP Receiver check bit error",
-    "21: LLP Receiver sequence number error",
-    "22: Request packet overflow",
-    "23: Request operation not supported by bridge",
-    "24: Request packet has invalid address for bridge widget",
-    "25: Incoming request xtalk command word error bit set or invalid sideband",
-    "26: Incoming response xtalk command word error bit set or invalid sideband",
-    "27: Framing error, request cmd data size does not match actual",
-    "28: Framing error, response cmd data size does not match actual",
-    "29: Unexpected response arrived",
-    "30: Access to SSRAM beyond device limits",
-    "31: Multiple errors occurred",
-};
-
-/*
- * PCI Bridge Error interrupt handling.
- * This routine gets invoked from system interrupt dispatcher
- * and is responsible for invoking appropriate error handler,
- * depending on the type of error.
- * This IS a duplicate of bridge_errintr defined specfic to IP30.
- * There are some minor differences in terms of the return value and
- * parameters passed. One of these two should be removed at some point
- * of time.
- */
-/*ARGSUSED */
-void
-pcibr_error_dump(pcibr_soft_t pcibr_soft)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             int_status;
-    int                     i;
-
-    int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
-
-    PRINT_ALERT( "%s PCI BRIDGE ERROR: int_status is 0x%X",
-	    pcibr_soft->bs_name, int_status);
-
-    for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
-	if (int_status & (1 << i)) {
-	    PRINT_WARNING( "%s", pcibr_isr_errs[i]);
-	}
-    }
-
-    if (int_status & BRIDGE_ISR_XTALK_ERROR) {
-	print_bridge_errcmd(bridge->b_wid_err_cmdword, "");
-
-	PRINT_WARNING("   Bridge error address 0x%lx",
-		(((uint64_t) bridge->b_wid_err_upper << 32) |
-		 bridge->b_wid_err_lower));
-
-	print_bridge_errcmd(bridge->b_wid_aux_err, "Aux");
-
-	if (int_status & (BRIDGE_ISR_BAD_XRESP_PKT | BRIDGE_ISR_RESP_XTLK_ERR)) {
-	    PRINT_WARNING("	Bridge response buffer: dev-num %d buff-num %d addr 0x%lx\n",
-		    ((bridge->b_wid_resp_upper >> 20) & 0x3),
-		    ((bridge->b_wid_resp_upper >> 16) & 0xF),
-		    (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32) |
-		     bridge->b_wid_resp_lower));
-	}
-    }
-    if (int_status & BRIDGE_ISR_SSRAM_PERR)
-	PRINT_WARNING("   Bridge SSRAM parity error register 0x%x",
-		bridge->b_ram_perr);
-
-    if (int_status & BRIDGE_ISR_PCIBUS_ERROR) {
-	PRINT_WARNING("   PCI/GIO error upper address register 0x%x",
-		bridge->b_pci_err_upper);
-
-	PRINT_WARNING("   PCI/GIO error lower address register 0x%x",
-		bridge->b_pci_err_lower);
-    }
-    if (int_status & BRIDGE_ISR_ERROR_FATAL) {
-	PRINT_PANIC("PCI Bridge Error interrupt killed the system");
-	/*NOTREACHED */
-    } else {
-	PRINT_ALERT( "Non-fatal Error in Bridge..");
-    }
-}
-
-#define PCIBR_ERRINTR_GROUP(error)	\
-		(( error & (BRIDGE_IRR_PCI_GRP|BRIDGE_IRR_GIO_GRP)
-
-uint32_t
-pcibr_errintr_group(uint32_t error)
-{
-    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
-
-    if (error & BRIDGE_IRR_PCI_GRP)
-	group |= BRIDGE_IRR_PCI_GRP_CLR;
-    if (error & BRIDGE_IRR_SSRAM_GRP)
-	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
-    if (error & BRIDGE_IRR_LLP_GRP)
-	group |= BRIDGE_IRR_LLP_GRP_CLR;
-    if (error & BRIDGE_IRR_REQ_DSP_GRP)
-	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
-    if (error & BRIDGE_IRR_RESP_BUF_GRP)
-	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
-    if (error & BRIDGE_IRR_CRP_GRP)
-	group |= BRIDGE_IRR_CRP_GRP_CLR;
-
-    return group;
-
-}
-
-
-/* pcibr_pioerr_check():
- *	Check to see if this pcibr has a PCI PIO
- *	TIMEOUT error; if so, clear it and bump
- *	the timeout-count on any piomaps that
- *	could cover the address.
- */
-static void
-pcibr_pioerr_check(pcibr_soft_t soft)
-{
-    bridge_t		   *bridge;
-    bridgereg_t		    b_int_status;
-    bridgereg_t		    b_pci_err_lower;
-    bridgereg_t		    b_pci_err_upper;
-    iopaddr_t		    pci_addr;
-    pciio_slot_t	    slot;
-    pcibr_piomap_t	    map;
-    iopaddr_t		    base;
-    size_t		    size;
-    unsigned		    win;
-    int			    func;
-
-    bridge = soft->bs_base;
-    b_int_status = bridge->b_int_status;
-    if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	b_pci_err_lower = bridge->b_pci_err_lower;
-	b_pci_err_upper = bridge->b_pci_err_upper;
-	b_int_status = bridge->b_int_status;
-	if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	    bridge->b_int_rst_stat = (BRIDGE_IRR_PCI_GRP_CLR|
-				      BRIDGE_IRR_MULTI_CLR);
-
-	    pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
-	    pci_addr = (pci_addr << 32) | b_pci_err_lower;
-
-	    slot = 8;
-	    while (slot-- > 0) {
-		int 		nfunc = soft->bs_slot[slot].bss_ninfo;
-		pcibr_info_h	pcibr_infoh = soft->bs_slot[slot].bss_infos;
-
-		for (func = 0; func < nfunc; func++) {
-		    pcibr_info_t 	pcibr_info = pcibr_infoh[func];
-
-		    if (!pcibr_info)
-			continue;
-
-		    for (map = pcibr_info->f_piomap;
-			 map != NULL; map = map->bp_next) {
-			base = map->bp_pciaddr;
-			size = map->bp_mapsz;
-			win = map->bp_space - PCIIO_SPACE_WIN(0);
-			if (win < 6)
-			    base += 
-				soft->bs_slot[slot].bss_window[win].bssw_base;
-			else if (map->bp_space == PCIIO_SPACE_ROM)
-			    base += pcibr_info->f_rbase;
-			if ((pci_addr >= base) && (pci_addr < (base + size)))
-			    atomic_inc(map->bp_toc);
-		    }
-		}
-	    }
-	}
-    }
-}
-
-/*
- * PCI Bridge Error interrupt handler.
- *      This gets invoked, whenever a PCI bridge sends an error interrupt.
- *      Primarily this servers two purposes.
- *              - If an error can be handled (typically a PIO read/write
- *                error, we try to do it silently.
- *              - If an error cannot be handled, we die violently.
- *      Interrupt due to PIO errors:
- *              - Bridge sends an interrupt, whenever a PCI operation
- *                done by the bridge as the master fails. Operations could
- *                be either a PIO read or a PIO write.
- *                PIO Read operation also triggers a bus error, and it's
- *                We primarily ignore this interrupt in that context..
- *                For PIO write errors, this is the only indication.
- *                and we have to handle with the info from here.
- *
- *                So, there is no way to distinguish if an interrupt is
- *                due to read or write error!.
- */
-
-
-LOCAL void
-pcibr_error_intr_handler(intr_arg_t arg)
-{
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge;
-    bridgereg_t             int_status;
-    bridgereg_t             err_status;
-    int                     i;
-
-    /* REFERENCED */
-    bridgereg_t             disable_errintr_mask = 0;
-
-#if PCIBR_SOFT_LIST
-    /* IP27 seems to be handing us junk.
-     */
-    {
-	pcibr_list_p            entry;
-
-	entry = pcibr_list;
-	while (1) {
-	    if (entry == NULL) {
-		printk("pcibr_error_intr_handler:\n"
-			"\tparameter (0x%p) is not a pcibr_soft!",
-			arg);
-		PRINT_PANIC("Invalid parameter to pcibr_error_intr_handler");
-	    }
-	    if ((intr_arg_t) entry->bl_soft == arg)
-		break;
-	    entry = entry->bl_next;
-	}
-    }
-#endif
-    pcibr_soft = (pcibr_soft_t) arg;
-    bridge = pcibr_soft->bs_base;
-
-    /*
-     * pcibr_error_intr_handler gets invoked whenever bridge encounters
-     * an error situation, and the interrupt for that error is enabled.
-     * This routine decides if the error is fatal or not, and takes
-     * action accordingly.
-     *
-     * In one case there is a need for special action.
-     * In case of PIO read/write timeouts due to user level, we do
-     * get an error interrupt. In this case, way to handle would
-     * be to start a timeout. If the error was due to "read", bus
-     * error handling code takes care of it. If error is due to write,
-     * it's handled at timeout
-     */
-
-    /* int_status is which bits we have to clear;
-     * err_status is the bits we haven't handled yet.
-     */
-
-    int_status = bridge->b_int_status &  ~BRIDGE_ISR_INT_MSK;
-    err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
-
-    if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
-	/*
-	 * No error bit set!!.
-	 */
-	return;
-    }
-    /* If we have a PCIBUS_PIOERR,
-     * hand it to the logger but otherwise
-     * ignore the event.
-     */
-    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	pcibr_pioerr_check(pcibr_soft);
-	err_status &= ~BRIDGE_ISR_PCIBUS_PIOERR;
-	int_status &= ~BRIDGE_ISR_PCIBUS_PIOERR;
-    }
-
-
-    if (err_status) {
-	struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
-
-	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) {
-	    if (err_status & (1 << i)) {
-		uint32_t              errrate = 0;
-		uint32_t              errcount = 0;
-		uint32_t              errinterval = 0, current_tick = 0;
-		int                     panic_on_llp_tx_retry = 0;
-		int                     is_llp_tx_retry_intr = 0;
-
-		bs_estat->bs_errcount_total++;
-
-#ifdef LATER
-		current_tick = lbolt;
-#else
-		current_tick = 0;
-#endif
-		errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
-		errcount = (bs_estat->bs_errcount_total -
-			    bs_estat->bs_lasterr_snapshot);
-
-		is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i));
-
-		/* On a non-zero error rate (which is equivalent to
-		 * to 100 errors /sec at least) for the LLP transmitter
-		 * retry interrupt we need to panic the system
-		 * to prevent potential data corruption .
-		 * NOTE : errcount is being compared to PCIBR_ERRTIME_THRESHOLD
-		 * to make sure that we are not seing cases like x error
-		 * interrupts per y ticks for very low x ,y (x > y ) which
-		 * makes error rate be > 100 /sec.
-		 */
-
-		/* Check for the divide by zero condition while
-		 * calculating the error rates.
-		 */
-
-		if (errinterval) {
-		    errrate = errcount / errinterval;
-		    /* If able to calculate error rate
-		     * on a LLP transmitter retry interrupt check
-		     * if the error rate is nonzero and we have seen
-		     * a certain minimum number of errors.
-		     */
-		    if (is_llp_tx_retry_intr &&
-			errrate &&
-			(errcount >= PCIBR_ERRTIME_THRESHOLD)) {
-			panic_on_llp_tx_retry = 1;
-		    }
-		} else {
-		    errrate = 0;
-		    /* Since we are not able to calculate the
-		     * error rate check if we exceeded a certain
-		     * minimum number of errors for LLP transmitter
-		     * retries. Note that this can only happen
-		     * within the first tick after the last snapshot.
-		     */
-		    if (is_llp_tx_retry_intr &&
-			(errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
-			panic_on_llp_tx_retry = 1;
-		    }
-		}
-		if (panic_on_llp_tx_retry) {
-		    static uint32_t       last_printed_rate;
-
-		    if (errrate > last_printed_rate) {
-			last_printed_rate = errrate;
-			/* Print the warning only if the error rate
-			 * for the transmitter retry interrupt
-			 * exceeded the previously printed rate.
-			 */
-			PRINT_WARNING(
-				"%s: %s, Excessive error interrupts : %d/tick\n",
-				pcibr_soft->bs_name,
-				pcibr_isr_errs[i],
-				errrate);
-
-		    }
-		    /*
-		     * Update snapshot, and time
-		     */
-		    bs_estat->bs_lasterr_timestamp = current_tick;
-		    bs_estat->bs_lasterr_snapshot =
-			bs_estat->bs_errcount_total;
-
-		}
-		/*
-		 * If the error rate is high enough, print the error rate.
-		 */
-		if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
-
-		    if (errrate > PCIBR_ERRRATE_THRESHOLD) {
-			PRINT_NOTICE( "%s: %s, Error rate %d/tick",
-				pcibr_soft->bs_name,
-				pcibr_isr_errs[i],
-				errrate);
-			/*
-			 * Update snapshot, and time
-			 */
-			bs_estat->bs_lasterr_timestamp = current_tick;
-			bs_estat->bs_lasterr_snapshot =
-			    bs_estat->bs_errcount_total;
-		    }
-		}
-		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
-		    /*
-		     * We have seen a fairly large number of errors of
-		     * this type. Let's disable the interrupt. But flash
-		     * a message about the interrupt being disabled.
-		     */
-		    PRINT_NOTICE(
-			    "%s Disabling error interrupt type %s. Error count %d",
-			    pcibr_soft->bs_name,
-			    pcibr_isr_errs[i],
-			    bs_estat->bs_errcount_total);
-		    disable_errintr_mask |= (1 << i);
-		}
-	    }
-	}
-    }
-
-    if (disable_errintr_mask) {
-	/*
-	 * Disable some high frequency errors as they
-	 * could eat up too much cpu time.
-	 */
-	bridge->b_int_enable &= ~disable_errintr_mask;
-    }
-    /*
-     * If we leave the PROM cacheable, T5 might
-     * try to do a cache line sized writeback to it,
-     * which will cause a BRIDGE_ISR_INVLD_ADDR.
-     */
-    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
-	(0x00000000 == bridge->b_wid_err_upper) &&
-	(0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
-	(0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
-	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
-    }
-#if defined (PCIBR_LLP_CONTROL_WAR)
-    /*
-     * The bridge bug, where the llp_config or control registers
-     * need to be read back after being written, affects an MP
-     * system since there could be small windows between writing
-     * the register and reading it back on one cpu while another
-     * cpu is fielding an interrupt. If we run into this scenario,
-     * workaround the problem by ignoring the error. (bug 454474)
-     * pcibr_llp_control_war_cnt keeps an approximate number of
-     * times we saw this problem on a system.
-     */
-
-    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
-	((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
-	 == (BRIDGE_INT_RST_STAT & 0xff0))) {
-#ifdef LATER
-	if (kdebug)
-	    PRINT_NOTICE( "%s bridge: ignoring llp/control address interrupt",
-		    pcibr_soft->bs_name);
-#endif
-	pcibr_llp_control_war_cnt++;
-	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
-    }
-#endif				/* PCIBR_LLP_CONTROL_WAR */
-
-#ifdef	DEBUG
-	if (err_status & BRIDGE_ISR_ERROR_DUMP)
-	    pcibr_error_dump(pcibr_soft);
-#else	
-	if (err_status & BRIDGE_ISR_ERROR_FATAL) {
-	    printk("BRIDGE ERR STATUS 0x%x\n", err_status);
-	    pcibr_error_dump(pcibr_soft);
-	}
-#endif
-
-    /*
-     * We can't return without re-enabling the interrupt, since
-     * it would cause problems for devices like IOC3 (Lost
-     * interrupts ?.). So, just cleanup the interrupt, and
-     * use saved values later..
-     */
-    bridge->b_int_rst_stat = pcibr_errintr_group(int_status);
-}
-
-/*
- * pcibr_addr_toslot
- *      Given the 'pciaddr' find out which slot this address is
- *      allocated to, and return the slot number.
- *      While we have the info handy, construct the
- *      function number, space code and offset as well.
- *
- * NOTE: if this routine is called, we don't know whether
- * the address is in CFG, MEM, or I/O space. We have to guess.
- * This will be the case on PIO stores, where the only way
- * we have of getting the address is to check the Bridge, which
- * stores the PCI address but not the space and not the xtalk
- * address (from which we could get it).
- */
-LOCAL int
-pcibr_addr_toslot(pcibr_soft_t pcibr_soft,
-		  iopaddr_t pciaddr,
-		  pciio_space_t *spacep,
-		  iopaddr_t *offsetp,
-		  pciio_function_t *funcp)
-{
-    int                     s, f=0, w;
-    iopaddr_t               base;
-    size_t                  size;
-    pciio_piospace_t        piosp;
-
-    /*
-     * Check if the address is in config space
-     */
-
-    if ((pciaddr >= BRIDGE_CONFIG_BASE) && (pciaddr < BRIDGE_CONFIG_END)) {
-
-	if (pciaddr >= BRIDGE_CONFIG1_BASE)
-	    pciaddr -= BRIDGE_CONFIG1_BASE;
-	else
-	    pciaddr -= BRIDGE_CONFIG_BASE;
-
-	s = pciaddr / BRIDGE_CONFIG_SLOT_SIZE;
-	pciaddr %= BRIDGE_CONFIG_SLOT_SIZE;
-
-	if (funcp) {
-	    f = pciaddr / 0x100;
-	    pciaddr %= 0x100;
-	}
-	if (spacep)
-	    *spacep = PCIIO_SPACE_CFG;
-	if (offsetp)
-	    *offsetp = pciaddr;
-	if (funcp)
-	    *funcp = f;
-
-	return s;
-    }
-    for (s = 0; s < 8; s++) {
-	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
-	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
-
-	for (f = 0; f < nf; f++) {
-	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
-
-	    if (!pcibr_info)
-		continue;
-	    for (w = 0; w < 6; w++) {
-		if (pcibr_info->f_window[w].w_space
-		    == PCIIO_SPACE_NONE) {
-		    continue;
-		}
-		base = pcibr_info->f_window[w].w_base;
-		size = pcibr_info->f_window[w].w_size;
-
-		if ((pciaddr >= base) && (pciaddr < (base + size))) {
-		    if (spacep)
-			*spacep = PCIIO_SPACE_WIN(w);
-		    if (offsetp)
-			*offsetp = pciaddr - base;
-		    if (funcp)
-			*funcp = f;
-		    return s;
-		}			/* endif match */
-	    }				/* next window */
-	}				/* next func */
-    }					/* next slot */
-
-    /*
-     * Check if the address was allocated as part of the
-     * pcibr_piospace_alloc calls.
-     */
-    for (s = 0; s < 8; s++) {
-	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
-	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
-
-	for (f = 0; f < nf; f++) {
-	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
-
-	    if (!pcibr_info)
-		continue;
-	    piosp = pcibr_info->f_piospace;
-	    while (piosp) {
-		if ((piosp->start <= pciaddr) &&
-		    ((piosp->count + piosp->start) > pciaddr)) {
-		    if (spacep)
-			*spacep = piosp->space;
-		    if (offsetp)
-			*offsetp = pciaddr - piosp->start;
-		    return s;
-		}			/* endif match */
-		piosp = piosp->next;
-	    }				/* next piosp */
-	}				/* next func */
-    }					/* next slot */
-
-    /*
-     * Some other random address on the PCI bus ...
-     * we have no way of knowing whether this was
-     * a MEM or I/O access; so, for now, we just
-     * assume that the low 1G is MEM, the next
-     * 3G is I/O, and anything above the 4G limit
-     * is obviously MEM.
-     */
-
-    if (spacep)
-	*spacep = ((pciaddr < (1ul << 30)) ? PCIIO_SPACE_MEM :
-		   (pciaddr < (4ul << 30)) ? PCIIO_SPACE_IO :
-		   PCIIO_SPACE_MEM);
-    if (offsetp)
-	*offsetp = pciaddr;
-
-    return PCIIO_SLOT_NONE;
-
-}
-
-LOCAL void
-pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    ASSERT(error_code & IOECODE_PIO);
-    error_code = error_code;
-
-    bridge->b_int_rst_stat =
-	(BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR);
-    (void) bridge->b_wid_tflush;	/* flushbus */
-}
-
-/*
- * pcibr_error_extract
- *      Given the 'pcibr vertex handle' find out which slot
- *      the bridge status error address (from pcibr_soft info
- *      hanging off the vertex)
- *      allocated to, and return the slot number.
- *      While we have the info handy, construct the
- *      space code and offset as well.
- *
- * NOTE: if this routine is called, we don't know whether
- * the address is in CFG, MEM, or I/O space. We have to guess.
- * This will be the case on PIO stores, where the only way
- * we have of getting the address is to check the Bridge, which
- * stores the PCI address but not the space and not the xtalk
- * address (from which we could get it).
- *
- * XXX- this interface has no way to return the function
- * number on a multifunction card, even though that data
- * is available.
- */
-
-pciio_slot_t
-pcibr_error_extract(devfs_handle_t pcibr_vhdl,
-		    pciio_space_t *spacep,
-		    iopaddr_t *offsetp)
-{
-    pcibr_soft_t            pcibr_soft = 0;
-    iopaddr_t               bserr_addr;
-    bridge_t               *bridge;
-    pciio_slot_t            slot = PCIIO_SLOT_NONE;
-    arbitrary_info_t	    rev;
-
-    /* Do a sanity check as to whether we really got a 
-     * bridge vertex handle.
-     */
-    if (hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &rev) !=
-	GRAPH_SUCCESS) 
-	return(slot);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (pcibr_soft) {
-	bridge = pcibr_soft->bs_base;
-	bserr_addr =
-	    bridge->b_pci_err_lower |
-	    ((uint64_t) (bridge->b_pci_err_upper &
-			   BRIDGE_ERRUPPR_ADDRMASK) << 32);
-
-	slot = pcibr_addr_toslot(pcibr_soft, bserr_addr,
-				 spacep, offsetp, NULL);
-    }
-    return slot;
-}
-
-/*ARGSUSED */
-void
-pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
-{
-    /*
-     * XXX
-     * Device failed to handle error. Take steps to
-     * disable this device ? HOW TO DO IT ?
-     *
-     * If there are any Read response buffers associated
-     * with this device, it's time to get them back!!
-     *
-     * We can disassociate any interrupt level associated
-     * with this device, and disable that interrupt level
-     *
-     * For now it's just a place holder
-     */
-}
-
-/*
- * pcibr_pioerror
- *      Handle PIO error that happened at the bridge pointed by pcibr_soft.
- *
- *      Queries the Bus interface attached to see if the device driver
- *      mapping the device-number that caused error can handle the
- *      situation. If so, it will clean up any error, and return
- *      indicating the error was handled. If the device driver is unable
- *      to handle the error, it expects the bus-interface to disable that
- *      device, and takes any steps needed here to take away any resources
- *      associated with this device.
- */
-
-#define BEM_ADD_STR(s)	printk("%s", (s))
-#ifdef SUPPORT_SGI_CMN_ERR_STUFF
-#define BEM_ADD_VAR(v)	printk("\t%20s: 0x%x\n", #v, (v))
-#define BEM_ADD_REG(r)	printk("\t%20s: %R\n", #r, (r), r ## _desc)
-
-#define BEM_ADD_NSPC(n,s)	printk("\t%20s: %R\n", n, s, space_desc)
-#else
-#define BEM_ADD_VAR(v)	
-#define BEM_ADD_REG(r)	
-#define BEM_ADD_NSPC(n,s)
-#endif
-#define BEM_ADD_SPC(s)		BEM_ADD_NSPC(#s, s)
-
-/* BEM_ADD_IOE doesn't dump the whole ioerror, it just
- * decodes the PCI specific portions -- we count on our
- * callers to dump the raw IOE data.
- */
-#ifdef LATER
-#define BEM_ADD_IOE(ioe)						\
-	do {								\
-	    if (IOERROR_FIELDVALID(ioe, busspace)) {			\
-		unsigned		spc;				\
-		unsigned		win;				\
-									\
-		spc = IOERROR_GETVALUE(ioe, busspace);			\
-		win = spc - PCIIO_SPACE_WIN(0);				\
-									\
-		switch (spc) {						\
-		case PCIIO_SPACE_CFG:					\
-		    printk("\tPCI Slot %d Func %d CFG space Offset 0x%x\n",	\
-	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		case PCIIO_SPACE_IO:					\
-		    printk("\tPCI I/O space  Offset 0x%x\n",		\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		case PCIIO_SPACE_MEM:					\
-		case PCIIO_SPACE_MEM32:					\
-		case PCIIO_SPACE_MEM64:					\
-		    printk("\tPCI MEM space Offset 0x%x\n",		\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		default:						\
-		    if (win < 6) {					\
-		    printk("\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\
-	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-			    win,					\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    }							\
-		    break;						\
-		}							\
-	    }								\
-	} while (0)
-#else
-#define BEM_ADD_IOE(ioe)
-#endif
-
-/*ARGSUSED */
-LOCAL int
-pcibr_pioerror(
-		  pcibr_soft_t pcibr_soft,
-		  int error_code,
-		  ioerror_mode_t mode,
-		  ioerror_t *ioe)
-{
-    int                     retval = IOERROR_HANDLED;
-
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    bridgereg_t             bridge_int_status;
-    bridgereg_t             bridge_pci_err_lower;
-    bridgereg_t             bridge_pci_err_upper;
-    bridgereg_t             bridge_pci_err_addr;
-
-    iopaddr_t               bad_xaddr;
-
-    pciio_space_t           raw_space;	/* raw PCI space */
-    iopaddr_t               raw_paddr;	/* raw PCI address */
-
-    pciio_space_t           space;	/* final PCI space */
-    pciio_slot_t            slot;	/* final PCI slot, if appropriate */
-    pciio_function_t        func;	/* final PCI func, if appropriate */
-    iopaddr_t               offset;	/* final PCI offset */
-    
-    int                     cs, cw, cf;
-    pciio_space_t           wx;
-    iopaddr_t               wb;
-    size_t                  ws;
-    iopaddr_t               wl;
-
-
-    /*
-     * We expect to have an "xtalkaddr" coming in,
-     * and need to construct the slot/space/offset.
-     */
-
-#ifdef LATER
-    bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr);
-#else
-    bad_xaddr = -1;
-#endif
-
-    slot = PCIIO_SLOT_NONE;
-    func = PCIIO_FUNC_NONE;
-    raw_space = PCIIO_SPACE_NONE;
-    raw_paddr = 0;
-
-    if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) &&
-	(bad_xaddr < BRIDGE_TYPE1_CFG)) {
-	raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0;
-	slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
-	raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
-	raw_space = PCIIO_SPACE_CFG;
-    }
-    if ((bad_xaddr >= BRIDGE_TYPE1_CFG) &&
-	(bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) {
-	/* Type 1 config space:
-	 * slot and function numbers not known.
-	 * Perhaps we can read them back?
-	 */
-	raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG;
-	raw_space = PCIIO_SPACE_CFG;
-    }
-    if ((bad_xaddr >= BRIDGE_DEVIO0) &&
-	(bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) {
-	int                     x;
-
-	raw_paddr = bad_xaddr - BRIDGE_DEVIO0;
-	x = raw_paddr / BRIDGE_DEVIO_OFF;
-	raw_paddr %= BRIDGE_DEVIO_OFF;
-	/* first two devio windows are double-sized */
-	if ((x == 1) || (x == 3))
-	    raw_paddr += BRIDGE_DEVIO_OFF;
-	if (x > 0)
-	    x--;
-	if (x > 1)
-	    x--;
-	/* x is which devio reg; no guarantee
-	 * PCI slot x will be responding.
-	 * still need to figure out who decodes
-	 * space/offset on the bus.
-	 */
-	raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
-	if (raw_space == PCIIO_SPACE_NONE) {
-	    /* Someone got an error because they
-	     * accessed the PCI bus via a DevIO(x)
-	     * window that pcibr has not yet assigned
-	     * to any specific PCI address. It is
-	     * quite possible that the Device(x)
-	     * register has been changed since they
-	     * made their access, but we will give it
-	     * our best decode shot.
-	     */
-	    raw_space = pcibr_soft->bs_slot[x].bss_device
-		& BRIDGE_DEV_DEV_IO_MEM
-		? PCIIO_SPACE_MEM
-		: PCIIO_SPACE_IO;
-	    raw_paddr +=
-		(pcibr_soft->bs_slot[x].bss_device &
-		 BRIDGE_DEV_OFF_MASK) <<
-		BRIDGE_DEV_OFF_ADDR_SHFT;
-	} else
-	    raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
-	raw_space = PCIIO_SPACE_MEM32;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
-	raw_space = PCIIO_SPACE_MEM64;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
-	raw_space = PCIIO_SPACE_IO;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
-    }
-    space = raw_space;
-    offset = raw_paddr;
-
-    if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
-	/* we've got a space/offset but not which
-	 * PCI slot decodes it. Check through our
-	 * notions of which devices decode where.
-	 *
-	 * Yes, this "duplicates" some logic in
-	 * pcibr_addr_toslot; the difference is,
-	 * this code knows which space we are in,
-	 * and can really really tell what is
-	 * going on (no guessing).
-	 */
-
-	for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) {
-	    int                     nf = pcibr_soft->bs_slot[cs].bss_ninfo;
-	    pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
-
-	    for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
-		pcibr_info_t            pcibr_info = pcibr_infoh[cf];
-
-		if (!pcibr_info)
-		    continue;
-		for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
-		    if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
-			((wb = pcibr_info->f_window[cw].w_base) != 0) &&
-			((ws = pcibr_info->f_window[cw].w_size) != 0) &&
-			((wl = wb + ws) > wb) &&
-			((wb <= offset) && (wl > offset))) {
-			/* MEM, MEM32 and MEM64 need to
-			 * compare as equal ...
-			 */
-			if ((wx == space) ||
-			    (((wx == PCIIO_SPACE_MEM) ||
-			      (wx == PCIIO_SPACE_MEM32) ||
-			      (wx == PCIIO_SPACE_MEM64)) &&
-			     ((space == PCIIO_SPACE_MEM) ||
-			      (space == PCIIO_SPACE_MEM32) ||
-			      (space == PCIIO_SPACE_MEM64)))) {
-			    slot = cs;
-			    func = cf;
-			    space = PCIIO_SPACE_WIN(cw);
-			    offset -= wb;
-			}		/* endif window space match */
-		    }			/* endif window valid and addr match */
-		}			/* next window unless slot set */
-	    }				/* next func unless slot set */
-	}				/* next slot unless slot set */
-	/* XXX- if slot is still -1, no PCI devices are
-	 * decoding here using their standard PCI BASE
-	 * registers. This would be a really good place
-	 * to cross-coordinate with the pciio PCI
-	 * address space allocation routines, to find
-	 * out if this address is "allocated" by any of
-	 * our subsidiary devices.
-	 */
-    }
-    /* Scan all piomap records on this PCI bus to update
-     * the TimeOut Counters on all matching maps. If we
-     * don't already know the slot number, take it from
-     * the first matching piomap. Note that we have to
-     * compare maps against raw_space and raw_paddr
-     * since space and offset could already be
-     * window-relative.
-     *
-     * There is a chance that one CPU could update
-     * through this path, and another CPU could also
-     * update due to an interrupt. Closing this hole
-     * would only result in the possibility of some
-     * errors never getting logged at all, and since the
-     * use for bp_toc is as a logical test rather than a
-     * strict count, the excess counts are not a
-     * problem.
-     */
-    for (cs = 0; cs < 8; ++cs) {
-	int 		nf = pcibr_soft->bs_slot[cs].bss_ninfo;
-	pcibr_info_h	pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
-
-	for (cf = 0; cf < nf; cf++) {
-	    pcibr_info_t 	pcibr_info = pcibr_infoh[cf];
-	    pcibr_piomap_t	map;    
-
-	    if (!pcibr_info)
-		continue;
-
-	    for (map = pcibr_info->f_piomap;
-	     map != NULL; map = map->bp_next) {
-	    wx = map->bp_space;
-	    wb = map->bp_pciaddr;
-	    ws = map->bp_mapsz;
-	    cw = wx - PCIIO_SPACE_WIN(0);
-	    if (cw < 6) {
-		wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
-		wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
-	    }
-	    if (wx == PCIIO_SPACE_ROM) {
-		wb += pcibr_info->f_rbase;
-		wx = PCIIO_SPACE_MEM;
-	    }
-	    if ((wx == PCIIO_SPACE_MEM32) ||
-		(wx == PCIIO_SPACE_MEM64))
-		wx = PCIIO_SPACE_MEM;
-	    wl = wb + ws;
-	    if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
-		atomic_inc(map->bp_toc);
-		if (slot == PCIIO_SLOT_NONE) {
-		    slot = cs;
-		    space = map->bp_space;
-		    if (cw < 6)
-			offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
-		}
-	    }
-	    }
-	}
-    }
-
-    if (space != PCIIO_SPACE_NONE) {
-	if (slot != PCIIO_SLOT_NONE) {
-#ifdef LATER
-	    if (func != PCIIO_FUNC_NONE)
-		IOERROR_SETVALUE(ioe, widgetdev, 
-				 pciio_widgetdev_create(slot,func));
-	    else
-    		IOERROR_SETVALUE(ioe, widgetdev, 
-				 pciio_widgetdev_create(slot,0));
-#else
-            if (func != PCIIO_FUNC_NONE) {
-                IOERROR_SETVALUE(ioe, widgetdev,
-                                 pciio_widgetdev_create(slot,func));
-            } else {
-                IOERROR_SETVALUE(ioe, widgetdev,
-                                 pciio_widgetdev_create(slot,0));
-	    }
-#endif
-	}
-
-	IOERROR_SETVALUE(ioe, busspace, space);
-	IOERROR_SETVALUE(ioe, busaddr, offset);
-    }
-    if (mode == MODE_DEVPROBE) {
-	/*
-	 * During probing, we don't really care what the
-	 * error is. Clean up the error in Bridge, notify
-	 * subsidiary devices, and return success.
-	 */
-	pcibr_error_cleanup(pcibr_soft, error_code);
-
-	/* if appropriate, give the error handler for this slot
-	 * a shot at this probe access as well.
-	 */
-	return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
-	    pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-    }
-    /*
-     * If we don't know what "PCI SPACE" the access
-     * was targeting, we may have problems at the
-     * Bridge itself. Don't touch any bridge registers,
-     * and do complain loudly.
-     */
-
-    if (space == PCIIO_SPACE_NONE) {
-	printk("XIO Bus Error at %s\n"
-		"\taccess to XIO bus offset 0x%lx\n"
-		"\tdoes not correspond to any PCI address\n",
-		pcibr_soft->bs_name, bad_xaddr);
-
-	/* caller will dump contents of ioe struct */
-	return IOERROR_XTALKLEVEL;
-    }
-    /*
-     * Read the PCI Bridge error log registers.
-     */
-    bridge_int_status = bridge->b_int_status;
-    bridge_pci_err_upper = bridge->b_pci_err_upper;
-    bridge_pci_err_lower = bridge->b_pci_err_lower;
-
-    bridge_pci_err_addr =
-	bridge_pci_err_lower
-	| (((iopaddr_t) bridge_pci_err_upper
-	    & BRIDGE_ERRUPPR_ADDRMASK) << 32);
-
-    /*
-     * Actual PCI Error handling situation.
-     * Typically happens when a user level process accesses
-     * PCI space, and it causes some error.
-     *
-     * Due to PCI Bridge implementation, we get two indication
-     * for a read error: an interrupt and a Bus error.
-     * We like to handle read error in the bus error context.
-     * But the interrupt comes and goes before bus error
-     * could make much progress. (NOTE: interrupd does
-     * come in _after_ bus error processing starts. But it's
-     * completed by the time bus error code reaches PCI PIO
-     * error handling.
-     * Similarly write error results in just an interrupt,
-     * and error handling has to be done at interrupt level.
-     * There is no way to distinguish at interrupt time, if an
-     * error interrupt is due to read/write error..
-     */
-
-    /* We know the xtalk addr, the raw PCI bus space,
-     * the raw PCI bus address, the decoded PCI bus
-     * space, the offset within that space, and the
-     * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
-     * is known to be involved).
-     */
-
-    /*
-     * Hand the error off to the handler registered
-     * for the slot that should have decoded the error,
-     * or to generic PCI handling (if pciio decides that
-     * such is appropriate).
-     */
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-
-    if (retval != IOERROR_HANDLED) {
-
-	/* Generate a generic message for IOERROR_UNHANDLED
-	 * since the subsidiary handlers were silent, and
-	 * did no recovery.
-	 */
-	if (retval == IOERROR_UNHANDLED) {
-	    retval = IOERROR_PANIC;
-
-	    /* we may or may not want to print some of this,
-	     * depending on debug level and which error code.
-	     */
-
-	    PRINT_ALERT(
-		    "PIO Error on PCI Bus %s",
-		    pcibr_soft->bs_name);
-	    /* this decodes part of the ioe; our caller
-	     * will dump the raw details in DEBUG and
-	     * kdebug kernels.
-	     */
-	    BEM_ADD_IOE(ioe);
-	}
-#if defined(FORCE_ERRORS)
-	if (0) {
-#elif !DEBUG
-	if (kdebug) {
-#endif
-	    /*
-	       * dump raw data from bridge
-	     */
-
-	    BEM_ADD_STR("DEBUG DATA -- raw info from Bridge ASIC:\n");
-	    BEM_ADD_REG(bridge_int_status);
-	    BEM_ADD_VAR(bridge_pci_err_upper);
-	    BEM_ADD_VAR(bridge_pci_err_lower);
-	    BEM_ADD_VAR(bridge_pci_err_addr);
-	    BEM_ADD_SPC(raw_space);
-	    BEM_ADD_VAR(raw_paddr);
-	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {
-
-#ifdef LATER
-		slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, 
-								 widgetdev));
-		func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, 
-								 widgetdev));
-#else
-		slot = -1;
-		func = -1;
-#endif
-		if (slot < 8) {
-#ifdef SUPPORT_SGI_CMN_ERR_STUFF
-		    bridgereg_t             device = bridge->b_device[slot].reg;
-#endif
-
-		    BEM_ADD_VAR(slot);
-		    BEM_ADD_VAR(func);
-		    BEM_ADD_REG(device);
-		}
-	    }
-#if !DEBUG || defined(FORCE_ERRORS)
-	}
-#endif
-
-	/*
-	 * Since error could not be handled at lower level,
-	 * error data logged has not  been cleared.
-	 * Clean up errors, and
-	 * re-enable bridge to interrupt on error conditions.
-	 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
-	 * dependent on INT_ENABLE register. This write just makes sure
-	 * that if the interrupt was enabled, we do get the interrupt.
-	 *
-	 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
-	 *      a group of interrupts. If while handling this error,
-	 *      some other error has occurred, that would be
-	 *      implicitly cleared by this write.
-	 *      Need a way to ensure we don't inadvertently clear some
-	 *      other errors.
-	 */
-#ifdef LATER
-	if (IOERROR_FIELDVALID(ioe, widgetdev))
-	    pcibr_device_disable(pcibr_soft, 
-				 pciio_widgetdev_slot_get(
-					  IOERROR_GETVALUE(ioe, widgetdev)));
-#endif
-
-	if (mode == MODE_DEVUSERERROR)
-	    pcibr_error_cleanup(pcibr_soft, error_code);
-    }
-    return retval;
-}
-
-/*
- * bridge_dmaerror
- *      Some error was identified in a DMA transaction.
- *      This routine will identify the <device, address> that caused the error,
- *      and try to invoke the appropriate bus service to handle this.
- */
-
-#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT)
-
-int
-pcibr_dmard_error(
-		     pcibr_soft_t pcibr_soft,
-		     int error_code,
-		     ioerror_mode_t mode,
-		     ioerror_t *ioe)
-{
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             bus_lowaddr, bus_uppraddr;
-    int                     retval = 0;
-    int                     bufnum;
-
-    /*
-     * In case of DMA errors, bridge should have logged the
-     * address that caused the error.
-     * Look up the address, in the bridge error registers, and
-     * take appropriate action
-     */
-#ifdef LATER
-    ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid);
-    ASSERT(bridge);
-#endif
-
-    /*
-     * read error log registers
-     */
-    bus_lowaddr = bridge->b_wid_resp_lower;
-    bus_uppraddr = bridge->b_wid_resp_upper;
-
-    bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
-    IOERROR_SETVALUE(ioe, widgetdev, 
-		     pciio_widgetdev_create(
-				    BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
-				    0));
-    IOERROR_SETVALUE(ioe, busaddr,
-		     (bus_lowaddr |
-		      ((iopaddr_t)
-		       (bus_uppraddr &
-			BRIDGE_ERRUPPR_ADDRMASK) << 32)));
-
-    /*
-     * need to ensure that the xtalk address in ioe
-     * maps to PCI error address read from bridge.
-     * How to convert PCI address back to Xtalk address ?
-     * (better idea: convert XTalk address to PCI address
-     * and then do the compare!)
-     */
-
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-    if (retval != IOERROR_HANDLED)
-#ifdef LATER
-	pcibr_device_disable(pcibr_soft, 
-			     pciio_widgetdev_slot_get(
-				      IOERROR_GETVALUE(ioe,widgetdev)));
-#else
-	pcibr_device_disable(pcibr_soft,
-			     pciio_widgetdev_slot_get(-1));
-#endif
-
-    /*
-     * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
-     * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
-     * not is dependent on INT_ENABLE register. This write just makes sure
-     * that if the interrupt was enabled, we do get the interrupt.
-     */
-    bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
-
-    /*
-     * Also, release the "bufnum" back to buffer pool that could be re-used.
-     * This is done by "disabling" the buffer for a moment, then restoring
-     * the original assignment.
-     */
-
-    {
-	reg_p                   regp;
-	bridgereg_t             regv;
-	bridgereg_t             mask;
-
-	regp = (bufnum & 1)
-	    ? &bridge->b_odd_resp
-	    : &bridge->b_even_resp;
-
-	mask = 0xF << ((bufnum >> 1) * 4);
-
-	regv = *regp;
-	*regp = regv & ~mask;
-	*regp = regv;
-    }
-
-    return retval;
-}
-
-/*
- * pcibr_dmawr_error:
- *      Handle a dma write error caused by a device attached to this bridge.
- *
- *      ioe has the widgetnum, widgetdev, and memaddr fields updated
- *      But we don't know the PCI address that corresponds to "memaddr"
- *      nor do we know which device driver is generating this address.
- *
- *      There is no easy way to find out the PCI address(es) that map
- *      to a specific system memory address. Bus handling code is also
- *      of not much help, since they don't keep track of the DMA mapping
- *      that have been handed out.
- *      So it's a dead-end at this time.
- *
- *      If translation is available, we could invoke the error handling
- *      interface of the device driver.
- */
-/*ARGSUSED */
-int
-pcibr_dmawr_error(
-		     pcibr_soft_t pcibr_soft,
-		     int error_code,
-		     ioerror_mode_t mode,
-		     ioerror_t *ioe)
-{
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    int                     retval;
-
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-
-#ifdef LATER
-    if (retval != IOERROR_HANDLED) {
-	pcibr_device_disable(pcibr_soft, 
-			     pciio_widgetdev_slot_get(
-				      IOERROR_GETVALUE(ioe, widgetdev)));
-
-    }
-#endif
-    return retval;
-}
-
-/*
- * Bridge error handler.
- *      Interface to handle all errors that involve bridge in some way.
- *
- *      This normally gets called from xtalk error handler.
- *      ioe has different set of fields set depending on the error that
- *      was encountered. So, we have a bit field indicating which of the
- *      fields are valid.
- *
- * NOTE: This routine could be operating in interrupt context. So,
- *      don't try to sleep here (till interrupt threads work!!)
- */
-LOCAL int
-pcibr_error_handler(
-		       error_handler_arg_t einfo,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioe)
-{
-    pcibr_soft_t            pcibr_soft;
-    int                     retval = IOERROR_BADERRORCODE;
-
-    pcibr_soft = (pcibr_soft_t) einfo;
-
-    /* If we are in the action handling phase clean out the error state
-     * on the xswitch.
-     */
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-    if (e_state == ERROR_STATE_ACTION)
-	(void)error_state_set(xconn_vhdl, ERROR_STATE_NONE);
-#endif
-
-#if DEBUG && ERROR_DEBUG
-    printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name);
-#endif
-
-    ASSERT(pcibr_soft != NULL);
-
-    if (error_code & IOECODE_PIO)
-	retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
-
-    if (error_code & IOECODE_DMA) {
-	if (error_code & IOECODE_READ) {
-	    /*
-	     * DMA read error occurs when a device attached to the bridge
-	     * tries to read some data from system memory, and this
-	     * either results in a timeout or access error.
-	     * First case is indicated by the bit "XREAD_REQ_TOUT"
-	     * and second case by "RESP_XTALK_ERROR" bit in bridge error
-	     * interrupt status register.
-	     *
-	     * pcibr_error_intr_handler would get invoked first, and it has
-	     * the responsibility of calling pcibr_error_handler with
-	     * suitable parameters.
-	     */
-
-	    retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
-	}
-	if (error_code & IOECODE_WRITE) {
-	    /*
-	     * A device attached to this bridge has been generating
-	     * bad DMA writes. Find out the device attached, and
-	     * slap on it's wrist.
-	     */
-
-	    retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
-	}
-    }
-    return retval;
-
-}
-
-/*
- * Reenable a device after handling the error.
- * This is called by the lower layers when they wish to be reenabled
- * after an error.
- * Note that each layer would be calling the previous layer to reenable
- * first, before going ahead with their own re-enabling.
- */
-
-int
-pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    ASSERT(error_code & IOECODE_PIO);
-
-    /* If the error is not known to be a write,
-     * we have to call devenable.
-     * write errors are isolated to the bridge.
-     */
-    if (!(error_code & IOECODE_WRITE)) {
-	devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-	int                     rc;
-
-	rc = xtalk_error_devenable(xconn_vhdl, pciio_slot, error_code);
-	if (rc != IOERROR_HANDLED)
-	    return rc;
-    }
-    pcibr_error_cleanup(pcibr_soft, error_code);
-    return IOERROR_HANDLED;
-}
-
-/* =====================================================================
- *    CONFIGURATION MANAGEMENT
- */
-/*ARGSUSED */
-void
-pcibr_provider_startup(devfs_handle_t pcibr)
-{
-}
-
-/*ARGSUSED */
-void
-pcibr_provider_shutdown(devfs_handle_t pcibr)
-{
-}
-
-int
-pcibr_reset(devfs_handle_t conn)
-{
-    pciio_info_t            pciio_info = pciio_info_get(conn);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             ctlreg;
-    unsigned                cfgctl[8];
-    unsigned long           s;
-    int                     f, nf;
-    pcibr_info_h            pcibr_infoh;
-    pcibr_info_t            pcibr_info;
-    int                     win;
-
-    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
-	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
-	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
-    }
-    if (pciio_slot < 4) {
-	s = pcibr_lock(pcibr_soft);
-	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
-	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
-	for (f = 0; f < nf; ++f)
-	    if (pcibr_infoh[f])
-		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
-
-	ctlreg = bridge->b_wid_control;
-	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
-	/* XXX delay? */
-	bridge->b_wid_control = ctlreg;
-	/* XXX delay? */
-
-	for (f = 0; f < nf; ++f)
-	    if ((pcibr_info = pcibr_infoh[f]))
-		for (win = 0; win < 6; ++win)
-		    if (pcibr_info->f_window[win].w_base != 0)
-			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
-			    pcibr_info->f_window[win].w_base;
-	for (f = 0; f < nf; ++f)
-	    if (pcibr_infoh[f])
-		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
-	pcibr_unlock(pcibr_soft, s);
-
-	return 0;
-    }
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    PRINT_WARNING( "%v: pcibr_reset unimplemented for slot %d\n",
-	    conn, pciio_slot);
-#endif
-    return -1;
-}
-
-pciio_endian_t
-pcibr_endian_set(devfs_handle_t pconn_vhdl,
-		 pciio_endian_t device_end,
-		 pciio_endian_t desired_end)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridgereg_t             devreg;
-    unsigned long           s;
-
-    /*
-     * Bridge supports hardware swapping; so we can always
-     * arrange for the caller's desired endianness.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-    if (device_end != desired_end)
-	devreg |= BRIDGE_DEV_SWAP_BITS;
-    else
-	devreg &= ~BRIDGE_DEV_SWAP_BITS;
-
-    /* NOTE- if we ever put SWAP bits
-     * onto the disabled list, we will
-     * have to change the logic here.
-     */
-    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-
-	bridge->b_device[pciio_slot].reg = devreg;
-	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-#if DEBUG && PCIBR_DEV_DEBUG
-    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
-#endif
-
-    return desired_end;
-}
-
-/* This (re)sets the GBR and REALTIME bits and also keeps track of how
- * many sets are outstanding. Reset succeeds only if the number of outstanding
- * sets == 1.
- */
-int
-pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
-			pciio_slot_t pciio_slot,
-			pciio_priority_t device_prio)
-{
-    unsigned long           s;
-    int                    *counter;
-    bridgereg_t             rtbits = 0;
-    bridgereg_t             devreg;
-    int                     rc = PRIO_SUCCESS;
-
-    /* in dual-slot configurations, the host and the
-     * guest have separate DMA resources, so they
-     * have separate requirements for priority bits.
-     */
-
-    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
-
-    /*
-     * Bridge supports PCI notions of LOW and HIGH priority
-     * arbitration rings via a "REAL_TIME" bit in the per-device
-     * Bridge register. The "GBR" bit controls access to the GBR
-     * ring on the xbow. These two bits are (re)set together.
-     *
-     * XXX- Bug in Rev B Bridge Si:
-     * Symptom: Prefetcher starts operating incorrectly. This happens
-     * due to corruption of the address storage ram in the prefetcher
-     * when a non-real time PCI request is pulled and a real-time one is
-     * put in it's place. Workaround: Use only a single arbitration ring
-     * on PCI bus. GBR and RR can still be uniquely used per
-     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
-     */
-
-    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
-	rtbits |= BRIDGE_DEV_RT;
-
-    /* NOTE- if we ever put DEV_RT or DEV_GBR on
-     * the disabled list, we will have to take
-     * it into account here.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-    if (device_prio == PCI_PRIO_HIGH) {
-	if ((++*counter == 1)) {
-	    if (rtbits)
-		devreg |= rtbits;
-	    else
-		rc = PRIO_FAIL;
-	}
-    } else if (device_prio == PCI_PRIO_LOW) {
-	if (*counter <= 0)
-	    rc = PRIO_FAIL;
-	else if (--*counter == 0)
-	    if (rtbits)
-		devreg &= ~rtbits;
-    }
-    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-
-	bridge->b_device[pciio_slot].reg = devreg;
-	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-    return rc;
-}
-
-pciio_priority_t
-pcibr_priority_set(devfs_handle_t pconn_vhdl,
-		   pciio_priority_t device_prio)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
-
-    return device_prio;
-}
-
-/*
- * Interfaces to allow special (e.g. SGI) drivers to set/clear
- * Bridge-specific device flags.  Many flags are modified through
- * PCI-generic interfaces; we don't allow them to be directly
- * manipulated here.  Only flags that at this point seem pretty
- * Bridge-specific can be set through these special interfaces.
- * We may add more flags as the need arises, or remove flags and
- * create PCI-generic interfaces as the need arises.
- *
- * Returns 0 on failure, 1 on success
- */
-int
-pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
-		       pcibr_device_flags_t flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridgereg_t             set = 0;
-    bridgereg_t             clr = 0;
-
-    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
-
-    if (flags & PCIBR_WRITE_GATHER)
-	set |= BRIDGE_DEV_PMU_WRGA_EN;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	clr |= BRIDGE_DEV_PMU_WRGA_EN;
-
-    if (flags & PCIBR_WRITE_GATHER)
-	set |= BRIDGE_DEV_DIR_WRGA_EN;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	clr |= BRIDGE_DEV_DIR_WRGA_EN;
-
-    if (flags & PCIBR_PREFETCH)
-	set |= BRIDGE_DEV_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	clr |= BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	set |= BRIDGE_DEV_PRECISE;
-    if (flags & PCIBR_NOPRECISE)
-	clr |= BRIDGE_DEV_PRECISE;
-
-    if (flags & PCIBR_BARRIER)
-	set |= BRIDGE_DEV_BARRIER;
-    if (flags & PCIBR_NOBARRIER)
-	clr |= BRIDGE_DEV_BARRIER;
-
-    if (flags & PCIBR_64BIT)
-	set |= BRIDGE_DEV_DEV_SIZE;
-    if (flags & PCIBR_NO64BIT)
-	clr |= BRIDGE_DEV_DEV_SIZE;
-
-    if (set || clr) {
-	bridgereg_t             devreg;
-	unsigned long           s;
-
-	s = pcibr_lock(pcibr_soft);
-	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-	devreg = (devreg & ~clr) | set;
-	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	    bridge_t               *bridge = pcibr_soft->bs_base;
-
-	    bridge->b_device[pciio_slot].reg = devreg;
-	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	}
-	pcibr_unlock(pcibr_soft, s);
-#if DEBUG && PCIBR_DEV_DEBUG
-	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
-#endif
-    }
-    return (1);
-}
-
-#ifdef LITTLE_ENDIAN
-/*
- * on sn-ia we need to twiddle the addresses going out
- * the pci bus because we use the unswizzled synergy space
- * (the alternative is to use the swizzled synergy space
- * and byte swap the data)
- */
-#define	CB(b,r)	(((volatile uint8_t *) b)[((r)^4)])
-#define	CS(b,r)	(((volatile uint16_t *) b)[((r^4)/2)])
-#define	CW(b,r)	(((volatile uint32_t *) b)[((r^4)/4)])
-#else
-#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
-#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
-#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
-#endif /* LITTLE_ENDIAN */
-
-
-LOCAL                   cfg_p
-pcibr_config_addr(devfs_handle_t conn,
-		  unsigned reg)
-{
-    pcibr_info_t            pcibr_info;
-    pciio_slot_t            pciio_slot;
-    pciio_function_t        pciio_func;
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge;
-    cfg_p                   cfgbase = (cfg_p)0;
-
-    pcibr_info = pcibr_info_get(conn);
-
-    pciio_slot = pcibr_info->f_slot;
-    if (pciio_slot == PCIIO_SLOT_NONE)
-	pciio_slot = PCI_TYPE1_SLOT(reg);
-
-    pciio_func = pcibr_info->f_func;
-    if (pciio_func == PCIIO_FUNC_NONE)
-	pciio_func = PCI_TYPE1_FUNC(reg);
-
-    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-
-    bridge = pcibr_soft->bs_base;
-
-    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
-
-    return cfgbase;
-}
-
-uint64_t
-pcibr_config_get(devfs_handle_t conn,
-		 unsigned reg,
-		 unsigned size)
-{
-    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
-			       PCI_TYPE1_REG(reg), size);
-}
-
-LOCAL uint64_t
-do_pcibr_config_get(
-		       cfg_p cfgbase,
-		       unsigned reg,
-		       unsigned size)
-{
-    unsigned                value;
-
-   
-    value = CW(cfgbase, reg);
-
-    if (reg & 3)
-	value >>= 8 * (reg & 3);
-    if (size < 4)
-	value &= (1 << (8 * size)) - 1;
-
-    return value;
-}
-
-void
-pcibr_config_set(devfs_handle_t conn,
-		 unsigned reg,
-		 unsigned size,
-		 uint64_t value)
-{
-    do_pcibr_config_set(pcibr_config_addr(conn, reg),
-			PCI_TYPE1_REG(reg), size, value);
-}
-
-LOCAL void
-do_pcibr_config_set(cfg_p cfgbase,
-		    unsigned reg,
-		    unsigned size,
-		    uint64_t value)
-{
-    switch (size) {
-    case 1:
-	CB(cfgbase, reg) = value;
-	break;
-    case 2:
-	if (reg & 1) {
-	    CB(cfgbase, reg) = value;
-	    CB(cfgbase, reg + 1) = value >> 8;
-	} else
-	    CS(cfgbase, reg) = value;
-	break;
-    case 3:
-	if (reg & 1) {
-	    CB(cfgbase, reg) = value;
-	    CS(cfgbase, (reg + 1)) = value >> 8;
-	} else {
-	    CS(cfgbase, reg) = value;
-	    CB(cfgbase, reg + 2) = value >> 16;
-	}
-	break;
-
-    case 4:
-	CW(cfgbase, reg) = value;
-	break;
-    }
-}
-
-pciio_provider_t        pcibr_provider =
-{
-    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
-    (pciio_piomap_free_f *) pcibr_piomap_free,
-    (pciio_piomap_addr_f *) pcibr_piomap_addr,
-    (pciio_piomap_done_f *) pcibr_piomap_done,
-    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
-    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
-    (pciio_piospace_free_f *) pcibr_piospace_free,
-
-    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
-    (pciio_dmamap_free_f *) pcibr_dmamap_free,
-    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
-    (pciio_dmamap_list_f *) pcibr_dmamap_list,
-    (pciio_dmamap_done_f *) pcibr_dmamap_done,
-    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
-    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
-    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
-    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
-    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
-
-    (pciio_intr_alloc_f *) pcibr_intr_alloc,
-    (pciio_intr_free_f *) pcibr_intr_free,
-    (pciio_intr_connect_f *) pcibr_intr_connect,
-    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
-    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
-
-    (pciio_provider_startup_f *) pcibr_provider_startup,
-    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
-    (pciio_reset_f *) pcibr_reset,
-    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
-    (pciio_endian_set_f *) pcibr_endian_set,
-    (pciio_priority_set_f *) pcibr_priority_set,
-    (pciio_config_get_f *) pcibr_config_get,
-    (pciio_config_set_f *) pcibr_config_set,
-
-    (pciio_error_devenable_f *) pcibr_error_devenable,
-    (pciio_error_extract_f *) pcibr_error_extract,
-
-#ifdef LATER
-    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
-    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
-#else
-    (pciio_driver_reg_callback_f *) 0,
-    (pciio_driver_unreg_callback_f *) 0,
-#endif
-    (pciio_device_unregister_f 	*) pcibr_device_unregister,
-    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
-};
-
-LOCAL                   pcibr_hints_t
-pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
-{
-    arbitrary_info_t        ainfo = 0;
-    graph_error_t	    rv;
-    pcibr_hints_t           hint;
-
-    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
-
-    if (alloc && (rv != GRAPH_SUCCESS)) {
-
-	NEW(hint);
-	hint->rrb_alloc_funct = NULL;
-	hint->ph_intr_bits = NULL;
-	rv = hwgraph_info_add_LBL(xconn_vhdl, 
-				  INFO_LBL_PCIBR_HINTS, 	
-				  (arbitrary_info_t) hint);
-	if (rv != GRAPH_SUCCESS)
-	    goto abnormal_exit;
-
-	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
-	
-	if (rv != GRAPH_SUCCESS)
-	    goto abnormal_exit;
-
-	if (ainfo != (arbitrary_info_t) hint)
-	    goto abnormal_exit;
-    }
-    return (pcibr_hints_t) ainfo;
-
-abnormal_exit:
-#ifdef LATER
-    printf("SHOULD NOT BE HERE\n");
-#endif
-    DEL(hint);
-    return(NULL);
-
-}
-
-void
-pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_rrb_fixed = mask;
-#if DEBUG
-    else
-	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
-{
-    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
-}
-
-void
-pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
-		     pciio_slot_t host,
-		     pciio_slot_t guest)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_host_slot[guest] = host + 1;
-#if DEBUG
-    else
-	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
-		      pcibr_intr_bits_f *xxx_intr_bits)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_intr_bits = xxx_intr_bits;
-#if DEBUG
-    else
-	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
-	       "\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->rrb_alloc_funct = rrb_alloc_funct;
-}
-
-void
-pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_hands_off = 1;
-#if DEBUG
-    else
-	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
-		    pciio_slot_t slot,
-		    uint64_t subdevs)
-{
-    arbitrary_info_t        ainfo = 0;
-    char                    sdname[16];
-    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
-
-    sprintf(sdname, "pci/%d", slot);
-    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
-    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
-#if DEBUG
-	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
-		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
-#endif
-	return;
-    }
-    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
-    if (ainfo == 0) {
-	uint64_t                *subdevp;
-
-	NEW(subdevp);
-	if (!subdevp) {
-#if DEBUG
-	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
-		    "\t%p\n", pconn_vhdl);
-#endif
-	    return;
-	}
-	*subdevp = subdevs;
-	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
-	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
-	if (ainfo == (arbitrary_info_t) subdevp)
-	    return;
-	DEL(subdevp);
-	if (ainfo == (arbitrary_info_t) NULL) {
-#if DEBUG
-	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
-		    "\t%p\n", pconn_vhdl);
-#endif
-	    return;
-	}
-#if DEBUG
-	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
-		"\t%p\n", pconn_vhdl);
-#endif
-    }
-    *(uint64_t *) ainfo = subdevs;
-}
-
-
-#ifdef LATER
-
-#include <sys/idbg.h>
-#include <sys/idbgentry.h>
-
-char *pci_space[] = {"NONE", 
-		     "ROM",
-		     "IO",
-		     "",
-		     "MEM",
-		     "MEM32",
-		     "MEM64",
-		     "CFG",
-		     "WIN0",
-		     "WIN1",
-		     "WIN2",
-		     "WIN3",
-		     "WIN4",
-		     "WIN5",
-		     "",
-		     "BAD"};
-
-void
-idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
-{
-    pcibr_info_t	pcibr_info = pcibr_infoh[func];
-    char		name[MAXDEVNAME];
-    int			win;
-    
-    if (!pcibr_info)
-	return;
-    qprintf("Per-slot Function Info\n");
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(name, "%v", pcibr_info->f_vertex);
-#endif
-    qprintf("\tSlot Name : %s\n",name);
-    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
-    qprintf("Slot : %d ", pcibr_info->f_slot);
-    qprintf("Function : %d ", pcibr_info->f_func);
-    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
-    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(name, "%v", pcibr_info->f_master);
-#endif
-    qprintf("\tBus provider : %s\n",name);
-    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
-    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
-	    pcibr_info->f_efunc,pcibr_info->f_einfo);
-    for(win = 0 ; win < 6 ; win++) 
-	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
-		win,pci_space[pcibr_info->f_window[win].w_space],
-		pcibr_info->f_window[win].w_base,
-		pcibr_info->f_window[win].w_size);
-
-    qprintf("\tRom base 0x%x size 0x%x\n", 
-	    pcibr_info->f_rbase,pcibr_info->f_rsize);
-
-    qprintf("\tInterrupt Bit Map\n");
-    qprintf("\t\tPCI Int#\tBridge Pin#\n");
-    for (win = 0 ; win < 4; win++)
-	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
-    qprintf("\n");
-}
-
-
-void
-idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
-{
-    pcibr_soft_slot_t	pss;
-    char		slot_conn_name[MAXDEVNAME];
-    int			func;
-
-    pss = &pcibr_soft->bs_slot[slot];
-    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
-    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
-    qprintf("\tHost Slot : %d\n",pss->host_slot);
-    sprintf(slot_conn_name, "%v", pss->slot_conn);
-    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
-    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
-    for (func = 0; func < pss->bss_ninfo; func++)
-	idbg_pss_func(pss->bss_infos,func);
-    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
-    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
-    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
-    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
-	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
-    
-    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
-	    "d32_base 0x%x d32_flags 0x%x\n",
-	    pss->bss_d64_base, pss->bss_d64_flags,
-	    pss->bss_d32_base, pss->bss_d32_flags);
-    
-    qprintf("\tExt ATEs active ? %s", 
-	    atomic_read(&pss->bss_ext_ates_active) ? "yes" : "no");
-    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
-    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
-
-    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
-	    pcibr_soft->bs_rrb_valid[slot],
-	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-		
-}
-
-int	ips = 0;
-
-void
-idbg_pss(pcibr_soft_t pcibr_soft)
-{
-    pciio_slot_t	slot;
-
-    
-    if (ips >= 0 && ips < 8)
-	idbg_pss_info(pcibr_soft,ips);
-    else if (ips < 0)
-	for (slot = 0; slot < 8; slot++) 
-	    idbg_pss_info(pcibr_soft,slot);
-    else
-	qprintf("Invalid ips %d\n",ips);
-}
-
-#endif /* LATER */
-
-int
-pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-	
-
-    return xtalk_dma_enabled(pcibr_soft->bs_conn);
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/pciio.c linux/arch/ia64/sn/io/pciio.c
--- linux.orig/arch/ia64/sn/io/pciio.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/pciio.c	2002-08-01 06:42:43.000000000 +0000
@@ -4,14 +4,18 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #define	USRPCI	0
 
+#include <linux/init.h>
 #include <linux/types.h>
 #include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/xtalk/xbow.h>	/* Must be before iograph.h to get MAX_PORT_NUM */
@@ -25,13 +29,16 @@
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pciio_private.h>
 #include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/pci/pci_bus_cvlink.h>
+#include <asm/sn/simulator.h>
 
 #define DEBUG_PCIIO
 #undef DEBUG_PCIIO	/* turn this on for yet more console output */
 
 
-#define NEW(ptr)	(ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
-#define DEL(ptr)	(kfree(ptr))
+#define GET_NEW(ptr)	(ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
+#define DO_DEL(ptr)	(kfree(ptr))
 
 char                    pciio_info_fingerprint[] = "pciio_info";
 
@@ -45,7 +52,11 @@
 
 	switch (len) {
 		case 4:
+#ifdef CONFIG_IA64_SGI_SN1
 			new_addr = (void *)(((u64) addr)^4);
+#else
+			new_addr = (void *) addr;
+#endif
 			ret = ia64_sn_probe_io_slot((long)new_addr, len, (void *)ptr);
 			break;
 		default:
@@ -63,6 +74,14 @@
 get_console_nasid(void)
 {
 	extern nasid_t console_nasid;
+	if (console_nasid < 0) {
+		console_nasid = ia64_sn_get_console_nasid();
+		if (console_nasid < 0) {
+// ZZZ What do we do if we don't get a console nasid on the hardware????
+			if (IS_RUNNING_ON_SIMULATOR() )
+				console_nasid = master_nasid;
+		}
+	} 
 	return console_nasid;
 }
 
@@ -105,7 +124,7 @@
  * completely disappear.
  */
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1)
 /*
  *    For the moment, we will assume that IP27
  *      only use Bridge ASICs to provide PCI support.
@@ -115,7 +134,7 @@
 #define CAST_PIOMAP(x)		((pcibr_piomap_t)(x))
 #define CAST_DMAMAP(x)		((pcibr_dmamap_t)(x))
 #define CAST_INTR(x)		((pcibr_intr_t)(x))
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
 /* =====================================================================
  *    Function Table of Contents
@@ -150,14 +169,11 @@
 
 pciio_intr_t            pciio_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
 void                    pciio_intr_free(pciio_intr_t);
-int                     pciio_intr_connect(pciio_intr_t, intr_func_t, intr_arg_t, void *thread);
+int                     pciio_intr_connect(pciio_intr_t);
 void                    pciio_intr_disconnect(pciio_intr_t);
 devfs_handle_t            pciio_intr_cpu_get(pciio_intr_t);
 
 void			pciio_slot_func_to_name(char *, pciio_slot_t, pciio_function_t);
-static pciio_info_t     pciio_cardinfo_get(devfs_handle_t, pciio_slot_t);
-int                     pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
-int                     pciio_error_devenable(devfs_handle_t, int);
 
 void                    pciio_provider_startup(devfs_handle_t);
 void                    pciio_provider_shutdown(devfs_handle_t);
@@ -257,7 +273,7 @@
 #if defined(SUPPORT_PRINTING_V_FORMAT)
 	PRINT_PANIC("%v: provider_fns == NULL", dev);
 #else
-	PRINT_PANIC("0x%x: provider_fns == NULL", dev);
+	PRINT_PANIC("0x%p: provider_fns == NULL", (void *)dev);
 #endif
 
     return provider_fns;
@@ -575,13 +591,10 @@
  * Returns 0 on success, returns <0 on failure.
  */
 int
-pciio_intr_connect(pciio_intr_t intr_hdl,	/* pciio intr resource handle */
-		   intr_func_t intr_func,	/* pciio intr handler */
-		   intr_arg_t intr_arg,	/* arg to intr handler */
-		   void *thread)
-{					/* intr thread to use */
+pciio_intr_connect(pciio_intr_t intr_hdl)	/* pciio intr resource handle */
+{
     return INTR_FUNC(intr_hdl, intr_connect)
-	(CAST_INTR(intr_hdl), intr_func, intr_arg, thread);
+	(CAST_INTR(intr_hdl));
 }
 
 /*
@@ -605,10 +618,6 @@
 	(CAST_INTR(intr_hdl));
 }
 
-/* =====================================================================
- *          ERROR MANAGEMENT
- */
-
 void
 pciio_slot_func_to_name(char		       *name,
 			pciio_slot_t		slot,
@@ -630,193 +639,6 @@
 	sprintf(name, "%d%c", slot, 'a'+func);
 }
 
-/*
- * pciio_cardinfo_get
- *
- * Get the pciio info structure corresponding to the
- * specified PCI "slot" (we like it when the same index
- * number is used for the PCI IDSEL, the REQ/GNT pair,
- * and the interrupt line being used for INTA. We like
- * it so much we call it the slot number).
- */
-static pciio_info_t
-pciio_cardinfo_get(
-		      devfs_handle_t pciio_vhdl,
-		      pciio_slot_t pci_slot)
-{
-    char                    namebuf[16];
-    pciio_info_t	    info = 0;
-    devfs_handle_t	    conn;
-
-    pciio_slot_func_to_name(namebuf, pci_slot, PCIIO_FUNC_NONE);
-    if (GRAPH_SUCCESS ==
-	hwgraph_traverse(pciio_vhdl, namebuf, &conn)) {
-	info = pciio_info_chk(conn);
-	hwgraph_vertex_unref(conn);
-    }
-
-    return info;
-}
-
-/*
- * pciio_error_handler:
- * dispatch an error to the appropriate
- * pciio connection point, or process
- * it as a generic pci error.
- * Yes, the first parameter is the
- * provider vertex at the middle of
- * the bus; we get to the pciio connect
- * point using the ioerror widgetdev field.
- *
- * This function is called by the
- * specific PCI provider, after it has figured
- * out where on the PCI bus (including which slot,
- * if it can tell) the error came from.
- */
-/*ARGSUSED */
-int
-pciio_error_handler(
-		       devfs_handle_t pciio_vhdl,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioerror)
-{
-    pciio_info_t            pciio_info;
-    devfs_handle_t            pconn_vhdl;
-#if USRPCI
-    devfs_handle_t            usrpci_v;
-#endif
-    pciio_slot_t            slot;
-
-    int                     retval;
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-    error_state_t	    e_state;
-#endif
-
-#if DEBUG && ERROR_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-    printk("%v: pciio_error_handler\n", pciio_vhdl);
-#else
-    printk("0x%x: pciio_error_handler\n", pciio_vhdl);
-#endif
-#endif
-
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-    IOERR_PRINTF(printk("%v: PCI Bus Error: Error code: %d Error mode: %d\n",
-			 pciio_vhdl, error_code, mode));
-#else
-    IOERR_PRINTF(printk("0x%x: PCI Bus Error: Error code: %d Error mode: %d\n",
-			 pciio_vhdl, error_code, mode));
-#endif
-
-    /* If there is an error handler sitting on
-     * the "no-slot" connection point, give it
-     * first crack at the error. NOTE: it is
-     * quite possible that this function may
-     * do further refining of the ioerror.
-     */
-    pciio_info = pciio_cardinfo_get(pciio_vhdl, PCIIO_SLOT_NONE);
-    if (pciio_info && pciio_info->c_efunc) {
-	pconn_vhdl = pciio_info_dev_get(pciio_info);
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-	e_state = error_state_get(pciio_vhdl);
-
-	if (e_state == ERROR_STATE_ACTION)
-	    (void)error_state_set(pciio_vhdl, ERROR_STATE_NONE);
-
-	if (error_state_set(pconn_vhdl,e_state) ==
-	    ERROR_RETURN_CODE_CANNOT_SET_STATE)
-	    return(IOERROR_UNHANDLED);
-#endif
-	retval = pciio_info->c_efunc
-	    (pciio_info->c_einfo, error_code, mode, ioerror);
-	if (retval != IOERROR_UNHANDLED)
-	    return retval;
-    }
-
-    /* Is the error associated with a particular slot?
-     */
-    if (IOERROR_FIELDVALID(ioerror, widgetdev)) {
-	/*
-	 * NOTE : 
-	 * widgetdev is a 4byte value encoded as slot in the higher order
-	 * 2 bytes and function in the lower order 2 bytes.
-	 */
-#ifdef LATER
-	slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioerror, widgetdev));
-#else
-	slot = 0;
-#endif
-
-	/* If this slot has an error handler,
-	 * deliver the error to it.
-	 */
-	pciio_info = pciio_cardinfo_get(pciio_vhdl, slot);
-	if (pciio_info != NULL) {
-	    if (pciio_info->c_efunc != NULL) {
-
-		pconn_vhdl = pciio_info_dev_get(pciio_info);
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-		e_state = error_state_get(pciio_vhdl);
-
-
-		if (e_state == ERROR_STATE_ACTION)
-		    (void)error_state_set(pciio_vhdl, ERROR_STATE_NONE);
-
-
-
-		if (error_state_set(pconn_vhdl,e_state) ==
-		    ERROR_RETURN_CODE_CANNOT_SET_STATE)
-		    return(IOERROR_UNHANDLED);
-#endif
-		retval = pciio_info->c_efunc
-		    (pciio_info->c_einfo, error_code, mode, ioerror);
-		if (retval != IOERROR_UNHANDLED)
-		    return retval;
-	    }
-
-#if USRPCI
-	    /* If the USRPCI driver is available and
-	     * knows about this connection point,
-	     * deliver the error to it.
-	     *
-	     * OK to use pconn_vhdl here, even though we
-	     * have already UNREF'd it, since we know that
-	     * it is not going away.
-	     */
-	    pconn_vhdl = pciio_info_dev_get(pciio_info);
-	    if (GRAPH_SUCCESS ==
-		hwgraph_traverse(pconn_vhdl, EDGE_LBL_USRPCI, &usrpci_v)) {
-		retval = usrpci_error_handler
-		    (usrpci_v, error_code, IOERROR_GETVALUE(ioerror, busaddr));
-		hwgraph_vertex_unref(usrpci_v);
-		if (retval != IOERROR_UNHANDLED) {
-		    /*
-		     * This unref is not needed.  If this code is called often enough,
-		     * the system will crash, due to vertex reference count reaching 0,
-		     * causing vertex to be unallocated.  -jeremy
-		     * hwgraph_vertex_unref(pconn_vhdl);
-		     */
-		    return retval;
-		}
-	    }
-#endif
-	}
-    }
-
-    return (mode == MODE_DEVPROBE)
-	? IOERROR_HANDLED	/* probes are OK */
-	: IOERROR_UNHANDLED;	/* otherwise, foo! */
-}
-
-int
-pciio_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
-{
-    return DEV_FUNC(pconn_vhdl, error_devenable)
-	(pconn_vhdl, error_code);
-    /* no cleanup specific to this layer. */
-}
-
 /* =====================================================================
  *          CONFIGURATION MANAGEMENT
  */
@@ -856,12 +678,12 @@
 
 #if DEBUG
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-    PRINT_ALERT("%v: pciio_endian_set is going away.\n"
+    printk(KERN_ALERT  "%v: pciio_endian_set is going away.\n"
 	    "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
 	    "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
 	    dev);
 #else
-    PRINT_ALERT("0x%x: pciio_endian_set is going away.\n"
+    printk(KERN_ALERT  "0x%x: pciio_endian_set is going away.\n"
 	    "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
 	    "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
 	    dev);
@@ -944,14 +766,6 @@
 /* =====================================================================
  *          GENERIC PCI SUPPORT FUNCTIONS
  */
-pciio_slot_t
-pciio_error_extract(devfs_handle_t 	dev,
-		   pciio_space_t 	*space,
-		   iopaddr_t		*offset)
-{
-	ASSERT(dev != NODEV);
-	return DEV_FUNC(dev,error_extract)(dev,space,offset);
-}
 
 /*
  * Issue a hardware reset to a card.
@@ -1054,14 +868,9 @@
     }
 #endif /* DEBUG_PCIIO */
 
-#ifdef BRINGUP
     if ((pciio_info != NULL) &&
 	(pciio_info->c_fingerprint != pciio_info_fingerprint)
 	&& (pciio_info->c_fingerprint != NULL)) {
-#else
-    if ((pciio_info != NULL) &&
-	(pciio_info->c_fingerprint != pciio_info_fingerprint)) {
-#endif /* BRINGUP */
 
 	return((pciio_info_t)-1); /* Should panic .. */
     }
@@ -1388,7 +1197,7 @@
 		pciio_device_id_t device_id)
 {
     if (!pciio_info)
-	NEW(pciio_info);
+	GET_NEW(pciio_info);
     ASSERT(pciio_info != NULL);
 
     pciio_info->c_slot = slot;
@@ -1420,6 +1229,7 @@
 {
     char		name[32];
     devfs_handle_t	pconn;
+    int device_master_set(devfs_handle_t, devfs_handle_t);
 
     pciio_slot_func_to_name(name,
 			    pciio_info->c_slot,
@@ -1431,16 +1241,14 @@
 
     pciio_info->c_vertex = pconn;
     pciio_info_set(pconn, pciio_info);
-#ifdef BRINGUP
+#ifdef DEBUG_PCIIO
     {
 	int pos;
 	char dname[256];
 	pos = devfs_generate_path(pconn, dname, 256);
-#ifdef DEBUG_PCIIO
 	printk("%s : pconn path= %s \n", __FUNCTION__, &dname[pos]);
-#endif
     }
-#endif /* BRINGUP */
+#endif /* DEBUG_PCIIO */
 
     /*
      * create link to our pci provider
@@ -1520,7 +1328,6 @@
     pciio_info_t            pciio_info;
     pciio_vendor_id_t       vendor_id;
     pciio_device_id_t       device_id;
-    int pciba_attach(devfs_handle_t);
 
 
     pciio_device_inventory_add(pconn);
@@ -1536,11 +1343,6 @@
      */
     ASSERT(pciio_registry != NULL);
 
-    /*
-     * Since pciba is not called from cdl routines .. call it here.
-     */
-    pciba_attach(pconn);
-
     return(cdl_add_connpt(pciio_registry, vendor_id, device_id, pconn, drv_flags));
 }
 
@@ -1625,3 +1427,85 @@
 {
 	return DEV_FUNC(pconn_vhdl, dma_enabled)(pconn_vhdl);
 }
+
+/*
+ * These are complementary Linux interfaces that takes in a pci_dev * as the 
+ * first arguement instead of devfs_handle_t.
+ */
+iopaddr_t               snia_pciio_dmatrans_addr(struct pci_dev *, device_desc_t, paddr_t, size_t, unsigned);
+pciio_dmamap_t          snia_pciio_dmamap_alloc(struct pci_dev *, device_desc_t, size_t, unsigned);
+void                    snia_pciio_dmamap_free(pciio_dmamap_t);
+iopaddr_t               snia_pciio_dmamap_addr(pciio_dmamap_t, paddr_t, size_t);
+void                    snia_pciio_dmamap_done(pciio_dmamap_t);
+pciio_endian_t          snia_pciio_endian_set(struct pci_dev *pci_dev, pciio_endian_t device_end,
+					      pciio_endian_t desired_end);
+
+#include <linux/module.h>
+EXPORT_SYMBOL(snia_pciio_dmatrans_addr);
+EXPORT_SYMBOL(snia_pciio_dmamap_alloc);
+EXPORT_SYMBOL(snia_pciio_dmamap_free);
+EXPORT_SYMBOL(snia_pciio_dmamap_addr);
+EXPORT_SYMBOL(snia_pciio_dmamap_done);
+EXPORT_SYMBOL(snia_pciio_endian_set);
+
+pciio_endian_t
+snia_pciio_endian_set(struct pci_dev *pci_dev,
+	pciio_endian_t device_end,
+	pciio_endian_t desired_end)
+{
+	devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+	
+	return DEV_FUNC(dev, endian_set)
+		(dev, device_end, desired_end);
+}
+
+iopaddr_t
+snia_pciio_dmatrans_addr(struct pci_dev *pci_dev, /* translate for this device */
+                    device_desc_t dev_desc,     /* device descriptor */
+                    paddr_t paddr,      /* system physical address */
+                    size_t byte_count,  /* length */
+                    unsigned flags)
+{                                       /* defined in dma.h */
+
+    devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+
+    return DEV_FUNC(dev, dmatrans_addr)
+        (dev, dev_desc, paddr, byte_count, flags);
+}
+
+pciio_dmamap_t
+snia_pciio_dmamap_alloc(struct pci_dev *pci_dev,  /* set up mappings for this device */
+                   device_desc_t dev_desc,      /* device descriptor */
+                   size_t byte_count_max,       /* max size of a mapping */
+                   unsigned flags)
+{                                       /* defined in dma.h */
+
+    devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+
+    return (pciio_dmamap_t) DEV_FUNC(dev, dmamap_alloc)
+        (dev, dev_desc, byte_count_max, flags);
+}
+
+void
+snia_pciio_dmamap_free(pciio_dmamap_t pciio_dmamap)
+{
+    DMAMAP_FUNC(pciio_dmamap, dmamap_free)
+        (CAST_DMAMAP(pciio_dmamap));
+}
+
+iopaddr_t
+snia_pciio_dmamap_addr(pciio_dmamap_t pciio_dmamap,  /* use these mapping resources */
+                  paddr_t paddr,        /* map for this address */
+                  size_t byte_count)
+{                                       /* map this many bytes */
+    return DMAMAP_FUNC(pciio_dmamap, dmamap_addr)
+        (CAST_DMAMAP(pciio_dmamap), paddr, byte_count);
+}
+
+void
+snia_pciio_dmamap_done(pciio_dmamap_t pciio_dmamap)
+{
+    DMAMAP_FUNC(pciio_dmamap, dmamap_done)
+        (CAST_DMAMAP(pciio_dmamap));
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sgi_if.c linux/arch/ia64/sn/io/sgi_if.c
--- linux.orig/arch/ia64/sn/io/sgi_if.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/sgi_if.c	2002-08-01 06:42:44.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -22,7 +21,7 @@
 #include <asm/sn/slotnum.h>
 
 void *
-kmem_zalloc(size_t size, int flag)
+snia_kmem_zalloc(size_t size, int flag)
 {
         void *ptr = kmalloc(size, GFP_KERNEL);
         BZERO(ptr, size);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sgi_io_init.c linux/arch/ia64/sn/io/sgi_io_init.c
--- linux.orig/arch/ia64/sn/io/sgi_io_init.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/sgi_io_init.c	2002-08-01 06:42:27.000000000 +0000
@@ -4,26 +4,24 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_private.h>
-#include <asm/sn/synergy.h>
+#include <asm/sn/pci/pciba.h>
 #include <linux/smp.h>
 
 extern void mlreset(int );
 extern int init_hcl(void);
 extern void klgraph_hack_init(void);
-extern void per_hub_init(cnodeid_t);
 extern void hubspc_init(void);
-extern void pciba_init(void);
 extern void pciio_init(void);
 extern void pcibr_init(void);
 extern void xtalk_init(void);
@@ -33,23 +31,21 @@
 extern void usrpci_init(void);
 extern void ioc3_init(void);
 extern void initialize_io(void);
-extern void init_platform_nodepda(nodepda_t *, cnodeid_t );
+#if defined(CONFIG_IA64_SGI_SN1)
 extern void intr_clear_all(nasid_t);
+#endif
 extern void klhwg_add_all_modules(devfs_handle_t);
 extern void klhwg_add_all_nodes(devfs_handle_t);
 
 void sn_mp_setup(void);
 extern devfs_handle_t hwgraph_root;
 extern void io_module_init(void);
-extern cnodeid_t nasid_to_compact_node[];
 extern void pci_bus_cvlink_init(void);
 extern void temp_hack(void);
-extern void init_platform_pda(cpuid_t cpu);
 
 extern int pci_bus_to_hcl_cvlink(void);
-extern synergy_da_t	*Synergy_da_indr[];
 
-#define DEBUG_IO_INIT
+/* #define DEBUG_IO_INIT 1 */
 #ifdef DEBUG_IO_INIT
 #define DBG(x...) printk(x)
 #else
@@ -57,20 +53,73 @@
 #endif /* DEBUG_IO_INIT */
 
 /*
- * kern/ml/csu.s calls mlsetup
- *   mlsetup calls mlreset(master) - kern/os/startup.c
- *   j main
- *
- 
- * SN/slave.s start_slave_loop calls slave_entry
- * SN/slave.s slave_entry calls slave_loop
- * SN/slave.s slave_loop calls bootstrap
- * bootstrap in SN1/SN1asm.s calls cboot
- * cboot calls mlreset(slave) - ml/SN/mp.c
+ * per_hub_init
  *
- * sgi_io_infrastructure_init() gets called right before pci_init() 
- * in Linux mainline.  This routine actually mirrors the IO Infrastructure 
- * call sequence in IRIX, ofcourse, nicely modified for Linux.
+ * 	This code is executed once for each Hub chip.
+ */
+static void
+per_hub_init(cnodeid_t cnode)
+{
+	nasid_t		nasid;
+	nodepda_t	*npdap;
+	ii_icmr_u_t	ii_icmr;
+	ii_ibcr_u_t	ii_ibcr;
+
+	nasid = COMPACT_TO_NASID_NODEID(cnode);
+
+	ASSERT(nasid != INVALID_NASID);
+	ASSERT(NASID_TO_COMPACT_NODEID(nasid) == cnode);
+
+	npdap = NODEPDA(cnode);
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	/* initialize per-node synergy perf instrumentation */
+	npdap->synergy_perf_enabled = 0; /* off by default */
+	npdap->synergy_perf_lock = SPIN_LOCK_UNLOCKED;
+	npdap->synergy_perf_freq = SYNERGY_PERF_FREQ_DEFAULT;
+	npdap->synergy_inactive_intervals = 0;
+	npdap->synergy_active_intervals = 0;
+	npdap->synergy_perf_data = NULL;
+	npdap->synergy_perf_first = NULL;
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
+	/*
+	 * Set the total number of CRBs that can be used.
+	 */
+	ii_icmr.ii_icmr_regval= 0x0;
+	ii_icmr.ii_icmr_fld_s.i_c_cnt = 0xF;
+	REMOTE_HUB_S(nasid, IIO_ICMR, ii_icmr.ii_icmr_regval);
+
+	/*
+	 * Set the number of CRBs that both of the BTEs combined
+	 * can use minus 1.
+	 */
+	ii_ibcr.ii_ibcr_regval= 0x0;
+	ii_ibcr.ii_ibcr_fld_s.i_count = 0x8;
+	REMOTE_HUB_S(nasid, IIO_IBCR, ii_ibcr.ii_ibcr_regval);
+
+	/*
+	 * Set CRB timeout to be 10ms.
+	 */
+	REMOTE_HUB_S(nasid, IIO_ICTP, 0x1000 );
+	REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	/* Reserve all of the hardwired interrupt levels. */
+	intr_reserve_hardwired(cnode);
+#endif
+
+	/* Initialize error interrupts for this hub. */
+	hub_error_init(cnode);
+}
+
+/*
+ * This routine is responsible for the setup of all the IRIX hwgraph style
+ * stuff that's been pulled into linux.  It's called by sn_pci_find_bios which
+ * is called just before the generic Linux PCI layer does its probing (by 
+ * platform_pci_fixup aka sn_pci_fixup).
  *
  * It is very IMPORTANT that this call is only made by the Master CPU!
  *
@@ -80,7 +129,6 @@
 sgi_master_io_infr_init(void)
 {
 	int cnode;
-	extern int maxnodes;
 
 	/*
 	 * Do any early init stuff .. einit_tbl[] etc.
@@ -88,17 +136,49 @@
 	DBG("--> sgi_master_io_infr_init: calling init_hcl().\n");
 	init_hcl(); /* Sets up the hwgraph compatibility layer with devfs */
 
+#ifdef Colin
+
+printk("Testing out Xbridge Access .. if it hangs Xbridge is not init yet.\n");
+printk("	Reading Xbridge WID at address 0xc00000080f000000 0x%p\n", (* (volatile uint32_t *)(0xc00000080f000000)));
+
+printk("Testing out PCI Address Space Accesses\n");
+printk("	Testing PCI Config Read Byte: address 0xc00000080f020000 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020000)));
+
+printk("	Testing PCI Config Read Byte: address 0xc00000080f020001 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020001)));
+
+printk("	Testing PCI Config Read Byte: address 0xc00000080f020002 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020002)));
+
+printk("	Testing PCI Config Read Byte: address 0xc00000080f020003 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020003)));
+
+printk("        Testing PCI Config Read Byte: address 0xc00000080f020004 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020004)));
+
+printk("        Testing PCI Config Read Byte: address 0xc00000080f020005 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020005)));
+
+printk("        Testing PCI Config Read Byte: address 0xc00000080f020006 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020006)));
+
+printk("        Testing PCI Config Read Byte: address 0xc00000080f020007 value 0x%x\n",(* (volatile uint8_t *)(0xc00000080f020007)));
+
+printk("	Testing PCI Config Word: address 0xc00000080f020004 value 0x%x\n",(* (volatile uint32_t *)(0xc00000080f020004)));
+
+printk("	Testing PCI Config Word: address 0xc00000080f020008 value 0x%x\n",(* (volatile uint32_t *)(0xc00000080f020008)));
+
+#endif
+
 	/*
 	 * initialize the Linux PCI to xwidget vertexes ..
 	 */
 	DBG("--> sgi_master_io_infr_init: calling pci_bus_cvlink_init().\n");
 	pci_bus_cvlink_init();
 
+#ifdef BRINGUP
+#ifdef CONFIG_IA64_SGI_SN1
 	/*
 	 * Hack to provide statically initialzed klgraph entries.
 	 */
 	DBG("--> sgi_master_io_infr_init: calling klgraph_hack_init()\n");
 	klgraph_hack_init();
+#endif /* CONFIG_IA64_SGI_SN1 */
+#endif /* BRINGUP */
 
 	/*
 	 * This is the Master CPU.  Emulate mlsetup and main.c in Irix.
@@ -117,7 +197,7 @@
 	sn_mp_setup();
 
 	DBG("--> sgi_master_io_infr_init: calling per_hub_init(0).\n");
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		per_hub_init(cnode);
 	}
 
@@ -133,9 +213,6 @@
 	DBG("--> sgi_master_io_infr_init: calling hubspc_init()\n");
 	hubspc_init();
 
-	DBG("--> sgi_master_io_infr_init: calling pciba_init()\n");
-	pciba_init();
-
 	DBG("--> sgi_master_io_infr_init: calling pciio_init()\n");
 	pciio_init();
 
@@ -172,6 +249,11 @@
 	DBG("--> sgi_master_io_infr_init: Setting up SGI IO Links for Linux PCI\n");
 	pci_bus_to_hcl_cvlink();
 
+#ifdef CONFIG_PCIBA
+	DBG("--> sgi_master_io_infr_init: calling pciba_init()\n");
+	pciba_init();
+#endif
+
 	DBG("--> Leave sgi_master_io_infr_init: DONE setting up SGI Links for PCI\n");
 }
 
@@ -199,76 +281,15 @@
 sn_mp_setup(void)
 {
 	cnodeid_t	cnode;
-	extern int	maxnodes;
 	cpuid_t		cpu;
 
-	DBG("sn_mp_setup: Entered.\n");
-	/*
-	 * NODEPDA(x) Macro depends on nodepda
-	 * subnodepda is also statically set to calias space which we 
-	 * do not currently support yet .. just a hack for now.
-	 */
-#ifdef NUMA_BASE
-        maxnodes = numnodes;
-	DBG("sn_mp_setup(): maxnodes= %d  numnodes= %d\n", maxnodes,numnodes);
-        printk("sn_mp_setup(): Allocating backing store for *Nodepdaindr[%2d] \n",
-                maxnodes);
-
-        /*
-         * Initialize Nodpdaindr and per-node nodepdaindr array
-         */
-        *Nodepdaindr = (nodepda_t *) kmalloc(sizeof(nodepda_t *)*numnodes, GFP_KERNEL);
-        for (cnode=0; cnode<maxnodes; cnode++) {
-            Nodepdaindr[cnode] = (nodepda_t *) kmalloc(sizeof(struct nodepda_s),
-                                                                GFP_KERNEL);
-	    Synergy_da_indr[cnode * 2] = (synergy_da_t *) kmalloc(
-		sizeof(synergy_da_t), GFP_KERNEL);
-	    Synergy_da_indr[(cnode * 2) + 1] = (synergy_da_t *) kmalloc(
-		sizeof(synergy_da_t), GFP_KERNEL);
-            Nodepdaindr[cnode]->pernode_pdaindr = Nodepdaindr;
-            subnodepda = &Nodepdaindr[cnode]->snpda[cnode];
-        }
-        nodepda = Nodepdaindr[0];
-#else
-        Nodepdaindr = (nodepda_t *) kmalloc(sizeof(struct nodepda_s), GFP_KERNEL);
-        nodepda = Nodepdaindr[0];
-        subnodepda = &Nodepdaindr[0]->snpda[0];
-
-#endif /* NUMA_BASE */
-
-	/*
-	 * Before we let the other processors run, set up the platform specific
-	 * stuff in the nodepda.
-	 *
-	 * ???? maxnodes set in mlreset .. who sets it now ????
-	 * ???? cpu_node_probe() called in mlreset to set up the following:
-	 *      compact_to_nasid_node[] - cnode id gives nasid
-	 *      nasid_to_compact_node[] - nasid gives cnode id
-	 *
-	 *	do_cpumask() sets the following:
-	 *      cpuid_to_compact_node[] - cpuid gives cnode id
-	 *
-	 *      nasid comes from gdap->g_nasidtable[]
-	 *      ml/SN/promif.c
-	 */
-
-#ifdef CONFIG_IA64_SGI_SN1
 	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
 		/* Skip holes in CPU space */
 		if (cpu_enabled(cpu)) {
 			init_platform_pda(cpu);
 		}
 	}
-#endif
-	for (cnode = 0; cnode < maxnodes; cnode++) {
-		/*
-		 * Set up platform-dependent nodepda fields.
-		 * The following routine actually sets up the hubinfo struct
-		 * in nodepda.
-		 */
-		DBG("sn_mp_io_setup: calling init_platform_nodepda(%2d)\n",cnode);
-		init_platform_nodepda(Nodepdaindr[cnode], cnode);
-	}
+
 	/*
 	 * Initialize platform-dependent vertices in the hwgraph:
 	 *	module
@@ -290,24 +311,26 @@
 	klhwg_add_all_nodes(hwgraph_root);
 
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 
 		/*
 		 * This routine clears the Hub's Interrupt registers.
 		 */
-#ifdef CONFIG_IA64_SGI_SN1
 		/*
 		 * We need to move this intr_clear_all() routine 
 		 * from SN/intr.c to a more appropriate file.
 		 * Talk to Al Mayer.
 		 */
+#if defined(CONFIG_IA64_SGI_SN1)
                 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode));
+#endif
 		/* now init the hub */
 	//	per_hub_init(cnode);
-#endif
+
 	}
 
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
+#if defined(CONFIG_IA64_SGI_SN1)
 	synergy_perf_init();
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
+#endif
+
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sgi_io_sim.c linux/arch/ia64/sn/io/sgi_io_sim.c
--- linux.orig/arch/ia64/sn/io/sgi_io_sim.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/sgi_io_sim.c	2002-08-01 06:42:39.000000000 +0000
@@ -4,31 +4,28 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/module.h>
 #include <asm/sn/nic.h>
 #include <asm/sn/sn_private.h>
-#include <asm/sn/synergy.h>
 
 cpuid_t         master_procid = 0;
-int maxnodes;
 char arg_maxnodes[4];
 
-nodepda_t       *Nodepdaindr[MAX_COMPACT_NODES];
-nodepda_t        *nodepda;
-subnode_pda_t    *subnodepda;
-
-synergy_da_t	*Synergy_da_indr[MAX_COMPACT_NODES * 2];
-
 extern void init_all_devices(void);
 
+#if defined(CONFIG_IA64_SGI_SN1)
+synergy_da_t	*Synergy_da_indr[MAX_COMPACT_NODES * 2];
+#endif
 
 /*
  * Return non-zero if the given variable was specified
@@ -73,27 +70,23 @@
  * Routines provided by ml/SN/promif.c.
  */
 static __psunsigned_t master_bridge_base = (__psunsigned_t)NULL;
-nasid_t console_nasid;
+nasid_t console_nasid = (nasid_t)-1;
 static char console_wid;
 static char console_pcislot;
 
 void
 set_master_bridge_base(void)
 {
-
-        console_nasid = KL_CONFIG_CH_CONS_INFO(master_nasid)->nasid;
         console_wid = WIDGETID_GET(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base);
         console_pcislot = KL_CONFIG_CH_CONS_INFO(master_nasid)->npci;
-        master_bridge_base = (__psunsigned_t)NODE_SWIN_BASE(console_nasid,
-                                                            console_wid);
-	FIXME("WARNING: set_master_bridge_base: NON NASID 0 DOES NOT WORK\n");
+        master_bridge_base = (__psunsigned_t)NODE_SWIN_BASE(console_nasid, console_wid);
+	// FIXME("WARNING: set_master_bridge_base: NON NASID 0 DOES NOT WORK\n");
 }
 
 int
 check_nasid_equiv(nasid_t nasida, nasid_t nasidb)
 {
-        if ((nasida == nasidb) ||
-            (nasida == NODEPDA(NASID_TO_COMPACT_NODEID(nasidb))->xbow_peer))
+        if ((nasida == nasidb) || (nasida == NODEPDA(NASID_TO_COMPACT_NODEID(nasidb))->xbow_peer))
                 return 1;
         else
                 return 0;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/hub_intr.c linux/arch/ia64/sn/io/sn1/hub_intr.c
--- linux.orig/arch/ia64/sn/io/sn1/hub_intr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/hub_intr.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,307 @@
+/* $Id: hub_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern xtalk_provider_t hub_provider;
+
+/* ARGSUSED */
+void
+hub_intr_init(devfs_handle_t hubv)
+{
+}
+
+/*
+ * hub_device_desc_update
+ *	Update the passed in device descriptor with the actual the
+ * 	target cpu number and interrupt priority level.
+ *	NOTE : These might be the same as the ones passed in thru
+ *	the descriptor.
+ */
+static void
+hub_device_desc_update(device_desc_t 	dev_desc, 
+		       ilvl_t 		intr_swlevel,
+		       cpuid_t		cpu)
+{
+}
+
+int allocate_my_bit = INTRCONNECT_ANYBIT;
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+static hub_intr_t
+do_hub_intr_alloc(devfs_handle_t dev,		/* which crosstalk device */
+		  device_desc_t dev_desc,	/* device descriptor */
+		  devfs_handle_t owner_dev,	/* owner of this interrupt, if known */
+		  int uncond_nothread)		/* unconditionally non-threaded */
+{
+	cpuid_t cpu = (cpuid_t)0;			/* cpu to receive interrupt */
+        int cpupicked = 0;
+	int bit;			/* interrupt vector */
+	/*REFERENCED*/
+	int intr_resflags = 0;
+	hub_intr_t intr_hdl;
+	cnodeid_t nodeid;		/* node to receive interrupt */
+	/*REFERENCED*/
+	nasid_t nasid;			/* nasid to receive interrupt */
+	struct xtalk_intr_s *xtalk_info;
+	iopaddr_t xtalk_addr;		/* xtalk addr on hub to set intr */
+	xwidget_info_t xwidget_info;	/* standard crosstalk widget info handle */
+	char *intr_name = NULL;
+	ilvl_t intr_swlevel = (ilvl_t)0;
+	extern int default_intr_pri;
+	extern void synergy_intr_alloc(int, int);
+
+
+	if (dev_desc) {
+		if (dev_desc->flags & D_INTR_ISERR) {
+			intr_resflags = II_ERRORINT;
+		} else if (!uncond_nothread && !(dev_desc->flags & D_INTR_NOTHREAD)) {
+			intr_resflags = II_THREADED;
+		} else {
+			/* Neither an error nor a thread. */
+			intr_resflags = 0;
+		}
+	} else {
+		intr_swlevel = default_intr_pri;
+		if (!uncond_nothread)
+			intr_resflags = II_THREADED;
+	}
+
+	/* XXX - Need to determine if the interrupt should be threaded. */
+
+	/* If the cpu has not been picked already then choose a candidate 
+	 * interrupt target and reserve the interrupt bit 
+	 */
+	if (!cpupicked) {
+		cpu = intr_heuristic(dev,dev_desc,allocate_my_bit,
+				     intr_resflags,owner_dev,
+				     intr_name,&bit);
+	}
+
+	/* At this point we SHOULD have a valid cpu */
+	if (cpu == CPU_NONE) {
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+		printk(KERN_WARNING  "%v hub_intr_alloc could not allocate interrupt\n",
+			owner_dev);
+#else
+		printk(KERN_WARNING  "%p hub_intr_alloc could not allocate interrupt\n",
+			(void *)owner_dev);
+#endif
+		return(0);
+
+	}
+
+	/* If the cpu has been picked already (due to the bridge data 
+	 * corruption bug) then try to reserve an interrupt bit .
+	 */
+	if (cpupicked) {
+		bit = intr_reserve_level(cpu, allocate_my_bit, 
+					 intr_resflags, 
+					 owner_dev, intr_name);
+		if (bit < 0) {
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+			printk(KERN_WARNING  "Could not reserve an interrupt bit for cpu "
+				" %d and dev %v\n",
+				cpu,owner_dev);
+#else
+			printk(KERN_WARNING  "Could not reserve an interrupt bit for cpu "
+				" %d and dev %p\n",
+				(int)cpu, (void *)owner_dev);
+#endif
+				
+			return(0);
+		}
+	}
+
+	nodeid = cpuid_to_cnodeid(cpu);
+	nasid = cpuid_to_nasid(cpu);
+	xtalk_addr = HUBREG_AS_XTALKADDR(nasid, PIREG(PI_INT_PEND_MOD, cpuid_to_subnode(cpu)));
+
+	/*
+	 * Allocate an interrupt handle, and fill it in.  There are two
+	 * pieces to an interrupt handle: the piece needed by generic
+	 * xtalk code which is used by crosstalk device drivers, and
+	 * the piece needed by low-level IP27 hardware code.
+	 */
+	intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, nodeid);
+	ASSERT_ALWAYS(intr_hdl);
+
+	/* 
+	 * Fill in xtalk information for generic xtalk interfaces that
+	 * operate on xtalk_intr_hdl's.
+	 */
+	xtalk_info = &intr_hdl->i_xtalk_info;
+	xtalk_info->xi_dev = dev;
+	xtalk_info->xi_vector = bit;
+	xtalk_info->xi_addr = xtalk_addr;
+
+	/*
+	 * Regardless of which CPU we ultimately interrupt, a given crosstalk
+	 * widget always handles interrupts (and PIO and DMA) through its 
+	 * designated "master" crosstalk provider.
+	 */
+	xwidget_info = xwidget_info_get(dev);
+	if (xwidget_info)
+		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
+
+	/* Fill in low level hub information for hub_* interrupt interface */
+	intr_hdl->i_swlevel = intr_swlevel;
+	intr_hdl->i_cpuid = cpu;
+	intr_hdl->i_bit = bit;
+	intr_hdl->i_flags = HUB_INTR_IS_ALLOCED;
+
+	/* Store the actual interrupt priority level & interrupt target
+	 * cpu back in the device descriptor.
+	 */
+	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
+	synergy_intr_alloc((int)bit, (int)cpu);
+	return(intr_hdl);
+}
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+hub_intr_t
+hub_intr_alloc(	devfs_handle_t dev,		/* which crosstalk device */
+		device_desc_t dev_desc,		/* device descriptor */
+		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
+}
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Uncondtionally request non-threaded, regardless of what the device
+ * descriptor might say.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,		/* which crosstalk device */
+		device_desc_t dev_desc,		/* device descriptor */
+		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
+}
+
+/*
+ * Free resources consumed by intr_alloc.
+ */
+void
+hub_intr_free(hub_intr_t intr_hdl)
+{
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_t xtalk_info;
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
+		/* Setting the following fields in the xtalk interrupt info
+	 	 * clears the interrupt target register in the xtalk user
+	 	 */
+		xtalk_info = &intr_hdl->i_xtalk_info;
+		xtalk_info->xi_dev = NODEV;
+		xtalk_info->xi_vector = 0;
+		xtalk_info->xi_addr = 0;
+		hub_intr_disconnect(intr_hdl);
+	}
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED)
+		kfree(intr_hdl);
+
+	intr_unreserve_level(cpu, bit);
+}
+
+
+/*
+ * Associate resources allocated with a previous hub_intr_alloc call with the
+ * described handler, arg, name, etc.
+ */
+/*ARGSUSED*/
+int
+hub_intr_connect(	hub_intr_t intr_hdl,		/* xtalk intr resource handle */
+			xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
+			void *setfunc_arg)		/* arg to setfunc */
+{
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	extern int synergy_intr_connect(int, int);
+
+	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
+
+	rv = intr_connect_level(cpu, bit, intr_hdl->i_swlevel, NULL);
+	if (rv < 0)
+		return(rv);
+
+	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
+	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
+
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
+	return(synergy_intr_connect((int)bit, (int)cpu));
+}
+
+
+/*
+ * Disassociate handler with the specified interrupt.
+ */
+void
+hub_intr_disconnect(hub_intr_t intr_hdl)
+{
+	/*REFERENCED*/
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_setfunc_t setfunc;
+
+	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
+
+	/* TBD: send disconnected interrupts somewhere harmless */
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	rv = intr_disconnect_level(cpu, bit);
+	ASSERT(rv == 0);
+	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
+}
+
+
+/*
+ * Return a hwgraph vertex that represents the CPU currently
+ * targeted by an interrupt.
+ */
+devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl)
+{
+	cpuid_t cpuid = intr_hdl->i_cpuid;
+	ASSERT(cpuid != CPU_NONE);
+
+	return(cpuid_to_vertex(cpuid));
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/hubcounters.c linux/arch/ia64/sn/io/sn1/hubcounters.c
--- linux.orig/arch/ia64/sn/io/sn1/hubcounters.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/hubcounters.c	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,283 @@
+/* $Id: hubcounters.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <asm/types.h>
+#include <asm/sn/io.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/router.h>
+#include <asm/sn/snconfig.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/clksupport.h>
+#include <asm/sn/sndrv.h>
+
+extern void hubni_error_handler(char *, int); /* huberror.c */
+
+static int hubstats_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+struct file_operations hub_mon_fops = {
+        ioctl:          hubstats_ioctl,
+};
+
+#define HUB_CAPTURE_TICKS	(2 * HZ)
+
+#define HUB_ERR_THRESH		500
+#define USEC_PER_SEC		1000000
+#define NSEC_PER_SEC		USEC_PER_SEC*1000
+
+volatile int hub_print_usecs = 600 * USEC_PER_SEC;
+
+/* Return success if the hub's crosstalk link is working */
+int
+hub_xtalk_link_up(nasid_t nasid)
+{
+	hubreg_t	llp_csr_reg;
+
+	/* Read the IO LLP control status register */
+	llp_csr_reg = REMOTE_HUB_L(nasid, IIO_LLP_CSR);
+
+	/* Check if the xtalk link is working */
+	if (llp_csr_reg & IIO_LLP_CSR_IS_UP) 
+		return(1);
+
+	return(0);
+
+	
+}
+
+static char *error_flag_to_type(unsigned char error_flag)
+{
+    switch(error_flag) {
+    case 0x1: return ("NI retries");
+    case 0x2: return ("NI SN errors");
+    case 0x4: return ("NI CB errors");
+    case 0x8: return ("II CB errors");
+    case 0x10: return ("II SN errors");
+    default: return ("Errors");
+    }
+}
+
+int
+print_hub_error(hubstat_t *hsp, hubreg_t reg,
+		int64_t delta, unsigned char error_flag)
+{
+	int64_t rate;
+
+	reg *= hsp->hs_per_minute;	/* Convert to minutes */
+	rate = reg / delta;
+
+	if (rate > HUB_ERR_THRESH) {
+		
+		if(hsp->hs_maint & error_flag) 
+		{
+		printk( "Excessive %s (%ld/min) on %s",
+			error_flag_to_type(error_flag), rate, hsp->hs_name); 
+		}
+		else 
+		{
+		   hsp->hs_maint |= error_flag;
+		printk( "Excessive %s (%ld/min) on %s",
+			error_flag_to_type(error_flag), rate, hsp->hs_name); 
+		}
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+
+int
+check_hub_error_rates(hubstat_t *hsp)
+{
+	int64_t delta = hsp->hs_timestamp - hsp->hs_timebase;
+	int printed = 0;
+
+	printed += print_hub_error(hsp, hsp->hs_ni_retry_errors,
+				   delta, 0x1);
+
+#if 0
+	printed += print_hub_error(hsp, hsp->hs_ni_sn_errors,
+				   delta, 0x2);
+#endif
+
+	printed += print_hub_error(hsp, hsp->hs_ni_cb_errors,
+				   delta, 0x4);
+
+
+	/* If the hub's xtalk link is not working there is 
+	 * no need to print the "Excessive..." warning 
+	 * messages
+	 */
+	if (!hub_xtalk_link_up(hsp->hs_nasid))
+		return(printed);
+
+
+	printed += print_hub_error(hsp, hsp->hs_ii_cb_errors,
+				   delta, 0x8);
+
+	printed += print_hub_error(hsp, hsp->hs_ii_sn_errors,
+				   delta, 0x10);
+
+	return printed;
+}
+
+
+void
+capture_hub_stats(cnodeid_t cnodeid, struct nodepda_s *npda)
+{
+	nasid_t nasid;
+	hubstat_t *hsp = &(npda->hubstats);
+	hubreg_t port_error;
+	ii_illr_u_t illr;
+	int count;
+	int overflow = 0;
+
+	/*
+	 * If our link wasn't up at boot time, don't worry about error rates.
+	 */
+	if (!(hsp->hs_ni_port_status & NPS_LINKUP_MASK)) {
+		printk("capture_hub_stats: cnode=%d hs_ni_port_status=0x%016lx : link is not up\n",
+		cnodeid, hsp->hs_ni_port_status);
+		return;
+	}
+
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+
+	hsp->hs_timestamp = GET_RTC_COUNTER();
+
+	port_error = REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+	count = ((port_error & NPE_RETRYCOUNT_MASK) >> NPE_RETRYCOUNT_SHFT);
+	hsp->hs_ni_retry_errors += count;
+	if (count == NPE_COUNT_MAX)
+		overflow = 1;
+	count = ((port_error & NPE_SNERRCOUNT_MASK) >> NPE_SNERRCOUNT_SHFT);
+	hsp->hs_ni_sn_errors += count;
+	if (count == NPE_COUNT_MAX)
+		overflow = 1;
+	count = ((port_error & NPE_CBERRCOUNT_MASK) >> NPE_CBERRCOUNT_SHFT);
+	hsp->hs_ni_cb_errors += count;
+	if (overflow || count == NPE_COUNT_MAX)
+		hsp->hs_ni_overflows++;
+
+	if (port_error & NPE_FATAL_ERRORS) {
+#ifdef ajm
+		hubni_error_handler("capture_hub_stats", 1);
+#else
+		printk("Error: hubni_error_handler in capture_hub_stats");
+#endif
+	}
+
+	illr.ii_illr_regval = REMOTE_HUB_L(nasid, IIO_LLP_LOG);
+	REMOTE_HUB_S(nasid, IIO_LLP_LOG, 0);
+
+	hsp->hs_ii_sn_errors += illr.ii_illr_fld_s.i_sn_cnt;
+	hsp->hs_ii_cb_errors += illr.ii_illr_fld_s.i_cb_cnt;
+	if ((illr.ii_illr_fld_s.i_sn_cnt == IIO_LLP_SN_MAX) ||
+	    (illr.ii_illr_fld_s.i_cb_cnt == IIO_LLP_CB_MAX))
+		hsp->hs_ii_overflows++;
+
+	if (hsp->hs_print) {
+		if (check_hub_error_rates(hsp)) {
+			hsp->hs_last_print = GET_RTC_COUNTER();
+			hsp->hs_print = 0;
+		}
+	} else {
+		if ((GET_RTC_COUNTER() -
+		    hsp->hs_last_print) > hub_print_usecs)
+			hsp->hs_print = 1;
+	}
+		
+	npda->hubticks = HUB_CAPTURE_TICKS;
+}
+
+
+void
+init_hub_stats(cnodeid_t cnodeid, struct nodepda_s *npda)
+{
+	hubstat_t *hsp = &(npda->hubstats);
+	nasid_t nasid = cnodeid_to_nasid(cnodeid);
+	bzero(&(npda->hubstats), sizeof(hubstat_t));
+
+	hsp->hs_version = HUBSTAT_VERSION;
+	hsp->hs_cnode = cnodeid;
+	hsp->hs_nasid = nasid;
+	hsp->hs_timebase = GET_RTC_COUNTER();
+	hsp->hs_ni_port_status = REMOTE_HUB_L(nasid, NI_PORT_STATUS);
+
+	/* Clear the II error counts. */
+	REMOTE_HUB_S(nasid, IIO_LLP_LOG, 0);
+
+	/* Clear the NI counts. */
+	REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+
+	hsp->hs_per_minute = (long long)RTC_CYCLES_PER_SEC * 60LL;
+
+	npda->hubticks = HUB_CAPTURE_TICKS;
+
+	/* XX should use kmem_alloc_node */
+	hsp->hs_name = (char *)kmalloc(MAX_HUB_PATH, GFP_KERNEL);
+	ASSERT_ALWAYS(hsp->hs_name);
+
+	sprintf(hsp->hs_name, "/dev/hw/" EDGE_LBL_MODULE "/%03d/"
+	        EDGE_LBL_NODE "/" EDGE_LBL_HUB,
+		npda->module_id);
+
+	hsp->hs_last_print = 0;
+	hsp->hs_print = 1;
+
+	hub_print_usecs = hub_print_usecs;
+
+#if 0
+	printk("init_hub_stats: cnode=%d nasid=%d hs_version=%d hs_ni_port_status=0x%016lx\n",
+		cnodeid, nasid, hsp->hs_version, hsp->hs_ni_port_status);
+#endif
+}
+
+static int
+hubstats_ioctl(struct inode *inode, struct file *file,
+        unsigned int cmd, unsigned long arg)
+{
+        cnodeid_t       cnode;
+        nodepda_t       *npdap;
+        uint64_t        longarg;
+        devfs_handle_t  d;
+
+        if ((d = devfs_get_handle_from_inode(inode)) == NULL)
+                return -ENODEV;
+        cnode = (cnodeid_t)hwgraph_fastinfo_get(d);
+        npdap = NODEPDA(cnode);
+
+	if (npdap->hubstats.hs_version != HUBSTAT_VERSION) {
+		init_hub_stats(cnode, npdap);
+	}
+
+        switch (cmd) {
+	case SNDRV_GET_INFOSIZE:
+		longarg = sizeof(hubstat_t);
+		if (copy_to_user((void *)arg, &longarg, sizeof(longarg))) {
+		    return -EFAULT;
+		}
+		break;
+
+	case SNDRV_GET_HUBINFO:
+		/* refresh npda->hubstats */
+		capture_hub_stats(cnode, npdap);
+		if (copy_to_user((void *)arg, &npdap->hubstats, sizeof(hubstat_t))) {
+		    return -EFAULT;
+		}
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/huberror.c linux/arch/ia64/sn/io/sn1/huberror.c
--- linux.orig/arch/ia64/sn/io/sn1/huberror.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/huberror.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,228 @@
+/* $Id: huberror.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+
+extern void hubni_eint_init(cnodeid_t cnode);
+extern void hubii_eint_init(cnodeid_t cnode);
+extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
+extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
+
+extern int maxcpus;
+
+#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
+
+
+void
+hub_error_clear(nasid_t nasid)
+{
+	int i;
+	hubreg_t idsr;
+	int sn;
+
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_PEND, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_A_CLR, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_B_CLR, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_0, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_1, 0);
+	}
+
+	REMOTE_HUB_L(nasid, MD_DIR_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_MEM_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_MISC1_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_PROTOCOL_ERR_CLR);
+
+    /*
+     * Make sure spurious write response errors are cleared
+     * (values are from hub_set_prb())
+     */
+    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
+        iprb_t prb;
+
+	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
+
+        /* Clear out some fields */
+        prb.iprb_ovflow = 1;
+        prb.iprb_bnakctr = 0;
+        prb.iprb_anakctr = 0;
+
+	/*
+	 * PIO reads in fire-and-forget mode on bedrock 1.0 don't
+	 * frob the credit count properly, making the responses appear
+	 * spurious.  So don't use fire-and-forget mode.  Bug 761802.
+	 */
+        prb.iprb_ff = 0;        /* disable fire-and-forget mode by default */
+
+        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
+
+        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
+    }
+
+    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
+    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
+    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
+
+    REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+    /* No need to clear NI_PORT_HEADER regs; they are continually overwritten*/
+
+    REMOTE_HUB_S(nasid, LB_ERROR_MASK_CLR, -1);
+    REMOTE_HUB_S(nasid, LB_ERROR_HDR1, 0);
+
+    /* Clear XB error regs, in order */
+    for (i = 0;
+         i <= XB_FIRST_ERROR_CLEAR - XB_POQ0_ERROR_CLEAR;
+         i += sizeof(hubreg_t)) {
+        REMOTE_HUB_S(nasid, XB_POQ0_ERROR_CLEAR + i, 0);
+    }
+}
+
+
+/*
+ * Function	: hub_error_init
+ * Purpose	: initialize the error handling requirements for a given hub.
+ * Parameters	: cnode, the compact nodeid.
+ * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
+ *			remote cpu, when this hub is headless.(cpuless)
+ * Returns	: None
+ */
+
+void
+hub_error_init(cnodeid_t cnode)
+{
+	nasid_t nasid;
+
+    nasid = cnodeid_to_nasid(cnode);
+    hub_error_clear(nasid);
+
+    /*
+     * Now setup the hub ii and ni error interrupt handler.
+     */
+
+    hubii_eint_init(cnode);
+    hubni_eint_init(cnode);
+
+    return;
+}
+
+/*
+ * Function	: hubii_eint_init
+ * Parameters	: cnode
+ * Purpose	: to initialize the hub iio error interrupt.
+ * Assumptions	: Called once per hub, by the cpu which will ultimately
+ *			handle this interrupt.
+ * Returns	: None.
+ */
+
+
+void
+hubii_eint_init(cnodeid_t cnode)
+{
+    int			bit, rv;
+    ii_iidsr_u_t    	hubio_eint;
+    hubinfo_t		hinfo; 
+    cpuid_t		intr_cpu;
+    devfs_handle_t 	hub_v;
+    ii_ilcsr_u_t	ilcsr;
+    int bit_pos_to_irq(int bit);
+    int synergy_intr_connect(int bit, int cpuid);
+
+
+    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
+    ASSERT_ALWAYS(hub_v);
+    hubinfo_get(hub_v, &hinfo);
+
+    ASSERT(hinfo);
+    ASSERT(hinfo->h_cnodeid == cnode);
+
+    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
+
+    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
+	/* 
+	 * HUB II link is not up. 
+	 * Just disable LLP, and don't connect any interrupts.
+	 */
+	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
+	return;
+    }
+    /* Select a possible interrupt target where there is a free interrupt
+     * bit and also reserve the interrupt bit for this IO error interrupt
+     */
+    intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
+			      "HUB IO error interrupt",&bit);
+    if (intr_cpu == CPU_NONE) {
+	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
+	return;
+    }
+	
+    rv = intr_connect_level(intr_cpu, bit, 0, NULL);
+    synergy_intr_connect(bit, intr_cpu);
+    request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, "SN hub error", (void *)hub_v);
+    ASSERT_ALWAYS(rv >= 0);
+    hubio_eint.ii_iidsr_regval = 0;
+    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
+    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
+    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
+    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
+
+}
+
+void
+hubni_eint_init(cnodeid_t cnode)
+{
+    int intr_bit;
+    cpuid_t targ;
+
+
+    if ((targ = cnodeid_to_cpuid(cnode)) == CPU_NONE)
+	return;
+
+	/* The prom chooses which cpu gets these interrupts, but we
+	*  don't know which one it chose.  We will register all of the 
+	*  cpus to be sure.  This only costs us an irqaction per cpu.
+	*/
+    for (; targ < CPUS_PER_NODE; targ++) {
+	if (!cpu_enabled(targ) ) continue;
+	/* connect the INTEND1 bits. */
+	for (intr_bit = XB_ERROR; intr_bit <= MSC_PANIC_INTR; intr_bit++) {
+		intr_connect_level(targ, intr_bit, II_ERRORINT, NULL);
+	}
+	request_irq(SGI_HUB_ERROR_IRQ + (targ << 8), snia_error_intr_handler, 0, "SN hub error", NULL);
+	/* synergy masks are initialized in the prom to enable all interrupts. */
+	/* We'll just leave them that way, here, for these interrupts. */
+    }
+}
+
+
+/*ARGSUSED*/
+void
+hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
+{
+
+	panic("Hubii interrupt\n");
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/ip37.c linux/arch/ia64/sn/io/sn1/ip37.c
--- linux.orig/arch/ia64/sn/io/sn1/ip37.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/ip37.c	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,47 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * ip37.c
+ *	Support for IP35/IP37 machines
+ */
+
+#include <linux/types.h>
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/pci/bridge.h>     /* for bridge_t */
+
+
+xwidgetnum_t
+hub_widget_id(nasid_t nasid)
+{
+	hubii_wcr_t	ii_wcr;	/* the control status register */
+		
+	ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
+
+	return ii_wcr.wcr_fields_s.wcr_widget_id;
+}
+
+int
+is_fine_dirmode(void)
+{
+	return (((LOCAL_HUB_L(LB_REV_ID) & LRI_SYSTEM_SIZE_MASK)
+		>> LRI_SYSTEM_SIZE_SHFT) == SYSTEM_SIZE_SMALL);
+
+}
+
+
+void
+ni_reset_port(void)
+{
+	LOCAL_HUB_S(NI_RESET_ENABLE, NRE_RESETOK);
+	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/mem_refcnt.c linux/arch/ia64/sn/io/sn1/mem_refcnt.c
--- linux.orig/arch/ia64/sn/io/sn1/mem_refcnt.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/mem_refcnt.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,221 @@
+/* $Id: mem_refcnt.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/sn1/mem_refcnt.h>
+#include <asm/sn/sn1/hwcntrs.h>
+#include <asm/sn/sn1/hubspc.h>
+// From numa_hw.h
+
+#define MIGR_COUNTER_MAX_GET(nodeid) \
+        (NODEPDA_MCD((nodeid))->migr_system_kparms.migr_threshold_reference)
+/*
+ * Get the Absolute Theshold
+ */
+#define MIGR_THRESHOLD_ABS_GET(nodeid) ( \
+        MD_MIG_VALUE_THRESH_GET(COMPACT_TO_NASID_NODEID(nodeid)))
+/*
+ * Get the current Differential Threshold
+ */
+#define MIGR_THRESHOLD_DIFF_GET(nodeid) \
+        (NODEPDA_MCD(nodeid)->migr_as_kparms.migr_base_threshold)
+
+#define NUM_OF_HW_PAGES_PER_SW_PAGE()   (NBPP / MD_PAGE_SIZE)
+
+// #include "migr_control.h"
+
+int
+mem_refcnt_attach(devfs_handle_t hub)
+{
+#ifndef CONFIG_IA64_SGI_SN
+        devfs_handle_t refcnt_dev;
+        
+        hwgraph_char_device_add(hub,
+                                "refcnt",
+                                "hubspc_", 
+				&refcnt_dev);
+        device_info_set(refcnt_dev, (void*)(ulong)HUBSPC_REFCOUNTERS);
+#endif
+
+        return (0);
+}
+
+
+/*ARGSUSED*/
+int
+mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
+{
+        cnodeid_t node;
+
+        node = master_node_get(*devp);
+
+        ASSERT( (node >= 0) && (node < numnodes) );
+
+        if (NODEPDA(node)->migr_refcnt_counterbuffer == NULL) {
+                return (ENODEV);
+        }
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != (size_t)0 );
+
+        return (0);
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+        return 0;
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+        cnodeid_t node;
+        int errcode;
+        char* buffer;
+        size_t blen;
+        
+        node = master_node_get(dev);
+
+        ASSERT( (node >= 0) && (node < numnodes) );
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
+
+        /*
+         * XXXX deal with prot's somewhere around here....
+         */
+
+        buffer = NODEPDA(node)->migr_refcnt_counterbuffer;
+        blen = NODEPDA(node)->migr_refcnt_cbsize;
+
+        /*
+         * Force offset to be a multiple of sizeof(refcnt_t)
+         * We round up.
+         */
+
+        off = (((off - 1)/sizeof(refcnt_t)) + 1) * sizeof(refcnt_t);
+
+        if ( ((buffer + blen) - (buffer + off + len)) < 0 ) {
+                return (EPERM);
+        }
+
+        errcode = v_mapphys(vt,
+                            buffer + off,
+                            len);
+
+        return errcode;
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+        return 0;
+}
+
+/* ARGSUSED */
+int
+mem_refcnt_ioctl(devfs_handle_t dev,
+                 int cmd,
+                 void *arg,
+                 int mode,
+                 cred_t *cred_p,
+                 int *rvalp)
+{
+        cnodeid_t node;
+        int errcode;
+	extern int numnodes;
+        
+        node = master_node_get(dev);
+
+        ASSERT( (node >= 0) && (node < numnodes) );
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
+
+        errcode = 0;
+        
+        switch (cmd) {
+        case RCB_INFO_GET:
+        {
+                rcb_info_t rcb;
+                
+                rcb.rcb_len = NODEPDA(node)->migr_refcnt_cbsize;
+                
+                rcb.rcb_sw_sets = NODEPDA(node)->migr_refcnt_numsets;
+                rcb.rcb_sw_counters_per_set = numnodes;
+                rcb.rcb_sw_counter_size = sizeof(refcnt_t);
+
+                rcb.rcb_base_pages = NODEPDA(node)->migr_refcnt_numsets /
+                                     NUM_OF_HW_PAGES_PER_SW_PAGE();  
+                rcb.rcb_base_page_size = NBPP;
+                rcb.rcb_base_paddr = ctob(slot_getbasepfn(node, 0));
+                
+                rcb.rcb_cnodeid = node;
+                rcb.rcb_granularity = MD_PAGE_SIZE;
+#ifdef LATER
+                rcb.rcb_hw_counter_max = MIGR_COUNTER_MAX_GET(node);
+                rcb.rcb_diff_threshold = MIGR_THRESHOLD_DIFF_GET(node);
+#endif
+                rcb.rcb_abs_threshold = MIGR_THRESHOLD_ABS_GET(node);
+                rcb.rcb_num_slots = MAX_MEM_SLOTS;
+
+                if (COPYOUT(&rcb, arg, sizeof(rcb_info_t))) {
+                        errcode = EFAULT;
+                }
+
+                break;
+        }
+        case RCB_SLOT_GET:
+        {
+                rcb_slot_t slot[MAX_MEM_SLOTS];
+                int s;
+                int nslots;
+
+                nslots = MAX_MEM_SLOTS;
+                ASSERT(nslots <= MAX_MEM_SLOTS);
+                for (s = 0; s < nslots; s++) {
+                        slot[s].base = (uint64_t)ctob(slot_getbasepfn(node, s));
+#ifdef LATER
+                        slot[s].size  = (uint64_t)ctob(slot_getsize(node, s));
+#else
+                        slot[s].size  = (uint64_t)1;
+#endif
+                }
+                if (COPYOUT(&slot[0], arg, nslots * sizeof(rcb_slot_t))) {
+                        errcode = EFAULT;
+                }
+                
+                *rvalp = nslots;
+                break;
+        }
+                
+        default:
+                errcode = EINVAL;
+                break;
+
+        }
+        
+        return errcode;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/ml_SN_intr.c linux/arch/ia64/sn/io/sn1/ml_SN_intr.c
--- linux.orig/arch/ia64/sn/io/sn1/ml_SN_intr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/ml_SN_intr.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,1154 @@
+/* $Id: ml_SN_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * intr.c-
+ *	This file contains all of the routines necessary to set up and
+ *	handle interrupts on an IP27 board.
+ */
+
+#ident  "$Revision: 1.1 $"
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+
+
+#if DEBUG_INTR_TSTAMP_DEBUG
+#include <sys/debug.h>
+#include <sys/idbg.h>
+#include <sys/inst.h>
+void do_splx_log(int, int);
+void spldebug_log_event(int);
+#endif
+
+#ifdef CONFIG_SMP
+extern unsigned long cpu_online_map;
+#endif
+#define cpu_allows_intr(cpu)	(1)
+// If I understand what's going on with this, 32 should work.
+// physmem_maxradius seems to be the maximum number of router
+// hops to get from one end of the system to the other.  With
+// a maximally configured machine, with the dumbest possible
+// topology, we would make 32 router hops.  For what we're using
+// it for, the dumbest possible should suffice.
+#define physmem_maxradius()	32
+
+#define SUBNODE_ANY (-1)
+
+extern int	nmied;
+extern int	hub_intr_wakeup_cnt;
+extern synergy_da_t	*Synergy_da_indr[];
+extern cpuid_t         master_procid;
+
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+
+extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
+
+
+#define INTR_LOCK(vecblk) \
+     (s = mutex_spinlock(&(vecblk)->vector_lock))
+#define INTR_UNLOCK(vecblk) \
+      mutex_spinunlock(&(vecblk)->vector_lock, s)
+
+/*
+ * REACT/Pro
+ */
+
+
+
+/* 
+ * Find first bit set 
+ * Used outside this file also 
+ */
+int ms1bit(unsigned long x)
+{
+    int			b;
+
+    if (x >> 32)	b  = 32, x >>= 32;
+    else		b  =  0;
+    if (x >> 16)	b += 16, x >>= 16;
+    if (x >>  8)	b +=  8, x >>=  8;
+    if (x >>  4)	b +=  4, x >>=  4;
+    if (x >>  2)	b +=  2, x >>=  2;
+
+    return b + (int) (x >> 1);
+}
+
+/* ARGSUSED */
+void
+intr_stray(void *lvl)
+{
+    printk(KERN_WARNING  "Stray Interrupt - level %ld to cpu %d", (long)lvl, smp_processor_id());
+}
+
+#if defined(DEBUG)
+
+/* Infrastructure  to gather the device - target cpu mapping info */
+#define MAX_DEVICES	1000	/* Reasonable large number . Need not be 
+				 * the exact maximum # devices possible.
+				 */
+#define MAX_NAME	100	
+typedef struct {
+	dev_t		dev;	/* device */
+	cpuid_t		cpuid;	/* target cpu */
+	cnodeid_t	cnodeid;/* node on which the target cpu is present */
+	int		bit;	/* intr bit reserved */
+	char		intr_name[MAX_NAME]; /* name of the interrupt */
+} intr_dev_targ_map_t;
+
+intr_dev_targ_map_t 	intr_dev_targ_map[MAX_DEVICES];
+uint64_t		intr_dev_targ_map_size;
+spinlock_t		intr_dev_targ_map_lock;
+
+/* Print out the device - target cpu mapping.
+ * This routine is used only in the idbg command
+ * "intrmap" 
+ */
+void
+intr_dev_targ_map_print(cnodeid_t cnodeid)
+{
+	int  i,j,size = 0;
+	int  print_flag = 0,verbose = 0;	
+	char node_name[10];
+	
+	if (cnodeid != CNODEID_NONE) {
+		nodepda_t 	*npda;
+
+		npda = NODEPDA(cnodeid);
+		for (j=0; j<NUM_SUBNODES; j++) {
+			qprintf("\n SUBNODE %d\n INT_PEND0: ", j);
+			for(i = 0 ; i < N_INTPEND_BITS ; i++)
+				qprintf("%d",SNPDA(npda,j)->intr_dispatch0.info[i].ii_flags);
+			qprintf("\n INT_PEND1: ");
+			for(i = 0 ; i < N_INTPEND_BITS ; i++)
+				qprintf("%d",SNPDA(npda,j)->intr_dispatch1.info[i].ii_flags);
+		}
+		verbose = 1;
+	}
+	qprintf("\n Device - Target Map [Interrupts: %s Node%s]\n\n",
+		(verbose ? "All" : "Non-hardwired"),
+		(cnodeid == CNODEID_NONE) ? "s: All" : node_name); 
+		
+	qprintf("Device\tCpu\tCnode\tIntr_bit\tIntr_name\n");
+	for (i = 0 ; i < intr_dev_targ_map_size ; i++) {
+
+		print_flag = 0;
+		if (verbose) {
+			if (cnodeid != CNODEID_NONE) {
+				if (cnodeid == intr_dev_targ_map[i].cnodeid)
+					print_flag = 1;
+			} else {
+				print_flag = 1;
+			}
+		} else {
+			if (intr_dev_targ_map[i].dev != 0) {
+				if (cnodeid != CNODEID_NONE) {
+					if (cnodeid == 
+					    intr_dev_targ_map[i].cnodeid)
+						print_flag = 1;
+				} else {
+					print_flag = 1;
+				}
+			}
+		}
+		if (print_flag) {
+			size++;
+			qprintf("%d\t%d\t%d\t%d\t%s\n",
+				intr_dev_targ_map[i].dev,
+				intr_dev_targ_map[i].cpuid,
+				intr_dev_targ_map[i].cnodeid,
+				intr_dev_targ_map[i].bit,
+				intr_dev_targ_map[i].intr_name);
+		}
+
+	}
+	qprintf("\nTotal : %d\n",size);
+}
+#endif /* DEBUG */
+
+/*
+ * The spinlocks have already been initialized.  Now initialize the interrupt
+ * vectors.  One processor on each hub does the work.
+ */
+void
+intr_init_vecblk(nodepda_t *npda, cnodeid_t node, int sn)
+{
+    int			i, ip=0;
+    intr_vecblk_t	*vecblk;
+    subnode_pda_t	*snpda;
+
+
+    snpda = SNPDA(npda,sn);
+    do {
+	if (ip == 0) {
+	    vecblk = &snpda->intr_dispatch0;
+	} else {
+	    vecblk = &snpda->intr_dispatch1;
+	}
+
+	/* Initialize this vector. */
+	for (i = 0; i < N_INTPEND_BITS; i++) {
+		vecblk->vectors[i].iv_func = intr_stray;
+		vecblk->vectors[i].iv_prefunc = NULL;
+		vecblk->vectors[i].iv_arg = (void *)(__psint_t)(ip * N_INTPEND_BITS + i);
+
+		vecblk->info[i].ii_owner_dev = 0;
+		strcpy(vecblk->info[i].ii_name, "Unused");
+		vecblk->info[i].ii_flags = 0;	/* No flags */
+		vecblk->vectors[i].iv_mustruncpu = -1; /* No CPU yet. */
+
+	    }
+
+	mutex_spinlock_init(&vecblk->vector_lock);
+
+	vecblk->vector_count = 0;    
+	for (i = 0; i < CPUS_PER_SUBNODE; i++)
+		vecblk->cpu_count[i] = 0;
+
+	vecblk->vector_state = VECTOR_UNINITED;
+
+    } while (++ip < 2);
+
+}
+
+
+/*
+ * do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
+ *					devfs_handle_t owner_dev, char *name)
+ *	Internal work routine to reserve or unreserve an interrupt level.
+ *		cpu is the CPU to which the interrupt will be sent.
+ *		bit is the level bit to reserve.  -1 means any level
+ *		resflags should include II_ERRORINT if this is an
+ *			error interrupt, II_THREADED if the interrupt handler
+ *			will be threaded, or 0 otherwise.
+ *		reserve should be set to II_RESERVE or II_UNRESERVE
+ *			to get or clear a reservation.
+ *		owner_dev is the device that "owns" this interrupt, if supplied
+ *		name is a human-readable name for this interrupt, if supplied
+ *	intr_reserve_level returns the bit reserved or -1 to indicate an error
+ */
+static int
+do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
+					devfs_handle_t owner_dev, char *name)
+{
+    intr_vecblk_t	*vecblk;
+    hub_intmasks_t 	*hub_intmasks;
+    unsigned long s;
+    int rv = 0;
+    int ip;
+    synergy_da_t	*sda;
+    int		which_synergy;
+    cnodeid_t	cnode;
+
+    ASSERT(bit < N_INTPEND_BITS * 2);
+
+    cnode = cpuid_to_cnodeid(cpu);
+    which_synergy = cpuid_to_synergy(cpu);
+    sda = Synergy_da_indr[(cnode * 2) + which_synergy];
+    hub_intmasks = &sda->s_intmasks;
+    // hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
+
+    // if (pdaindr[cpu].pda == NULL) return -1;
+    if ((bit < N_INTPEND_BITS) && !(resflags & II_ERRORINT)) {
+	vecblk = hub_intmasks->dispatch0;
+	ip = 0;
+    } else {
+	ASSERT((bit >= N_INTPEND_BITS) || (bit == -1));
+	bit -= N_INTPEND_BITS;	/* Get position relative to INT_PEND1 reg. */
+	vecblk = hub_intmasks->dispatch1;
+	ip = 1;
+    }
+
+    INTR_LOCK(vecblk);
+
+    if (bit <= -1) {
+	bit = 0;
+	ASSERT(reserve == II_RESERVE);
+	/* Choose any available level */
+	for (; bit < N_INTPEND_BITS; bit++) {
+	    if (!(vecblk->info[bit].ii_flags & II_RESERVE)) {
+		rv = bit;
+		break;
+	    }
+	}
+
+	/* Return -1 if all interrupt levels int this register are taken. */
+	if (bit == N_INTPEND_BITS)
+	    rv = -1;
+
+    } else {
+	/* Reserve a particular level if it's available. */
+	if ((vecblk->info[bit].ii_flags & II_RESERVE) == reserve) {
+	    /* Can't (un)reserve a level that's already (un)reserved. */
+	    rv = -1;
+	} else {
+	    rv = bit;
+	}
+    }
+
+    /* Reserve the level and bump the count. */
+    if (rv != -1) {
+	if (reserve) {
+	    int maxlen = sizeof(vecblk->info[bit].ii_name) - 1;
+	    int namelen;
+	    vecblk->info[bit].ii_flags |= (II_RESERVE | resflags);
+	    vecblk->info[bit].ii_owner_dev = owner_dev;
+	    /* Copy in the name. */
+	    namelen = name ? strlen(name) : 0;
+	    strncpy(vecblk->info[bit].ii_name, name, min(namelen, maxlen)); 
+	    vecblk->info[bit].ii_name[maxlen] = '\0';
+	    vecblk->vector_count++;
+	} else {
+	    vecblk->info[bit].ii_flags = 0;	/* Clear all the flags */
+	    vecblk->info[bit].ii_owner_dev = 0;
+	    /* Clear the name. */
+	    vecblk->info[bit].ii_name[0] = '\0';
+	    vecblk->vector_count--;
+	}
+    }
+
+    INTR_UNLOCK(vecblk);
+
+#if defined(DEBUG)
+    if (rv >= 0) {
+	    int namelen = name ? strlen(name) : 0;
+	    /* Gather this device - target cpu mapping information
+	     * in a table which can be used later by the idbg "intrmap"
+	     * command
+	     */
+	    s = mutex_spinlock(&intr_dev_targ_map_lock);
+	    if (intr_dev_targ_map_size < MAX_DEVICES) {
+		    intr_dev_targ_map_t	*p;
+
+		    p 		= &intr_dev_targ_map[intr_dev_targ_map_size];
+		    p->dev  	= owner_dev;
+		    p->cpuid 	= cpu; 
+		    p->cnodeid 	= cpuid_to_cnodeid(cpu); 
+		    p->bit 	= ip * N_INTPEND_BITS + rv;
+		    strncpy(p->intr_name,
+			    name,
+			    min(MAX_NAME,namelen));
+		    intr_dev_targ_map_size++;
+	    }
+	    mutex_spinunlock(&intr_dev_targ_map_lock,s);
+    }
+#endif /* DEBUG */
+
+    return (((rv == -1) ? rv : (ip * N_INTPEND_BITS) + rv)) ;
+}
+
+
+/*
+ * WARNING:  This routine should only be called from within ml/SN.
+ *	Reserve an interrupt level.
+ */
+int
+intr_reserve_level(cpuid_t cpu, int bit, int resflags, devfs_handle_t owner_dev, char *name)
+{
+	return(do_intr_reserve_level(cpu, bit, resflags, II_RESERVE, owner_dev, name));
+}
+
+
+/*
+ * WARNING:  This routine should only be called from within ml/SN.
+ *	Unreserve an interrupt level.
+ */
+void
+intr_unreserve_level(cpuid_t cpu, int bit)
+{
+	(void)do_intr_reserve_level(cpu, bit, 0, II_UNRESERVE, 0, NULL);
+}
+
+/*
+ * Get values that vary depending on which CPU and bit we're operating on
+ */
+static hub_intmasks_t *
+intr_get_ptrs(cpuid_t cpu, int bit,
+	      int *new_bit,		/* Bit relative to the register */
+	      hubreg_t **intpend_masks, /* Masks for this register */
+	      intr_vecblk_t **vecblk,	/* Vecblock for this interrupt */
+	      int *ip)			/* Which intpend register */
+{
+	hub_intmasks_t *hub_intmasks;
+	synergy_da_t	*sda;
+	int		which_synergy;
+	cnodeid_t	cnode;
+
+	ASSERT(bit < N_INTPEND_BITS * 2);
+
+	cnode = cpuid_to_cnodeid(cpu);
+	which_synergy = cpuid_to_synergy(cpu);
+	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
+	hub_intmasks = &sda->s_intmasks;
+
+	// hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
+
+	if (bit < N_INTPEND_BITS) {
+		*intpend_masks = hub_intmasks->intpend0_masks;
+		*vecblk = hub_intmasks->dispatch0;
+		*ip = 0;
+		*new_bit = bit;
+	} else {
+		*intpend_masks = hub_intmasks->intpend1_masks;
+		*vecblk = hub_intmasks->dispatch1;
+		*ip = 1;
+		*new_bit = bit - N_INTPEND_BITS;
+	}
+
+	return hub_intmasks;
+}
+
+
+/*
+ * intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
+ *		intr_func_t intr_func, void *intr_arg);
+ *	This is the lowest-level interface to the interrupt code.  It shouldn't
+ *	be called from outside the ml/SN directory.
+ *	intr_connect_level hooks up an interrupt to a particular bit in
+ *	the INT_PEND0/1 masks.  Returns 0 on success.
+ *		cpu is the CPU to which the interrupt will be sent.
+ *		bit is the level bit to connect to
+ *		intr_swlevel tells which software level to use
+ *		intr_func is the interrupt handler
+ *		intr_arg is an arbitrary argument interpreted by the handler
+ *		intr_prefunc is a prologue function, to be called
+ *			with interrupts disabled, to disable
+ *			the interrupt at source.  It is called
+ *			with the same argument.  Should be NULL for
+ *			typical interrupts, which can be masked
+ *			by the infrastructure at the level bit.
+ *	intr_connect_level returns 0 on success or nonzero on an error
+ */
+/* ARGSUSED */
+int
+intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, intr_func_t intr_prefunc)
+{
+    intr_vecblk_t	*vecblk;
+    hubreg_t		*intpend_masks;
+    int rv = 0;
+    int ip;
+    unsigned long s;
+
+    ASSERT(bit < N_INTPEND_BITS * 2);
+
+    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
+				 &vecblk, &ip);
+
+    INTR_LOCK(vecblk);
+
+    if ((vecblk->info[bit].ii_flags & II_INUSE) ||
+	(!(vecblk->info[bit].ii_flags & II_RESERVE))) {
+	/* Can't assign to a level that's in use or isn't reserved. */
+	rv = -1;
+    } else {
+	/* Stuff parameters into vector and info */
+	vecblk->vectors[bit].iv_prefunc = intr_prefunc;
+	vecblk->info[bit].ii_flags |= II_INUSE;
+    }
+
+    /* Now stuff the masks if everything's okay. */
+    if (!rv) {
+	int lslice;
+	volatile hubreg_t *mask_reg;
+	// nasid_t nasid = COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu));
+	nasid_t nasid = cpuid_to_nasid(cpu);
+	int	subnode = cpuid_to_subnode(cpu);
+
+	/* Make sure it's not already pending when we connect it. */
+	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit + ip * N_INTPEND_BITS);
+
+	if (bit >= GFX_INTR_A && bit <= CC_PEND_B) {
+		intpend_masks[0] |= (1ULL << (uint64_t)bit);
+	}
+
+	lslice = cpuid_to_localslice(cpu);
+	vecblk->cpu_count[lslice]++;
+#if SN1
+	/*
+	 * On SN1, there are 8 interrupt mask registers per node:
+	 * 	PI_0 MASK_0 A
+	 * 	PI_0 MASK_1 A
+	 * 	PI_0 MASK_0 B
+	 * 	PI_0 MASK_1 B
+	 * 	PI_1 MASK_0 A
+	 * 	PI_1 MASK_1 A
+	 * 	PI_1 MASK_0 B
+	 * 	PI_1 MASK_1 B
+	 */
+#endif
+	if (ip == 0) {
+		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode, 
+		        PI_INT_MASK0_A + PI_INT_MASK_OFFSET * lslice);
+	} else {
+		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode,
+			PI_INT_MASK1_A + PI_INT_MASK_OFFSET * lslice);
+	}
+
+	HUB_S(mask_reg, intpend_masks[0]);
+    }
+
+    INTR_UNLOCK(vecblk);
+
+    return rv;
+}
+
+
+/*
+ * intr_disconnect_level(cpuid_t cpu, int bit)
+ *
+ *	This is the lowest-level interface to the interrupt code.  It should
+ *	not be called from outside the ml/SN directory.
+ *	intr_disconnect_level removes a particular bit from an interrupt in
+ * 	the INT_PEND0/1 masks.  Returns 0 on success or nonzero on failure.
+ */
+int
+intr_disconnect_level(cpuid_t cpu, int bit)
+{
+    intr_vecblk_t	*vecblk;
+    hubreg_t		*intpend_masks;
+    unsigned long s;
+    int rv = 0;
+    int ip;
+
+    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
+				 &vecblk, &ip);
+
+    INTR_LOCK(vecblk);
+
+    if ((vecblk->info[bit].ii_flags & (II_RESERVE | II_INUSE)) !=
+	((II_RESERVE | II_INUSE))) {
+	/* Can't remove a level that's not in use or isn't reserved. */
+	rv = -1;
+    } else {
+	/* Stuff parameters into vector and info */
+	vecblk->vectors[bit].iv_func = (intr_func_t)NULL;
+	vecblk->vectors[bit].iv_prefunc = (intr_func_t)NULL;
+	vecblk->vectors[bit].iv_arg = 0;
+	vecblk->info[bit].ii_flags &= ~II_INUSE;
+#ifdef BASE_ITHRTEAD
+	vecblk->vectors[bit].iv_mustruncpu = -1; /* No mustrun CPU any more. */
+#endif
+    }
+
+    /* Now clear the masks if everything's okay. */
+    if (!rv) {
+	int lslice;
+	volatile hubreg_t *mask_reg;
+
+	intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
+	lslice = cpuid_to_localslice(cpu);
+	vecblk->cpu_count[lslice]--;
+	mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+				   cpuid_to_subnode(cpu),
+				   ip == 0 ? PI_INT_MASK0_A : PI_INT_MASK1_A);
+	mask_reg = (volatile hubreg_t *)((__psunsigned_t)mask_reg +
+					(PI_INT_MASK_OFFSET * lslice));
+	*mask_reg = intpend_masks[0];
+    }
+
+    INTR_UNLOCK(vecblk);
+
+    return rv;
+}
+
+/*
+ * Actually block or unblock an interrupt
+ */
+void
+do_intr_block_bit(cpuid_t cpu, int bit, int block)
+{
+	intr_vecblk_t *vecblk;
+	int ip;
+	unsigned long s;
+	hubreg_t *intpend_masks;
+	volatile hubreg_t mask_value;
+	volatile hubreg_t *mask_reg;
+
+	intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &vecblk, &ip);
+
+	INTR_LOCK(vecblk);
+
+	if (block)
+		/* Block */
+		intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
+	else
+		/* Unblock */
+		intpend_masks[0] |= (1ULL << (uint64_t)bit);
+
+	if (ip == 0) {
+		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+		        cpuid_to_subnode(cpu), PI_INT_MASK0_A);
+	} else {
+		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+			cpuid_to_subnode(cpu), PI_INT_MASK1_A);
+	}
+
+	HUB_S(mask_reg, intpend_masks[0]);
+
+	/*
+	 * Wait for it to take effect.  (One read should suffice.)
+	 * This is only necessary when blocking an interrupt
+	 */
+	if (block)
+		while ((mask_value = HUB_L(mask_reg)) != intpend_masks[0])
+			;
+
+	INTR_UNLOCK(vecblk);
+}
+
+
+/*
+ * Block a particular interrupt (cpu/bit pair).
+ */
+/* ARGSUSED */
+void
+intr_block_bit(cpuid_t cpu, int bit)
+{
+	do_intr_block_bit(cpu, bit, 1);
+}
+
+
+/*
+ * Unblock a particular interrupt (cpu/bit pair).
+ */
+/* ARGSUSED */
+void
+intr_unblock_bit(cpuid_t cpu, int bit)
+{
+	do_intr_block_bit(cpu, bit, 0);
+}
+
+
+/* verifies that the specified CPUID is on the specified SUBNODE (if any) */
+#define cpu_on_subnode(cpuid, which_subnode) \
+	   (((which_subnode) == SUBNODE_ANY) || (cpuid_to_subnode(cpuid) == (which_subnode)))
+
+
+/*
+ * Choose one of the CPUs on a specified node or subnode to receive
+ * interrupts. Don't pick a cpu which has been specified as a NOINTR cpu.
+ *
+ * Among all acceptable CPUs, the CPU that has the fewest total number
+ * of interrupts targetted towards it is chosen.  Note that we never
+ * consider how frequent each of these interrupts might occur, so a rare
+ * hardware error interrupt is weighted equally with a disk interrupt.
+ */
+static cpuid_t
+do_intr_cpu_choose(cnodeid_t cnode, int which_subnode)
+{
+	cpuid_t 	cpu, best_cpu = CPU_NONE;
+	int		slice, min_count=1000;
+
+	min_count = 1000;
+	for (slice=0; slice < CPUS_PER_NODE; slice++) {
+		intr_vecblk_t 	*vecblk0, *vecblk1;
+		int total_intrs_to_slice;
+		subnode_pda_t *snpda;
+		int local_cpu_num;
+
+		cpu = cnode_slice_to_cpuid(cnode, slice);
+		if (cpu == CPU_NONE)
+			continue;
+
+		/* If this cpu isn't enabled for interrupts, skip it */
+		if (!cpu_enabled(cpu) || !cpu_allows_intr(cpu))
+			continue;
+
+		/* If this isn't the right subnode, skip it */
+		if (!cpu_on_subnode(cpu, which_subnode))
+			continue;
+
+		/* OK, this one's a potential CPU for interrupts */
+		snpda = SUBNODEPDA(cnode,SUBNODE(slice));
+		vecblk0 = &snpda->intr_dispatch0;
+		vecblk1 = &snpda->intr_dispatch1;
+		local_cpu_num = LOCALCPU(slice);
+		total_intrs_to_slice = vecblk0->cpu_count[local_cpu_num] +
+		              vecblk1->cpu_count[local_cpu_num];
+
+		if (min_count > total_intrs_to_slice) {
+			min_count = total_intrs_to_slice;
+			best_cpu = cpu;
+		}
+	}
+	return best_cpu;
+}
+
+/*
+ * Choose an appropriate interrupt target CPU on a specified node.
+ * If which_subnode is SUBNODE_ANY, then subnode is not considered.
+ * Otherwise, the chosen CPU must be on the specified subnode.
+ */
+static cpuid_t
+intr_cpu_choose_from_node(cnodeid_t cnode, int which_subnode)
+{
+	return(do_intr_cpu_choose(cnode, which_subnode));
+}
+
+
+/* Make it easy to identify subnode vertices in the hwgraph */
+void
+mark_subnodevertex_as_subnode(devfs_handle_t vhdl, int which_subnode)
+{
+	graph_error_t rv;
+
+	ASSERT(0 <= which_subnode);
+	ASSERT(which_subnode < NUM_SUBNODES);
+
+	rv = hwgraph_info_add_LBL(vhdl, INFO_LBL_CPUBUS, (arbitrary_info_t)which_subnode);
+	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
+
+	rv = hwgraph_info_export_LBL(vhdl, INFO_LBL_CPUBUS, sizeof(arbitrary_info_t));
+	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ * Given a device descriptor, extract interrupt target information and
+ * choose an appropriate CPU.  Return CPU_NONE if we can't make sense
+ * out of the target information.
+ * TBD: Should this be considered platform-independent code?
+ */
+
+
+/*
+ * intr_bit_reserve_test(cpuid,which_subnode,cnode,req_bit,intr_resflags,
+ *		owner_dev,intr_name,*resp_bit)
+ *	Either cpuid is not CPU_NONE or cnodeid not CNODE_NONE but
+ * 	not both.
+ * 1. 	If cpuid is specified, this routine tests if this cpu can be a valid
+ * 	interrupt target candidate.
+ * 2. 	If cnodeid is specified, this routine tests if there is a cpu on 
+ *	this node which can be a valid interrupt target candidate.
+ * 3.	If a valid interrupt target cpu candidate is found then an attempt at 
+ * 	reserving an interrupt bit on the corresponding cnode is made.
+ *
+ * If steps 1 & 2 both fail or step 3 fails then we are not able to get a valid
+ * interrupt target cpu then routine returns CPU_NONE (failure)
+ * Otherwise routine returns cpuid of interrupt target (success)
+ */
+static cpuid_t
+intr_bit_reserve_test(cpuid_t 		cpuid,
+		      int		favor_subnode,
+		      cnodeid_t 	cnodeid,
+		      int		req_bit,
+		      int 		intr_resflags,
+		      devfs_handle_t 	owner_dev,
+		      char		*intr_name,
+		      int		*resp_bit)
+{
+
+	ASSERT((cpuid==CPU_NONE) || (cnodeid==CNODEID_NONE));
+
+	if (cnodeid != CNODEID_NONE) {
+		/* Try to choose a interrupt cpu candidate */
+		cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
+	}
+
+	if (cpuid != CPU_NONE) {
+		/* Try to reserve an interrupt bit on the hub 
+		 * corresponding to the canidate cnode. If we
+		 * are successful then we got a cpu which can
+		 * act as an interrupt target for the io device.
+		 * Otherwise we need to continue the search
+		 * further.
+		 */
+		*resp_bit = do_intr_reserve_level(cpuid, 
+						  req_bit,
+						  intr_resflags,
+						  II_RESERVE,
+						  owner_dev, 
+						  intr_name);
+
+		if (*resp_bit >= 0)
+			/* The interrupt target  specified was fine */
+			return(cpuid);
+	}
+	return(CPU_NONE);
+}
+/*
+ * intr_heuristic(dev_t dev,device_desc_t dev_desc,
+ *		  int req_bit,int intr_resflags,dev_t owner_dev,
+ *		  char *intr_name,int *resp_bit)
+ *
+ * Choose an interrupt destination for an interrupt.
+ *	dev is the device for which the interrupt is being set up
+ *	dev_desc is a description of hardware and policy that could
+ *		help determine where this interrupt should go
+ *	req_bit is the interrupt bit requested 
+ *		(can be INTRCONNECT_ANY_BIT in which the first available
+ * 		 interrupt bit is used)
+ *	intr_resflags indicates whether we want to (un)reserve bit
+ *	owner_dev is the owner device
+ *	intr_name is the readable interrupt name	
+ * 	resp_bit indicates whether we succeeded in getting the required
+ *		 action  { (un)reservation} done	
+ *		 negative value indicates failure
+ *
+ */
+/* ARGSUSED */
+cpuid_t
+intr_heuristic(devfs_handle_t 		dev,
+	       device_desc_t 	dev_desc,
+	       int		req_bit,
+	       int 		intr_resflags,
+	       devfs_handle_t 		owner_dev,
+	       char		*intr_name,
+	       int		*resp_bit)
+{
+	cpuid_t		cpuid;				/* possible intr targ*/
+	cnodeid_t 	candidate;			/* possible canidate */
+	int		which_subnode = SUBNODE_ANY;
+
+/* SN1 + pcibr Addressing Limitation */
+	{
+	devfs_handle_t pconn_vhdl;
+	pcibr_soft_t pcibr_soft;
+
+	/*
+	 * This combination of SN1 and Bridge hardware has an odd "limitation".
+	 * Due to the choice of addresses for PI0 and PI1 registers on SN1
+	 * and historical limitations in Bridge, Bridge is unable to
+	 * send interrupts to both PI0 CPUs and PI1 CPUs -- we have
+	 * to choose one set or the other.  That choice is implicitly
+	 * made when Bridge first attaches its error interrupt.  After
+	 * that point, all subsequent interrupts are restricted to the
+	 * same PI number (though it's possible to send interrupts to
+	 * the same PI number on a different node).
+	 *
+	 * Since neither SN1 nor Bridge designers are willing to admit a
+	 * bug, we can't really call this a "workaround".  It's a permanent
+	 * solution for an SN1-specific and Bridge-specific hardware
+	 * limitation that won't ever be lifted.
+	 */
+        if ((hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
+	   ((pcibr_soft = pcibr_soft_get(pconn_vhdl)) != NULL)) {
+		/*
+		 * We "know" that the error interrupt is the first
+		 * interrupt set up by pcibr_attach.  Send all interrupts
+		 * on this bridge to the same subnode number.
+		 */
+		if (pcibr_soft->bsi_err_intr) {
+			which_subnode = cpuid_to_subnode(((hub_intr_t) pcibr_soft->bsi_err_intr)->i_cpuid);
+		}
+	}
+	}
+
+	/* Check if we can find a valid interrupt target candidate on
+	 * the master node for the device.
+	 */
+	cpuid = intr_bit_reserve_test(CPU_NONE,
+				      which_subnode,	
+				      master_node_get(dev),
+				      req_bit,
+				      intr_resflags,
+				      owner_dev,
+				      intr_name,
+				      resp_bit);
+
+	if (cpuid != CPU_NONE) {
+		if (cpu_on_subnode(cpuid, which_subnode))
+			return(cpuid);	/* got a valid interrupt target */
+		else
+			intr_unreserve_level(cpuid, *resp_bit);
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts to closest node(%d): (0x%lx)\n",
+		master_node_get(dev),(unsigned long)owner_dev);
+
+	/* Fall through into the default algorithm
+	 * (exhaustive-search-for-the-nearest-possible-interrupt-target)
+	 * for finding the interrupt target
+	 */
+
+	{
+	/*
+	 * Do a stupid round-robin assignment of the node.
+	 *  (Should do a "nearest neighbor" but not for SN1.
+	 */
+		static cnodeid_t last_node = -1;
+
+		if (last_node >= numnodes) last_node = 0;
+		for (candidate = last_node + 1; candidate != last_node; candidate++) {
+			if (candidate == numnodes) candidate = 0;
+			cpuid = intr_bit_reserve_test(CPU_NONE,
+					      which_subnode,
+					      candidate,
+					      req_bit,
+					      intr_resflags,
+					      owner_dev,
+					      intr_name,
+					      resp_bit);
+
+			if (cpuid != CPU_NONE) {
+				if (cpu_on_subnode(cpuid, which_subnode)) {
+					last_node = candidate;
+					return(cpuid);	/* got a valid interrupt target */
+				}
+				else
+					intr_unreserve_level(cpuid, *resp_bit);
+			}
+		}
+		last_node = candidate;
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts to any close node: %ld (0x%lx)\n",
+		(long)owner_dev, (unsigned long)owner_dev);
+
+	/* In the worst case try to allocate interrupt bits on the
+	 * master processor's node. We may get here during error interrupt
+	 * allocation phase when the topology matrix is not yet setup
+	 * and hence cannot do an exhaustive search.
+	 */
+	ASSERT(cpu_allows_intr(master_procid));
+	cpuid = intr_bit_reserve_test(master_procid,
+				      which_subnode,
+				      CNODEID_NONE,
+				      req_bit,
+				      intr_resflags,
+				      owner_dev,
+				      intr_name,
+				      resp_bit);
+
+	if (cpuid != CPU_NONE) {
+		if (cpu_on_subnode(cpuid, which_subnode))
+			return(cpuid);
+		else
+			intr_unreserve_level(cpuid, *resp_bit);
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts: (0x%lx)\n",
+		(unsigned long)owner_dev);
+
+	return(CPU_NONE);	/* Should never get here */
+}
+
+struct hardwired_intr_s {
+	signed char level;
+	int flags;
+	char *name;
+} const hardwired_intr[] = {
+	{ INT_PEND0_BASELVL + RESERVED_INTR,	0,	"Reserved" },
+	{ INT_PEND0_BASELVL + GFX_INTR_A,	0, 	"Gfx A" },
+	{ INT_PEND0_BASELVL + GFX_INTR_B,	0, 	"Gfx B" },
+	{ INT_PEND0_BASELVL + PG_MIG_INTR,	II_THREADED, "Migration" },
+	{ INT_PEND0_BASELVL + UART_INTR,	II_THREADED, "Bedrock/L1" },
+	{ INT_PEND0_BASELVL + CC_PEND_A,	0,	"Crosscall A" },
+	{ INT_PEND0_BASELVL + CC_PEND_B,	0,	"Crosscall B" },
+	{ INT_PEND1_BASELVL + CLK_ERR_INTR,	II_ERRORINT, "Clock Error" },
+	{ INT_PEND1_BASELVL + COR_ERR_INTR_A,	II_ERRORINT, "Correctable Error A" },
+	{ INT_PEND1_BASELVL + COR_ERR_INTR_B,	II_ERRORINT, "Correctable Error B" },
+	{ INT_PEND1_BASELVL + MD_COR_ERR_INTR,	II_ERRORINT, "MD Correct. Error" },
+	{ INT_PEND1_BASELVL + NI_ERROR_INTR,	II_ERRORINT, "NI Error" },
+	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_A,	II_ERRORINT, "Remote NI Error"},
+	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_B,	II_ERRORINT, "Remote NI Error"},
+	{ INT_PEND1_BASELVL + MSC_PANIC_INTR,	II_ERRORINT, "MSC Panic" },
+	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_A,	II_ERRORINT, "LLP Pfail WAR" },
+	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_B,	II_ERRORINT, "LLP Pfail WAR" },
+	{ INT_PEND1_BASELVL + NACK_INT_A,	0, "CPU A Nack count == NACK_CMP" },
+	{ INT_PEND1_BASELVL + NACK_INT_B,	0, "CPU B Nack count == NACK_CMP" },
+	{ INT_PEND1_BASELVL + LB_ERROR,		0, "Local Block Error" },
+	{ INT_PEND1_BASELVL + XB_ERROR,		0, "Local XBar Error" },
+	{ -1, 0, (char *)NULL},
+};
+
+/*
+ * Reserve all of the hardwired interrupt levels so they're not used as
+ * general purpose bits later.
+ */
+void
+intr_reserve_hardwired(cnodeid_t cnode)
+{
+	cpuid_t cpu;
+	int level;
+	int i;
+	char subnode_done[NUM_SUBNODES];
+
+	// cpu = cnodetocpu(cnode);
+	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
+		if (cpuid_to_cnodeid(cpu) == cnode) {
+			break;
+		}
+	}
+	if (cpu == smp_num_cpus) cpu = CPU_NONE;
+	if (cpu == CPU_NONE) {
+		printk("Node %d has no CPUs", cnode);
+		return;
+	}
+
+	for (i=0; i<NUM_SUBNODES; i++)
+		subnode_done[i] = 0;
+
+	for (; cpu<smp_num_cpus && cpu_enabled(cpu) && cpuid_to_cnodeid(cpu) == cnode; cpu++) {
+		int which_subnode = cpuid_to_subnode(cpu);
+		if (subnode_done[which_subnode])
+			continue;
+		subnode_done[which_subnode] = 1;
+
+		for (i = 0; hardwired_intr[i].level != -1; i++) {
+			level = hardwired_intr[i].level;
+
+			if (level != intr_reserve_level(cpu, level,
+						hardwired_intr[i].flags,
+						(devfs_handle_t) NULL,
+						hardwired_intr[i].name))
+				panic("intr_reserve_hardwired: Can't reserve level %d, cpu %ld.", level, cpu);
+		}
+	}
+}
+
+
+/*
+ * Check and clear interrupts.
+ */
+/*ARGSUSED*/
+static void
+intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level,
+		char *name)
+{
+	volatile hubreg_t bits;
+	int i;
+
+	/* Check pending interrupts */
+	if ((bits = HUB_L(pend)) != 0) {
+		for (i = 0; i < N_INTPEND_BITS; i++) {
+			if (bits & (1 << i)) {
+#ifdef INTRDEBUG
+				printk(KERN_WARNING  "Nasid %d interrupt bit %d set in %s",
+					nasid, i, name);
+#endif
+				LOCAL_HUB_CLR_INTR(base_level + i);
+			}
+		}
+	}
+}
+
+/*
+ * Clear out our interrupt registers.
+ */
+void
+intr_clear_all(nasid_t nasid)
+{
+	int	sn;
+
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_A, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_B, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_A, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_B, 0);
+	
+		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND0),
+				INT_PEND0_BASELVL, "INT_PEND0");
+		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND1),
+				INT_PEND1_BASELVL, "INT_PEND1");
+	}
+}
+
+/* 
+ * Dump information about a particular interrupt vector.
+ */
+static void
+dump_vector(intr_info_t *info, intr_vector_t *vector, int bit, hubreg_t ip,
+		hubreg_t ima, hubreg_t imb, void (*pf)(char *, ...))
+{
+	hubreg_t value = 1LL << bit;
+
+	pf("  Bit %02d: %s: func 0x%x arg 0x%x prefunc 0x%x\n",
+		bit, info->ii_name,
+		vector->iv_func, vector->iv_arg, vector->iv_prefunc);
+	pf("   vertex 0x%x %s%s",
+		info->ii_owner_dev,
+		((info->ii_flags) & II_RESERVE) ? "R" : "U",
+		((info->ii_flags) & II_INUSE) ? "C" : "-");
+	pf("%s%s%s%s",
+		ip & value ? "P" : "-",
+		ima & value ? "A" : "-",
+		imb & value ? "B" : "-",
+		((info->ii_flags) & II_ERRORINT) ? "E" : "-");
+	pf("\n");
+}
+
+
+/*
+ * Dump information about interrupt vector assignment.
+ */
+void
+intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...))
+{
+	nodepda_t *npda;
+	int ip, sn, bit;
+	intr_vecblk_t *dispatch;
+	hubreg_t ipr, ima, imb;
+	nasid_t nasid;
+
+	if ((cnode < 0) || (cnode >= numnodes)) {
+		pf("intr_dumpvec: cnodeid out of range: %d\n", cnode);
+		return ;
+	}
+
+	nasid = COMPACT_TO_NASID_NODEID(cnode);
+
+	if (nasid == INVALID_NASID) {
+		pf("intr_dumpvec: Bad cnodeid: %d\n", cnode);
+		return ;
+	}
+		
+
+	npda = NODEPDA(cnode);
+
+	for (sn = 0; sn < NUM_SUBNODES; sn++) {
+		for (ip = 0; ip < 2; ip++) {
+			dispatch = ip ? &(SNPDA(npda,sn)->intr_dispatch1) : &(SNPDA(npda,sn)->intr_dispatch0);
+			ipr = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_PEND1 : PI_INT_PEND0);
+			ima = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_A : PI_INT_MASK0_A);
+			imb = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_B : PI_INT_MASK0_B);
+	
+			pf("Node %d INT_PEND%d:\n", cnode, ip);
+	
+			if (dispatch->ithreads_enabled)
+				pf(" Ithreads enabled\n");
+			else
+				pf(" Ithreads disabled\n");
+			pf(" vector_count = %d, vector_state = %d\n",
+				dispatch->vector_count,
+				dispatch->vector_state);
+			pf(" CPU A count %d, CPU B count %d\n",
+ 		   	dispatch->cpu_count[0],
+ 		   	dispatch->cpu_count[1]);
+			pf(" &vector_lock = 0x%x\n",
+				&(dispatch->vector_lock));
+			for (bit = 0; bit < N_INTPEND_BITS; bit++) {
+				if ((dispatch->info[bit].ii_flags & II_RESERVE) ||
+			    	(ipr & (1L << bit))) {
+					dump_vector(&(dispatch->info[bit]),
+					    	&(dispatch->vectors[bit]),
+					    	bit, ipr, ima, imb, pf);
+				}
+			}
+			pf("\n");
+		}
+	}
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn1/pcibr.c linux/arch/ia64/sn/io/sn1/pcibr.c
--- linux.orig/arch/ia64/sn/io/sn1/pcibr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn1/pcibr.c	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,7950 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+int NeedXbridgeSwap = 0;
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+extern boolean_t                is_sys_critical_vertex(devfs_handle_t);
+
+#undef PCIBR_ATE_DEBUG
+
+#if 0
+#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */
+#endif
+#define PCI_DEBUG 1
+#define ATTACH_DEBUG 1
+#define PCIBR_SOFT_LIST 1
+
+#ifndef	LOCAL
+#define	LOCAL		static
+#endif
+
+/*
+ * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
+ * appears that if the lucent part can get into a retry loop if it sees a
+ * DAC on the bus during a pio read retry.  The loop is broken after about
+ * 1ms, so we need to set up bridges holding this part to allow at least
+ * 1ms for pio.
+ */
+
+#define USS302_TIMEOUT_WAR
+
+#ifdef USS302_TIMEOUT_WAR
+#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
+#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
+#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
+#define USS302_BRIDGE_TIMEOUT_HLD	4
+#endif
+
+#define PCIBR_LLP_CONTROL_WAR
+#if defined (PCIBR_LLP_CONTROL_WAR)
+int                     pcibr_llp_control_war_cnt;
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+int                     pcibr_devflag = D_MP;
+
+#ifdef LATER
+#define F(s,n)		{ 1l<<(s),-(s), n }
+
+struct reg_desc         bridge_int_status_desc[] =
+{
+    F(31, "MULTI_ERR"),
+    F(30, "PMU_ESIZE_EFAULT"),
+    F(29, "UNEXPECTED_RESP"),
+    F(28, "BAD_XRESP_PACKET"),
+    F(27, "BAD_XREQ_PACKET"),
+    F(26, "RESP_XTALK_ERROR"),
+    F(25, "REQ_XTALK_ERROR"),
+    F(24, "INVALID_ADDRESS"),
+    F(23, "UNSUPPORTED_XOP"),
+    F(22, "XREQ_FIFO_OFLOW"),
+    F(21, "LLP_REC_SNERROR"),
+    F(20, "LLP_REC_CBERROR"),
+    F(19, "LLP_RCTY"),
+    F(18, "LLP_TX_RETRY"),
+    F(17, "LLP_TCTY"),
+    F(16, "SSRAM_PERR"),
+    F(15, "PCI_ABORT"),
+    F(14, "PCI_PARITY"),
+    F(13, "PCI_SERR"),
+    F(12, "PCI_PERR"),
+    F(11, "PCI_MASTER_TOUT"),
+    F(10, "PCI_RETRY_CNT"),
+    F(9, "XREAD_REQ_TOUT"),
+    F(8, "GIO_BENABLE_ERR"),
+    F(7, "INT7"),
+    F(6, "INT6"),
+    F(5, "INT5"),
+    F(4, "INT4"),
+    F(3, "INT3"),
+    F(2, "INT2"),
+    F(1, "INT1"),
+    F(0, "INT0"),
+    {0}
+};
+
+struct reg_values       space_v[] =
+{
+    {PCIIO_SPACE_NONE, "none"},
+    {PCIIO_SPACE_ROM, "ROM"},
+    {PCIIO_SPACE_IO, "I/O"},
+    {PCIIO_SPACE_MEM, "MEM"},
+    {PCIIO_SPACE_MEM32, "MEM(32)"},
+    {PCIIO_SPACE_MEM64, "MEM(64)"},
+    {PCIIO_SPACE_CFG, "CFG"},
+    {PCIIO_SPACE_WIN(0), "WIN(0)"},
+    {PCIIO_SPACE_WIN(1), "WIN(1)"},
+    {PCIIO_SPACE_WIN(2), "WIN(2)"},
+    {PCIIO_SPACE_WIN(3), "WIN(3)"},
+    {PCIIO_SPACE_WIN(4), "WIN(4)"},
+    {PCIIO_SPACE_WIN(5), "WIN(5)"},
+    {PCIIO_SPACE_BAD, "BAD"},
+    {0}
+};
+
+struct reg_desc         space_desc[] =
+{
+    {0xFF, 0, "space", 0, space_v},
+    {0}
+};
+
+#if DEBUG
+#define	device_desc	device_bits
+LOCAL struct reg_desc   device_bits[] =
+{
+    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
+    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
+    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
+    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
+    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
+    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
+    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
+    {BRIDGE_DEV_RT, 0, "RT"},
+    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
+    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
+    {BRIDGE_DEV_PREF, 0, "PREF"},
+    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
+    {BRIDGE_DEV_COH, 0, "COH"},
+    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
+    {BRIDGE_DEV_GBR, 0, "GBR"},
+    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
+    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
+    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
+    {0}
+};
+#endif	/* DEBUG */
+
+#ifdef SUPPORT_PRINTING_R_FORMAT
+LOCAL struct reg_values xio_cmd_pactyp[] =
+{
+    {0x0, "RdReq"},
+    {0x1, "RdResp"},
+    {0x2, "WrReqWithResp"},
+    {0x3, "WrResp"},
+    {0x4, "WrReqNoResp"},
+    {0x5, "Reserved(5)"},
+    {0x6, "FetchAndOp"},
+    {0x7, "Reserved(7)"},
+    {0x8, "StoreAndOp"},
+    {0x9, "Reserved(9)"},
+    {0xa, "Reserved(a)"},
+    {0xb, "Reserved(b)"},
+    {0xc, "Reserved(c)"},
+    {0xd, "Reserved(d)"},
+    {0xe, "SpecialReq"},
+    {0xf, "SpecialResp"},
+    {0}
+};
+
+LOCAL struct reg_desc   xio_cmd_bits[] =
+{
+    {WIDGET_DIDN, -28, "DIDN", "%x"},
+    {WIDGET_SIDN, -24, "SIDN", "%x"},
+    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
+    {WIDGET_TNUM, -15, "TNUM", "%x"},
+    {WIDGET_COHERENT, 0, "COHERENT"},
+    {WIDGET_DS, 0, "DS"},
+    {WIDGET_GBR, 0, "GBR"},
+    {WIDGET_VBPM, 0, "VBPM"},
+    {WIDGET_ERROR, 0, "ERROR"},
+    {WIDGET_BARRIER, 0, "BARRIER"},
+    {0}
+};
+#endif	/* SUPPORT_PRINTING_R_FORMAT */
+
+#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUG
+LOCAL struct reg_desc   ate_bits[] =
+{
+    {0xFFFF000000000000ull, -48, "RMF", "%x"},
+    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
+     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
+    {0x0000000000000F00ull, -8, "port", "%x"},
+    {0x0000000000000010ull, 0, "Barrier"},
+    {0x0000000000000008ull, 0, "Prefetch"},
+    {0x0000000000000004ull, 0, "Precise"},
+    {0x0000000000000002ull, 0, "Coherent"},
+    {0x0000000000000001ull, 0, "Valid"},
+    {0}
+};
+#endif
+
+#if PCIBR_ATE_DEBUG
+LOCAL struct reg_values ssram_sizes[] =
+{
+    {BRIDGE_CTRL_SSRAM_512K, "512k"},
+    {BRIDGE_CTRL_SSRAM_128K, "128k"},
+    {BRIDGE_CTRL_SSRAM_64K, "64k"},
+    {BRIDGE_CTRL_SSRAM_1K, "1k"},
+    {0}
+};
+
+LOCAL struct reg_desc   control_bits[] =
+{
+    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
+    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
+    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
+    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
+    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
+    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
+    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
+    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
+    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
+    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
+    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
+    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
+    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
+    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
+    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
+    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
+    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},
+    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+/* kbrick widgetnum-to-bus layout */
+int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
+        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
+        2,                                      /* 0x8          */
+        1,                                      /* 0x9          */
+        0, 0,                                   /* 0xa - 0xb    */
+        5,                                      /* 0xc          */
+        6,                                      /* 0xd          */
+        4,                                      /* 0xe          */
+        3,                                      /* 0xf          */
+};
+
+/*
+ * Additional PIO spaces per slot are
+ * recorded in this structure.
+ */
+struct pciio_piospace_s {
+    pciio_piospace_t        next;	/* another space for this device */
+    char                    free;	/* 1 if free, 0 if in use               */
+    pciio_space_t           space;	/* Which space is in use                */
+    iopaddr_t               start;	/* Starting address of the PIO space    */
+    size_t                  count;	/* size of PIO space                    */
+};
+
+#if PCIBR_SOFT_LIST
+pcibr_list_p            pcibr_list = 0;
+#endif
+
+#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"
+
+#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)
+#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)
+
+#define PCIBR_VALID_SLOT(s)	(s < 8)
+
+#ifdef SN_XXX
+extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
+                                     hub_widget_flags_t flags);
+#endif
+extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
+extern void free_pciio_dmamap(pcibr_dmamap_t);
+
+/*
+ * This is the file operation table for the pcibr driver.
+ * As each of the functions are implemented, put the 
+ * appropriate function name below.
+ */
+struct file_operations pcibr_fops = {
+        owner:  THIS_MODULE,
+        llseek: NULL,
+        read: NULL,
+        write: NULL,
+        readdir: NULL,
+        poll: NULL,
+        ioctl: NULL,
+        mmap: NULL,
+        open: NULL,
+        flush: NULL,
+        release: NULL,
+        fsync: NULL,
+        fasync: NULL,
+        lock: NULL,
+        readv: NULL,
+        writev: NULL
+};
+
+extern devfs_handle_t hwgraph_root;
+extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);
+extern int cap_able(uint64_t x);
+extern uint64_t rmalloc(struct map *mp, size_t size);
+extern void rmfree(struct map *mp, size_t size, uint64_t a);
+extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
+extern long atoi(register char *p);
+extern void *swap_ptr(void **loc, void *new);
+extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
+extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);
+extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);
+extern struct map *rmallocmap(uint64_t mapsiz);
+extern void rmfreemap(struct map *mp);
+extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);
+extern int io_path_map_widget(devfs_handle_t vertex);
+
+
+
+/* =====================================================================
+ *    Function Table of Contents
+ *
+ *      The order of functions in this file has stopped
+ *      making much sense. We might want to take a look
+ *      at it some time and bring back some sanity, or
+ *      perhaps bust this file into smaller chunks.
+ */
+
+LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);
+LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);
+LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+int			pcibr_wrb_flush(devfs_handle_t);
+int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+void                    pcibr_rrb_flush(devfs_handle_t);
+
+LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
+void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
+
+LOCAL void              pcibr_clearwidint(bridge_t *);
+LOCAL void              pcibr_setwidint(xtalk_intr_t);
+LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);
+
+void                    pcibr_init(void);
+int                     pcibr_attach(devfs_handle_t);
+int			pcibr_detach(devfs_handle_t);
+int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);
+int                     pcibr_close(devfs_handle_t, int, int, cred_t *);
+int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
+int                     pcibr_unmap(devfs_handle_t, vhandl_t *);
+int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
+
+void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+
+LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);
+LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);
+LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);
+
+LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);
+LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
+LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
+LOCAL iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+
+pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
+void                    pcibr_piomap_free(pcibr_piomap_t);
+caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
+void                    pcibr_piomap_done(pcibr_piomap_t);
+caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
+void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
+
+LOCAL iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
+LOCAL bridge_ate_t      pcibr_flags_to_ate(unsigned);
+
+pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
+void                    pcibr_dmamap_free(pcibr_dmamap_t);
+LOCAL bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
+LOCAL iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
+iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
+alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_done(pcibr_dmamap_t);
+cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
+iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
+alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_drain(pcibr_dmamap_t);
+void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
+void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
+iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+static unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+void                    pcibr_intr_free(pcibr_intr_t);
+LOCAL void              pcibr_setpciint(xtalk_intr_t);
+int                     pcibr_intr_connect(pcibr_intr_t);
+void                    pcibr_intr_disconnect(pcibr_intr_t);
+
+devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
+void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+void                    pcibr_intr_func(intr_arg_t);
+
+void                    pcibr_provider_startup(devfs_handle_t);
+void                    pcibr_provider_shutdown(devfs_handle_t);
+
+int                     pcibr_reset(devfs_handle_t);
+pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
+int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
+pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
+int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
+
+LOCAL cfg_p             pcibr_config_addr(devfs_handle_t, unsigned);
+uint64_t                pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+LOCAL uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
+void                    pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+LOCAL void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+LOCAL pcibr_hints_t     pcibr_hints_get(devfs_handle_t, int);
+void                    pcibr_hints_fix_rrbs(devfs_handle_t);
+void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+void                    pcibr_hints_handsoff(devfs_handle_t);
+void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
+
+LOCAL int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
+
+#ifdef LATER
+LOCAL int	        pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t,
+                                               pcibr_slot_info_resp_t);
+LOCAL void       	pcibr_slot_func_info_return(pcibr_info_h, int,
+                                                    pcibr_slot_func_info_resp_t);
+#endif	/* LATER */
+
+LOCAL int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
+LOCAL int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_call_device_attach(devfs_handle_t,
+						      pciio_slot_t, int);
+LOCAL int		pcibr_slot_call_device_detach(devfs_handle_t,
+						      pciio_slot_t, int);
+
+LOCAL int               pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
+LOCAL int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
+#ifdef LATER
+LOCAL int		pcibr_slot_query(devfs_handle_t, pcibr_slot_info_req_t);
+#endif
+
+/* =====================================================================
+ *    RRB management
+ */
+
+#define LSBIT(word)		((word) &~ ((word)-1))
+
+#define PCIBR_RRB_SLOT_VIRTUAL	8
+
+LOCAL void
+do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
+{
+    bridgereg_t             status;
+
+    /* bridge_lock must be held;
+     * this RRB must be disabled.
+     */
+
+    /* wait until RRB has no outstanduing XIO packets. */
+    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
+	;				/* XXX- beats on bridge. bad idea? */
+    }
+
+    /* if the RRB has data, drain it. */
+    if (status & BRIDGE_RRB_VALID(rrb)) {
+	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
+
+	/* wait until RRB is no longer valid. */
+	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
+	    ;				/* XXX- beats on bridge. bad idea? */
+	}
+    }
+}
+
+LOCAL void
+do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
+{
+    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
+    bridgereg_t             rrbv;
+    int                     shft = 4 * (rrbn >> 1);
+    unsigned                ebit = BRIDGE_RRB_EN << shft;
+
+    rrbv = *rrbp;
+    if (rrbv & ebit)
+	*rrbp = rrbv & ~ebit;
+
+    do_pcibr_rrb_clear(bridge, rrbn);
+
+    if (rrbv & ebit)
+	*rrbp = rrbv;
+}
+
+/*
+ *    pcibr_rrb_count_valid: count how many RRBs are
+ *      marked valid for the specified PCI slot on this
+ *      bridge.
+ *
+ *      NOTE: The "slot" parameter for all pcibr_rrb
+ *      management routines must include the "virtual"
+ *      bit; when manageing both the normal and the
+ *      virtual channel, separate calls to these
+ *      routines must be made. To denote the virtual
+ *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
+ *      number.
+ *
+ *      IMPL NOTE: The obvious algorithm is to iterate
+ *      through the RRB fields, incrementing a count if
+ *      the RRB is valid and matches the slot. However,
+ *      it is much simpler to use an algorithm derived
+ *      from the "partitioned add" idea. First, XOR in a
+ *      pattern such that the fields that match this
+ *      slot come up "all ones" and all other fields
+ *      have zeros in the mismatching bits. Then AND
+ *      together the bits in the field, so we end up
+ *      with one bit turned on for each field that
+ *      matched. Now we need to count these bits. This
+ *      can be done either with a series of shift/add
+ *      instructions or by using "tmp % 15"; I expect
+ *      that the cascaded shift/add will be faster.
+ */
+
+LOCAL int
+do_pcibr_rrb_count_valid(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp ^= 0x11111111 * (7 - slot / 2);
+    tmp &= (0xCCCCCCCC & tmp) >> 2;
+    tmp &= (0x22222222 & tmp) >> 1;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_count_avail: count how many RRBs are
+ *      available to be allocated for the specified slot.
+ *
+ *      IMPL NOTE: similar to the above, except we are
+ *      just counting how many fields have the valid bit
+ *      turned off.
+ */
+LOCAL int
+do_pcibr_rrb_count_avail(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~tmp) >> 3;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_alloc: allocate some additional RRBs
+ *      for the specified slot. Returns -1 if there were
+ *      insufficient free RRBs to satisfy the request,
+ *      or 0 if the request was fulfilled.
+ *
+ *      Note that if a request can be partially filled,
+ *      it will be, even if we return failure.
+ *
+ *      IMPL NOTE: again we avoid iterating across all
+ *      the RRBs; instead, we form up a word containing
+ *      one bit for each free RRB, then peel the bits
+ *      off from the low end.
+ */
+LOCAL int
+do_pcibr_rrb_alloc(bridge_t *bridge,
+		   pciio_slot_t slot,
+		   int more)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, bit;
+
+    reg = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~reg) >> 3;
+    while (more-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+    return rv;
+}
+
+/*
+ *    do_pcibr_rrb_free: release some of the RRBs that
+ *      have been allocated for the specified
+ *      slot. Returns zero for success, or negative if
+ *      it was unable to free that many RRBs.
+ *
+ *      IMPL NOTE: We form up a bit for each RRB
+ *      allocated to the slot, aligned with the VALID
+ *      bitfield this time; then we peel bits off one at
+ *      a time, releasing the corresponding RRB.
+ */
+LOCAL int
+do_pcibr_rrb_free(bridge_t *bridge,
+		  pciio_slot_t slot,
+		  int less)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, clr, bit;
+    int                     i;
+
+    clr = 0;
+    reg = bridge->b_rrb_map[slot & 1].reg;
+
+    /* This needs to be done otherwise the rrb's on the virtual channel
+     * for this slot won't be freed !!
+     */
+    tmp = reg & 0xbbbbbbbb;
+
+    tmp ^= (0x11111111 * (7 - slot / 2));
+    tmp &= (0x33333333 & tmp) << 2;
+    tmp &= (0x44444444 & tmp) << 1;
+    while (less-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg &= ~bit;
+	clr |= bit;
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+
+    for (i = 0; i < 8; i++)
+	if (clr & (8 << (4 * i)))
+	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
+
+    return rv;
+}
+
+LOCAL void
+do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
+		       int slot,
+		       int more_rrbs)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     got;
+
+    for (got = 0; got < more_rrbs; ++got) {
+	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
+	    pcibr_soft->bs_rrb_res[slot & 7]--;
+	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
+	    pcibr_soft->bs_rrb_avail[slot & 1]--;
+	else
+	    break;
+	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
+	    break;
+#if PCIBR_RRB_DEBUG
+	printk( "do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
+		slot & 7, slot & 8 ? "v" : "");
+#endif
+	pcibr_soft->bs_rrb_valid[slot]++;
+    }
+#if PCIBR_RRB_DEBUG
+    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
+	    pcibr_soft->bs_rrb_avail[0],
+	    pcibr_soft->bs_rrb_avail[1]);
+    for (slot = 0; slot < 8; ++slot)
+	printk("\t%d+%d+%d",
+		0xFFF & pcibr_soft->bs_rrb_valid[slot],
+		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+		pcibr_soft->bs_rrb_res[slot]);
+	printk("\n");
+#endif
+}
+
+/*
+ * Device driver interface to flush the write buffers for a specified
+ * device hanging off the bridge.
+ */
+int
+pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    volatile bridgereg_t   *wrb_flush;
+
+    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
+    while (*wrb_flush);
+
+    return(0);
+}
+/*
+ * Device driver interface to request RRBs for a specified device
+ * hanging off a Bridge.  The driver requests the total number of
+ * RRBs it would like for the normal channel (vchan0) and for the
+ * "virtual channel" (vchan1).  The actual number allocated to each
+ * channel is returned.
+ *
+ * If we cannot allocate at least one RRB to a channel that needs
+ * at least one, return -1 (failure).  Otherwise, satisfy the request
+ * as best we can and return 0.
+ */
+int
+pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     desired_vchan0;
+    int                     desired_vchan1;
+    int                     orig_vchan0;
+    int                     orig_vchan1;
+    int                     delta_vchan0;
+    int                     delta_vchan1;
+    int                     final_vchan0;
+    int                     final_vchan1;
+    int                     avail_rrbs;
+    unsigned long           s;
+    int                     error;
+
+    /*
+     * TBD: temper request with admin info about RRB allocation,
+     * and according to demand from other devices on this Bridge.
+     *
+     * One way of doing this would be to allocate two RRBs
+     * for each device on the bus, before any drivers start
+     * asking for extras. This has the weakness that one
+     * driver might not give back an "extra" RRB until after
+     * another driver has already failed to get one that
+     * it wanted.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+
+    /* How many RRBs do we own? */
+    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
+    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+    /* How many RRBs do we want? */
+    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
+    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
+
+    /* How many RRBs are free? */
+    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	+ pcibr_soft->bs_rrb_res[pciio_slot];
+
+    /* Figure desired deltas */
+    delta_vchan0 = desired_vchan0 - orig_vchan0;
+    delta_vchan1 = desired_vchan1 - orig_vchan1;
+
+    /* Trim back deltas to something
+     * that we can actually meet, by
+     * decreasing the ending allocation
+     * for whichever channel wants
+     * more RRBs. If both want the same
+     * number, cut the second channel.
+     * NOTE: do not change the allocation for
+     * a channel that was passed as NULL.
+     */
+    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
+	if (count_vchan0 &&
+	    (!count_vchan1 ||
+	     ((orig_vchan0 + delta_vchan0) >
+	      (orig_vchan1 + delta_vchan1))))
+	    delta_vchan0--;
+	else
+	    delta_vchan1--;
+    }
+
+    /* Figure final RRB allocations
+     */
+    final_vchan0 = orig_vchan0 + delta_vchan0;
+    final_vchan1 = orig_vchan1 + delta_vchan1;
+
+    /* If either channel wants RRBs but our actions
+     * would leave it with none, declare an error,
+     * but DO NOT change any RRB allocations.
+     */
+    if ((desired_vchan0 && !final_vchan0) ||
+	(desired_vchan1 && !final_vchan1)) {
+
+	error = -1;
+
+    } else {
+
+	/* Commit the allocations: free, then alloc.
+	 */
+	if (delta_vchan0 < 0)
+	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
+	if (delta_vchan1 < 0)
+	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
+
+	if (delta_vchan0 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
+	if (delta_vchan1 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
+
+	/* Return final values to caller.
+	 */
+	if (count_vchan0)
+	    *count_vchan0 = final_vchan0;
+	if (count_vchan1)
+	    *count_vchan1 = final_vchan1;
+
+	/* prevent automatic changes to this slot's RRBs
+	 */
+	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
+
+	/* Track the actual allocations, release
+	 * any further reservations, and update the
+	 * number of available RRBs.
+	 */
+
+	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
+	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
+	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	    + pcibr_soft->bs_rrb_res[pciio_slot]
+	    - delta_vchan0
+	    - delta_vchan1;
+	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
+
+#if PCIBR_RRB_DEBUG
+	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
+		pciio_slot, final_vchan0, final_vchan1,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
+	    printk("\t%d+%d+%d",
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
+		    pcibr_soft->bs_rrb_res[pciio_slot]);
+	printk("\n");
+#endif
+
+	error = 0;
+    }
+
+    pcibr_unlock(pcibr_soft, s);
+    return error;
+}
+
+/*
+ * Device driver interface to check the current state
+ * of the RRB allocations.
+ *
+ *   pconn_vhdl is your PCI connection point (specifies which
+ *      PCI bus and which slot).
+ *
+ *   count_vchan0 points to where to return the number of RRBs
+ *      assigned to the primary DMA channel, used by all DMA
+ *      that does not explicitly ask for the alternate virtual
+ *      channel.
+ *
+ *   count_vchan1 points to where to return the number of RRBs
+ *      assigned to the secondary DMA channel, used when
+ *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
+ *
+ *   count_reserved points to where to return the number of RRBs
+ *      that have been automatically reserved for your device at
+ *      startup, but which have not been assigned to a
+ *      channel. RRBs must be assigned to a channel to be used;
+ *      this can be done either with an explicit pcibr_rrb_alloc
+ *      call, or automatically by the infrastructure when a DMA
+ *      translation is constructed. Any call to pcibr_rrb_alloc
+ *      will release any unassigned reserved RRBs back to the
+ *      free pool.
+ *
+ *   count_pool points to where to return the number of RRBs
+ *      that are currently unassigned and unreserved. This
+ *      number can (and will) change as other drivers make calls
+ *      to pcibr_rrb_alloc, or automatically allocate RRBs for
+ *      DMA beyond their initial reservation.
+ *
+ * NULL may be passed for any of the return value pointers
+ * the caller is not interested in.
+ *
+ * The return value is "0" if all went well, or "-1" if
+ * there is a problem. Additionally, if the wrong vertex
+ * is passed in, one of the subsidiary support functions
+ * could panic with a "bad pciio fingerprint."
+ */
+
+int
+pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1,
+		int *count_reserved,
+		int *count_pool)
+{
+    pciio_info_t            pciio_info;
+    pciio_slot_t            pciio_slot;
+    pcibr_soft_t            pcibr_soft;
+    unsigned long           s;
+    int                     error = -1;
+
+    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
+	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
+	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
+
+	s = pcibr_lock(pcibr_soft);
+
+	if (count_vchan0)
+	    *count_vchan0 =
+		pcibr_soft->bs_rrb_valid[pciio_slot];
+
+	if (count_vchan1)
+	    *count_vchan1 =
+		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+	if (count_reserved)
+	    *count_reserved =
+		pcibr_soft->bs_rrb_res[pciio_slot];
+
+	if (count_pool)
+	    *count_pool =
+		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
+
+	error = 0;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return error;
+}
+
+/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
+ * requested for each of the devies.  The evn_odd argument indicates whether
+ * allcoation for the odd or even rrbs is requested and next group of four pairse
+ * are the amount to assign to each device (they should sum to <= 8) and
+ * whether to set the viritual bit for that device (1 indictaes yes, 0 indicates no)
+ * the devices in order are either 0, 2, 4, 6 or 1, 3, 5, 7
+ * if even_odd is even we alloc even rrbs else we allocate odd rrbs
+ * returns 0 if no errors else returns -1
+ */
+
+int
+pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
+		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
+{
+    devfs_handle_t            pcibr_vhdl;
+    pcibr_soft_t            pcibr_soft = NULL;
+    bridge_t               *bridge = NULL;
+
+    uint32_t              rrb_setting = 0;
+    int                     rrb_shift = 7;
+    uint32_t              cur_rrb;
+    int                     dev_rrbs[4];
+    int                     virt[4];
+    int                     i, j;
+    unsigned long           s;
+
+    if (GRAPH_SUCCESS ==
+	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
+	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+	if (pcibr_soft)
+	    bridge = pcibr_soft->bs_base;
+	hwgraph_vertex_unref(pcibr_vhdl);
+    }
+    if (bridge == NULL)
+	bridge = (bridge_t *) xtalk_piotrans_addr
+	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
+
+    even_odd &= 1;
+
+    dev_rrbs[0] = dev_1_rrbs;
+    dev_rrbs[1] = dev_2_rrbs;
+    dev_rrbs[2] = dev_3_rrbs;
+    dev_rrbs[3] = dev_4_rrbs;
+
+    virt[0] = virt1;
+    virt[1] = virt2;
+    virt[2] = virt3;
+    virt[3] = virt4;
+
+    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
+	return -1;
+    }
+    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
+	return -1;
+    }
+    /* walk through rrbs */
+    for (i = 0; i < 4; i++) {
+	if (virt[i]) {
+	    cur_rrb = i | 0xc;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	    dev_rrbs[i] = dev_rrbs[i] - 1;
+	}
+	for (j = 0; j < dev_rrbs[i]; j++) {
+	    cur_rrb = i | 0x8;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	}
+    }
+
+    if (pcibr_soft)
+	s = pcibr_lock(pcibr_soft);
+
+    bridge->b_rrb_map[even_odd].reg = rrb_setting;
+
+    if (pcibr_soft) {
+
+	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
+
+	/* since we've "FIXED" the allocations
+	 * for these slots, we probably can dispense
+	 * with tracking avail/res/valid data, but
+	 * keeping it up to date helps debugging.
+	 */
+
+	pcibr_soft->bs_rrb_avail[even_odd] =
+	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
+
+	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return 0;
+}
+
+/*
+ *    pcibr_rrb_flush: chase down all the RRBs assigned
+ *      to the specified connection point, and flush
+ *      them.
+ */
+void
+pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned long           s;
+    reg_p                   rrbp;
+    unsigned                rrbm;
+    int                     i;
+    int                     rrbn;
+    unsigned                sval;
+    unsigned                mask;
+
+    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
+    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
+    rrbn = pciio_slot & 1;
+    rrbp = &bridge->b_rrb_map[rrbn].reg;
+
+    s = pcibr_lock(pcibr_soft);
+    rrbm = *rrbp;
+    for (i = 0; i < 8; ++i) {
+	if ((rrbm & mask) == sval)
+	    do_pcibr_rrb_flush(bridge, rrbn);
+	rrbm >>= 4;
+	rrbn += 2;
+    }
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Device(x) register management
+ */
+
+/* pcibr_try_set_device: attempt to modify Device(x)
+ * for the specified slot on the specified bridge
+ * as requested in flags, limited to the specified
+ * bits. Returns which BRIDGE bits were in conflict,
+ * or ZERO if everything went OK.
+ *
+ * Caller MUST hold pcibr_lock when calling this function.
+ */
+LOCAL int
+pcibr_try_set_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     unsigned flags,
+		     bridgereg_t mask)
+{
+    bridge_t               *bridge;
+    pcibr_soft_slot_t       slotp;
+    bridgereg_t             old;
+    bridgereg_t             new;
+    bridgereg_t             chg;
+    bridgereg_t             bad;
+    bridgereg_t             badpmu;
+    bridgereg_t             badd32;
+    bridgereg_t             badd64;
+    bridgereg_t             fix;
+    unsigned long           s;
+    bridgereg_t             xmask;
+
+    xmask = mask;
+    if (pcibr_soft->bs_xbridge) {
+    	if (mask == BRIDGE_DEV_PMU_BITS)
+		xmask = XBRIDGE_DEV_PMU_BITS;
+	if (mask == BRIDGE_DEV_D64_BITS)
+		xmask = XBRIDGE_DEV_D64_BITS;
+    }
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    bridge = pcibr_soft->bs_base;
+
+    old = slotp->bss_device;
+
+    /* figure out what the desired
+     * Device(x) bits are based on
+     * the flags specified.
+     */
+
+    new = old;
+
+    /* Currently, we inherit anything that
+     * the new caller has not specified in
+     * one way or another, unless we take
+     * action here to not inherit.
+     *
+     * This is needed for the "swap" stuff,
+     * since it could have been set via
+     * pcibr_endian_set -- altho note that
+     * any explicit PCIBR_BYTE_STREAM or
+     * PCIBR_WORD_VALUES will freely override
+     * the effect of that call (and vice
+     * versa, no protection either way).
+     *
+     * I want to get rid of pcibr_endian_set
+     * in favor of tracking DMA endianness
+     * using the flags specified when DMA
+     * channels are created.
+     */
+
+#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
+#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
+
+    /* Do not use Barrier, Write Gather,
+     * or Prefetch unless asked.
+     * Leave everything else as it
+     * was from the last time.
+     */
+    new = new
+	& ~BRIDGE_DEV_BARRIER
+	& ~BRIDGE_DEV_WRGA_BITS
+	& ~BRIDGE_DEV_PREF
+	;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {
+	new = (new
+            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
+            | BRIDGE_DEV_PREF;          /* prefetch on */
+
+    }
+    if (flags & PCIIO_DMA_CMD) {
+        new = ((new
+            & ~BRIDGE_DEV_PREF)         /* prefetch off */
+            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
+            | BRIDGE_DEV_BARRIER;       /* barrier on */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIIO_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_BYTE_STREAM)
+	new |= (pcibr_soft->bs_xbridge) ? 
+			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
+    if (flags & PCIIO_WORD_VALUES)
+	new &= (pcibr_soft->bs_xbridge) ? 
+			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	new |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	new &= ~BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	new |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	new &= ~BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	new |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	new &= ~BRIDGE_DEV_DEV_SIZE;
+
+    chg = old ^ new;				/* what are we changing, */
+    chg &= xmask;				/* of the interesting bits */
+
+    if (chg) {
+
+	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
+	if (pcibr_soft->bs_xbridge) {
+		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
+	} else {
+		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
+	}
+	bad = badpmu | badd32 | badd64;
+
+	if (bad) {
+
+	    /* some conflicts can be resolved by
+	     * forcing the bit on. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit off,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
+                             BRIDGE_DEV_BARRIER)) ){
+		bad &= ~fix;
+		/* don't change these bits if
+		 * they are already set in "old"
+		 */
+		chg &= ~(fix & old);
+	    }
+	    /* some conflicts can be resolved by
+	     * forcing the bit off. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit on,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
+			     BRIDGE_DEV_PREF)) ) {
+		bad &= ~fix;
+		/* don't change these bits if
+		 * we wanted to turn them on.
+		 */
+		chg &= ~(fix & new);
+	    }
+	    /* conflicts in other bits mean
+	     * we can not establish this DMA
+	     * channel while the other(s) are
+	     * still present.
+	     */
+	    if (bad) {
+		pcibr_unlock(pcibr_soft, s);
+#if (DEBUG && PCIBR_DEV_DEBUG)
+		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
+#endif
+		return bad;
+	    }
+	}
+    }
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr++;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr++;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr++;
+
+    /* the value we want to write is the
+     * original value, with the bits for
+     * our selected changes flipped, and
+     * with any disabled features turned off.
+     */
+    new = old ^ chg;			/* only change what we want to change */
+
+    if (slotp->bss_device == new) {
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
+#endif
+
+    return 0;
+}
+
+void
+pcibr_release_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     bridgereg_t mask)
+{
+    pcibr_soft_slot_t       slotp;
+    unsigned long           s;
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr--;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr--;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr--;
+
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * flush write gather buffer for slot
+ */
+LOCAL void
+pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
+              pciio_slot_t slot)
+{
+    bridge_t               *bridge;
+    unsigned long          s;
+    volatile uint32_t     wrf;
+    s = pcibr_lock(pcibr_soft);
+    bridge = pcibr_soft->bs_base;
+    wrf = bridge->b_wr_req_buf[slot].reg;
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Bridge (pcibr) "Device Driver" entry points
+ */
+
+/*
+ * pcibr_probe_slot: read a config space word
+ * while trapping any errors; reutrn zero if
+ * all went OK, or nonzero if there was an error.
+ * The value read, if any, is passed back
+ * through the valp parameter.
+ */
+LOCAL int
+pcibr_probe_slot(bridge_t *bridge,
+		 cfg_p cfg,
+		 unsigned *valp)
+{
+    int                     rv;
+    bridgereg_t             old_enable, new_enable;
+    int badaddr_val(volatile void *, int, volatile void *);
+
+
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+
+    bridge->b_int_enable = new_enable;
+
+	/*
+	 * The xbridge doesn't clear b_err_int_view unless
+	 * multi-err is cleared...
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+	    }
+
+    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
+	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
+	(void) bridge->b_wid_tflush;	/* flushbus */
+    }
+    rv = badaddr_val((void *) cfg, 4, valp);
+
+	/*
+	 * The xbridge doesn't set master timeout in b_int_status
+	 * here.  Fortunately it's in error_interrupt_view.
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+		rv = 1;		/* unoccupied slot */
+	    }
+
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    return rv;
+}
+
+/*
+ *    pcibr_init: called once during system startup or
+ *      when a loadable driver is loaded.
+ *
+ *      The driver_register function should normally
+ *      be in _reg, not _init.  But the pcibr driver is
+ *      required by devinit before the _reg routines
+ *      are called, so this is an exception.
+ */
+void
+pcibr_init(void)
+{
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_init\n");
+#endif
+
+    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
+			    XBRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
+			    BRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+}
+
+/*
+ * open/close mmap/munmap interface would be used by processes
+ * that plan to map the PCI bridge, and muck around with the
+ * registers. This is dangerous to do, and will be allowed
+ * to a select brand of programs. Typically these are
+ * diagnostics programs, or some user level commands we may
+ * write to do some weird things.
+ * To start with expect them to have root priveleges.
+ * We will ask for more later.
+ */
+/* ARGSUSED */
+int
+pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+    int                     error;
+    devfs_handle_t            vhdl = dev_to_vhdl(dev);
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    ASSERT(pcibr_soft);
+    len = ctob(btoc(len));		/* Make len page aligned */
+    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
+
+    /*
+     * If the offset being mapped corresponds to the flash prom
+     * base, and if the mapping succeeds, and if the user
+     * has requested the protections to be WRITE, enable the
+     * flash prom to be written.
+     *
+     * XXX- deprecate this in favor of using the
+     * real flash driver ...
+     */
+    if (!error &&
+	((off == BRIDGE_EXTERNAL_FLASH) ||
+	 (len > BRIDGE_EXTERNAL_FLASH))) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return error;
+}
+
+/*ARGSUSED */
+int
+pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    /*
+     * If flashprom write was enabled, disable it, as
+     * this is the last unmap.
+     */
+    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return 0;
+}
+
+/* This is special case code used by grio. There are plans to make
+ * this a bit more general in the future, but till then this should
+ * be sufficient.
+ */
+pciio_slot_t
+pcibr_device_slot_get(devfs_handle_t dev_vhdl)
+{
+    char                    devname[MAXDEVNAME];
+    devfs_handle_t            tdev;
+    pciio_info_t            pciio_info;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+
+    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
+
+    /* run back along the canonical path
+     * until we find a PCI connection point.
+     */
+    tdev = hwgraph_connectpt_get(dev_vhdl);
+    while (tdev != GRAPH_VERTEX_NONE) {
+	pciio_info = pciio_info_chk(tdev);
+	if (pciio_info) {
+	    slot = pciio_info_slot_get(pciio_info);
+	    break;
+	}
+	hwgraph_vertex_unref(tdev);
+	tdev = hwgraph_connectpt_get(tdev);
+    }
+    hwgraph_vertex_unref(tdev);
+
+    return slot;
+}
+
+/*==========================================================================
+ *	BRIDGE PCI SLOT RELATED IOCTLs
+ */
+char *pci_space_name[] = {"NONE", 
+			  "ROM",
+			  "IO",
+			  "",
+			  "MEM",
+			  "MEM32",
+			  "MEM64",
+			  "CFG",
+			  "WIN0",
+			  "WIN1",
+			  "WIN2",
+			  "WIN3",
+			  "WIN4",
+			  "WIN5",
+			  "",
+			  "BAD"};
+
+
+#ifdef LATER
+
+void
+pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
+                            int func,
+                            pcibr_slot_func_info_resp_t funcp)
+{
+    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
+    int                          win;
+
+    funcp->resp_f_status = 0;
+
+    if (!pcibr_info) {
+        return;
+    }
+
+    funcp->resp_f_status |= FUNC_IS_VALID;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
+#else
+    sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex);
+#endif
+
+    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
+        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
+    }
+
+    funcp->resp_f_bus = pcibr_info->f_bus;
+    funcp->resp_f_slot = pcibr_info->f_slot;
+    funcp->resp_f_func = pcibr_info->f_func;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
+#else
+    sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master);
+#endif
+    funcp->resp_f_pops = pcibr_info->f_pops;
+    funcp->resp_f_efunc = pcibr_info->f_efunc;
+    funcp->resp_f_einfo = pcibr_info->f_einfo;
+
+    funcp->resp_f_vendor = pcibr_info->f_vendor;
+    funcp->resp_f_device = pcibr_info->f_device;
+
+    for(win = 0 ; win < 6 ; win++) {
+        funcp->resp_f_window[win].resp_w_base =
+                                  pcibr_info->f_window[win].w_base;
+        funcp->resp_f_window[win].resp_w_size =
+                                  pcibr_info->f_window[win].w_size;
+        sprintf(funcp->resp_f_window[win].resp_w_space,
+                "%s",
+                pci_space_name[pcibr_info->f_window[win].w_space]);
+    }
+
+    funcp->resp_f_rbase = pcibr_info->f_rbase;
+    funcp->resp_f_rsize = pcibr_info->f_rsize;
+
+    for (win = 0 ; win < 4; win++) {
+        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
+    }
+
+    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
+
+}
+
+int
+pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
+                       pciio_slot_t             slot,
+                       pcibr_slot_info_resp_t   respp)
+{
+    pcibr_soft_slot_t            pss;
+    int                          func;
+    bridge_t                    *bridge = pcibr_soft->bs_base;
+    reg_p                        b_respp;
+    pcibr_slot_info_resp_t       slotp;
+    pcibr_slot_func_info_resp_t  funcp;
+
+    slotp = snia_kmem_zalloc(sizeof(*slotp), KM_SLEEP);
+    if (slotp == NULL) {
+        return(ENOMEM);
+    }
+
+    pss = &pcibr_soft->bs_slot[slot];
+    
+    printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot);
+
+    slotp->resp_has_host = pss->has_host;
+    slotp->resp_host_slot = pss->host_slot;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
+#else
+    sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn);
+#endif
+    slotp->resp_slot_status = pss->slot_status;
+    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (is_sys_critical_vertex(pss->slot_conn)) {
+        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
+    }
+
+    slotp->resp_bss_ninfo = pss->bss_ninfo;
+
+    for (func = 0; func < pss->bss_ninfo; func++) {
+        funcp = &(slotp->resp_func[func]);
+        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
+    }
+
+    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
+            pci_space_name[pss->bss_devio.bssd_space]);
+    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
+    slotp->resp_bss_device = pss->bss_device;
+
+    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
+    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
+    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
+
+    slotp->resp_bss_d64_base = pss->bss_d64_base;
+    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
+    slotp->resp_bss_d32_base = pss->bss_d32_base;
+    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
+
+    slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active);
+
+    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
+    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
+
+    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
+    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
+                                                      PCIBR_RRB_SLOT_VIRTUAL];
+    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
+
+    if (slot & 1) {
+        b_respp = &bridge->b_odd_resp;
+    } else {
+        b_respp = &bridge->b_even_resp;
+    }
+
+    slotp->resp_b_resp = *b_respp;
+
+    slotp->resp_b_int_device = bridge->b_int_device;
+    slotp->resp_b_int_enable = bridge->b_int_enable;
+    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
+
+    if (COPYOUT(slotp, respp, sizeof(*respp))) {
+        return(EFAULT);
+    }
+
+    snia_kmem_free(slotp, sizeof(*slotp));
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_query
+ *	Return information about the PCI slot maintained by the infrastructure.
+ *	Information is requested in the request structure.
+ *
+ *      Information returned in the response structure:
+ *		Slot hwgraph name
+ *		Vendor/Device info
+ *		Base register info
+ *		Interrupt mapping from device pins to the bridge pins
+ *		Devio register
+ *		Software RRB info
+ *		RRB register info
+ *		Host/Gues info
+ *		PCI Bus #,slot #, function #
+ *		Slot provider hwgraph name
+ *		Provider Functions
+ *		Error handler
+ *		DMA mapping usage counters
+ *		DMA direct translation info
+ *		External SSRAM workaround info
+ */
+int
+pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t            slot = reqp->req_slot;
+    pciio_slot_t            tmp_slot;
+    pcibr_slot_info_resp_t  respp = (pcibr_slot_info_resp_t) reqp->req_respp;
+    int                     size = reqp->req_size;
+    int                     error;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(EINVAL);
+    }
+
+    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
+    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
+        return(EINVAL);
+    }
+
+    /* Return information for the requested PCI slot */
+    if (slot != PCIIO_SLOT_NONE) {
+        if (size < sizeof(*respp)) {
+            return(EINVAL);
+        }
+
+        /* Acquire read access to the slot */
+        mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
+
+        /* Release the slot lock */
+        mrunlock(pcibr_soft->bs_slot[slot].slot_lock);
+
+        return(error);
+    }
+
+    /* Return information for all the slots */
+    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
+
+        if (size < sizeof(*respp)) {
+            return(EINVAL);
+        }
+
+        /* Acquire read access to the slot */
+        mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
+
+        /* Release the slot lock */
+        mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock);
+
+        if (error) {
+            return(error);
+        }
+
+        ++respp;
+        size -= sizeof(*respp);
+    }
+
+    return(error);
+}
+#endif	/* LATER */
+
+
+/*ARGSUSED */
+int
+pcibr_ioctl(devfs_handle_t dev,
+	    int cmd,
+	    void *arg,
+	    int flag,
+	    struct cred *cr,
+	    int *rvalp)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
+#ifdef LATER
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+#endif
+    int                     error = 0;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    switch (cmd) {
+#ifdef LATER
+    case GIOCSETBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
+	    break;
+	}
+
+    case GIOCRELEASEBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
+	    break;
+	}
+
+    case PCIBR_SLOT_POWERUP:
+	{
+	    pciio_slot_t	slot;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+	    slot = (pciio_slot_t)(uint64_t)arg;
+	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
+	    break;
+	}
+    case PCIBR_SLOT_SHUTDOWN:
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+	    slot = (pciio_slot_t)(uint64_t)arg;
+	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
+	    break;
+	}
+    case PCIBR_SLOT_QUERY:
+	{
+	    struct pcibr_slot_info_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+            error = pcibr_slot_query(pcibr_vhdl, &req);
+	    break;
+	}
+#endif	/* LATER */
+    default:
+	break;
+
+    }
+
+    return error;
+}
+
+void
+pcibr_freeblock_sub(iopaddr_t *free_basep,
+		    iopaddr_t *free_lastp,
+		    iopaddr_t base,
+		    size_t size)
+{
+    iopaddr_t               free_base = *free_basep;
+    iopaddr_t               free_last = *free_lastp;
+    iopaddr_t               last = base + size - 1;
+
+    if ((last < free_base) || (base > free_last));	/* free block outside arena */
+
+    else if ((base <= free_base) && (last >= free_last))
+	/* free block contains entire arena */
+	*free_basep = *free_lastp = 0;
+
+    else if (base <= free_base)
+	/* free block is head of arena */
+	*free_basep = last + 1;
+
+    else if (last >= free_last)
+	/* free block is tail of arena */
+	*free_lastp = base - 1;
+
+    /*
+     * We are left with two regions: the free area
+     * in the arena "below" the block, and the free
+     * area in the arena "above" the block. Keep
+     * the one that is bigger.
+     */
+
+    else if ((base - free_base) > (free_last - last))
+	*free_lastp = base - 1;		/* keep lower chunk */
+    else
+	*free_basep = last + 1;		/* keep upper chunk */
+}
+
+/* Convert from ssram_bits in control register to number of SSRAM entries */
+#define ATE_NUM_ENTRIES(n) _ate_info[n]
+
+/* Possible choices for number of ATE entries in Bridge's SSRAM */
+LOCAL int               _ate_info[] =
+{
+    0,					/* 0 entries */
+    8 * 1024,				/* 8K entries */
+    16 * 1024,				/* 16K entries */
+    64 * 1024				/* 64K entries */
+};
+
+#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
+#define ATE_PROBE_VALUE 0x0123456789abcdefULL
+
+/*
+ * Determine the size of this bridge's external mapping SSRAM, and set
+ * the control register appropriately to reflect this size, and initialize
+ * the external SSRAM.
+ */
+LOCAL int
+pcibr_init_ext_ate_ram(bridge_t *bridge)
+{
+    int                     largest_working_size = 0;
+    int                     num_entries, entry;
+    int                     i, j;
+    bridgereg_t             old_enable, new_enable;
+    int                     s;
+
+    /* Probe SSRAM to determine its size. */
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+    bridge->b_int_enable = new_enable;
+
+    for (i = 1; i < ATE_NUM_SIZES; i++) {
+	/* Try writing a value */
+	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+
+	/* Guard against wrap */
+	for (j = 1; j < i; j++)
+	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
+
+	/* See if value was written */
+	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+	    largest_working_size = i;
+    }
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * ensure that we write and read without any interruption.
+     * The read following the write is required for the Bridge war
+     */
+
+    s = splhi();
+    bridge->b_wid_control = (bridge->b_wid_control
+	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+    bridge->b_wid_control;		/* inval addr bug war */
+    splx(s);
+
+    num_entries = ATE_NUM_ENTRIES(largest_working_size);
+
+#if PCIBR_ATE_DEBUG
+    if (num_entries)
+	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
+    else
+	printk("bridge at 0x%x: no externa9422l ATE RAM found\n", bridge);
+#endif
+
+    /* Initialize external mapping entries */
+    for (entry = 0; entry < num_entries; entry++)
+	bridge->b_ext_ate_ram[entry] = 0;
+
+    return (num_entries);
+}
+
+/*
+ * Allocate "count" contiguous Bridge Address Translation Entries
+ * on the specified bridge to be used for PCI to XTALK mappings.
+ * Indices in rm map range from 1..num_entries.  Indicies returned
+ * to caller range from 0..num_entries-1.
+ *
+ * Return the start index on success, -1 on failure.
+ */
+LOCAL int
+pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
+{
+    int                     index = 0;
+
+    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
+/* printk("Colin: pcibr_ate_alloc - index %d count %d \n", index, count); */
+
+    if (!index && pcibr_soft->bs_ext_ate_map)
+	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
+
+    /* rmalloc manages resources in the 1..n
+     * range, with 0 being failure.
+     * pcibr_ate_alloc manages resources
+     * in the 0..n-1 range, with -1 being failure.
+     */
+    return index - 1;
+}
+
+LOCAL void
+pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
+/* Who says there's no such thing as a free meal? :-) */
+{
+    /* note the "+1" since rmalloc handles 1..n but
+     * we start counting ATEs at zero.
+     */
+/* printk("Colin: pcibr_ate_free - index %d count %d\n", index, count); */
+
+    rmfree((index < pcibr_soft->bs_int_ate_size)
+	   ? pcibr_soft->bs_int_ate_map
+	   : pcibr_soft->bs_ext_ate_map,
+	   count, index + 1);
+}
+
+LOCAL pcibr_info_t
+pcibr_info_get(devfs_handle_t vhdl)
+{
+    return (pcibr_info_t) pciio_info_get(vhdl);
+}
+
+pcibr_info_t
+pcibr_device_info_new(
+			 pcibr_soft_t pcibr_soft,
+			 pciio_slot_t slot,
+			 pciio_function_t rfunc,
+			 pciio_vendor_id_t vendor,
+			 pciio_device_id_t device)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_function_t        func;
+    int                     ibit;
+
+    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
+
+    NEW(pcibr_info);
+    pciio_device_info_new(&pcibr_info->f_c,
+			  pcibr_soft->bs_vhdl,
+			  slot, rfunc,
+			  vendor, device);
+
+    if (slot != PCIIO_SLOT_NONE) {
+
+	/*
+	 * Currently favored mapping from PCI
+	 * slot number and INTA/B/C/D to Bridge
+	 * PCI Interrupt Bit Number:
+	 *
+	 *     SLOT     A B C D
+	 *      0       0 4 0 4
+	 *      1       1 5 1 5
+	 *      2       2 6 2 6
+	 *      3       3 7 3 7
+	 *      4       4 0 4 0
+	 *      5       5 1 5 1
+	 *      6       6 2 6 2
+	 *      7       7 3 7 3
+	 *
+	 * XXX- allow pcibr_hints to override default
+	 * XXX- allow ADMIN to override pcibr_hints
+	 */
+	for (ibit = 0; ibit < 4; ++ibit)
+	    pcibr_info->f_ibit[ibit] =
+		(slot + 4 * ibit) & 7;
+
+	/*
+	 * Record the info in the sparse func info space.
+	 */
+	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
+	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
+    }
+    return pcibr_info;
+}
+
+void
+pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pcibr_info_t	pcibr_info;
+    pciio_function_t	func;
+    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
+    int			nfunc = slotp->bss_ninfo;
+
+
+    for (func = 0; func < nfunc; func++) {
+	pcibr_info = slotp->bss_infos[func];
+
+	if (!pcibr_info) 
+	    continue;
+
+	slotp->bss_infos[func] = 0;
+	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
+	pciio_device_info_free(&pcibr_info->f_c);
+	DEL(pcibr_info);
+    }
+
+    /* Clear the DEVIO(x) for this slot */
+    slotp->bss_devio.bssd_space = PCIIO_SPACE_NONE;
+    slotp->bss_devio.bssd_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_device  = 0;
+
+    
+    /* Reset the mapping usage counters */
+    slotp->bss_pmu_uctr = 0;
+    slotp->bss_d32_uctr = 0;
+    slotp->bss_d64_uctr = 0;
+
+    /* Clear the Direct translation info */
+    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
+    slotp->bss_d64_flags = 0;
+    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_d32_flags = 0;
+
+    /* Clear out shadow info necessary for the external SSRAM workaround */
+    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
+    slotp->bss_cmd_pointer = 0;
+    slotp->bss_cmd_shadow = 0;
+
+}
+
+/* 
+ * PCI_ADDR_SPACE_LIMITS_LOAD
+ *	Gets the current values of 
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
+    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
+    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
+    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
+    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
+    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
+    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
+    printf("+++++++++++++++++++++++\n"			\
+	   "IO base 0x%x last 0x%x\n"			\
+	   "SWIN base 0x%x last 0x%x\n"			\
+	   "MEM base 0x%x last 0x%x\n"			\
+	   "+++++++++++++++++++++++\n",			\
+	   pcibr_soft->bs_spinfo.pci_io_base,		\
+	   pcibr_soft->bs_spinfo.pci_io_last,		\
+	   pcibr_soft->bs_spinfo.pci_swin_base,		\
+	   pcibr_soft->bs_spinfo.pci_swin_last,		\
+	   pcibr_soft->bs_spinfo.pci_mem_base,		\
+	   pcibr_soft->bs_spinfo.pci_mem_last);
+
+/*
+ * pcibr_slot_info_init
+ *	Probe for this slot and see if it is populated.
+ *	If it is populated initialize the generic PCI infrastructural
+ * 	information associated with this particular PCI device.
+ */
+int
+pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
+		     pciio_slot_t 	slot)
+{
+    pcibr_soft_t	    pcibr_soft;
+    pcibr_info_h	    pcibr_infoh;
+    pcibr_info_t	    pcibr_info;
+    bridge_t		   *bridge;
+    cfg_p                   cfgw;
+    unsigned                idword;
+    unsigned                pfail;
+    unsigned                idwords[8];
+    pciio_vendor_id_t       vendor;
+    pciio_device_id_t       device;
+    unsigned                htype;
+    cfg_p                   wptr;
+    int                     win;
+    pciio_space_t           space;
+    iopaddr_t		    pci_io_fb,	pci_io_fl;
+    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
+    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
+    int			    nfunc;
+    pciio_function_t	    rfunc;
+    int			    func;
+    devfs_handle_t	    conn_vhdl;
+    pcibr_soft_slot_t	    slotp;
+    
+    /* Get the basic software information required to proceed */
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft)
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+    if (!PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
+     * is done by the host slot then we are done.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);    
+    }
+
+    /* Check for a slot with any system critical functions */
+    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    /* Load the current values of allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+    
+    /* Try to read the device-id/vendor-id from the config space */
+    cfgw = bridge->b_type0_cfg_dev[slot].l;
+
+    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
+	return(ENODEV);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+    slotp->slot_status |= SLOT_POWER_UP;
+
+    vendor = 0xFFFF & idword;
+    /* If the vendor id is not valid then the slot is not populated
+     * and we are done.
+     */
+    if (vendor == 0xFFFF) 
+	return(ENODEV);			
+    
+    device = 0xFFFF & (idword >> 16);
+    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+
+    nfunc = 1;
+    rfunc = PCIIO_FUNC_NONE;
+    pfail = 0;
+
+    /* NOTE: if a card claims to be multifunction
+     * but only responds to config space 0, treat
+     * it as a unifunction card.
+     */
+
+    if (htype & 0x80) {		/* MULTIFUNCTION */
+	for (func = 1; func < 8; ++func) {
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    vendor = 0xFFFF & idwords[func];
+	    if (vendor == 0xFFFF) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    nfunc = func + 1;
+	    rfunc = 0;
+	}
+	cfgw = bridge->b_type0_cfg_dev[slot].l;
+    }
+    NEWA(pcibr_infoh, nfunc);
+    
+    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
+    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+    for (func = 0; func < nfunc; ++func) {
+	unsigned                cmd_reg;
+	
+	if (func) {
+	    if (pfail & (1 << func))
+		continue;
+	    
+	    idword = idwords[func];
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    
+	    device = 0xFFFF & (idword >> 16);
+	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+	    rfunc = func;
+	}
+	htype &= 0x7f;
+	if (htype != 0x00) {
+	    printk(KERN_WARNING  "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
+		    pcibr_soft->bs_name, slot, func, htype);
+	    continue;
+	}
+#if DEBUG && ATTACH_DEBUG
+	printk(KERN_NOTICE   
+		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
+		pcibr_soft->bs_name, slot, func, vendor, device);
+#endif	
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, rfunc, vendor, device);
+	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
+	if (func == 0)
+	    slotp->slot_conn = conn_vhdl;
+
+#ifdef LITTLE_ENDIAN
+	cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4];
+#else
+	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
+#endif
+	
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) {
+	    iopaddr_t               base, mask, code;
+	    size_t                  size;
+
+	    /*
+	     * GET THE BASE & SIZE OF THIS WINDOW:
+	     *
+	     * The low two or four bits of the BASE register
+	     * determines which address space we are in; the
+	     * rest is a base address. BASE registers
+	     * determine windows that are power-of-two sized
+	     * and naturally aligned, so we can get the size
+	     * of a window by writing all-ones to the
+	     * register, reading it back, and seeing which
+	     * bits are used for decode; the least
+	     * significant nonzero bit is also the size of
+	     * the window.
+	     *
+	     * WARNING: someone may already have allocated
+	     * some PCI space to this window, and in fact
+	     * PIO may be in process at this very moment
+	     * from another processor (or even from this
+	     * one, if we get interrupted)! So, if the BASE
+	     * already has a nonzero address, be generous
+	     * and use the LSBit of that address as the
+	     * size; this could overstate the window size.
+	     * Usually, when one card is set up, all are set
+	     * up; so, since we don't bitch about
+	     * overlapping windows, we are ok.
+	     *
+	     * UNFORTUNATELY, some cards do not clear their
+	     * BASE registers on reset. I have two heuristics
+	     * that can detect such cards: first, if the
+	     * decode enable is turned off for the space
+	     * that the window uses, we can disregard the
+	     * initial value. second, if the address is
+	     * outside the range that we use, we can disregard
+	     * it as well.
+	     *
+	     * This is looking very PCI generic. Except for
+	     * knowing how many slots and where their config
+	     * spaces are, this window loop and the next one
+	     * could probably be shared with other PCI host
+	     * adapters. It would be interesting to see if
+	     * this could be pushed up into pciio, when we
+	     * start supporting more PCI providers.
+	     */
+#ifdef LITTLE_ENDIAN
+	    base = wptr[((win*4)^4)/4];
+#else
+	    base = wptr[win];
+#endif
+
+	    if (base & PCI_BA_IO_SPACE) {
+		/* BASE is in I/O space. */
+		space = PCIIO_SPACE_IO;
+		mask = -4;
+		code = base & 3;
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		}
+	    } else {
+		/* BASE is in MEM space. */
+		space = PCIIO_SPACE_MEM;
+		mask = -16;
+		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		} else if (base & 0xC0000000) {
+		    base = 0;	/* outside permissable range */
+		} else if ((code == PCI_BA_MEM_64BIT) &&
+#ifdef LITTLE_ENDIAN
+			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
+#else 
+			   (wptr[win + 1] != 0)) {
+#endif /* LITTLE_ENDIAN */
+		    base = 0;	/* outside permissable range */
+		}
+	    }
+
+	    if (base != 0) {	/* estimate size */
+		size = base & -base;
+	    } else {		/* calculate size */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
+		size = wptr[((win*4)^4)/4];	/* get stored bits */
+#else 
+		wptr[win] = ~0;	/* turn on all bits */
+		size = wptr[win];	/* get stored bits */
+#endif /* LITTLE_ENDIAN */
+		size &= mask;	/* keep addr */
+		size &= -size;	/* keep lsbit */
+		if (size == 0)
+		    continue;
+	    }	
+
+	    pcibr_info->f_window[win].w_space = space;
+	    pcibr_info->f_window[win].w_base = base;
+	    pcibr_info->f_window[win].w_size = size;
+
+	    /*
+	     * If this window already has PCI space
+	     * allocated for it, "subtract" that space from
+	     * our running freeblocks. Don't worry about
+	     * overlaps in existing allocated windows; we
+	     * may be overstating their sizes anyway.
+	     */
+
+	    if (base && size) {
+		if (space == PCIIO_SPACE_IO) {
+		    pcibr_freeblock_sub(&pci_io_fb,
+					&pci_io_fl,
+					base, size);
+		} else {
+		    pcibr_freeblock_sub(&pci_lo_fb,
+					&pci_lo_fl,
+					base, size);
+		    pcibr_freeblock_sub(&pci_hi_fb,
+					&pci_hi_fl,
+					base, size);
+		}	
+	    }
+#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
+	    /*
+	     * IOC3 BASE_ADDR* BUG WORKAROUND
+	     *
+	     
+	     * If we write to BASE1 on the IOC3, the
+	     * data in BASE0 is replaced. The
+	     * original workaround was to remember
+	     * the value of BASE0 and restore it
+	     * when we ran off the end of the BASE
+	     * registers; however, a later
+	     * workaround was added (I think it was
+	     * rev 1.44) to avoid setting up
+	     * anything but BASE0, with the comment
+	     * that writing all ones to BASE1 set
+	     * the enable-parity-error test feature
+	     * in IOC3's SCR bit 14.
+	     *
+	     * So, unless we defer doing any PCI
+	     * space allocation until drivers
+	     * attach, and set up a way for drivers
+	     * (the IOC3 in paricular) to tell us
+	     * generically to keep our hands off
+	     * BASE registers, we gotta "know" about
+	     * the IOC3 here.
+	     *
+	     * Too bad the PCI folks didn't reserve the
+	     * all-zero value for 'no BASE here' (it is a
+	     * valid code for an uninitialized BASE in
+	     * 32-bit PCI memory space).
+	     */
+	    
+	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
+		(device == IOC3_DEVICE_ID_NUM))
+		break;
+#endif
+	    if (code == PCI_BA_MEM_64BIT) {
+		win++;		/* skip upper half */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
+#else 
+		wptr[win] = 0;	/* which must be zero */
+#endif /* LITTLE_ENDIAN */
+	    }
+	}				/* next win */
+    }				/* next func */
+
+    /* Store back the values for allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}					
+
+/*
+ * pcibr_slot_info_free
+ *	Remove all the PCI infrastructural information associated
+ * 	with a particular PCI device.
+ */
+int
+pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
+                     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    int			nfunc;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+
+    pcibr_device_info_free(pcibr_vhdl, slot);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    DELA(pcibr_infoh,nfunc);
+    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
+
+    return(0);
+}
+
+int as_debug = 0;
+/*
+ * pcibr_slot_addr_space_init
+ *	Reserve chunks of PCI address space as required by 
+ * 	the base registers in the card.
+ */
+int
+pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    iopaddr_t		pci_io_fb, pci_io_fl;
+    iopaddr_t		pci_lo_fb, pci_lo_fl;
+    iopaddr_t		pci_hi_fb, pci_hi_fl;
+    size_t              align;
+    iopaddr_t           mask;
+    int		    	nbars;
+    int		       	nfunc;
+    int			func;
+    int			win;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Get the current values for the allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+
+    if (as_debug)
+#ifdef LATER
+    PCI_ADDR_SPACE_LIMITS_PRINT();
+#endif
+    /* allocate address space,
+     * for windows that have not been
+     * previously assigned.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);
+    }
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    if (nfunc < 1)
+	return(EINVAL);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    if (!pcibr_infoh)
+	return(EINVAL);
+
+    /*
+     * Try to make the DevIO windows not
+     * overlap by pushing the "io" and "hi"
+     * allocation areas up to the next one
+     * or two megabyte bound. This also
+     * keeps them from being zero.
+     *
+     * DO NOT do this with "pci_lo" since
+     * the entire "lo" area is only a
+     * megabyte, total ...
+     */
+    align = (slot < 2) ? 0x200000 : 0x100000;
+    mask = -align;
+    pci_io_fb = (pci_io_fb + align - 1) & mask;
+    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
+
+    for (func = 0; func < nfunc; ++func) {
+	cfg_p                   cfgw;
+	cfg_p                   wptr;
+	pciio_space_t           space;
+	iopaddr_t               base;
+	size_t                  size;
+	cfg_p                   pci_cfg_cmd_reg_p;
+	unsigned                pci_cfg_cmd_reg;
+	unsigned                pci_cfg_cmd_reg_add = 0;
+
+	pcibr_info = pcibr_infoh[func];
+
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+	
+	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	nbars = PCI_CFG_BASE_ADDRS;
+
+	for (win = 0; win < nbars; ++win) {
+
+	    space = pcibr_info->f_window[win].w_space;
+	    base = pcibr_info->f_window[win].w_base;
+	    size = pcibr_info->f_window[win].w_size;
+	    
+	    if (size < 1)
+		continue;
+
+	    if (base >= size) {
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
+			slot, func, win, space, base, base + size - 1);
+#endif
+		continue;		/* already allocated */
+	    }
+	    align = size;		/* ie. 0x00001000 */
+	    if (align < _PAGESZ)
+		align = _PAGESZ;	/* ie. 0x00004000 */
+	    mask = -align;		/* ie. 0xFFFFC000 */
+
+	    switch (space) {
+	    case PCIIO_SPACE_IO:
+		base = (pci_io_fb + align - 1) & mask;
+		if ((base + size) > pci_io_fl) {
+		    base = 0;
+		    break;
+		}
+		pci_io_fb = base + size;
+		break;
+		
+	    case PCIIO_SPACE_MEM:
+#ifdef LITTLE_ENDIAN
+		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
+#else
+		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
+#endif  /* LITTLE_ENDIAN */
+		    PCI_BA_MEM_1MEG) {
+		    /* allocate from 20-bit PCI space */
+		    base = (pci_lo_fb + align - 1) & mask;
+		    if ((base + size) > pci_lo_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_lo_fb = base + size;
+		} else {
+		    /* allocate from 32-bit or 64-bit PCI space */
+		    base = (pci_hi_fb + align - 1) & mask;
+		    if ((base + size) > pci_hi_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_hi_fb = base + size;
+		}
+		break;
+		
+	    default:
+		base = 0;
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d window %d had bad space code %d\n",
+			slot, win, space);
+#endif
+	    }
+	    pcibr_info->f_window[win].w_base = base;
+#ifdef LITTLE_ENDIAN
+	    wptr[((win*4)^4)/4] = base;
+#if DEBUG && PCI_DEBUG
+		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
+#endif
+#else
+	    wptr[win] = base;
+#endif  /* LITTLE_ENDIAN */
+
+#if DEBUG && PCI_DEBUG
+	    if (base >= size)
+		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
+			slot, func, win, space, base, base + size - 1);
+	    else
+		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
+			slot, func, win, size, space);
+#endif
+	}				/* next base */
+
+	/*
+	 * Allocate space for the EXPANSION ROM
+	 * NOTE: DO NOT DO THIS ON AN IOC3,
+	 * as it blows the system away.
+	 */
+	base = size = 0;
+	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
+	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
+
+	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
+#ifdef LITTLE_ENDIAN
+	    wptr[1] = 0xFFFFF000;
+	    mask = wptr[1];
+#else
+	    *wptr = 0xFFFFF000;
+	    mask = *wptr;
+#endif  /* LITTLE_ENDIAN */
+	    if (mask & 0xFFFFF000) {
+		size = mask & -mask;
+		align = size;
+		if (align < _PAGESZ)
+		    align = _PAGESZ;
+		mask = -align;
+		base = (pci_hi_fb + align - 1) & mask;
+		if ((base + size) > pci_hi_fl)
+		    base = size = 0;
+		else {
+		    pci_hi_fb = base + size;
+#ifdef LITTLE_ENDIAN
+		    wptr[1] = base;
+#else
+		    *wptr = base;
+#endif  /* LITTLE_ENDIAN */
+#if DEBUG && PCI_DEBUG
+		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
+			    pcibr_soft->bs_name, slot,
+			    base, base + size - 1);
+#endif
+		}
+	    }
+	}
+	pcibr_info->f_rbase = base;
+	pcibr_info->f_rsize = size;
+	
+	/*
+	 * if necessary, update the board's
+	 * command register to enable decoding
+	 * in the windows we added.
+	 *
+	 * There are some bits we always want to
+	 * be sure are set.
+	 */
+	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
+
+	/*
+	 * The Adaptec 1160 FC Controller WAR #767995:
+	 * The part incorrectly ignores the upper 32 bits of a 64 bit
+	 * address when decoding references to it's registers so to
+	 * keep it from responding to a bus cycle that it shouldn't
+	 * we only use I/O space to get at it's registers.  Don't
+	 * enable memory space accesses on that PCI device.
+	 */
+	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
+	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
+
+	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
+	    (pcibr_info->f_device != FCADP_DEVID))
+	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
+
+	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
+
+	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
+	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
+#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
+	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
+	    fast_back_to_back_enable = 0;
+#endif
+	pci_cfg_cmd_reg &= 0xFFFF;
+	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
+	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
+	
+    }				/* next func */
+
+    /* Now that we have allocated new chunks of PCI address spaces to this
+     * card we need to update the bookkeeping values which indicate
+     * the current PCI address space allocations.
+     */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}
+
+/*
+ * pcibr_slot_device_init
+ * 	Setup the device register in the bridge for this PCI slot.
+ */
+int
+pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
+		       pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    bridgereg_t		 devreg;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * Adjustments to Device(x)
+     * and init of bss_device shadow
+     */
+    devreg = bridge->b_device[slot].reg;
+    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
+    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
+#ifdef LITTLE_ENDIAN
+    devreg |= BRIDGE_DEV_DEV_SWAP;
+#endif
+    pcibr_soft->bs_slot[slot].bss_device = devreg;
+    bridge->b_device[slot].reg = devreg;
+
+#if DEBUG && PCI_DEBUG
+	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
+#endif
+
+#if DEBUG && PCI_DEBUG
+    printk("pcibr: PCI space allocation done.\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_guest_info_init
+ *	Setup the host/guest relations for a PCI slot.
+ */
+int
+pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    pcibr_soft_slot_t	slotp;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    /* create info and verticies for guest slots;
+     * for compatibilitiy macros, create info
+     * for even unpopulated slots (but do not
+     * build verticies for them).
+     */
+    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
+	NEWA(pcibr_infoh, 1);
+	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
+	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
+	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+
+	if (pcibr_soft->bs_slot[slot].has_host) {
+	    slotp->slot_conn = pciio_device_info_register
+		(pcibr_vhdl, &pcibr_info->f_c);
+	}
+    }
+
+    /* generate host/guest relations
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	int  host = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
+
+	hwgraph_edge_add(slotp->slot_conn,
+			 host_slotp->slot_conn,
+			 EDGE_LBL_HOST);
+
+	/* XXX- only gives us one guest edge per
+	 * host. If/when we have a host with more than
+	 * one guest, we will need to figure out how
+	 * the host finds all its guests, and sorts
+	 * out which one is which.
+	 */
+	hwgraph_edge_add(host_slotp->slot_conn,
+			 slotp->slot_conn,
+			 EDGE_LBL_GUEST);
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_initial_rrb_alloc
+ *	Allocate a default number of rrbs for this slot on 
+ * 	the two channels.  This is dictated by the rrb allocation
+ * 	strategy routine defined per platform.
+ */
+
+int
+pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    int                 c0, c1;
+    int			r;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* How may RRBs are on this slot?
+     */
+    c0 = do_pcibr_rrb_count_valid(bridge, slot);
+    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
+
+#if PCIBR_RRB_DEBUG
+    printk("pcibr_attach: slot %d started with %d+%d\n", slot, c0, c1);
+#endif
+
+    /* Do we really need any?
+     */
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    pcibr_info = pcibr_infoh[0];
+    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
+	!pcibr_soft->bs_slot[slot].has_host) {
+	if (c0 > 0)
+	    do_pcibr_rrb_free(bridge, slot, c0);
+	if (c1 > 0)
+	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
+	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
+	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
+	return(ENODEV);
+    }
+
+    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
+    pcibr_soft->bs_rrb_valid[slot] = c0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
+
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    r = 3 - (c0 + c1);
+
+    if (r > 0) {
+	pcibr_soft->bs_rrb_res[slot] = r;
+	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_call_device_attach
+ *	This calls the associated driver attach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    async_attach_t	aa = NULL;
+    int			func;
+    devfs_handle_t	xconn_vhdl,conn_vhdl;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+        return(EPERM);
+    }
+    
+    xconn_vhdl = pcibr_soft->bs_conn;
+    aa = async_attach_get_info(xconn_vhdl);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+#ifdef LATER
+	/*
+	 * Activate if and when we support cdl.
+	 */
+	if (aa)
+	    async_attach_add_info(conn_vhdl, aa);
+#endif	/* LATER */
+
+	error_func = pciio_device_attach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+        error = error_slot;
+
+    }				/* next func */
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_call_device_detach
+ *	This calls the associated driver detach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    int			func;
+    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    if (pcibr_soft->bs_slot[slot].has_host)
+        return(EPERM);
+
+    /* Make sure that we do not detach a system critical function vertex */
+    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+	error_func = pciio_device_detach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+	error = error_slot;
+
+    }				/* next func */
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        if (conn_vhdl != GRAPH_VERTEX_NONE) 
+            pcibr_device_unregister(conn_vhdl);
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_detach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific freeing that needs to be done.
+ */
+int
+pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags)
+{
+    int		  error;
+    
+    /* Call the device detach function */
+    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
+    return (error);
+
+}
+
+/*
+ * pcibr_is_slot_sys_critical
+ *      Check slot for any functions that are system critical.
+ *      Return 1 if any are system critical or 0 otherwise.
+ *
+ *      This function will always return 0 when called by 
+ *      pcibr_attach() because the system critical vertices 
+ *      have not yet been set in the hwgraph.
+ */
+int
+pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
+                      pciio_slot_t slot)
+{
+    pcibr_soft_t        pcibr_soft;
+    pcibr_info_h        pcibr_infoh;
+    pcibr_info_t        pcibr_info;
+    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
+    int                 nfunc;
+    int                 func;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+        return(0);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+        pcibr_info = pcibr_infoh[func];
+        if (!pcibr_info)
+            continue;
+
+        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+            continue;
+
+        conn_vhdl = pcibr_info->f_vertex;
+        if (is_sys_critical_vertex(conn_vhdl)) { 
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+            printk(KERN_WARNING  "%v is a system critical device vertex\n", conn_vhdl);
+#else
+            printk(KERN_WARNING  "%p is a system critical device vertex\n", (void *)conn_vhdl);
+#endif
+            return(1); 
+        }
+
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_device_unregister
+ *	This frees up any hardware resources reserved for this PCI device
+ * 	and removes any PCI infrastructural information setup for it.
+ *	This is usually used at the time of shutting down of the PCI card.
+ */
+int
+pcibr_device_unregister(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t	 pciio_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    int			 error_call;
+    int			 error = 0;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Clear all the hardware xtalk resources for this device */
+    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
+
+    /* Flush all the rrbs */
+    pcibr_rrb_flush(pconn_vhdl);
+
+    /* Free the rrbs allocated to this slot */
+    error_call = do_pcibr_rrb_free(bridge, slot, 
+		                   pcibr_soft->bs_rrb_valid[slot] +
+		                   pcibr_soft->bs_rrb_valid[slot + 
+                                   PCIBR_RRB_SLOT_VIRTUAL]);
+
+    if (error_call)
+        error = ERANGE;
+
+    pcibr_soft->bs_rrb_valid[slot] = 0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0;
+    pcibr_soft->bs_rrb_res[slot] = 0;
+
+    /* Flush the write buffers !! */
+    error_call = pcibr_wrb_flush(pconn_vhdl);
+
+    if (error_call)
+        error = error_call;
+
+    /* Clear the information specific to the slot */
+    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
+
+    if (error_call)
+        error = error_call;
+
+    return(error);
+    
+}
+
+/* 
+ * build a convenience link path in the
+ * form of ".../<iobrick>/bus/<busnum>"
+ * 
+ * returns 1 on success, 0 otherwise
+ *
+ * depends on hwgraph separator == '/'
+ */
+int
+pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
+{
+        char dst[MAXDEVNAME];
+	char *dp = dst;
+        char *cp, *xp;
+        int widgetnum;
+        char pcibus[8];
+	devfs_handle_t nvtx, svtx;
+	int rv;
+
+#if DEBUG
+	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
+		slot, f_c);
+	{
+		int pos;
+		char dname[256];
+		pos = devfs_generate_path(f_c, dname, 256);
+		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
+	}
+#endif
+
+	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
+		return 0;
+
+	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
+
+	/* find the widget number */
+	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
+	if (xp == NULL)
+		return 0;
+	widgetnum = atoi(xp+7);
+	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
+		return 0;
+
+	/* remove "/pci/direct" from path */
+	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
+	if (cp == NULL)
+		return 0;
+	*cp = (char)NULL;
+
+	/* get the vertex for the widget */
+	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
+		return 0;
+
+	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
+
+	/* dst example now == /hw/module/001c02/Pbrick */
+
+	/* get the bus number */
+        strcat(dst, "/bus");
+        sprintf(pcibus, "%d", p_busnum[widgetnum]);
+
+	/* link to bus to widget */
+	rv = hwgraph_path_add(NULL, dp, &nvtx);
+	if (GRAPH_SUCCESS == rv)
+		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
+
+	return (rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ *    pcibr_attach: called every time the crosstalk
+ *      infrastructure is asked to initialize a widget
+ *      that matches the part number we handed to the
+ *      registration routine above.
+ */
+/*ARGSUSED */
+int
+pcibr_attach(devfs_handle_t xconn_vhdl)
+{
+    /* REFERENCED */
+    graph_error_t           rc;
+    devfs_handle_t            pcibr_vhdl;
+    devfs_handle_t            ctlr_vhdl;
+    bridge_t               *bridge = NULL;
+    bridgereg_t             id;
+    int                     rev;
+    pcibr_soft_t            pcibr_soft;
+    pcibr_info_t            pcibr_info;
+    xwidget_info_t          info;
+    xtalk_intr_t            xtalk_intr;
+    device_desc_t           dev_desc = (device_desc_t)0;
+    int                     slot;
+    int                     ibit;
+    devfs_handle_t            noslot_conn;
+    char                    devnm[MAXDEVNAME], *s;
+    pcibr_hints_t           pcibr_hints;
+    bridgereg_t             b_int_enable;
+    unsigned                rrb_fixed = 0;
+
+    iopaddr_t               pci_io_fb, pci_io_fl;
+    iopaddr_t               pci_lo_fb, pci_lo_fl;
+    iopaddr_t               pci_hi_fb, pci_hi_fl;
+
+    int                     spl_level;
+#ifdef LATER
+    char		    *nicinfo = (char *)0;
+#endif
+
+#if PCI_FBBE
+    int                     fast_back_to_back_enable;
+#endif
+    l1sc_t		    *scp;
+    nasid_t		    nasid;
+
+    async_attach_t          aa = NULL;
+
+    aa = async_attach_get_info(xconn_vhdl);
+
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
+    {
+	int pos;
+	char dname[256];
+	pos = devfs_generate_path(xconn_vhdl, dname, 256);
+	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
+    }
+#endif
+
+    /* Setup the PRB for the bridge in CONVEYOR BELT
+     * mode. PRBs are setup in default FIRE-AND-FORGET
+     * mode during the initialization.
+     */
+    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
+
+    bridge = (bridge_t *)
+	xtalk_piotrans_addr(xconn_vhdl, NULL,
+			    0, sizeof(bridge_t), 0);
+
+#ifndef MEDUSA_HACK
+    if ((bridge->b_wid_stat & BRIDGE_STAT_PCI_GIO_N) == 0)
+	return -1;			/* someone else handles GIO bridges. */
+#endif
+
+    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
+	NeedXbridgeSwap = 1;
+
+    /*
+     * Create the vertex for the PCI bus, which we
+     * will also use to hold the pcibr_soft and
+     * which will be the "master" vertex for all the
+     * pciio connection points we will hang off it.
+     * This needs to happen before we call nic_bridge_vertex_info
+     * as we are some of the *_vmc functions need access to the edges.
+     *
+     * Opening this vertex will provide access to
+     * the Bridge registers themselves.
+     */
+    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
+    ASSERT(rc == GRAPH_SUCCESS);
+
+    ctlr_vhdl = NULL;
+    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
+                0, DEVFS_FL_AUTO_DEVNUM,
+                0, 0,
+                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+                &pcibr_fops, NULL);
+
+    ASSERT(ctlr_vhdl != NULL);
+
+    /*
+     * decode the nic, and hang its stuff off our
+     * connection point where other drivers can get
+     * at it.
+     */
+#ifdef LATER
+    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
+#endif
+
+    /*
+     * Get the hint structure; if some NIC callback
+     * marked this vertex as "hands-off" then we
+     * just return here, before doing anything else.
+     */
+    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
+
+    if (pcibr_hints && pcibr_hints->ph_hands_off)
+	return -1;			/* generic operations disabled */
+
+    id = bridge->b_wid_id;
+    rev = XWIDGET_PART_REV_NUM(id);
+
+    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
+
+    /*
+     * allocate soft state structure, fill in some
+     * fields, and hook it up to our vertex.
+     */
+    NEW(pcibr_soft);
+    BZERO(pcibr_soft, sizeof *pcibr_soft);
+    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
+
+    pcibr_soft->bs_conn = xconn_vhdl;
+    pcibr_soft->bs_vhdl = pcibr_vhdl;
+    pcibr_soft->bs_base = bridge;
+    pcibr_soft->bs_rev_num = rev;
+    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
+    if (is_xbridge(bridge)) {
+	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 1;
+    } else {
+	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 0;
+    }
+
+    nasid = NASID_GET(bridge);
+    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
+    pcibr_soft->bs_l1sc = scp;
+    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
+    pcibr_soft->bsi_err_intr = 0;
+
+    /* Bridges up through REV C
+     * are unable to set the direct
+     * byteswappers to BYTE_STREAM.
+     */
+    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
+	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
+	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
+    }
+#if PCIBR_SOFT_LIST
+    {
+	pcibr_list_p            self;
+
+	NEW(self);
+	self->bl_soft = pcibr_soft;
+	self->bl_vhdl = pcibr_vhdl;
+	self->bl_next = pcibr_list;
+	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
+    }
+#endif
+
+    /*
+     * get the name of this bridge vertex and keep the info. Use this
+     * only where it is really needed now: like error interrupts.
+     */
+    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
+    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    strcpy(pcibr_soft->bs_name, s);
+
+#if SHOW_REVS || DEBUG
+#if !DEBUG
+    if (kdebug)
+#endif
+	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
+		is_xbridge(bridge) ? "X" : "",
+		(rev == BRIDGE_PART_REV_A) ? "A" :
+		(rev == BRIDGE_PART_REV_B) ? "B" :
+		(rev == BRIDGE_PART_REV_C) ? "C" :
+		(rev == BRIDGE_PART_REV_D) ? "D" :
+		(rev == XBRIDGE_PART_REV_A) ? "A" :
+		(rev == XBRIDGE_PART_REV_B) ? "B" :
+		"unknown",
+		rev, pcibr_soft->bs_name);
+#endif
+
+    info = xwidget_info_get(xconn_vhdl);
+    pcibr_soft->bs_xid = xwidget_info_id_get(info);
+    pcibr_soft->bs_master = xwidget_info_master_get(info);
+    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
+
+    /*
+     * Init bridge lock.
+     */
+    spin_lock_init(&pcibr_soft->bs_lock);
+
+    /*
+     * If we have one, process the hints structure.
+     */
+    if (pcibr_hints) {
+	rrb_fixed = pcibr_hints->ph_rrb_fixed;
+
+	pcibr_soft->bs_rrb_fixed = rrb_fixed;
+
+	if (pcibr_hints->ph_intr_bits)
+	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
+
+	for (slot = 0; slot < 8; ++slot) {
+	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
+
+	    if (hslot < 0) {
+		pcibr_soft->bs_slot[slot].host_slot = slot;
+	    } else {
+		pcibr_soft->bs_slot[slot].has_host = 1;
+		pcibr_soft->bs_slot[slot].host_slot = hslot;
+	    }
+	}
+    }
+    /*
+     * set up initial values for state fields
+     */
+    for (slot = 0; slot < 8; ++slot) {
+	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
+	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
+    }
+
+    for (ibit = 0; ibit < 8; ++ibit) {
+	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
+							&(bridge->b_int_status);
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
+    }
+
+    /*
+     * Initialize various Bridge registers.
+     */
+
+    /*
+     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
+     * to zero to avoid dropping stores. (#475347)
+     */
+    if (rev < BRIDGE_PART_REV_D)
+	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
+
+    /*
+     * Clear all pending interrupts.
+     */
+    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
+
+    /*
+     * Until otherwise set up,
+     * assume all interrupts are
+     * from slot 7.
+     */
+    bridge->b_int_device = (uint32_t) 0xffffffff;
+
+    {
+	bridgereg_t             dirmap;
+	paddr_t                 paddr;
+	iopaddr_t               xbase;
+	xwidgetnum_t            xport;
+	iopaddr_t               offset;
+	int                     num_entries = 0;
+	int                     entry;
+	cnodeid_t		cnodeid;
+	nasid_t			nasid;
+
+	/* Set the Bridge's 32-bit PCI to XTalk
+	 * Direct Map register to the most useful
+	 * value we can determine.  Note that we
+	 * must use a single xid for all of:
+	 *      direct-mapped 32-bit DMA accesses
+	 *      direct-mapped 64-bit DMA accesses
+	 *      DMA accesses through the PMU
+	 *      interrupts
+	 * This is the only way to guarantee that
+	 * completion interrupts will reach a CPU
+	 * after all DMA data has reached memory.
+	 * (Of course, there may be a few special
+	 * drivers/controlers that explicitly manage
+	 * this ordering problem.)
+	 */
+
+	cnodeid = 0;  /* default node id */
+	/*
+	 * Determine the base address node id to be used for all 32-bit
+	 * Direct Mapping I/O. The default is node 0, but this can be changed
+	 * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE
+	 * attribute in the irix.sm config file. A device driver can obtain
+	 * this node value via a call to pcibr_get_dmatrans_node().
+	 */
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+	paddr = NODE_OFFSET(nasid) + 0;
+
+	/* currently, we just assume that if we ask
+	 * for a DMA mapping to "zero" the XIO
+	 * host will transmute this into a request
+	 * for the lowest hunk of memory.
+	 */
+	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
+				    paddr, _PAGESZ, 0);
+
+	if (xbase != XIO_NOWHERE) {
+	    if (XIO_PACKED(xbase)) {
+		xport = XIO_PORT(xbase);
+		xbase = XIO_ADDR(xbase);
+	    } else
+		xport = pcibr_soft->bs_mxid;
+
+	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
+	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
+
+	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
+
+	    if (xbase)
+		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
+	    else if (offset >= (512 << 20))
+		dirmap |= BRIDGE_DIRMAP_ADD512;
+
+	    bridge->b_dir_map = dirmap;
+	}
+	/*
+	 * Set bridge's idea of page size according to the system's
+	 * idea of "IO page size".  TBD: The idea of IO page size
+	 * should really go away.
+	 */
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	spl_level = splhi();
+#if IOPGSIZE == 4096
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#elif IOPGSIZE == 16384
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#else
+	<<<Unable to deal with IOPGSIZE >>>;
+#endif
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(spl_level);
+
+	/* Initialize internal mapping entries */
+	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++)
+	    bridge->b_int_ate_ram[entry].wr = 0;
+
+	/*
+	 * Determine if there's external mapping SSRAM on this
+	 * bridge.  Set up Bridge control register appropriately,
+	 * inititlize SSRAM, and set software up to manage RAM
+	 * entries as an allocatable resource.
+	 *
+	 * Currently, we just use the rm* routines to manage ATE
+	 * allocation.  We should probably replace this with a
+	 * Best Fit allocator.
+	 *
+	 * For now, if we have external SSRAM, avoid using
+	 * the internal ssram: we can't turn PREFETCH on
+	 * when we use the internal SSRAM; and besides,
+	 * this also guarantees that no allocation will
+	 * straddle the internal/external line, so we
+	 * can increment ATE write addresses rather than
+	 * recomparing against BRIDGE_INTERNAL_ATES every
+	 * time.
+	 */
+	if (is_xbridge(bridge))
+		num_entries = 0;
+	else
+		num_entries = pcibr_init_ext_ate_ram(bridge);
+
+	/* we always have 128 ATEs (512 for Xbridge) inside the chip
+	 * even if disabled for debugging.
+	 */
+	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
+	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
+#endif
+
+	if (num_entries > pcibr_soft->bs_int_ate_size) {
+#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
+	    printk("pcibr_attach: disabling internal ATEs.\n");
+	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
+#endif
+	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
+	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
+			   num_entries - pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
+		    num_entries - pcibr_soft->bs_int_ate_size);
+#endif
+	}
+    }
+
+    {
+	bridgereg_t             dirmap;
+	iopaddr_t               xbase;
+
+	/*
+	 * now figure the *real* xtalk base address
+	 * that dirmap sends us to.
+	 */
+	dirmap = bridge->b_dir_map;
+	if (dirmap & BRIDGE_DIRMAP_OFF)
+	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
+			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
+	else if (dirmap & BRIDGE_DIRMAP_ADD512)
+	    xbase = 512 << 20;
+	else
+	    xbase = 0;
+
+	pcibr_soft->bs_dir_xbase = xbase;
+
+	/* it is entirely possible that we may, at this
+	 * point, have our dirmap pointing somewhere
+	 * other than our "master" port.
+	 */
+	pcibr_soft->bs_dir_xport =
+	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
+    }
+
+    /* pcibr sources an error interrupt;
+     * figure out where to send it.
+     *
+     * If any interrupts are enabled in bridge,
+     * then the prom set us up and our interrupt
+     * has already been reconnected in mlreset
+     * above.
+     *
+     * Need to set the D_INTR_ISERR flag
+     * in the dev_desc used for allocating the
+     * error interrupt, so our interrupt will
+     * be properly routed and prioritized.
+     *
+     * If our crosstalk provider wants to
+     * fix widget error interrupts to specific
+     * destinations, D_INTR_ISERR is how it
+     * knows to do this.
+     */
+
+    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
+    ASSERT(xtalk_intr != NULL);
+
+    pcibr_soft->bsi_err_intr = xtalk_intr;
+
+    /*
+     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
+     * in order to work around some addressing limitations.  In order
+     * for that fire wall to work properly, we need to make sure we
+     * start from a known clean state.
+     */
+    pcibr_clearwidint(bridge);
+
+    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge);
+
+    /*
+     * now we can start handling error interrupts;
+     * enable all of them.
+     * NOTE: some PCI ints may already be enabled.
+     */
+    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
+
+
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
+
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * Depending on the rev of bridge, disable certain features.
+     * Easiest way seems to be to force the PCIBR_NOwhatever
+     * flag to be on for all DMA calls, which overrides any
+     * PCIBR_whatever flag or even the setting of whatever
+     * from the PCIIO_DMA_class flags (or even from the other
+     * PCIBR flags, since NO overrides YES).
+     */
+    pcibr_soft->bs_dma_flags = 0;
+
+    /* PREFETCH:
+     * Always completely disabled for REV.A;
+     * at "pcibr_prefetch_enable_rev", anyone
+     * asking for PCIIO_PREFETCH gets it.
+     * Between these two points, you have to ask
+     * for PCIBR_PREFETCH, which promises that
+     * your driver knows about known Bridge WARs.
+     */
+    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
+	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
+    else if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
+
+    /* WRITE_GATHER:
+     * Disabled up to but not including the
+     * rev number in pcibr_wg_enable_rev. There
+     * is no "WAR range" as with prefetch.
+     */
+    if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
+
+    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
+    pciio_provider_startup(pcibr_vhdl);
+
+    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
+    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
+
+    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
+    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
+
+    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
+    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
+
+
+    PCI_ADDR_SPACE_LIMITS_STORE();
+
+    /* build "no-slot" connection point
+     */
+    pcibr_info = pcibr_device_info_new
+	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
+	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+    noslot_conn = pciio_device_info_register
+	(pcibr_vhdl, &pcibr_info->f_c);
+
+    /* Remember the no slot connection point info for tearing it
+     * down during detach.
+     */
+    pcibr_soft->bs_noslot_conn = noslot_conn;
+    pcibr_soft->bs_noslot_info = pcibr_info;
+#if PCI_FBBE
+    fast_back_to_back_enable = 1;
+#endif
+
+#if PCI_FBBE
+    if (fast_back_to_back_enable) {
+	/*
+	 * All devices on the bus are capable of fast back to back, so
+	 * we need to set the fast back to back bit in all devices on
+	 * the bus that are capable of doing such accesses.
+	 */
+    }
+#endif
+
+#ifdef LATER
+    /* If the bridge has been reset then there is no need to reset
+     * the individual PCI slots.
+     */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Reset all the slots */
+	(void)pcibr_slot_reset(pcibr_vhdl, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)
+	/* Find out what is out there */
+	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up the address space for this slot in the pci land */
+	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup the device register */
+	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
+
+#ifndef __ia64
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up convenience links */
+	if (is_xbridge(bridge))
+		if (pcibr_soft->bs_slot[slot].bss_ninfo > 0) /* if occupied */
+			pcibr_bus_cnvlink(pcibr_info->f_vertex, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup host/guest relations */
+	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Initial RRB management */
+	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
+
+    /* driver attach routines should be called out from generic linux code */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Call the device attach */
+	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
+
+    /*
+     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
+     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
+     */
+    if (pcibr_soft->bs_moduleid > 0) {
+	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
+	case 'p':		/* Pbrick */
+		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		break;
+	case 'i':		/* Ibrick */
+	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
+		if (pcibr_soft->bs_xid == 0xe) {
+			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		}
+		else {
+		    	/* allocate one RRB for the serial port */
+			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
+		}
+		break;
+	} /* switch */
+    }
+
+#ifdef LATER
+    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
+	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+#if PCIBR_RRB_DEBUG
+	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
+
+	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
+		pcibr_vhdl,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+
+	for (slot = 0; slot < 8; ++slot)
+	    printf("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+
+	printf("\n");
+#endif
+    }
+#else
+	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
+#endif
+
+    if (aa)
+	    async_attach_add_info(noslot_conn, aa);
+
+    pciio_device_attach(noslot_conn, 0);
+
+
+    /* 
+     * Tear down pointer to async attach info -- async threads for
+     * bridge's descendants may be running but the bridge's work is done.
+     */
+    if (aa)
+	    async_attach_del_info(xconn_vhdl);
+
+    return 0;
+}
+/*
+ * pcibr_detach:
+ *	Detach the bridge device from the hwgraph after cleaning out all the 
+ *	underlying vertices.
+ */
+int
+pcibr_detach(devfs_handle_t xconn)
+{
+    pciio_slot_t	slot;
+    devfs_handle_t	pcibr_vhdl;
+    pcibr_soft_t	pcibr_soft;
+    bridge_t		*bridge;
+
+    /* Get the bridge vertex from its xtalk connection point */
+    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
+	return(1);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Disable the interrupts from the bridge */
+    bridge->b_int_enable = 0;
+
+    /* Detach all the PCI devices talking to this bridge */
+    for(slot = 0; slot < 8; slot++) {
+#ifdef DEBUG
+	printk("pcibr_device_detach called for %p/%d\n",
+		pcibr_vhdl,slot);
+#endif
+	pcibr_slot_detach(pcibr_vhdl, slot, 0);
+    }
+
+    /* Unregister the no-slot connection point */
+    pciio_device_info_unregister(pcibr_vhdl,
+				 &(pcibr_soft->bs_noslot_info->f_c));
+
+    spin_lock_destroy(&pcibr_soft->bs_lock);
+    kfree(pcibr_soft->bs_name);
+    
+    /* Error handler gets unregistered when the widget info is 
+     * cleaned 
+     */
+    /* Free the soft ATE maps */
+    if (pcibr_soft->bs_int_ate_map)
+	rmfreemap(pcibr_soft->bs_int_ate_map);
+    if (pcibr_soft->bs_ext_ate_map)
+	rmfreemap(pcibr_soft->bs_ext_ate_map);
+
+    /* Disconnect the error interrupt and free the xtalk resources 
+     * associated with it.
+     */
+    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
+    xtalk_intr_free(pcibr_soft->bsi_err_intr);
+
+    /* Clear the software state maintained by the bridge driver for this
+     * bridge.
+     */
+    DEL(pcibr_soft);
+    /* Remove the Bridge revision labelled info */
+    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
+    /* Remove the character device associated with this bridge */
+    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
+    /* Remove the PCI bridge vertex */
+    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
+
+    return(0);
+}
+
+int
+pcibr_asic_rev(devfs_handle_t pconn_vhdl)
+{
+    devfs_handle_t            pcibr_vhdl;
+    arbitrary_info_t        ainfo;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
+	return -1;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
+	return -1;
+
+    return (int) ainfo;
+}
+
+int
+pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t  slot;
+    slot = pciio_info_slot_get(pciio_info);
+    pcibr_device_write_gather_flush(pcibr_soft, slot);
+    return 0;
+}
+
+/* =====================================================================
+ *    PIO MANAGEMENT
+ */
+
+LOCAL iopaddr_t
+pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
+		      pciio_slot_t slot,
+		      pciio_space_t space,
+		      iopaddr_t pci_addr,
+		      size_t req_size,
+		      unsigned flags)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    unsigned                bar;	/* which BASE reg on device is decoding */
+    iopaddr_t               xio_addr = XIO_NOWHERE;
+
+    pciio_space_t           wspace;	/* which space device is decoding */
+    iopaddr_t               wbase;	/* base of device decode on PCI */
+    size_t                  wsize;	/* size of device decode on PCI */
+
+    int                     try;	/* DevIO(x) window scanning order control */
+    int                     win;	/* which DevIO(x) window is being used */
+    pciio_space_t           mspace;	/* target space for devio(x) register */
+    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
+    size_t                  msize;	/* size of devio(x) mapped area on PCI */
+    size_t                  mmask;	/* addr bits stored in Device(x) */
+
+    unsigned long           s;
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	slot = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
+    }
+    if (space == PCIIO_SPACE_NONE)
+	goto done;
+
+    if (space == PCIIO_SPACE_CFG) {
+	/*
+	 * Usually, the first mapping
+	 * established to a PCI device
+	 * is to its config space.
+	 *
+	 * In any case, we definitely
+	 * do NOT need to worry about
+	 * PCI BASE registers, and
+	 * MUST NOT attempt to point
+	 * the DevIO(x) window at
+	 * this access ...
+	 */
+	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
+	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
+	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
+
+	goto done;
+    }
+    if (space == PCIIO_SPACE_ROM) {
+	/* PIO to the Expansion Rom.
+	 * Driver is responsible for
+	 * enabling and disabling
+	 * decodes properly.
+	 */
+	wbase = pcibr_info->f_rbase;
+	wsize = pcibr_info->f_rsize;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	pci_addr += wbase;
+	space = PCIIO_SPACE_MEM;
+    }
+    /*
+     * reduce window mappings to raw
+     * space mappings (maybe allocating
+     * windows), and try for DevIO(x)
+     * usage (setting it if it is available).
+     */
+    bar = space - PCIIO_SPACE_WIN0;
+    if (bar < 6) {
+	wspace = pcibr_info->f_window[bar].w_space;
+	if (wspace == PCIIO_SPACE_NONE)
+	    goto done;
+
+	/* get PCI base and size */
+	wbase = pcibr_info->f_window[bar].w_base;
+	wsize = pcibr_info->f_window[bar].w_size;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	/* shift from window relative to
+	 * decoded space relative.
+	 */
+	pci_addr += wbase;
+	space = wspace;
+    } else
+	bar = -1;
+
+    /* Scan all the DevIO(x) windows twice looking for one
+     * that can satisfy our request. The first time through,
+     * only look at assigned windows; the second time, also
+     * look at PCIIO_SPACE_NONE windows. Arrange the order
+     * so we always look at our own window first.
+     *
+     * We will not attempt to satisfy a single request
+     * by concatinating multiple windows.
+     */
+    for (try = 0; try < 16; ++try) {
+	bridgereg_t             devreg;
+	unsigned                offset;
+
+	win = (try + slot) % 8;
+
+	/* If this DevIO(x) mapping area can provide
+	 * a mapping to this address, use it.
+	 */
+	msize = (win < 2) ? 0x200000 : 0x100000;
+	mmask = -msize;
+	if (space != PCIIO_SPACE_IO)
+	    mmask &= 0x3FFFFFFF;
+
+	offset = pci_addr & (msize - 1);
+
+	/* If this window can't possibly handle that request,
+	 * go on to the next window.
+	 */
+	if (((pci_addr & (msize - 1)) + req_size) > msize)
+	    continue;
+
+	devreg = pcibr_soft->bs_slot[win].bss_device;
+
+	/* Is this window "nailed down"?
+	 * If not, maybe we can use it.
+	 * (only check this the second time through)
+	 */
+	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
+	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
+
+	    /* If this is the primary DevIO(x) window
+	     * for some other device, skip it.
+	     */
+	    if ((win != slot) &&
+		(PCIIO_VENDOR_ID_NONE !=
+		 pcibr_soft->bs_slot[win].bss_vendor_id))
+		continue;
+
+	    /* It's a free window, and we fit in it.
+	     * Set up Device(win) to our taste.
+	     */
+	    mbase = pci_addr & mmask;
+
+	    /* check that we would really get from
+	     * here to there.
+	     */
+	    if ((mbase | offset) != pci_addr)
+		continue;
+
+	    devreg &= ~BRIDGE_DEV_OFF_MASK;
+	    if (space != PCIIO_SPACE_IO)
+		devreg |= BRIDGE_DEV_DEV_IO_MEM;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
+	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	    /* default is WORD_VALUES.
+	     * if you specify both,
+	     * operation is undefined.
+	     */
+	    if (flags & PCIIO_BYTE_STREAM)
+		devreg |= BRIDGE_DEV_DEV_SWAP;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_SWAP;
+
+	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
+		bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+
+#if DEBUG && PCI_DEBUG
+		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
+#endif
+	    }
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
+	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
+		    __FUNCTION__, __LINE__, space, space_desc,
+		    pci_addr, pci_addr + req_size - 1,
+		    slot, win, devreg);
+#endif
+
+	    goto done;
+	}				/* endif DevIO(x) not pointed */
+	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
+
+	/* Now check for request incompat with DevIO(x)
+	 */
+	if ((mspace != space) ||
+	    (pci_addr < mbase) ||
+	    ((pci_addr + req_size) > (mbase + msize)) ||
+	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
+	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
+	    continue;
+
+	/* DevIO(x) window is pointed at PCI space
+	 * that includes our target. Calculate the
+	 * final XIO address, release the lock and
+	 * return.
+	 */
+	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
+		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
+#endif
+	goto done;
+    }
+
+    switch (space) {
+	/*
+	 * Accesses to device decode
+	 * areas that do a not fit
+	 * within the DevIO(x) space are
+	 * modified to be accesses via
+	 * the direct mapping areas.
+	 *
+	 * If necessary, drivers can
+	 * explicitly ask for mappings
+	 * into these address spaces,
+	 * but this should never be needed.
+	 */
+    case PCIIO_SPACE_MEM:		/* "mem space" */
+    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM32_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
+	break;
+
+    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM64_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
+	break;
+
+    case PCIIO_SPACE_IO:		/* "i/o space" */
+	/* Bridge Hardware Bug WAR #482741:
+	 * The 4G area that maps directly from
+	 * XIO space to PCI I/O space is busted
+	 * until Bridge Rev D.
+	 */
+	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
+	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
+	     BRIDGE_PCI_IO_LIMIT))
+	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
+	break;
+    }
+
+    /* Check that "Direct PIO" byteswapping matches,
+     * try to change it if it does not.
+     */
+    if (xio_addr != XIO_NOWHERE) {
+	unsigned                bst;	/* nonzero to set bytestream */
+	unsigned               *bfp;	/* addr of record of how swapper is set */
+	unsigned                swb;	/* which control bit to mung */
+	unsigned                bfo;	/* current swapper setting */
+	unsigned                bfn;	/* desired swapper setting */
+
+	bfp = ((space == PCIIO_SPACE_IO)
+	       ? (&pcibr_soft->bs_pio_end_io)
+	       : (&pcibr_soft->bs_pio_end_mem));
+
+	bfo = *bfp;
+
+	bst = flags & PCIIO_BYTE_STREAM;
+
+	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
+
+	if (bfn == bfo) {		/* we already match. */
+	    ;
+	} else if (bfo != 0) {		/* we have a conflict. */
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
+		    space, 
+		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	    xio_addr = XIO_NOWHERE;
+	} else {			/* OK to make the change. */
+	    bridgereg_t             octl, nctl;
+
+	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
+	    octl = bridge->b_wid_control;
+	    nctl = bst ? octl | swb : octl & ~swb;
+
+	    if (octl != nctl)		/* make the change if any */
+		bridge->b_wid_control = nctl;
+
+	    *bfp = bfn;			/* record the assignment */
+
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
+		    space, 
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	}
+    }
+  done:
+    pcibr_unlock(pcibr_soft, s);
+    return xio_addr;
+}
+
+/*ARGSUSED6 */
+pcibr_piomap_t
+pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   pciio_space_t space,
+		   iopaddr_t pci_addr,
+		   size_t req_size,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    pcibr_piomap_t         *mapptr;
+    pcibr_piomap_t          maplist;
+    pcibr_piomap_t          pcibr_piomap;
+    iopaddr_t               xio_addr;
+    xtalk_piomap_t          xtalk_piomap;
+    unsigned long           s;
+
+    /* Make sure that the req sizes are non-zero */
+    if ((req_size < 1) || (req_size_max < 1))
+	return NULL;
+
+    /*
+     * Code to translate slot/space/addr
+     * into xio_addr is common between
+     * this routine and pcibr_piotrans_addr.
+     */
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    /* Check the piomap list to see if there is already an allocated
+     * piomap entry but not in use. If so use that one. Otherwise
+     * allocate a new piomap entry and add it to the piomap list
+     */
+    mapptr = &(pcibr_info->f_piomap);
+
+    s = pcibr_lock(pcibr_soft);
+    for (pcibr_piomap = *mapptr;
+	 pcibr_piomap != NULL;
+	 pcibr_piomap = pcibr_piomap->bp_next) {
+	if (pcibr_piomap->bp_mapsz == 0)
+	    break;
+    }
+
+    if (pcibr_piomap)
+	mapptr = NULL;
+    else {
+	pcibr_unlock(pcibr_soft, s);
+	NEW(pcibr_piomap);
+    }
+
+    pcibr_piomap->bp_dev = pconn_vhdl;
+    pcibr_piomap->bp_slot = pciio_slot;
+    pcibr_piomap->bp_flags = flags;
+    pcibr_piomap->bp_space = space;
+    pcibr_piomap->bp_pciaddr = pci_addr;
+    pcibr_piomap->bp_mapsz = req_size;
+    pcibr_piomap->bp_soft = pcibr_soft;
+    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
+
+    if (mapptr) {
+	s = pcibr_lock(pcibr_soft);
+	maplist = *mapptr;
+	pcibr_piomap->bp_next = maplist;
+	*mapptr = pcibr_piomap;
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+
+    if (pcibr_piomap) {
+	xtalk_piomap =
+	    xtalk_piomap_alloc(xconn_vhdl, 0,
+			       xio_addr,
+			       req_size, req_size_max,
+			       flags & PIOMAP_FLAGS);
+	if (xtalk_piomap) {
+	    pcibr_piomap->bp_xtalk_addr = xio_addr;
+	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
+	} else {
+	    pcibr_piomap->bp_mapsz = 0;
+	    pcibr_piomap = 0;
+	}
+    }
+    return pcibr_piomap;
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
+    pcibr_piomap->bp_xtalk_pio = 0;
+    pcibr_piomap->bp_mapsz = 0;
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
+		  iopaddr_t pci_addr,
+		  size_t req_size)
+{
+    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
+			     pcibr_piomap->bp_xtalk_addr +
+			     pci_addr - pcibr_piomap->bp_pciaddr,
+			     req_size);
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    pciio_space_t space,
+		    iopaddr_t pci_addr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    iopaddr_t               xio_addr;
+
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
+}
+
+/*
+ * PIO Space allocation and management.
+ *      Allocate and Manage the PCI PIO space (mem and io space)
+ *      This routine is pretty simplistic at this time, and
+ *      does pretty trivial management of allocation and freeing..
+ *      The current scheme is prone for fragmentation..
+ *      Change the scheme to use bitmaps.
+ */
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
+		     device_desc_t dev_desc,
+		     pciio_space_t space,
+		     size_t req_size,
+		     size_t alignment)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+
+    iopaddr_t              *pciaddr, *pcilast;
+    iopaddr_t               start_addr;
+    size_t                  align_mask;
+
+    /*
+     * Check for proper alignment
+     */
+    ASSERT(alignment >= NBPP);
+    ASSERT((alignment & (alignment - 1)) == 0);
+
+    align_mask = alignment - 1;
+    s = pcibr_lock(pcibr_soft);
+
+    /*
+     * First look if a previously allocated chunk exists.
+     */
+    if ((piosp = pcibr_info->f_piospace)) {
+	/*
+	 * Look through the list for a right sized free chunk.
+	 */
+	do {
+	    if (piosp->free &&
+		(piosp->space == space) &&
+		(piosp->count >= req_size) &&
+		!(piosp->start & align_mask)) {
+		piosp->free = 0;
+		pcibr_unlock(pcibr_soft, s);
+		return piosp->start;
+	    }
+	    piosp = piosp->next;
+	} while (piosp);
+    }
+    ASSERT(!piosp);
+
+    switch (space) {
+    case PCIIO_SPACE_IO:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
+	break;
+    case PCIIO_SPACE_MEM:
+    case PCIIO_SPACE_MEM32:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
+	break;
+    default:
+	ASSERT(0);
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+
+    start_addr = *pciaddr;
+
+    /*
+     * Align start_addr.
+     */
+    if (start_addr & align_mask)
+	start_addr = (start_addr + align_mask) & ~align_mask;
+
+    if ((start_addr + req_size) > *pcilast) {
+	/*
+	 * If too big a request, reject it.
+	 */
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    *pciaddr = (start_addr + req_size);
+
+    NEW(piosp);
+    piosp->free = 0;
+    piosp->space = space;
+    piosp->start = start_addr;
+    piosp->count = req_size;
+    piosp->next = pcibr_info->f_piospace;
+    pcibr_info->f_piospace = piosp;
+
+    pcibr_unlock(pcibr_soft, s);
+    return start_addr;
+}
+
+/*ARGSUSED */
+void
+pcibr_piospace_free(devfs_handle_t pconn_vhdl,
+		    pciio_space_t space,
+		    iopaddr_t pciaddr,
+		    size_t req_size)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+    char                    name[1024];
+
+    /*
+     * Look through the bridge data structures for the pciio_piospace_t
+     * structure corresponding to  'pciaddr'
+     */
+    s = pcibr_lock(pcibr_soft);
+    piosp = pcibr_info->f_piospace;
+    while (piosp) {
+	/*
+	 * Piospace free can only be for the complete
+	 * chunk and not parts of it..
+	 */
+	if (piosp->start == pciaddr) {
+	    if (piosp->count == req_size)
+		break;
+	    /*
+	     * Improper size passed for freeing..
+	     * Print a message and break;
+	     */
+	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
+	    printk(KERN_WARNING  "pcibr_piospace_free: error");
+	    printk(KERN_WARNING  "Device %s freeing size (0x%lx) different than allocated (0x%lx)",
+					name, req_size, piosp->count);
+	    printk(KERN_WARNING  "Freeing 0x%lx instead", piosp->count);
+	    break;
+	}
+	piosp = piosp->next;
+    }
+
+    if (!piosp) {
+	printk(KERN_WARNING  
+		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
+		pciaddr, req_size);
+	pcibr_unlock(pcibr_soft, s);
+	return;
+    }
+    piosp->free = 1;
+    pcibr_unlock(pcibr_soft, s);
+    return;
+}
+
+/* =====================================================================
+ *    DMA MANAGEMENT
+ *
+ *      The Bridge ASIC provides three methods of doing
+ *      DMA: via a "direct map" register available in
+ *      32-bit PCI space (which selects a contiguous 2G
+ *      address space on some other widget), via
+ *      "direct" addressing via 64-bit PCI space (all
+ *      destination information comes from the PCI
+ *      address, including transfer attributes), and via
+ *      a "mapped" region that allows a bunch of
+ *      different small mappings to be established with
+ *      the PMU.
+ *
+ *      For efficiency, we most prefer to use the 32-bit
+ *      direct mapping facility, since it requires no
+ *      resource allocations. The advantage of using the
+ *      PMU over the 64-bit direct is that single-cycle
+ *      PCI addressing can be used; the advantage of
+ *      using 64-bit direct over PMU addressing is that
+ *      we do not have to allocate entries in the PMU.
+ */
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Direct Map attribute bits.
+ */
+LOCAL iopaddr_t
+pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
+{
+    iopaddr_t               attributes = 0;
+
+    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
+#ifdef LATER
+    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
+#endif
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
+	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
+	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    /* the swap bit is in the address attributes for xbridge */
+    if (pcibr_soft->bs_xbridge) {
+    	if (flags & PCIIO_BYTE_STREAM)
+        	attributes |= PCI64_ATTR_SWAP;
+    	if (flags & PCIIO_WORD_VALUES)
+        	attributes &= ~PCI64_ATTR_SWAP;
+    }
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= PCI64_ATTR_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~PCI64_ATTR_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= PCI64_ATTR_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~PCI64_ATTR_PREC;
+
+    if (flags & PCIBR_VCHAN1)
+	attributes |= PCI64_ATTR_VIRTUAL;
+    if (flags & PCIBR_VCHAN0)
+	attributes &= ~PCI64_ATTR_VIRTUAL;
+
+    return (attributes);
+}
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Address Translation Entry attribute bits.
+ */
+LOCAL bridge_ate_t
+pcibr_flags_to_ate(unsigned flags)
+{
+    bridge_ate_t            attributes;
+
+    /* default if nothing specified:
+     * NOBARRIER
+     * NOPREFETCH
+     * NOPRECISE
+     * COHERENT
+     * Plus the valid bit
+     */
+    attributes = ATE_CO | ATE_V;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~ATE_BAR;		/* no barrier */
+	attributes |= ATE_PREF;		/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= ATE_BAR;		/* barrier bit on */
+	attributes &= ~ATE_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= ATE_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~ATE_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= ATE_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~ATE_PREC;
+
+    return (attributes);
+}
+
+/*ARGSUSED */
+pcibr_dmamap_t
+pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            slot;
+    xwidgetnum_t            xio_port;
+
+    xtalk_dmamap_t          xtalk_dmamap;
+    pcibr_dmamap_t          pcibr_dmamap;
+    int                     ate_count;
+    int                     ate_index;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+#ifdef IRIX
+    NEWf(pcibr_dmamap, flags);
+#else
+    /*
+     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
+     * can be called within an interrupt thread.
+     */
+    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
+#endif
+
+    if (!pcibr_dmamap)
+	return 0;
+
+    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
+				      flags & DMAMAP_FLAGS);
+    if (!xtalk_dmamap) {
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
+#endif
+#ifdef IRIX
+	DEL(pcibr_dmamap);
+#else
+	free_pciio_dmamap(pcibr_dmamap);
+#endif
+	return 0;
+    }
+    xio_port = pcibr_soft->bs_mxid;
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_dmamap->bd_dev = pconn_vhdl;
+    pcibr_dmamap->bd_slot = slot;
+    pcibr_dmamap->bd_soft = pcibr_soft;
+    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
+    pcibr_dmamap->bd_max_size = req_size_max;
+    pcibr_dmamap->bd_xio_port = xio_port;
+
+    if (flags & PCIIO_DMA_A64) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    iopaddr_t               pci_addr;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+	    /* Device is capable of A64 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     */
+
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_pci_addr = pci_addr;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct64\n");
+#endif
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct64\n");
+#endif
+	flags &= ~PCIIO_DMA_A64;
+    }
+    if (flags & PCIIO_FIXED) {
+	/* warning: mappings may fail later,
+	 * if direct32 can't get to the address.
+	 */
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
+	    /* User desires DIRECT A32 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     * Mapping calls may fail if target
+	     * is outside the direct32 range.
+	     */
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct32\n");
+#endif
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
+	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct32\n");
+#endif
+	/* If the user demands FIXED and we can't
+	 * give it to him, fail.
+	 */
+	xtalk_dmamap_free(xtalk_dmamap);
+#ifdef IRIX
+	DEL(pcibr_dmamap);
+#else
+	free_pciio_dmamap(pcibr_dmamap);
+#endif
+	return 0;
+    }
+    /*
+     * Allocate Address Translation Entries from the mapping RAM.
+     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
+     * the maximum number of ATEs is based on the worst-case
+     * scenario, where the requested target is in the
+     * last byte of an ATE; thus, mapping IOPGSIZE+2
+     * does end up requiring three ATEs.
+     */
+    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
+	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
+		     +req_size_max	/* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    } else {	/* assume requested target is page aligned */
+	ate_count = IOPG(req_size_max   /* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    }
+
+    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
+
+    if (ate_index != -1) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
+	    bridge_ate_t            ate_proto;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using PMU\n");
+#endif
+
+	    ate_proto = pcibr_flags_to_ate(flags);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_pci_addr =
+		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
+	    /*
+	     * for xbridge the byte-swap bit == bit 29 of PCI address
+	     */
+	    if (pcibr_soft->bs_xbridge) {
+		    if (flags & PCIIO_BYTE_STREAM)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    /*
+		     * If swap was set in bss_device in pcibr_endian_set()
+		     * we need to change the address bit.
+		     */
+		    if (pcibr_soft->bs_slot[slot].bss_device & 
+							BRIDGE_DEV_SWAP_PMU)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    if (flags & PCIIO_WORD_VALUES)
+			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
+	    }
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
+	    pcibr_dmamap->bd_ate_index = ate_index;
+	    pcibr_dmamap->bd_ate_count = ate_count;
+	    pcibr_dmamap->bd_ate_proto = ate_proto;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (ate_proto & ATE_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
+				!pcibr_soft->bs_xbridge) {
+		bridge_t               *bridge = pcibr_soft->bs_base;
+		volatile unsigned      *cmd_regp;
+		unsigned                cmd_reg;
+		unsigned long           s;
+
+		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
+
+		s = pcibr_lock(pcibr_soft);
+		cmd_regp = &(bridge->
+			     b_type0_cfg_dev[slot].
+			     l[PCI_CFG_COMMAND / 4]);
+		cmd_reg = *cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
+		pcibr_unlock(pcibr_soft, s);
+	    }
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use PMU\n");
+#endif
+	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
+    }
+    /* total failure: sorry, you just can't
+     * get from here to there that way.
+     */
+#if PCIBR_ATE_DEBUG
+    printk("pcibr_dmamap_alloc: complete failure.\n");
+#endif
+    xtalk_dmamap_free(xtalk_dmamap);
+#ifdef IRIX
+    DEL(pcibr_dmamap);
+#else
+    free_pciio_dmamap(pcibr_dmamap);
+#endif
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
+
+    unsigned                flags = pcibr_dmamap->bd_flags;
+
+    /* Make sure that bss_ext_ates_active
+     * is properly kept up to date.
+     */
+
+    if (PCIBR_DMAMAP_BUSY & flags)
+	if (PCIBR_DMAMAP_SSRAM & flags)
+	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
+
+    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
+
+    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
+    }
+    if (pcibr_dmamap->bd_ate_count) {
+	pcibr_ate_free(pcibr_dmamap->bd_soft,
+		       pcibr_dmamap->bd_ate_index,
+		       pcibr_dmamap->bd_ate_count);
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
+    }
+#ifdef IRIX
+    DEL(pcibr_dmamap);
+#else
+    free_pciio_dmamap(pcibr_dmamap);
+#endif
+}
+
+/*
+ * Setup an Address Translation Entry as specified.  Use either the Bridge
+ * internal maps or the external map RAM, as appropriate.
+ */
+LOCAL bridge_ate_p
+pcibr_ate_addr(pcibr_soft_t pcibr_soft,
+	       int ate_index)
+{
+    bridge_t *bridge = pcibr_soft->bs_base;
+
+    return (ate_index < pcibr_soft->bs_int_ate_size)
+	? &(bridge->b_int_ate_ram[ate_index].wr)
+	: &(bridge->b_ext_ate_ram[ate_index]);
+}
+
+/*
+ *    pcibr_addr_xio_to_pci: given a PIO range, hand
+ *      back the corresponding base PCI MEM address;
+ *      this is used to short-circuit DMA requests that
+ *      loop back onto this PCI bus.
+ */
+LOCAL iopaddr_t
+pcibr_addr_xio_to_pci(pcibr_soft_t soft,
+		      iopaddr_t xio_addr,
+		      size_t req_size)
+{
+    iopaddr_t               xio_lim = xio_addr + req_size - 1;
+    iopaddr_t               pci_addr;
+    pciio_slot_t            slot;
+
+    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
+	return pci_addr;
+    }
+    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
+	return pci_addr;
+    }
+    for (slot = 0; slot < 8; ++slot)
+	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
+	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
+	    bridgereg_t             dev;
+
+	    dev = soft->bs_slot[slot].bss_device;
+	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
+	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
+	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
+	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
+	}
+    return 0;
+}
+
+/* We are starting to get more complexity
+ * surrounding writing ATEs, so pull
+ * the writing code into this new function.
+ */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif
+
+LOCAL unsigned
+ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   unsigned *freeze_time_ptr,
+#endif
+	   unsigned *cmd_regs)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+#ifdef LATER
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+#endif
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+    int                     slot;
+
+    unsigned long           s;
+    unsigned                cmd_reg;
+    volatile unsigned      *cmd_lwa;
+    unsigned                cmd_lwd;
+
+    if (!ext_ates)
+	return 0;
+
+    /* Bridge Hardware Bug WAR #484930:
+     * Bridge can't handle updating External ATEs
+     * while DMA is occuring that uses External ATEs,
+     * even if the particular ATEs involved are disjoint.
+     */
+
+    /* need to prevent anyone else from
+     * unfreezing the grant while we
+     * are working; also need to prevent
+     * this thread from being interrupted
+     * to keep PCI grant freeze time
+     * at an absolute minimum.
+     */
+    s = pcibr_lock(pcibr_soft);
+
+#ifdef LATER
+    /* just in case pcibr_dmamap_done was not called */
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+    }
+#endif	/* LATER */
+#if PCIBR_FREEZE_TIME
+    *freeze_time_ptr = get_timestamp();
+#endif
+
+    cmd_lwa = 0;
+    for (slot = 0; slot < 8; ++slot)
+	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+	    cmd_reg = pcibr_soft->
+		bs_slot[slot].
+		bss_cmd_shadow;
+	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
+		cmd_lwa = pcibr_soft->
+		    bs_slot[slot].
+		    bss_cmd_pointer;
+		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
+		cmd_lwa[0] = cmd_lwd;
+	    }
+	    cmd_regs[slot] = cmd_reg;
+	} else
+	    cmd_regs[slot] = 0;
+
+    if (cmd_lwa) {
+	    bridge_t	*bridge = pcibr_soft->bs_base;
+
+	    /* Read the last master bit that has been cleared. This PIO read
+	     * on the PCI bus is to ensure the completion of any DMAs that
+	     * are due to bus requests issued by PCI devices before the
+	     * clearing of master bits.
+	     */
+	    cmd_lwa[0];
+
+	    /* Flush all the write buffers in the bridge */
+	    for (slot = 0; slot < 8; ++slot)
+		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+			    /* Flush the write buffer associated with this
+			     * PCI device which might be using dma map RAM.
+			     */
+			    bridge->b_wr_req_buf[slot].reg;
+		    }
+    }
+    return s;
+}
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+
+LOCAL void
+ate_write(bridge_ate_p ate_ptr,
+	  int ate_count,
+	  bridge_ate_t ate)
+{
+    while (ate_count-- > 0) {
+	*ate_ptr++ = ate;
+	ate += IOPGSIZE;
+    }
+}
+
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+LOCAL void
+ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 int ate_index,
+#if PCIBR_FREEZE_TIME
+	 bridge_ate_t ate,
+	 int ate_total,
+	 unsigned freeze_time_start,
+#endif
+	 unsigned *cmd_regs,
+	 unsigned s)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+    int                     slot;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+
+    unsigned                cmd_reg;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+    static unsigned         max_freeze_time = 0;
+    static unsigned         max_ate_total;
+#endif
+
+    if (!ext_ates)
+	return;
+
+    /* restore cmd regs */
+    for (slot = 0; slot < 8; ++slot)
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
+	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+
+    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
+    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+
+#if PCIBR_FREEZE_TIME
+    freeze_time = get_timestamp() - freeze_time_start;
+
+    if ((max_freeze_time < freeze_time) ||
+	(max_ate_total < ate_total)) {
+	if (max_freeze_time < freeze_time)
+	    max_freeze_time = freeze_time;
+	if (max_ate_total < ate_total)
+	    max_ate_total = ate_total;
+	pcibr_unlock(pcibr_soft, s);
+	printk("%s: pci freeze time %d usec for %d ATEs\n"
+		"\tfirst ate: %R\n",
+		pcibr_soft->bs_name,
+		freeze_time * 1000 / 1250,
+		ate_total,
+		ate, ate_bits);
+    } else
+#endif
+	pcibr_unlock(pcibr_soft, s);
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
+		  paddr_t paddr,
+		  size_t req_size)
+{
+    pcibr_soft_t            pcibr_soft;
+    iopaddr_t               xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    unsigned                flags;
+
+    ASSERT(pcibr_dmamap != NULL);
+    ASSERT(req_size > 0);
+    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    flags = pcibr_dmamap->bd_flags;
+
+    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
+    if (XIO_PACKED(xio_addr)) {
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+    } else
+	xio_port = pcibr_dmamap->bd_xio_port;
+
+    /* If this DMA is to an address that
+     * refers back to this Bridge chip,
+     * reduce it back to the correct
+     * PCI MEM address.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+    } else if (flags & PCIIO_DMA_A64) {
+	/* A64 DMA:
+	 * always use 64-bit direct mapping,
+	 * which always works.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	/* attributes are already bundled up into bd_pci_addr.
+	 */
+	pci_addr = pcibr_dmamap->bd_pci_addr
+	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
+	    | xio_addr;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    pci_addr &= ~PCI64_ATTR_PREF;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct64):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else if (flags & PCIIO_FIXED) {
+	/* A32 direct DMA:
+	 * always use 32-bit direct mapping,
+	 * which may fail.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	if (xio_port != pcibr_soft->bs_dir_xport)
+	    pci_addr = 0;		/* wrong DIDN */
+	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
+	    pci_addr = 0;		/* out of range */
+	else if ((xio_addr + req_size) >
+		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
+	    pci_addr = 0;		/* out of range */
+	else
+	    pci_addr = pcibr_dmamap->bd_pci_addr +
+		xio_addr - pcibr_dmamap->bd_xio_addr;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct32):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+	iopaddr_t               offset = IOPGOFF(xio_addr);
+	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
+	int                     ate_count = IOPG(offset + req_size - 1) + 1;
+
+	int                     ate_index = pcibr_dmamap->bd_ate_index;
+	unsigned                cmd_regs[8];
+	unsigned                s;
+
+#if PCIBR_FREEZE_TIME
+	int                     ate_total = ate_count;
+	unsigned                freeze_time;
+#endif
+
+#if PCIBR_ATE_DEBUG
+	bridge_ate_t            ate_cmp;
+	bridge_ate_p            ate_cptr;
+	unsigned                ate_lo, ate_hi;
+	int                     ate_bad = 0;
+	int                     ate_rbc = 0;
+#endif
+	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	bridge_ate_t            ate;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    ate_proto &= ~ATE_PREF;
+
+	ate = ate_proto
+	    | (xio_port << ATE_TIDSHIFT)
+	    | (xio_addr - offset);
+
+	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
+
+	/* Fill in our mapping registers
+	 * with the appropriate xtalk data,
+	 * and hand back the PCI address.
+	 */
+
+	ASSERT(ate_count > 0);
+	if (ate_count <= pcibr_dmamap->bd_ate_count) {
+		ATE_FREEZE();
+		ATE_WRITE();
+		ATE_THAW();
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	} else {
+		/* The number of ATE's required is greater than the number
+		 * allocated for this map. One way this can happen is if
+		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
+		 * flag, and then when that map is used (right now), the
+		 * target address tells us we really did need to roundup.
+		 * The other possibility is that the map is just plain too
+		 * small to handle the requested target area.
+		 */
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING   "pcibr_dmamap_addr :\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\tate_count 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			paddr, paddr + req_size - 1,
+			ate_count, pcibr_dmamap->bd_ate_count);
+#endif
+		pci_addr = 0;
+	}
+
+    }
+    return pci_addr;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
+		  alenlist_t palenlist,
+		  unsigned flags)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge=NULL;
+
+    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+    int                     inplace = flags & PCIIO_INPLACE;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist;
+    size_t                  length;
+    iopaddr_t               offset;
+    unsigned                direct64;
+    int                     ate_index = 0;
+    int                     ate_count = 0;
+    int                     ate_total = 0;
+    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
+    bridge_ate_t            ate_proto = (bridge_ate_t)0;
+    bridge_ate_t            ate_prev;
+    bridge_ate_t            ate;
+    alenaddr_t              xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    alenaddr_t              new_addr;
+
+    unsigned                cmd_regs[8];
+    unsigned                s = 0;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+#endif
+    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
+							 * with an ATE_FREEZE
+							 */
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
+				       flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
+    if (!direct64) {
+	bridge = pcibr_soft->bs_base;
+	ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	ate_index = pcibr_dmamap->bd_ate_index;
+	ate_proto = pcibr_dmamap->bd_ate_proto;
+	ATE_FREEZE();
+	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
+    }
+    pci_addr = pcibr_dmamap->bd_pci_addr;
+
+    ate_prev = 0;			/* matches no valid ATEs */
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &length, al_flags)) {
+	if (XIO_PACKED(xio_addr)) {
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_dmamap->bd_xio_port;
+
+	if (xio_port == pcibr_soft->bs_xid) {
+	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
+	    if (new_addr == PCI_NOWHERE)
+		goto fail;
+	} else if (direct64) {
+	    new_addr = pci_addr | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Bridge Hardware WAR #482836:
+	     * If the transfer is not cache aligned
+	     * and the Bridge Rev is <= B, force
+	     * prefetch to be off.
+	     */
+	    if (flags & PCIBR_NOPREFETCH)
+		new_addr &= ~PCI64_ATTR_PREF;
+
+	} else {
+	    /* calculate the ate value for
+	     * the first address. If it
+	     * matches the previous
+	     * ATE written (ie. we had
+	     * multiple blocks in the
+	     * same IOPG), then back up
+	     * and reuse that ATE.
+	     *
+	     * We are NOT going to
+	     * aggressively try to
+	     * reuse any other ATEs.
+	     */
+	    offset = IOPGOFF(xio_addr);
+	    ate = ate_proto
+		| (xio_port << ATE_TIDSHIFT)
+		| (xio_addr - offset);
+	    if (ate == ate_prev) {
+#if PCIBR_ATE_DEBUG
+		printk("pcibr_dmamap_list: ATE share\n");
+#endif
+		ate_ptr--;
+		ate_index--;
+		pci_addr -= IOPGSIZE;
+	    }
+	    new_addr = pci_addr + offset;
+
+	    /* Fill in the hardware ATEs
+	     * that contain this block.
+	     */
+	    ate_count = IOPG(offset + length - 1) + 1;
+	    ate_total += ate_count;
+
+	    /* Ensure that this map contains enough ATE's */
+	    if (ate_total > pcibr_dmamap->bd_ate_count) {
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING   "pcibr_dmamap_list :\n"
+			"\twanted xio_addr [0x%x..0x%x]\n"
+			"\tate_total 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			xio_addr, xio_addr + length - 1,
+			ate_total, pcibr_dmamap->bd_ate_count);
+#endif
+		goto fail;
+	    }
+
+	    ATE_WRITE();
+
+	    ate_index += ate_count;
+	    ate_ptr += ate_count;
+
+	    ate_count <<= IOPFNSHIFT;
+	    ate += ate_count;
+	    pci_addr += ate_count;
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &new_addr, &length, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				new_addr, length, al_flags))
+		goto fail;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+
+
+    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
+     * changes that ATE_FREEZE has done to implement the external SSRAM
+     * bug workaround.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    return pciio_alenlist;
+
+  fail:
+    /* There are various points of failure after doing an ATE_FREEZE
+     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
+     * The decision to do an ATE_THAW needs to be based on whether a
+     * an ATE_FREEZE was done before.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;
+    }
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
+{
+    /*
+     * We could go through and invalidate ATEs here;
+     * for performance reasons, we don't.
+     * We also don't enforce the strict alternation
+     * between _addr/_list and _done, but Hub does.
+     */
+
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
+    }
+
+    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+}
+
+
+/*
+ * For each bridge, the DIR_OFF value in the Direct Mapping Register
+ * determines the PCI to Crosstalk memory mapping to be used for all
+ * 32-bit Direct Mapping memory accesses. This mapping can be to any
+ * node in the system. This function will return that compact node id.
+ */
+
+/*ARGSUSED */
+cnodeid_t
+pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
+{
+
+	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
+	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    paddr_t paddr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+
+    xwidgetnum_t            xio_port;
+    iopaddr_t               xio_addr;
+    iopaddr_t               pci_addr;
+
+    int                     have_rrbs;
+    int                     min_rrbs;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
+				   flags & DMAMAP_FLAGS);
+
+    if (!xio_addr) {
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+	return 0;
+    }
+    /*
+     * find which XIO port this goes to.
+     */
+    if (XIO_PACKED(xio_addr)) {
+	if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	    return 0;
+	}
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+
+    } else
+	xio_port = pcibr_soft->bs_mxid;
+
+    /*
+     * If this DMA comes back to us,
+     * return the PCI MEM address on
+     * which it would land, or NULL
+     * if the target is something
+     * on bridge other than PCI MEM.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+	return pci_addr;
+    }
+    /* If the caller can use A64, try to
+     * satisfy the request with the 64-bit
+     * direct map. This can fail if the
+     * configuration bits in Device(x)
+     * conflict with our flags.
+     */
+
+    if (flags & PCIIO_DMA_A64) {
+	pci_addr = slotp->bss_d64_base;
+	if (!(flags & PCIBR_VCHAN1))
+	    flags |= PCIBR_VCHAN0;
+	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+#if DEBUG && PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr);
+#endif
+	    return (pci_addr);
+	}
+	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_addr;
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n"
+			"\tnew flags: 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr, (uint64_t) flags);
+#endif
+	    return (pci_addr);
+	}
+	/* our flags conflict with Device(x).
+	 */
+	flags = flags
+	    & ~PCIIO_DMA_A64
+	    & ~PCIBR_VCHAN0
+	    ;
+
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n"
+		"\tUnable to set Device(x) bits for Direct-64\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+    }
+    /* Try to satisfy the request with the 32-bit direct
+     * map. This can fail if the configuration bits in
+     * Device(x) conflict with our flags, or if the
+     * target address is outside where DIR_OFF points.
+     */
+    {
+	size_t                  map_size = 1ULL << 31;
+	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
+	iopaddr_t               offset = xio_addr - xio_base;
+	iopaddr_t               endoff = req_size + offset;
+
+	if ((req_size > map_size) ||
+	    (xio_addr < xio_base) ||
+	    (xio_port != pcibr_soft->bs_dir_xport) ||
+	    (endoff > map_size)) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\txio region outside direct32 target\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	} else {
+	    pci_addr = slotp->bss_d32_base;
+	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
+		(flags == slotp->bss_d32_flags)) {
+
+		pci_addr |= offset;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tmapped via direct32 offset 0x%x\n"
+			"\twill DMA via pci addr 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, offset, pci_addr);
+#endif
+		return (pci_addr);
+	    }
+	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
+
+		pci_addr = PCI32_DIRECT_BASE;
+		slotp->bss_d32_flags = flags;
+		slotp->bss_d32_base = pci_addr;
+		pci_addr |= offset;
+
+		/* Make sure we have an RRB (or two).
+		 */
+		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		    if (have_rrbs < 2) {
+			if (slotp->bss_device & BRIDGE_DEV_PREF)
+			    min_rrbs = 2;
+			else
+			    min_rrbs = 1;
+			if (have_rrbs < min_rrbs)
+			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		    }
+		}
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+		if (xio_addr != 0x20000000)
+#endif
+		    printk("pcibr_dmatrans_addr:\n"
+			    "\tpciio connection point %v\n"
+			    "\txtalk connection point %v\n"
+			    "\twanted paddr [0x%x..0x%x]\n"
+			    "\txtalk_dmatrans_addr returned 0x%x\n"
+			    "\tmapped via direct32 offset 0x%x\n"
+			    "\twill DMA via pci addr 0x%x\n"
+			    "\tnew flags: 0x%x\n",
+			    pconn_vhdl, xconn_vhdl,
+			    paddr, paddr + req_size - 1,
+			    xio_addr, offset, pci_addr, (uint64_t) flags);
+#endif
+		return (pci_addr);
+	    }
+	    /* our flags conflict with Device(x).
+	     */
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\tUnable to set Device(x) bits for Direct-32\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	}
+    }
+
+#if PCIBR_DMA_DEBUG
+    printk("pcibr_dmatrans_addr:\n"
+	    "\tpciio connection point %v\n"
+	    "\txtalk connection point %v\n"
+	    "\twanted paddr [0x%x..0x%x]\n"
+	    "\txtalk_dmatrans_addr returned 0x%x\n"
+	    "\tno acceptable PCI address found or constructable\n",
+	    pconn_vhdl, xconn_vhdl,
+	    paddr, paddr + req_size - 1,
+	    xio_addr);
+#endif
+
+    return 0;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    alenlist_t palenlist,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+    xwidgetnum_t            xio_port;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist = 0;
+
+    int                     inplace;
+    unsigned                direct64;
+    unsigned                al_flags;
+
+    iopaddr_t               xio_base;
+    alenaddr_t              xio_addr;
+    size_t                  xio_size;
+
+    size_t                  map_size;
+    iopaddr_t               pci_base;
+    alenaddr_t              pci_addr;
+
+    unsigned                relbits = 0;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    inplace = flags & PCIIO_INPLACE;
+    direct64 = flags & PCIIO_DMA_A64;
+    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+
+    if (direct64) {
+	map_size = 1ull << 48;
+	xio_base = 0;
+	pci_base = slotp->bss_d64_base;
+	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D64_BITS;
+	    pci_base =
+		pcibr_flags_to_d64(flags, pcibr_soft);
+	}
+    } else {
+	xio_base = pcibr_soft->bs_dir_xbase;
+	map_size = 1ull << 31;
+	pci_base = slotp->bss_d32_base;
+	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
+	    (flags == slotp->bss_d32_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D32_BITS;
+	    pci_base = PCI32_DIRECT_BASE;
+	}
+    }
+
+    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
+					 flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &xio_size, al_flags)) {
+
+	/*
+	 * find which XIO port this goes to.
+	 */
+	if (XIO_PACKED(xio_addr)) {
+	    if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr);
+#endif
+		return 0;
+	    }
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_soft->bs_mxid;
+
+	/*
+	 * If this DMA comes back to us,
+	 * return the PCI MEM address on
+	 * which it would land, or NULL
+	 * if the target is something
+	 * on bridge other than PCI MEM.
+	 */
+	if (xio_port == pcibr_soft->bs_xid) {
+	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
+	    if ( (pci_addr == (alenaddr_t)NULL) )
+		goto fail;
+	} else if (direct64) {
+	    ASSERT(xio_port != 0);
+	    pci_addr = pci_base | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+	} else {
+	    iopaddr_t               offset = xio_addr - xio_base;
+	    iopaddr_t               endoff = xio_size + offset;
+
+	    if ((xio_size > map_size) ||
+		(xio_addr < xio_base) ||
+		(xio_port != pcibr_soft->bs_dir_xport) ||
+		(endoff > map_size))
+		goto fail;
+
+	    pci_addr = pci_base + (xio_addr - xio_base);
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &pci_addr, &xio_size, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				pci_addr, xio_size, al_flags))
+		goto fail;
+	}
+    }
+
+    if (relbits) {
+	if (direct64) {
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_base;
+	} else {
+	    slotp->bss_d32_flags = flags;
+	    slotp->bss_d32_base = pci_base;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+    return pciio_alenlist;
+
+  fail:
+    if (relbits)
+	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+void
+pcibr_dmamap_drain(pcibr_dmamap_t map)
+{
+    xtalk_dmamap_drain(map->bd_xtalk);
+}
+
+void
+pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
+		    paddr_t paddr,
+		    size_t bytes)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
+}
+
+void
+pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
+		    alenlist_t list)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmalist_drain(xconn_vhdl, list);
+}
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+iopaddr_t
+pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
+{
+    return (pcibr_dmamap->bd_pci_addr);
+}
+
+/*
+ *	There are end cases where a deadlock can occur if interrupt 
+ *	processing completes and the Bridge b_int_status bit is still set.
+ *
+ *	One scenerio is if a second PCI interrupt occurs within 60ns of
+ *	the previous interrupt being cleared. In this case the Bridge
+ *	does not detect the transition, the Bridge b_int_status bit
+ *	remains set, and because no transition was detected no interrupt
+ *	packet is sent to the Hub/Heart.
+ *
+ *	A second scenerio is possible when a b_int_status bit is being
+ *	shared by multiple devices:
+ *						Device #1 generates interrupt
+ *						Bridge b_int_status bit set
+ *						Device #2 generates interrupt
+ *		interrupt processing begins
+ *		  ISR for device #1 runs and
+ *			clears interrupt
+ *						Device #1 generates interrupt
+ *		  ISR for device #2 runs and
+ *			clears interrupt
+ *						(b_int_status bit still set)
+ *		interrupt processing completes
+ *		  
+ *	Interrupt processing is now complete, but an interrupt is still
+ *	outstanding for Device #1. But because there was no transition of
+ *	the b_int_status bit, no interrupt packet will be generated and
+ *	a deadlock will occur.
+ *
+ *	To avoid these deadlock situations, this function is used
+ *	to check if a specific Bridge b_int_status bit is set, and if so,
+ *	cause the setting of the corresponding interrupt bit.
+ *
+ *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
+ *	Interrupt register.
+ */
+void
+pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
+{
+	unsigned	bit;
+	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
+	bridge_t       *bridge = pcibr_soft->bs_base;
+	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
+
+	bit = wrap->iw_intr;
+
+	if (pcibr_soft->bs_xbridge) {
+	    bridge->b_force_pin[bit].intr = 1;
+	} else if ((1 << bit) & *wrap->iw_stat) {
+	    cpuid_t	    cpu;
+	    unsigned        intr_bit;
+	    xtalk_intr_t    xtalk_intr =
+				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
+
+	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
+	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
+#endif
+	}
+}
+
+/* =====================================================================
+ *    INTERRUPT MANAGEMENT
+ */
+
+static unsigned
+pcibr_intr_bits(pciio_info_t info,
+		pciio_intr_line_t lines)
+{
+    pciio_slot_t            slot = pciio_info_slot_get(info);
+    unsigned		    bbits = 0;
+
+    /*
+     * Currently favored mapping from PCI
+     * slot number and INTA/B/C/D to Bridge
+     * PCI Interrupt Bit Number:
+     *
+     *     SLOT     A B C D
+     *      0       0 4 0 4
+     *      1       1 5 1 5
+     *      2       2 6 2 6
+     *      3       3 7 3 7
+     *      4       4 0 4 0
+     *      5       5 1 5 1
+     *      6       6 2 6 2
+     *      7       7 3 7 3
+     */
+
+    if (slot < 8) {
+	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
+	    bbits |= 1 << slot;
+	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
+	    bbits |= 1 << (slot ^ 4);
+    }
+    return bbits;
+}
+
+
+/*ARGSUSED */
+pcibr_intr_t
+pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
+		 device_desc_t dev_desc,
+		 pciio_intr_line_t lines,
+		 devfs_handle_t owner_dev)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     is_threaded = 0;
+    int                     thread_swlevel;
+
+    xtalk_intr_t           *xtalk_intr_p;
+    pcibr_intr_t           *pcibr_intr_p;
+    pcibr_intr_list_t      *intr_list_p;
+
+    unsigned                pcibr_int_bits;
+    unsigned                pcibr_int_bit;
+    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
+    hub_intr_t		    hub_intr;
+    pcibr_intr_t            pcibr_intr;
+    pcibr_intr_list_t       intr_entry;
+    pcibr_intr_list_t       intr_list;
+    bridgereg_t             int_dev;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_alloc\n"
+	    "%v:%s%s%s%s%s\n",
+	    owner_dev, pconn_vhdl,
+	    !(lines & 15) ? " No INTs?" : "",
+	    lines & 1 ? " INTA" : "",
+	    lines & 2 ? " INTB" : "",
+	    lines & 4 ? " INTC" : "",
+	    lines & 8 ? " INTD" : "");
+#endif
+
+    NEW(pcibr_intr);
+    if (!pcibr_intr)
+	return NULL;
+
+    if (dev_desc) {
+	cpuid_t intr_target_from_desc(device_desc_t, int);
+    } else {
+	extern int default_intr_pri;
+
+	is_threaded = 1; /* PCI interrupts are threaded, by default */
+	thread_swlevel = default_intr_pri;
+    }
+
+    pcibr_intr->bi_dev = pconn_vhdl;
+    pcibr_intr->bi_lines = lines;
+    pcibr_intr->bi_soft = pcibr_soft;
+    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
+    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
+    pcibr_intr->bi_mustruncpu = CPU_NONE;
+    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
+
+    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
+
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+#if DEBUG && INTR_DEBUG
+    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
+#endif 
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    xtalk_intr = *xtalk_intr_p;
+
+	    if (xtalk_intr == NULL) {
+		/*
+		 * This xtalk_intr_alloc is constrained for two reasons:
+		 * 1) Normal interrupts and error interrupts need to be delivered
+		 *    through a single xtalk target widget so that there aren't any
+		 *    ordering problems with DMA, completion interrupts, and error
+		 *    interrupts. (Use of xconn_vhdl forces this.)
+		 *
+		 * 2) On IP35, addressing constraints on IP35 and Bridge force
+		 *    us to use a single PI number for all interrupts from a
+		 *    single Bridge. (IP35-specific code forces this, and we
+		 *    verify in pcibr_setwidint.)
+		 */
+
+		/*
+		 * All code dealing with threaded PCI interrupt handlers
+		 * is located at the pcibr level. Because of this,
+		 * we always want the lower layers (hub/heart_intr_alloc, 
+		 * intr_level_connect) to treat us as non-threaded so we
+		 * don't set up a duplicate threaded environment. We make
+		 * this happen by calling a special xtalk interface.
+		 */
+		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
+			owner_dev);
+#if DEBUG && INTR_DEBUG
+		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
+#endif
+
+		/* both an assert and a runtime check on this:
+		 * we need to check in non-DEBUG kernels, and
+		 * the ASSERT gets us more information when
+		 * we use DEBUG kernels.
+		 */
+		ASSERT(xtalk_intr != NULL);
+		if (xtalk_intr == NULL) {
+		    /* it is quite possible that our
+		     * xtalk_intr_alloc failed because
+		     * someone else got there first,
+		     * and we can find their results
+		     * in xtalk_intr_p.
+		     */
+		    if (!*xtalk_intr_p) {
+#ifdef SUPPORT_PRINTING_V_FORMAT
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
+				xconn_vhdl);
+#else
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc 0x%p: unable to get xtalk interrupt resources",
+				(void *)xconn_vhdl);
+#endif
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
+		    /*
+		     * now tell the bridge which slot is
+		     * using this interrupt line.
+		     */
+		    int_dev = bridge->b_int_device;
+		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
+		    bridge->b_int_device = int_dev;	/* XXXMP */
+
+#if DEBUG && INTR_DEBUG
+		    printk("%v: bridge intr bit %d clears my wrb\n",
+			    pconn_vhdl, pcibr_int_bit);
+#endif
+		} else {
+		    /* someone else got one allocated first;
+		     * free the one we just created, and
+		     * retrieve the one they allocated.
+		     */
+		    xtalk_intr_free(xtalk_intr);
+		    xtalk_intr = *xtalk_intr_p;
+#if PARANOID
+		    /* once xtalk_intr is set, we never clear it,
+		     * so if the CAS fails above, this condition
+		     * can "never happen" ...
+		     */
+		    if (!xtalk_intr) {
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
+				xconn_vhdl);
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+#endif
+		}
+	    }
+
+	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
+
+	    NEW(intr_entry);
+	    intr_entry->il_next = NULL;
+	    intr_entry->il_intr = pcibr_intr;
+	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
+	    intr_list_p = 
+		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+#if DEBUG && INTR_DEBUG
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#else
+	    printk("%v: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#endif
+#endif
+
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the first interrupt on this bridge bit.
+		 */
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list = *intr_list_p;
+	    pcibr_intr_p = &intr_list->il_intr;
+	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		/* first entry on list was erased,
+		 * and we replaced it, so we
+		 * don't need our intr_entry.
+		 */
+		DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list_p = &intr_list->il_next;
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the new second interrupt on this bit.
+		 */
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    while (1) {
+		pcibr_intr_p = &intr_list->il_intr;
+		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		    /* an entry on list was erased,
+		     * and we replaced it, so we
+		     * don't need our intr_entry.
+		     */
+		    DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		intr_list_p = &intr_list->il_next;
+		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		    /* entry appended to share list
+		     */
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		/* step to next record in chain
+		 */
+		intr_list = *intr_list_p;
+	    }
+	}
+    }
+
+#if DEBUG && INTR_DEBUG
+    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
+#endif
+    hub_intr = (hub_intr_t)xtalk_intr;
+    pcibr_intr->bi_irq = hub_intr->i_bit;
+    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
+    return pcibr_intr;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_free(pcibr_intr_t pcibr_intr)
+{
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bit;
+    pcibr_intr_list_t       intr_list;
+    int			    intr_shared;
+    xtalk_intr_t	    *xtalk_intrp;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    for (intr_list = 
+		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+		 intr_list != NULL;
+		 intr_list = intr_list->il_next)
+		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
+					 pcibr_intr, 
+					 NULL)) {
+#if DEBUG && INTR_DEBUG
+		    printk("%s: cleared a handler from bit %d\n",
+			    pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+		}
+	    /* If this interrupt line is not being shared between multiple
+	     * devices release the xtalk interrupt resources.
+	     */
+	    intr_shared = 
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
+	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    if ((!intr_shared) && (*xtalk_intrp)) {
+
+		bridge_t 	*bridge = pcibr_soft->bs_base;
+		bridgereg_t	int_dev;
+
+		xtalk_intr_free(*xtalk_intrp);
+		*xtalk_intrp = 0;
+
+		/* Clear the PCI device interrupt to bridge interrupt pin
+		 * mapping.
+		 */
+		int_dev = bridge->b_int_device;
+		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		bridge->b_int_device = int_dev;
+
+	    }
+	}
+    }
+    DEL(pcibr_intr);
+}
+
+LOCAL void
+pcibr_setpciint(xtalk_intr_t xtalk_intr)
+{
+    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
+    bridgereg_t            *int_addr = (bridgereg_t *)
+    xtalk_intr_sfarg_get(xtalk_intr);
+
+#ifdef CONFIG_IA64_SGI_SN2
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 26)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+#elif CONFIG_IA64_SGI_SN1
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+#endif
+}
+
+/*ARGSUSED */
+int
+pcibr_intr_connect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    if (pcibr_intr == NULL)
+	return -1;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_connect\n",
+	    pcibr_intr->bi_dev);
+#endif
+
+    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_t            xtalk_intr;
+
+	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    /*
+	     * If this interrupt line is being shared and the connect has
+	     * already been done, no need to do it again.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
+		continue;
+
+
+	    /*
+	     * Use the pcibr wrapper function to handle all Bridge interrupts
+	     * regardless of whether the interrupt line is shared or not.
+	     */
+	    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint,
+			       (void *)&(bridge->b_int_addr[pcibr_int_bit].addr));
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%v bridge bit %d wrapper connected\n",
+		    pcibr_intr->bi_dev, pcibr_int_bit);
+#endif
+	}
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable |= pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    /* Stop calling the function. Now.
+     */
+    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and disconnect the interrupt.
+     */
+
+    /* don't disable interrupts for lines that
+     * are shared between devices.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
+	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
+	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
+    if (!pcibr_int_bits)
+	return;
+
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable &= ~pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    /* if the interrupt line is now shared,
+	     * do not disconnect it.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
+		pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+
+	    /* if we are sharing the interrupt line,
+	     * connect us up; this closes the hole
+	     * where the another pcibr_intr_alloc()
+	     * was in progress as we disconnected.
+	     */
+	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
+			       (xtalk_intr_setfunc_t)pcibr_setpciint,
+			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr));
+	}
+}
+
+/*ARGSUSED */
+devfs_handle_t
+pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit))
+	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+    return 0;
+}
+
+/* =====================================================================
+ *    INTERRUPT HANDLING
+ */
+LOCAL void
+pcibr_clearwidint(bridge_t *bridge)
+{
+    bridge->b_wid_int_upper = 0;
+    bridge->b_wid_int_lower = 0;
+}
+
+LOCAL void
+pcibr_setwidint(xtalk_intr_t intr)
+{
+    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
+    iopaddr_t               addr = xtalk_intr_addr_get(intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
+    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
+    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
+
+    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
+
+    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+			       XTALK_ADDR_TO_UPPER(addr));
+    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+
+    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
+    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
+
+    /* Verify that all interrupts from this Bridge are using a single PI */
+    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
+	/*
+	 * Once set, these registers shouldn't change; they should
+	 * be set multiple times with the same values.
+	 *
+	 * If we're attempting to change these registers, it means
+	 * that our heuristics for allocating interrupts in a way
+	 * appropriate for IP35 have failed, and the admin needs to
+	 * explicitly direct some interrupts (or we need to make the
+	 * heuristics more clever).
+	 *
+	 * In practice, we hope this doesn't happen very often, if
+	 * at all.
+	 */
+	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
+	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
+		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
+		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
+		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
+		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
+			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
+			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
+		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
+	}
+    }
+
+    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
+    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
+    bridge->b_int_host_err = vect;
+}
+
+/*
+ * pcibr_intr_preset: called during mlreset time
+ * if the platform specific code needs to route
+ * one of the Bridge's xtalk interrupts before the
+ * xtalk infrastructure is available.
+ */
+void
+pcibr_xintr_preset(void *which_widget,
+		   int which_widget_intr,
+		   xwidgetnum_t targ,
+		   iopaddr_t addr,
+		   xtalk_intr_vector_t vect)
+{
+    bridge_t               *bridge = (bridge_t *) which_widget;
+
+    if (which_widget_intr == -1) {
+	/* bridge widget error interrupt */
+	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+				   XTALK_ADDR_TO_UPPER(addr));
+	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+	bridge->b_int_host_err = vect;
+
+	/* turn on all interrupts except
+	 * the PCI interrupt requests,
+	 * at least at heart.
+	 */
+	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
+
+    } else {
+	/* routing a PCI device interrupt.
+	 * targ and low 38 bits of addr must
+	 * be the same as the already set
+	 * value for the widget error interrupt.
+	 */
+	bridge->b_int_addr[which_widget_intr].addr =
+	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+	     (BRIDGE_INT_ADDR_FLD & vect));
+	/*
+	 * now bridge can let it through;
+	 * NB: still should be blocked at
+	 * xtalk provider end, until the service
+	 * function is set.
+	 */
+	bridge->b_int_enable |= 1 << vect;
+    }
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+}
+
+
+/*
+ * pcibr_intr_func()
+ *
+ * This is the pcibr interrupt "wrapper" function that is called,
+ * in interrupt context, to initiate the interrupt handler(s) registered
+ * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
+ * handlers will be called directly, and threaded handlers will have their 
+ * thread woken up.
+ */
+void
+pcibr_intr_func(intr_arg_t arg)
+{
+    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
+    reg_p                   wrbf;
+    pcibr_intr_t            intr;
+    pcibr_intr_list_t       list;
+    int                     clearit;
+    int			    do_nonthreaded = 1;
+    int			    is_threaded = 0;
+    int			    x = 0;
+
+	/*
+	 * If any handler is still running from a previous interrupt
+	 * just return. If there's a need to call the handler(s) again,
+	 * another interrupt will be generated either by the device or by
+	 * pcibr_force_interrupt().
+	 */
+
+	if (wrap->iw_hdlrcnt) {
+		return;
+	}
+
+    /*
+     * Call all interrupt handlers registered.
+     * First, the pcibr_intrd threads for any threaded handlers will be
+     * awoken, then any non-threaded handlers will be called sequentially.
+     */
+	
+	clearit = 1;
+	while (do_nonthreaded) {
+	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
+		if ((intr = list->il_intr) &&
+		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
+
+		/*
+		 * This device may have initiated write
+		 * requests since the bridge last saw
+		 * an edge on this interrupt input; flushing
+		 * the buffer prior to invoking the handler
+		 * should help but may not be sufficient if we 
+		 * get more requests after the flush, followed
+		 * by the card deciding it wants service, before
+		 * the interrupt handler checks to see if things need
+		 * to be done.
+		 *
+		 * There is a similar race condition if
+		 * an interrupt handler loops around and
+		 * notices further service is required.
+		 * Perhaps we need to have an explicit
+		 * call that interrupt handlers need to
+		 * do between noticing that DMA to memory
+		 * has completed, but before observing the
+		 * contents of memory?
+		 */
+
+			if ((do_nonthreaded) && (!is_threaded)) {
+			/* Non-threaded. 
+			 * Call the interrupt handler at interrupt level
+			 */
+
+			/* Only need to flush write buffers if sharing */
+
+			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
+			    if ((x = *wrbf))	/* write request buffer flush */
+#ifdef SUPPORT_PRINTING_V_FORMAT
+				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
+				    "write buffer flush failed, wrbf=0x%x\n", 
+				    list->il_intr->bi_dev, wrbf);
+#else
+				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
+				    "write buffer flush failed, wrbf=0x%lx\n", 
+				    (void *)list->il_intr->bi_dev, (long) wrbf);
+#endif
+			}
+		    }
+
+		    clearit = 0;
+		}
+	    }
+
+		do_nonthreaded = 0;
+		/*
+		 * If the non-threaded handler was the last to complete,
+		 * (i.e., no threaded handlers still running) force an
+		 * interrupt to avoid a potential deadlock situation.
+		 */
+		if (wrap->iw_hdlrcnt == 0) {
+			pcibr_force_interrupt(wrap);
+		}
+	}
+
+	/* If there were no handlers,
+	 * disable the interrupt and return.
+	 * It will get enabled again after
+	 * a handler is connected.
+	 * If we don't do this, we would
+	 * sit here and spin through the
+	 * list forever.
+	 */
+	if (clearit) {
+	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+	    bridgereg_t             b_int_enable;
+	    bridgereg_t		    mask = 1 << wrap->iw_intr;
+	    unsigned long           s;
+
+	    s = pcibr_lock(pcibr_soft);
+	    b_int_enable = bridge->b_int_enable;
+	    b_int_enable &= ~mask;
+	    bridge->b_int_enable = b_int_enable;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	    pcibr_unlock(pcibr_soft, s);
+	    return;
+	}
+}
+
+/* =====================================================================
+ *    CONFIGURATION MANAGEMENT
+ */
+/*ARGSUSED */
+void
+pcibr_provider_startup(devfs_handle_t pcibr)
+{
+}
+
+/*ARGSUSED */
+void
+pcibr_provider_shutdown(devfs_handle_t pcibr)
+{
+}
+
+int
+pcibr_reset(devfs_handle_t conn)
+{
+    pciio_info_t            pciio_info = pciio_info_get(conn);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             ctlreg;
+    unsigned                cfgctl[8];
+    unsigned long           s;
+    int                     f, nf;
+    pcibr_info_h            pcibr_infoh;
+    pcibr_info_t            pcibr_info;
+    int                     win;
+
+    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
+	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
+    }
+    if (pciio_slot < 4) {
+	s = pcibr_lock(pcibr_soft);
+	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
+	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
+
+	ctlreg = bridge->b_wid_control;
+	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
+	/* XXX delay? */
+	bridge->b_wid_control = ctlreg;
+	/* XXX delay? */
+
+	for (f = 0; f < nf; ++f)
+	    if ((pcibr_info = pcibr_infoh[f]))
+		for (win = 0; win < 6; ++win)
+		    if (pcibr_info->f_window[win].w_base != 0)
+			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
+			    pcibr_info->f_window[win].w_base;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
+	pcibr_unlock(pcibr_soft, s);
+
+	return 0;
+    }
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    printk(KERN_WARNING   "%v: pcibr_reset unimplemented for slot %d\n",
+	    conn, pciio_slot);
+#endif
+    return -1;
+}
+
+pciio_endian_t
+pcibr_endian_set(devfs_handle_t pconn_vhdl,
+		 pciio_endian_t device_end,
+		 pciio_endian_t desired_end)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             devreg;
+    unsigned long           s;
+
+    /*
+     * Bridge supports hardware swapping; so we can always
+     * arrange for the caller's desired endianness.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_end != desired_end)
+	devreg |= BRIDGE_DEV_SWAP_BITS;
+    else
+	devreg &= ~BRIDGE_DEV_SWAP_BITS;
+
+    /* NOTE- if we ever put SWAP bits
+     * onto the disabled list, we will
+     * have to change the logic here.
+     */
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
+#endif
+
+    return desired_end;
+}
+
+/* This (re)sets the GBR and REALTIME bits and also keeps track of how
+ * many sets are outstanding. Reset succeeds only if the number of outstanding
+ * sets == 1.
+ */
+int
+pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
+			pciio_slot_t pciio_slot,
+			pciio_priority_t device_prio)
+{
+    unsigned long           s;
+    int                    *counter;
+    bridgereg_t             rtbits = 0;
+    bridgereg_t             devreg;
+    int                     rc = PRIO_SUCCESS;
+
+    /* in dual-slot configurations, the host and the
+     * guest have separate DMA resources, so they
+     * have separate requirements for priority bits.
+     */
+
+    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
+
+    /*
+     * Bridge supports PCI notions of LOW and HIGH priority
+     * arbitration rings via a "REAL_TIME" bit in the per-device
+     * Bridge register. The "GBR" bit controls access to the GBR
+     * ring on the xbow. These two bits are (re)set together.
+     *
+     * XXX- Bug in Rev B Bridge Si:
+     * Symptom: Prefetcher starts operating incorrectly. This happens
+     * due to corruption of the address storage ram in the prefetcher
+     * when a non-real time PCI request is pulled and a real-time one is
+     * put in it's place. Workaround: Use only a single arbitration ring
+     * on PCI bus. GBR and RR can still be uniquely used per
+     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
+     */
+
+    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
+	rtbits |= BRIDGE_DEV_RT;
+
+    /* NOTE- if we ever put DEV_RT or DEV_GBR on
+     * the disabled list, we will have to take
+     * it into account here.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_prio == PCI_PRIO_HIGH) {
+	if ((++*counter == 1)) {
+	    if (rtbits)
+		devreg |= rtbits;
+	    else
+		rc = PRIO_FAIL;
+	}
+    } else if (device_prio == PCI_PRIO_LOW) {
+	if (*counter <= 0)
+	    rc = PRIO_FAIL;
+	else if (--*counter == 0)
+	    if (rtbits)
+		devreg &= ~rtbits;
+    }
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+    return rc;
+}
+
+pciio_priority_t
+pcibr_priority_set(devfs_handle_t pconn_vhdl,
+		   pciio_priority_t device_prio)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
+
+    return device_prio;
+}
+
+/*
+ * Interfaces to allow special (e.g. SGI) drivers to set/clear
+ * Bridge-specific device flags.  Many flags are modified through
+ * PCI-generic interfaces; we don't allow them to be directly
+ * manipulated here.  Only flags that at this point seem pretty
+ * Bridge-specific can be set through these special interfaces.
+ * We may add more flags as the need arises, or remove flags and
+ * create PCI-generic interfaces as the need arises.
+ *
+ * Returns 0 on failure, 1 on success
+ */
+int
+pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
+		       pcibr_device_flags_t flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             set = 0;
+    bridgereg_t             clr = 0;
+
+    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_PMU_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_PMU_WRGA_EN;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_DIR_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_DIR_WRGA_EN;
+
+    if (flags & PCIBR_PREFETCH)
+	set |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	clr |= BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	set |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	clr |= BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	set |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	clr |= BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	set |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	clr |= BRIDGE_DEV_DEV_SIZE;
+
+    if (set || clr) {
+	bridgereg_t             devreg;
+	unsigned long           s;
+
+	s = pcibr_lock(pcibr_soft);
+	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+	devreg = (devreg & ~clr) | set;
+	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+
+	    bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	}
+	pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
+#endif
+    }
+    return (1);
+}
+
+#ifdef LITTLE_ENDIAN
+/*
+ * on sn-ia we need to twiddle the the addresses going out
+ * the pci bus because we use the unswizzled synergy space
+ * (the alternative is to use the swizzled synergy space
+ * and byte swap the data)
+ */
+#define	CB(b,r)	(((volatile uint8_t *) b)[((r)^4)])
+#define	CS(b,r)	(((volatile uint16_t *) b)[((r^4)/2)])
+#define	CW(b,r)	(((volatile uint32_t *) b)[((r^4)/4)])
+#else
+#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
+#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
+#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
+#endif /* LITTLE_ENDIAN */
+
+
+LOCAL                   cfg_p
+pcibr_config_addr(devfs_handle_t conn,
+		  unsigned reg)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_slot_t            pciio_slot;
+    pciio_function_t        pciio_func;
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    cfg_p                   cfgbase = (cfg_p)0;
+
+    pcibr_info = pcibr_info_get(conn);
+
+    pciio_slot = pcibr_info->f_slot;
+    if (pciio_slot == PCIIO_SLOT_NONE)
+	pciio_slot = PCI_TYPE1_SLOT(reg);
+
+    pciio_func = pcibr_info->f_func;
+    if (pciio_func == PCIIO_FUNC_NONE)
+	pciio_func = PCI_TYPE1_FUNC(reg);
+
+    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    bridge = pcibr_soft->bs_base;
+
+    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
+
+    return cfgbase;
+}
+
+uint64_t
+pcibr_config_get(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size)
+{
+    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
+			       PCI_TYPE1_REG(reg), size);
+}
+
+LOCAL uint64_t
+do_pcibr_config_get(
+		       cfg_p cfgbase,
+		       unsigned reg,
+		       unsigned size)
+{
+    unsigned                value;
+
+   
+    value = CW(cfgbase, reg);
+
+    if (reg & 3)
+	value >>= 8 * (reg & 3);
+    if (size < 4)
+	value &= (1 << (8 * size)) - 1;
+
+    return value;
+}
+
+void
+pcibr_config_set(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size,
+		 uint64_t value)
+{
+    do_pcibr_config_set(pcibr_config_addr(conn, reg),
+			PCI_TYPE1_REG(reg), size, value);
+}
+
+LOCAL void
+do_pcibr_config_set(cfg_p cfgbase,
+		    unsigned reg,
+		    unsigned size,
+		    uint64_t value)
+{
+    switch (size) {
+    case 1:
+	CB(cfgbase, reg) = value;
+	break;
+    case 2:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 1) = value >> 8;
+	} else
+	    CS(cfgbase, reg) = value;
+	break;
+    case 3:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CS(cfgbase, (reg + 1)) = value >> 8;
+	} else {
+	    CS(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 2) = value >> 16;
+	}
+	break;
+
+    case 4:
+	CW(cfgbase, reg) = value;
+	break;
+    }
+}
+
+pciio_provider_t        pcibr_provider =
+{
+    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
+    (pciio_piomap_free_f *) pcibr_piomap_free,
+    (pciio_piomap_addr_f *) pcibr_piomap_addr,
+    (pciio_piomap_done_f *) pcibr_piomap_done,
+    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
+    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
+    (pciio_piospace_free_f *) pcibr_piospace_free,
+
+    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
+    (pciio_dmamap_free_f *) pcibr_dmamap_free,
+    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
+    (pciio_dmamap_list_f *) pcibr_dmamap_list,
+    (pciio_dmamap_done_f *) pcibr_dmamap_done,
+    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
+    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
+    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
+    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
+    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
+
+    (pciio_intr_alloc_f *) pcibr_intr_alloc,
+    (pciio_intr_free_f *) pcibr_intr_free,
+    (pciio_intr_connect_f *) pcibr_intr_connect,
+    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
+    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
+
+    (pciio_provider_startup_f *) pcibr_provider_startup,
+    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
+    (pciio_reset_f *) pcibr_reset,
+    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
+    (pciio_endian_set_f *) pcibr_endian_set,
+    (pciio_priority_set_f *) pcibr_priority_set,
+    (pciio_config_get_f *) pcibr_config_get,
+    (pciio_config_set_f *) pcibr_config_set,
+
+    (pciio_error_devenable_f *) 0,
+    (pciio_error_extract_f *) 0,
+
+#ifdef LATER
+    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
+    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
+#else
+    (pciio_driver_reg_callback_f *) 0,
+    (pciio_driver_unreg_callback_f *) 0,
+#endif
+    (pciio_device_unregister_f 	*) pcibr_device_unregister,
+    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
+};
+
+LOCAL                   pcibr_hints_t
+pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
+{
+    arbitrary_info_t        ainfo = 0;
+    graph_error_t	    rv;
+    pcibr_hints_t           hint;
+
+    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+
+    if (alloc && (rv != GRAPH_SUCCESS)) {
+
+	NEW(hint);
+	hint->rrb_alloc_funct = NULL;
+	hint->ph_intr_bits = NULL;
+	rv = hwgraph_info_add_LBL(xconn_vhdl, 
+				  INFO_LBL_PCIBR_HINTS, 	
+				  (arbitrary_info_t) hint);
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+	
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	if (ainfo != (arbitrary_info_t) hint)
+	    goto abnormal_exit;
+    }
+    return (pcibr_hints_t) ainfo;
+
+abnormal_exit:
+#ifdef LATER
+    printf("SHOULD NOT BE HERE\n");
+#endif
+    DEL(hint);
+    return(NULL);
+
+}
+
+void
+pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_rrb_fixed = mask;
+#if DEBUG
+    else
+	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
+}
+
+void
+pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
+		     pciio_slot_t host,
+		     pciio_slot_t guest)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_host_slot[guest] = host + 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
+		      pcibr_intr_bits_f *xxx_intr_bits)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_intr_bits = xxx_intr_bits;
+#if DEBUG
+    else
+	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
+	       "\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->rrb_alloc_funct = rrb_alloc_funct;
+}
+
+void
+pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_hands_off = 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
+		    pciio_slot_t slot,
+		    uint64_t subdevs)
+{
+    arbitrary_info_t        ainfo = 0;
+    char                    sdname[16];
+    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
+
+    sprintf(sdname, "pci/%d", slot);
+    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
+    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
+#if DEBUG
+	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
+		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
+#endif
+	return;
+    }
+    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+    if (ainfo == 0) {
+	uint64_t                *subdevp;
+
+	NEW(subdevp);
+	if (!subdevp) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+	*subdevp = subdevs;
+	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
+	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+	if (ainfo == (arbitrary_info_t) subdevp)
+	    return;
+	DEL(subdevp);
+	if (ainfo == (arbitrary_info_t) NULL) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+#if DEBUG
+	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
+		"\t%p\n", pconn_vhdl);
+#endif
+    }
+    *(uint64_t *) ainfo = subdevs;
+}
+
+
+#ifdef LATER
+
+#include <sys/idbg.h>
+#include <sys/idbgentry.h>
+
+char *pci_space[] = {"NONE", 
+		     "ROM",
+		     "IO",
+		     "",
+		     "MEM",
+		     "MEM32",
+		     "MEM64",
+		     "CFG",
+		     "WIN0",
+		     "WIN1",
+		     "WIN2",
+		     "WIN3",
+		     "WIN4",
+		     "WIN5",
+		     "",
+		     "BAD"};
+
+void
+idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
+{
+    pcibr_info_t	pcibr_info = pcibr_infoh[func];
+    char		name[MAXDEVNAME];
+    int			win;
+    
+    if (!pcibr_info)
+	return;
+    qprintf("Per-slot Function Info\n");
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(name, "%v", pcibr_info->f_vertex);
+#endif
+    qprintf("\tSlot Name : %s\n",name);
+    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
+    qprintf("Slot : %d ", pcibr_info->f_slot);
+    qprintf("Function : %d ", pcibr_info->f_func);
+    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
+    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(name, "%v", pcibr_info->f_master);
+#endif
+    qprintf("\tBus provider : %s\n",name);
+    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
+    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
+	    pcibr_info->f_efunc,pcibr_info->f_einfo);
+    for(win = 0 ; win < 6 ; win++) 
+	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
+		win,pci_space[pcibr_info->f_window[win].w_space],
+		pcibr_info->f_window[win].w_base,
+		pcibr_info->f_window[win].w_size);
+
+    qprintf("\tRom base 0x%x size 0x%x\n", 
+	    pcibr_info->f_rbase,pcibr_info->f_rsize);
+
+    qprintf("\tInterrupt Bit Map\n");
+    qprintf("\t\tPCI Int#\tBridge Pin#\n");
+    for (win = 0 ; win < 4; win++)
+	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
+    qprintf("\n");
+}
+
+
+void
+idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
+{
+    pcibr_soft_slot_t	pss;
+    char		slot_conn_name[MAXDEVNAME];
+    int			func;
+
+    pss = &pcibr_soft->bs_slot[slot];
+    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
+    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
+    qprintf("\tHost Slot : %d\n",pss->host_slot);
+    sprintf(slot_conn_name, "%v", pss->slot_conn);
+    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
+    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
+    for (func = 0; func < pss->bss_ninfo; func++)
+	idbg_pss_func(pss->bss_infos,func);
+    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
+    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
+    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
+    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
+	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
+    
+    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
+	    "d32_base 0x%x d32_flags 0x%x\n",
+	    pss->bss_d64_base, pss->bss_d64_flags,
+	    pss->bss_d32_base, pss->bss_d32_flags);
+    
+    qprintf("\tExt ATEs active ? %s", 
+	    atomic_read(&pss->bss_ext_ates_active) ? "yes" : "no");
+    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
+    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
+
+    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
+	    pcibr_soft->bs_rrb_valid[slot],
+	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+		
+}
+
+int	ips = 0;
+
+void
+idbg_pss(pcibr_soft_t pcibr_soft)
+{
+    pciio_slot_t	slot;
+
+    
+    if (ips >= 0 && ips < 8)
+	idbg_pss_info(pcibr_soft,ips);
+    else if (ips < 0)
+	for (slot = 0; slot < 8; slot++) 
+	    idbg_pss_info(pcibr_soft,slot);
+    else
+	qprintf("Invalid ips %d\n",ips);
+}
+
+#endif /* LATER */
+
+int
+pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+	
+
+    return xtalk_dma_enabled(pcibr_soft->bs_conn);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/bte_error.c linux/arch/ia64/sn/io/sn2/bte_error.c
--- linux.orig/arch/ia64/sn/io/sn2/bte_error.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/bte_error.c	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,190 @@
+/* $Id: bte_error.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000,2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/ioerror.h>
+#include <asm/sn/sn2/shubio.h>
+#include <asm/sn/bte.h>
+
+/************************************************************************
+ *									*
+ * 			 BTE ERROR RECOVERY				*
+ *									*
+ * Given a BTE error, the node causing the error must do the following: *
+ *    a) Clear all crbs relating to that BTE				*
+ *		1) Read CRBA value for crb in question			*
+ *		2) Mark CRB as VALID, store local physical 		*
+ *		   address known to be good in the address field	*
+ *		   (bte_notification_targ is a known good local		*
+ *		    address).						*
+ *		3) Write CRBA						*
+ *		4) Using ICCR, FLUSH the CRB, and wait for it to 	*
+ *		   complete.						*
+ *		... BTE BUSY bit should now be clear (or at least 	*
+ *		    should be after ALL CRBs associated with the 	*
+ *		    transfer are complete.				*
+ *									*
+ *    b) Re-enable BTE							*
+ *		1) Write IMEM with BTE Enable + XXX bits
+ *		2) Write IECLR with BTE clear bits
+ *		3) Clear IIDSR INT_SENT bits.
+ *									*
+ ************************************************************************/
+
+#ifdef BTE_ERROR
+// This routine is not called.  Yet.  It may be someday.  It probably
+// *should* be someday.  Until then, ifdef it out.
+bte_result_t
+bte_error_handler(bte_handle_t *bh)
+/*
+ * Function: 	bte_error_handler
+ * Purpose:	Process a BTE error after a transfer has failed.
+ * Parameters:	bh - bte handle of bte that failed.
+ * Returns:	The BTE error type.
+ * Notes:
+ */
+{
+    devfs_handle_t	hub_v;
+    hubinfo_t		hinfo;
+    int			il;
+    hubreg_t		iidsr, imem, ieclr;
+    hubreg_t		bte_status;
+
+    bh->bh_bte->bte_error_count++;
+
+    /* 
+     * Process any CRB logs - we know that the bte_context contains
+     * the BTE completion status, but to avoid a race with error
+     * processing, we force a call to pick up any CRB errors pending. 
+     * After this call, we know that we have any CRB errors related to 
+     * this BTE transfer in the context.
+     */
+    hub_v = cnodeid_to_vertex(bh->bh_bte->bte_cnode);
+    hubinfo_get(hub_v, &hinfo);
+    (void)hubiio_crb_error_handler(hub_v, hinfo);
+
+    /* Be sure BTE is stopped */
+
+    (void)BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_CTRL);
+
+    /*	
+     * Now clear up the rest of the error - be sure to hold crblock 
+     * to avoid race with other cpu on this node.
+     */
+    imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
+    ieclr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IECLR);
+    if (bh->bh_bte->bte_num == 0) {
+	imem |= IIO_IMEM_W0ESD | IIO_IMEM_B0ESD;
+	ieclr|= IECLR_BTE0;
+    } else {
+	imem |= IIO_IMEM_W0ESD | IIO_IMEM_B1ESD;
+	ieclr|= IECLR_BTE1;
+    }
+
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IMEM, imem);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, ieclr);
+
+    iidsr  = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR);
+    iidsr &= ~IIO_IIDSR_SENT_MASK;
+    iidsr |= IIO_IIDSR_ENB_MASK;
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, iidsr);
+    mutex_spinunlock(&hinfo->h_crblock, il);
+
+    bte_status = BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_STAT);
+    BTE_STORE(bh->bh_bte->bte_base, BTEOFF_STAT, bte_status & ~IBLS_BUSY);
+    ASSERT(!BTE_IS_BUSY(BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_STAT)));
+
+    switch(bh->bh_error) {
+    case IIO_ICRB_ECODE_PERR:
+	return(BTEFAIL_POISON);
+    case IIO_ICRB_ECODE_WERR:
+	return(BTEFAIL_PROT);
+    case IIO_ICRB_ECODE_AERR:
+	return(BTEFAIL_ACCESS);
+    case IIO_ICRB_ECODE_TOUT:
+	return(BTEFAIL_TOUT);
+    case IIO_ICRB_ECODE_XTERR:
+	return(BTEFAIL_ERROR);
+    case IIO_ICRB_ECODE_DERR:
+	return(BTEFAIL_DIR);
+    case IIO_ICRB_ECODE_PWERR:
+    case IIO_ICRB_ECODE_PRERR:
+	/* NO BREAK */
+    default:
+	printk("BTE failure (%d) unexpected\n", 
+		bh->bh_error);
+	return(BTEFAIL_ERROR);
+    }
+}
+#endif // BTE_ERROR
+
+void
+bte_crb_error_handler(devfs_handle_t hub_v, int btenum, 
+		      int crbnum, ioerror_t *ioe)
+/*
+ * Function: 	bte_crb_error_handler
+ * Purpose:	Process a CRB for a specific HUB/BTE
+ * Parameters:	hub_v	- vertex of hub in HW graph
+ *		btenum	- bte number on hub (0 == a, 1 == b)
+ *		crbnum	- crb number being processed
+ * Notes: 
+ *	This routine assumes serialization at a higher level. A CRB 
+ *	should not be processed more than once. The error recovery 
+ *	follows the following sequence - if you change this, be real
+ *	sure about what you are doing. 
+ *
+ */
+{
+        hubinfo_t	hinfo;
+	icrba_t		crba; 
+	icrbb_t		crbb; 
+	nasid_t		n;
+
+	hubinfo_get(hub_v, &hinfo);
+
+
+	n = hinfo->h_nasid;
+	
+	/* Step 1 */
+	crba.ii_icrb0_a_regval = REMOTE_HUB_L(n, IIO_ICRB_A(crbnum));
+	crbb.ii_icrb0_b_regval = REMOTE_HUB_L(n, IIO_ICRB_B(crbnum));
+
+
+	/* Zero error and error code to prevent error_dump complaining
+	 * about these CRBs. 
+	 */
+	crbb.b_error=0;
+	crbb.b_ecode=0;
+
+	/* Step 2 */
+	REMOTE_HUB_S(n, IIO_ICRB_A(crbnum), crba.ii_icrb0_a_regval);
+	/* Step 3 */
+	REMOTE_HUB_S(n, IIO_ICCR, 
+		     IIO_ICCR_PENDING | IIO_ICCR_CMD_FLUSH | crbnum);
+	while (REMOTE_HUB_L(n, IIO_ICCR) & IIO_ICCR_PENDING)
+	    ;
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/ml_SN_intr.c linux/arch/ia64/sn/io/sn2/ml_SN_intr.c
--- linux.orig/arch/ia64/sn/io/sn2/ml_SN_intr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/ml_SN_intr.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,469 @@
+/* $Id: ml_SN_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+/*
+ * intr.c-
+ *	This file contains all of the routines necessary to set up and
+ *	handle interrupts on an IPXX board.
+ */
+
+#ident  "$Revision: 1.1 $"
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <asm/smp.h>
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/sn2/shub_mmr_t.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+
+extern irqpda_t	*irqpdaindr[];
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+extern nasid_t master_nasid;
+
+//  Initialize some shub registers for interrupts, both IO and error.
+
+void
+intr_init_vecblk( nodepda_t *npda,
+		cnodeid_t node,
+		int sn)
+{
+	int 			nasid = cnodeid_to_nasid(node);
+	nasid_t			console_nasid;
+	sh_ii_int0_config_u_t	ii_int_config;
+	cpuid_t			cpu;
+	cpuid_t			cpu0, cpu1;
+	nodepda_t		*lnodepda;
+	sh_ii_int0_enable_u_t	ii_int_enable;
+	sh_local_int0_config_u_t	local_int_config;
+	sh_local_int0_enable_u_t	local_int_enable;
+	sh_fsb_system_agent_config_u_t	fsb_system_agent;
+	sh_int_node_id_config_u_t	node_id_config;
+	int is_console;
+
+	console_nasid = get_console_nasid();
+	if (console_nasid < 0) {
+		console_nasid = master_nasid;
+	}
+
+	is_console = nasid == console_nasid;
+
+	if (is_headless_node(node) ) {
+		int cnode;
+		struct ia64_sal_retval ret_stuff;
+
+		// retarget all interrupts on this node to the master node.
+		node_id_config.sh_int_node_id_config_regval = 0;
+		node_id_config.sh_int_node_id_config_s.node_id = master_nasid;
+		node_id_config.sh_int_node_id_config_s.id_sel = 1;
+		HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_INT_NODE_ID_CONFIG),
+			node_id_config.sh_int_node_id_config_regval);
+		cnode = nasid_to_cnodeid(master_nasid);
+		lnodepda = NODEPDA(cnode);
+		cpu = lnodepda->node_first_cpu;
+		cpu = cpu_physical_id(cpu);
+		SAL_CALL(ret_stuff, SN_SAL_REGISTER_CE, nasid, cpu, master_nasid,0,0,0,0);
+		if (ret_stuff.status < 0) {
+			printk("%s: SN_SAL_REGISTER_CE SAL_CALL failed\n",__FUNCTION__);
+		}
+	} else {
+		lnodepda = NODEPDA(node);
+		cpu = lnodepda->node_first_cpu;
+		cpu = cpu_physical_id(cpu);
+	}
+
+	// Get the physical id's of the cpu's on this node.
+	cpu0 = id_eid_to_cpu_physical_id(nasid, 0);
+	cpu1 = id_eid_to_cpu_physical_id(nasid, 1);
+
+	HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_ERROR_MASK), 0);
+	HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_CRBP_ERROR_MASK), 0);
+
+	// The II_INT_CONFIG register for cpu 0.
+	ii_int_config.sh_ii_int0_config_s.type = 0;
+	ii_int_config.sh_ii_int0_config_s.agt = 0;
+	ii_int_config.sh_ii_int0_config_s.pid = cpu0;
+	ii_int_config.sh_ii_int0_config_s.base = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_CONFIG),
+		ii_int_config.sh_ii_int0_config_regval);
+
+	// The II_INT_CONFIG register for cpu 1.
+	ii_int_config.sh_ii_int0_config_s.type = 0;
+	ii_int_config.sh_ii_int0_config_s.agt = 0;
+	ii_int_config.sh_ii_int0_config_s.pid = cpu1;
+	ii_int_config.sh_ii_int0_config_s.base = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_CONFIG),
+		ii_int_config.sh_ii_int0_config_regval);
+
+	// Enable interrupts for II_INT0 and 1.
+	ii_int_enable.sh_ii_int0_enable_s.ii_enable = 1;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_ENABLE),
+		ii_int_enable.sh_ii_int0_enable_regval);
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_ENABLE),
+		ii_int_enable.sh_ii_int0_enable_regval);
+
+	// init error regs
+	// LOCAL_INT0 is for the UART only.
+
+	local_int_config.sh_local_int0_config_s.type = 0;
+	local_int_config.sh_local_int0_config_s.agt = 0;
+	local_int_config.sh_local_int0_config_s.pid = cpu;
+	local_int_config.sh_local_int0_config_s.base = 0;
+	local_int_config.sh_local_int0_config_s.idx = SGI_UART_VECTOR;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	// LOCAL_INT1 is for all hardware errors.
+	// It will send a BERR, which will result in an MCA.
+	local_int_config.sh_local_int0_config_s.idx = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	// Clear the LOCAL_INT_ENABLE register.
+	local_int_enable.sh_local_int0_enable_regval = 0;
+
+	if (is_console) {
+		// Enable the UART interrupt.  Only applies to the console nasid.
+		local_int_enable.sh_local_int0_enable_s.uart_int = 1;
+
+		HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_ENABLE),
+			local_int_enable.sh_local_int0_enable_regval);
+	}
+
+	// Enable all the error interrupts.
+	local_int_enable.sh_local_int0_enable_s.uart_int = 0;
+	local_int_enable.sh_local_int0_enable_s.pi_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.lb_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.ii_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.pi_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.system_shutdown_int = 1;
+	local_int_enable.sh_local_int0_enable_s.l1_nmi_int = 1;
+	local_int_enable.sh_local_int0_enable_s.stop_clock = 1;
+
+
+	// Send BERR, rather than an interrupt, for shub errors.
+	local_int_config.sh_local_int0_config_s.agt = 1;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	// Make sure BERR is enabled.
+	fsb_system_agent.sh_fsb_system_agent_config_regval = 
+		HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG) );
+	fsb_system_agent.sh_fsb_system_agent_config_s.berr_assert_en = 1;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG),
+		fsb_system_agent.sh_fsb_system_agent_config_regval);
+
+	// Set LOCAL_INT2 to field CEs
+
+	local_int_enable.sh_local_int0_enable_regval = 0;
+
+	local_int_config.sh_local_int0_config_s.agt = 0;
+	local_int_config.sh_local_int0_config_s.idx = SGI_SHUB_ERROR_VECTOR;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	local_int_enable.sh_local_int0_enable_s.pi_ce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_ce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_ce_int = 1;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	// Make sure all the rest of the LOCAL_INT regs are disabled.
+	local_int_enable.sh_local_int0_enable_regval = 0;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT3_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT4_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT5_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+}
+
+// (Un)Reserve an irq on this cpu.
+
+static int
+do_intr_reserve_level(cpuid_t cpu,
+			int bit,
+			int reserve)
+{
+	int i;
+	irqpda_t	*irqs = irqpdaindr[cpu];
+
+	if (reserve) {
+		if (bit < 0) {
+			for (i = IA64_SN2_FIRST_DEVICE_VECTOR; i <= IA64_SN2_LAST_DEVICE_VECTOR; i++) {
+				if (irqs->irq_flags[i] == 0) {
+					bit = i;
+					break;
+				}
+			}
+		}
+		if (bit < 0) {
+			return -1;
+		}
+		if (irqs->irq_flags[bit] & SN2_IRQ_RESERVED) {
+			return -1;
+		} else {
+			irqs->num_irq_used++;
+			irqs->irq_flags[bit] |= SN2_IRQ_RESERVED;
+			return bit;
+		}
+	} else {
+		if (irqs->irq_flags[bit] & SN2_IRQ_RESERVED) {
+			irqs->num_irq_used--;
+			irqs->irq_flags[bit] &= ~SN2_IRQ_RESERVED;
+			return bit;
+		} else {
+			return -1;
+		}
+	}
+}
+
+int
+intr_reserve_level(cpuid_t cpu,
+		int bit,
+		int resflags,
+		devfs_handle_t owner_dev,
+		char *name)
+{
+	return(do_intr_reserve_level(cpu, bit, 1));
+}
+
+void
+intr_unreserve_level(cpuid_t cpu,
+		int bit)
+{
+	(void)do_intr_reserve_level(cpu, bit, 0);
+}
+
+// Mark an irq on this cpu as (dis)connected.
+
+static int
+do_intr_connect_level(cpuid_t cpu,
+			int bit,
+			int connect)
+{
+	irqpda_t	*irqs = irqpdaindr[cpu];
+
+	if (connect) {
+		if (irqs->irq_flags[bit] & SN2_IRQ_CONNECTED) {
+			return -1;
+		} else {
+			irqs->irq_flags[bit] |= SN2_IRQ_CONNECTED;
+			return bit;
+		}
+	} else {
+		if (irqs->irq_flags[bit] & SN2_IRQ_CONNECTED) {
+			irqs->irq_flags[bit] &= ~SN2_IRQ_CONNECTED;
+			return bit;
+		} else {
+			return -1;
+		}
+	}
+	return(bit);
+}
+
+int
+intr_connect_level(cpuid_t cpu,
+		int bit,
+		ilvl_t is,
+		intr_func_t intr_prefunc)
+{
+	return(do_intr_connect_level(cpu, bit, 1));
+}
+
+int
+intr_disconnect_level(cpuid_t cpu,
+		int bit)
+{
+	return(do_intr_connect_level(cpu, bit, 0));
+}
+
+// Choose a cpu on this node.
+// We choose the one with the least number of int's assigned to it.
+
+static cpuid_t
+do_intr_cpu_choose(cnodeid_t cnode) {
+	cpuid_t		cpu, best_cpu = CPU_NONE;
+	int		slice, min_count = 1000;
+	irqpda_t	*irqs;
+
+	for (slice = 0; slice < CPUS_PER_NODE; slice++) {
+		int intrs;
+
+		cpu = cnode_slice_to_cpuid(cnode, slice);
+		if (cpu == CPU_NONE) {
+			continue;
+		}
+
+		if (!cpu_enabled(cpu)) {
+			continue;
+		}
+
+		irqs = irqpdaindr[cpu];
+		intrs = irqs->num_irq_used;
+
+		if (min_count > intrs) {
+			min_count = intrs;
+			best_cpu = cpu;
+		}
+	}
+	return best_cpu;
+}
+
+static cpuid_t
+intr_cpu_choose_from_node(cnodeid_t cnode)
+{
+	return(do_intr_cpu_choose(cnode));
+}
+
+// See if we can use this cpu/vect.
+
+static cpuid_t
+intr_bit_reserve_test(cpuid_t cpu,
+			int favor_subnode,
+			cnodeid_t cnode,
+			int req_bit,
+			int resflags,
+			devfs_handle_t owner_dev,
+			char *name,
+			int *resp_bit)
+{
+	ASSERT( (cpu == CPU_NONE) || (cnode == CNODEID_NONE) );
+
+	if (cnode != CNODEID_NONE) {
+		cpu = intr_cpu_choose_from_node(cnode);
+	}
+
+	if (cpu != CPU_NONE) {
+		*resp_bit = do_intr_reserve_level(cpu, req_bit, 1);
+		if (*resp_bit >= 0) {
+			return(cpu);
+		}
+	}
+	return CPU_NONE;
+}
+
+// Find the node to assign for this interrupt.
+
+cpuid_t
+intr_heuristic(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		int	req_bit,
+		int resflags,
+		devfs_handle_t owner_dev,
+		char *name,
+		int *resp_bit)
+{
+	cpuid_t		cpuid;
+	cnodeid_t	candidate = -1;
+	devfs_handle_t	pconn_vhdl;
+	pcibr_soft_t	pcibr_soft;
+
+/* SN2 + pcibr addressing limitation */
+/* Due to this limitation, all interrupts from a given bridge must go to the name node.*/
+/* This limitation does not exist on PIC. */
+
+	if ( (hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
+		( (pcibr_soft = pcibr_soft_get(pconn_vhdl) ) != NULL) ) {
+			if (pcibr_soft->bsi_err_intr) {
+				candidate = cpuid_to_cnodeid( ((hub_intr_t)pcibr_soft->bsi_err_intr)->i_cpuid);
+			}
+	}
+
+	if (candidate >= 0) {
+		// The node was chosen already when we assigned the error interrupt.
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+						0,
+						candidate,
+						req_bit,
+						0,
+						owner_dev,
+						name,
+						resp_bit);
+	} else {
+		// Need to choose one.  Try the controlling c-brick first.
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+						0,
+						master_node_get(dev),
+						req_bit,
+						0,
+						owner_dev,
+						name,
+						resp_bit);
+	}
+
+	if (cpuid != CPU_NONE) {
+		return cpuid;
+	}
+
+	if (candidate >= 0) {
+		printk("Cannot target interrupt to target node (%d).\n",candidate);
+		return CPU_NONE;
+	} else {
+		printk("Cannot target interrupt to closest node (%d) 0x%p\n",
+			master_node_get(dev), (void *)owner_dev);
+	}
+
+	// We couldn't put it on the closest node.  Try to find another one.
+	// Do a stupid round-robin assignment of the node.
+
+	{
+		static cnodeid_t last_node = -1;
+		if (last_node >= numnodes) last_node = 0;
+		for (candidate = last_node + 1; candidate != last_node; candidate++) {
+			if (candidate == numnodes) candidate = 0;
+			cpuid = intr_bit_reserve_test(CPU_NONE,
+							0,
+							candidate,
+							req_bit,
+							0,
+							owner_dev,
+							name,
+							resp_bit);
+			if (cpuid != CPU_NONE) {
+				return cpuid;
+			}
+		}
+	}
+
+	printk("cannot target interrupt: 0x%p\n",(void *)owner_dev);
+	return CPU_NONE;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,454 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+uint64_t atealloc(struct map *mp, size_t size);
+void atefree(struct map *mp, size_t size, uint64_t a);
+void atemapfree(struct map *mp);
+struct map *atemapalloc(uint64_t mapsiz);
+
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+
+#ifdef LATER
+#if (PCIBR_FREEZE_TIME) || PCIBR_ATE_DEBUG
+LOCAL struct reg_desc   ate_bits[] =
+{
+    {0xFFFF000000000000ull, -48, "RMF", "%x"},
+    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
+     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
+    {0x0000000000000F00ull, -8, "port", "%x"},
+    {0x0000000000000010ull, 0, "Barrier"},
+    {0x0000000000000008ull, 0, "Prefetch"},
+    {0x0000000000000004ull, 0, "Precise"},
+    {0x0000000000000002ull, 0, "Coherent"},
+    {0x0000000000000001ull, 0, "Valid"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+#ifndef LOCAL
+#define LOCAL           static
+#endif
+
+/*
+ * functions
+ */
+int               pcibr_init_ext_ate_ram(bridge_t *);
+int               pcibr_ate_alloc(pcibr_soft_t, int);
+void              pcibr_ate_free(pcibr_soft_t, int, int);
+bridge_ate_t      pcibr_flags_to_ate(unsigned);
+bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
+unsigned 	  ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   			unsigned *freeze_time_ptr,
+#endif
+	   			unsigned *cmd_regs);
+void 	  ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+void ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 			int ate_index,
+#if PCIBR_FREEZE_TIME
+	 			bridge_ate_t ate,
+	 			int ate_total,
+	 			unsigned freeze_time_start,
+#endif
+	 			unsigned *cmd_regs,
+	 			unsigned s);
+
+
+/* Convert from ssram_bits in control register to number of SSRAM entries */
+#define ATE_NUM_ENTRIES(n) _ate_info[n]
+
+/* Possible choices for number of ATE entries in Bridge's SSRAM */
+LOCAL int               _ate_info[] =
+{
+    0,					/* 0 entries */
+    8 * 1024,				/* 8K entries */
+    16 * 1024,				/* 16K entries */
+    64 * 1024				/* 64K entries */
+};
+
+#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
+#define ATE_PROBE_VALUE 0x0123456789abcdefULL
+
+/*
+ * Determine the size of this bridge's external mapping SSRAM, and set
+ * the control register appropriately to reflect this size, and initialize
+ * the external SSRAM.
+ */
+int
+pcibr_init_ext_ate_ram(bridge_t *bridge)
+{
+    int                     largest_working_size = 0;
+    int                     num_entries, entry;
+    int                     i, j;
+    bridgereg_t             old_enable, new_enable;
+    int                     s;
+
+    /* Probe SSRAM to determine its size. */
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+    bridge->b_int_enable = new_enable;
+
+    for (i = 1; i < ATE_NUM_SIZES; i++) {
+	/* Try writing a value */
+	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+
+	/* Guard against wrap */
+	for (j = 1; j < i; j++)
+	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
+
+	/* See if value was written */
+	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+	    largest_working_size = i;
+    }
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * ensure that we write and read without any interruption.
+     * The read following the write is required for the Bridge war
+     */
+
+    s = splhi();
+    bridge->b_wid_control = (bridge->b_wid_control
+	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+    bridge->b_wid_control;		/* inval addr bug war */
+    splx(s);
+
+    num_entries = ATE_NUM_ENTRIES(largest_working_size);
+
+#if PCIBR_ATE_DEBUG
+    if (num_entries)
+	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
+    else
+	printk("bridge at 0x%x: no external ATE RAM found\n", bridge);
+#endif
+
+    /* Initialize external mapping entries */
+    for (entry = 0; entry < num_entries; entry++)
+	bridge->b_ext_ate_ram[entry] = 0;
+
+    return (num_entries);
+}
+
+/*
+ * Allocate "count" contiguous Bridge Address Translation Entries
+ * on the specified bridge to be used for PCI to XTALK mappings.
+ * Indices in rm map range from 1..num_entries.  Indicies returned
+ * to caller range from 0..num_entries-1.
+ *
+ * Return the start index on success, -1 on failure.
+ */
+int
+pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
+{
+    int                     index = 0;
+
+    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
+
+    if (!index && pcibr_soft->bs_ext_ate_map)
+	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
+
+    /* rmalloc manages resources in the 1..n
+     * range, with 0 being failure.
+     * pcibr_ate_alloc manages resources
+     * in the 0..n-1 range, with -1 being failure.
+     */
+    return index - 1;
+}
+
+void
+pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
+/* Who says there's no such thing as a free meal? :-) */
+{
+    /* note the "+1" since rmalloc handles 1..n but
+     * we start counting ATEs at zero.
+     */
+    rmfree((index < pcibr_soft->bs_int_ate_size)
+	   ? pcibr_soft->bs_int_ate_map
+	   : pcibr_soft->bs_ext_ate_map,
+	   count, index + 1);
+}
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Address Translation Entry attribute bits.
+ */
+bridge_ate_t
+pcibr_flags_to_ate(unsigned flags)
+{
+    bridge_ate_t            attributes;
+
+    /* default if nothing specified:
+     * NOBARRIER
+     * NOPREFETCH
+     * NOPRECISE
+     * COHERENT
+     * Plus the valid bit
+     */
+    attributes = ATE_CO | ATE_V;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~ATE_BAR;		/* no barrier */
+	attributes |= ATE_PREF;		/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= ATE_BAR;		/* barrier bit on */
+	attributes &= ~ATE_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= ATE_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~ATE_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= ATE_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~ATE_PREC;
+
+    return (attributes);
+}
+
+/*
+ * Setup an Address Translation Entry as specified.  Use either the Bridge
+ * internal maps or the external map RAM, as appropriate.
+ */
+bridge_ate_p
+pcibr_ate_addr(pcibr_soft_t pcibr_soft,
+	       int ate_index)
+{
+    bridge_t *bridge = pcibr_soft->bs_base;
+
+    return (ate_index < pcibr_soft->bs_int_ate_size)
+	? &(bridge->b_int_ate_ram[ate_index].wr)
+	: &(bridge->b_ext_ate_ram[ate_index]);
+}
+
+/* We are starting to get more complexity
+ * surrounding writing ATEs, so pull
+ * the writing code into this new function.
+ */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif
+
+unsigned
+ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   unsigned *freeze_time_ptr,
+#endif
+	   unsigned *cmd_regs)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+#ifdef LATER
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+#endif
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+    int                     slot;
+
+    unsigned long           s;
+    unsigned                cmd_reg;
+    volatile unsigned      *cmd_lwa;
+    unsigned                cmd_lwd;
+
+    if (!ext_ates)
+	return 0;
+
+    /* Bridge Hardware Bug WAR #484930:
+     * Bridge can't handle updating External ATEs
+     * while DMA is occuring that uses External ATEs,
+     * even if the particular ATEs involved are disjoint.
+     */
+
+    /* need to prevent anyone else from
+     * unfreezing the grant while we
+     * are working; also need to prevent
+     * this thread from being interrupted
+     * to keep PCI grant freeze time
+     * at an absolute minimum.
+     */
+    s = pcibr_lock(pcibr_soft);
+
+#ifdef LATER
+    /* just in case pcibr_dmamap_done was not called */
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+    }
+#endif	/* LATER */
+#if PCIBR_FREEZE_TIME
+    *freeze_time_ptr = get_timestamp();
+#endif
+
+    cmd_lwa = 0;
+    for (slot = 0; slot < 8; ++slot)
+	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+	    cmd_reg = pcibr_soft->
+		bs_slot[slot].
+		bss_cmd_shadow;
+	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
+		cmd_lwa = pcibr_soft->
+		    bs_slot[slot].
+		    bss_cmd_pointer;
+		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
+		cmd_lwa[0] = cmd_lwd;
+	    }
+	    cmd_regs[slot] = cmd_reg;
+	} else
+	    cmd_regs[slot] = 0;
+
+    if (cmd_lwa) {
+	    bridge_t	*bridge = pcibr_soft->bs_base;
+
+	    /* Read the last master bit that has been cleared. This PIO read
+	     * on the PCI bus is to ensure the completion of any DMAs that
+	     * are due to bus requests issued by PCI devices before the
+	     * clearing of master bits.
+	     */
+	    cmd_lwa[0];
+
+	    /* Flush all the write buffers in the bridge */
+	    for (slot = 0; slot < 8; ++slot)
+		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+			    /* Flush the write buffer associated with this
+			     * PCI device which might be using dma map RAM.
+			     */
+			    bridge->b_wr_req_buf[slot].reg;
+		    }
+    }
+    return s;
+}
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+
+void
+ate_write(bridge_ate_p ate_ptr,
+	  int ate_count,
+	  bridge_ate_t ate)
+{
+    while (ate_count-- > 0) {
+	*ate_ptr++ = ate;
+	ate += IOPGSIZE;
+    }
+}
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+void
+ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 int ate_index,
+#if PCIBR_FREEZE_TIME
+	 bridge_ate_t ate,
+	 int ate_total,
+	 unsigned freeze_time_start,
+#endif
+	 unsigned *cmd_regs,
+	 unsigned s)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+    int                     slot;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+
+    unsigned                cmd_reg;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+    static unsigned         max_freeze_time = 0;
+    static unsigned         max_ate_total;
+#endif
+
+    if (!ext_ates)
+	return;
+
+    /* restore cmd regs */
+    for (slot = 0; slot < 8; ++slot)
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
+	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+
+    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
+    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+
+#if PCIBR_FREEZE_TIME
+    freeze_time = get_timestamp() - freeze_time_start;
+
+    if ((max_freeze_time < freeze_time) ||
+	(max_ate_total < ate_total)) {
+	if (max_freeze_time < freeze_time)
+	    max_freeze_time = freeze_time;
+	if (max_ate_total < ate_total)
+	    max_ate_total = ate_total;
+	pcibr_unlock(pcibr_soft, s);
+	printk("%s: pci freeze time %d usec for %d ATEs\n"
+		"\tfirst ate: %R\n",
+		pcibr_soft->bs_name,
+		freeze_time * 1000 / 1250,
+		ate_total,
+		ate, ate_bits);
+    } else
+#endif
+	pcibr_unlock(pcibr_soft, s);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,167 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+extern pcibr_info_t      pcibr_info_get(devfs_handle_t);
+
+uint64_t          pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
+void              pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+#ifdef LITTLE_ENDIAN
+#ifdef CONFIG_IA64_SGI_SN1
+/*
+ * on sn-ia we need to twiddle the the addresses going out
+ * the pci bus because we use the unswizzled synergy space
+ * (the alternative is to use the swizzled synergy space
+ * and byte swap the data)
+ */
+#define CB(b,r) (((volatile uint8_t *) b)[((r)^4)])
+#define CS(b,r) (((volatile uint16_t *) b)[((r^4)/2)])
+#define CW(b,r) (((volatile uint32_t *) b)[((r^4)/4)])
+#else
+#ifdef CONFIG_IA64_SGI_SN2
+/*
+ * On sn-ia sn2 everything is little endian.  No swizzling 
+ * or byte swapping of addresses required.
+ */
+#define CB(b,r) (((volatile uint8_t *) b)[(r)])
+#define CS(b,r) (((volatile uint16_t *) b)[(r)/2])
+#define CW(b,r) (((volatile uint32_t *) b)[(r)/4])
+#endif
+#endif
+#else
+#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
+#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
+#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
+#endif
+
+
+cfg_p
+pcibr_config_addr(devfs_handle_t conn,
+		  unsigned reg)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_slot_t            pciio_slot;
+    pciio_function_t        pciio_func;
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    cfg_p                   cfgbase = (cfg_p)0;
+
+    pcibr_info = pcibr_info_get(conn);
+
+    pciio_slot = pcibr_info->f_slot;
+    if (pciio_slot == PCIIO_SLOT_NONE)
+	pciio_slot = PCI_TYPE1_SLOT(reg);
+
+    pciio_func = pcibr_info->f_func;
+    if (pciio_func == PCIIO_FUNC_NONE)
+	pciio_func = PCI_TYPE1_FUNC(reg);
+
+    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    bridge = pcibr_soft->bs_base;
+
+    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
+
+    return cfgbase;
+}
+
+uint64_t
+pcibr_config_get(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size)
+{
+    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
+			       PCI_TYPE1_REG(reg), size);
+}
+
+uint64_t
+do_pcibr_config_get(
+		       cfg_p cfgbase,
+		       unsigned reg,
+		       unsigned size)
+{
+    unsigned                value;
+
+    value = CW(cfgbase, reg);
+
+    if (reg & 3)
+	value >>= 8 * (reg & 3);
+    if (size < 4)
+	value &= (1 << (8 * size)) - 1;
+    return value;
+}
+
+void
+pcibr_config_set(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size,
+		 uint64_t value)
+{
+    do_pcibr_config_set(pcibr_config_addr(conn, reg),
+			PCI_TYPE1_REG(reg), size, value);
+}
+
+void
+do_pcibr_config_set(cfg_p cfgbase,
+		    unsigned reg,
+		    unsigned size,
+		    uint64_t value)
+{
+    switch (size) {
+    case 1:
+	CB(cfgbase, reg) = value;
+	break;
+    case 2:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 1) = value >> 8;
+	} else
+	    CS(cfgbase, reg) = value;
+	break;
+    case 3:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CS(cfgbase, (reg + 1)) = value >> 8;
+	} else {
+	    CS(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 2) = value >> 16;
+	}
+	break;
+
+    case 4:
+	CW(cfgbase, reg) = value;
+	break;
+    }
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,4288 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+/*
+ * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
+ * appears that if the lucent part can get into a retry loop if it sees a
+ * DAC on the bus during a pio read retry.  The loop is broken after about
+ * 1ms, so we need to set up bridges holding this part to allow at least
+ * 1ms for pio.
+ */
+
+#define USS302_TIMEOUT_WAR
+
+#ifdef USS302_TIMEOUT_WAR
+#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
+#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
+#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
+#define USS302_BRIDGE_TIMEOUT_HLD	4
+#endif
+
+int                     pcibr_devflag = D_MP;
+
+/*
+ * This is the file operation table for the pcibr driver.
+ * As each of the functions are implemented, put the
+ * appropriate function name below.
+ */
+struct file_operations pcibr_fops = {
+	owner:  THIS_MODULE,
+	llseek: NULL,
+	read: NULL,
+	write: NULL,
+	readdir: NULL,
+	poll: NULL,
+	ioctl: NULL,
+	mmap: NULL,
+	open: NULL,
+	flush: NULL,
+	release: NULL,
+	fsync: NULL,
+	fasync: NULL,
+	lock: NULL,
+	readv: NULL,
+	writev: NULL
+};
+
+#ifdef LATER
+
+#if PCIBR_ATE_DEBUG
+static struct reg_values ssram_sizes[] =
+{
+    {BRIDGE_CTRL_SSRAM_512K, "512k"},
+    {BRIDGE_CTRL_SSRAM_128K, "128k"},
+    {BRIDGE_CTRL_SSRAM_64K, "64k"},
+    {BRIDGE_CTRL_SSRAM_1K, "1k"},
+    {0}
+};
+
+static struct reg_desc   control_bits[] =
+{
+    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
+    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
+    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
+    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
+    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
+    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
+    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
+    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
+    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
+    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
+    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
+    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
+    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
+    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
+    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
+    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
+
+    {BRIDGE_CTRL_BUS_SPEED_MASK, -4, "BUS_SPEED", "%d"},
+    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+/* kbrick widgetnum-to-bus layout */
+int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
+        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
+        2,                                      /* 0x8          */
+        1,                                      /* 0x9          */
+        0, 0,                                   /* 0xa - 0xb    */
+        5,                                      /* 0xc          */
+        6,                                      /* 0xd          */
+        4,                                      /* 0xe          */
+        3,                                      /* 0xf          */
+};
+
+/*
+ * Additional PIO spaces per slot are
+ * recorded in this structure.
+ */
+struct pciio_piospace_s {
+    pciio_piospace_t        next;       /* another space for this device */
+    char                    free;       /* 1 if free, 0 if in use               */
+    pciio_space_t           space;      /* Which space is in use                */
+    iopaddr_t               start;      /* Starting address of the PIO space    */
+    size_t                  count;      /* size of PIO space                    */
+};
+
+#if PCIBR_SOFT_LIST
+pcibr_list_p            pcibr_list = 0;
+#endif
+
+extern int              hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
+extern int              hub_device_flags_set(devfs_handle_t widget_dev, hub_widget_flags_t flags);
+extern long             atoi(register char *p);
+extern cnodeid_t        nodevertex_to_cnodeid(devfs_handle_t vhdl);
+extern void             *swap_ptr(void **loc, void *new);
+extern char             *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
+extern struct map       *atemapalloc(uint64_t);
+extern void             atefree(struct map *, size_t, uint64_t);
+extern void             atemapfree(struct map *);
+extern pciio_dmamap_t   get_free_pciio_dmamap(devfs_handle_t);
+extern void		free_pciio_dmamap(pcibr_dmamap_t);
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif /* PCIBR_FREEZE_TIME */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+
+/* =====================================================================
+ *    Function Table of Contents
+ *
+ *      The order of functions in this file has stopped
+ *      making much sense. We might want to take a look
+ *      at it some time and bring back some sanity, or
+ *      perhaps bust this file into smaller chunks.
+ */
+
+extern void              do_pcibr_rrb_clear(bridge_t *, int);
+extern void              do_pcibr_rrb_flush(bridge_t *, int);
+extern int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+extern int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+extern int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+extern int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+extern void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+extern int  		 pcibr_wrb_flush(devfs_handle_t);
+extern int               pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+extern int               pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+extern int               pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+extern void              pcibr_rrb_flush(devfs_handle_t);
+
+static int                pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
+void                     pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
+
+extern void              pcibr_clearwidint(bridge_t *);
+extern void              pcibr_setwidint(xtalk_intr_t);
+
+void                     pcibr_init(void);
+int                      pcibr_attach(devfs_handle_t);
+int			 pcibr_detach(devfs_handle_t);
+int                      pcibr_open(devfs_handle_t *, int, int, cred_t *);
+int                      pcibr_close(devfs_handle_t, int, int, cred_t *);
+int                      pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
+int                      pcibr_unmap(devfs_handle_t, vhandl_t *);
+int                      pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
+
+void                     pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+
+extern int               pcibr_init_ext_ate_ram(bridge_t *);
+extern int               pcibr_ate_alloc(pcibr_soft_t, int);
+extern void              pcibr_ate_free(pcibr_soft_t, int, int);
+
+extern unsigned          ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   		 unsigned *freeze_time_ptr,
+#endif
+						unsigned *cmd_regs);
+extern void              ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+extern void              ate_thaw(pcibr_dmamap_t pcibr_dmamap, int ate_index,
+#if PCIBR_FREEZE_TIME
+	 				bridge_ate_t ate,
+	 				int ate_total,
+	 				unsigned freeze_time_start,
+#endif
+	 				unsigned *cmd_regs,
+	 				unsigned s);
+
+pcibr_info_t             pcibr_info_get(devfs_handle_t);
+
+static iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+
+pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
+void                    pcibr_piomap_free(pcibr_piomap_t);
+caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
+void                    pcibr_piomap_done(pcibr_piomap_t);
+caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
+void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
+
+static iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
+extern bridge_ate_t     pcibr_flags_to_ate(unsigned);
+
+pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
+void                    pcibr_dmamap_free(pcibr_dmamap_t);
+extern bridge_ate_p     pcibr_ate_addr(pcibr_soft_t, int);
+static iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
+iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
+alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_done(pcibr_dmamap_t);
+cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
+iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
+alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_drain(pcibr_dmamap_t);
+void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
+void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
+iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+extern unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+extern pcibr_intr_t     pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+extern void             pcibr_intr_free(pcibr_intr_t);
+extern void             pcibr_setpciint(xtalk_intr_t);
+extern int              pcibr_intr_connect(pcibr_intr_t);
+extern void             pcibr_intr_disconnect(pcibr_intr_t);
+
+extern devfs_handle_t     pcibr_intr_cpu_get(pcibr_intr_t);
+extern void             pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+extern void             pcibr_intr_func(intr_arg_t);
+
+extern void             print_bridge_errcmd(uint32_t, char *);
+
+extern void             pcibr_error_dump(pcibr_soft_t);
+extern uint32_t         pcibr_errintr_group(uint32_t);
+extern void	        pcibr_pioerr_check(pcibr_soft_t);
+extern void             pcibr_error_intr_handler(intr_arg_t);
+
+extern int              pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *);
+extern void             pcibr_error_cleanup(pcibr_soft_t, int);
+extern void                    pcibr_device_disable(pcibr_soft_t, int);
+extern int              pcibr_pioerror(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_error_devenable(devfs_handle_t, int);
+
+void                    pcibr_provider_startup(devfs_handle_t);
+void                    pcibr_provider_shutdown(devfs_handle_t);
+
+int                     pcibr_reset(devfs_handle_t);
+pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
+int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
+pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
+int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
+
+extern cfg_p            pcibr_config_addr(devfs_handle_t, unsigned);
+extern uint64_t         pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+extern void             pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+extern void             do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+extern pcibr_hints_t    pcibr_hints_get(devfs_handle_t, int);
+extern void             pcibr_hints_fix_rrbs(devfs_handle_t);
+extern void             pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+extern void	 	pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+extern void             pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+extern void             pcibr_hints_handsoff(devfs_handle_t);
+extern void             pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+
+#ifdef BRIDGE_B_DATACORR_WAR
+extern int              ql_bridge_rev_b_war(devfs_handle_t);
+extern int              bridge_rev_b_data_check_disable;
+char                   *rev_b_datacorr_warning =
+"***************************** WARNING! ******************************\n";
+char                   *rev_b_datacorr_mesg =
+"UNRECOVERABLE IO LINK ERROR. CONTACT SERVICE PROVIDER\n";
+#endif
+
+extern int		pcibr_slot_reset(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
+extern int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_call_device_attach(devfs_handle_t, pciio_slot_t, int);
+extern int		pcibr_slot_call_device_detach(devfs_handle_t, pciio_slot_t, int);
+extern int              pcibr_slot_attach(devfs_handle_t, pciio_slot_t, int, char *, int *);
+extern int              pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
+extern int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
+
+#ifdef LATER
+extern int		pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t);
+extern int		pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t);
+extern int		pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t);
+#endif
+
+extern int		pcibr_slot_initial_rrb_alloc(devfs_handle_t, pciio_slot_t);
+extern int		pcibr_initial_rrb(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+
+
+
+/* =====================================================================
+ *    Device(x) register management
+ */
+
+/* pcibr_try_set_device: attempt to modify Device(x)
+ * for the specified slot on the specified bridge
+ * as requested in flags, limited to the specified
+ * bits. Returns which BRIDGE bits were in conflict,
+ * or ZERO if everything went OK.
+ *
+ * Caller MUST hold pcibr_lock when calling this function.
+ */
+static int
+pcibr_try_set_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     unsigned flags,
+		     bridgereg_t mask)
+{
+    bridge_t               *bridge;
+    pcibr_soft_slot_t       slotp;
+    bridgereg_t             old;
+    bridgereg_t             new;
+    bridgereg_t             chg;
+    bridgereg_t             bad;
+    bridgereg_t             badpmu;
+    bridgereg_t             badd32;
+    bridgereg_t             badd64;
+    bridgereg_t             fix;
+    unsigned long           s;
+    bridgereg_t             xmask;
+
+    xmask = mask;
+    if (pcibr_soft->bs_xbridge) {
+    	if (mask == BRIDGE_DEV_PMU_BITS)
+		xmask = XBRIDGE_DEV_PMU_BITS;
+	if (mask == BRIDGE_DEV_D64_BITS)
+		xmask = XBRIDGE_DEV_D64_BITS;
+    }
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    bridge = pcibr_soft->bs_base;
+
+    old = slotp->bss_device;
+
+    /* figure out what the desired
+     * Device(x) bits are based on
+     * the flags specified.
+     */
+
+    new = old;
+
+    /* Currently, we inherit anything that
+     * the new caller has not specified in
+     * one way or another, unless we take
+     * action here to not inherit.
+     *
+     * This is needed for the "swap" stuff,
+     * since it could have been set via
+     * pcibr_endian_set -- altho note that
+     * any explicit PCIBR_BYTE_STREAM or
+     * PCIBR_WORD_VALUES will freely override
+     * the effect of that call (and vice
+     * versa, no protection either way).
+     *
+     * I want to get rid of pcibr_endian_set
+     * in favor of tracking DMA endianness
+     * using the flags specified when DMA
+     * channels are created.
+     */
+
+#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
+#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
+
+    /* Do not use Barrier, Write Gather,
+     * or Prefetch unless asked.
+     * Leave everything else as it
+     * was from the last time.
+     */
+    new = new
+	& ~BRIDGE_DEV_BARRIER
+	& ~BRIDGE_DEV_WRGA_BITS
+	& ~BRIDGE_DEV_PREF
+	;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {
+	new = (new
+            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
+            | BRIDGE_DEV_PREF;          /* prefetch on */
+
+    }
+    if (flags & PCIIO_DMA_CMD) {
+        new = ((new
+            & ~BRIDGE_DEV_PREF)         /* prefetch off */
+            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
+            | BRIDGE_DEV_BARRIER;       /* barrier on */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIIO_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_BYTE_STREAM)
+	new |= (pcibr_soft->bs_xbridge) ? 
+			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
+    if (flags & PCIIO_WORD_VALUES)
+	new &= (pcibr_soft->bs_xbridge) ? 
+			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	new |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	new &= ~BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	new |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	new &= ~BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	new |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	new &= ~BRIDGE_DEV_DEV_SIZE;
+
+    chg = old ^ new;				/* what are we changing, */
+    chg &= xmask;				/* of the interesting bits */
+
+    if (chg) {
+
+	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
+	if (pcibr_soft->bs_xbridge) {
+		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
+	} else {
+		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
+	}
+	bad = badpmu | badd32 | badd64;
+
+	if (bad) {
+
+	    /* some conflicts can be resolved by
+	     * forcing the bit on. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit off,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
+                             BRIDGE_DEV_BARRIER)) ){
+		bad &= ~fix;
+		/* don't change these bits if
+		 * they are already set in "old"
+		 */
+		chg &= ~(fix & old);
+	    }
+	    /* some conflicts can be resolved by
+	     * forcing the bit off. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit on,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
+			     BRIDGE_DEV_PREF)) ) {
+		bad &= ~fix;
+		/* don't change these bits if
+		 * we wanted to turn them on.
+		 */
+		chg &= ~(fix & new);
+	    }
+	    /* conflicts in other bits mean
+	     * we can not establish this DMA
+	     * channel while the other(s) are
+	     * still present.
+	     */
+	    if (bad) {
+		pcibr_unlock(pcibr_soft, s);
+#if (DEBUG && PCIBR_DEV_DEBUG)
+		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
+#endif
+		return bad;
+	    }
+	}
+    }
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr++;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr++;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr++;
+
+    /* the value we want to write is the
+     * original value, with the bits for
+     * our selected changes flipped, and
+     * with any disabled features turned off.
+     */
+    new = old ^ chg;			/* only change what we want to change */
+
+    if (slotp->bss_device == new) {
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
+#endif
+
+    return 0;
+}
+
+void
+pcibr_release_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     bridgereg_t mask)
+{
+    pcibr_soft_slot_t       slotp;
+    unsigned long           s;
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr--;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr--;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr--;
+
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * flush write gather buffer for slot
+ */
+static void
+pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
+              pciio_slot_t slot)
+{
+    bridge_t               *bridge;
+    unsigned long          s;
+    volatile uint32_t     wrf;
+    s = pcibr_lock(pcibr_soft);
+    bridge = pcibr_soft->bs_base;
+    wrf = bridge->b_wr_req_buf[slot].reg;
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Bridge (pcibr) "Device Driver" entry points
+ */
+
+
+/*
+ *    pcibr_init: called once during system startup or
+ *      when a loadable driver is loaded.
+ *
+ *      The driver_register function should normally
+ *      be in _reg, not _init.  But the pcibr driver is
+ *      required by devinit before the _reg routines
+ *      are called, so this is an exception.
+ */
+void
+pcibr_init(void)
+{
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_init\n");
+#endif
+
+    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
+			    XBRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
+			    BRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+}
+
+/*
+ * open/close mmap/munmap interface would be used by processes
+ * that plan to map the PCI bridge, and muck around with the
+ * registers. This is dangerous to do, and will be allowed
+ * to a select brand of programs. Typically these are
+ * diagnostics programs, or some user level commands we may
+ * write to do some weird things.
+ * To start with expect them to have root priveleges.
+ * We will ask for more later.
+ */
+/* ARGSUSED */
+int
+pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+    int                     error;
+    devfs_handle_t            vhdl = dev_to_vhdl(dev);
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    ASSERT(pcibr_soft);
+    len = ctob(btoc(len));		/* Make len page aligned */
+    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
+
+    /*
+     * If the offset being mapped corresponds to the flash prom
+     * base, and if the mapping succeeds, and if the user
+     * has requested the protections to be WRITE, enable the
+     * flash prom to be written.
+     *
+     * XXX- deprecate this in favor of using the
+     * real flash driver ...
+     */
+    if (!error &&
+	((off == BRIDGE_EXTERNAL_FLASH) ||
+	 (len > BRIDGE_EXTERNAL_FLASH))) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+
+    return error;
+}
+
+/*ARGSUSED */
+int
+pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    /*
+     * If flashprom write was enabled, disable it, as
+     * this is the last unmap.
+     */
+    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return 0;
+}
+
+/* This is special case code used by grio. There are plans to make
+ * this a bit more general in the future, but till then this should
+ * be sufficient.
+ */
+pciio_slot_t
+pcibr_device_slot_get(devfs_handle_t dev_vhdl)
+{
+    char                    devname[MAXDEVNAME];
+    devfs_handle_t            tdev;
+    pciio_info_t            pciio_info;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+
+    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
+
+    /* run back along the canonical path
+     * until we find a PCI connection point.
+     */
+    tdev = hwgraph_connectpt_get(dev_vhdl);
+    while (tdev != GRAPH_VERTEX_NONE) {
+	pciio_info = pciio_info_chk(tdev);
+	if (pciio_info) {
+	    slot = pciio_info_slot_get(pciio_info);
+	    break;
+	}
+	hwgraph_vertex_unref(tdev);
+	tdev = hwgraph_connectpt_get(tdev);
+    }
+    hwgraph_vertex_unref(tdev);
+
+    return slot;
+}
+
+/*ARGSUSED */
+int
+pcibr_ioctl(devfs_handle_t dev,
+	    int cmd,
+	    void *arg,
+	    int flag,
+	    struct cred *cr,
+	    int *rvalp)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
+#ifdef LATER
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+#endif
+    int                     error = 0;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    switch (cmd) {
+#ifdef LATER
+    case GIOCSETBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
+	    break;
+	}
+
+    case GIOCRELEASEBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
+	    break;
+	}
+
+    case PCIBR_SLOT_STARTUP:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+	    error = pcibr_slot_startup(pcibr_vhdl, &req);
+	    break;
+	}
+    case PCIBR_SLOT_SHUTDOWN:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+	    error = pcibr_slot_shutdown(pcibr_vhdl, &req);
+	    break;
+	}
+    case PCIBR_SLOT_QUERY:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+            error = pcibr_slot_query(pcibr_vhdl, &req);
+	    break;
+	}
+#endif	/* LATER */
+    default:
+	break;
+
+    }
+
+    return error;
+}
+
+void
+pcibr_freeblock_sub(iopaddr_t *free_basep,
+		    iopaddr_t *free_lastp,
+		    iopaddr_t base,
+		    size_t size)
+{
+    iopaddr_t               free_base = *free_basep;
+    iopaddr_t               free_last = *free_lastp;
+    iopaddr_t               last = base + size - 1;
+
+    if ((last < free_base) || (base > free_last));	/* free block outside arena */
+
+    else if ((base <= free_base) && (last >= free_last))
+	/* free block contains entire arena */
+	*free_basep = *free_lastp = 0;
+
+    else if (base <= free_base)
+	/* free block is head of arena */
+	*free_basep = last + 1;
+
+    else if (last >= free_last)
+	/* free block is tail of arena */
+	*free_lastp = base - 1;
+
+    /*
+     * We are left with two regions: the free area
+     * in the arena "below" the block, and the free
+     * area in the arena "above" the block. Keep
+     * the one that is bigger.
+     */
+
+    else if ((base - free_base) > (free_last - last))
+	*free_lastp = base - 1;		/* keep lower chunk */
+    else
+	*free_basep = last + 1;		/* keep upper chunk */
+}
+
+pcibr_info_t
+pcibr_info_get(devfs_handle_t vhdl)
+{
+    return (pcibr_info_t) pciio_info_get(vhdl);
+}
+
+pcibr_info_t
+pcibr_device_info_new(
+			 pcibr_soft_t pcibr_soft,
+			 pciio_slot_t slot,
+			 pciio_function_t rfunc,
+			 pciio_vendor_id_t vendor,
+			 pciio_device_id_t device)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_function_t        func;
+    int                     ibit;
+
+    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
+
+    NEW(pcibr_info);
+
+    pciio_device_info_new(&pcibr_info->f_c,
+			  pcibr_soft->bs_vhdl,
+			  slot, rfunc,
+			  vendor, device);
+
+/* pfg - this is new ..... */
+    /* Set PCI bus number */
+    pcibr_info->f_bus = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (slot != PCIIO_SLOT_NONE) {
+
+	/*
+	 * Currently favored mapping from PCI
+	 * slot number and INTA/B/C/D to Bridge
+	 * PCI Interrupt Bit Number:
+	 *
+	 *     SLOT     A B C D
+	 *      0       0 4 0 4
+	 *      1       1 5 1 5
+	 *      2       2 6 2 6
+	 *      3       3 7 3 7
+	 *      4       4 0 4 0
+	 *      5       5 1 5 1
+	 *      6       6 2 6 2
+	 *      7       7 3 7 3
+	 *
+	 * XXX- allow pcibr_hints to override default
+	 * XXX- allow ADMIN to override pcibr_hints
+	 */
+	for (ibit = 0; ibit < 4; ++ibit)
+	    pcibr_info->f_ibit[ibit] =
+		(slot + 4 * ibit) & 7;
+
+	/*
+	 * Record the info in the sparse func info space.
+	 */
+	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
+	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
+    }
+    return pcibr_info;
+}
+
+
+/* FIXME:  for now this is needed by both pcibr.c and
+ * pcibr_slot.c.  Need to find a better way, the least
+ * of which would be to move it to pcibr_private.h
+ */
+
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+
+/*
+ * pcibr_device_unregister
+ *	This frees up any hardware resources reserved for this PCI device
+ * 	and removes any PCI infrastructural information setup for it.
+ *	This is usually used at the time of shutting down of the PCI card.
+ */
+int
+pcibr_device_unregister(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t	 pciio_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    int                  count_vchan0, count_vchan1;
+    unsigned             s;
+    int			 error_call;
+    int			 error = 0;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Clear all the hardware xtalk resources for this device */
+    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
+
+    /* Flush all the rrbs */
+    pcibr_rrb_flush(pconn_vhdl);
+
+    /*
+     * If the RRB configuration for this slot has changed, set it 
+     * back to the boot-time default
+     */
+    if (pcibr_soft->bs_rrb_valid_dflt[slot] >= 0) {
+
+        s = pcibr_lock(pcibr_soft);
+
+        /* Free the rrbs allocated to this slot */
+        error_call = do_pcibr_rrb_free(bridge, slot, 
+		                       pcibr_soft->bs_rrb_valid[slot] +
+		                       pcibr_soft->bs_rrb_valid[slot + 
+                                       PCIBR_RRB_SLOT_VIRTUAL]);
+
+        if (error_call)
+            error = ERANGE;
+   
+         pcibr_soft->bs_rrb_res[slot] = pcibr_soft->bs_rrb_res[slot] +
+                                        pcibr_soft->bs_rrb_valid[slot] +
+                                        pcibr_soft->bs_rrb_valid[slot +
+                                        PCIBR_RRB_SLOT_VIRTUAL];
+
+        count_vchan0 = pcibr_soft->bs_rrb_valid_dflt[slot];
+        count_vchan1 = pcibr_soft->bs_rrb_valid_dflt[slot +
+                                                     PCIBR_RRB_SLOT_VIRTUAL];
+
+        pcibr_unlock(pcibr_soft, s);
+
+        pcibr_rrb_alloc(pconn_vhdl, &count_vchan0, &count_vchan1);
+
+    }
+
+    /* Flush the write buffers !! */
+    error_call = pcibr_wrb_flush(pconn_vhdl);
+
+    if (error_call)
+        error = error_call;
+
+    /* Clear the information specific to the slot */
+    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
+
+    if (error_call)
+        error = error_call;
+
+    return(error);
+    
+}
+
+/*
+ * pcibr_driver_reg_callback
+ *      CDL will call this function for each device found in the PCI
+ *      registry that matches the vendor/device IDs supported by 
+ *      the driver being registered.  The device's connection vertex
+ *      and the driver's attach function return status enable the
+ *      slot's device status to be set.
+ */
+void
+pcibr_driver_reg_callback(devfs_handle_t pconn_vhdl,
+			  int key1, int key2, int error)
+{
+    pciio_info_t	 pciio_info;
+    pcibr_info_t         pcibr_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+
+    /* Do not set slot status for vendor/device ID wildcard drivers */
+    if ((key1 == -1) || (key2 == -1))
+        return;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_info = pcibr_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    /* This may be a loadable driver so lock out any pciconfig actions */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    pcibr_info->f_att_det_error = error;
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+}
+
+/*
+ * pcibr_driver_unreg_callback
+ *      CDL will call this function for each device found in the PCI
+ *      registry that matches the vendor/device IDs supported by 
+ *      the driver being unregistered.  The device's connection vertex
+ *      and the driver's detach function return status enable the
+ *      slot's device status to be set.
+ */
+void
+pcibr_driver_unreg_callback(devfs_handle_t pconn_vhdl, 
+                            int key1, int key2, int error)
+{
+    pciio_info_t	 pciio_info;
+    pcibr_info_t         pcibr_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+
+    /* Do not set slot status for vendor/device ID wildcard drivers */
+    if ((key1 == -1) || (key2 == -1))
+        return;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_info = pcibr_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    /* This may be a loadable driver so lock out any pciconfig actions */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    pcibr_info->f_att_det_error = error;
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+}
+
+/* 
+ * build a convenience link path in the
+ * form of ".../<iobrick>/bus/<busnum>"
+ * 
+ * returns 1 on success, 0 otherwise
+ *
+ * depends on hwgraph separator == '/'
+ */
+int
+pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
+{
+        char dst[MAXDEVNAME];
+	char *dp = dst;
+        char *cp, *xp;
+        int widgetnum;
+        char pcibus[8];
+	devfs_handle_t nvtx, svtx;
+	int rv;
+
+#if DEBUG
+	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
+		slot, f_c);
+	{
+		int pos;
+		char dname[256];
+		pos = devfs_generate_path(f_c, dname, 256);
+		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
+	}
+#endif
+
+	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
+		return 0;
+
+	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
+
+	/* find the widget number */
+	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
+	if (xp == NULL)
+		return 0;
+	widgetnum = atoi(xp+7);
+	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
+		return 0;
+
+	/* remove "/pci/direct" from path */
+	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
+	if (cp == NULL)
+		return 0;
+	*cp = (char)NULL;
+
+	/* get the vertex for the widget */
+	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
+		return 0;
+
+	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
+
+	/* dst example now == /hw/module/001c02/Pbrick */
+
+	/* get the bus number */
+        strcat(dst, "/bus");
+        sprintf(pcibus, "%d", p_busnum[widgetnum]);
+
+	/* link to bus to widget */
+	rv = hwgraph_path_add(NULL, dp, &nvtx);
+	if (GRAPH_SUCCESS == rv)
+		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
+
+	return (rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ *    pcibr_attach: called every time the crosstalk
+ *      infrastructure is asked to initialize a widget
+ *      that matches the part number we handed to the
+ *      registration routine above.
+ */
+/*ARGSUSED */
+int
+pcibr_attach(devfs_handle_t xconn_vhdl)
+{
+    /* REFERENCED */
+    graph_error_t           rc;
+    devfs_handle_t            pcibr_vhdl;
+    devfs_handle_t            ctlr_vhdl;
+    bridge_t               *bridge = NULL;
+    bridgereg_t             id;
+    int                     rev;
+    pcibr_soft_t            pcibr_soft;
+    pcibr_info_t            pcibr_info;
+    xwidget_info_t          info;
+    xtalk_intr_t            xtalk_intr;
+    device_desc_t           dev_desc = (device_desc_t)0;
+    int                     slot;
+    int                     ibit;
+    devfs_handle_t            noslot_conn;
+    char                    devnm[MAXDEVNAME], *s;
+    pcibr_hints_t           pcibr_hints;
+    bridgereg_t             b_int_enable;
+    unsigned                rrb_fixed = 0;
+
+    iopaddr_t               pci_io_fb, pci_io_fl;
+    iopaddr_t               pci_lo_fb, pci_lo_fl;
+    iopaddr_t               pci_hi_fb, pci_hi_fl;
+
+    int                     spl_level;
+#ifdef LATER
+    char		    *nicinfo = (char *)0;
+#endif
+
+#if PCI_FBBE
+    int                     fast_back_to_back_enable;
+#endif
+    l1sc_t		    *scp;
+    nasid_t		    nasid;
+
+    async_attach_t          aa = NULL;
+
+    aa = async_attach_get_info(xconn_vhdl);
+
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
+    {
+	int pos;
+	char dname[256];
+	pos = devfs_generate_path(xconn_vhdl, dname, 256);
+	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
+    }
+#endif
+
+    /* Setup the PRB for the bridge in CONVEYOR BELT
+     * mode. PRBs are setup in default FIRE-AND-FORGET
+     * mode during the initialization.
+     */
+    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
+
+    bridge = (bridge_t *)
+	xtalk_piotrans_addr(xconn_vhdl, NULL,
+			    0, sizeof(bridge_t), 0);
+
+    /*
+     * Create the vertex for the PCI bus, which we
+     * will also use to hold the pcibr_soft and
+     * which will be the "master" vertex for all the
+     * pciio connection points we will hang off it.
+     * This needs to happen before we call nic_bridge_vertex_info
+     * as we are some of the *_vmc functions need access to the edges.
+     *
+     * Opening this vertex will provide access to
+     * the Bridge registers themselves.
+     */
+    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
+    ASSERT(rc == GRAPH_SUCCESS);
+
+    ctlr_vhdl = NULL;
+    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
+                0, DEVFS_FL_AUTO_DEVNUM,
+                0, 0,
+                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+                &pcibr_fops, NULL);
+
+    ASSERT(ctlr_vhdl != NULL);
+
+    /*
+     * decode the nic, and hang its stuff off our
+     * connection point where other drivers can get
+     * at it.
+     */
+#ifdef LATER
+    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
+#endif
+
+    /*
+     * Get the hint structure; if some NIC callback
+     * marked this vertex as "hands-off" then we
+     * just return here, before doing anything else.
+     */
+    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
+
+    if (pcibr_hints && pcibr_hints->ph_hands_off)
+	return -1;			/* generic operations disabled */
+
+    id = bridge->b_wid_id;
+    rev = XWIDGET_PART_REV_NUM(id);
+
+    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
+
+    /*
+     * allocate soft state structure, fill in some
+     * fields, and hook it up to our vertex.
+     */
+    NEW(pcibr_soft);
+    BZERO(pcibr_soft, sizeof *pcibr_soft);
+    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
+
+    pcibr_soft->bs_conn = xconn_vhdl;
+    pcibr_soft->bs_vhdl = pcibr_vhdl;
+    pcibr_soft->bs_base = bridge;
+    pcibr_soft->bs_rev_num = rev;
+    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
+    if (is_xbridge(bridge)) {
+	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 1;
+    } else {
+	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 0;
+    }
+
+    nasid = NASID_GET(bridge);
+    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
+    pcibr_soft->bs_l1sc = scp;
+    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
+    pcibr_soft->bsi_err_intr = 0;
+
+    /* Bridges up through REV C
+     * are unable to set the direct
+     * byteswappers to BYTE_STREAM.
+     */
+    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
+	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
+	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
+    }
+#if PCIBR_SOFT_LIST
+    {
+	pcibr_list_p            self;
+
+	NEW(self);
+	self->bl_soft = pcibr_soft;
+	self->bl_vhdl = pcibr_vhdl;
+	self->bl_next = pcibr_list;
+	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
+    }
+#endif
+
+    /*
+     * get the name of this bridge vertex and keep the info. Use this
+     * only where it is really needed now: like error interrupts.
+     */
+    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
+    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    strcpy(pcibr_soft->bs_name, s);
+
+#if SHOW_REVS || DEBUG
+#if !DEBUG
+    if (kdebug)
+#endif
+	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
+		is_xbridge(bridge) ? "X" : "",
+		(rev == BRIDGE_PART_REV_A) ? "A" :
+		(rev == BRIDGE_PART_REV_B) ? "B" :
+		(rev == BRIDGE_PART_REV_C) ? "C" :
+		(rev == BRIDGE_PART_REV_D) ? "D" :
+		(rev == XBRIDGE_PART_REV_A) ? "A" :
+		(rev == XBRIDGE_PART_REV_B) ? "B" :
+		"unknown",
+		rev, pcibr_soft->bs_name);
+#endif
+
+    info = xwidget_info_get(xconn_vhdl);
+    pcibr_soft->bs_xid = xwidget_info_id_get(info);
+    pcibr_soft->bs_master = xwidget_info_master_get(info);
+    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
+
+    /*
+     * Init bridge lock.
+     */
+    spin_lock_init(&pcibr_soft->bs_lock);
+
+    /*
+     * If we have one, process the hints structure.
+     */
+    if (pcibr_hints) {
+	rrb_fixed = pcibr_hints->ph_rrb_fixed;
+
+	pcibr_soft->bs_rrb_fixed = rrb_fixed;
+
+	if (pcibr_hints->ph_intr_bits)
+	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
+
+	for (slot = 0; slot < 8; ++slot) {
+	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
+
+	    if (hslot < 0) {
+		pcibr_soft->bs_slot[slot].host_slot = slot;
+	    } else {
+		pcibr_soft->bs_slot[slot].has_host = 1;
+		pcibr_soft->bs_slot[slot].host_slot = hslot;
+	    }
+	}
+    }
+    /*
+     * set up initial values for state fields
+     */
+    for (slot = 0; slot < 8; ++slot) {
+	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
+	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
+    }
+
+    for (ibit = 0; ibit < 8; ++ibit) {
+	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
+							&(bridge->b_int_status);
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
+    }
+
+    /*
+     * Initialize various Bridge registers.
+     */
+
+    /*
+     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
+     * to zero to avoid dropping stores. (#475347)
+     */
+    if (rev < BRIDGE_PART_REV_D)
+	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
+
+    /*
+     * Clear all pending interrupts.
+     */
+    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
+
+    /*
+     * Until otherwise set up,
+     * assume all interrupts are
+     * from slot 7.
+     */
+    bridge->b_int_device = (uint32_t) 0xffffffff;
+
+    {
+	bridgereg_t             dirmap;
+	paddr_t                 paddr;
+	iopaddr_t               xbase;
+	xwidgetnum_t            xport;
+	iopaddr_t               offset;
+	int                     num_entries = 0;
+	int                     entry;
+	cnodeid_t		cnodeid;
+	nasid_t			nasid;
+
+	/* Set the Bridge's 32-bit PCI to XTalk
+	 * Direct Map register to the most useful
+	 * value we can determine.  Note that we
+	 * must use a single xid for all of:
+	 *      direct-mapped 32-bit DMA accesses
+	 *      direct-mapped 64-bit DMA accesses
+	 *      DMA accesses through the PMU
+	 *      interrupts
+	 * This is the only way to guarantee that
+	 * completion interrupts will reach a CPU
+	 * after all DMA data has reached memory.
+	 * (Of course, there may be a few special
+	 * drivers/controlers that explicitly manage
+	 * this ordering problem.)
+	 */
+
+	cnodeid = 0;  /* default node id */
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+	paddr = NODE_OFFSET(nasid) + 0;
+
+	/* currently, we just assume that if we ask
+	 * for a DMA mapping to "zero" the XIO
+	 * host will transmute this into a request
+	 * for the lowest hunk of memory.
+	 */
+	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
+				    paddr, _PAGESZ, 0);
+
+	if (xbase != XIO_NOWHERE) {
+	    if (XIO_PACKED(xbase)) {
+		xport = XIO_PORT(xbase);
+		xbase = XIO_ADDR(xbase);
+	    } else
+		xport = pcibr_soft->bs_mxid;
+
+	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
+	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
+
+	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
+
+	    if (xbase)
+		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
+	    else if (offset >= (512 << 20))
+		dirmap |= BRIDGE_DIRMAP_ADD512;
+
+	    bridge->b_dir_map = dirmap;
+	}
+	/*
+	 * Set bridge's idea of page size according to the system's
+	 * idea of "IO page size".  TBD: The idea of IO page size
+	 * should really go away.
+	 */
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	spl_level = splhi();
+#if IOPGSIZE == 4096
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#elif IOPGSIZE == 16384
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#else
+	<<<Unable to deal with IOPGSIZE >>>;
+#endif
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(spl_level);
+
+	/* Initialize internal mapping entries */
+	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++) {
+	    bridge->b_int_ate_ram[entry].wr = 0;
+	}
+
+	/*
+	 * Determine if there's external mapping SSRAM on this
+	 * bridge.  Set up Bridge control register appropriately,
+	 * inititlize SSRAM, and set software up to manage RAM
+	 * entries as an allocatable resource.
+	 *
+	 * Currently, we just use the rm* routines to manage ATE
+	 * allocation.  We should probably replace this with a
+	 * Best Fit allocator.
+	 *
+	 * For now, if we have external SSRAM, avoid using
+	 * the internal ssram: we can't turn PREFETCH on
+	 * when we use the internal SSRAM; and besides,
+	 * this also guarantees that no allocation will
+	 * straddle the internal/external line, so we
+	 * can increment ATE write addresses rather than
+	 * recomparing against BRIDGE_INTERNAL_ATES every
+	 * time.
+	 */
+	if (is_xbridge(bridge))
+		num_entries = 0;
+	else
+		num_entries = pcibr_init_ext_ate_ram(bridge);
+
+	/* we always have 128 ATEs (512 for Xbridge) inside the chip
+	 * even if disabled for debugging.
+	 */
+	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
+	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
+#endif
+
+	if (num_entries > pcibr_soft->bs_int_ate_size) {
+#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
+	    printk("pcibr_attach: disabling internal ATEs.\n");
+	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
+#endif
+	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
+	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
+			   num_entries - pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
+		    num_entries - pcibr_soft->bs_int_ate_size);
+#endif
+	}
+    }
+
+    {
+	bridgereg_t             dirmap;
+	iopaddr_t               xbase;
+
+	/*
+	 * now figure the *real* xtalk base address
+	 * that dirmap sends us to.
+	 */
+	dirmap = bridge->b_dir_map;
+	if (dirmap & BRIDGE_DIRMAP_OFF)
+	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
+			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
+	else if (dirmap & BRIDGE_DIRMAP_ADD512)
+	    xbase = 512 << 20;
+	else
+	    xbase = 0;
+
+	pcibr_soft->bs_dir_xbase = xbase;
+
+	/* it is entirely possible that we may, at this
+	 * point, have our dirmap pointing somewhere
+	 * other than our "master" port.
+	 */
+	pcibr_soft->bs_dir_xport =
+	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
+    }
+
+    /* pcibr sources an error interrupt;
+     * figure out where to send it.
+     *
+     * If any interrupts are enabled in bridge,
+     * then the prom set us up and our interrupt
+     * has already been reconnected in mlreset
+     * above.
+     *
+     * Need to set the D_INTR_ISERR flag
+     * in the dev_desc used for allocating the
+     * error interrupt, so our interrupt will
+     * be properly routed and prioritized.
+     *
+     * If our crosstalk provider wants to
+     * fix widget error interrupts to specific
+     * destinations, D_INTR_ISERR is how it
+     * knows to do this.
+     */
+
+    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
+    ASSERT(xtalk_intr != NULL);
+
+    pcibr_soft->bsi_err_intr = xtalk_intr;
+
+    /*
+     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
+     * in order to work around some addressing limitations.  In order
+     * for that fire wall to work properly, we need to make sure we
+     * start from a known clean state.
+     */
+    pcibr_clearwidint(bridge);
+
+    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge);
+
+    /*
+     * now we can start handling error interrupts;
+     * enable all of them.
+     * NOTE: some PCI ints may already be enabled.
+     */
+    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
+
+
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
+
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * Depending on the rev of bridge, disable certain features.
+     * Easiest way seems to be to force the PCIBR_NOwhatever
+     * flag to be on for all DMA calls, which overrides any
+     * PCIBR_whatever flag or even the setting of whatever
+     * from the PCIIO_DMA_class flags (or even from the other
+     * PCIBR flags, since NO overrides YES).
+     */
+    pcibr_soft->bs_dma_flags = 0;
+
+    /* PREFETCH:
+     * Always completely disabled for REV.A;
+     * at "pcibr_prefetch_enable_rev", anyone
+     * asking for PCIIO_PREFETCH gets it.
+     * Between these two points, you have to ask
+     * for PCIBR_PREFETCH, which promises that
+     * your driver knows about known Bridge WARs.
+     */
+    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
+	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
+    else if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
+
+    /* WRITE_GATHER:
+     * Disabled up to but not including the
+     * rev number in pcibr_wg_enable_rev. There
+     * is no "WAR range" as with prefetch.
+     */
+    if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
+
+    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
+    pciio_provider_startup(pcibr_vhdl);
+
+    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
+    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
+
+    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
+    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
+
+    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
+    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
+
+
+    PCI_ADDR_SPACE_LIMITS_STORE();
+
+    /* build "no-slot" connection point
+     */
+    pcibr_info = pcibr_device_info_new
+	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
+	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+    noslot_conn = pciio_device_info_register
+	(pcibr_vhdl, &pcibr_info->f_c);
+
+    /* Remember the no slot connection point info for tearing it
+     * down during detach.
+     */
+    pcibr_soft->bs_noslot_conn = noslot_conn;
+    pcibr_soft->bs_noslot_info = pcibr_info;
+#if PCI_FBBE
+    fast_back_to_back_enable = 1;
+#endif
+
+#if PCI_FBBE
+    if (fast_back_to_back_enable) {
+	/*
+	 * All devices on the bus are capable of fast back to back, so
+	 * we need to set the fast back to back bit in all devices on
+	 * the bus that are capable of doing such accesses.
+	 */
+    }
+#endif
+
+#ifdef LATER
+    /* If the bridge has been reset then there is no need to reset
+     * the individual PCI slots.
+     */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Reset all the slots */
+	(void)pcibr_slot_reset(pcibr_vhdl, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)
+	/* Find out what is out there */
+	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up the address space for this slot in the pci land */
+	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup the device register */
+	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup host/guest relations */
+	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Initial RRB management */
+	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
+
+    /* driver attach routines should be called out from generic linux code */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Call the device attach */
+	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
+
+    /*
+     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
+     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
+     */
+    if (pcibr_soft->bs_moduleid > 0) {
+	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
+	case 'p':		/* Pbrick */
+		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		break;
+	case 'i':		/* Ibrick */
+	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
+		if (pcibr_soft->bs_xid == 0xe) {
+			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		}
+		else {
+		    	/* allocate one RRB for the serial port */
+			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
+		}
+		break;
+	} /* switch */
+    }
+
+#ifdef LATER
+    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
+	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+#if PCIBR_RRB_DEBUG
+	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
+
+	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
+		pcibr_vhdl,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+
+	for (slot = 0; slot < 8; ++slot)
+	    printf("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+
+	printf("\n");
+#endif
+    }
+#else
+	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
+#endif
+
+    if (aa)
+	    async_attach_add_info(noslot_conn, aa);
+
+    pciio_device_attach(noslot_conn, 0);
+
+
+    /* 
+     * Tear down pointer to async attach info -- async threads for
+     * bridge's descendants may be running but the bridge's work is done.
+     */
+    if (aa)
+	    async_attach_del_info(xconn_vhdl);
+
+    return 0;
+}
+/*
+ * pcibr_detach:
+ *	Detach the bridge device from the hwgraph after cleaning out all the 
+ *	underlying vertices.
+ */
+int
+pcibr_detach(devfs_handle_t xconn)
+{
+    pciio_slot_t	slot;
+    devfs_handle_t	pcibr_vhdl;
+    pcibr_soft_t	pcibr_soft;
+    bridge_t		*bridge;
+
+    /* Get the bridge vertex from its xtalk connection point */
+    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
+	return(1);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Disable the interrupts from the bridge */
+    bridge->b_int_enable = 0;
+
+    /* Detach all the PCI devices talking to this bridge */
+    for(slot = 0; slot < 8; slot++) {
+#ifdef DEBUG
+	printk("pcibr_device_detach called for %p/%d\n",
+		pcibr_vhdl,slot);
+#endif
+	pcibr_slot_detach(pcibr_vhdl, slot, 0);
+    }
+
+    /* Unregister the no-slot connection point */
+    pciio_device_info_unregister(pcibr_vhdl,
+				 &(pcibr_soft->bs_noslot_info->f_c));
+
+    spin_lock_destroy(&pcibr_soft->bs_lock);
+    kfree(pcibr_soft->bs_name);
+    
+    /* Error handler gets unregistered when the widget info is 
+     * cleaned 
+     */
+    /* Free the soft ATE maps */
+    if (pcibr_soft->bs_int_ate_map)
+	rmfreemap(pcibr_soft->bs_int_ate_map);
+    if (pcibr_soft->bs_ext_ate_map)
+	rmfreemap(pcibr_soft->bs_ext_ate_map);
+
+    /* Disconnect the error interrupt and free the xtalk resources 
+     * associated with it.
+     */
+    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
+    xtalk_intr_free(pcibr_soft->bsi_err_intr);
+
+    /* Clear the software state maintained by the bridge driver for this
+     * bridge.
+     */
+    DEL(pcibr_soft);
+    /* Remove the Bridge revision labelled info */
+    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
+    /* Remove the character device associated with this bridge */
+    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
+    /* Remove the PCI bridge vertex */
+    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
+
+    return(0);
+}
+
+int
+pcibr_asic_rev(devfs_handle_t pconn_vhdl)
+{
+    devfs_handle_t            pcibr_vhdl;
+    arbitrary_info_t        ainfo;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
+	return -1;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
+	return -1;
+
+    return (int) ainfo;
+}
+
+int
+pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t  slot;
+    slot = pciio_info_slot_get(pciio_info);
+    pcibr_device_write_gather_flush(pcibr_soft, slot);
+    return 0;
+}
+
+/* =====================================================================
+ *    PIO MANAGEMENT
+ */
+
+static iopaddr_t
+pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
+		      pciio_slot_t slot,
+		      pciio_space_t space,
+		      iopaddr_t pci_addr,
+		      size_t req_size,
+		      unsigned flags)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    unsigned                bar;	/* which BASE reg on device is decoding */
+    iopaddr_t               xio_addr = XIO_NOWHERE;
+
+    pciio_space_t           wspace;	/* which space device is decoding */
+    iopaddr_t               wbase;	/* base of device decode on PCI */
+    size_t                  wsize;	/* size of device decode on PCI */
+
+    int                     try;	/* DevIO(x) window scanning order control */
+    int                     win;	/* which DevIO(x) window is being used */
+    pciio_space_t           mspace;	/* target space for devio(x) register */
+    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
+    size_t                  msize;	/* size of devio(x) mapped area on PCI */
+    size_t                  mmask;	/* addr bits stored in Device(x) */
+
+    unsigned long           s;
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	slot = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
+    }
+    if (space == PCIIO_SPACE_NONE)
+	goto done;
+
+    if (space == PCIIO_SPACE_CFG) {
+	/*
+	 * Usually, the first mapping
+	 * established to a PCI device
+	 * is to its config space.
+	 *
+	 * In any case, we definitely
+	 * do NOT need to worry about
+	 * PCI BASE registers, and
+	 * MUST NOT attempt to point
+	 * the DevIO(x) window at
+	 * this access ...
+	 */
+	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
+	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
+	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
+
+	goto done;
+    }
+    if (space == PCIIO_SPACE_ROM) {
+	/* PIO to the Expansion Rom.
+	 * Driver is responsible for
+	 * enabling and disabling
+	 * decodes properly.
+	 */
+	wbase = pcibr_info->f_rbase;
+	wsize = pcibr_info->f_rsize;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	pci_addr += wbase;
+	space = PCIIO_SPACE_MEM;
+    }
+    /*
+     * reduce window mappings to raw
+     * space mappings (maybe allocating
+     * windows), and try for DevIO(x)
+     * usage (setting it if it is available).
+     */
+    bar = space - PCIIO_SPACE_WIN0;
+    if (bar < 6) {
+	wspace = pcibr_info->f_window[bar].w_space;
+	if (wspace == PCIIO_SPACE_NONE)
+	    goto done;
+
+	/* get PCI base and size */
+	wbase = pcibr_info->f_window[bar].w_base;
+	wsize = pcibr_info->f_window[bar].w_size;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	/* shift from window relative to
+	 * decoded space relative.
+	 */
+	pci_addr += wbase;
+	space = wspace;
+    } else
+	bar = -1;
+
+    /* Scan all the DevIO(x) windows twice looking for one
+     * that can satisfy our request. The first time through,
+     * only look at assigned windows; the second time, also
+     * look at PCIIO_SPACE_NONE windows. Arrange the order
+     * so we always look at our own window first.
+     *
+     * We will not attempt to satisfy a single request
+     * by concatinating multiple windows.
+     */
+    for (try = 0; try < 16; ++try) {
+	bridgereg_t             devreg;
+	unsigned                offset;
+
+	win = (try + slot) % 8;
+
+	/* If this DevIO(x) mapping area can provide
+	 * a mapping to this address, use it.
+	 */
+	msize = (win < 2) ? 0x200000 : 0x100000;
+	mmask = -msize;
+	if (space != PCIIO_SPACE_IO)
+	    mmask &= 0x3FFFFFFF;
+
+	offset = pci_addr & (msize - 1);
+
+	/* If this window can't possibly handle that request,
+	 * go on to the next window.
+	 */
+	if (((pci_addr & (msize - 1)) + req_size) > msize)
+	    continue;
+
+	devreg = pcibr_soft->bs_slot[win].bss_device;
+
+	/* Is this window "nailed down"?
+	 * If not, maybe we can use it.
+	 * (only check this the second time through)
+	 */
+	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
+	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
+
+	    /* If this is the primary DevIO(x) window
+	     * for some other device, skip it.
+	     */
+	    if ((win != slot) &&
+		(PCIIO_VENDOR_ID_NONE !=
+		 pcibr_soft->bs_slot[win].bss_vendor_id))
+		continue;
+
+	    /* It's a free window, and we fit in it.
+	     * Set up Device(win) to our taste.
+	     */
+	    mbase = pci_addr & mmask;
+
+	    /* check that we would really get from
+	     * here to there.
+	     */
+	    if ((mbase | offset) != pci_addr)
+		continue;
+
+	    devreg &= ~BRIDGE_DEV_OFF_MASK;
+	    if (space != PCIIO_SPACE_IO)
+		devreg |= BRIDGE_DEV_DEV_IO_MEM;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
+	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	    /* default is WORD_VALUES.
+	     * if you specify both,
+	     * operation is undefined.
+	     */
+	    if (flags & PCIIO_BYTE_STREAM)
+		devreg |= BRIDGE_DEV_DEV_SWAP;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_SWAP;
+
+	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
+		bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+
+#if DEBUG && PCI_DEBUG
+		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
+#endif
+	    }
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
+	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
+		    __FUNCTION__, __LINE__, space, space_desc,
+		    pci_addr, pci_addr + req_size - 1,
+		    slot, win, devreg);
+#endif
+
+	    goto done;
+	}				/* endif DevIO(x) not pointed */
+	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
+
+	/* Now check for request incompat with DevIO(x)
+	 */
+	if ((mspace != space) ||
+	    (pci_addr < mbase) ||
+	    ((pci_addr + req_size) > (mbase + msize)) ||
+	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
+	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
+	    continue;
+
+	/* DevIO(x) window is pointed at PCI space
+	 * that includes our target. Calculate the
+	 * final XIO address, release the lock and
+	 * return.
+	 */
+	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
+		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
+#endif
+	goto done;
+    }
+
+    switch (space) {
+	/*
+	 * Accesses to device decode
+	 * areas that do a not fit
+	 * within the DevIO(x) space are
+	 * modified to be accesses via
+	 * the direct mapping areas.
+	 *
+	 * If necessary, drivers can
+	 * explicitly ask for mappings
+	 * into these address spaces,
+	 * but this should never be needed.
+	 */
+    case PCIIO_SPACE_MEM:		/* "mem space" */
+    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM32_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
+	break;
+
+    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM64_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
+	break;
+
+    case PCIIO_SPACE_IO:		/* "i/o space" */
+	/* Bridge Hardware Bug WAR #482741:
+	 * The 4G area that maps directly from
+	 * XIO space to PCI I/O space is busted
+	 * until Bridge Rev D.
+	 */
+	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
+	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
+	     BRIDGE_PCI_IO_LIMIT))
+	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
+	break;
+    }
+
+    /* Check that "Direct PIO" byteswapping matches,
+     * try to change it if it does not.
+     */
+    if (xio_addr != XIO_NOWHERE) {
+	unsigned                bst;	/* nonzero to set bytestream */
+	unsigned               *bfp;	/* addr of record of how swapper is set */
+	unsigned                swb;	/* which control bit to mung */
+	unsigned                bfo;	/* current swapper setting */
+	unsigned                bfn;	/* desired swapper setting */
+
+	bfp = ((space == PCIIO_SPACE_IO)
+	       ? (&pcibr_soft->bs_pio_end_io)
+	       : (&pcibr_soft->bs_pio_end_mem));
+
+	bfo = *bfp;
+
+	bst = flags & PCIIO_BYTE_STREAM;
+
+	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
+
+	if (bfn == bfo) {		/* we already match. */
+	    ;
+	} else if (bfo != 0) {		/* we have a conflict. */
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
+		    space, 
+		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	    xio_addr = XIO_NOWHERE;
+	} else {			/* OK to make the change. */
+	    bridgereg_t             octl, nctl;
+
+	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
+	    octl = bridge->b_wid_control;
+	    nctl = bst ? octl | swb : octl & ~swb;
+
+	    if (octl != nctl)		/* make the change if any */
+		bridge->b_wid_control = nctl;
+
+	    *bfp = bfn;			/* record the assignment */
+
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
+		    space, 
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	}
+    }
+  done:
+    pcibr_unlock(pcibr_soft, s);
+    return xio_addr;
+}
+
+/*ARGSUSED6 */
+pcibr_piomap_t
+pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   pciio_space_t space,
+		   iopaddr_t pci_addr,
+		   size_t req_size,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    pcibr_piomap_t         *mapptr;
+    pcibr_piomap_t          maplist;
+    pcibr_piomap_t          pcibr_piomap;
+    iopaddr_t               xio_addr;
+    xtalk_piomap_t          xtalk_piomap;
+    unsigned long           s;
+
+    /* Make sure that the req sizes are non-zero */
+    if ((req_size < 1) || (req_size_max < 1))
+	return NULL;
+
+    /*
+     * Code to translate slot/space/addr
+     * into xio_addr is common between
+     * this routine and pcibr_piotrans_addr.
+     */
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    /* Check the piomap list to see if there is already an allocated
+     * piomap entry but not in use. If so use that one. Otherwise
+     * allocate a new piomap entry and add it to the piomap list
+     */
+    mapptr = &(pcibr_info->f_piomap);
+
+    s = pcibr_lock(pcibr_soft);
+    for (pcibr_piomap = *mapptr;
+	 pcibr_piomap != NULL;
+	 pcibr_piomap = pcibr_piomap->bp_next) {
+	if (pcibr_piomap->bp_mapsz == 0)
+	    break;
+    }
+
+    if (pcibr_piomap)
+	mapptr = NULL;
+    else {
+	pcibr_unlock(pcibr_soft, s);
+	NEW(pcibr_piomap);
+    }
+
+    pcibr_piomap->bp_dev = pconn_vhdl;
+    pcibr_piomap->bp_slot = pciio_slot;
+    pcibr_piomap->bp_flags = flags;
+    pcibr_piomap->bp_space = space;
+    pcibr_piomap->bp_pciaddr = pci_addr;
+    pcibr_piomap->bp_mapsz = req_size;
+    pcibr_piomap->bp_soft = pcibr_soft;
+    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
+
+    if (mapptr) {
+	s = pcibr_lock(pcibr_soft);
+	maplist = *mapptr;
+	pcibr_piomap->bp_next = maplist;
+	*mapptr = pcibr_piomap;
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+
+    if (pcibr_piomap) {
+	xtalk_piomap =
+	    xtalk_piomap_alloc(xconn_vhdl, 0,
+			       xio_addr,
+			       req_size, req_size_max,
+			       flags & PIOMAP_FLAGS);
+	if (xtalk_piomap) {
+	    pcibr_piomap->bp_xtalk_addr = xio_addr;
+	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
+	} else {
+	    pcibr_piomap->bp_mapsz = 0;
+	    pcibr_piomap = 0;
+	}
+    }
+    return pcibr_piomap;
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
+    pcibr_piomap->bp_xtalk_pio = 0;
+    pcibr_piomap->bp_mapsz = 0;
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
+		  iopaddr_t pci_addr,
+		  size_t req_size)
+{
+    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
+			     pcibr_piomap->bp_xtalk_addr +
+			     pci_addr - pcibr_piomap->bp_pciaddr,
+			     req_size);
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    pciio_space_t space,
+		    iopaddr_t pci_addr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    iopaddr_t               xio_addr;
+
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
+}
+
+/*
+ * PIO Space allocation and management.
+ *      Allocate and Manage the PCI PIO space (mem and io space)
+ *      This routine is pretty simplistic at this time, and
+ *      does pretty trivial management of allocation and freeing..
+ *      The current scheme is prone for fragmentation..
+ *      Change the scheme to use bitmaps.
+ */
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
+		     device_desc_t dev_desc,
+		     pciio_space_t space,
+		     size_t req_size,
+		     size_t alignment)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+
+    iopaddr_t              *pciaddr, *pcilast;
+    iopaddr_t               start_addr;
+    size_t                  align_mask;
+
+    /*
+     * Check for proper alignment
+     */
+    ASSERT(alignment >= NBPP);
+    ASSERT((alignment & (alignment - 1)) == 0);
+
+    align_mask = alignment - 1;
+    s = pcibr_lock(pcibr_soft);
+
+    /*
+     * First look if a previously allocated chunk exists.
+     */
+    if ((piosp = pcibr_info->f_piospace)) {
+	/*
+	 * Look through the list for a right sized free chunk.
+	 */
+	do {
+	    if (piosp->free &&
+		(piosp->space == space) &&
+		(piosp->count >= req_size) &&
+		!(piosp->start & align_mask)) {
+		piosp->free = 0;
+		pcibr_unlock(pcibr_soft, s);
+		return piosp->start;
+	    }
+	    piosp = piosp->next;
+	} while (piosp);
+    }
+    ASSERT(!piosp);
+
+    switch (space) {
+    case PCIIO_SPACE_IO:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
+	break;
+    case PCIIO_SPACE_MEM:
+    case PCIIO_SPACE_MEM32:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
+	break;
+    default:
+	ASSERT(0);
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+
+    start_addr = *pciaddr;
+
+    /*
+     * Align start_addr.
+     */
+    if (start_addr & align_mask)
+	start_addr = (start_addr + align_mask) & ~align_mask;
+
+    if ((start_addr + req_size) > *pcilast) {
+	/*
+	 * If too big a request, reject it.
+	 */
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    *pciaddr = (start_addr + req_size);
+
+    NEW(piosp);
+    piosp->free = 0;
+    piosp->space = space;
+    piosp->start = start_addr;
+    piosp->count = req_size;
+    piosp->next = pcibr_info->f_piospace;
+    pcibr_info->f_piospace = piosp;
+
+    pcibr_unlock(pcibr_soft, s);
+    return start_addr;
+}
+
+/*ARGSUSED */
+void
+pcibr_piospace_free(devfs_handle_t pconn_vhdl,
+		    pciio_space_t space,
+		    iopaddr_t pciaddr,
+		    size_t req_size)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+    char                    name[1024];
+
+    /*
+     * Look through the bridge data structures for the pciio_piospace_t
+     * structure corresponding to  'pciaddr'
+     */
+    s = pcibr_lock(pcibr_soft);
+    piosp = pcibr_info->f_piospace;
+    while (piosp) {
+	/*
+	 * Piospace free can only be for the complete
+	 * chunk and not parts of it..
+	 */
+	if (piosp->start == pciaddr) {
+	    if (piosp->count == req_size)
+		break;
+	    /*
+	     * Improper size passed for freeing..
+	     * Print a message and break;
+	     */
+	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
+	    printk(KERN_WARNING  "pcibr_piospace_free: error");
+	    printk(KERN_WARNING  "Device %s freeing size (0x%lx) different than allocated (0x%lx)",
+					name, req_size, piosp->count);
+	    printk(KERN_WARNING  "Freeing 0x%lx instead", piosp->count);
+	    break;
+	}
+	piosp = piosp->next;
+    }
+
+    if (!piosp) {
+	printk(KERN_WARNING  
+		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
+		pciaddr, req_size);
+	pcibr_unlock(pcibr_soft, s);
+	return;
+    }
+    piosp->free = 1;
+    pcibr_unlock(pcibr_soft, s);
+    return;
+}
+
+/* =====================================================================
+ *    DMA MANAGEMENT
+ *
+ *      The Bridge ASIC provides three methods of doing
+ *      DMA: via a "direct map" register available in
+ *      32-bit PCI space (which selects a contiguous 2G
+ *      address space on some other widget), via
+ *      "direct" addressing via 64-bit PCI space (all
+ *      destination information comes from the PCI
+ *      address, including transfer attributes), and via
+ *      a "mapped" region that allows a bunch of
+ *      different small mappings to be established with
+ *      the PMU.
+ *
+ *      For efficiency, we most prefer to use the 32-bit
+ *      direct mapping facility, since it requires no
+ *      resource allocations. The advantage of using the
+ *      PMU over the 64-bit direct is that single-cycle
+ *      PCI addressing can be used; the advantage of
+ *      using 64-bit direct over PMU addressing is that
+ *      we do not have to allocate entries in the PMU.
+ */
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Direct Map attribute bits.
+ */
+static iopaddr_t
+pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
+{
+    iopaddr_t               attributes = 0;
+
+    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
+#ifdef LATER
+    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
+#endif
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
+	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
+	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    /* the swap bit is in the address attributes for xbridge */
+    if (pcibr_soft->bs_xbridge) {
+    	if (flags & PCIIO_BYTE_STREAM)
+        	attributes |= PCI64_ATTR_SWAP;
+    	if (flags & PCIIO_WORD_VALUES)
+        	attributes &= ~PCI64_ATTR_SWAP;
+    }
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= PCI64_ATTR_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~PCI64_ATTR_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= PCI64_ATTR_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~PCI64_ATTR_PREC;
+
+    if (flags & PCIBR_VCHAN1)
+	attributes |= PCI64_ATTR_VIRTUAL;
+    if (flags & PCIBR_VCHAN0)
+	attributes &= ~PCI64_ATTR_VIRTUAL;
+
+    return (attributes);
+}
+
+/*ARGSUSED */
+pcibr_dmamap_t
+pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            slot;
+    xwidgetnum_t            xio_port;
+
+    xtalk_dmamap_t          xtalk_dmamap;
+    pcibr_dmamap_t          pcibr_dmamap;
+    int                     ate_count;
+    int                     ate_index;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    /*
+     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
+     * can be called within an interrupt thread.
+     */
+    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
+
+    if (!pcibr_dmamap)
+	return 0;
+
+    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
+				      flags & DMAMAP_FLAGS);
+    if (!xtalk_dmamap) {
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
+#endif
+	free_pciio_dmamap(pcibr_dmamap);
+	return 0;
+    }
+    xio_port = pcibr_soft->bs_mxid;
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_dmamap->bd_dev = pconn_vhdl;
+    pcibr_dmamap->bd_slot = slot;
+    pcibr_dmamap->bd_soft = pcibr_soft;
+    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
+    pcibr_dmamap->bd_max_size = req_size_max;
+    pcibr_dmamap->bd_xio_port = xio_port;
+
+    if (flags & PCIIO_DMA_A64) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    iopaddr_t               pci_addr;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+	    /* Device is capable of A64 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     */
+
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_pci_addr = pci_addr;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct64\n");
+#endif
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct64\n");
+#endif
+	flags &= ~PCIIO_DMA_A64;
+    }
+    if (flags & PCIIO_FIXED) {
+	/* warning: mappings may fail later,
+	 * if direct32 can't get to the address.
+	 */
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
+	    /* User desires DIRECT A32 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     * Mapping calls may fail if target
+	     * is outside the direct32 range.
+	     */
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct32\n");
+#endif
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
+	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct32\n");
+#endif
+	/* If the user demands FIXED and we can't
+	 * give it to him, fail.
+	 */
+	xtalk_dmamap_free(xtalk_dmamap);
+	free_pciio_dmamap(pcibr_dmamap);
+	return 0;
+    }
+    /*
+     * Allocate Address Translation Entries from the mapping RAM.
+     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
+     * the maximum number of ATEs is based on the worst-case
+     * scenario, where the requested target is in the
+     * last byte of an ATE; thus, mapping IOPGSIZE+2
+     * does end up requiring three ATEs.
+     */
+    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
+	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
+		     +req_size_max	/* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    } else {	/* assume requested target is page aligned */
+	ate_count = IOPG(req_size_max   /* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    }
+
+    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
+
+    if (ate_index != -1) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
+	    bridge_ate_t            ate_proto;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using PMU\n");
+#endif
+
+	    ate_proto = pcibr_flags_to_ate(flags);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_pci_addr =
+		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
+	    /*
+	     * for xbridge the byte-swap bit == bit 29 of PCI address
+	     */
+	    if (pcibr_soft->bs_xbridge) {
+		    if (flags & PCIIO_BYTE_STREAM)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    /*
+		     * If swap was set in bss_device in pcibr_endian_set()
+		     * we need to change the address bit.
+		     */
+		    if (pcibr_soft->bs_slot[slot].bss_device & 
+							BRIDGE_DEV_SWAP_PMU)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    if (flags & PCIIO_WORD_VALUES)
+			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
+	    }
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
+	    pcibr_dmamap->bd_ate_index = ate_index;
+	    pcibr_dmamap->bd_ate_count = ate_count;
+	    pcibr_dmamap->bd_ate_proto = ate_proto;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (ate_proto & ATE_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
+				!pcibr_soft->bs_xbridge) {
+		bridge_t               *bridge = pcibr_soft->bs_base;
+		volatile unsigned      *cmd_regp;
+		unsigned                cmd_reg;
+		unsigned long           s;
+
+		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
+
+		s = pcibr_lock(pcibr_soft);
+		cmd_regp = &(bridge->
+			     b_type0_cfg_dev[slot].
+			     l[PCI_CFG_COMMAND / 4]);
+		cmd_reg = *cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
+		pcibr_unlock(pcibr_soft, s);
+	    }
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use PMU\n");
+#endif
+	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
+    }
+    /* total failure: sorry, you just can't
+     * get from here to there that way.
+     */
+#if PCIBR_ATE_DEBUG
+    printk("pcibr_dmamap_alloc: complete failure.\n");
+#endif
+    xtalk_dmamap_free(xtalk_dmamap);
+    free_pciio_dmamap(pcibr_dmamap);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
+
+    unsigned                flags = pcibr_dmamap->bd_flags;
+
+    /* Make sure that bss_ext_ates_active
+     * is properly kept up to date.
+     */
+
+    if (PCIBR_DMAMAP_BUSY & flags)
+	if (PCIBR_DMAMAP_SSRAM & flags)
+	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
+
+    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
+
+    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
+    }
+    if (pcibr_dmamap->bd_ate_count) {
+	pcibr_ate_free(pcibr_dmamap->bd_soft,
+		       pcibr_dmamap->bd_ate_index,
+		       pcibr_dmamap->bd_ate_count);
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
+    }
+
+    free_pciio_dmamap(pcibr_dmamap);
+}
+
+/*
+ *    pcibr_addr_xio_to_pci: given a PIO range, hand
+ *      back the corresponding base PCI MEM address;
+ *      this is used to short-circuit DMA requests that
+ *      loop back onto this PCI bus.
+ */
+static iopaddr_t
+pcibr_addr_xio_to_pci(pcibr_soft_t soft,
+		      iopaddr_t xio_addr,
+		      size_t req_size)
+{
+    iopaddr_t               xio_lim = xio_addr + req_size - 1;
+    iopaddr_t               pci_addr;
+    pciio_slot_t            slot;
+
+    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
+	return pci_addr;
+    }
+    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
+	return pci_addr;
+    }
+    for (slot = 0; slot < 8; ++slot)
+	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
+	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
+	    bridgereg_t             dev;
+
+	    dev = soft->bs_slot[slot].bss_device;
+	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
+	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
+	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
+	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
+	}
+    return 0;
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
+		  paddr_t paddr,
+		  size_t req_size)
+{
+    pcibr_soft_t            pcibr_soft;
+    iopaddr_t               xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    unsigned                flags;
+
+    ASSERT(pcibr_dmamap != NULL);
+    ASSERT(req_size > 0);
+    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    flags = pcibr_dmamap->bd_flags;
+
+    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
+    if (XIO_PACKED(xio_addr)) {
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+    } else
+	xio_port = pcibr_dmamap->bd_xio_port;
+
+    /* If this DMA is to an address that
+     * refers back to this Bridge chip,
+     * reduce it back to the correct
+     * PCI MEM address.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+    } else if (flags & PCIIO_DMA_A64) {
+	/* A64 DMA:
+	 * always use 64-bit direct mapping,
+	 * which always works.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	/* attributes are already bundled up into bd_pci_addr.
+	 */
+	pci_addr = pcibr_dmamap->bd_pci_addr
+	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
+	    | xio_addr;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    pci_addr &= ~PCI64_ATTR_PREF;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct64):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else if (flags & PCIIO_FIXED) {
+	/* A32 direct DMA:
+	 * always use 32-bit direct mapping,
+	 * which may fail.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	if (xio_port != pcibr_soft->bs_dir_xport)
+	    pci_addr = 0;		/* wrong DIDN */
+	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
+	    pci_addr = 0;		/* out of range */
+	else if ((xio_addr + req_size) >
+		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
+	    pci_addr = 0;		/* out of range */
+	else
+	    pci_addr = pcibr_dmamap->bd_pci_addr +
+		xio_addr - pcibr_dmamap->bd_xio_addr;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct32):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+	iopaddr_t               offset = IOPGOFF(xio_addr);
+	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
+	int                     ate_count = IOPG(offset + req_size - 1) + 1;
+
+	int                     ate_index = pcibr_dmamap->bd_ate_index;
+	unsigned                cmd_regs[8];
+	unsigned                s;
+
+#if PCIBR_FREEZE_TIME
+	int                     ate_total = ate_count;
+	unsigned                freeze_time;
+#endif
+
+#if PCIBR_ATE_DEBUG
+	bridge_ate_t            ate_cmp;
+	bridge_ate_p            ate_cptr;
+	unsigned                ate_lo, ate_hi;
+	int                     ate_bad = 0;
+	int                     ate_rbc = 0;
+#endif
+	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	bridge_ate_t            ate;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    ate_proto &= ~ATE_PREF;
+
+	ate = ate_proto
+	    | (xio_port << ATE_TIDSHIFT)
+	    | (xio_addr - offset);
+
+	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
+
+	/* Fill in our mapping registers
+	 * with the appropriate xtalk data,
+	 * and hand back the PCI address.
+	 */
+
+	ASSERT(ate_count > 0);
+	if (ate_count <= pcibr_dmamap->bd_ate_count) {
+		ATE_FREEZE();
+		ATE_WRITE();
+		ATE_THAW();
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	} else {
+		/* The number of ATE's required is greater than the number
+		 * allocated for this map. One way this can happen is if
+		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
+		 * flag, and then when that map is used (right now), the
+		 * target address tells us we really did need to roundup.
+		 * The other possibility is that the map is just plain too
+		 * small to handle the requested target area.
+		 */
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING "pcibr_dmamap_addr :\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\tate_count 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			paddr, paddr + req_size - 1,
+			ate_count, pcibr_dmamap->bd_ate_count);
+#endif
+		pci_addr = 0;
+	}
+
+    }
+    return pci_addr;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
+		  alenlist_t palenlist,
+		  unsigned flags)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge=NULL;
+
+    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+    int                     inplace = flags & PCIIO_INPLACE;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist;
+    size_t                  length;
+    iopaddr_t               offset;
+    unsigned                direct64;
+    int                     ate_index = 0;
+    int                     ate_count = 0;
+    int                     ate_total = 0;
+    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
+    bridge_ate_t            ate_proto = (bridge_ate_t)0;
+    bridge_ate_t            ate_prev;
+    bridge_ate_t            ate;
+    alenaddr_t              xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    alenaddr_t              new_addr;
+    unsigned                cmd_regs[8];
+    unsigned                s = 0;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+#endif
+    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
+							 * with an ATE_FREEZE
+							 */
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
+				       flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
+    if (!direct64) {
+	bridge = pcibr_soft->bs_base;
+	ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	ate_index = pcibr_dmamap->bd_ate_index;
+	ate_proto = pcibr_dmamap->bd_ate_proto;
+	ATE_FREEZE();
+	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
+    }
+    pci_addr = pcibr_dmamap->bd_pci_addr;
+
+    ate_prev = 0;			/* matches no valid ATEs */
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &length, al_flags)) {
+	if (XIO_PACKED(xio_addr)) {
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_dmamap->bd_xio_port;
+
+	if (xio_port == pcibr_soft->bs_xid) {
+	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
+	    if (new_addr == PCI_NOWHERE)
+		goto fail;
+	} else if (direct64) {
+	    new_addr = pci_addr | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Bridge Hardware WAR #482836:
+	     * If the transfer is not cache aligned
+	     * and the Bridge Rev is <= B, force
+	     * prefetch to be off.
+	     */
+	    if (flags & PCIBR_NOPREFETCH)
+		new_addr &= ~PCI64_ATTR_PREF;
+
+	} else {
+	    /* calculate the ate value for
+	     * the first address. If it
+	     * matches the previous
+	     * ATE written (ie. we had
+	     * multiple blocks in the
+	     * same IOPG), then back up
+	     * and reuse that ATE.
+	     *
+	     * We are NOT going to
+	     * aggressively try to
+	     * reuse any other ATEs.
+	     */
+	    offset = IOPGOFF(xio_addr);
+	    ate = ate_proto
+		| (xio_port << ATE_TIDSHIFT)
+		| (xio_addr - offset);
+	    if (ate == ate_prev) {
+#if PCIBR_ATE_DEBUG
+		printk("pcibr_dmamap_list: ATE share\n");
+#endif
+		ate_ptr--;
+		ate_index--;
+		pci_addr -= IOPGSIZE;
+	    }
+	    new_addr = pci_addr + offset;
+
+	    /* Fill in the hardware ATEs
+	     * that contain this block.
+	     */
+	    ate_count = IOPG(offset + length - 1) + 1;
+	    ate_total += ate_count;
+
+	    /* Ensure that this map contains enough ATE's */
+	    if (ate_total > pcibr_dmamap->bd_ate_count) {
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING "pcibr_dmamap_list :\n"
+			"\twanted xio_addr [0x%x..0x%x]\n"
+			"\tate_total 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			xio_addr, xio_addr + length - 1,
+			ate_total, pcibr_dmamap->bd_ate_count);
+#endif
+		goto fail;
+	    }
+
+	    ATE_WRITE();
+
+	    ate_index += ate_count;
+	    ate_ptr += ate_count;
+
+	    ate_count <<= IOPFNSHIFT;
+	    ate += ate_count;
+	    pci_addr += ate_count;
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &new_addr, &length, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				new_addr, length, al_flags))
+		goto fail;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+
+
+    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
+     * changes that ATE_FREEZE has done to implement the external SSRAM
+     * bug workaround.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    return pciio_alenlist;
+
+  fail:
+    /* There are various points of failure after doing an ATE_FREEZE
+     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
+     * The decision to do an ATE_THAW needs to be based on whether a
+     * an ATE_FREEZE was done before.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;
+    }
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
+{
+    /*
+     * We could go through and invalidate ATEs here;
+     * for performance reasons, we don't.
+     * We also don't enforce the strict alternation
+     * between _addr/_list and _done, but Hub does.
+     */
+
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
+    }
+    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+}
+
+
+/*
+ * For each bridge, the DIR_OFF value in the Direct Mapping Register
+ * determines the PCI to Crosstalk memory mapping to be used for all
+ * 32-bit Direct Mapping memory accesses. This mapping can be to any
+ * node in the system. This function will return that compact node id.
+ */
+
+/*ARGSUSED */
+cnodeid_t
+pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
+{
+
+	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
+	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    paddr_t paddr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+
+    xwidgetnum_t            xio_port;
+    iopaddr_t               xio_addr;
+    iopaddr_t               pci_addr;
+
+    int                     have_rrbs;
+    int                     min_rrbs;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
+				   flags & DMAMAP_FLAGS);
+    if (!xio_addr) {
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+	return 0;
+    }
+    /*
+     * find which XIO port this goes to.
+     */
+    if (XIO_PACKED(xio_addr)) {
+	if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	    return 0;
+	}
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+
+    } else
+	xio_port = pcibr_soft->bs_mxid;
+
+    /*
+     * If this DMA comes back to us,
+     * return the PCI MEM address on
+     * which it would land, or NULL
+     * if the target is something
+     * on bridge other than PCI MEM.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+	return pci_addr;
+    }
+    /* If the caller can use A64, try to
+     * satisfy the request with the 64-bit
+     * direct map. This can fail if the
+     * configuration bits in Device(x)
+     * conflict with our flags.
+     */
+
+    if (flags & PCIIO_DMA_A64) {
+	pci_addr = slotp->bss_d64_base;
+	if (!(flags & PCIBR_VCHAN1))
+	    flags |= PCIBR_VCHAN0;
+	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+
+#ifdef CONFIG_IA64_SGI_SN2
+	    pci_addr |= (PHYS_TO_DMA(xio_addr))
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+#else
+	    pci_addr |=  xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+#endif
+
+#if DEBUG && PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr);
+#endif
+	    return (pci_addr);
+	}
+	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_addr;
+#ifdef CONFIG_IA64_SGI_SN2
+	    pci_addr |= (PHYS_TO_DMA(xio_addr))
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+#else
+            pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+#endif
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n"
+			"\tnew flags: 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr, (uint64_t) flags);
+#endif
+	    return (pci_addr);
+	}
+	/* our flags conflict with Device(x).
+	 */
+	flags = flags
+	    & ~PCIIO_DMA_A64
+	    & ~PCIBR_VCHAN0
+	    ;
+
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n"
+		"\tUnable to set Device(x) bits for Direct-64\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+    }
+    /* Try to satisfy the request with the 32-bit direct
+     * map. This can fail if the configuration bits in
+     * Device(x) conflict with our flags, or if the
+     * target address is outside where DIR_OFF points.
+     */
+    {
+	size_t                  map_size = 1ULL << 31;
+	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
+	iopaddr_t               offset = xio_addr - xio_base;
+	iopaddr_t               endoff = req_size + offset;
+
+	if ((req_size > map_size) ||
+	    (xio_addr < xio_base) ||
+	    (xio_port != pcibr_soft->bs_dir_xport) ||
+	    (endoff > map_size)) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\txio region outside direct32 target\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	} else {
+	    pci_addr = slotp->bss_d32_base;
+	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
+		(flags == slotp->bss_d32_flags)) {
+
+		pci_addr |= offset;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tmapped via direct32 offset 0x%x\n"
+			"\twill DMA via pci addr 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, offset, pci_addr);
+#endif
+		return (pci_addr);
+	    }
+	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
+
+		pci_addr = PCI32_DIRECT_BASE;
+		slotp->bss_d32_flags = flags;
+		slotp->bss_d32_base = pci_addr;
+		pci_addr |= offset;
+
+		/* Make sure we have an RRB (or two).
+		 */
+		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		    if (have_rrbs < 2) {
+			if (slotp->bss_device & BRIDGE_DEV_PREF)
+			    min_rrbs = 2;
+			else
+			    min_rrbs = 1;
+			if (have_rrbs < min_rrbs)
+			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		    }
+		}
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+		if (xio_addr != 0x20000000)
+#endif
+		    printk("pcibr_dmatrans_addr:\n"
+			    "\tpciio connection point %v\n"
+			    "\txtalk connection point %v\n"
+			    "\twanted paddr [0x%x..0x%x]\n"
+			    "\txtalk_dmatrans_addr returned 0x%x\n"
+			    "\tmapped via direct32 offset 0x%x\n"
+			    "\twill DMA via pci addr 0x%x\n"
+			    "\tnew flags: 0x%x\n",
+			    pconn_vhdl, xconn_vhdl,
+			    paddr, paddr + req_size - 1,
+			    xio_addr, offset, pci_addr, (uint64_t) flags);
+#endif
+		return (pci_addr);
+	    }
+	    /* our flags conflict with Device(x).
+	     */
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\tUnable to set Device(x) bits for Direct-32\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	}
+    }
+
+#if PCIBR_DMA_DEBUG
+    printk("pcibr_dmatrans_addr:\n"
+	    "\tpciio connection point %v\n"
+	    "\txtalk connection point %v\n"
+	    "\twanted paddr [0x%x..0x%x]\n"
+	    "\txtalk_dmatrans_addr returned 0x%x\n"
+	    "\tno acceptable PCI address found or constructable\n",
+	    pconn_vhdl, xconn_vhdl,
+	    paddr, paddr + req_size - 1,
+	    xio_addr);
+#endif
+
+    return 0;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    alenlist_t palenlist,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+    xwidgetnum_t            xio_port;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist = 0;
+
+    int                     inplace;
+    unsigned                direct64;
+    unsigned                al_flags;
+
+    iopaddr_t               xio_base;
+    alenaddr_t              xio_addr;
+    size_t                  xio_size;
+
+    size_t                  map_size;
+    iopaddr_t               pci_base;
+    alenaddr_t              pci_addr;
+
+    unsigned                relbits = 0;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    inplace = flags & PCIIO_INPLACE;
+    direct64 = flags & PCIIO_DMA_A64;
+    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+
+    if (direct64) {
+	map_size = 1ull << 48;
+	xio_base = 0;
+	pci_base = slotp->bss_d64_base;
+	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D64_BITS;
+	    pci_base =
+		pcibr_flags_to_d64(flags, pcibr_soft);
+	}
+    } else {
+	xio_base = pcibr_soft->bs_dir_xbase;
+	map_size = 1ull << 31;
+	pci_base = slotp->bss_d32_base;
+	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
+	    (flags == slotp->bss_d32_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D32_BITS;
+	    pci_base = PCI32_DIRECT_BASE;
+	}
+    }
+
+    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
+					 flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &xio_size, al_flags)) {
+
+	/*
+	 * find which XIO port this goes to.
+	 */
+	if (XIO_PACKED(xio_addr)) {
+	    if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr);
+#endif
+		return 0;
+	    }
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_soft->bs_mxid;
+
+	/*
+	 * If this DMA comes back to us,
+	 * return the PCI MEM address on
+	 * which it would land, or NULL
+	 * if the target is something
+	 * on bridge other than PCI MEM.
+	 */
+	if (xio_port == pcibr_soft->bs_xid) {
+	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
+	    if ( (pci_addr == (alenaddr_t)NULL) )
+		goto fail;
+	} else if (direct64) {
+	    ASSERT(xio_port != 0);
+	    pci_addr = pci_base | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+	} else {
+	    iopaddr_t               offset = xio_addr - xio_base;
+	    iopaddr_t               endoff = xio_size + offset;
+
+	    if ((xio_size > map_size) ||
+		(xio_addr < xio_base) ||
+		(xio_port != pcibr_soft->bs_dir_xport) ||
+		(endoff > map_size))
+		goto fail;
+
+	    pci_addr = pci_base + (xio_addr - xio_base);
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &pci_addr, &xio_size, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				pci_addr, xio_size, al_flags))
+		goto fail;
+	}
+    }
+
+    if (relbits) {
+	if (direct64) {
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_base;
+	} else {
+	    slotp->bss_d32_flags = flags;
+	    slotp->bss_d32_base = pci_base;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+    return pciio_alenlist;
+
+  fail:
+    if (relbits)
+	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+void
+pcibr_dmamap_drain(pcibr_dmamap_t map)
+{
+    xtalk_dmamap_drain(map->bd_xtalk);
+}
+
+void
+pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
+		    paddr_t paddr,
+		    size_t bytes)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
+}
+
+void
+pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
+		    alenlist_t list)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmalist_drain(xconn_vhdl, list);
+}
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+iopaddr_t
+pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
+{
+    return (pcibr_dmamap->bd_pci_addr);
+}
+
+/* =====================================================================
+ *    CONFIGURATION MANAGEMENT
+ */
+/*ARGSUSED */
+void
+pcibr_provider_startup(devfs_handle_t pcibr)
+{
+}
+
+/*ARGSUSED */
+void
+pcibr_provider_shutdown(devfs_handle_t pcibr)
+{
+}
+
+int
+pcibr_reset(devfs_handle_t conn)
+{
+    pciio_info_t            pciio_info = pciio_info_get(conn);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             ctlreg;
+    unsigned                cfgctl[8];
+    unsigned long           s;
+    int                     f, nf;
+    pcibr_info_h            pcibr_infoh;
+    pcibr_info_t            pcibr_info;
+    int                     win;
+
+    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
+	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
+    }
+    if (pciio_slot < 4) {
+	s = pcibr_lock(pcibr_soft);
+	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
+	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
+
+	ctlreg = bridge->b_wid_control;
+	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
+	/* XXX delay? */
+	bridge->b_wid_control = ctlreg;
+	/* XXX delay? */
+
+	for (f = 0; f < nf; ++f)
+	    if ((pcibr_info = pcibr_infoh[f]))
+		for (win = 0; win < 6; ++win)
+		    if (pcibr_info->f_window[win].w_base != 0)
+			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
+			    pcibr_info->f_window[win].w_base;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
+	pcibr_unlock(pcibr_soft, s);
+
+	return 0;
+    }
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    printk(KERN_WARNING   "%v: pcibr_reset unimplemented for slot %d\n",
+	    conn, pciio_slot);
+#endif
+    return -1;
+}
+
+pciio_endian_t
+pcibr_endian_set(devfs_handle_t pconn_vhdl,
+		 pciio_endian_t device_end,
+		 pciio_endian_t desired_end)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             devreg;
+    unsigned long           s;
+
+    /*
+     * Bridge supports hardware swapping; so we can always
+     * arrange for the caller's desired endianness.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_end != desired_end)
+	devreg |= BRIDGE_DEV_SWAP_BITS;
+    else
+	devreg &= ~BRIDGE_DEV_SWAP_BITS;
+
+    /* NOTE- if we ever put SWAP bits
+     * onto the disabled list, we will
+     * have to change the logic here.
+     */
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
+#endif
+
+    return desired_end;
+}
+
+/* This (re)sets the GBR and REALTIME bits and also keeps track of how
+ * many sets are outstanding. Reset succeeds only if the number of outstanding
+ * sets == 1.
+ */
+int
+pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
+			pciio_slot_t pciio_slot,
+			pciio_priority_t device_prio)
+{
+    unsigned long           s;
+    int                    *counter;
+    bridgereg_t             rtbits = 0;
+    bridgereg_t             devreg;
+    int                     rc = PRIO_SUCCESS;
+
+    /* in dual-slot configurations, the host and the
+     * guest have separate DMA resources, so they
+     * have separate requirements for priority bits.
+     */
+
+    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
+
+    /*
+     * Bridge supports PCI notions of LOW and HIGH priority
+     * arbitration rings via a "REAL_TIME" bit in the per-device
+     * Bridge register. The "GBR" bit controls access to the GBR
+     * ring on the xbow. These two bits are (re)set together.
+     *
+     * XXX- Bug in Rev B Bridge Si:
+     * Symptom: Prefetcher starts operating incorrectly. This happens
+     * due to corruption of the address storage ram in the prefetcher
+     * when a non-real time PCI request is pulled and a real-time one is
+     * put in it's place. Workaround: Use only a single arbitration ring
+     * on PCI bus. GBR and RR can still be uniquely used per
+     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
+     */
+
+    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
+	rtbits |= BRIDGE_DEV_RT;
+
+    /* NOTE- if we ever put DEV_RT or DEV_GBR on
+     * the disabled list, we will have to take
+     * it into account here.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_prio == PCI_PRIO_HIGH) {
+	if ((++*counter == 1)) {
+	    if (rtbits)
+		devreg |= rtbits;
+	    else
+		rc = PRIO_FAIL;
+	}
+    } else if (device_prio == PCI_PRIO_LOW) {
+	if (*counter <= 0)
+	    rc = PRIO_FAIL;
+	else if (--*counter == 0)
+	    if (rtbits)
+		devreg &= ~rtbits;
+    }
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+    return rc;
+}
+
+pciio_priority_t
+pcibr_priority_set(devfs_handle_t pconn_vhdl,
+		   pciio_priority_t device_prio)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
+
+    return device_prio;
+}
+
+/*
+ * Interfaces to allow special (e.g. SGI) drivers to set/clear
+ * Bridge-specific device flags.  Many flags are modified through
+ * PCI-generic interfaces; we don't allow them to be directly
+ * manipulated here.  Only flags that at this point seem pretty
+ * Bridge-specific can be set through these special interfaces.
+ * We may add more flags as the need arises, or remove flags and
+ * create PCI-generic interfaces as the need arises.
+ *
+ * Returns 0 on failure, 1 on success
+ */
+int
+pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
+		       pcibr_device_flags_t flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             set = 0;
+    bridgereg_t             clr = 0;
+
+    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_PMU_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_PMU_WRGA_EN;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_DIR_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_DIR_WRGA_EN;
+
+    if (flags & PCIBR_PREFETCH)
+	set |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	clr |= BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	set |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	clr |= BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	set |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	clr |= BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	set |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	clr |= BRIDGE_DEV_DEV_SIZE;
+
+    if (set || clr) {
+	bridgereg_t             devreg;
+	unsigned long           s;
+
+	s = pcibr_lock(pcibr_soft);
+	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+	devreg = (devreg & ~clr) | set;
+	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+
+	    bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	}
+	pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
+#endif
+    }
+    return (1);
+}
+
+pciio_provider_t        pcibr_provider =
+{
+    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
+    (pciio_piomap_free_f *) pcibr_piomap_free,
+    (pciio_piomap_addr_f *) pcibr_piomap_addr,
+    (pciio_piomap_done_f *) pcibr_piomap_done,
+    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
+    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
+    (pciio_piospace_free_f *) pcibr_piospace_free,
+
+    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
+    (pciio_dmamap_free_f *) pcibr_dmamap_free,
+    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
+    (pciio_dmamap_list_f *) pcibr_dmamap_list,
+    (pciio_dmamap_done_f *) pcibr_dmamap_done,
+    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
+    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
+    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
+    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
+    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
+
+    (pciio_intr_alloc_f *) pcibr_intr_alloc,
+    (pciio_intr_free_f *) pcibr_intr_free,
+    (pciio_intr_connect_f *) pcibr_intr_connect,
+    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
+    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
+
+    (pciio_provider_startup_f *) pcibr_provider_startup,
+    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
+    (pciio_reset_f *) pcibr_reset,
+    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
+    (pciio_endian_set_f *) pcibr_endian_set,
+    (pciio_priority_set_f *) pcibr_priority_set,
+    (pciio_config_get_f *) pcibr_config_get,
+    (pciio_config_set_f *) pcibr_config_set,
+
+    (pciio_error_devenable_f *) 0,
+    (pciio_error_extract_f *) 0,
+
+#ifdef LATER
+    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
+    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
+#else
+    (pciio_driver_reg_callback_f *) 0,
+    (pciio_driver_unreg_callback_f *) 0,
+#endif
+    (pciio_device_unregister_f 	*) pcibr_device_unregister,
+    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
+};
+
+int
+pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+	
+
+    return xtalk_dma_enabled(pcibr_soft->bs_conn);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,1737 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+extern int	hubii_check_widget_disabled(nasid_t, int);
+
+/* =====================================================================
+ *    ERROR HANDLING
+ */
+
+#ifdef	DEBUG
+#ifdef	ERROR_DEBUG
+#define BRIDGE_PIOERR_TIMEOUT	100	/* Timeout with ERROR_DEBUG defined */
+#else
+#define BRIDGE_PIOERR_TIMEOUT	40	/* Timeout in debug mode  */
+#endif
+#else
+#define BRIDGE_PIOERR_TIMEOUT	1	/* Timeout in non-debug mode                            */
+#endif
+
+#ifdef  DEBUG
+#ifdef ERROR_DEBUG
+bridgereg_t bridge_errors_to_dump = ~BRIDGE_ISR_INT_MSK;
+#else
+bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_DUMP;
+#endif
+#else
+bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_FATAL |
+                                BRIDGE_ISR_PCIBUS_PIOERR;
+#endif
+
+#if defined (PCIBR_LLP_CONTROL_WAR)
+int                     pcibr_llp_control_war_cnt;
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+/* FIXME: can these arrays be local ? */
+
+#ifdef LATER
+
+struct reg_values xio_cmd_pactyp[] =
+{
+    {0x0, "RdReq"},
+    {0x1, "RdResp"},
+    {0x2, "WrReqWithResp"},
+    {0x3, "WrResp"},
+    {0x4, "WrReqNoResp"},
+    {0x5, "Reserved(5)"},
+    {0x6, "FetchAndOp"},
+    {0x7, "Reserved(7)"},
+    {0x8, "StoreAndOp"},
+    {0x9, "Reserved(9)"},
+    {0xa, "Reserved(a)"},
+    {0xb, "Reserved(b)"},
+    {0xc, "Reserved(c)"},
+    {0xd, "Reserved(d)"},
+    {0xe, "SpecialReq"},
+    {0xf, "SpecialResp"},
+    {0}
+};
+
+struct reg_desc   xio_cmd_bits[] =
+{
+    {WIDGET_DIDN, -28, "DIDN", "%x"},
+    {WIDGET_SIDN, -24, "SIDN", "%x"},
+    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
+    {WIDGET_TNUM, -15, "TNUM", "%x"},
+    {WIDGET_COHERENT, 0, "COHERENT"},
+    {WIDGET_DS, 0, "DS"},
+    {WIDGET_GBR, 0, "GBR"},
+    {WIDGET_VBPM, 0, "VBPM"},
+    {WIDGET_ERROR, 0, "ERROR"},
+    {WIDGET_BARRIER, 0, "BARRIER"},
+    {0}
+};
+
+#define F(s,n)          { 1l<<(s),-(s), n }
+
+struct reg_desc         bridge_int_status_desc[] =
+{
+    F(31, "MULTI_ERR"),
+    F(30, "PMU_ESIZE_EFAULT"),
+    F(29, "UNEXPECTED_RESP"),
+    F(28, "BAD_XRESP_PACKET"),
+    F(27, "BAD_XREQ_PACKET"),
+    F(26, "RESP_XTALK_ERROR"),
+    F(25, "REQ_XTALK_ERROR"),
+    F(24, "INVALID_ADDRESS"),
+    F(23, "UNSUPPORTED_XOP"),
+    F(22, "XREQ_FIFO_OFLOW"),
+    F(21, "LLP_REC_SNERROR"),
+    F(20, "LLP_REC_CBERROR"),
+    F(19, "LLP_RCTY"),
+    F(18, "LLP_TX_RETRY"),
+    F(17, "LLP_TCTY"),
+    F(16, "SSRAM_PERR"),
+    F(15, "PCI_ABORT"),
+    F(14, "PCI_PARITY"),
+    F(13, "PCI_SERR"),
+    F(12, "PCI_PERR"),
+    F(11, "PCI_MASTER_TOUT"),
+    F(10, "PCI_RETRY_CNT"),
+    F(9, "XREAD_REQ_TOUT"),
+    F(8, "GIO_BENABLE_ERR"),
+    F(7, "INT7"),
+    F(6, "INT6"),
+    F(5, "INT5"),
+    F(4, "INT4"),
+    F(3, "INT3"),
+    F(2, "INT2"),
+    F(1, "INT1"),
+    F(0, "INT0"),
+    {0}
+};
+
+struct reg_values       space_v[] =
+{
+    {PCIIO_SPACE_NONE, "none"},
+    {PCIIO_SPACE_ROM, "ROM"},
+    {PCIIO_SPACE_IO, "I/O"},
+    {PCIIO_SPACE_MEM, "MEM"},
+    {PCIIO_SPACE_MEM32, "MEM(32)"},
+    {PCIIO_SPACE_MEM64, "MEM(64)"},
+    {PCIIO_SPACE_CFG, "CFG"},
+    {PCIIO_SPACE_WIN(0), "WIN(0)"},
+    {PCIIO_SPACE_WIN(1), "WIN(1)"},
+    {PCIIO_SPACE_WIN(2), "WIN(2)"},
+    {PCIIO_SPACE_WIN(3), "WIN(3)"},
+    {PCIIO_SPACE_WIN(4), "WIN(4)"},
+    {PCIIO_SPACE_WIN(5), "WIN(5)"},
+    {PCIIO_SPACE_BAD, "BAD"},
+    {0}
+};
+struct reg_desc         space_desc[] =
+{
+    {0xFF, 0, "space", 0, space_v},
+    {0}
+};
+#define	device_desc	device_bits
+struct reg_desc   device_bits[] =
+{
+    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
+    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
+    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
+    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
+    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
+    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
+    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
+    {BRIDGE_DEV_RT, 0, "RT"},
+    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
+    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
+    {BRIDGE_DEV_PREF, 0, "PREF"},
+    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
+    {BRIDGE_DEV_COH, 0, "COH"},
+    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
+    {BRIDGE_DEV_GBR, 0, "GBR"},
+    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
+    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
+    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
+    {0}
+};
+
+#endif	/* LATER */
+
+void
+print_bridge_errcmd(uint32_t cmdword, char *errtype)
+{
+    printk(
+	    "\t    Bridge %s Error Command Word Register %R\n",
+	    errtype, cmdword, xio_cmd_bits);
+}
+
+char             *pcibr_isr_errs[] =
+{
+    "", "", "", "", "", "", "", "",
+    "08: GIO non-contiguous byte enable in crosstalk packet",
+    "09: PCI to Crosstalk read request timeout",
+    "10: PCI retry operation count exhausted.",
+    "11: PCI bus device select timeout",
+    "12: PCI device reported parity error",
+    "13: PCI Address/Cmd parity error ",
+    "14: PCI Bridge detected parity error",
+    "15: PCI abort condition",
+    "16: SSRAM parity error",
+    "17: LLP Transmitter Retry count wrapped",
+    "18: LLP Transmitter side required Retry",
+    "19: LLP Receiver retry count wrapped",
+    "20: LLP Receiver check bit error",
+    "21: LLP Receiver sequence number error",
+    "22: Request packet overflow",
+    "23: Request operation not supported by bridge",
+    "24: Request packet has invalid address for bridge widget",
+    "25: Incoming request xtalk command word error bit set or invalid sideband",
+    "26: Incoming response xtalk command word error bit set or invalid sideband",
+    "27: Framing error, request cmd data size does not match actual",
+    "28: Framing error, response cmd data size does not match actual",
+    "29: Unexpected response arrived",
+    "30: PMU Access Fault",
+    "31: Multiple errors occurred",
+};
+
+#define BEM_ADD_STR(s)  printk("%s", (s))
+#define BEM_ADD_VAR(v)  printk("\t%20s: 0x%x\n", #v, (v))
+#define BEM_ADD_REG(r)  printk("\t%20s: %R\n", #r, (r), r ## _desc)
+#define BEM_ADD_NSPC(n,s)       printk("\t%20s: %R\n", n, s, space_desc)
+#define BEM_ADD_SPC(s)          BEM_ADD_NSPC(#s, s)
+
+/*
+ * display memory directory state
+ */
+void
+pcibr_show_dir_state(paddr_t paddr, char *prefix)
+{
+	int state;
+	uint64_t vec_ptr;
+	hubreg_t elo;
+	extern char *dir_state_str[];
+	extern void get_dir_ent(paddr_t, int *, uint64_t *, hubreg_t *);
+
+	get_dir_ent(paddr, &state, &vec_ptr, &elo);
+
+	printf("%saddr 0x%x: state 0x%x owner 0x%x (%s)\n", 
+		prefix, paddr, state, vec_ptr, dir_state_str[state]);
+}
+
+
+/*
+ *	Dump relevant error information for Bridge error interrupts.
+ */
+/*ARGSUSED */
+void
+pcibr_error_dump(pcibr_soft_t pcibr_soft)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             int_status;
+    bridgereg_t             mult_int;
+    int			    bit;
+    int                     i;
+    char		    *reg_desc;
+    paddr_t		    addr;
+
+    int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
+    if (!int_status) {
+	/* No error bits set */
+	return;
+    }
+
+    /* Check if dumping the same error information multiple times */
+    if (test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat,
+	    int_status) == int_status) {
+	return;
+    }
+
+    printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%X for %s\n"
+	"    Dumping relevant %sBridge registers for each bit set...\n",
+	    int_status, pcibr_soft->bs_name,
+	    (is_xbridge(bridge) ? "X" : ""));
+
+    for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
+	bit = 1 << i;
+
+	/*
+	 * A number of int_status bits are only defined for Bridge.
+	 * Ignore them in the case of an XBridge.
+	 */
+	if (is_xbridge(bridge) && ((bit == BRIDGE_ISR_MULTI_ERR) ||
+		(bit == BRIDGE_ISR_SSRAM_PERR) ||
+		(bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) {
+	    continue;
+	}
+
+	if (int_status & bit) {
+	    printk("\t%s\n", pcibr_isr_errs[i]);
+
+	    switch (bit) {
+	    case BRIDGE_ISR_PAGE_FAULT:		/* PMU_PAGE_FAULT  (XBridge) */
+/*	    case BRIDGE_ISR_PMU_ESIZE_FAULT:	   PMU_ESIZE_FAULT (Bridge) */
+		if (is_xbridge(bridge))
+		    reg_desc = "Map Fault Address";
+		else
+		    reg_desc = "SSRAM Parity Error";
+
+		printk("\t    %s Register: 0x%x\n", reg_desc,
+		    bridge->b_ram_perr_or_map_fault);
+		break;
+
+	    case BRIDGE_ISR_UNEXP_RESP:		/* UNEXPECTED_RESP */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "Aux");
+		break;
+
+	    case BRIDGE_ISR_BAD_XRESP_PKT:		/* BAD_RESP_PACKET */
+	    case BRIDGE_ISR_RESP_XTLK_ERR:		/* RESP_XTALK_ERROR */
+	    case BRIDGE_ISR_XREAD_REQ_TIMEOUT:		/* XREAD_REQ_TOUT */
+
+		addr = (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32)
+			| bridge->b_wid_resp_lower);
+		printk(
+		    "\t    Bridge Response Buffer Error Upper Address Register: 0x%x\n"
+		    "\t    Bridge Response Buffer Error Lower Address Register: 0x%x\n"
+		    "\t    dev-num %d buff-num %d addr 0x%x\n",
+		    bridge->b_wid_resp_upper, bridge->b_wid_resp_lower,
+		    ((bridge->b_wid_resp_upper >> 20) & 0x3),
+		    ((bridge->b_wid_resp_upper >> 16) & 0xF),
+		    addr);
+		if (bit == BRIDGE_ISR_RESP_XTLK_ERR) {
+			/* display memory directory associated with cacheline */
+			pcibr_show_dir_state(addr, "\t    ");
+		}
+		break;
+
+	    case BRIDGE_ISR_BAD_XREQ_PKT:		/* BAD_XREQ_PACKET */
+	    case BRIDGE_ISR_REQ_XTLK_ERR:		/* REQ_XTALK_ERROR */
+	    case BRIDGE_ISR_INVLD_ADDR:			/* INVALID_ADDRESS */
+	    case BRIDGE_ISR_UNSUPPORTED_XOP:		/* UNSUPPORTED_XOP */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "");
+		printk("\t    Bridge Error Upper Address Register: 0x%x\n"
+		    "\t    Bridge Error Lower Address Register: 0x%x\n"
+		    "\t    Bridge Error Address: 0x%x\n",
+		    (uint64_t) bridge->b_wid_err_upper,
+		    (uint64_t) bridge->b_wid_err_lower,
+		    (((uint64_t) bridge->b_wid_err_upper << 32) |
+		    bridge->b_wid_err_lower));
+		break;
+
+	    case BRIDGE_ISR_SSRAM_PERR:			/* SSRAM_PERR */
+		if (!is_xbridge(bridge)) {	/* only defined on Bridge */
+		    printk(
+			"\t    Bridge SSRAM Parity Error Register: 0x%x\n",
+			bridge->b_ram_perr);
+		}
+		break;
+
+	    case BRIDGE_ISR_PCI_ABORT:			/* PCI_ABORT */
+	    case BRIDGE_ISR_PCI_PARITY:			/* PCI_PARITY */
+	    case BRIDGE_ISR_PCI_SERR:			/* PCI_SERR */
+	    case BRIDGE_ISR_PCI_PERR:			/* PCI_PERR */
+	    case BRIDGE_ISR_PCI_MST_TIMEOUT:		/* PCI_MASTER_TOUT */
+	    case BRIDGE_ISR_PCI_RETRY_CNT:		/* PCI_RETRY_CNT */
+	    case BRIDGE_ISR_GIO_B_ENBL_ERR:		/* GIO BENABLE_ERR */
+		printk("\t    PCI Error Upper Address Register: 0x%x\n"
+		    "\t    PCI Error Lower Address Register: 0x%x\n"
+		    "\t    PCI Error Address: 0x%x\n",
+		    (uint64_t) bridge->b_pci_err_upper,
+		    (uint64_t) bridge->b_pci_err_lower,
+		    (((uint64_t) bridge->b_pci_err_upper << 32) |
+		    bridge->b_pci_err_lower));
+		break;
+	    }
+	}
+    }
+
+    if (is_xbridge(bridge) && (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK)) {
+	mult_int = bridge->b_mult_int;
+	printk("    XBridge Multiple Interrupt Register is 0x%x\n",
+		mult_int);
+	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
+	    if (mult_int & (1 << i))
+		printk("\t%s\n", pcibr_isr_errs[i]);
+	    }
+	}
+}
+
+#define PCIBR_ERRINTR_GROUP(error)	\
+		(( error & (BRIDGE_IRR_PCI_GRP|BRIDGE_IRR_GIO_GRP)
+
+uint32_t
+pcibr_errintr_group(uint32_t error)
+{
+    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
+
+    if (error & BRIDGE_IRR_PCI_GRP)
+	group |= BRIDGE_IRR_PCI_GRP_CLR;
+    if (error & BRIDGE_IRR_SSRAM_GRP)
+	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
+    if (error & BRIDGE_IRR_LLP_GRP)
+	group |= BRIDGE_IRR_LLP_GRP_CLR;
+    if (error & BRIDGE_IRR_REQ_DSP_GRP)
+	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
+    if (error & BRIDGE_IRR_RESP_BUF_GRP)
+	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
+    if (error & BRIDGE_IRR_CRP_GRP)
+	group |= BRIDGE_IRR_CRP_GRP_CLR;
+
+    return group;
+
+}
+
+
+/* pcibr_pioerr_check():
+ *	Check to see if this pcibr has a PCI PIO
+ *	TIMEOUT error; if so, bump the timeout-count
+ *	on any piomaps that could cover the address.
+ */
+static void
+pcibr_pioerr_check(pcibr_soft_t soft)
+{
+    bridge_t		   *bridge;
+    bridgereg_t		    b_int_status;
+    bridgereg_t		    b_pci_err_lower;
+    bridgereg_t		    b_pci_err_upper;
+    iopaddr_t		    pci_addr;
+    pciio_slot_t	    slot;
+    pcibr_piomap_t	    map;
+    iopaddr_t		    base;
+    size_t		    size;
+    unsigned		    win;
+    int			    func;
+
+    bridge = soft->bs_base;
+    b_int_status = bridge->b_int_status;
+    if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+	b_pci_err_lower = bridge->b_pci_err_lower;
+	b_pci_err_upper = bridge->b_pci_err_upper;
+	b_int_status = bridge->b_int_status;
+	if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+
+	    pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
+	    pci_addr = (pci_addr << 32) | b_pci_err_lower;
+
+	    slot = 8;
+	    while (slot-- > 0) {
+		int 		nfunc = soft->bs_slot[slot].bss_ninfo;
+		pcibr_info_h	pcibr_infoh = soft->bs_slot[slot].bss_infos;
+
+		for (func = 0; func < nfunc; func++) {
+		    pcibr_info_t 	pcibr_info = pcibr_infoh[func];
+
+		    if (!pcibr_info)
+			continue;
+
+		    for (map = pcibr_info->f_piomap;
+			 map != NULL; map = map->bp_next) {
+			base = map->bp_pciaddr;
+			size = map->bp_mapsz;
+			win = map->bp_space - PCIIO_SPACE_WIN(0);
+			if (win < 6)
+			    base += 
+				soft->bs_slot[slot].bss_window[win].bssw_base;
+			else if (map->bp_space == PCIIO_SPACE_ROM)
+			    base += pcibr_info->f_rbase;
+			if ((pci_addr >= base) && (pci_addr < (base + size)))
+			    atomicAddInt(map->bp_toc, 1);
+		    }
+		}
+	    }
+	}
+    }
+}
+
+/*
+ * PCI Bridge Error interrupt handler.
+ *      This gets invoked, whenever a PCI bridge sends an error interrupt.
+ *      Primarily this servers two purposes.
+ *              - If an error can be handled (typically a PIO read/write
+ *                error, we try to do it silently.
+ *              - If an error cannot be handled, we die violently.
+ *      Interrupt due to PIO errors:
+ *              - Bridge sends an interrupt, whenever a PCI operation
+ *                done by the bridge as the master fails. Operations could
+ *                be either a PIO read or a PIO write.
+ *                PIO Read operation also triggers a bus error, and it's
+ *                We primarily ignore this interrupt in that context..
+ *                For PIO write errors, this is the only indication.
+ *                and we have to handle with the info from here.
+ *
+ *                So, there is no way to distinguish if an interrupt is
+ *                due to read or write error!.
+ */
+
+
+void
+pcibr_error_intr_handler(intr_arg_t arg)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    bridgereg_t             int_status;
+    bridgereg_t             err_status;
+    int                     i;
+
+    /* REFERENCED */
+    bridgereg_t             disable_errintr_mask = 0;
+    int 		    rv;
+    int 		    error_code = IOECODE_DMA | IOECODE_READ;
+    ioerror_mode_t 	    mode = MODE_DEVERROR;
+    ioerror_t 	            ioe;
+    nasid_t		    nasid;
+
+#if PCIBR_SOFT_LIST
+    {
+	extern pcibr_list_p	pcibr_list;
+	pcibr_list_p            entry;
+
+	entry = pcibr_list;
+	while (1) {
+	    if (entry == NULL) {
+		PRINT_PANIC(
+			"pcibr_error_intr_handler:\n"
+			"\tmy parameter (0x%x) is not a pcibr_soft!",
+			arg);
+	    }
+	    if ((intr_arg_t) entry->bl_soft == arg)
+		break;
+	    entry = entry->bl_next;
+	}
+    }
+#endif
+    pcibr_soft = (pcibr_soft_t) arg;
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * pcibr_error_intr_handler gets invoked whenever bridge encounters
+     * an error situation, and the interrupt for that error is enabled.
+     * This routine decides if the error is fatal or not, and takes
+     * action accordingly.
+     *
+     * In the case of PIO read/write timeouts, there is no way
+     * to know if it was a read or write request that timed out.
+     * If the error was due to a "read", a bus error will also occur
+     * and the bus error handling code takes care of it. 
+     * If the error is due to a "write", the error is currently logged 
+     * by this routine. For SN1 and SN0, if fire-and-forget mode is 
+     * disabled, a write error response xtalk packet will be sent to 
+     * the II, which will cause an II error interrupt. No write error 
+     * recovery actions of any kind currently take place at the pcibr 
+     * layer! (e.g., no panic on unrecovered write error)
+     *
+     * Prior to reading the Bridge int_status register we need to ensure
+     * that there are no error bits set in the lower layers (hubii)
+     * that have disabled PIO access to the widget. If so, there is nothing
+     * we can do until the bits clear, so we setup a timeout and try again
+     * later.
+     */
+
+    nasid = NASID_GET(bridge);
+    if (hubii_check_widget_disabled(nasid, pcibr_soft->bs_xid)) {
+	timeout(pcibr_error_intr_handler, pcibr_soft, BRIDGE_PIOERR_TIMEOUT);
+	pcibr_soft->bs_errinfo.bserr_toutcnt++;
+	return;
+    }
+
+    /* int_status is which bits we have to clear;
+     * err_status is the bits we haven't handled yet.
+     */
+
+    int_status = bridge->b_int_status &  ~BRIDGE_ISR_INT_MSK;
+    err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
+
+    if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
+	/*
+	 * No error bit set!!.
+	 */
+	return;
+    }
+    /*
+     * If we have a PCIBUS_PIOERR, hand it to the logger.
+     */
+    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+	pcibr_pioerr_check(pcibr_soft);
+    }
+
+    if (err_status) {
+	struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
+
+	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) {
+	    if (err_status & (1 << i)) {
+		uint32_t              errrate = 0;
+		uint32_t              errcount = 0;
+		uint32_t              errinterval = 0, current_tick = 0;
+		int                     llp_tx_retry_errors = 0;
+		int                     is_llp_tx_retry_intr = 0;
+
+		bs_estat->bs_errcount_total++;
+
+		current_tick = lbolt;
+		errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
+		errcount = (bs_estat->bs_errcount_total -
+			    bs_estat->bs_lasterr_snapshot);
+
+		is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i));
+
+		/* Check for the divide by zero condition while
+		 * calculating the error rates.
+		 */
+
+		if (errinterval) {
+		    errrate = errcount / errinterval;
+		    /* If able to calculate error rate
+		     * on a LLP transmitter retry interrupt, check
+		     * if the error rate is nonzero and we have seen
+		     * a certain minimum number of errors.
+		     *
+		     * NOTE : errcount is being compared to
+		     * PCIBR_ERRTIME_THRESHOLD to make sure that we are not
+		     * seeing cases like x error interrupts per y ticks for
+		     * very low x ,y (x > y ) which could result in a
+		     * rate > 100/tick.
+		     */
+		    if (is_llp_tx_retry_intr &&
+			errrate &&
+			(errcount >= PCIBR_ERRTIME_THRESHOLD)) {
+			llp_tx_retry_errors = 1;
+		    }
+		} else {
+		    errrate = 0;
+		    /* Since we are not able to calculate the
+		     * error rate check if we exceeded a certain
+		     * minimum number of errors for LLP transmitter
+		     * retries. Note that this can only happen
+		     * within the first tick after the last snapshot.
+		     */
+		    if (is_llp_tx_retry_intr &&
+			(errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
+			llp_tx_retry_errors = 1;
+		    }
+		}
+
+		/*
+		 * If a non-zero error rate (which is equivalent to
+		 * to 100 errors/tick at least) for the LLP transmitter
+		 * retry interrupt was seen, check if we should print
+		 * a warning message.
+		 */
+
+		if (llp_tx_retry_errors) {
+		    static uint32_t       last_printed_rate;
+
+		    if (errrate > last_printed_rate) {
+			last_printed_rate = errrate;
+			/* Print the warning only if the error rate
+			 * for the transmitter retry interrupt
+			 * exceeded the previously printed rate.
+			 */
+			printk(KERN_WARNING
+				"%s: %s, Excessive error interrupts : %d/tick\n",
+				pcibr_soft->bs_name,
+				pcibr_isr_errs[i],
+				errrate);
+
+		    }
+		    /*
+		     * Update snapshot, and time
+		     */
+		    bs_estat->bs_lasterr_timestamp = current_tick;
+		    bs_estat->bs_lasterr_snapshot =
+			bs_estat->bs_errcount_total;
+
+		}
+		/*
+		 * If the error rate is high enough, print the error rate.
+		 */
+		if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
+
+		    if (errrate > PCIBR_ERRRATE_THRESHOLD) {
+			printk(KERN_NOTICE "%s: %s, Error rate %d/tick",
+				pcibr_soft->bs_name,
+				pcibr_isr_errs[i],
+				errrate);
+			/*
+			 * Update snapshot, and time
+			 */
+			bs_estat->bs_lasterr_timestamp = current_tick;
+			bs_estat->bs_lasterr_snapshot =
+			    bs_estat->bs_errcount_total;
+		    }
+		}
+		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
+		    /*
+		     * We have seen a fairly large number of errors of
+		     * this type. Let's disable the interrupt. But flash
+		     * a message about the interrupt being disabled.
+		     */
+		    printk(KERN_NOTICE
+			    "%s Disabling error interrupt type %s. Error count %d",
+			    pcibr_soft->bs_name,
+			    pcibr_isr_errs[i],
+			    bs_estat->bs_errcount_total);
+		    disable_errintr_mask |= (1 << i);
+		}
+	    }
+	}
+    }
+
+    if (disable_errintr_mask) {
+	/*
+	 * Disable some high frequency errors as they
+	 * could eat up too much cpu time.
+	 */
+	bridge->b_int_enable &= ~disable_errintr_mask;
+    }
+    /*
+     * If we leave the PROM cacheable, T5 might
+     * try to do a cache line sized writeback to it,
+     * which will cause a BRIDGE_ISR_INVLD_ADDR.
+     */
+    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
+	(0x00000000 == bridge->b_wid_err_upper) &&
+	(0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
+	(0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
+	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
+    }
+#if defined (PCIBR_LLP_CONTROL_WAR)
+    /*
+     * The bridge bug, where the llp_config or control registers
+     * need to be read back after being written, affects an MP
+     * system since there could be small windows between writing
+     * the register and reading it back on one cpu while another
+     * cpu is fielding an interrupt. If we run into this scenario,
+     * workaround the problem by ignoring the error. (bug 454474)
+     * pcibr_llp_control_war_cnt keeps an approximate number of
+     * times we saw this problem on a system.
+     */
+
+    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
+	((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
+	 == (BRIDGE_INT_RST_STAT & 0xff0))) {
+#if 0
+	if (kdebug)
+	    printk(KERN_NOTICE "%s bridge: ignoring llp/control address interrupt",
+		    pcibr_soft->bs_name);
+#endif
+	pcibr_llp_control_war_cnt++;
+	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
+    }
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+#ifdef EHE_ENABLE
+    /* Check if this is the RESP_XTALK_ERROR interrupt. 
+     * This can happen due to a failed DMA READ operation.
+     */
+    if (err_status & BRIDGE_ISR_RESP_XTLK_ERR) {
+	/* Phase 1 : Look at the error state in the bridge and further
+	 * down in the device layers.
+	 */
+	(void)error_state_set(pcibr_soft->bs_conn, ERROR_STATE_LOOKUP);
+	IOERROR_SETVALUE(&ioe, widgetnum, pcibr_soft->bs_xid);
+	(void)pcibr_error_handler((error_handler_arg_t)pcibr_soft,
+				  error_code,
+				  mode,
+				  &ioe);
+	/* Phase 2 : Perform the action agreed upon in phase 1.
+	 */
+	(void)error_state_set(pcibr_soft->bs_conn, ERROR_STATE_ACTION);
+	rv = pcibr_error_handler((error_handler_arg_t)pcibr_soft,
+				 error_code,
+				 mode,
+				 &ioe);
+    }
+    if (rv != IOERROR_HANDLED) {
+#endif /* EHE_ENABLE */
+
+    /* Dump/Log Bridge error interrupt info */
+    if (err_status & bridge_errors_to_dump) {
+	printk("BRIDGE ERR_STATUS 0x%x\n", err_status);
+	pcibr_error_dump(pcibr_soft);
+    }
+
+    if (err_status & BRIDGE_ISR_ERROR_FATAL) {
+	machine_error_dump("");
+	cmn_err_tag(14, CE_PANIC, "PCI Bridge Error interrupt killed the system");
+	    /*NOTREACHED */
+    }
+
+#ifdef EHE_ENABLE
+    }
+#endif
+
+    /*
+     * We can't return without re-enabling the interrupt, since
+     * it would cause problems for devices like IOC3 (Lost
+     * interrupts ?.). So, just cleanup the interrupt, and
+     * use saved values later..
+     */
+    bridge->b_int_rst_stat = pcibr_errintr_group(int_status);
+
+    /* Zero out bserr_intstat field */
+    test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat, 0);
+}
+
+/*
+ * pcibr_addr_toslot
+ *      Given the 'pciaddr' find out which slot this address is
+ *      allocated to, and return the slot number.
+ *      While we have the info handy, construct the
+ *      function number, space code and offset as well.
+ *
+ * NOTE: if this routine is called, we don't know whether
+ * the address is in CFG, MEM, or I/O space. We have to guess.
+ * This will be the case on PIO stores, where the only way
+ * we have of getting the address is to check the Bridge, which
+ * stores the PCI address but not the space and not the xtalk
+ * address (from which we could get it).
+ */
+int
+pcibr_addr_toslot(pcibr_soft_t pcibr_soft,
+		  iopaddr_t pciaddr,
+		  pciio_space_t *spacep,
+		  iopaddr_t *offsetp,
+		  pciio_function_t *funcp)
+{
+    int                     s, f, w;
+    iopaddr_t               base;
+    size_t                  size;
+    pciio_piospace_t        piosp;
+
+    /*
+     * Check if the address is in config space
+     */
+
+    if ((pciaddr >= BRIDGE_CONFIG_BASE) && (pciaddr < BRIDGE_CONFIG_END)) {
+
+	if (pciaddr >= BRIDGE_CONFIG1_BASE)
+	    pciaddr -= BRIDGE_CONFIG1_BASE;
+	else
+	    pciaddr -= BRIDGE_CONFIG_BASE;
+
+	s = pciaddr / BRIDGE_CONFIG_SLOT_SIZE;
+	pciaddr %= BRIDGE_CONFIG_SLOT_SIZE;
+
+	if (funcp) {
+	    f = pciaddr / 0x100;
+	    pciaddr %= 0x100;
+	}
+	if (spacep)
+	    *spacep = PCIIO_SPACE_CFG;
+	if (offsetp)
+	    *offsetp = pciaddr;
+	if (funcp)
+	    *funcp = f;
+
+	return s;
+    }
+    for (s = 0; s < 8; s++) {
+	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
+	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
+
+	for (f = 0; f < nf; f++) {
+	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
+
+	    if (!pcibr_info)
+		continue;
+	    for (w = 0; w < 6; w++) {
+		if (pcibr_info->f_window[w].w_space
+		    == PCIIO_SPACE_NONE) {
+		    continue;
+		}
+		base = pcibr_info->f_window[w].w_base;
+		size = pcibr_info->f_window[w].w_size;
+
+		if ((pciaddr >= base) && (pciaddr < (base + size))) {
+		    if (spacep)
+			*spacep = PCIIO_SPACE_WIN(w);
+		    if (offsetp)
+			*offsetp = pciaddr - base;
+		    if (funcp)
+			*funcp = f;
+		    return s;
+		}			/* endif match */
+	    }				/* next window */
+	}				/* next func */
+    }					/* next slot */
+
+    /*
+     * Check if the address was allocated as part of the
+     * pcibr_piospace_alloc calls.
+     */
+    for (s = 0; s < 8; s++) {
+	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
+	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
+
+	for (f = 0; f < nf; f++) {
+	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
+
+	    if (!pcibr_info)
+		continue;
+	    piosp = pcibr_info->f_piospace;
+	    while (piosp) {
+		if ((piosp->start <= pciaddr) &&
+		    ((piosp->count + piosp->start) > pciaddr)) {
+		    if (spacep)
+			*spacep = piosp->space;
+		    if (offsetp)
+			*offsetp = pciaddr - piosp->start;
+		    return s;
+		}			/* endif match */
+		piosp = piosp->next;
+	    }				/* next piosp */
+	}				/* next func */
+    }					/* next slot */
+
+    /*
+     * Some other random address on the PCI bus ...
+     * we have no way of knowing whether this was
+     * a MEM or I/O access; so, for now, we just
+     * assume that the low 1G is MEM, the next
+     * 3G is I/O, and anything above the 4G limit
+     * is obviously MEM.
+     */
+
+    if (spacep)
+	*spacep = ((pciaddr < (1ul << 30)) ? PCIIO_SPACE_MEM :
+		   (pciaddr < (4ul << 30)) ? PCIIO_SPACE_IO :
+		   PCIIO_SPACE_MEM);
+    if (offsetp)
+	*offsetp = pciaddr;
+
+    return PCIIO_SLOT_NONE;
+
+}
+
+void
+pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    ASSERT(error_code & IOECODE_PIO);
+    error_code = error_code;
+
+    bridge->b_int_rst_stat =
+	(BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR);
+    (void) bridge->b_wid_tflush;	/* flushbus */
+}
+
+/*
+ * pcibr_error_extract
+ *      Given the 'pcibr vertex handle' find out which slot
+ *      the bridge status error address (from pcibr_soft info
+ *      hanging off the vertex)
+ *      allocated to, and return the slot number.
+ *      While we have the info handy, construct the
+ *      space code and offset as well.
+ *
+ * NOTE: if this routine is called, we don't know whether
+ * the address is in CFG, MEM, or I/O space. We have to guess.
+ * This will be the case on PIO stores, where the only way
+ * we have of getting the address is to check the Bridge, which
+ * stores the PCI address but not the space and not the xtalk
+ * address (from which we could get it).
+ *
+ * XXX- this interface has no way to return the function
+ * number on a multifunction card, even though that data
+ * is available.
+ */
+
+pciio_slot_t
+pcibr_error_extract(devfs_handle_t pcibr_vhdl,
+		    pciio_space_t *spacep,
+		    iopaddr_t *offsetp)
+{
+    pcibr_soft_t            pcibr_soft = 0;
+    iopaddr_t               bserr_addr;
+    bridge_t               *bridge;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+    arbitrary_info_t	    rev;
+
+    /* Do a sanity check as to whether we really got a 
+     * bridge vertex handle.
+     */
+    if (hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &rev) !=
+	GRAPH_SUCCESS) 
+	return(slot);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (pcibr_soft) {
+	bridge = pcibr_soft->bs_base;
+	bserr_addr =
+	    bridge->b_pci_err_lower |
+	    ((uint64_t) (bridge->b_pci_err_upper &
+			   BRIDGE_ERRUPPR_ADDRMASK) << 32);
+
+	slot = pcibr_addr_toslot(pcibr_soft, bserr_addr,
+				 spacep, offsetp, NULL);
+    }
+    return slot;
+}
+
+/*ARGSUSED */
+void
+pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
+{
+    /*
+     * XXX
+     * Device failed to handle error. Take steps to
+     * disable this device ? HOW TO DO IT ?
+     *
+     * If there are any Read response buffers associated
+     * with this device, it's time to get them back!!
+     *
+     * We can disassociate any interrupt level associated
+     * with this device, and disable that interrupt level
+     *
+     * For now it's just a place holder
+     */
+}
+
+/*
+ * pcibr_pioerror
+ *      Handle PIO error that happened at the bridge pointed by pcibr_soft.
+ *
+ *      Queries the Bus interface attached to see if the device driver
+ *      mapping the device-number that caused error can handle the
+ *      situation. If so, it will clean up any error, and return
+ *      indicating the error was handled. If the device driver is unable
+ *      to handle the error, it expects the bus-interface to disable that
+ *      device, and takes any steps needed here to take away any resources
+ *      associated with this device.
+ */
+
+#define BEM_ADD_STR(s)	printk("%s", (s))
+#define BEM_ADD_VAR(v)	printk("\t%20s: 0x%x\n", #v, (v))
+#define BEM_ADD_REG(r)	printk("\t%20s: %R\n", #r, (r), r ## _desc)
+
+#define BEM_ADD_NSPC(n,s)	printk("\t%20s: %R\n", n, s, space_desc)
+#define BEM_ADD_SPC(s)		BEM_ADD_NSPC(#s, s)
+
+/* BEM_ADD_IOE doesn't dump the whole ioerror, it just
+ * decodes the PCI specific portions -- we count on our
+ * callers to dump the raw IOE data.
+ */
+#define BEM_ADD_IOE(ioe)						\
+	do {								\
+	    if (IOERROR_FIELDVALID(ioe, busspace)) {			\
+		unsigned		spc;				\
+		unsigned		win;				\
+									\
+		spc = IOERROR_GETVALUE(ioe, busspace);			\
+		win = spc - PCIIO_SPACE_WIN(0);				\
+									\
+		switch (spc) {						\
+		case PCIIO_SPACE_CFG:					\
+		    printk(					\
+			    "\tPCI Slot %d Func %d CFG space Offset 0x%x\n",	\
+	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		case PCIIO_SPACE_IO:					\
+		    printk(					\
+			    "\tPCI I/O space  Offset 0x%x\n",		\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		case PCIIO_SPACE_MEM:					\
+		case PCIIO_SPACE_MEM32:					\
+		case PCIIO_SPACE_MEM64:					\
+		    printk(					\
+			    "\tPCI MEM space Offset 0x%x\n",		\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		default:						\
+		    if (win < 6) {					\
+		    printk(					\
+			    "\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\
+	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+			    win,					\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    }							\
+		    break;						\
+		}							\
+	    }								\
+	} while (0)
+
+/*ARGSUSED */
+int
+pcibr_pioerror(
+		  pcibr_soft_t pcibr_soft,
+		  int error_code,
+		  ioerror_mode_t mode,
+		  ioerror_t *ioe)
+{
+    int                     retval = IOERROR_HANDLED;
+
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    iopaddr_t               bad_xaddr;
+
+    pciio_space_t           raw_space;	/* raw PCI space */
+    iopaddr_t               raw_paddr;	/* raw PCI address */
+
+    pciio_space_t           space;	/* final PCI space */
+    pciio_slot_t            slot;	/* final PCI slot, if appropriate */
+    pciio_function_t        func;	/* final PCI func, if appropriate */
+    iopaddr_t               offset;	/* final PCI offset */
+    
+    int                     cs, cw, cf;
+    pciio_space_t           wx;
+    iopaddr_t               wb;
+    size_t                  ws;
+    iopaddr_t               wl;
+
+
+    /*
+     * We expect to have an "xtalkaddr" coming in,
+     * and need to construct the slot/space/offset.
+     */
+
+    bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr);
+
+    slot = PCIIO_SLOT_NONE;
+    func = PCIIO_FUNC_NONE;
+    raw_space = PCIIO_SPACE_NONE;
+    raw_paddr = 0;
+
+    if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) &&
+	(bad_xaddr < BRIDGE_TYPE1_CFG)) {
+	raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0;
+	slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
+	raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
+	raw_space = PCIIO_SPACE_CFG;
+    }
+    if ((bad_xaddr >= BRIDGE_TYPE1_CFG) &&
+	(bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) {
+	/* Type 1 config space:
+	 * slot and function numbers not known.
+	 * Perhaps we can read them back?
+	 */
+	raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG;
+	raw_space = PCIIO_SPACE_CFG;
+    }
+    if ((bad_xaddr >= BRIDGE_DEVIO0) &&
+	(bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) {
+	int                     x;
+
+	raw_paddr = bad_xaddr - BRIDGE_DEVIO0;
+	x = raw_paddr / BRIDGE_DEVIO_OFF;
+	raw_paddr %= BRIDGE_DEVIO_OFF;
+	/* first two devio windows are double-sized */
+	if ((x == 1) || (x == 3))
+	    raw_paddr += BRIDGE_DEVIO_OFF;
+	if (x > 0)
+	    x--;
+	if (x > 1)
+	    x--;
+	/* x is which devio reg; no guarantee
+	 * PCI slot x will be responding.
+	 * still need to figure out who decodes
+	 * space/offset on the bus.
+	 */
+	raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
+	if (raw_space == PCIIO_SPACE_NONE) {
+	    /* Someone got an error because they
+	     * accessed the PCI bus via a DevIO(x)
+	     * window that pcibr has not yet assigned
+	     * to any specific PCI address. It is
+	     * quite possible that the Device(x)
+	     * register has been changed since they
+	     * made their access, but we will give it
+	     * our best decode shot.
+	     */
+	    raw_space = pcibr_soft->bs_slot[x].bss_device
+		& BRIDGE_DEV_DEV_IO_MEM
+		? PCIIO_SPACE_MEM
+		: PCIIO_SPACE_IO;
+	    raw_paddr +=
+		(pcibr_soft->bs_slot[x].bss_device &
+		 BRIDGE_DEV_OFF_MASK) <<
+		BRIDGE_DEV_OFF_ADDR_SHFT;
+	} else
+	    raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
+	raw_space = PCIIO_SPACE_MEM32;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
+	raw_space = PCIIO_SPACE_MEM64;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
+	raw_space = PCIIO_SPACE_IO;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
+    }
+    space = raw_space;
+    offset = raw_paddr;
+
+    if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
+	/* we've got a space/offset but not which
+	 * PCI slot decodes it. Check through our
+	 * notions of which devices decode where.
+	 *
+	 * Yes, this "duplicates" some logic in
+	 * pcibr_addr_toslot; the difference is,
+	 * this code knows which space we are in,
+	 * and can really really tell what is
+	 * going on (no guessing).
+	 */
+
+	for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) {
+	    int                     nf = pcibr_soft->bs_slot[cs].bss_ninfo;
+	    pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
+
+	    for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
+		pcibr_info_t            pcibr_info = pcibr_infoh[cf];
+
+		if (!pcibr_info)
+		    continue;
+		for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
+		    if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
+			((wb = pcibr_info->f_window[cw].w_base) != 0) &&
+			((ws = pcibr_info->f_window[cw].w_size) != 0) &&
+			((wl = wb + ws) > wb) &&
+			((wb <= offset) && (wl > offset))) {
+			/* MEM, MEM32 and MEM64 need to
+			 * compare as equal ...
+			 */
+			if ((wx == space) ||
+			    (((wx == PCIIO_SPACE_MEM) ||
+			      (wx == PCIIO_SPACE_MEM32) ||
+			      (wx == PCIIO_SPACE_MEM64)) &&
+			     ((space == PCIIO_SPACE_MEM) ||
+			      (space == PCIIO_SPACE_MEM32) ||
+			      (space == PCIIO_SPACE_MEM64)))) {
+			    slot = cs;
+			    func = cf;
+			    space = PCIIO_SPACE_WIN(cw);
+			    offset -= wb;
+			}		/* endif window space match */
+		    }			/* endif window valid and addr match */
+		}			/* next window unless slot set */
+	    }				/* next func unless slot set */
+	}				/* next slot unless slot set */
+	/* XXX- if slot is still -1, no PCI devices are
+	 * decoding here using their standard PCI BASE
+	 * registers. This would be a really good place
+	 * to cross-coordinate with the pciio PCI
+	 * address space allocation routines, to find
+	 * out if this address is "allocated" by any of
+	 * our subsidiary devices.
+	 */
+    }
+    /* Scan all piomap records on this PCI bus to update
+     * the TimeOut Counters on all matching maps. If we
+     * don't already know the slot number, take it from
+     * the first matching piomap. Note that we have to
+     * compare maps against raw_space and raw_paddr
+     * since space and offset could already be
+     * window-relative.
+     *
+     * There is a chance that one CPU could update
+     * through this path, and another CPU could also
+     * update due to an interrupt. Closing this hole
+     * would only result in the possibility of some
+     * errors never getting logged at all, and since the
+     * use for bp_toc is as a logical test rather than a
+     * strict count, the excess counts are not a
+     * problem.
+     */
+    for (cs = 0; cs < 8; ++cs) {
+	int 		nf = pcibr_soft->bs_slot[cs].bss_ninfo;
+	pcibr_info_h	pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
+
+	for (cf = 0; cf < nf; cf++) {
+	    pcibr_info_t 	pcibr_info = pcibr_infoh[cf];
+	    pcibr_piomap_t	map;    
+
+	    if (!pcibr_info)
+		continue;
+
+	    for (map = pcibr_info->f_piomap;
+	     map != NULL; map = map->bp_next) {
+	    wx = map->bp_space;
+	    wb = map->bp_pciaddr;
+	    ws = map->bp_mapsz;
+	    cw = wx - PCIIO_SPACE_WIN(0);
+	    if (cw < 6) {
+		wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
+		wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
+	    }
+	    if (wx == PCIIO_SPACE_ROM) {
+		wb += pcibr_info->f_rbase;
+		wx = PCIIO_SPACE_MEM;
+	    }
+	    if ((wx == PCIIO_SPACE_MEM32) ||
+		(wx == PCIIO_SPACE_MEM64))
+		wx = PCIIO_SPACE_MEM;
+	    wl = wb + ws;
+	    if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
+		atomicAddInt(map->bp_toc, 1);
+		if (slot == PCIIO_SLOT_NONE) {
+		    slot = cs;
+		    space = map->bp_space;
+		    if (cw < 6)
+			offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
+		}
+	    }
+	    }
+	}
+    }
+
+    if (space != PCIIO_SPACE_NONE) {
+	if (slot != PCIIO_SLOT_NONE) 
+	    if (func != PCIIO_FUNC_NONE)
+		IOERROR_SETVALUE(ioe, widgetdev, 
+				 pciio_widgetdev_create(slot,func));
+	    else
+    		IOERROR_SETVALUE(ioe, widgetdev, 
+				 pciio_widgetdev_create(slot,0));
+
+	IOERROR_SETVALUE(ioe, busspace, space);
+	IOERROR_SETVALUE(ioe, busaddr, offset);
+    }
+    if (mode == MODE_DEVPROBE) {
+	/*
+	 * During probing, we don't really care what the
+	 * error is. Clean up the error in Bridge, notify
+	 * subsidiary devices, and return success.
+	 */
+	pcibr_error_cleanup(pcibr_soft, error_code);
+
+	/* if appropriate, give the error handler for this slot
+	 * a shot at this probe access as well.
+	 */
+	return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
+	    pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+    }
+    /*
+     * If we don't know what "PCI SPACE" the access
+     * was targeting, we may have problems at the
+     * Bridge itself. Don't touch any bridge registers,
+     * and do complain loudly.
+     */
+
+    if (space == PCIIO_SPACE_NONE) {
+	printk("XIO Bus Error at %s\n"
+		"\taccess to XIO bus offset 0x%x\n"
+		"\tdoes not correspond to any PCI address\n",
+		pcibr_soft->bs_name, bad_xaddr);
+
+	/* caller will dump contents of ioe struct */
+	return IOERROR_XTALKLEVEL;
+    }
+
+    /*
+     * Actual PCI Error handling situation.
+     * Typically happens when a user level process accesses
+     * PCI space, and it causes some error.
+     *
+     * Due to PCI Bridge implementation, we get two indication
+     * for a read error: an interrupt and a Bus error.
+     * We like to handle read error in the bus error context.
+     * But the interrupt comes and goes before bus error
+     * could make much progress. (NOTE: interrupd does
+     * come in _after_ bus error processing starts. But it's
+     * completed by the time bus error code reaches PCI PIO
+     * error handling.
+     * Similarly write error results in just an interrupt,
+     * and error handling has to be done at interrupt level.
+     * There is no way to distinguish at interrupt time, if an
+     * error interrupt is due to read/write error..
+     */
+
+    /* We know the xtalk addr, the raw PCI bus space,
+     * the raw PCI bus address, the decoded PCI bus
+     * space, the offset within that space, and the
+     * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
+     * is known to be involved).
+     */
+
+    /*
+     * Hand the error off to the handler registered
+     * for the slot that should have decoded the error,
+     * or to generic PCI handling (if pciio decides that
+     * such is appropriate).
+     */
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+
+    if (retval != IOERROR_HANDLED) {
+
+	/* Generate a generic message for IOERROR_UNHANDLED
+	 * since the subsidiary handlers were silent, and
+	 * did no recovery.
+	 */
+	if (retval == IOERROR_UNHANDLED) {
+	    retval = IOERROR_PANIC;
+
+	    /* we may or may not want to print some of this,
+	     * depending on debug level and which error code.
+	     */
+
+	    printk(KERN_ALERT
+		    "PIO Error on PCI Bus %s",
+		    pcibr_soft->bs_name);
+	    /* this decodes part of the ioe; our caller
+	     * will dump the raw details in DEBUG and
+	     * kdebug kernels.
+	     */
+	    BEM_ADD_IOE(ioe);
+	}
+#if defined(FORCE_ERRORS)
+	if (0) {
+#elif !DEBUG
+	if (kdebug) {
+#endif
+	    /*
+	     * Dump raw data from Bridge/PCI layer.
+	     */
+
+	    BEM_ADD_STR("Raw info from Bridge/PCI layer:\n");
+	    if (bridge->b_int_status & BRIDGE_ISR_PCIBUS_PIOERR)
+		pcibr_error_dump(pcibr_soft);
+	    BEM_ADD_SPC(raw_space);
+	    BEM_ADD_VAR(raw_paddr);
+	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {
+
+		slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, 
+								 widgetdev));
+		func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, 
+								 widgetdev));
+		if (slot < 8) {
+		    bridgereg_t             device = bridge->b_device[slot].reg;
+
+		    BEM_ADD_VAR(slot);
+		    BEM_ADD_VAR(func);
+		    BEM_ADD_REG(device);
+		}
+	    }
+#if !DEBUG || defined(FORCE_ERRORS)
+	}
+#endif
+
+	/*
+	 * Since error could not be handled at lower level,
+	 * error data logged has not  been cleared.
+	 * Clean up errors, and
+	 * re-enable bridge to interrupt on error conditions.
+	 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
+	 * dependent on INT_ENABLE register. This write just makes sure
+	 * that if the interrupt was enabled, we do get the interrupt.
+	 *
+	 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
+	 *      a group of interrupts. If while handling this error,
+	 *      some other error has occured, that would be
+	 *      implicitly cleared by this write.
+	 *      Need a way to ensure we don't inadvertently clear some
+	 *      other errors.
+	 */
+	if (IOERROR_FIELDVALID(ioe, widgetdev))
+	    pcibr_device_disable(pcibr_soft, 
+				 pciio_widgetdev_slot_get(
+					  IOERROR_GETVALUE(ioe, widgetdev)));
+
+	if (mode == MODE_DEVUSERERROR)
+	    pcibr_error_cleanup(pcibr_soft, error_code);
+    }
+    return retval;
+}
+
+/*
+ * bridge_dmaerror
+ *      Some error was identified in a DMA transaction.
+ *      This routine will identify the <device, address> that caused the error,
+ *      and try to invoke the appropriate bus service to handle this.
+ */
+
+#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+
+int
+pcibr_dmard_error(
+		     pcibr_soft_t pcibr_soft,
+		     int error_code,
+		     ioerror_mode_t mode,
+		     ioerror_t *ioe)
+{
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             bus_lowaddr, bus_uppraddr;
+    int                     retval = 0;
+    int                     bufnum;
+
+    /*
+     * In case of DMA errors, bridge should have logged the
+     * address that caused the error.
+     * Look up the address, in the bridge error registers, and
+     * take appropriate action
+     */
+    ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid);
+    ASSERT(bridge);
+
+    /*
+     * read error log registers
+     */
+    bus_lowaddr = bridge->b_wid_resp_lower;
+    bus_uppraddr = bridge->b_wid_resp_upper;
+
+    bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
+    IOERROR_SETVALUE(ioe, widgetdev, 
+		     pciio_widgetdev_create(
+				    BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
+				    0));
+    IOERROR_SETVALUE(ioe, busaddr,
+		     (bus_lowaddr |
+		      ((iopaddr_t)
+		       (bus_uppraddr &
+			BRIDGE_ERRUPPR_ADDRMASK) << 32)));
+
+    /*
+     * need to ensure that the xtalk adress in ioe
+     * maps to PCI error address read from bridge.
+     * How to convert PCI address back to Xtalk address ?
+     * (better idea: convert XTalk address to PCI address
+     * and then do the compare!)
+     */
+
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+    if (retval != IOERROR_HANDLED)
+	pcibr_device_disable(pcibr_soft, 
+			     pciio_widgetdev_slot_get(
+				      IOERROR_GETVALUE(ioe,widgetdev)));
+
+    /*
+     * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
+     * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
+     * not is dependent on INT_ENABLE register. This write just makes sure
+     * that if the interrupt was enabled, we do get the interrupt.
+     */
+    bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
+
+    /*
+     * Also, release the "bufnum" back to buffer pool that could be re-used.
+     * This is done by "disabling" the buffer for a moment, then restoring
+     * the original assignment.
+     */
+
+    {
+	reg_p                   regp;
+	bridgereg_t             regv;
+	bridgereg_t             mask;
+
+	regp = (bufnum & 1)
+	    ? &bridge->b_odd_resp
+	    : &bridge->b_even_resp;
+
+	mask = 0xF << ((bufnum >> 1) * 4);
+
+	regv = *regp;
+	*regp = regv & ~mask;
+	*regp = regv;
+    }
+
+    return retval;
+}
+
+/*
+ * pcibr_dmawr_error:
+ *      Handle a dma write error caused by a device attached to this bridge.
+ *
+ *      ioe has the widgetnum, widgetdev, and memaddr fields updated
+ *      But we don't know the PCI address that corresponds to "memaddr"
+ *      nor do we know which device driver is generating this address.
+ *
+ *      There is no easy way to find out the PCI address(es) that map
+ *      to a specific system memory address. Bus handling code is also
+ *      of not much help, since they don't keep track of the DMA mapping
+ *      that have been handed out.
+ *      So it's a dead-end at this time.
+ *
+ *      If translation is available, we could invoke the error handling
+ *      interface of the device driver.
+ */
+/*ARGSUSED */
+int
+pcibr_dmawr_error(
+		     pcibr_soft_t pcibr_soft,
+		     int error_code,
+		     ioerror_mode_t mode,
+		     ioerror_t *ioe)
+{
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    int                     retval;
+
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+
+    if (retval != IOERROR_HANDLED) {
+	pcibr_device_disable(pcibr_soft, 
+			     pciio_widgetdev_slot_get(
+				      IOERROR_GETVALUE(ioe, widgetdev)));
+
+    }
+    return retval;
+}
+
+/*
+ * Bridge error handler.
+ *      Interface to handle all errors that involve bridge in some way.
+ *
+ *      This normally gets called from xtalk error handler.
+ *      ioe has different set of fields set depending on the error that
+ *      was encountered. So, we have a bit field indicating which of the
+ *      fields are valid.
+ *
+ * NOTE: This routine could be operating in interrupt context. So,
+ *      don't try to sleep here (till interrupt threads work!!)
+ */
+int
+pcibr_error_handler(
+		       error_handler_arg_t einfo,
+		       int error_code,
+		       ioerror_mode_t mode,
+		       ioerror_t *ioe)
+{
+    pcibr_soft_t            pcibr_soft;
+    int                     retval = IOERROR_BADERRORCODE;
+
+#ifdef EHE_ENABLE
+    devfs_handle_t	    xconn_vhdl,pcibr_vhdl;
+    error_state_t	    e_state;
+#endif /* EHE_ENABLE */
+
+    pcibr_soft = (pcibr_soft_t) einfo;
+
+#ifdef EHE_ENABLE
+    xconn_vhdl = pcibr_soft->bs_conn;
+    pcibr_vhdl = pcibr_soft->bs_vhdl;
+
+    e_state = error_state_get(xconn_vhdl);
+    
+    if (error_state_set(pcibr_vhdl, e_state) == 
+	ERROR_RETURN_CODE_CANNOT_SET_STATE)
+	return(IOERROR_UNHANDLED);
+
+    /* If we are in the action handling phase clean out the error state
+     * on the xswitch.
+     */
+    if (e_state == ERROR_STATE_ACTION)
+	(void)error_state_set(xconn_vhdl, ERROR_STATE_NONE);
+#endif /* EHE_ENABLE */
+
+#if DEBUG && ERROR_DEBUG
+    printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name);
+#endif
+
+    ASSERT(pcibr_soft != NULL);
+
+    if (error_code & IOECODE_PIO)
+	retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
+
+    if (error_code & IOECODE_DMA) {
+	if (error_code & IOECODE_READ) {
+	    /*
+	     * DMA read error occurs when a device attached to the bridge
+	     * tries to read some data from system memory, and this
+	     * either results in a timeout or access error.
+	     * First case is indicated by the bit "XREAD_REQ_TOUT"
+	     * and second case by "RESP_XTALK_ERROR" bit in bridge error
+	     * interrupt status register.
+	     *
+	     * pcibr_error_intr_handler would get invoked first, and it has
+	     * the responsibility of calling pcibr_error_handler with
+	     * suitable parameters.
+	     */
+
+	    retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
+	}
+	if (error_code & IOECODE_WRITE) {
+	    /*
+	     * A device attached to this bridge has been generating
+	     * bad DMA writes. Find out the device attached, and
+	     * slap on it's wrist.
+	     */
+
+	    retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
+	}
+    }
+    return retval;
+
+}
+
+/*
+ * Reenable a device after handling the error.
+ * This is called by the lower layers when they wish to be reenabled
+ * after an error.
+ * Note that each layer would be calling the previous layer to reenable
+ * first, before going ahead with their own re-enabling.
+ */
+
+int
+pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    ASSERT(error_code & IOECODE_PIO);
+
+    /* If the error is not known to be a write,
+     * we have to call devenable.
+     * write errors are isolated to the bridge.
+     */
+    if (!(error_code & IOECODE_WRITE)) {
+	devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+	int                     rc;
+
+	rc = xtalk_error_devenable(xconn_vhdl, pciio_slot, error_code);
+	if (rc != IOERROR_HANDLED)
+	    return rc;
+    }
+    pcibr_error_cleanup(pcibr_soft, error_code);
+    return IOERROR_HANDLED;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,204 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+pcibr_hints_t           pcibr_hints_get(devfs_handle_t, int);
+void                    pcibr_hints_fix_rrbs(devfs_handle_t);
+void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+void                    pcibr_hints_handsoff(devfs_handle_t);
+void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+
+pcibr_hints_t
+pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
+{
+    arbitrary_info_t        ainfo = 0;
+    graph_error_t	    rv;
+    pcibr_hints_t           hint;
+
+    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+
+    if (alloc && (rv != GRAPH_SUCCESS)) {
+
+	NEW(hint);
+	hint->rrb_alloc_funct = NULL;
+	hint->ph_intr_bits = NULL;
+	rv = hwgraph_info_add_LBL(xconn_vhdl, 
+				  INFO_LBL_PCIBR_HINTS, 	
+				  (arbitrary_info_t) hint);
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+	
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	if (ainfo != (arbitrary_info_t) hint)
+	    goto abnormal_exit;
+    }
+    return (pcibr_hints_t) ainfo;
+
+abnormal_exit:
+#ifdef LATER
+    printf("SHOULD NOT BE HERE\n");
+#endif
+    DEL(hint);
+    return(NULL);
+
+}
+
+void
+pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_rrb_fixed = mask;
+#if DEBUG
+    else
+	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
+}
+
+void
+pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
+		     pciio_slot_t host,
+		     pciio_slot_t guest)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_host_slot[guest] = host + 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
+		      pcibr_intr_bits_f *xxx_intr_bits)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_intr_bits = xxx_intr_bits;
+#if DEBUG
+    else
+	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
+	       "\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->rrb_alloc_funct = rrb_alloc_funct;
+}
+
+void
+pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_hands_off = 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
+		    pciio_slot_t slot,
+		    uint64_t subdevs)
+{
+    arbitrary_info_t        ainfo = 0;
+    char                    sdname[16];
+    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
+
+    sprintf(sdname, "pci/%d", slot);
+    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
+    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
+#if DEBUG
+	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
+		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
+#endif
+	return;
+    }
+    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+    if (ainfo == 0) {
+	uint64_t                *subdevp;
+
+	NEW(subdevp);
+	if (!subdevp) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+	*subdevp = subdevs;
+	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
+	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+	if (ainfo == (arbitrary_info_t) subdevp)
+	    return;
+	DEL(subdevp);
+	if (ainfo == (arbitrary_info_t) NULL) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+#if DEBUG
+	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
+		"\t%p\n", pconn_vhdl);
+#endif
+    }
+    *(uint64_t *) ainfo = subdevs;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,147 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef LATER
+
+char *pci_space[] = {"NONE", 
+		     "ROM",
+		     "IO",
+		     "",
+		     "MEM",
+		     "MEM32",
+		     "MEM64",
+		     "CFG",
+		     "WIN0",
+		     "WIN1",
+		     "WIN2",
+		     "WIN3",
+		     "WIN4",
+		     "WIN5",
+		     "",
+		     "BAD"};
+
+void
+idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
+{
+    pcibr_info_t	pcibr_info = pcibr_infoh[func];
+    char		name[MAXDEVNAME];
+    int			win;
+    
+    if (!pcibr_info)
+	return;
+    qprintf("Per-slot Function Info\n");
+    sprintf(name, "%v", pcibr_info->f_vertex);
+    qprintf("\tSlot Name : %s\n",name);
+    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
+    qprintf("Slot : %d ", pcibr_info->f_slot);
+    qprintf("Function : %d ", pcibr_info->f_func);
+    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
+    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
+    sprintf(name, "%v", pcibr_info->f_master);
+    qprintf("\tBus provider : %s\n",name);
+    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
+    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
+	    pcibr_info->f_efunc,pcibr_info->f_einfo);
+    for(win = 0 ; win < 6 ; win++) 
+	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
+		win,pci_space[pcibr_info->f_window[win].w_space],
+		pcibr_info->f_window[win].w_base,
+		pcibr_info->f_window[win].w_size);
+
+    qprintf("\tRom base 0x%x size 0x%x\n", 
+	    pcibr_info->f_rbase,pcibr_info->f_rsize);
+
+    qprintf("\tInterrupt Bit Map\n");
+    qprintf("\t\tPCI Int#\tBridge Pin#\n");
+    for (win = 0 ; win < 4; win++)
+	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
+    qprintf("\n");
+}
+
+
+void
+idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
+{
+    pcibr_soft_slot_t	pss;
+    char		slot_conn_name[MAXDEVNAME];
+    int			func;
+
+    pss = &pcibr_soft->bs_slot[slot];
+    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
+    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
+    qprintf("\tHost Slot : %d\n",pss->host_slot);
+    sprintf(slot_conn_name, "%v", pss->slot_conn);
+    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
+    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
+    for (func = 0; func < pss->bss_ninfo; func++)
+	idbg_pss_func(pss->bss_infos,func);
+    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
+    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
+    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
+    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
+	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
+    
+    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
+	    "d32_base 0x%x d32_flags 0x%x\n",
+	    pss->bss_d64_base, pss->bss_d64_flags,
+	    pss->bss_d32_base, pss->bss_d32_flags);
+    
+    qprintf("\tExt ATEs active ? %s", 
+	    pss->bss_ext_ates_active ? "yes" : "no");
+    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
+    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
+
+    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
+	    pcibr_soft->bs_rrb_valid[slot],
+	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+		
+}
+
+int	ips = 0;
+
+void
+idbg_pss(pcibr_soft_t pcibr_soft)
+{
+    pciio_slot_t	slot;
+
+    
+    if (ips >= 0 && ips < 8)
+	idbg_pss_info(pcibr_soft,ips);
+    else if (ips < 0)
+	for (slot = 0; slot < 8; slot++) 
+	    idbg_pss_info(pcibr_soft,slot);
+    else
+	qprintf("Invalid ips %d\n",ips);
+}
+#endif	/* LATER */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,907 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+void                    pcibr_intr_free(pcibr_intr_t);
+void              pcibr_setpciint(xtalk_intr_t);
+int                     pcibr_intr_connect(pcibr_intr_t);
+void                    pcibr_intr_disconnect(pcibr_intr_t);
+
+devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
+void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+void                    pcibr_intr_func(intr_arg_t);
+
+extern pcibr_info_t      pcibr_info_get(devfs_handle_t);
+
+/* =====================================================================
+ *    INTERRUPT MANAGEMENT
+ */
+
+unsigned
+pcibr_intr_bits(pciio_info_t info,
+		pciio_intr_line_t lines)
+{
+    pciio_slot_t            slot = pciio_info_slot_get(info);
+    unsigned		    bbits = 0;
+
+    /*
+     * Currently favored mapping from PCI
+     * slot number and INTA/B/C/D to Bridge
+     * PCI Interrupt Bit Number:
+     *
+     *     SLOT     A B C D
+     *      0       0 4 0 4
+     *      1       1 5 1 5
+     *      2       2 6 2 6
+     *      3       3 7 3 7
+     *      4       4 0 4 0
+     *      5       5 1 5 1
+     *      6       6 2 6 2
+     *      7       7 3 7 3
+     */
+
+    if (slot < 8) {
+	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
+	    bbits |= 1 << slot;
+	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
+	    bbits |= 1 << (slot ^ 4);
+    }
+    return bbits;
+}
+
+
+/*
+ *	Get the next wrapper pointer queued in the interrupt circular buffer.
+ */
+pcibr_intr_wrap_t
+pcibr_wrap_get(pcibr_intr_cbuf_t cbuf)
+{
+    pcibr_intr_wrap_t	wrap;
+
+	if (cbuf->ib_in == cbuf->ib_out)
+	    PRINT_PANIC( "pcibr intr circular buffer empty, cbuf=0x%p, ib_in=ib_out=%d\n",
+		(void *)cbuf, cbuf->ib_out);
+
+	wrap = cbuf->ib_cbuf[cbuf->ib_out++];
+	cbuf->ib_out = cbuf->ib_out % IBUFSIZE;
+	return(wrap);
+}
+
+/* 
+ *	Queue a wrapper pointer in the interrupt circular buffer.
+ */
+void
+pcibr_wrap_put(pcibr_intr_wrap_t wrap, pcibr_intr_cbuf_t cbuf)
+{
+	int	in;
+	int	s;
+
+	/*
+	 * Multiple CPUs could be executing this code simultaneously
+	 * if a handler has registered multiple interrupt lines and
+	 * the interrupts are directed to different CPUs.
+	 */
+	s = mutex_spinlock(&cbuf->ib_lock);
+	in = (cbuf->ib_in + 1) % IBUFSIZE;
+	if (in == cbuf->ib_out) 
+	    PRINT_PANIC( "pcibr intr circular buffer full, cbuf=0x%p, ib_in=%d\n",
+		(void *)cbuf, cbuf->ib_in);
+
+	cbuf->ib_cbuf[cbuf->ib_in] = wrap;
+	cbuf->ib_in = in;
+	mutex_spinunlock(&cbuf->ib_lock, s);
+	return;
+}
+
+/*
+ *	There are end cases where a deadlock can occur if interrupt 
+ *	processing completes and the Bridge b_int_status bit is still set.
+ *
+ *	One scenerio is if a second PCI interrupt occurs within 60ns of
+ *	the previous interrupt being cleared. In this case the Bridge
+ *	does not detect the transition, the Bridge b_int_status bit
+ *	remains set, and because no transition was detected no interrupt
+ *	packet is sent to the Hub/Heart.
+ *
+ *	A second scenerio is possible when a b_int_status bit is being
+ *	shared by multiple devices:
+ *						Device #1 generates interrupt
+ *						Bridge b_int_status bit set
+ *						Device #2 generates interrupt
+ *		interrupt processing begins
+ *		  ISR for device #1 runs and
+ *			clears interrupt
+ *						Device #1 generates interrupt
+ *		  ISR for device #2 runs and
+ *			clears interrupt
+ *						(b_int_status bit still set)
+ *		interrupt processing completes
+ *		  
+ *	Interrupt processing is now complete, but an interrupt is still
+ *	outstanding for Device #1. But because there was no transition of
+ *	the b_int_status bit, no interrupt packet will be generated and
+ *	a deadlock will occur.
+ *
+ *	To avoid these deadlock situations, this function is used
+ *	to check if a specific Bridge b_int_status bit is set, and if so,
+ *	cause the setting of the corresponding interrupt bit.
+ *
+ *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
+ *	Interrupt register.
+ */
+void
+pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
+{
+	unsigned	bit;
+	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
+	bridge_t       *bridge = pcibr_soft->bs_base;
+	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
+
+	bit = wrap->iw_intr;
+
+	if (pcibr_soft->bs_xbridge) {
+	    bridge->b_force_pin[bit].intr = 1;
+	} else if ((1 << bit) & *wrap->iw_stat) {
+	    cpuid_t	    cpu;
+	    unsigned        intr_bit;
+	    xtalk_intr_t    xtalk_intr =
+				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
+
+	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
+	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
+#endif
+	}
+}
+
+/*ARGSUSED */
+pcibr_intr_t
+pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
+		 device_desc_t dev_desc,
+		 pciio_intr_line_t lines,
+		 devfs_handle_t owner_dev)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     is_threaded = 0;
+    int                     thread_swlevel;
+
+    xtalk_intr_t           *xtalk_intr_p;
+    pcibr_intr_t           *pcibr_intr_p;
+    pcibr_intr_list_t      *intr_list_p;
+
+    unsigned                pcibr_int_bits;
+    unsigned                pcibr_int_bit;
+    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
+    hub_intr_t		    hub_intr;
+    pcibr_intr_t            pcibr_intr;
+    pcibr_intr_list_t       intr_entry;
+    pcibr_intr_list_t       intr_list;
+    bridgereg_t             int_dev;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_alloc\n"
+	    "%v:%s%s%s%s%s\n",
+	    owner_dev, pconn_vhdl,
+	    !(lines & 15) ? " No INTs?" : "",
+	    lines & 1 ? " INTA" : "",
+	    lines & 2 ? " INTB" : "",
+	    lines & 4 ? " INTC" : "",
+	    lines & 8 ? " INTD" : "");
+#endif
+
+    NEW(pcibr_intr);
+    if (!pcibr_intr)
+	return NULL;
+
+    if (dev_desc) {
+	cpuid_t intr_target_from_desc(device_desc_t, int);
+    } else {
+	extern int default_intr_pri;
+
+	is_threaded = 1; /* PCI interrupts are threaded, by default */
+	thread_swlevel = default_intr_pri;
+    }
+
+    pcibr_intr->bi_dev = pconn_vhdl;
+    pcibr_intr->bi_lines = lines;
+    pcibr_intr->bi_soft = pcibr_soft;
+    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
+    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
+    pcibr_intr->bi_mustruncpu = CPU_NONE;
+    pcibr_intr->bi_ibuf.ib_in = 0;
+    pcibr_intr->bi_ibuf.ib_out = 0;
+    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
+
+    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
+
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+#if DEBUG && INTR_DEBUG
+    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
+#endif 
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    xtalk_intr = *xtalk_intr_p;
+
+	    if (xtalk_intr == NULL) {
+		/*
+		 * This xtalk_intr_alloc is constrained for two reasons:
+		 * 1) Normal interrupts and error interrupts need to be delivered
+		 *    through a single xtalk target widget so that there aren't any
+		 *    ordering problems with DMA, completion interrupts, and error
+		 *    interrupts. (Use of xconn_vhdl forces this.)
+		 *
+		 * 2) On IP35, addressing constraints on IP35 and Bridge force
+		 *    us to use a single PI number for all interrupts from a
+		 *    single Bridge. (IP35-specific code forces this, and we
+		 *    verify in pcibr_setwidint.)
+		 */
+
+		/*
+		 * All code dealing with threaded PCI interrupt handlers
+		 * is located at the pcibr level. Because of this,
+		 * we always want the lower layers (hub/heart_intr_alloc, 
+		 * intr_level_connect) to treat us as non-threaded so we
+		 * don't set up a duplicate threaded environment. We make
+		 * this happen by calling a special xtalk interface.
+		 */
+		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
+			owner_dev);
+#if DEBUG && INTR_DEBUG
+		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
+#endif
+
+		/* both an assert and a runtime check on this:
+		 * we need to check in non-DEBUG kernels, and
+		 * the ASSERT gets us more information when
+		 * we use DEBUG kernels.
+		 */
+		ASSERT(xtalk_intr != NULL);
+		if (xtalk_intr == NULL) {
+		    /* it is quite possible that our
+		     * xtalk_intr_alloc failed because
+		     * someone else got there first,
+		     * and we can find their results
+		     * in xtalk_intr_p.
+		     */
+		    if (!*xtalk_intr_p) {
+#ifdef SUPPORT_PRINTING_V_FORMAT
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
+				xconn_vhdl);
+#else
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc 0x%p: unable to get xtalk interrupt resources",
+				(void *)xconn_vhdl);
+#endif
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
+		    /*
+		     * now tell the bridge which slot is
+		     * using this interrupt line.
+		     */
+		    int_dev = bridge->b_int_device;
+		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
+		    bridge->b_int_device = int_dev;	/* XXXMP */
+
+#if DEBUG && INTR_DEBUG
+		    printk("%v: bridge intr bit %d clears my wrb\n",
+			    pconn_vhdl, pcibr_int_bit);
+#endif
+		} else {
+		    /* someone else got one allocated first;
+		     * free the one we just created, and
+		     * retrieve the one they allocated.
+		     */
+		    xtalk_intr_free(xtalk_intr);
+		    xtalk_intr = *xtalk_intr_p;
+#if PARANOID
+		    /* once xtalk_intr is set, we never clear it,
+		     * so if the CAS fails above, this condition
+		     * can "never happen" ...
+		     */
+		    if (!xtalk_intr) {
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
+				xconn_vhdl);
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+#endif
+		}
+	    }
+
+	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
+
+	    NEW(intr_entry);
+	    intr_entry->il_next = NULL;
+	    intr_entry->il_intr = pcibr_intr;
+	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
+	    intr_list_p = 
+		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+#if DEBUG && INTR_DEBUG
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#else
+	    printk("%v: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#endif
+#endif
+
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the first interrupt on this bridge bit.
+		 */
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list = *intr_list_p;
+	    pcibr_intr_p = &intr_list->il_intr;
+	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		/* first entry on list was erased,
+		 * and we replaced it, so we
+		 * don't need our intr_entry.
+		 */
+		DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list_p = &intr_list->il_next;
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the new second interrupt on this bit.
+		 */
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    while (1) {
+		pcibr_intr_p = &intr_list->il_intr;
+		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		    /* an entry on list was erased,
+		     * and we replaced it, so we
+		     * don't need our intr_entry.
+		     */
+		    DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		intr_list_p = &intr_list->il_next;
+		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		    /* entry appended to share list
+		     */
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		/* step to next record in chain
+		 */
+		intr_list = *intr_list_p;
+	    }
+	}
+    }
+
+#if DEBUG && INTR_DEBUG
+    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
+#endif
+    hub_intr = (hub_intr_t)xtalk_intr;
+    pcibr_intr->bi_irq = hub_intr->i_bit;
+    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
+    return pcibr_intr;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_free(pcibr_intr_t pcibr_intr)
+{
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bit;
+    pcibr_intr_list_t       intr_list;
+    int			    intr_shared;
+    xtalk_intr_t	    *xtalk_intrp;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    for (intr_list = 
+		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+		 intr_list != NULL;
+		 intr_list = intr_list->il_next)
+		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
+					 pcibr_intr, 
+					 NULL)) {
+#if DEBUG && INTR_DEBUG
+		    printk("%s: cleared a handler from bit %d\n",
+			    pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+		}
+	    /* If this interrupt line is not being shared between multiple
+	     * devices release the xtalk interrupt resources.
+	     */
+	    intr_shared = 
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
+	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    if ((!intr_shared) && (*xtalk_intrp)) {
+
+		bridge_t 	*bridge = pcibr_soft->bs_base;
+		bridgereg_t	int_dev;
+
+		xtalk_intr_free(*xtalk_intrp);
+		*xtalk_intrp = 0;
+
+		/* Clear the PCI device interrupt to bridge interrupt pin
+		 * mapping.
+		 */
+		int_dev = bridge->b_int_device;
+		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		bridge->b_int_device = int_dev;
+
+	    }
+	}
+    }
+    DEL(pcibr_intr);
+}
+
+void
+pcibr_setpciint(xtalk_intr_t xtalk_intr)
+{
+    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
+    bridgereg_t            *int_addr = (bridgereg_t *)
+    xtalk_intr_sfarg_get(xtalk_intr);
+
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+}
+
+/*ARGSUSED */
+int
+pcibr_intr_connect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    if (pcibr_intr == NULL)
+	return -1;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_connect\n",
+	    pcibr_intr->bi_dev);
+#endif
+
+    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_t            xtalk_intr;
+
+	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    /*
+	     * If this interrupt line is being shared and the connect has
+	     * already been done, no need to do it again.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
+		continue;
+
+
+	    /*
+	     * Use the pcibr wrapper function to handle all Bridge interrupts
+	     * regardless of whether the interrupt line is shared or not.
+	     */
+	    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint,
+			       (void *)&(bridge->b_int_addr[pcibr_int_bit].addr));
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%v bridge bit %d wrapper connected\n",
+		    pcibr_intr->bi_dev, pcibr_int_bit);
+#endif
+	}
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable |= pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    /* Stop calling the function. Now.
+     */
+    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and disconnect the interrupt.
+     */
+
+    /* don't disable interrupts for lines that
+     * are shared between devices.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
+	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
+	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
+    if (!pcibr_int_bits)
+	return;
+
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable &= ~pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    /* if the interrupt line is now shared,
+	     * do not disconnect it.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
+		pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+
+	    /* if we are sharing the interrupt line,
+	     * connect us up; this closes the hole
+	     * where the another pcibr_intr_alloc()
+	     * was in progress as we disconnected.
+	     */
+	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
+			       (xtalk_intr_setfunc_t)pcibr_setpciint,
+			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr));
+	}
+}
+
+/*ARGSUSED */
+devfs_handle_t
+pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit))
+	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+    return 0;
+}
+
+/* =====================================================================
+ *    INTERRUPT HANDLING
+ */
+void
+pcibr_clearwidint(bridge_t *bridge)
+{
+    bridge->b_wid_int_upper = 0;
+    bridge->b_wid_int_lower = 0;
+}
+
+
+void
+pcibr_setwidint(xtalk_intr_t intr)
+{
+    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
+    iopaddr_t               addr = xtalk_intr_addr_get(intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
+    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
+    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
+
+    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
+
+    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+			       XTALK_ADDR_TO_UPPER(addr));
+    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+
+    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
+    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
+
+    /* Verify that all interrupts from this Bridge are using a single PI */
+    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
+	/*
+	 * Once set, these registers shouldn't change; they should
+	 * be set multiple times with the same values.
+	 *
+	 * If we're attempting to change these registers, it means
+	 * that our heuristics for allocating interrupts in a way
+	 * appropriate for IP35 have failed, and the admin needs to
+	 * explicitly direct some interrupts (or we need to make the
+	 * heuristics more clever).
+	 *
+	 * In practice, we hope this doesn't happen very often, if
+	 * at all.
+	 */
+	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
+	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
+		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
+		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
+		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
+		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
+			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
+			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
+		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
+	}
+    }
+
+    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
+    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
+    bridge->b_int_host_err = vect;
+}
+
+/*
+ * pcibr_intr_preset: called during mlreset time
+ * if the platform specific code needs to route
+ * one of the Bridge's xtalk interrupts before the
+ * xtalk infrastructure is available.
+ */
+void
+pcibr_xintr_preset(void *which_widget,
+		   int which_widget_intr,
+		   xwidgetnum_t targ,
+		   iopaddr_t addr,
+		   xtalk_intr_vector_t vect)
+{
+    bridge_t               *bridge = (bridge_t *) which_widget;
+
+    if (which_widget_intr == -1) {
+	/* bridge widget error interrupt */
+	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+				   XTALK_ADDR_TO_UPPER(addr));
+	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+	bridge->b_int_host_err = vect;
+
+	/* turn on all interrupts except
+	 * the PCI interrupt requests,
+	 * at least at heart.
+	 */
+	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
+
+    } else {
+	/* routing a PCI device interrupt.
+	 * targ and low 38 bits of addr must
+	 * be the same as the already set
+	 * value for the widget error interrupt.
+	 */
+	bridge->b_int_addr[which_widget_intr].addr =
+	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+	     (BRIDGE_INT_ADDR_FLD & vect));
+	/*
+	 * now bridge can let it through;
+	 * NB: still should be blocked at
+	 * xtalk provider end, until the service
+	 * function is set.
+	 */
+	bridge->b_int_enable |= 1 << vect;
+    }
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+}
+
+
+/*
+ * pcibr_intr_func()
+ *
+ * This is the pcibr interrupt "wrapper" function that is called,
+ * in interrupt context, to initiate the interrupt handler(s) registered
+ * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
+ * handlers will be called directly, and threaded handlers will have their 
+ * thread woken up.
+ */
+void
+pcibr_intr_func(intr_arg_t arg)
+{
+    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
+    reg_p                   wrbf;
+    pcibr_intr_t            intr;
+    pcibr_intr_list_t       list;
+    int                     clearit;
+    int			    do_nonthreaded = 1;
+    int			    is_threaded = 0;
+    int			    x = 0;
+
+	/*
+	 * If any handler is still running from a previous interrupt
+	 * just return. If there's a need to call the handler(s) again,
+	 * another interrupt will be generated either by the device or by
+	 * pcibr_force_interrupt().
+	 */
+
+	if (wrap->iw_hdlrcnt) {
+		return;
+	}
+
+    /*
+     * Call all interrupt handlers registered.
+     * First, the pcibr_intrd threads for any threaded handlers will be
+     * awoken, then any non-threaded handlers will be called sequentially.
+     */
+	
+	clearit = 1;
+	while (do_nonthreaded) {
+	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
+		if ((intr = list->il_intr) &&
+		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
+
+		/*
+		 * This device may have initiated write
+		 * requests since the bridge last saw
+		 * an edge on this interrupt input; flushing
+		 * the buffer prior to invoking the handler
+		 * should help but may not be sufficient if we 
+		 * get more requests after the flush, followed
+		 * by the card deciding it wants service, before
+		 * the interrupt handler checks to see if things need
+		 * to be done.
+		 *
+		 * There is a similar race condition if
+		 * an interrupt handler loops around and
+		 * notices further service is required.
+		 * Perhaps we need to have an explicit
+		 * call that interrupt handlers need to
+		 * do between noticing that DMA to memory
+		 * has completed, but before observing the
+		 * contents of memory?
+		 */
+
+			if ((do_nonthreaded) && (!is_threaded)) {
+			/* Non-threaded. 
+			 * Call the interrupt handler at interrupt level
+			 */
+
+			/* Only need to flush write buffers if sharing */
+
+			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
+			    if ((x = *wrbf))	/* write request buffer flush */
+#ifdef SUPPORT_PRINTING_V_FORMAT
+				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
+				    "write buffer flush failed, wrbf=0x%x\n", 
+				    list->il_intr->bi_dev, wrbf);
+#else
+				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
+				    "write buffer flush failed, wrbf=0x%lx\n", 
+				    (void *)list->il_intr->bi_dev, (long) wrbf);
+#endif
+			}
+		    }
+
+		    clearit = 0;
+		}
+	    }
+
+		do_nonthreaded = 0;
+		/*
+		 * If the non-threaded handler was the last to complete,
+		 * (i.e., no threaded handlers still running) force an
+		 * interrupt to avoid a potential deadlock situation.
+		 */
+		if (wrap->iw_hdlrcnt == 0) {
+			pcibr_force_interrupt(wrap);
+		}
+	}
+
+	/* If there were no handlers,
+	 * disable the interrupt and return.
+	 * It will get enabled again after
+	 * a handler is connected.
+	 * If we don't do this, we would
+	 * sit here and spin through the
+	 * list forever.
+	 */
+	if (clearit) {
+	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+	    bridgereg_t             b_int_enable;
+	    bridgereg_t		    mask = 1 << wrap->iw_intr;
+	    unsigned long           s;
+
+	    s = pcibr_lock(pcibr_soft);
+	    b_int_enable = bridge->b_int_enable;
+	    b_int_enable &= ~mask;
+	    bridge->b_int_enable = b_int_enable;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	    pcibr_unlock(pcibr_soft, s);
+	    return;
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,896 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+void              do_pcibr_rrb_clear(bridge_t *, int);
+void              do_pcibr_rrb_flush(bridge_t *, int);
+int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+int		  pcibr_wrb_flush(devfs_handle_t);
+int               pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+int               pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+int               pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+void              pcibr_rrb_flush(devfs_handle_t);
+int		  pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+
+/* 
+ *    RRB Management
+ */
+
+#define LSBIT(word)		((word) &~ ((word)-1))
+
+void
+do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
+{
+    bridgereg_t             status;
+
+    /* bridge_lock must be held;
+     * this RRB must be disabled.
+     */
+
+    /* wait until RRB has no outstanduing XIO packets. */
+    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
+	;				/* XXX- beats on bridge. bad idea? */
+    }
+
+    /* if the RRB has data, drain it. */
+    if (status & BRIDGE_RRB_VALID(rrb)) {
+	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
+
+	/* wait until RRB is no longer valid. */
+	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
+	    ;				/* XXX- beats on bridge. bad idea? */
+	}
+    }
+}
+
+void
+do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
+{
+    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
+    bridgereg_t             rrbv;
+    int                     shft = 4 * (rrbn >> 1);
+    unsigned                ebit = BRIDGE_RRB_EN << shft;
+
+    rrbv = *rrbp;
+    if (rrbv & ebit)
+	*rrbp = rrbv & ~ebit;
+
+    do_pcibr_rrb_clear(bridge, rrbn);
+
+    if (rrbv & ebit)
+	*rrbp = rrbv;
+}
+
+/*
+ *    pcibr_rrb_count_valid: count how many RRBs are
+ *      marked valid for the specified PCI slot on this
+ *      bridge.
+ *
+ *      NOTE: The "slot" parameter for all pcibr_rrb
+ *      management routines must include the "virtual"
+ *      bit; when manageing both the normal and the
+ *      virtual channel, separate calls to these
+ *      routines must be made. To denote the virtual
+ *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
+ *      number.
+ *
+ *      IMPL NOTE: The obvious algorithm is to iterate
+ *      through the RRB fields, incrementing a count if
+ *      the RRB is valid and matches the slot. However,
+ *      it is much simpler to use an algorithm derived
+ *      from the "partitioned add" idea. First, XOR in a
+ *      pattern such that the fields that match this
+ *      slot come up "all ones" and all other fields
+ *      have zeros in the mismatching bits. Then AND
+ *      together the bits in the field, so we end up
+ *      with one bit turned on for each field that
+ *      matched. Now we need to count these bits. This
+ *      can be done either with a series of shift/add
+ *      instructions or by using "tmp % 15"; I expect
+ *      that the cascaded shift/add will be faster.
+ */
+
+int
+do_pcibr_rrb_count_valid(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp ^= 0x11111111 * (7 - slot / 2);
+    tmp &= (0xCCCCCCCC & tmp) >> 2;
+    tmp &= (0x22222222 & tmp) >> 1;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_count_avail: count how many RRBs are
+ *      available to be allocated for the specified slot.
+ *
+ *      IMPL NOTE: similar to the above, except we are
+ *      just counting how many fields have the valid bit
+ *      turned off.
+ */
+int
+do_pcibr_rrb_count_avail(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~tmp) >> 3;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_alloc: allocate some additional RRBs
+ *      for the specified slot. Returns -1 if there were
+ *      insufficient free RRBs to satisfy the request,
+ *      or 0 if the request was fulfilled.
+ *
+ *      Note that if a request can be partially filled,
+ *      it will be, even if we return failure.
+ *
+ *      IMPL NOTE: again we avoid iterating across all
+ *      the RRBs; instead, we form up a word containing
+ *      one bit for each free RRB, then peel the bits
+ *      off from the low end.
+ */
+int
+do_pcibr_rrb_alloc(bridge_t *bridge,
+		   pciio_slot_t slot,
+		   int more)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, bit;
+
+    reg = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~reg) >> 3;
+    while (more-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+    return rv;
+}
+
+/*
+ *    do_pcibr_rrb_free: release some of the RRBs that
+ *      have been allocated for the specified
+ *      slot. Returns zero for success, or negative if
+ *      it was unable to free that many RRBs.
+ *
+ *      IMPL NOTE: We form up a bit for each RRB
+ *      allocated to the slot, aligned with the VALID
+ *      bitfield this time; then we peel bits off one at
+ *      a time, releasing the corresponding RRB.
+ */
+int
+do_pcibr_rrb_free(bridge_t *bridge,
+		  pciio_slot_t slot,
+		  int less)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, clr, bit;
+    int                     i;
+
+    clr = 0;
+    reg = bridge->b_rrb_map[slot & 1].reg;
+
+    /* This needs to be done otherwise the rrb's on the virtual channel
+     * for this slot won't be freed !!
+     */
+    tmp = reg & 0xbbbbbbbb;
+
+    tmp ^= (0x11111111 * (7 - slot / 2));
+    tmp &= (0x33333333 & tmp) << 2;
+    tmp &= (0x44444444 & tmp) << 1;
+    while (less-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg &= ~bit;
+	clr |= bit;
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+
+    for (i = 0; i < 8; i++)
+	if (clr & (8 << (4 * i)))
+	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
+
+    return rv;
+}
+
+void
+do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
+		       int slot,
+		       int more_rrbs)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     got;
+
+    for (got = 0; got < more_rrbs; ++got) {
+	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
+	    pcibr_soft->bs_rrb_res[slot & 7]--;
+	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
+	    pcibr_soft->bs_rrb_avail[slot & 1]--;
+	else
+	    break;
+	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
+	    break;
+#if PCIBR_RRB_DEBUG
+	printk("do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
+		slot & 7, slot & 8 ? "v" : "");
+#endif
+	pcibr_soft->bs_rrb_valid[slot]++;
+    }
+#if PCIBR_RRB_DEBUG
+    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
+	    pcibr_soft->bs_rrb_avail[0],
+	    pcibr_soft->bs_rrb_avail[1]);
+    for (slot = 0; slot < 8; ++slot)
+	printk("\t%d+%d+%d",
+		0xFFF & pcibr_soft->bs_rrb_valid[slot],
+		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+		pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+}
+
+/*
+ * Device driver interface to flush the write buffers for a specified
+ * device hanging off the bridge.
+ */
+int
+pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    volatile bridgereg_t   *wrb_flush;
+
+    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
+    while (*wrb_flush);
+
+    return(0);
+}
+
+/*
+ * Device driver interface to request RRBs for a specified device
+ * hanging off a Bridge.  The driver requests the total number of
+ * RRBs it would like for the normal channel (vchan0) and for the
+ * "virtual channel" (vchan1).  The actual number allocated to each
+ * channel is returned.
+ *
+ * If we cannot allocate at least one RRB to a channel that needs
+ * at least one, return -1 (failure).  Otherwise, satisfy the request
+ * as best we can and return 0.
+ */
+int
+pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     desired_vchan0;
+    int                     desired_vchan1;
+    int                     orig_vchan0;
+    int                     orig_vchan1;
+    int                     delta_vchan0;
+    int                     delta_vchan1;
+    int                     final_vchan0;
+    int                     final_vchan1;
+    int                     avail_rrbs;
+    int                     res_rrbs;
+    unsigned long           s;
+    int                     error;
+
+    /*
+     * TBD: temper request with admin info about RRB allocation,
+     * and according to demand from other devices on this Bridge.
+     *
+     * One way of doing this would be to allocate two RRBs
+     * for each device on the bus, before any drivers start
+     * asking for extras. This has the weakness that one
+     * driver might not give back an "extra" RRB until after
+     * another driver has already failed to get one that
+     * it wanted.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+
+    /* Save the boot-time RRB configuration for this slot */
+    if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] < 0) {
+        pcibr_soft->bs_rrb_valid_dflt[pciio_slot] =
+                pcibr_soft->bs_rrb_valid[pciio_slot]; 
+        pcibr_soft->bs_rrb_valid_dflt[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] =
+                pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+        pcibr_soft->bs_rrb_res_dflt[pciio_slot] =
+                pcibr_soft->bs_rrb_res[pciio_slot];
+                  
+    }
+
+    /* How many RRBs do we own? */
+    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
+    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+    /* How many RRBs do we want? */
+    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
+    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
+
+    /* How many RRBs are free? */
+    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	+ pcibr_soft->bs_rrb_res[pciio_slot];
+
+    /* Figure desired deltas */
+    delta_vchan0 = desired_vchan0 - orig_vchan0;
+    delta_vchan1 = desired_vchan1 - orig_vchan1;
+
+    /* Trim back deltas to something
+     * that we can actually meet, by
+     * decreasing the ending allocation
+     * for whichever channel wants
+     * more RRBs. If both want the same
+     * number, cut the second channel.
+     * NOTE: do not change the allocation for
+     * a channel that was passed as NULL.
+     */
+    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
+	if (count_vchan0 &&
+	    (!count_vchan1 ||
+	     ((orig_vchan0 + delta_vchan0) >
+	      (orig_vchan1 + delta_vchan1))))
+	    delta_vchan0--;
+	else
+	    delta_vchan1--;
+    }
+
+    /* Figure final RRB allocations
+     */
+    final_vchan0 = orig_vchan0 + delta_vchan0;
+    final_vchan1 = orig_vchan1 + delta_vchan1;
+
+    /* If either channel wants RRBs but our actions
+     * would leave it with none, declare an error,
+     * but DO NOT change any RRB allocations.
+     */
+    if ((desired_vchan0 && !final_vchan0) ||
+	(desired_vchan1 && !final_vchan1)) {
+
+	error = -1;
+
+    } else {
+
+	/* Commit the allocations: free, then alloc.
+	 */
+	if (delta_vchan0 < 0)
+	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
+	if (delta_vchan1 < 0)
+	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
+
+	if (delta_vchan0 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
+	if (delta_vchan1 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
+
+	/* Return final values to caller.
+	 */
+	if (count_vchan0)
+	    *count_vchan0 = final_vchan0;
+	if (count_vchan1)
+	    *count_vchan1 = final_vchan1;
+
+	/* prevent automatic changes to this slot's RRBs
+	 */
+	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
+
+	/* Track the actual allocations, release
+	 * any further reservations, and update the
+	 * number of available RRBs.
+	 */
+
+	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
+	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
+	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	    + pcibr_soft->bs_rrb_res[pciio_slot]
+	    - delta_vchan0
+	    - delta_vchan1;
+	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
+
+        /*
+         * Reserve enough RRBs so this slot's RRB configuration can be
+         * reset to its boot-time default following a hot-plug shut-down
+         */
+        res_rrbs =   (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] -
+                      pcibr_soft->bs_rrb_valid[pciio_slot]) 
+                   + (pcibr_soft->bs_rrb_valid_dflt[pciio_slot +
+                                                    PCIBR_RRB_SLOT_VIRTUAL] -
+                      pcibr_soft->bs_rrb_valid[pciio_slot +
+                                               PCIBR_RRB_SLOT_VIRTUAL])
+                   + (pcibr_soft->bs_rrb_res_dflt[pciio_slot] -
+                      pcibr_soft->bs_rrb_res[pciio_slot]);
+
+         if (res_rrbs > 0) {
+             pcibr_soft->bs_rrb_res[pciio_slot] = res_rrbs;
+             pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+                 pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+                 - res_rrbs;
+         }
+ 
+#if PCIBR_RRB_DEBUG
+	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
+		pciio_slot, final_vchan0, final_vchan1,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
+	    printk("\t%d+%d+%d",
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
+		    pcibr_soft->bs_rrb_res[pciio_slot]);
+	printk("\n");
+#endif
+
+	error = 0;
+    }
+
+    pcibr_unlock(pcibr_soft, s);
+
+    return error;
+}
+
+/*
+ * Device driver interface to check the current state
+ * of the RRB allocations.
+ *
+ *   pconn_vhdl is your PCI connection point (specifies which
+ *      PCI bus and which slot).
+ *
+ *   count_vchan0 points to where to return the number of RRBs
+ *      assigned to the primary DMA channel, used by all DMA
+ *      that does not explicitly ask for the alternate virtual
+ *      channel.
+ *
+ *   count_vchan1 points to where to return the number of RRBs
+ *      assigned to the secondary DMA channel, used when
+ *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
+ *
+ *   count_reserved points to where to return the number of RRBs
+ *      that have been automatically reserved for your device at
+ *      startup, but which have not been assigned to a
+ *      channel. RRBs must be assigned to a channel to be used;
+ *      this can be done either with an explicit pcibr_rrb_alloc
+ *      call, or automatically by the infrastructure when a DMA
+ *      translation is constructed. Any call to pcibr_rrb_alloc
+ *      will release any unassigned reserved RRBs back to the
+ *      free pool.
+ *
+ *   count_pool points to where to return the number of RRBs
+ *      that are currently unassigned and unreserved. This
+ *      number can (and will) change as other drivers make calls
+ *      to pcibr_rrb_alloc, or automatically allocate RRBs for
+ *      DMA beyond their initial reservation.
+ *
+ * NULL may be passed for any of the return value pointers
+ * the caller is not interested in.
+ *
+ * The return value is "0" if all went well, or "-1" if
+ * there is a problem. Additionally, if the wrong vertex
+ * is passed in, one of the subsidiary support functions
+ * could panic with a "bad pciio fingerprint."
+ */
+
+int
+pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1,
+		int *count_reserved,
+		int *count_pool)
+{
+    pciio_info_t            pciio_info;
+    pciio_slot_t            pciio_slot;
+    pcibr_soft_t            pcibr_soft;
+    unsigned long           s;
+    int                     error = -1;
+
+    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
+	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
+	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
+
+	s = pcibr_lock(pcibr_soft);
+
+	if (count_vchan0)
+	    *count_vchan0 =
+		pcibr_soft->bs_rrb_valid[pciio_slot];
+
+	if (count_vchan1)
+	    *count_vchan1 =
+		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+	if (count_reserved)
+	    *count_reserved =
+		pcibr_soft->bs_rrb_res[pciio_slot];
+
+	if (count_pool)
+	    *count_pool =
+		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
+
+	error = 0;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return error;
+}
+
+/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
+ * requested for each of the devices.  The evn_odd argument indicates whether
+ * allocation is for the odd or even rrbs. The next group of four argument
+ * pairs indicate the amount of rrbs to be assigned to each device. The first
+ * argument of each pair indicate the total number of rrbs to allocate for that
+ * device. The second argument of each pair indicates how many rrb's from the
+ * first argument should be assigned to the virtual channel. The total of all
+ * of the first arguments should be <= 8. The second argument should be <= the
+ * first argument.
+ * if even_odd = 0 the devices in order are 0, 2, 4, 6 
+ * if even_odd = 1 the devices in order are 1, 3, 5, 7
+ * returns 0 if no errors else returns -1
+ */
+
+int
+pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
+		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
+{
+    devfs_handle_t          pcibr_vhdl;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t)0;
+    bridge_t               *bridge = NULL;
+
+    uint32_t                rrb_setting = 0;
+    int                     rrb_shift = 7;
+    uint32_t                cur_rrb;
+    int                     dev_rrbs[4];
+    int                     virt[4];
+    int                     i, j;
+    unsigned long           s;
+
+    if (GRAPH_SUCCESS ==
+	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
+	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+	if (pcibr_soft)
+	    bridge = pcibr_soft->bs_base;
+	hwgraph_vertex_unref(pcibr_vhdl);
+    }
+    if (bridge == NULL)
+	bridge = (bridge_t *) xtalk_piotrans_addr
+	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
+
+    even_odd &= 1;
+
+    dev_rrbs[0] = dev_1_rrbs;
+    dev_rrbs[1] = dev_2_rrbs;
+    dev_rrbs[2] = dev_3_rrbs;
+    dev_rrbs[3] = dev_4_rrbs;
+
+    virt[0] = virt1;
+    virt[1] = virt2;
+    virt[2] = virt3;
+    virt[3] = virt4;
+
+    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
+	return -1;
+    }
+    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
+	return -1;
+    }
+    /* walk through rrbs */
+    for (i = 0; i < 4; i++) {
+	if (virt[i]) {
+		for( j = 0; j < virt[i]; j++) {
+			cur_rrb = i | 0xc;
+			cur_rrb = cur_rrb << (rrb_shift * 4);
+			rrb_shift--;
+			rrb_setting = rrb_setting | cur_rrb;
+			dev_rrbs[i] = dev_rrbs[i] - 1;
+		}
+	}
+	for (j = 0; j < dev_rrbs[i]; j++) {
+	    cur_rrb = i | 0x8;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	}
+    }
+
+    if (pcibr_soft)
+	s = pcibr_lock(pcibr_soft);
+
+    bridge->b_rrb_map[even_odd].reg = rrb_setting;
+
+    if (pcibr_soft) {
+
+	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
+
+	/* since we've "FIXED" the allocations
+	 * for these slots, we probably can dispense
+	 * with tracking avail/res/valid data, but
+	 * keeping it up to date helps debugging.
+	 */
+
+	pcibr_soft->bs_rrb_avail[even_odd] =
+	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
+
+	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return 0;
+}
+
+/*
+ *    pcibr_rrb_flush: chase down all the RRBs assigned
+ *      to the specified connection point, and flush
+ *      them.
+ */
+void
+pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned long           s;
+    reg_p                   rrbp;
+    unsigned                rrbm;
+    int                     i;
+    int                     rrbn;
+    unsigned                sval;
+    unsigned                mask;
+
+    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
+    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
+    rrbn = pciio_slot & 1;
+    rrbp = &bridge->b_rrb_map[rrbn].reg;
+
+    s = pcibr_lock(pcibr_soft);
+    rrbm = *rrbp;
+    for (i = 0; i < 8; ++i) {
+	if ((rrbm & mask) == sval)
+	    do_pcibr_rrb_flush(bridge, rrbn);
+	rrbm >>= 4;
+	rrbn += 2;
+    }
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * pcibr_slot_initial_rrb_alloc
+ *	Allocate a default number of rrbs for this slot on 
+ * 	the two channels.  This is dictated by the rrb allocation
+ * 	strategy routine defined per platform.
+ */
+
+int
+pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    pcibr_info_h	 pcibr_infoh;
+    pcibr_info_t	 pcibr_info;
+    bridge_t		*bridge;
+    int                  c0, c1, r;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* How may RRBs are on this slot?
+     */
+    c0 = do_pcibr_rrb_count_valid(bridge, slot);
+    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
+
+#if PCIBR_RRB_DEBUG
+    printk(
+	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d\n",
+            slot, c0, c1);
+#endif
+
+    /* Do we really need any?
+     */
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    pcibr_info = pcibr_infoh[0];
+    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
+	!pcibr_soft->bs_slot[slot].has_host) {
+	if (c0 > 0)
+	    do_pcibr_rrb_free(bridge, slot, c0);
+	if (c1 > 0)
+	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
+	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
+	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
+	return(ENODEV);
+    }
+
+    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
+    pcibr_soft->bs_rrb_valid[slot] = c0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
+
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    r = 3 - (c0 + c1);
+
+    if (r > 0) {
+	pcibr_soft->bs_rrb_res[slot] = r;
+	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_initial_rrb
+ *      Assign an equal total number of RRBs to all candidate slots, 
+ *      where the total is the sum of the number of RRBs assigned to
+ *      the normal channel, the number of RRBs assigned to the virtual
+ *      channel, and the number of RRBs assigned as reserved. 
+ *
+ *      A candidate slot is a populated slot on a non-SN1 system or 
+ *      any existing (populated or empty) slot on an SN1 system.
+ *      Empty SN1 slots need RRBs to support hot-plug operations.
+ */
+
+int
+pcibr_initial_rrb(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t first, pciio_slot_t last)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    pciio_slot_t            slot;
+    int                     c0, c1;
+    int                     have[2][3];
+    int                     res[2];
+    int                     eo;
+
+    have[0][0] = have[0][1] = have[0][2] = 0;
+    have[1][0] = have[1][1] = have[1][2] = 0;
+    res[0] = res[1] = 0;
+
+    for (slot = 0; slot < 8; ++slot) {
+        /* Initial RRB management; give back RRBs in all non-existent slots */
+        (void) pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
+
+        /* Base calculations only on existing slots */
+        if ((slot >= first) && (slot <= last)) {
+            c0 = pcibr_soft->bs_rrb_valid[slot];
+            c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL];
+            if ((c0 + c1) < 3)
+                have[slot & 1][c0 + c1]++;
+        }
+    }
+
+    /* Initialize even/odd slot available RRB counts */
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    /*
+     * Calculate reserved RRBs for slots based on current RRB usage
+     */
+    for (eo = 0; eo < 2; eo++) {
+        if ((3 * have[eo][0] + 2 * have[eo][1] + have[eo][2]) <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 3;
+        else if ((2 * have[eo][0] + have[eo][1]) <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 2;
+        else if (have[eo][0] <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 1;
+        else
+            res[eo] = 0;
+
+    }
+
+    /* Assign reserved RRBs to existing slots */
+    for (slot = first; slot <= last; ++slot) {
+        int                     r;
+
+        c0 = pcibr_soft->bs_rrb_valid[slot];
+        c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL];
+        r = res[slot & 1] - (c0 + c1);
+
+        if (r > 0) {
+            pcibr_soft->bs_rrb_res[slot] = r;
+            pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+            }
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("%v RRB MANAGEMENT: %d+%d free\n",
+            pcibr_vhdl,
+            pcibr_soft->bs_rrb_avail[0],
+            pcibr_soft->bs_rrb_avail[1]);
+    for (slot = first; slot <= last; ++slot)
+        printk("\tslot %d: %d+%d+%d", slot,
+                0xFFF & pcibr_soft->bs_rrb_valid[slot],
+                0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+                pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return 0;
+
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c linux/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
--- linux.orig/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,1692 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+extern pcibr_info_t     pcibr_info_get(devfs_handle_t);
+extern int              pcibr_widget_to_bus(int);
+extern pcibr_info_t     pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
+extern void             pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+extern int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+#if 0
+int pcibr_slot_reset(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+#endif
+
+int pcibr_slot_info_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_slot_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+		 pciio_slot_t slot, int drv_flags);
+int pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+		 pciio_slot_t slot, int drv_flags);
+int pcibr_slot_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags);
+int pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_probe_slot(bridge_t *, cfg_p, unsigned int *);
+void		 pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
+extern uint64_t  do_pcibr_config_get(cfg_p, unsigned, unsigned);
+
+#ifdef LATER
+int pcibr_slot_attach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot,
+                int drv_flags, char *l1_msg, int *sub_errorp);
+int pcibr_slot_pwr(devfs_handle_t, pciio_slot_t, int, char *);
+int pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t);
+int pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t);
+void pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh, int func,
+                 pcibr_slot_func_info_resp_t funcp);
+int pcibr_slot_info_return(pcibr_soft_t pcibr_soft, pciio_slot_t slot,
+                 pcibr_slot_info_resp_t respp);
+int pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t);
+#endif	/* LATER */
+
+extern devfs_handle_t baseio_pci_vhdl;
+int scsi_ctlr_nums_add(devfs_handle_t, devfs_handle_t);
+
+/* For now .... */
+/*
+ * PCI Hot-Plug Capability Flags
+ */
+#define D_PCI_HOT_PLUG_ATTACH  0x200  /* Driver supports PCI hot-plug attach */
+#define D_PCI_HOT_PLUG_DETACH  0x400  /* Driver supports PCI hot-plug detach */
+
+
+/*==========================================================================
+ *	BRIDGE PCI SLOT RELATED IOCTLs
+ */
+
+#ifdef LATER
+
+/*
+ * pcibr_slot_startup
+ *	Software start-up the PCI slot.
+ */
+int
+pcibr_slot_startup(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t                   pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t                   slot = reqp->req_slot;
+    int                            error = 0;
+    char                           l1_msg[BRL1_QSIZE+1];
+    struct pcibr_slot_up_resp_s    tmp_up_resp;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    /* Do not allow start-up of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+ 
+    /* Check for the valid slot */
+    if (!PCIBR_VALID_SLOT(slot))
+        return(PCI_NOT_A_SLOT);
+
+    /* Acquire update access to the bus */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    if (pcibr_soft->bs_slot[slot].slot_status & SLOT_STARTUP_CMPLT) {
+        error = PCI_SLOT_ALREADY_UP;
+        goto startup_unlock;
+    }
+
+    error = pcibr_slot_attach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_ATTACH,
+                              l1_msg, &tmp_up_resp.resp_sub_errno);
+
+    strncpy(tmp_up_resp.resp_l1_msg, l1_msg, L1_QSIZE);
+    tmp_up_resp.resp_l1_msg[L1_QSIZE] = '\0';
+
+    if (COPYOUT(&tmp_up_resp, reqp->req_respp.up, reqp->req_size)) {
+        return(EFAULT);
+    }
+
+    startup_unlock:
+
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+    return(error);
+}
+
+/*
+ * pcibr_slot_shutdown
+ *	Software shut-down the PCI slot
+ */
+int
+pcibr_slot_shutdown(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t                   pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t                      *bridge;
+    pciio_slot_t                   slot = reqp->req_slot;
+    int                            error = 0;
+    char                           l1_msg[BRL1_QSIZE+1];
+    struct pcibr_slot_down_resp_s  tmp_down_resp;
+    pciio_slot_t                   tmp_slot;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Check for valid slot */
+    if (!PCIBR_VALID_SLOT(slot))
+        return(PCI_NOT_A_SLOT);
+
+    /* Do not allow shut-down of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+
+    /* Acquire update access to the bus */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    if ((pcibr_soft->bs_slot[slot].slot_status & SLOT_SHUTDOWN_CMPLT) ||
+        ((pcibr_soft->bs_slot[slot].slot_status & SLOT_STATUS_MASK) == 0)) {
+        error = PCI_SLOT_ALREADY_DOWN;
+        /*
+         * RJR - Should we invoke an L1 slot power-down command just in case
+         *       a previous shut-down failed to power-down the slot?
+         */
+        goto shutdown_unlock;
+    }
+
+    /* Do not allow the last 33 MHz card to be removed */
+    if ((bridge->b_wid_control & BRIDGE_CTRL_BUS_SPEED_MASK) ==
+         BRIDGE_CTRL_BUS_SPEED_33) {
+        for (tmp_slot = pcibr_soft->bs_first_slot;
+             tmp_slot <= pcibr_soft->bs_last_slot; tmp_slot++)
+            if (tmp_slot != slot)
+                if (pcibr_soft->bs_slot[tmp_slot].slot_status & SLOT_POWER_UP) {
+                    error++;
+                    break;
+                }
+        if (!error) {
+            error = PCI_EMPTY_33MHZ;
+            goto shutdown_unlock;
+        }
+    }
+
+    error = pcibr_slot_detach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_DETACH,
+                              l1_msg, &tmp_down_resp.resp_sub_errno);
+
+    strncpy(tmp_down_resp.resp_l1_msg, l1_msg, L1_QSIZE);
+    tmp_down_resp.resp_l1_msg[L1_QSIZE] = '\0';
+
+    if (COPYOUT(&tmp_down_resp, reqp->req_respp.down, reqp->req_size)) {
+        return(EFAULT);
+    }
+
+    shutdown_unlock:
+
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+    return(error);
+}
+
+char *pci_space_name[] = {"NONE", 
+			  "ROM",
+			  "IO",
+			  "",
+			  "MEM",
+			  "MEM32",
+			  "MEM64",
+			  "CFG",
+			  "WIN0",
+			  "WIN1",
+			  "WIN2",
+			  "WIN3",
+			  "WIN4",
+			  "WIN5",
+			  "",
+			  "BAD"};
+
+void
+pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
+                            int func,
+                            pcibr_slot_func_info_resp_t funcp)
+{
+    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
+    int                          win;
+
+    funcp->resp_f_status = 0;
+
+    if (!pcibr_info) {
+        return;
+    }
+
+    funcp->resp_f_status |= FUNC_IS_VALID;
+    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
+
+    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
+        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
+    }
+
+    funcp->resp_f_bus = pcibr_info->f_bus;
+    funcp->resp_f_slot = pcibr_info->f_slot;
+    funcp->resp_f_func = pcibr_info->f_func;
+    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
+    funcp->resp_f_pops = pcibr_info->f_pops;
+    funcp->resp_f_efunc = pcibr_info->f_efunc;
+    funcp->resp_f_einfo = pcibr_info->f_einfo;
+
+    funcp->resp_f_vendor = pcibr_info->f_vendor;
+    funcp->resp_f_device = pcibr_info->f_device;
+
+    for(win = 0 ; win < 6 ; win++) {
+        funcp->resp_f_window[win].resp_w_base =
+                                  pcibr_info->f_window[win].w_base;
+        funcp->resp_f_window[win].resp_w_size =
+                                  pcibr_info->f_window[win].w_size;
+        sprintf(funcp->resp_f_window[win].resp_w_space,
+                "%s",
+                pci_space_name[pcibr_info->f_window[win].w_space]);
+    }
+
+    funcp->resp_f_rbase = pcibr_info->f_rbase;
+    funcp->resp_f_rsize = pcibr_info->f_rsize;
+
+    for (win = 0 ; win < 4; win++) {
+        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
+    }
+
+    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
+
+}
+
+int
+pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
+                       pciio_slot_t             slot,
+                       pcibr_slot_info_resp_t   respp)
+{
+    pcibr_soft_slot_t            pss;
+    int                          func;
+    bridge_t                    *bridge = pcibr_soft->bs_base;
+    reg_p                        b_respp;
+    pcibr_slot_info_resp_t       slotp;
+    pcibr_slot_func_info_resp_t  funcp;
+
+    slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP);
+    if (slotp == NULL) {
+        return(ENOMEM);
+    }
+
+    pss = &pcibr_soft->bs_slot[slot];
+
+    slotp->resp_has_host = pss->has_host;
+    slotp->resp_host_slot = pss->host_slot;
+    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
+    slotp->resp_slot_status = pss->slot_status;
+
+    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (is_sys_critical_vertex(pss->slot_conn)) {
+        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
+    }
+
+    slotp->resp_bss_ninfo = pss->bss_ninfo;
+
+    for (func = 0; func < pss->bss_ninfo; func++) {
+        funcp = &(slotp->resp_func[func]);
+        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
+    }
+
+    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
+            pci_space_name[pss->bss_devio.bssd_space]);
+    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
+    slotp->resp_bss_device = pss->bss_device;
+
+    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
+    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
+    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
+
+    slotp->resp_bss_d64_base = pss->bss_d64_base;
+    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
+    slotp->resp_bss_d32_base = pss->bss_d32_base;
+    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
+
+    slotp->resp_bss_ext_ates_active = pss->bss_ext_ates_active;
+
+    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
+    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
+
+    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
+    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
+                                                      PCIBR_RRB_SLOT_VIRTUAL];
+    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
+
+    if (slot & 1) {
+        b_respp = &bridge->b_odd_resp;
+    } else {
+        b_respp = &bridge->b_even_resp;
+    }
+
+    slotp->resp_b_resp = *b_respp;
+
+    slotp->resp_b_wid_control = bridge->b_wid_control;
+    slotp->resp_b_int_device = bridge->b_int_device;
+    slotp->resp_b_int_enable = bridge->b_int_enable;
+    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
+
+    if (COPYOUT(slotp, respp, sizeof(*respp))) {
+        return(EFAULT);
+    }
+
+    kmem_free(slotp, sizeof(*slotp));
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_query
+ *	Return information about the PCI slot maintained by the infrastructure.
+ *	Information is requested in the request structure.
+ *
+ *      Information returned in the response structure:
+ *		Slot hwgraph name
+ *		Vendor/Device info
+ *		Base register info
+ *		Interrupt mapping from device pins to the bridge pins
+ *		Devio register
+ *		Software RRB info
+ *		RRB register info
+ *		Host/Gues info
+ *		PCI Bus #,slot #, function #
+ *		Slot provider hwgraph name
+ *		Provider Functions
+ *		Error handler
+ *		DMA mapping usage counters
+ *		DMA direct translation info
+ *		External SSRAM workaround info
+ */
+int
+pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t            slot = reqp->req_slot;
+    pciio_slot_t            tmp_slot;
+    pcibr_slot_info_resp_t  respp = reqp->req_respp.query;
+    int                     size = reqp->req_size;
+    int                     error;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
+    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
+        return(PCI_NOT_A_SLOT);
+    }
+
+    /* Do not allow a query of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+
+    /* Return information for the requested PCI slot */
+    if (slot != PCIIO_SLOT_NONE) {
+        if (size < sizeof(*respp)) {
+            return(PCI_RESP_AREA_TOO_SMALL);
+        }
+
+        /* Acquire read access to the bus */
+        mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
+
+        /* Release the bus lock */
+        mrunlock(pcibr_soft->bs_bus_lock);
+
+        return(error);
+    }
+
+    /* Return information for all the slots */
+    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
+
+        if (size < sizeof(*respp)) {
+            return(PCI_RESP_AREA_TOO_SMALL);
+        }
+
+        /* Acquire read access to the bus */
+        mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
+
+        /* Release the bus lock */
+        mrunlock(pcibr_soft->bs_bus_lock);
+
+        if (error) {
+            return(error);
+        }
+
+        ++respp;
+        size -= sizeof(*respp);
+    }
+
+    return(error);
+}
+#endif	/* LATER */
+
+/* FIXME: there should be a better way to do this.
+ * pcibr_attach() needs PCI_ADDR_SPACE_LIMITS_STORE
+ */
+
+/* 
+ * PCI_ADDR_SPACE_LIMITS_LOAD
+ *	Gets the current values of 
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
+    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
+    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
+    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
+    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
+    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
+    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
+    printf("+++++++++++++++++++++++\n"			\
+	   "IO base 0x%x last 0x%x\n"			\
+	   "SWIN base 0x%x last 0x%x\n"			\
+	   "MEM base 0x%x last 0x%x\n"			\
+	   "+++++++++++++++++++++++\n",			\
+	   pcibr_soft->bs_spinfo.pci_io_base,		\
+	   pcibr_soft->bs_spinfo.pci_io_last,		\
+	   pcibr_soft->bs_spinfo.pci_swin_base,		\
+	   pcibr_soft->bs_spinfo.pci_swin_last,		\
+	   pcibr_soft->bs_spinfo.pci_mem_base,		\
+	   pcibr_soft->bs_spinfo.pci_mem_last);
+
+
+/*
+ * pcibr_slot_info_init
+ *	Probe for this slot and see if it is populated.
+ *	If it is populated initialize the generic PCI infrastructural
+ * 	information associated with this particular PCI device.
+ */
+int
+pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
+		     pciio_slot_t 	slot)
+{
+    pcibr_soft_t	    pcibr_soft;
+    pcibr_info_h	    pcibr_infoh;
+    pcibr_info_t	    pcibr_info;
+    bridge_t		   *bridge;
+    cfg_p                   cfgw;
+    unsigned                idword;
+    unsigned                pfail;
+    unsigned                idwords[8];
+    pciio_vendor_id_t       vendor;
+    pciio_device_id_t       device;
+    unsigned                htype;
+    cfg_p                   wptr;
+    int                     win;
+    pciio_space_t           space;
+    iopaddr_t		    pci_io_fb,	pci_io_fl;
+    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
+    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
+    int			    nfunc;
+    pciio_function_t	    rfunc;
+    int			    func;
+    devfs_handle_t	    conn_vhdl;
+    pcibr_soft_slot_t	    slotp;
+    
+    /* Get the basic software information required to proceed */
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft)
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+    if (!PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
+     * is done by the host slot then we are done.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);    
+    }
+
+    /* Check for a slot with any system critical functions */
+    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    /* Load the current values of allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+    
+    /* Try to read the device-id/vendor-id from the config space */
+    cfgw = bridge->b_type0_cfg_dev[slot].l;
+
+    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
+	return(ENODEV);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+    slotp->slot_status |= SLOT_POWER_UP;
+
+    vendor = 0xFFFF & idword;
+    /* If the vendor id is not valid then the slot is not populated
+     * and we are done.
+     */
+    if (vendor == 0xFFFF) 
+	return(ENODEV);			
+    
+    device = 0xFFFF & (idword >> 16);
+    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+
+    nfunc = 1;
+    rfunc = PCIIO_FUNC_NONE;
+    pfail = 0;
+
+    /* NOTE: if a card claims to be multifunction
+     * but only responds to config space 0, treat
+     * it as a unifunction card.
+     */
+
+    if (htype & 0x80) {		/* MULTIFUNCTION */
+	for (func = 1; func < 8; ++func) {
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    vendor = 0xFFFF & idwords[func];
+	    if (vendor == 0xFFFF) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    nfunc = func + 1;
+	    rfunc = 0;
+	}
+	cfgw = bridge->b_type0_cfg_dev[slot].l;
+    }
+    NEWA(pcibr_infoh, nfunc);
+    
+    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
+    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+    for (func = 0; func < nfunc; ++func) {
+	unsigned                cmd_reg;
+	
+	if (func) {
+	    if (pfail & (1 << func))
+		continue;
+	    
+	    idword = idwords[func];
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    
+	    device = 0xFFFF & (idword >> 16);
+	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+	    rfunc = func;
+	}
+	htype &= 0x7f;
+	if (htype != 0x00) {
+	    printk(KERN_WARNING  "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
+		    pcibr_soft->bs_name, slot, func, htype);
+	    continue;
+	}
+#if DEBUG && ATTACH_DEBUG
+	printk(KERN_NOTICE   
+		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
+		pcibr_soft->bs_name, slot, func, vendor, device);
+#endif	
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, rfunc, vendor, device);
+	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
+	if (func == 0)
+	    slotp->slot_conn = conn_vhdl;
+
+#ifdef SN1_LITTLE_ENDIAN
+	cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4];
+#else
+	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
+#endif
+	
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) {
+	    iopaddr_t               base, mask, code;
+	    size_t                  size;
+
+	    /*
+	     * GET THE BASE & SIZE OF THIS WINDOW:
+	     *
+	     * The low two or four bits of the BASE register
+	     * determines which address space we are in; the
+	     * rest is a base address. BASE registers
+	     * determine windows that are power-of-two sized
+	     * and naturally aligned, so we can get the size
+	     * of a window by writing all-ones to the
+	     * register, reading it back, and seeing which
+	     * bits are used for decode; the least
+	     * significant nonzero bit is also the size of
+	     * the window.
+	     *
+	     * WARNING: someone may already have allocated
+	     * some PCI space to this window, and in fact
+	     * PIO may be in process at this very moment
+	     * from another processor (or even from this
+	     * one, if we get interrupted)! So, if the BASE
+	     * already has a nonzero address, be generous
+	     * and use the LSBit of that address as the
+	     * size; this could overstate the window size.
+	     * Usually, when one card is set up, all are set
+	     * up; so, since we don't bitch about
+	     * overlapping windows, we are ok.
+	     *
+	     * UNFORTUNATELY, some cards do not clear their
+	     * BASE registers on reset. I have two heuristics
+	     * that can detect such cards: first, if the
+	     * decode enable is turned off for the space
+	     * that the window uses, we can disregard the
+	     * initial value. second, if the address is
+	     * outside the range that we use, we can disregard
+	     * it as well.
+	     *
+	     * This is looking very PCI generic. Except for
+	     * knowing how many slots and where their config
+	     * spaces are, this window loop and the next one
+	     * could probably be shared with other PCI host
+	     * adapters. It would be interesting to see if
+	     * this could be pushed up into pciio, when we
+	     * start supporting more PCI providers.
+	     */
+#ifdef SN1_LITTLE_ENDIAN
+	    base = wptr[((win*4)^4)/4];
+#else
+	    base = wptr[win];
+#endif
+
+	    if (base & PCI_BA_IO_SPACE) {
+		/* BASE is in I/O space. */
+		space = PCIIO_SPACE_IO;
+		mask = -4;
+		code = base & 3;
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		}
+	    } else {
+		/* BASE is in MEM space. */
+		space = PCIIO_SPACE_MEM;
+		mask = -16;
+		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		} else if (base & 0xC0000000) {
+		    base = 0;	/* outside permissable range */
+		} else if ((code == PCI_BA_MEM_64BIT) &&
+#ifdef SN1_LITTLE_ENDIAN
+			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
+#else 
+			   (wptr[win + 1] != 0)) {
+#endif /* LITTLE_ENDIAN */
+		    base = 0;	/* outside permissable range */
+		}
+	    }
+
+	    if (base != 0) {	/* estimate size */
+		size = base & -base;
+	    } else {		/* calculate size */
+#ifdef SN1_LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
+		size = wptr[((win*4)^4)/4];	/* get stored bits */
+#else 
+		wptr[win] = ~0;	/* turn on all bits */
+		size = wptr[win];	/* get stored bits */
+#endif /* LITTLE_ENDIAN */
+		size &= mask;	/* keep addr */
+		size &= -size;	/* keep lsbit */
+		if (size == 0)
+		    continue;
+	    }	
+
+	    pcibr_info->f_window[win].w_space = space;
+	    pcibr_info->f_window[win].w_base = base;
+	    pcibr_info->f_window[win].w_size = size;
+
+	    /*
+	     * If this window already has PCI space
+	     * allocated for it, "subtract" that space from
+	     * our running freeblocks. Don't worry about
+	     * overlaps in existing allocated windows; we
+	     * may be overstating their sizes anyway.
+	     */
+
+	    if (base && size) {
+		if (space == PCIIO_SPACE_IO) {
+		    pcibr_freeblock_sub(&pci_io_fb,
+					&pci_io_fl,
+					base, size);
+		} else {
+		    pcibr_freeblock_sub(&pci_lo_fb,
+					&pci_lo_fl,
+					base, size);
+		    pcibr_freeblock_sub(&pci_hi_fb,
+					&pci_hi_fl,
+					base, size);
+		}	
+	    }
+#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
+	    /*
+	     * IOC3 BASE_ADDR* BUG WORKAROUND
+	     *
+	     
+	     * If we write to BASE1 on the IOC3, the
+	     * data in BASE0 is replaced. The
+	     * original workaround was to remember
+	     * the value of BASE0 and restore it
+	     * when we ran off the end of the BASE
+	     * registers; however, a later
+	     * workaround was added (I think it was
+	     * rev 1.44) to avoid setting up
+	     * anything but BASE0, with the comment
+	     * that writing all ones to BASE1 set
+	     * the enable-parity-error test feature
+	     * in IOC3's SCR bit 14.
+	     *
+	     * So, unless we defer doing any PCI
+	     * space allocation until drivers
+	     * attach, and set up a way for drivers
+	     * (the IOC3 in paricular) to tell us
+	     * generically to keep our hands off
+	     * BASE registers, we gotta "know" about
+	     * the IOC3 here.
+	     *
+	     * Too bad the PCI folks didn't reserve the
+	     * all-zero value for 'no BASE here' (it is a
+	     * valid code for an uninitialized BASE in
+	     * 32-bit PCI memory space).
+	     */
+	    
+	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
+		(device == IOC3_DEVICE_ID_NUM))
+		break;
+#endif
+	    if (code == PCI_BA_MEM_64BIT) {
+		win++;		/* skip upper half */
+#ifdef SN1_LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
+#else 
+		wptr[win] = 0;	/* which must be zero */
+#endif /* LITTLE_ENDIAN */
+	    }
+	}				/* next win */
+    }				/* next func */
+
+    /* Store back the values for allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}					
+
+/*
+ * pcibr_slot_info_free
+ *	Remove all the PCI infrastructural information associated
+ * 	with a particular PCI device.
+ */
+int
+pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
+                     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    int			nfunc;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+
+    pcibr_device_info_free(pcibr_vhdl, slot);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    DELA(pcibr_infoh,nfunc);
+    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
+
+    return(0);
+}
+
+int as_debug = 0;
+/*
+ * pcibr_slot_addr_space_init
+ *	Reserve chunks of PCI address space as required by 
+ * 	the base registers in the card.
+ */
+int
+pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    iopaddr_t		pci_io_fb, pci_io_fl;
+    iopaddr_t		pci_lo_fb, pci_lo_fl;
+    iopaddr_t		pci_hi_fb, pci_hi_fl;
+    size_t              align;
+    iopaddr_t           mask;
+    int		    	nbars;
+    int		       	nfunc;
+    int			func;
+    int			win;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Get the current values for the allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+
+    if (as_debug)
+#ifdef LATER
+    PCI_ADDR_SPACE_LIMITS_PRINT();
+#endif
+
+    /* allocate address space,
+     * for windows that have not been
+     * previously assigned.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);
+    }
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    if (nfunc < 1)
+	return(EINVAL);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    if (!pcibr_infoh)
+	return(EINVAL);
+
+    /*
+     * Try to make the DevIO windows not
+     * overlap by pushing the "io" and "hi"
+     * allocation areas up to the next one
+     * or two megabyte bound. This also
+     * keeps them from being zero.
+     *
+     * DO NOT do this with "pci_lo" since
+     * the entire "lo" area is only a
+     * megabyte, total ...
+     */
+    align = (slot < 2) ? 0x200000 : 0x100000;
+    mask = -align;
+    pci_io_fb = (pci_io_fb + align - 1) & mask;
+    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
+
+    for (func = 0; func < nfunc; ++func) {
+	cfg_p                   cfgw;
+	cfg_p                   wptr;
+	pciio_space_t           space;
+	iopaddr_t               base;
+	size_t                  size;
+	cfg_p                   pci_cfg_cmd_reg_p;
+	unsigned                pci_cfg_cmd_reg;
+	unsigned                pci_cfg_cmd_reg_add = 0;
+
+	pcibr_info = pcibr_infoh[func];
+
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+	
+	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	nbars = PCI_CFG_BASE_ADDRS;
+
+	for (win = 0; win < nbars; ++win) {
+
+	    space = pcibr_info->f_window[win].w_space;
+	    base = pcibr_info->f_window[win].w_base;
+	    size = pcibr_info->f_window[win].w_size;
+	    
+	    if (size < 1)
+		continue;
+
+	    if (base >= size) {
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
+			slot, func, win, space, base, base + size - 1);
+#endif
+		continue;		/* already allocated */
+	    }
+	    align = size;		/* ie. 0x00001000 */
+	    if (align < _PAGESZ)
+		align = _PAGESZ;	/* ie. 0x00004000 */
+	    mask = -align;		/* ie. 0xFFFFC000 */
+
+	    switch (space) {
+	    case PCIIO_SPACE_IO:
+		base = (pci_io_fb + align - 1) & mask;
+		if ((base + size) > pci_io_fl) {
+		    base = 0;
+		    break;
+		}
+		pci_io_fb = base + size;
+		break;
+		
+	    case PCIIO_SPACE_MEM:
+#ifdef SN1_LITTLE_ENDIAN
+		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
+#else
+		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
+#endif  /* LITTLE_ENDIAN */
+		    PCI_BA_MEM_1MEG) {
+		    /* allocate from 20-bit PCI space */
+		    base = (pci_lo_fb + align - 1) & mask;
+		    if ((base + size) > pci_lo_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_lo_fb = base + size;
+		} else {
+		    /* allocate from 32-bit or 64-bit PCI space */
+		    base = (pci_hi_fb + align - 1) & mask;
+		    if ((base + size) > pci_hi_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_hi_fb = base + size;
+		}
+		break;
+		
+	    default:
+		base = 0;
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d window %d had bad space code %d\n",
+			slot, win, space);
+#endif
+	    }
+	    pcibr_info->f_window[win].w_base = base;
+#ifdef SN1_LITTLE_ENDIAN
+	    wptr[((win*4)^4)/4] = base;
+#if DEBUG && PCI_DEBUG
+		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
+#endif
+#else
+	    wptr[win] = base;
+#endif  /* LITTLE_ENDIAN */
+
+#if DEBUG && PCI_DEBUG
+	    if (base >= size)
+		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
+			slot, func, win, space, base, base + size - 1);
+	    else
+		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
+			slot, func, win, size, space);
+#endif
+	}				/* next base */
+
+	/*
+	 * Allocate space for the EXPANSION ROM
+	 * NOTE: DO NOT DO THIS ON AN IOC3,
+	 * as it blows the system away.
+	 */
+	base = size = 0;
+	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
+	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
+
+	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
+#ifdef SN1_LITTLE_ENDIAN
+	    wptr[1] = 0xFFFFF000;
+	    mask = wptr[1];
+#else
+	    *wptr = 0xFFFFF000;
+	    mask = *wptr;
+#endif  /* LITTLE_ENDIAN */
+	    if (mask & 0xFFFFF000) {
+		size = mask & -mask;
+		align = size;
+		if (align < _PAGESZ)
+		    align = _PAGESZ;
+		mask = -align;
+		base = (pci_hi_fb + align - 1) & mask;
+		if ((base + size) > pci_hi_fl)
+		    base = size = 0;
+		else {
+		    pci_hi_fb = base + size;
+#ifdef SN1_LITTLE_ENDIAN
+		    wptr[1] = base;
+#else
+		    *wptr = base;
+#endif  /* LITTLE_ENDIAN */
+#if DEBUG && PCI_DEBUG
+		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
+			    pcibr_soft->bs_name, slot,
+			    base, base + size - 1);
+#endif
+		}
+	    }
+	}
+	pcibr_info->f_rbase = base;
+	pcibr_info->f_rsize = size;
+	
+	/*
+	 * if necessary, update the board's
+	 * command register to enable decoding
+	 * in the windows we added.
+	 *
+	 * There are some bits we always want to
+	 * be sure are set.
+	 */
+	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
+
+	/*
+	 * The Adaptec 1160 FC Controller WAR #767995:
+	 * The part incorrectly ignores the upper 32 bits of a 64 bit
+	 * address when decoding references to it's registers so to
+	 * keep it from responding to a bus cycle that it shouldn't
+	 * we only use I/O space to get at it's registers.  Don't
+	 * enable memory space accesses on that PCI device.
+	 */
+	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
+	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
+
+	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
+	    (pcibr_info->f_device != FCADP_DEVID))
+	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
+
+	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
+
+	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
+	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
+#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
+	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
+	    fast_back_to_back_enable = 0;
+#endif
+	pci_cfg_cmd_reg &= 0xFFFF;
+	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
+	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
+	
+    }				/* next func */
+
+    /* Now that we have allocated new chunks of PCI address spaces to this
+     * card we need to update the bookkeeping values which indicate
+     * the current PCI address space allocations.
+     */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}
+
+/*
+ * pcibr_slot_device_init
+ * 	Setup the device register in the bridge for this PCI slot.
+ */
+int
+pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
+		       pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    bridgereg_t		 devreg;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * Adjustments to Device(x)
+     * and init of bss_device shadow
+     */
+    devreg = bridge->b_device[slot].reg;
+    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
+    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
+#ifdef LITTLE_ENDIAN
+    devreg |= BRIDGE_DEV_DEV_SWAP;
+#endif
+    pcibr_soft->bs_slot[slot].bss_device = devreg;
+    bridge->b_device[slot].reg = devreg;
+
+#if DEBUG && PCI_DEBUG
+	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
+#endif
+
+#if DEBUG && PCI_DEBUG
+    printk("pcibr: PCI space allocation done.\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_guest_info_init
+ *	Setup the host/guest relations for a PCI slot.
+ */
+int
+pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    pcibr_soft_slot_t	slotp;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    /* create info and verticies for guest slots;
+     * for compatibilitiy macros, create info
+     * for even unpopulated slots (but do not
+     * build verticies for them).
+     */
+    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
+	NEWA(pcibr_infoh, 1);
+	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
+	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
+	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+
+	if (pcibr_soft->bs_slot[slot].has_host) {
+	    slotp->slot_conn = pciio_device_info_register
+		(pcibr_vhdl, &pcibr_info->f_c);
+	}
+    }
+
+    /* generate host/guest relations
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	int  host = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
+
+	hwgraph_edge_add(slotp->slot_conn,
+			 host_slotp->slot_conn,
+			 EDGE_LBL_HOST);
+
+	/* XXX- only gives us one guest edge per
+	 * host. If/when we have a host with more than
+	 * one guest, we will need to figure out how
+	 * the host finds all its guests, and sorts
+	 * out which one is which.
+	 */
+	hwgraph_edge_add(host_slotp->slot_conn,
+			 slotp->slot_conn,
+			 EDGE_LBL_GUEST);
+    }
+
+    return(0);
+}
+
+
+/*
+ * pcibr_slot_call_device_attach
+ *	This calls the associated driver attach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    async_attach_t	aa = NULL;
+    int			func;
+    devfs_handle_t	xconn_vhdl,conn_vhdl;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+        return(EPERM);
+    }
+    
+    xconn_vhdl = pcibr_soft->bs_conn;
+    aa = async_attach_get_info(xconn_vhdl);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+#ifdef LATER
+	/*
+	 * Activate if and when we support cdl.
+	 */
+	if (aa)
+	    async_attach_add_info(conn_vhdl, aa);
+#endif	/* LATER */
+
+	error_func = pciio_device_attach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+        error = error_slot;
+
+    }				/* next func */
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_call_device_detach
+ *	This calls the associated driver detach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    int			func;
+    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    if (pcibr_soft->bs_slot[slot].has_host)
+        return(EPERM);
+
+    /* Make sure that we do not detach a system critical function vertex */
+    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+	error_func = pciio_device_detach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+	error = error_slot;
+
+    }				/* next func */
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        if (conn_vhdl != GRAPH_VERTEX_NONE) 
+            pcibr_device_unregister(conn_vhdl);
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    return(error);
+}
+
+#ifdef LATER
+
+/*
+ * pcibr_slot_attach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific initialization that needs to be done.
+ *	This is usually called when we want to initialize a new
+ * 	PCI card on the bus.
+ */
+int
+pcibr_slot_attach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags,
+		  char        *l1_msg,
+                  int         *sub_errorp)
+{
+    pcibr_soft_t  pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    timespec_t    ts;
+    int		  error;
+
+    if (!(pcibr_soft->bs_slot[slot].slot_status & SLOT_POWER_UP)) { 
+        /* Power-up the slot */
+        error = pcibr_slot_pwr(pcibr_vhdl, slot, L1_REQ_PCI_UP, l1_msg);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_L1_ERR);
+        } else {
+            pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_POWER_MASK;
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_POWER_UP;
+        }
+
+#ifdef LATER
+        /*
+         * Allow cards like the Alteon Gigabit Ethernet Adapter to complete
+         * on-card initialization following the slot reset
+         */
+         ts.tv_sec = 0;                      /* 0 secs */
+         ts.tv_nsec = 500 * (1000 * 1000);   /* 500 msecs */
+         nano_delay(&ts);
+#else
+#endif
+#if 0
+        /* Reset the slot */
+        error = pcibr_slot_reset(pcibr_vhdl, slot)
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_RESET_ERR);
+        }
+#endif
+
+        /* Find out what is out there */
+        error = pcibr_slot_info_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_INFO_INIT_ERR);
+        }
+
+        /* Set up the address space for this slot in the PCI land */
+        error = pcibr_slot_addr_space_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_ADDR_INIT_ERR);
+        }
+
+        /* Setup the device register */
+        error = pcibr_slot_device_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_DEV_INIT_ERR);
+        }
+
+        /* Setup host/guest relations */
+        error = pcibr_slot_guest_info_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_GUEST_INIT_ERR);
+        }
+
+        /* Initial RRB management */
+        error = pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_RRB_ALLOC_ERR);
+        }
+
+    }
+
+    /* Call the device attach */
+    error = pcibr_slot_call_device_attach(pcibr_vhdl, slot, drv_flags);
+    if (error) {
+        if (sub_errorp)
+            *sub_errorp = error;
+        if (error == EUNATCH)
+            return(PCI_NO_DRIVER);
+        else
+            return(PCI_SLOT_DRV_ATTACH_ERR);
+    }
+
+    return(0);
+}
+#endif	/* LATER */
+
+/*
+ * pcibr_slot_detach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific freeing that needs to be done.
+ */
+int
+pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags)
+{
+    int		  error;
+    
+    /* Call the device detach function */
+    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
+    return (error);
+
+}
+
+/*
+ * pcibr_is_slot_sys_critical
+ *      Check slot for any functions that are system critical.
+ *      Return 1 if any are system critical or 0 otherwise.
+ *
+ *      This function will always return 0 when called by 
+ *      pcibr_attach() because the system critical vertices 
+ *      have not yet been set in the hwgraph.
+ */
+int
+pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
+                      pciio_slot_t slot)
+{
+    pcibr_soft_t        pcibr_soft;
+    pcibr_info_h        pcibr_infoh;
+    pcibr_info_t        pcibr_info;
+    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
+    int                 nfunc;
+    int                 func;
+    boolean_t		is_sys_critical_vertex(devfs_handle_t);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+        return(0);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+        pcibr_info = pcibr_infoh[func];
+        if (!pcibr_info)
+            continue;
+
+        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+            continue;
+
+        conn_vhdl = pcibr_info->f_vertex;
+        if (is_sys_critical_vertex(conn_vhdl)) { 
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+            printk(KERN_WARNING  "%v is a system critical device vertex\n", conn_vhdl);
+#else
+            printk(KERN_WARNING  "%p is a system critical device vertex\n", (void *)conn_vhdl);
+#endif
+            return(1); 
+        }
+
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_probe_slot: read a config space word
+ * while trapping any errors; reutrn zero if
+ * all went OK, or nonzero if there was an error.
+ * The value read, if any, is passed back
+ * through the valp parameter.
+ */
+int
+pcibr_probe_slot(bridge_t *bridge,
+		 cfg_p cfg,
+		 unsigned *valp)
+{
+    int                     rv;
+    bridgereg_t             old_enable, new_enable;
+    int badaddr_val(volatile void *, int, volatile void *);
+
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+
+    bridge->b_int_enable = new_enable;
+
+	/*
+	 * The xbridge doesn't clear b_err_int_view unless
+	 * multi-err is cleared...
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+	    }
+
+    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
+	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
+	(void) bridge->b_wid_tflush;	/* flushbus */
+    }
+    rv = badaddr_val((void *) cfg, 4, valp);
+
+	/*
+	 * The xbridge doesn't set master timeout in b_int_status
+	 * here.  Fortunately it's in error_interrupt_view.
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+		rv = 1;		/* unoccupied slot */
+	    }
+
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    return rv;
+}
+
+void
+pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pcibr_info_t	pcibr_info;
+    pciio_function_t	func;
+    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
+    int			nfunc = slotp->bss_ninfo;
+    int                 bar;
+    int                 devio_index;
+    int                 s;
+
+
+    for (func = 0; func < nfunc; func++) {
+	pcibr_info = slotp->bss_infos[func];
+
+	if (!pcibr_info) 
+	    continue;
+
+        s = pcibr_lock(pcibr_soft);
+
+        for (bar = 0; bar < PCI_CFG_BASE_ADDRS; bar++) {
+            if (pcibr_info->f_window[bar].w_space == PCIIO_SPACE_NONE)
+                continue;
+
+            /* Get index of the DevIO(x) register used to access this BAR */
+            devio_index = pcibr_info->f_window[bar].w_devio_index;
+
+ 
+            /* On last use, clear the DevIO(x) used to access this BAR */
+            if (! --pcibr_soft->bs_slot[devio_index].bss_devio.bssd_ref_cnt) {
+               pcibr_soft->bs_slot[devio_index].bss_devio.bssd_space =
+                                                       PCIIO_SPACE_NONE; 
+               pcibr_soft->bs_slot[devio_index].bss_devio.bssd_base =
+                                                       PCIBR_D32_BASE_UNSET;
+               pcibr_soft->bs_slot[devio_index].bss_device = 0;
+            }
+        }
+
+        pcibr_unlock(pcibr_soft, s);
+
+	slotp->bss_infos[func] = 0;
+	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
+	pciio_device_info_free(&pcibr_info->f_c);
+
+	DEL(pcibr_info);
+    }
+
+    /* Reset the mapping usage counters */
+    slotp->bss_pmu_uctr = 0;
+    slotp->bss_d32_uctr = 0;
+    slotp->bss_d64_uctr = 0;
+
+    /* Clear the Direct translation info */
+    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
+    slotp->bss_d64_flags = 0;
+    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_d32_flags = 0;
+
+    /* Clear out shadow info necessary for the external SSRAM workaround */
+    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
+    slotp->bss_cmd_pointer = 0;
+    slotp->bss_cmd_shadow = 0;
+
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/shub_intr.c linux/arch/ia64/sn/io/sn2/shub_intr.c
--- linux.orig/arch/ia64/sn/io/sn2/shub_intr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/shub_intr.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,215 @@
+/* $Id: shub_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern void hub_device_desc_update(device_desc_t, ilvl_t, cpuid_t);
+
+/* ARGSUSED */
+void
+hub_intr_init(devfs_handle_t hubv)
+{
+	extern void sn_cpei_handler(int, void *, struct pt_regs *);
+	extern void sn_init_cpei_timer(void);
+
+	if (request_irq(SGI_SHUB_ERROR_VECTOR, sn_cpei_handler, 0, "SN hub error", NULL) ) {
+		printk("hub_intr_init: Couldn't register SGI_SHUB_ERROR_VECTOR = %x\n",SGI_SHUB_ERROR_VECTOR);
+	}
+	sn_init_cpei_timer();
+}
+
+xwidgetnum_t
+hub_widget_id(nasid_t nasid)
+{
+        hubii_wcr_t     ii_wcr; /* the control status register */
+        
+        ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
+        
+        return ii_wcr.wcr_fields_s.wcr_widget_id;
+}
+
+static hub_intr_t
+do_hub_intr_alloc(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev,
+		int uncond_nothread)
+{
+	cpuid_t		cpu = 0;
+	int		vector;
+	hub_intr_t	intr_hdl;
+	cnodeid_t	cnode;
+	int		cpuphys, slice;
+	int		nasid;
+	iopaddr_t	xtalk_addr;
+	struct xtalk_intr_s	*xtalk_info;
+	xwidget_info_t	xwidget_info;
+	ilvl_t		intr_swlevel = 0;
+
+	cpu = intr_heuristic(dev, dev_desc, -1, 0, owner_dev, NULL, &vector);
+
+	if (cpu == CPU_NONE) {
+		printk("Unable to allocate interrupt for 0x%p\n", (void *)owner_dev);
+		return(0);
+	}
+
+	cpuphys = cpu_physical_id(cpu);
+	slice = cpu_physical_id_to_slice(cpuphys);
+	nasid = cpu_physical_id_to_nasid(cpuphys);
+	cnode = cpuid_to_cnodeid(cpu);
+
+	if (slice) {
+		xtalk_addr = SH_II_INT1 | GLOBAL_MMR_SPACE |
+			((unsigned long)nasid << 36) | (1UL << 47);
+	} else {
+		xtalk_addr = SH_II_INT0 | GLOBAL_MMR_SPACE |
+			((unsigned long)nasid << 36) | (1UL << 47);
+	}
+
+	intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, cnode);
+	ASSERT_ALWAYS(intr_hdl);
+
+	xtalk_info = &intr_hdl->i_xtalk_info;
+	xtalk_info->xi_dev = dev;
+	xtalk_info->xi_vector = vector;
+	xtalk_info->xi_addr = xtalk_addr;
+
+	xwidget_info = xwidget_info_get(dev);
+	if (xwidget_info) {
+		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
+	}
+
+	intr_hdl->i_swlevel = intr_swlevel;
+	intr_hdl->i_cpuid = cpu;
+	intr_hdl->i_bit = vector;
+	intr_hdl->i_flags |= HUB_INTR_IS_ALLOCED;
+
+	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
+	return(intr_hdl);
+}
+
+hub_intr_t
+hub_intr_alloc(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev)
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
+}
+
+hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev)
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
+}
+
+void
+hub_intr_free(hub_intr_t intr_hdl)
+{
+	cpuid_t		cpu = intr_hdl->i_cpuid;
+	int		vector = intr_hdl->i_bit;
+	xtalk_intr_t	xtalk_info;
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
+		xtalk_info = &intr_hdl->i_xtalk_info;
+		xtalk_info->xi_dev = NODEV;
+		xtalk_info->xi_vector = 0;
+		xtalk_info->xi_addr = 0;
+		hub_intr_disconnect(intr_hdl);
+	}
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED) {
+		kfree(intr_hdl);
+	}
+	intr_unreserve_level(cpu, vector);
+}
+
+int
+hub_intr_connect(hub_intr_t intr_hdl,
+		xtalk_intr_setfunc_t setfunc,
+		void *setfunc_arg)
+{
+	int		rv;
+	cpuid_t		cpu = intr_hdl->i_cpuid;
+	int 		vector = intr_hdl->i_bit;
+
+	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
+
+	rv = intr_connect_level(cpu, vector, intr_hdl->i_swlevel, NULL);
+
+	if (rv < 0) {
+		return rv;
+	}
+
+	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
+	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
+
+	if (setfunc) {
+		(*setfunc)((xtalk_intr_t)intr_hdl);
+	}
+
+	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
+
+	return 0;
+}
+
+/*
+ * Disassociate handler with the specified interrupt.
+ */
+void
+hub_intr_disconnect(hub_intr_t intr_hdl)
+{
+	/*REFERENCED*/
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_setfunc_t setfunc;
+
+	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
+
+	/* TBD: send disconnected interrupts somewhere harmless */
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	rv = intr_disconnect_level(cpu, bit);
+	ASSERT(rv == 0);
+	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
+}
+
+
+/*
+ * Return a hwgraph vertex that represents the CPU currently
+ * targeted by an interrupt.
+ */
+devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl)
+{
+	cpuid_t cpuid = intr_hdl->i_cpuid;
+
+	ASSERT(cpuid != CPU_NONE);
+
+	return(cpuid_to_vertex(cpuid));
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/sn2/shuberror.c linux/arch/ia64/sn/io/sn2/shuberror.c
--- linux.orig/arch/ia64/sn/io/sn2/shuberror.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/io/sn2/shuberror.c	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,478 @@
+/* $Id: shuberror.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000,2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/ioerror.h>
+#include <asm/sn/sn2/shubio.h>
+#include <asm/sn/bte.h>
+
+extern void hubni_eint_init(cnodeid_t cnode);
+extern void hubii_eint_init(cnodeid_t cnode);
+extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
+int hubiio_crb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo);
+int hubiio_prb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo);
+extern void bte_crb_error_handler(devfs_handle_t hub_v, int btenum, int crbnum, ioerror_t *ioe);
+
+extern int maxcpus;
+
+#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
+
+
+void
+hub_error_clear(nasid_t nasid)
+{
+	int i;
+	hubreg_t idsr;
+
+    /*
+     * Make sure spurious write response errors are cleared
+     * (values are from hub_set_prb())
+     */
+    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
+        iprb_t prb;
+
+	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
+
+        /* Clear out some fields */
+        prb.iprb_ovflow = 1;
+        prb.iprb_bnakctr = 0;
+        prb.iprb_anakctr = 0;
+
+        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
+
+        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
+    }
+
+    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
+    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
+    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
+
+}
+
+
+/*
+ * Function	: hub_error_init
+ * Purpose	: initialize the error handling requirements for a given hub.
+ * Parameters	: cnode, the compact nodeid.
+ * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
+ *			remote cpu, when this hub is headless.(cpuless)
+ * Returns	: None
+ */
+
+void
+hub_error_init(cnodeid_t cnode)
+{
+	nasid_t nasid;
+
+    nasid = cnodeid_to_nasid(cnode);
+    hub_error_clear(nasid);
+
+
+    /*
+     * Now setup the hub ii error interrupt handler.
+     */
+
+    hubii_eint_init(cnode);
+
+    return;
+}
+
+/*
+ * Function	: hubii_eint_init
+ * Parameters	: cnode
+ * Purpose	: to initialize the hub iio error interrupt.
+ * Assumptions	: Called once per hub, by the cpu which will ultimately
+ *			handle this interrupt.
+ * Returns	: None.
+ */
+
+
+void
+hubii_eint_init(cnodeid_t cnode)
+{
+    int			bit, rv;
+    ii_iidsr_u_t    	hubio_eint;
+    hubinfo_t		hinfo; 
+    cpuid_t		intr_cpu;
+    devfs_handle_t 	hub_v;
+    ii_ilcsr_u_t	ilcsr;
+    int bit_pos_to_irq(int bit);
+    int synergy_intr_connect(int bit, int cpuid);
+
+
+    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
+    ASSERT_ALWAYS(hub_v);
+    hubinfo_get(hub_v, &hinfo);
+
+    ASSERT(hinfo);
+    ASSERT(hinfo->h_cnodeid == cnode);
+
+    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
+
+    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
+	/* 
+	 * HUB II link is not up. 
+	 * Just disable LLP, and don't connect any interrupts.
+	 */
+	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
+	return;
+    }
+    /* Select a possible interrupt target where there is a free interrupt
+     * bit and also reserve the interrupt bit for this IO error interrupt
+     */
+    intr_cpu = intr_heuristic(hub_v,0,-1,0,hub_v,
+			      "HUB IO error interrupt",&bit);
+    if (intr_cpu == CPU_NONE) {
+	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
+	return;
+    }
+	
+    rv = intr_connect_level(intr_cpu, bit, 0, NULL);
+    request_irq(bit + (intr_cpu << 8), hubii_eint_handler, 0, "SN hub error", (void *)hub_v);
+    ASSERT_ALWAYS(rv >= 0);
+    hubio_eint.ii_iidsr_regval = 0;
+    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
+    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
+    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
+    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
+
+}
+
+
+/*ARGSUSED*/
+void
+hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
+{
+    devfs_handle_t	hub_v;
+    hubinfo_t		hinfo; 
+    ii_wstat_u_t	wstat;
+    hubreg_t		idsr;
+
+
+    /* two levels of casting avoids compiler warning.!! */
+    hub_v = (devfs_handle_t)(long)(arg); 
+    ASSERT(hub_v);
+
+    hubinfo_get(hub_v, &hinfo);
+    
+    /* 
+     * Identify the reason for error. 
+     */
+    wstat.ii_wstat_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_WSTAT);
+
+    if (wstat.ii_wstat_fld_s.w_crazy) {
+	char	*reason;
+	/*
+	 * We can do a couple of things here. 
+	 * Look at the fields TX_MX_RTY/XT_TAIL_TO/XT_CRD_TO to check
+	 * which of these caused the CRAZY bit to be set. 
+	 * You may be able to check if the Link is up really.
+	 */
+	if (wstat.ii_wstat_fld_s.w_tx_mx_rty)
+		reason = "Micro Packet Retry Timeout";
+	else if (wstat.ii_wstat_fld_s.w_xt_tail_to)
+		reason = "Crosstalk Tail Timeout";
+	else if (wstat.ii_wstat_fld_s.w_xt_crd_to)
+		reason = "Crosstalk Credit Timeout";
+	else {
+		hubreg_t	hubii_imem;
+		/*
+		 * Check if widget 0 has been marked as shutdown, or
+		 * if BTE 0/1 has been marked.
+		 */
+		hubii_imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
+		if (hubii_imem & IIO_IMEM_W0ESD)
+			reason = "Hub Widget 0 has been Shutdown";
+		else if (hubii_imem & IIO_IMEM_B0ESD)
+			reason = "BTE 0 has been shutdown";
+		else if (hubii_imem & IIO_IMEM_B1ESD)
+			reason = "BTE 1 has been shutdown";
+		else	reason = "Unknown";
+	
+	}
+	/*
+	 * Note: we may never be able to print this, if the II talking
+	 * to Xbow which hosts the console is dead. 
+	 */
+	printk("Hub %d to Xtalk Link failed (II_ECRAZY) Reason: %s", 
+		hinfo->h_cnodeid, reason);
+    }
+
+    /* 
+     * It's a toss as to which one among PRB/CRB to check first. 
+     * Current decision is based on the severity of the errors. 
+     * IO CRB errors tend to be more severe than PRB errors.
+     *
+     * It is possible for BTE errors to have been handled already, so we
+     * may not see any errors handled here. 
+     */
+    (void)hubiio_crb_error_handler(hub_v, hinfo);
+    (void)hubiio_prb_error_handler(hub_v, hinfo);
+    /*
+     * If we reach here, it indicates crb/prb handlers successfully
+     * handled the error. So, re-enable II to send more interrupt
+     * and return.
+     */
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, 0xffffff);
+    idsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR) & ~IIO_IIDSR_SENT_MASK;
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, idsr);
+}
+
+/*
+ * Free the hub CRB "crbnum" which encountered an error.
+ * Assumption is, error handling was successfully done,
+ * and we now want to return the CRB back to Hub for normal usage.
+ *
+ * In order to free the CRB, all that's needed is to de-allocate it
+ *
+ * Assumption:
+ *      No other processor is mucking around with the hub control register.
+ *      So, upper layer has to single thread this.
+ */
+void
+hubiio_crb_free(hubinfo_t hinfo, int crbnum)
+{
+	ii_icrb0_a_u_t         icrba;
+
+	/*
+	* The hardware does NOT clear the mark bit, so it must get cleared
+	* here to be sure the error is not processed twice.
+	*/
+	icrba.ii_icrb0_a_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ICRB_A(crbnum));
+	icrba.a_valid   = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ICRB_A(crbnum), icrba.ii_icrb0_a_regval);
+	/*
+	* Deallocate the register.
+	*/
+
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ICDR, (IIO_ICDR_PND | crbnum));
+
+	/*
+	* Wait till hub indicates it's done.
+	*/
+	while (REMOTE_HUB_L(hinfo->h_nasid, IIO_ICDR) & IIO_ICDR_PND)
+		us_delay(1);
+
+}
+
+
+/*
+ * Array of error names  that get logged in CRBs
+ */ 
+char *hubiio_crb_errors[] = {
+	"Directory Error",
+	"CRB Poison Error",
+	"I/O Write Error",
+	"I/O Access Error",
+	"I/O Partial Write Error",
+	"I/O Partial Read Error",
+	"I/O Timeout Error",
+	"Xtalk Error Packet"
+};
+
+/*
+ * hubiio_crb_error_handler
+ *
+ *	This routine gets invoked when a hub gets an error 
+ *	interrupt. So, the routine is running in interrupt context
+ *	at error interrupt level.
+ * Action:
+ *	It's responsible for identifying ALL the CRBs that are marked
+ *	with error, and process them. 
+ *	
+ * 	If you find the CRB that's marked with error, map this to the
+ *	reason it caused error, and invoke appropriate error handler.
+ *
+ *	XXX Be aware of the information in the context register.
+ *
+ * NOTE:
+ *	Use REMOTE_HUB_* macro instead of LOCAL_HUB_* so that the interrupt
+ *	handler can be run on any node. (not necessarily the node 
+ *	corresponding to the hub that encountered error).
+ */
+
+int
+hubiio_crb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo)
+{
+	cnodeid_t	cnode;
+	nasid_t		nasid;
+	ii_icrb0_a_u_t		icrba;		/* II CRB Register A */
+	ii_icrb0_b_u_t		icrbb;		/* II CRB Register B */
+	ii_icrb0_c_u_t		icrbc;		/* II CRB Register C */
+	ii_icrb0_d_u_t		icrbd;		/* II CRB Register D */
+	int		i;
+	int		num_errors = 0;	/* Num of errors handled */
+	ioerror_t	ioerror;
+
+	nasid = hinfo->h_nasid;
+	cnode = NASID_TO_COMPACT_NODEID(nasid);
+
+	/*
+	 * Scan through all CRBs in the Hub, and handle the errors
+	 * in any of the CRBs marked.
+	 */
+	for (i = 0; i < IIO_NUM_CRBS; i++) {
+		icrba.ii_icrb0_a_regval = REMOTE_HUB_L(nasid, IIO_ICRB_A(i));
+
+		IOERROR_INIT(&ioerror);
+
+		/* read other CRB error registers. */
+		icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(nasid, IIO_ICRB_B(i));
+		icrbc.ii_icrb0_c_regval = REMOTE_HUB_L(nasid, IIO_ICRB_C(i));
+		icrbd.ii_icrb0_d_regval = REMOTE_HUB_L(nasid, IIO_ICRB_D(i));
+
+		IOERROR_SETVALUE(&ioerror,errortype,icrbb.b_ecode);
+		/* Check if this error is due to BTE operation,
+		* and handle it separately.
+		*/
+		if (icrbd.d_bteop ||
+			((icrbb.b_initiator == IIO_ICRB_INIT_BTE0 ||
+			icrbb.b_initiator == IIO_ICRB_INIT_BTE1) &&
+			(icrbb.b_imsgtype == IIO_ICRB_IMSGT_BTE ||
+			icrbb.b_imsgtype == IIO_ICRB_IMSGT_SN1NET))){
+
+			int bte_num;
+
+			if (icrbd.d_bteop)
+				bte_num = icrbc.c_btenum;
+			else /* b_initiator bit 2 gives BTE number */
+				bte_num = (icrbb.b_initiator & 0x4) >> 2;
+
+			bte_crb_error_handler(hub_v, bte_num,
+					i, &ioerror);
+			hubiio_crb_free(hinfo, i);
+			num_errors++;
+			continue;
+		}
+
+		/*
+		 * XXX
+		 * Assuming the only other error that would reach here is
+		 * crosstalk errors. 
+		 * If CRB times out on a message from Xtalk, it changes 
+		 * the message type to CRB. 
+		 *
+		 * If we get here due to other errors (SN0net/CRB)
+		 * what's the action ?
+		 */
+
+		/*
+		 * Pick out the useful fields in CRB, and
+		 * tuck them away into ioerror structure.
+		 */
+		IOERROR_SETVALUE(&ioerror,xtalkaddr,icrba.a_addr << IIO_ICRB_ADDR_SHFT);
+		IOERROR_SETVALUE(&ioerror,widgetnum,icrba.a_sidn);
+
+
+		if (icrba.a_iow){
+			/*
+			 * XXX We shouldn't really have BRIDGE-specific code
+			 * here, but alas....
+			 *
+			 * The BRIDGE (or XBRIDGE) sets the upper bit of TNUM
+			 * to indicate a WRITE operation.  It sets the next
+			 * bit to indicate an INTERRUPT operation.  The bottom
+			 * 3 bits of TNUM indicate which device was responsible.
+			 */
+			IOERROR_SETVALUE(&ioerror,widgetdev,
+					 TNUM_TO_WIDGET_DEV(icrba.a_tnum));
+
+		}
+
+	}
+	return	num_errors;
+}
+
+/*ARGSUSED*/
+/*
+ * hubii_prb_handler
+ *      Handle the error reported in the PRB for wiget number wnum.
+ *      This typically happens on a PIO write error.
+ *      There is nothing much we can do in this interrupt context for
+ *      PIO write errors. For e.g. QL scsi controller has the
+ *      habit of flaking out on PIO writes.
+ *      Print a message and try to continue for now
+ *      Cleanup involes freeing the PRB register
+ */
+static void
+hubii_prb_handler(devfs_handle_t hub_v, hubinfo_t hinfo, int wnum)
+{
+        nasid_t         nasid;
+
+        nasid = hinfo->h_nasid;
+        /*
+         * Clear error bit by writing to IECLR register.
+         */
+        REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, (1 << wnum));
+        /*
+         * PIO Write to Widget 'i' got into an error.
+         * Invoke hubiio_error_handler with this information.
+         */
+        printk( "Hub nasid %d got a PIO Write error from widget %d, cleaning up and continuing",
+                        nasid, wnum);
+        /*
+         * XXX
+         * It may be necessary to adjust IO PRB counter
+         * to account for any lost credits.
+         */
+}
+
+int
+hubiio_prb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo)
+{
+        int             wnum;
+        nasid_t         nasid;
+        int             num_errors = 0;
+        iprb_t          iprb;
+
+        nasid = hinfo->h_nasid;
+        /*
+         * Check if IPRB0 has any error first.
+         */
+        iprb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB(0));
+        if (iprb.iprb_error) {
+                num_errors++;
+                hubii_prb_handler(hub_v, hinfo, 0);
+        }
+        /*
+         * Look through PRBs 8 - F to see if any of them has error bit set.
+         * If true, invoke hub iio error handler for this widget.
+         */
+        for (wnum = HUB_WIDGET_ID_MIN; wnum <= HUB_WIDGET_ID_MAX; wnum++) {
+                iprb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB(wnum));
+
+                if (!iprb.iprb_error)
+                        continue;
+
+                num_errors++;
+                hubii_prb_handler(hub_v, hinfo, wnum);
+        }
+
+        return num_errors;
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/stubs.c linux/arch/ia64/sn/io/stubs.c
--- linux.orig/arch/ia64/sn/io/stubs.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/stubs.c	2002-08-01 06:42:37.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -21,6 +20,7 @@
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/slotnum.h>
 #include <asm/sn/vector.h>
+#include <asm/sn/nic.h>
 
 /******
  ****** hack defines ......
@@ -61,45 +61,45 @@
 }
 
 void *
-kmem_alloc_node(register size_t size, register int flags, cnodeid_t node)
+snia_kmem_alloc_node(register size_t size, register int flags, cnodeid_t node)
 {
         /* Allocates on node 'node' */
-	FIXME("kmem_alloc_node : use kmalloc");
+	FIXME("snia_kmem_alloc_node : use kmalloc");
 	return(kmalloc(size, GFP_KERNEL));
 }
 
 void *
-kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node)
+snia_kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node)
 {
-	FIXME("kmem_zalloc_node : use kmalloc");
+	FIXME("snia_kmem_zalloc_node : use kmalloc");
 	return(kmalloc(size, GFP_KERNEL));
 }
 
 void
-kmem_free(void *where, int size)
+snia_kmem_free(void *where, int size)
 {
-	FIXME("kmem_free : use kfree");
+	FIXME("snia_kmem_free : use kfree");
 	return(kfree(where));
 }
 
 
 void *
-kmem_zone_alloc(register zone_t *zone, int flags)
+snia_kmem_zone_alloc(register zone_t *zone, int flags)
 {
-	FIXME("kmem_zone_alloc : return null");
+	FIXME("snia_kmem_zone_alloc : return null");
 	return((void *)0);
 }
 
 void
-kmem_zone_free(register zone_t *zone, void *ptr)
+snia_kmem_zone_free(register zone_t *zone, void *ptr)
 {
-	FIXME("kmem_zone_free : no-op");
+	FIXME("snia_kmem_zone_free : no-op");
 }
 
 zone_t *
-kmem_zone_init(register int size, char *zone_name)
+snia_kmem_zone_init(register int size, char *zone_name)
 {
-	FIXME("kmem_zone_free : returns NULL");
+	FIXME("snia_kmem_zone_free : returns NULL");
 	return((zone_t *)0);
 }
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/xbow.c linux/arch/ia64/sn/io/xbow.c
--- linux.orig/arch/ia64/sn/io/xbow.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/xbow.c	2002-08-01 06:42:27.000000000 +0000
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -19,6 +18,7 @@
 #include <asm/sn/hack.h>
 #include <asm/sn/pci/bridge.h>
 #include <asm/sn/xtalk/xtalk_private.h>
+#include <asm/sn/simulator.h>
 
 /* #define DEBUG		1 */
 /* #define XBOW_DEBUG	1 */
@@ -102,7 +102,6 @@
 #ifdef LATER
 static void             xbow_setwidint(xtalk_intr_t);
 static void             xbow_errintr_handler(intr_arg_t);
-static error_handler_f  xbow_error_handler;
 #endif
 void                    xbow_intr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
 
@@ -281,7 +280,7 @@
                         /* &hcl_fops */ (void *)&vhdl, NULL);
     if (!vhdl) {
         printk(KERN_WARNING "xbow_attach: Unable to create char device for xbow conn %p\n",
-                conn);
+                (void *)conn);
     }
 
     /*
@@ -306,7 +305,7 @@
 
     /*
      * get the name of this xbow vertex and keep the info.
-     * This is needed during errors and interrupts, but as
+     * This is needed during errors and interupts, but as
      * long as we have it, we can use it elsewhere.
      */
     s = dev_to_name(vhdl, devnm, MAXDEVNAME);
@@ -371,36 +370,9 @@
     }
 
     /*
-     * attach the crossbow error interrupt.
-     */
-#ifdef LATER
-    dev_desc = device_desc_dup(vhdl);
-    device_desc_flags_set(dev_desc,
-			  device_desc_flags_get(dev_desc) | D_INTR_ISERR);
-    device_desc_intr_name_set(dev_desc, "Crossbow error");
-
-    intr_hdl = xtalk_intr_alloc(conn, dev_desc, vhdl);
-    ASSERT(intr_hdl != NULL);
-
-    xtalk_intr_connect(intr_hdl,
-		       (intr_func_t) xbow_errintr_handler,
-		       (intr_arg_t) soft,
-		       (xtalk_intr_setfunc_t) xbow_setwidint,
-		       (void *) xbow,
-		       (void *) 0);
-    device_desc_free(dev_desc);
-
-    xwidget_error_register(conn, xbow_error_handler, soft);
-
-#else
-    FIXME("xbow_attach: Fixme: we bypassed attaching xbow error interrupt.\n");
-#endif /* LATER */
-
-    /*
      * Enable xbow error interrupts
      */
-    xbow->xb_wid_control = (XB_WID_CTRL_REG_ACC_IE |
-			    XB_WID_CTRL_XTALK_IE);
+    xbow->xb_wid_control = (XB_WID_CTRL_REG_ACC_IE | XB_WID_CTRL_XTALK_IE);
 
     /*
      * take a census of the widgets present,
@@ -918,460 +890,6 @@
     return 1;
 }
 
-/*
- * xbow_errintr_handler will be called if the xbow
- * sends an interrupt request to report an error.
- */
-
-#ifdef LATER
-static void
-xbow_errintr_handler(intr_arg_t arg)
-{
-    ioerror_t               ioe[1];
-    xbow_soft_t             soft = (xbow_soft_t) arg;
-    xbow_t                 *xbow = soft->base;
-    xbowreg_t               wid_control;
-    xbowreg_t               wid_stat;
-    xbowreg_t               wid_err_cmdword;
-    xbowreg_t               wid_err_upper;
-    xbowreg_t               wid_err_lower;
-    w_err_cmd_word_u        wid_err;
-    uint64_t                 wid_err_addr;
-
-    int                     fatal = 0;
-    int                     dump_ioe = 0;
-
-    wid_control = xbow->xb_wid_control;
-    wid_stat = xbow->xb_wid_stat_clr;
-    wid_err_cmdword = xbow->xb_wid_err_cmdword;
-    wid_err_upper = xbow->xb_wid_err_upper;
-    wid_err_lower = xbow->xb_wid_err_lower;
-    xbow->xb_wid_err_cmdword = 0;
-
-    wid_err_addr =
-	wid_err_lower
-	| (((iopaddr_t) wid_err_upper
-	    & WIDGET_ERR_UPPER_ADDR_ONLY)
-	   << 32);
-
-    if (wid_stat & XB_WID_STAT_LINK_INTR_MASK) {
-	int                     port;
-
-	wid_err.r = wid_err_cmdword;
-
-	for (port = MAX_PORT_NUM - MAX_XBOW_PORTS;
-	     port < MAX_PORT_NUM; port++) {
-	    if (wid_stat & XB_WID_STAT_LINK_INTR(port)) {
-		xb_linkregs_t          *link = &(xbow->xb_link(port));
-		xbowreg_t               link_control = link->link_control;
-		xbowreg_t               link_status = link->link_status_clr;
-		xbowreg_t               link_aux_status = link->link_aux_status;
-		xbowreg_t               link_pend;
-
-		link_pend = link_status & link_control &
-		    (XB_STAT_ILLEGAL_DST_ERR
-		     | XB_STAT_OALLOC_IBUF_ERR
-		     | XB_STAT_RCV_CNT_OFLOW_ERR
-		     | XB_STAT_XMT_CNT_OFLOW_ERR
-		     | XB_STAT_XMT_MAX_RTRY_ERR
-		     | XB_STAT_RCV_ERR
-		     | XB_STAT_XMT_RTRY_ERR
-		     | XB_STAT_MAXREQ_TOUT_ERR
-		     | XB_STAT_SRC_TOUT_ERR
-		    );
-
-		if (link_pend & XB_STAT_ILLEGAL_DST_ERR) {
-		    if (wid_err.f.sidn == port) {
-			IOERROR_INIT(ioe);
-			IOERROR_SETVALUE(ioe, widgetnum, port);
-			IOERROR_SETVALUE(ioe, xtalkaddr, wid_err_addr);
-			if (IOERROR_HANDLED ==
-			    xbow_error_handler(soft,
-					       IOECODE_DMA,
-					       MODE_DEVERROR,
-					       ioe)) {
-			    link_pend &= ~XB_STAT_ILLEGAL_DST_ERR;
-			} else {
-			    dump_ioe++;
-			}
-		    }
-		}
-		/* Xbow/Bridge WAR:
-		 * if the bridge signals an LLP Transmitter Retry,
-		 * rewrite its control register.
-		 * If someone else triggers this interrupt,
-		 * ignore (and disable) the interrupt.
-		 */
-		if (link_pend & XB_STAT_XMT_RTRY_ERR) {
-		    if (!xbow_xmit_retry_error(soft, port)) {
-			link_control &= ~XB_CTRL_XMT_RTRY_IE;
-			link->link_control = link_control;
-			link->link_control;	/* stall until written */
-		    }
-		    link_pend &= ~XB_STAT_XMT_RTRY_ERR;
-		}
-		if (link_pend) {
-		    devfs_handle_t	xwidget_vhdl;
-		    char		*xwidget_name;
-		    
-		    /* Get the widget name corresponding to the current
-		     * xbow link.
-		     */
-		    xwidget_vhdl = xbow_widget_lookup(soft->busv,port);
-		    xwidget_name = xwidget_name_get(xwidget_vhdl);
-
-#ifdef	LATER
-		    printk("%s port %X[%s] XIO Bus Error",
-			    soft->name, port, xwidget_name);
-		    if (link_status & XB_STAT_MULTI_ERR)
-			XEM_ADD_STR("\tMultiple Errors\n");
-		    if (link_status & XB_STAT_ILLEGAL_DST_ERR)
-			XEM_ADD_STR("\tInvalid Packet Destination\n");
-		    if (link_status & XB_STAT_OALLOC_IBUF_ERR)
-			XEM_ADD_STR("\tInput Overallocation Error\n");
-		    if (link_status & XB_STAT_RCV_CNT_OFLOW_ERR)
-			XEM_ADD_STR("\tLLP receive error counter overflow\n");
-		    if (link_status & XB_STAT_XMT_CNT_OFLOW_ERR)
-			XEM_ADD_STR("\tLLP transmit retry counter overflow\n");
-		    if (link_status & XB_STAT_XMT_MAX_RTRY_ERR)
-			XEM_ADD_STR("\tLLP Max Transmitter Retry\n");
-		    if (link_status & XB_STAT_RCV_ERR)
-			XEM_ADD_STR("\tLLP Receiver error\n");
-		    if (link_status & XB_STAT_XMT_RTRY_ERR)
-			XEM_ADD_STR("\tLLP Transmitter Retry\n");
-		    if (link_status & XB_STAT_MAXREQ_TOUT_ERR)
-			XEM_ADD_STR("\tMaximum Request Timeout\n");
-		    if (link_status & XB_STAT_SRC_TOUT_ERR)
-			XEM_ADD_STR("\tSource Timeout Error\n");
-#endif	/* LATER */
-		    {
-			int                     other_port;
-
-			for (other_port = 8; other_port < 16; ++other_port) {
-			    if (link_aux_status & (1 << other_port)) {
-				/* XXX- need to go to "other_port"
-				 * and clean up after the timeout?
-				 */
-				XEM_ADD_VAR(other_port);
-			    }
-			}
-		    }
-
-#if !DEBUG
-		    if (kdebug) {
-#endif
-			XEM_ADD_VAR(link_control);
-			XEM_ADD_VAR(link_status);
-			XEM_ADD_VAR(link_aux_status);
-
-			if (dump_ioe) {
-			    XEM_ADD_IOE();
-			    dump_ioe = 0;
-			}
-#if !DEBUG
-		    }
-#endif
-		    fatal++;
-		}
-	    }
-	}
-    }
-    if (wid_stat & wid_control & XB_WID_STAT_WIDGET0_INTR) {
-	/* we have a "widget zero" problem */
-
-	if (wid_stat & (XB_WID_STAT_MULTI_ERR
-			| XB_WID_STAT_XTALK_ERR
-			| XB_WID_STAT_REG_ACC_ERR)) {
-
-	    printk("%s Port 0 XIO Bus Error",
-		    soft->name);
-	    if (wid_stat & XB_WID_STAT_MULTI_ERR)
-		XEM_ADD_STR("\tMultiple Error\n");
-	    if (wid_stat & XB_WID_STAT_XTALK_ERR)
-		XEM_ADD_STR("\tXIO Error\n");
-	    if (wid_stat & XB_WID_STAT_REG_ACC_ERR)
-		XEM_ADD_STR("\tRegister Access Error\n");
-
-	    fatal++;
-	}
-    }
-    if (fatal) {
-	XEM_ADD_VAR(wid_stat);
-	XEM_ADD_VAR(wid_control);
-	XEM_ADD_VAR(wid_err_cmdword);
-	XEM_ADD_VAR(wid_err_upper);
-	XEM_ADD_VAR(wid_err_lower);
-	XEM_ADD_VAR(wid_err_addr);
-	PRINT_PANIC("XIO Bus Error");
-    }
-}
-#endif	/* LATER */
-
-/*
- * XBOW ERROR Handling routines.
- * These get invoked as part of walking down the error handling path
- * from hub/heart towards the I/O device that caused the error.
- */
-
-/*
- * xbow_error_handler
- *      XBow error handling dispatch routine.
- *      This is the primary interface used by external world to invoke
- *      in case of an error related to a xbow.
- *      Only functionality in this layer is to identify the widget handle
- *      given the widgetnum. Otherwise, xbow does not gathers any error
- *      data.
- */
-
-#ifdef LATER
-static int
-xbow_error_handler(
-		      void *einfo,
-		      int error_code,
-		      ioerror_mode_t mode,
-		      ioerror_t *ioerror)
-{
-    int                     retval = IOERROR_WIDGETLEVEL;
-
-    xbow_soft_t             soft = (xbow_soft_t) einfo;
-    int                     port;
-    devfs_handle_t            conn;
-    devfs_handle_t            busv;
-
-    xbow_t                 *xbow = soft->base;
-    xbowreg_t               wid_stat;
-    xbowreg_t               wid_err_cmdword;
-    xbowreg_t               wid_err_upper;
-    xbowreg_t               wid_err_lower;
-    uint64_t                 wid_err_addr;
-
-    xb_linkregs_t          *link;
-    xbowreg_t               link_control;
-    xbowreg_t               link_status;
-    xbowreg_t               link_aux_status;
-
-    ASSERT(soft != 0);
-    busv = soft->busv;
-
-#if DEBUG && ERROR_DEBUG
-    printk("%s: xbow_error_handler\n", soft->name, busv);
-#endif
-
-    port = IOERROR_GETVALUE(ioerror, widgetnum);
-
-    if (port == 0) {
-	/* error during access to xbow:
-	 * do NOT attempt to access xbow regs.
-	 */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on Crossbow at %s\n"
-		    "\tbut Crosbow never initiates DMA!",
-		    soft->name);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERt("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO controller\n"
-		    "\twith offset 0x%X",
-		    soft->name,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-	/* caller will dump contents of ioerror
-	 * in DEBUG and kdebug kernels.
-	 */
-
-	return retval;
-    }
-    /*
-     * error not on port zero:
-     * safe to read xbow registers.
-     */
-    wid_stat = xbow->xb_wid_stat;
-    wid_err_cmdword = xbow->xb_wid_err_cmdword;
-    wid_err_upper = xbow->xb_wid_err_upper;
-    wid_err_lower = xbow->xb_wid_err_lower;
-
-    wid_err_addr =
-	wid_err_lower
-	| (((iopaddr_t) wid_err_upper
-	    & WIDGET_ERR_UPPER_ADDR_ONLY)
-	   << 32);
-
-    if ((port < BASE_XBOW_PORT) ||
-	(port >= MAX_PORT_NUM)) {
-
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on XIO port at %s/%d\n"
-		    "\tbut Crossbow does not support that port",
-		    soft->name, port);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERT("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO port %d\n"
-		    "\t(which Crossbow does not support)"
-		    "\twith offset 0x%X",
-		    soft->name, port,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-#if !DEBUG
-	if (kdebug) {
-#endif
-	    XEM_ADD_STR("Raw status values for Crossbow:\n");
-	    XEM_ADD_VAR(wid_stat);
-	    XEM_ADD_VAR(wid_err_cmdword);
-	    XEM_ADD_VAR(wid_err_upper);
-	    XEM_ADD_VAR(wid_err_lower);
-	    XEM_ADD_VAR(wid_err_addr);
-#if !DEBUG
-	}
-#endif
-
-	/* caller will dump contents of ioerror
-	 * in DEBUG and kdebug kernels.
-	 */
-
-	return retval;
-    }
-    /* access to valid port:
-     * ok to check port status.
-     */
-
-    link = &(xbow->xb_link(port));
-    link_control = link->link_control;
-    link_status = link->link_status;
-    link_aux_status = link->link_aux_status;
-
-    /* Check that there is something present
-     * in that XIO port.
-     */
-    if (!(link_aux_status & XB_AUX_STAT_PRESENT)) {
-	/* nobody connected. */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on XIO port at %s/%d\n"
-		    "\tbut there is no device connected there.",
-		    soft->name, port);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERT("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO port %d\n"
-		    "\t(which has no device connected)"
-		    "\twith offset 0x%X",
-		    soft->name, port,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-#if !DEBUG
-	if (kdebug) {
-#endif
-	    XEM_ADD_STR("Raw status values for Crossbow:\n");
-	    XEM_ADD_VAR(wid_stat);
-	    XEM_ADD_VAR(wid_err_cmdword);
-	    XEM_ADD_VAR(wid_err_upper);
-	    XEM_ADD_VAR(wid_err_lower);
-	    XEM_ADD_VAR(wid_err_addr);
-	    XEM_ADD_VAR(port);
-	    XEM_ADD_VAR(link_control);
-	    XEM_ADD_VAR(link_status);
-	    XEM_ADD_VAR(link_aux_status);
-#if !DEBUG
-	}
-#endif
-	return retval;
-
-    }
-    /* Check that the link is alive.
-     */
-    if (!(link_status & XB_STAT_LINKALIVE)) {
-	/* nobody connected. */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	PRINT_ALERT("%s%sError on XIO Bus %s port %d",
-		(error_code & IOECODE_DMA) ? "DMA " : "",
-		(error_code & IOECODE_PIO) ? "PIO " : "",
-		soft->name, port);
-
-	if ((error_code & IOECODE_PIO) &&
-	    (IOERROR_FIELDVALID(ioerror, xtalkaddr))) {
-	    printk("\tAccess attempted to offset 0x%X\n",
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-	if (link_aux_status & XB_AUX_LINKFAIL_RST_BAD)
-	    XEM_ADD_STR("\tLink never came out of reset\n");
-	else
-	    XEM_ADD_STR("\tLink failed while transferring data\n");
-
-    }
-    /* get the connection point for the widget
-     * involved in this error; if it exists and
-     * is not our connectpoint, cycle back through
-     * xtalk_error_handler to deliver control to
-     * the proper handler (or to report a generic
-     * crosstalk error).
-     *
-     * If the downstream handler won't handle
-     * the problem, we let our upstream caller
-     * deal with it, after (in DEBUG and kdebug
-     * kernels) dumping the xbow state for this
-     * port.
-     */
-    conn = xbow_widget_lookup(busv, port);
-    if ((conn != GRAPH_VERTEX_NONE) &&
-	(conn != soft->conn)) {
-	retval = xtalk_error_handler(conn, error_code, mode, ioerror);
-	if (retval == IOERROR_HANDLED)
-	    return IOERROR_HANDLED;
-    }
-    if (mode == MODE_DEVPROBE)
-	return IOERROR_HANDLED;
-
-    if (retval == IOERROR_UNHANDLED) {
-	retval = IOERROR_PANIC;
-
-	PRINT_ALERT("%s%sError on XIO Bus %s port %d",
-		(error_code & IOECODE_DMA) ? "DMA " : "",
-		(error_code & IOECODE_PIO) ? "PIO " : "",
-		soft->name, port);
-
-	if ((error_code & IOECODE_PIO) &&
-	    (IOERROR_FIELDVALID(ioerror, xtalkaddr))) {
-	    printk("\tAccess attempted to offset 0x%X\n",
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-    }
-
-#if !DEBUG
-    if (kdebug) {
-#endif
-	XEM_ADD_STR("Raw status values for Crossbow:\n");
-	XEM_ADD_VAR(wid_stat);
-	XEM_ADD_VAR(wid_err_cmdword);
-	XEM_ADD_VAR(wid_err_upper);
-	XEM_ADD_VAR(wid_err_lower);
-	XEM_ADD_VAR(wid_err_addr);
-	XEM_ADD_VAR(port);
-	XEM_ADD_VAR(link_control);
-	XEM_ADD_VAR(link_status);
-	XEM_ADD_VAR(link_aux_status);
-#if !DEBUG
-    }
-#endif
-    /* caller will dump raw ioerror data
-     * in DEBUG and kdebug kernels.
-     */
-
-    return retval;
-}
-
-#endif	/* LATER */
-
 void
 xbow_update_perf_counters(devfs_handle_t vhdl)
 {
@@ -1520,7 +1038,7 @@
 
 	if (lnk_sts.linkstatus & ~(XB_STAT_RCV_ERR | XB_STAT_XMT_RTRY_ERR | XB_STAT_LINKALIVE)) {
 #ifdef	LATER
-	    PRINT_WARNING("link %d[%s]: bad status 0x%x\n",
+	    printk(KERN_WARNING  "link %d[%s]: bad status 0x%x\n",
 		    link, xwidget_name, lnk_sts.linkstatus);
 #endif
 	}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/xswitch.c linux/arch/ia64/sn/io/xswitch.c
--- linux.orig/arch/ia64/sn/io/xswitch.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/io/xswitch.c	2002-08-01 06:42:35.000000000 +0000
@@ -4,14 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/io/xtalk.c linux/arch/ia64/sn/io/xtalk.c
--- linux.orig/arch/ia64/sn/io/xtalk.c	2001-04-12 19:16:35.000000000 +0000
+++ linux/arch/ia64/sn/io/xtalk.c	2002-08-01 06:42:33.000000000 +0000
@@ -4,24 +4,22 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/hcl_util.h>
-
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/xtalk/xswitch.h>
 #include <asm/sn/xtalk/xwidget.h>
-
 #include <asm/sn/xtalk/xtalk_private.h>
 
 /*
@@ -41,7 +39,6 @@
 
 cdl_p                   xtalk_registry = NULL;
 
-#include <asm/sn/agent.h>
 #define	DEV_FUNC(dev,func)	hub_##func
 #define	CAST_PIOMAP(x)		((hub_piomap_t)(x))
 #define	CAST_DMAMAP(x)		((hub_dmamap_t)(x))
@@ -72,7 +69,7 @@
 xtalk_intr_t            xtalk_intr_alloc(devfs_handle_t, device_desc_t, devfs_handle_t);
 xtalk_intr_t            xtalk_intr_alloc_nothd(devfs_handle_t, device_desc_t, devfs_handle_t);
 void                    xtalk_intr_free(xtalk_intr_t);
-int                     xtalk_intr_connect(xtalk_intr_t, intr_func_t, intr_arg_t, xtalk_intr_setfunc_t, void *, void *);
+int                     xtalk_intr_connect(xtalk_intr_t, xtalk_intr_setfunc_t, void *);
 void                    xtalk_intr_disconnect(xtalk_intr_t);
 devfs_handle_t            xtalk_intr_cpu_get(xtalk_intr_t);
 int                     xtalk_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
@@ -113,8 +110,6 @@
 					 xwidgetnum_t, devfs_handle_t, 
 					 xwidgetnum_t, async_attach_t);
 int			xwidget_unregister(devfs_handle_t);
-void                    xwidget_error_register(devfs_handle_t, error_handler_f *,
-					       error_handler_arg_t);
 void                    xwidget_reset(devfs_handle_t);
 char			*xwidget_name_get(devfs_handle_t);
 #if !defined(DEV_FUNC)
@@ -472,14 +467,11 @@
  */
 int
 xtalk_intr_connect(xtalk_intr_t intr_hdl,	/* xtalk intr resource handle */
-		   intr_func_t intr_func,	/* xtalk intr handler */
-		   intr_arg_t intr_arg,		/* arg to intr handler */
 		   xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
-		   void *setfunc_arg,	/* arg to setfunc */
-		   void *thread)
-{				/* intr thread to use */
+		   void *setfunc_arg)	/* arg to setfunc */
+{
     return INTR_FUNC(intr_hdl, intr_connect)
-	(CAST_INTR(intr_hdl), intr_func, intr_arg, setfunc, setfunc_arg, thread);
+	(CAST_INTR(intr_hdl), setfunc, setfunc_arg);
 }
 
 
@@ -506,85 +498,6 @@
 }
 
 
-/*
- * =====================================================================
- *                      ERROR MANAGEMENT
- */
-
-/*
- * xtalk_error_handler:
- * pass this error on to the handler registered
- * at the specified xtalk connecdtion point,
- * or complain about it here if there is no handler.
- *
- * This routine plays two roles during error delivery
- * to most widgets: first, the external agent (heart,
- * hub, or whatever) calls in with the error and the
- * connect point representing the crosstalk switch,
- * or whatever crosstalk device is directly connected
- * to the agent.
- *
- * If there is a switch, it will generally look at the
- * widget number stashed in the ioerror structure; and,
- * if the error came from some widget other than the
- * switch, it will call back into xtalk_error_handler
- * with the connection point of the offending port.
- */
-int
-xtalk_error_handler(
-		       devfs_handle_t xconn,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioerror)
-{
-    xwidget_info_t          xwidget_info;
-
-#if DEBUG && ERROR_DEBUG
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    printk("%v: xtalk_error_handler\n", xconn);
-#else
-    printk("%x: xtalk_error_handler\n", xconn);
-#endif
-#endif
-
-    xwidget_info = xwidget_info_get(xconn);
-    /* Make sure that xwidget_info is a valid pointer before derefencing it.
-     * We could come in here during very early initialization. 
-     */
-    if (xwidget_info && xwidget_info->w_efunc)
-	return xwidget_info->w_efunc
-	    (xwidget_info->w_einfo,
-	     error_code, mode, ioerror);
-    /*
-     * no error handler registered for
-     * the offending port. it's not clear
-     * what needs to be done, but reporting
-     * it would be a good thing, unless it
-     * is a mode that requires nothing.
-     */
-    if ((mode == MODE_DEVPROBE) || (mode == MODE_DEVUSERERROR) ||
-	(mode == MODE_DEVREENABLE))
-	return IOERROR_HANDLED;
-
-#ifdef	LATER
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    PRINT_WARNING("Xbow at %v encountered Fatal error", xconn);
-#else
-    PRINT_WARNING("Xbow at %x encountered Fatal error", xconn);
-#endif
-#endif	/* LATER */
-    ioerror_dump("xtalk", error_code, mode, ioerror);
-
-    return IOERROR_UNHANDLED;
-}
-
-int
-xtalk_error_devenable(devfs_handle_t xconn_vhdl, int devnum, int error_code)
-{
-    return DEV_FUNC(xconn_vhdl, error_devenable) (xconn_vhdl, devnum, error_code);
-}
-
-
 /* =====================================================================
  *                    CONFIGURATION MANAGEMENT
  */
@@ -977,7 +890,7 @@
     widget_info->w_einfo = 0;
     /*
      * get the name of this xwidget vertex and keep the info.
-     * This is needed during errors and interrupts, but as
+     * This is needed during errors and interupts, but as
      * long as we have it, we can use it elsewhere.
      */
     s = dev_to_name(widget,devnm,MAXDEVNAME);
@@ -1038,19 +951,6 @@
     return(0);
 }
 
-void
-xwidget_error_register(devfs_handle_t xwidget,
-		       error_handler_f *efunc,
-		       error_handler_arg_t einfo)
-{
-    xwidget_info_t          xwidget_info;
-
-    xwidget_info = xwidget_info_get(xwidget);
-    ASSERT(xwidget_info != NULL);
-    xwidget_info->w_efunc = efunc;
-    xwidget_info->w_einfo = einfo;
-}
-
 /*
  * Issue a link reset to a widget.
  */
@@ -1122,15 +1022,3 @@
 	
 	return(0);
 }
-/*
- * xtalk_device_inquiry
- *	Find out hardware information about the xtalk widget.
- */
-int
-xtalk_device_inquiry(devfs_handle_t xbus_vhdl, xwidgetnum_t widget)
-{
-
-	extern void hub_device_inquiry(devfs_handle_t, xwidgetnum_t);
-	hub_device_inquiry(xbus_vhdl, widget);
-	return(0);
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/Makefile linux/arch/ia64/sn/kernel/Makefile
--- linux.orig/arch/ia64/sn/kernel/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/Makefile	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,62 @@
+# arch/ia64/sn/Makefile
+#
+# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
+#
+# This program is free software; you can redistribute it and/or modify it 
+# under the terms of version 2 of the GNU General Public License 
+# as published by the Free Software Foundation.
+# 
+# This program is distributed in the hope that it would be useful, but 
+# WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+# 
+# Further, this software is distributed without any warranty that it is 
+# free of the rightful claim of any third person regarding infringement 
+# or the like.  Any license provided herein, whether implied or 
+# otherwise, applies only to this software file.  Patent licenses, if 
+# any, provided herein do not apply to combinations of this program with 
+# other software, or any other product whatsoever.
+# 
+# You should have received a copy of the GNU General Public 
+# License along with this program; if not, write the Free Software 
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+# 
+# Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+# Mountain View, CA  94043, or:
+# 
+# http://www.sgi.com 
+# 
+# For further information regarding this notice, see: 
+# 
+# http://oss.sgi.com/projects/GenInfo/NoticeExplan
+#
+
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+O_TARGET        = sn.o
+
+ifeq ($(CONFIG_MODULES),y)
+export-objs = sn_ksyms.o
+endif
+
+subdir-$(CONFIG_IA64_SGI_SN1)	= sn1
+subdir-$(CONFIG_IA64_SGI_SN2)	= sn2
+
+obj-y		= probe.o setup.o sn_asm.o sv.o bte.o iomv.o
+obj-$(CONFIG_IA64_SGI_SN1)      += irq.o mca.o
+obj-$(CONFIG_IA64_SGI_SN2)      += irq.o mca.o
+
+obj-$(CONFIG_IA64_SGI_SN1)      += sn1/sn1.a  
+obj-$(CONFIG_IA64_SGI_SN2)      += sn2/sn2.a  
+
+obj-$(CONFIG_IA64_SGI_AUTOTEST) += llsc4.o misctest.o
+obj-$(CONFIG_IA64_GENERIC)      += machvec.o
+obj-$(CONFIG_MODULES)           += sn_ksyms.o
+
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/bte.c linux/arch/ia64/sn/kernel/bte.c
--- linux.orig/arch/ia64/sn/kernel/bte.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/bte.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,263 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <asm/sn/nodepda.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pda.h>
+#include <asm/nodedata.h>
+
+#include <linux/bootmem.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+
+#include <asm/sn/bte_copy.h>
+
+int bte_offsets[] = { IIO_IBLS0, IIO_IBLS1 };
+
+/*
+ * bte_init_node(nodepda, cnode, cmdline_p)
+ *
+ * Initialize the nodepda structure with BTE base addresses and
+ * spinlocks.
+ *
+ */
+void
+bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode, char **cmdline_p)
+{
+	int bteTestMode = 0;
+	int cmdoffset = 0;
+	int i;
+
+#ifdef ZZZ
+	if (!cmdoffset) {
+		for (;cmdline_p[cmdoffset]; cmdoffset++) {
+			if (strstr(cmdline_p[cmdoffset], "btetest")) {
+				bteTestMode = 1;
+				break;
+			}
+		}
+	}
+#endif
+
+	/*
+	 * Indicate that all the block transfer engines on this node
+	 * are available.
+	 */
+	for (i = 0; i < BTES_PER_NODE; i++) {
+#ifdef CONFIG_IA64_SGI_SN2
+		/* >>> Don't know why the 0x1800000L is here.  Robin */
+		mynodepda->node_bte_info[i].bte_base_addr =
+		    (char *)LOCAL_MMR_ADDR(bte_offsets[i] | 0x1800000L);
+#elif CONFIG_IA64_SGI_SN1
+		mynodepda->node_bte_info[i].bte_base_addr =
+		    (char *)LOCAL_HUB_ADDR(bte_offsets[i]);
+#else
+#error BTE Not defined for this hardware platform.
+#endif
+
+#ifdef CONFIG_IA64_SGI_BTE_LOCKING
+		/* Initialize the notification and spinlock */
+		/* so the first transfer can occur. */
+		mynodepda->node_bte_info[i].mostRecentNotification =
+		    &(mynodepda->node_bte_info[i].notify);
+		mynodepda->node_bte_info[i].notify = 0L;
+		spin_lock_init(&mynodepda->node_bte_info[i].spinlock);
+#endif				/* CONFIG_IA64_SGI_BTE_LOCKING */
+
+		if (bteTestMode) {
+			mynodepda->node_bte_info[i].bteTestBuf =
+				alloc_bootmem_node(NODE_DATA(cnode),
+						   BTE_MAX_XFER);
+		}
+	}
+}
+
+/*
+ * bte_init_cpu()
+ *
+ * Initialize the cpupda structure with pointers to the
+ * nodepda bte blocks.
+ *
+ */
+void
+bte_init_cpu(void)
+{
+	/* Called by setup.c as each cpu is being added to the nodepda */
+	if (local_node_data->active_cpu_count & 0x1) {
+		pda.cpubte[0] = &(nodepda->node_bte_info[0]);
+		pda.cpubte[1] = &(nodepda->node_bte_info[1]);
+	} else {
+		pda.cpubte[0] = &(nodepda->node_bte_info[1]);
+		pda.cpubte[1] = &(nodepda->node_bte_info[0]);
+	}
+}
+
+
+/*
+ * bte_unaligned_copy(src, dest, len, mode)
+ *
+ * use the block transfer engine to move kernel
+ * memory from src to dest using the assigned mode.
+ *
+ * Paramaters:
+ *   src - physical address of the transfer source.
+ *   dest - physical address of the transfer destination.
+ *   len - number of bytes to transfer from source to dest.
+ *   mode - hardware defined.  See reference information
+ *          for IBCT0/1 in the SGI documentation.
+ *   bteBlock - kernel virtual address of a temporary
+ *              buffer used during unaligned transfers.
+ *
+ * NOTE: If the source, dest, and len are all cache line aligned,
+ * then it would be _FAR_ preferrable to use bte_copy instead.
+ */
+bte_result_t
+bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode, char *bteBlock)
+{
+	int destFirstCacheOffset;
+	u64 headBteSource;
+	u64 headBteLen;
+	u64 headBcopySrcOffset;
+	u64 headBcopyDest;
+	u64 headBcopyLen;
+	u64 footBteSource;
+	u64 footBteLen;
+	u64 footBcopyDest;
+	u64 footBcopyLen;
+	bte_result_t rv;
+
+	if (len == 0) {
+		return (BTE_SUCCESS);
+	}
+
+	headBcopySrcOffset = src & L1_CACHE_MASK;
+	destFirstCacheOffset = dest & L1_CACHE_MASK;
+
+	/*
+	 * At this point, the transfer is broken into
+	 * (up to) three sections.  The first section is
+	 * from the start address to the first physical
+	 * cache line, the second is from the first physical
+	 * cache line to the last complete cache line,
+	 * and the third is from the last cache line to the
+	 * end of the buffer.  The first and third sections
+	 * are handled by bte copying into a temporary buffer
+	 * and then bcopy'ing the necessary section into the
+	 * final location.  The middle section is handled with
+	 * a standard bte copy.
+	 *
+	 * One nasty exception to the above rule is when the
+	 * source and destination are not symetrically
+	 * mis-aligned.  If the source offset from the first
+	 * cache line is different from the destination offset,
+	 * we make the first section be the entire transfer
+	 * and the bcopy the entire block into place.
+	 */
+	if (headBcopySrcOffset == destFirstCacheOffset) {
+
+		/*
+		 * Both the source and destination are the same
+		 * distance from a cache line boundary so we can
+		 * use the bte to transfer the bulk of the
+		 * data.
+		 */
+		headBteSource = src & ~L1_CACHE_MASK;
+		headBcopyDest = dest;
+		if (headBcopySrcOffset) {
+			headBcopyLen =
+			    (len >
+			     (L1_CACHE_BYTES -
+			      headBcopySrcOffset) ? L1_CACHE_BYTES
+			     - headBcopySrcOffset : len);
+			headBteLen = L1_CACHE_BYTES;
+		} else {
+			headBcopyLen = 0;
+			headBteLen = 0;
+		}
+
+		if (len > headBcopyLen) {
+			footBcopyLen =
+			    (len - headBcopyLen) & L1_CACHE_MASK;
+			footBteLen = L1_CACHE_BYTES;
+
+			footBteSource = src + len - footBcopyLen;
+			footBcopyDest = dest + len - footBcopyLen;
+
+			if (footBcopyDest ==
+			    (headBcopyDest + headBcopyLen)) {
+				/*
+				 * We have two contigous bcopy
+				 * blocks.  Merge them.
+				 */
+				headBcopyLen += footBcopyLen;
+				headBteLen += footBteLen;
+			} else if (footBcopyLen > 0) {
+				rv = bte_copy(footBteSource,
+					      __pa(bteBlock),
+					      footBteLen, mode, NULL);
+				if (rv != BTE_SUCCESS) {
+					return (rv);
+				}
+
+
+				memcpy(__va(footBcopyDest),
+				       (char *)bteBlock, footBcopyLen);
+			}
+		} else {
+			footBcopyLen = 0;
+			footBteLen = 0;
+		}
+
+		if (len > (headBcopyLen + footBcopyLen)) {
+			/* now transfer the middle. */
+			rv = bte_copy((src + headBcopyLen),
+				      (dest +
+				       headBcopyLen),
+				      (len - headBcopyLen -
+				       footBcopyLen), mode, NULL);
+			if (rv != BTE_SUCCESS) {
+				return (rv);
+			}
+
+		}
+	} else {
+
+
+		/*
+		 * The transfer is not symetric, we will
+		 * allocate a buffer large enough for all the
+		 * data, bte_copy into that buffer and then
+		 * bcopy to the destination.
+		 */
+
+		/* Add the leader from source */
+		headBteLen = len + (src & L1_CACHE_MASK);
+		/* Add the trailing bytes from footer. */
+		headBteLen +=
+		    L1_CACHE_BYTES - (headBteLen & L1_CACHE_MASK);
+		headBteSource = src & ~L1_CACHE_MASK;
+		headBcopySrcOffset = src & L1_CACHE_MASK;
+		headBcopyDest = dest;
+		headBcopyLen = len;
+	}
+
+	if (headBcopyLen > 0) {
+		rv = bte_copy(headBteSource,
+			      __pa(bteBlock), headBteLen, mode, NULL);
+		if (rv != BTE_SUCCESS) {
+			return (rv);
+		}
+
+		memcpy(__va(headBcopyDest), ((char *)bteBlock +
+					     headBcopySrcOffset),
+		       headBcopyLen);
+	}
+	return (BTE_SUCCESS);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/iomv.c linux/arch/ia64/sn/kernel/iomv.c
--- linux.orig/arch/ia64/sn/kernel/iomv.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/iomv.c	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,119 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <asm/io.h>
+
+#if 1	/* ##jh */
+#ifdef CONFIG_IA64_SGI_SN1
+#define mmiob sn1_mmiob
+#else
+#define mmiob sn2_mmiob
+#endif
+extern void mmiob(void);
+#endif /* ##jh */
+
+extern void * sn_io_addr(unsigned long port); /* defined in sn[12]/iomv.c */
+
+/**
+ * sn_inb - read a byte from a port
+ * @port: port to read from
+ *
+ * Reads a byte from @port and returns it to the caller.
+ */
+unsigned int
+sn_inb (unsigned long port)
+{
+	volatile unsigned char *addr = sn_io_addr(port);
+	unsigned char ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn_inw - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn_inw (unsigned long port)
+{
+	volatile unsigned short *addr = sn_io_addr(port);
+	unsigned short ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn_inl - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn_inl (unsigned long port)
+{
+	volatile unsigned int *addr = sn_io_addr(port);
+	unsigned int ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn_outb - write a byte to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn_outb (unsigned char val, unsigned long port)
+{
+	volatile unsigned char *addr = sn_io_addr(port);
+
+	*addr = val;
+	mmiob();
+}
+
+/**
+ * sn_outw - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn_outw (unsigned short val, unsigned long port)
+{
+	volatile unsigned short *addr = sn_io_addr(port);
+
+	*addr = val;
+	mmiob();
+}
+
+/**
+ * sn_outl - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn_outl (unsigned int val, unsigned long port)
+{
+	volatile unsigned int *addr = sn_io_addr(port);
+
+	*addr = val;
+	mmiob();
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/irq.c linux/arch/ia64/sn/kernel/irq.c
--- linux.orig/arch/ia64/sn/kernel/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/irq.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,343 @@
+/*
+ * Platform dependent support for SGI SN1
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <asm/current.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/types.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pciio_private.h>
+#ifdef ajmtestintr
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#endif /* ajmtestintr */
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/io.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/arch.h>
+
+int irq_to_bit_pos(int irq);
+
+
+
+static unsigned int
+sn_startup_irq(unsigned int irq)
+{
+        return(0);
+}
+
+static void
+sn_shutdown_irq(unsigned int irq)
+{
+}
+
+static void
+sn_disable_irq(unsigned int irq)
+{
+}
+
+static void
+sn_enable_irq(unsigned int irq)
+{
+}
+
+static void
+sn_ack_irq(unsigned int irq)
+{
+#ifdef CONFIG_IA64_SGI_SN1
+	int bit = -1;
+	unsigned long long intpend_val;
+	int subnode;
+#endif
+#ifdef CONFIG_IA64_SGI_SN2
+	unsigned long event_occurred, mask = 0;
+#endif
+	int nasid;
+
+	irq = irq & 0xff;
+	nasid = smp_physical_node_id();
+#ifdef CONFIG_IA64_SGI_SN1
+	subnode = cpuid_to_subnode(smp_processor_id());
+	if (irq == SGI_UART_IRQ) {
+		intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
+		if (intpend_val & (1L<<GFX_INTR_A) ) {
+			bit = GFX_INTR_A;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if ( intpend_val & (1L<<GFX_INTR_B) ) {
+			bit = GFX_INTR_B;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<PG_MIG_INTR) ) {
+			bit = PG_MIG_INTR;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<CC_PEND_A)) {
+			bit = CC_PEND_A;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<CC_PEND_B)) {
+			bit = CC_PEND_B;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		return;
+	}
+	bit = irq_to_bit_pos(irq);
+	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN2
+	event_occurred = HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid,SH_EVENT_OCCURRED) );
+	if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_UART_INT_SHFT);
+	}
+	if (event_occurred & SH_EVENT_OCCURRED_IPI_INT_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_IPI_INT_SHFT);
+	}
+	if (event_occurred & SH_EVENT_OCCURRED_II_INT0_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_II_INT0_SHFT);
+	}
+	if (event_occurred & SH_EVENT_OCCURRED_II_INT1_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_II_INT1_SHFT);
+	}
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED_ALIAS), mask );
+#endif
+}
+
+static void
+sn_end_irq(unsigned int irq)
+{
+#ifdef CONFIG_IA64_SGI_SN1
+	unsigned long long intpend_val, mask = 0x70L;
+	int subnode;
+#endif
+	int nasid;
+#ifdef CONFIG_IA64_SGI_SN2
+	unsigned long event_occurred;
+#endif
+
+	irq = irq & 0xff;
+#ifdef CONFIG_IA64_SGI_SN1
+	if (irq == SGI_UART_IRQ) {
+		nasid = smp_physical_node_id();
+		subnode = cpuid_to_subnode(smp_processor_id());
+		intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
+		if (intpend_val & mask) {
+			platform_send_ipi(smp_processor_id(), SGI_UART_IRQ, IA64_IPI_DM_INT, 0);
+		}
+	}
+#endif
+#ifdef CONFIG_IA64_SGI_SN2
+	if (irq == SGI_UART_VECTOR) {
+		nasid = smp_physical_node_id();
+		event_occurred = HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid,SH_EVENT_OCCURRED) );
+		// If the UART bit is set here, we may have received an interrupt from the
+		// UART that the driver missed.  To make sure, we IPI ourselves to force us
+		// to look again.
+		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
+				platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, IA64_IPI_DM_INT, 0);
+		}
+	}
+#endif
+
+}
+
+static void
+sn_set_affinity_irq(unsigned int irq, unsigned long mask)
+{
+}
+
+
+struct hw_interrupt_type irq_type_iosapic_level = {
+	"SN hub",
+	sn_startup_irq,
+	sn_shutdown_irq,
+	sn_enable_irq,
+	sn_disable_irq,
+	sn_ack_irq, 
+	sn_end_irq,
+	sn_set_affinity_irq
+};
+
+
+#define irq_type_sn irq_type_iosapic_level
+struct irq_desc *_sn_irq_desc[NR_CPUS];
+
+struct irq_desc *
+sn_irq_desc(unsigned int irq) {
+	int cpu = irq >> 8;
+
+	irq = irq & 0xff;
+
+	return(_sn_irq_desc[cpu] + irq);
+}
+
+u8
+sn_irq_to_vector(u8 irq) {
+	return(irq & 0xff);
+}
+
+unsigned int
+sn_local_vector_to_irq(u8 vector) {
+	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
+}
+
+int
+sn_valid_irq(u8 irq) {
+
+	return( ((irq & 0xff) < NR_IRQS) && ((irq >> 8) < NR_CPUS) );
+}
+
+void *kmalloc(size_t, int);
+
+void
+sn_irq_init (void)
+{
+	int i;
+	irq_desc_t *base_desc = _irq_desc;
+
+	for (i=IA64_FIRST_DEVICE_VECTOR; i<NR_IRQS; i++) {
+		if (base_desc[i].handler == &no_irq_type) {
+			base_desc[i].handler = &irq_type_sn;
+		}
+	}
+}
+
+void
+sn_init_irq_desc(void) {
+	int i;
+	irq_desc_t *base_desc = _irq_desc, *p;
+
+	for (i=0; i < NR_CPUS; i++) {
+		p =  page_address(alloc_pages_node(local_cnodeid(), GFP_KERNEL,
+			get_order(sizeof(struct irq_desc) * NR_IRQS) ) );
+		ASSERT(p);
+		memcpy(p, base_desc, sizeof(struct irq_desc) * NR_IRQS);
+		_sn_irq_desc[i] = p;
+	}
+}
+
+
+#if !defined(CONFIG_IA64_SGI_SN)
+void
+sn_pci_fixup(void)
+{
+}
+#endif
+
+int
+bit_pos_to_irq(int bit) {
+#define BIT_TO_IRQ 64
+	if (bit > 118) bit = 118;
+
+#ifdef CONFIG_IA64_SGI_SN1
+	if (bit >= GFX_INTR_A && bit <= CC_PEND_B) {
+		return SGI_UART_IRQ;
+	}
+#endif
+
+        return bit + BIT_TO_IRQ;
+}
+
+int
+irq_to_bit_pos(int irq) {
+#define IRQ_TO_BIT 64
+	int bit = irq - IRQ_TO_BIT;
+
+        return bit;
+}
+
+#ifdef ajmtestintr
+
+#include <linux/timer.h>
+struct timer_list intr_test_timer;
+int intr_test_icount[NR_IRQS];
+struct intr_test_reg_struct {
+	pcibr_soft_t pcibr_soft;
+	int slot;
+};
+struct intr_test_reg_struct intr_test_registered[NR_IRQS];
+
+void
+intr_test_handle_timer(unsigned long data) {
+	int i;
+	bridge_t	*bridge;
+
+	for (i=0;i<NR_IRQS;i++) {
+		if (intr_test_registered[i].pcibr_soft) {
+			pcibr_soft_t pcibr_soft = intr_test_registered[i].pcibr_soft;
+			xtalk_intr_t intr = pcibr_soft->bs_intr[intr_test_registered[i].slot].bsi_xtalk_intr;
+			/* send interrupt */
+			bridge = pcibr_soft->bs_base;
+			bridge->b_force_always[intr_test_registered[i].slot].intr = 1;
+		}
+	}
+	del_timer(&intr_test_timer);
+	intr_test_timer.expires = jiffies + HZ/100;
+	add_timer(&intr_test_timer);
+}
+
+void
+intr_test_set_timer(void) {
+	intr_test_timer.expires = jiffies + HZ/100;
+	intr_test_timer.function = intr_test_handle_timer;
+	add_timer(&intr_test_timer);
+}
+
+void
+intr_test_register_irq(int irq, pcibr_soft_t pcibr_soft, int slot) {
+	irq = irq & 0xff;
+	intr_test_registered[irq].pcibr_soft = pcibr_soft;
+	intr_test_registered[irq].slot = slot;
+}
+
+void
+intr_test_handle_intr(int irq, void *junk, struct pt_regs *morejunk) {
+	intr_test_icount[irq]++;
+	printk("RECEIVED %d INTERRUPTS ON IRQ %d\n",intr_test_icount[irq], irq);
+}
+#endif /* ajmtestintr */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/llsc4.c linux/arch/ia64/sn/kernel/llsc4.c
--- linux.orig/arch/ia64/sn/kernel/llsc4.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/llsc4.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,1044 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel_stat.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <asm/efi.h>
+#include <asm/page.h>
+#include <linux/threads.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/leds.h>
+
+#include "llsc4.h"
+
+
+#ifdef STANDALONE
+#include "lock.h"
+#endif
+
+#ifdef INTTEST
+static int	inttest=0;
+#endif
+
+#ifdef IA64_SEMFIX_INSN
+#undef IA64_SEMFIX_INSN
+#endif
+#ifdef IA64_SEMFIX
+#undef IA64_SEMFIX
+#endif
+# define IA64_SEMFIX_INSN
+# define IA64_SEMFIX    ""
+
+#define NOLOCK		0xdead
+#define BGUARD(linei)	(0xbbbb0000 | (linei));
+#define EGUARD(linei)	(0xeeee0000 | (linei));
+#define GUARDLINE(v)	((v)&0xffff)
+
+/*
+ * Test parameter table for AUTOTEST
+ */
+typedef struct {
+	int	passes;
+	int	linecount;
+	int	linepad;
+} autotest_table_t;
+
+autotest_table_t autotest_table[] = {
+	{50000000,	2,	0x2b4		},
+	{50000000,	16,	0,		},
+	{50000000,	16,	4,		},
+	{50000000,	128,	0x44		},
+	{50000000,	128,	0x84		},
+	{50000000,	128,	0x200		},
+	{50000000,	128,	0x204		},
+	{50000000,	128,	0x2b4		},
+	{50000000,	2,	8*MB+0x2b4	},
+	{50000000,	16,	8*MB+0		},
+	{50000000,	16,	8*MB+4		},
+	{50000000,	128,	8*MB+0x44	},
+	{50000000,	128,	8*MB+0x84	},
+	{50000000,	128,	8*MB+0x200	},
+	{50000000,	128,	8*MB+0x204	},
+	{50000000,	128,	8*MB+0x2b4	},
+	{0}};
+
+/*
+ * Array of virtual addresses available for test purposes.
+ */
+
+typedef struct {
+	long	vstart;
+	long	vend;
+	long	nextaddr;
+	long	nextinit;
+	int	wrapcount;
+} memmap_t;
+
+#define MAPCHUNKS		128
+memmap_t 	memmap[MAPCHUNKS];
+int		memmapx=0;
+
+typedef struct {
+	void	*addr;
+	long	data[16];
+	long	data_fc[16];
+} capture_line_t;
+
+typedef struct {
+	int	size;
+	void	*blockaddr;
+	void	*shadaddr;
+	long	blockdata[48];
+	long	shaddata[48];
+	long	blockdata_fc[48];
+	long	shaddata_fc[48];
+	long	synerr;
+} capture_t;
+
+/*
+ * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and
+ * the rest of the tables have to start at 1MB to skip PROM tables.
+ */
+#define THREADPRIVATESZ()	((sizeof(threadprivate_t)+511)/512*512)
+#define THREADPRIVATE(t)	((threadprivate_t*)(((long)mbase)+4096+t*THREADPRIVATESZ()))
+
+#define k_capture		mbase->sk_capture
+#define k_go			mbase->sk_go
+#define k_linecount		mbase->sk_linecount
+#define k_passes		mbase->sk_passes
+#define k_napticks		mbase->sk_napticks
+#define k_stop_on_error		mbase->sk_stop_on_error
+#define k_verbose		mbase->sk_verbose
+#define k_threadprivate		mbase->sk_threadprivate
+#define k_blocks		mbase->sk_blocks
+#define k_iter_msg		mbase->sk_iter_msg
+#define k_vv			mbase->sk_vv
+#define k_linepad		mbase->sk_linepad
+#define k_options		mbase->sk_options
+#define k_testnumber		mbase->sk_testnumber
+#define k_currentpass		mbase->sk_currentpass
+
+static long		blocks[MAX_LINECOUNT];		/* addresses of data blocks */
+static control_t	*mbase;
+static vint		initialized=0;
+
+static unsigned int ran_conf_llsc(int);
+static int  rerr(capture_t *, char *, void *, void *, int, int, int, int, int, int);
+static void dumpline(void *, char *, char *, void *, void *, int);
+static int  checkstop(int, int, uint);
+static void spin(int);
+static void capturedata(capture_t *, uint, void *, void *, int);
+static int  randn(uint max, uint *seed);
+static uint zrandom (uint *zranseed);
+static int  set_lock(uint *, uint);
+static int  clr_lock(uint *, uint);
+static void Speedo(void);
+
+int autotest_enabled=0;
+static int llsctest_number=-1;
+static int errstop_enabled=0;
+static int fail_enabled=0;
+static int l4_opt=0;
+static int selective_trigger=0;
+static int dump_block_addrs_opt=0;
+static lock_t errlock=NOLOCK;
+static private_t init_private[LLSC_MAXCPUS];
+
+static int __init autotest_enable(char *str)
+{
+        autotest_enabled = 1;
+	return 1;
+}
+static int __init set_llscblkadr(char *str)
+{
+	dump_block_addrs_opt = 1;
+	return 1;
+}
+static int __init set_llscselt(char *str)
+{
+	selective_trigger = 1;
+	return 1;
+}
+static int __init set_llsctest(char *str)
+{
+        llsctest_number = simple_strtol(str, &str, 10);
+	if (llsctest_number < 0 || llsctest_number > 15)
+		llsctest_number = -1;
+	return 1;
+}
+static int __init set_llscerrstop(char *str)
+{
+        errstop_enabled = 1;
+	return 1;
+}
+static int __init set_llscfail(char *str)
+{
+        fail_enabled = 8;
+	return 1;
+}
+static int __init set_llscl4(char *str)
+{
+        l4_opt = 1;
+	return 1;
+}
+
+static void print_params(void)
+{
+	printk ("********* Enter AUTOTEST facility on master cpu *************\n");
+	printk ("  Test options:\n");
+	printk ("     llsctest=<n>\t%d\tTest number to run (all = -1)\n", llsctest_number);
+	printk ("     llscerrstop \t%s\tStop on error\n", errstop_enabled ? "on" : "off");
+	printk ("     llscfail    \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off");
+	printk ("     llscselt    \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off");
+	printk ("     llscblkadr  \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off");
+	printk ("     llscl4      \t%s\tRun only tests that evict from L4\n", l4_opt ? "on" : "off");
+	printk ("  SEMFIX: %s\n", IA64_SEMFIX);
+	printk ("\n");
+}
+__setup("autotest", autotest_enable);
+__setup("llsctest=", set_llsctest);
+__setup("llscerrstop", set_llscerrstop);
+__setup("llscfail", set_llscfail);
+__setup("llscselt", set_llscselt);
+__setup("llscblkadr", set_llscblkadr);
+__setup("llscl4", set_llscl4);
+
+
+
+static inline int
+set_lock(uint *lock, uint id)
+{
+	uint	old;
+	old = cmpxchg_acq(lock, NOLOCK, id);
+	return (old == NOLOCK);
+}
+
+static inline int
+clr_lock(uint *lock, uint id)
+{
+	uint	old;
+	old = cmpxchg_rel(lock, id, NOLOCK);
+	return (old == id);
+}
+
+static inline void
+init_lock(uint *lock)
+{
+	*lock = NOLOCK;
+}
+
+/*------------------------------------------------------------------------+
+| Routine  :  ran_conf_llsc - ll/sc shared data test                      |
+| Description: This test checks the coherency of shared data              |
++------------------------------------------------------------------------*/
+static unsigned int
+ran_conf_llsc(int thread)
+{
+	private_t	pval;
+	share_t		sval, sval2;
+	uint		vv, linei, slinei, sharei, pass;
+	long		t;
+	lock_t		lockpat;
+	share_t		*sharecopy;
+	long		verbose, napticks, passes, linecount, lcount;
+	dataline_t	*linep, *slinep;
+	int		s, seed;
+	threadprivate_t	*tp;
+	uint		iter_msg, iter_msg_i=0;
+	int		vv_mask;
+	int		correct_errors;
+	int		errs=0;
+	int		stillbad;
+	capture_t	capdata;
+	private_t	*privp;
+	share_t		*sharep;
+
+
+	linecount = k_linecount;
+	napticks = k_napticks;
+	verbose = k_verbose;
+	passes = k_passes;
+	iter_msg = k_iter_msg;
+	seed = (thread + 1) * 647;
+	tp = THREADPRIVATE(thread);
+	vv_mask = (k_vv>>((thread%16)*4)) & 0xf;
+	correct_errors = k_options&0xff;
+
+	memset (&capdata, 0, sizeof(capdata));
+	for (linei=0; linei<linecount; linei++)
+		tp->private[linei] = thread;	
+
+	for (pass = 1; passes == 0 || pass < passes; pass++) {
+		lockpat = (pass & 0x0fffffff) + (thread <<28);
+		if (lockpat == NOLOCK)
+			continue;
+		tp->threadpasses = pass;
+		if (checkstop(thread, pass, lockpat))
+			return 0;
+		iter_msg_i++;
+		if (iter_msg && iter_msg_i > iter_msg) {
+			printk("Thread %d, Pass %d\n", thread, pass);
+			iter_msg_i = 0;
+		}
+		lcount = 0;
+
+		/*
+		 * Select line to perform operations on.
+		 */
+		linei = randn(linecount, &seed);
+		sharei = randn(2, &seed);
+		slinei = (linei + (linecount/2))%linecount;		/* I dont like this - fix later */
+
+		linep = (dataline_t *)blocks[linei];
+		slinep = (dataline_t *)blocks[slinei];
+		if (sharei == 0)
+			sharecopy = &slinep->share0;
+		else
+			sharecopy = &slinep->share1;
+
+
+		vv = randn(4, &seed);
+		if ((vv_mask & (1<<vv)) == 0)
+			continue;
+
+		if (napticks) {
+			t = randn(napticks, &seed);
+			udelay(t);
+		}
+		privp = &linep->private[thread];
+		sharep = &linep->share[sharei];
+		
+		switch(vv) {
+		case 0:
+			/* Read and verify private count on line. */
+			pval = *privp;
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
+			if (pval != tp->private[linei]) {
+				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
+				stillbad = (*privp != tp->private[linei]);
+				if (rerr(&capdata, "Private count", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
+					return 1;
+				}
+				if (correct_errors) {
+					tp->private[linei] = *privp;
+				}
+				errs++;
+			}
+			break;
+
+		case 1:
+			/* Read, verify, and increment private count on line. */
+			pval = *privp;
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
+			if (pval != tp->private[linei]) {
+				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
+				stillbad = (*privp != tp->private[linei]);
+				if (rerr(&capdata, "Private count & inc", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
+					return 1;
+				}
+				errs++;
+			}
+			pval = (pval==255) ? 0 : pval+1;
+			*privp = pval;
+			tp->private[linei] = pval;
+			break;
+
+		case 2:
+			/* Lock line, read and verify shared data. */
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
+			lcount = 0;
+			while (LOCK(sharei) != 1) {
+				if (checkstop(thread, pass, lockpat))
+					return 0;
+				if (lcount++>1000000) {
+					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
+					stillbad = (GETLOCK(sharei) != 0);
+					rerr(&capdata, "Shared data lock", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
+					return 1;
+				}
+				if ((lcount&0x3fff) == 0)
+					udelay(1000);
+			}
+
+			sval = *sharep;
+			sval2 = *sharecopy;
+			if (pass > 12 && thread == 0 && fail_enabled == 1)
+				sval++;
+			if (sval != sval2) {
+				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
+				stillbad = (*sharep != *sharecopy);
+				if (!stillbad && *sharep != sval && *sharecopy == sval2)
+					stillbad = 2;
+				if (rerr(&capdata, "Shared data", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
+					return 1;
+				}
+				if (correct_errors)
+					*sharep = *sharecopy;
+				errs++;
+			}
+
+
+			if ( (s=UNLOCK(sharei)) != 1) {
+				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
+				stillbad = (GETLOCK(sharei) != lockpat);
+				if (rerr(&capdata, "Shared data unlock", linep, slinep, thread, pass, linei, lockpat, GETLOCK(sharei), stillbad))
+					return 1;
+				if (correct_errors)
+					ZEROLOCK(sharei);	
+				errs++;
+			}
+			break;
+
+		case 3:
+			/* Lock line, read and verify shared data, modify shared data. */
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
+			lcount = 0;
+			while (LOCK(sharei) != 1) {
+				if (checkstop(thread, pass, lockpat))
+					return 0;
+				if (lcount++>1000000) {
+					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
+					stillbad = (GETLOCK(sharei) != 0);
+					rerr(&capdata, "Shared data lock & inc", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
+					return 1;
+				}
+				if ((lcount&0x3fff) == 0)
+					udelay(1000);
+			}
+			sval = *sharep;
+			sval2 = *sharecopy;
+			if (sval != sval2) {
+				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
+				stillbad = (*sharep != *sharecopy);
+				if (!stillbad && *sharep != sval && *sharecopy == sval2)
+					stillbad = 2;
+				if (rerr(&capdata, "Shared data & inc", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
+					return 1;
+				}
+				errs++;
+			}
+
+			*sharep = lockpat;
+			*sharecopy = lockpat;
+
+
+			if ( (s=UNLOCK(sharei)) != 1) {
+				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
+				stillbad = (GETLOCK(sharei) != lockpat);
+				if (rerr(&capdata, "Shared data & inc unlock", linep, slinep, thread, pass, linei, thread, GETLOCK(sharei), stillbad))
+					return 1;
+				if (correct_errors)
+					ZEROLOCK(sharei);	
+				errs++;
+			}
+			break;
+		}
+	}
+
+	return (errs > 0);
+}
+
+static void
+trigger_la(long val)
+{
+	long	*p;
+
+	p = (long*)0xc0000a0001000020L; /* PI_CPU_NUM */
+	*p = val;
+}
+
+static long
+getsynerr(void)
+{
+	long	err, *errp;
+
+	errp = (long*)0xc0000e0000000340L;	/* SYN_ERR */
+	err = *errp;
+	if (err)
+		*errp = -1L;
+	return (err & ~0x60);
+}
+
+static int
+rerr(capture_t *cap, char *msg, void *lp, void *slp, int thread, int pass, int badlinei, int exp, int found, int stillbad)
+{
+	int		cpu, i, linei;
+	long 		synerr;
+	int		selt;
+
+
+	selt = selective_trigger && stillbad > 1 && 
+			memcmp(cap->blockdata, cap->blockdata_fc, 128) != 0 &&
+			memcmp(cap->shaddata, cap->shaddata_fc, 128) == 0;
+	if (selt) {
+		trigger_la(pass);
+	} else if (selective_trigger) {
+		k_go = ST_STOP;
+		return k_stop_on_error;;
+	}
+
+	spin(1);
+	i = 100;
+	while (i && set_lock(&errlock, 1) != 1) {
+		spin(1);
+		i--;
+	}
+	printk ("\nDataError!: %-20s, test %ld, thread %d, line:%d, pass %d (0x%x), time %ld expected:%x, found:%x\n",
+	    msg, k_testnumber, thread, badlinei, pass, pass, jiffies, exp, found);
+
+	dumpline (lp, "Corrupted data", "D ", cap->blockaddr, cap->blockdata, cap->size);
+#ifdef ZZZ
+	if (memcmp(cap->blockdata, cap->blockdata_fc, 128))
+		dumpline (lp, "Corrupted data", "DF", cap->blockaddr, cap->blockdata_fc, cap->size);
+#endif
+
+	if (cap->shadaddr) {
+		dumpline (slp, "Shadow    data", "S ", cap->shadaddr, cap->shaddata, cap->size);
+#ifdef ZZZ
+		if (memcmp(cap->shaddata, cap->shaddata_fc, 128))
+			dumpline (slp, "Shadow    data", "SF", cap->shadaddr, cap->shaddata_fc, cap->size);
+#endif
+	}
+	
+	printk("Threadpasses: ");
+	for (cpu=0,i=0; cpu<LLSC_MAXCPUS; cpu++)
+		if (k_threadprivate[cpu]->threadpasses) {
+			if (i && (i%8) == 0)
+				printk("\n            : ");
+			printk("  %d:0x%x", cpu, k_threadprivate[cpu]->threadpasses);
+			i++;
+		}
+	printk("\n");
+	
+	for (linei=0; linei<k_linecount; linei++) {
+		int		slinei, g1linei, g2linei, g1err, g2err, sh0err, sh1err;
+		dataline_t	*linep, *slinep;
+
+		slinei = (linei + (k_linecount/2))%k_linecount;
+		linep = (dataline_t *)blocks[linei];
+		slinep = (dataline_t *)blocks[slinei];
+
+		g1linei = GUARDLINE(linep->guard1);
+		g2linei = GUARDLINE(linep->guard2);
+		g1err = (g1linei != linei);
+		g2err = (g2linei != linei);
+		sh0err = (linep->share[0] != slinep->share0);
+		sh1err = (linep->share[1] != slinep->share1);
+
+		if (g1err || g2err || sh0err || sh1err) {
+			printk("Line 0x%lx (%03d), %sG1 0x%lx (%03d), %sG2 0x%lx (%03d), %sSH0 %08x (%08x), %sSH1 %08x (%08x)\n",
+				blocks[linei], linei, 
+				g1err ? "*" : " ", blocks[g1linei], g1linei,
+				g2err ? "*" : " ", blocks[g2linei], g2linei,
+				sh0err ? "*" : " ", linep->share[0], slinep->share0,
+				sh1err ? "*" : " ", linep->share[1], slinep->share1);
+
+
+		}
+	}
+
+	printk("\nData was %sfixed by flushcache\n", (stillbad == 1 ? "**** NOT **** " : " "));
+	synerr = getsynerr();
+	if (synerr)
+		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
+	spin(2);
+	printk("\n\n");
+	clr_lock(&errlock, 1);
+
+	if (errstop_enabled) {
+		local_irq_disable();
+		while(1);
+	}
+	return k_stop_on_error;
+}
+
+
+static void
+dumpline(void *lp, char *str1, char *str2, void *addr, void *data, int size)
+{
+	long *p;
+	int i, off;
+
+	printk("%s at 0x%lx, size %d, block starts at 0x%lx\n", str1, (long)addr, size, (long)lp);
+	p = (long*) data;
+	for (i=0; i<48; i++, p++) {
+		if (i%8 == 0) printk("%2s", i==16 ? str2 : "  ");
+		printk(" %016lx", *p);
+		if ((i&7)==7) printk("\n");
+	}
+	printk("   ");
+	off = (((long)addr) ^ size) & 63L;
+	for (i=0; i<off+size; i++) {
+		printk("%s", (i>=off) ? "--" : "  ");
+		if ((i%8) == 7)
+			printk(" ");
+	}
+
+	off = ((long)addr) & 127;
+	printk(" (line %d)\n", 2+off/64+1);
+}
+
+
+static int
+randn(uint max, uint *seedp)
+{
+	if (max == 1)
+		return(0);
+	else
+		return((int)(zrandom(seedp)>>10) % max);
+}
+
+
+static int
+checkstop(int thread, int pass, uint lockpat)
+{
+	long	synerr;
+
+	if (k_go == ST_RUN)
+		return 0;
+	if (k_go == ST_STOP)
+		return 1;
+
+	if (errstop_enabled) {
+		local_irq_disable();
+		while(1);
+	}
+	synerr = getsynerr();
+	spin(2);
+	if (k_go == ST_STOP)
+		return 1;
+	if (synerr)
+		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
+	return 1;
+}
+
+
+static void
+spin(int j)
+{
+	udelay(j * 500000);
+}
+
+static void
+capturedata(capture_t *cap, uint pass, void *blockaddr, void *shadaddr, int size)
+{
+
+	if (!selective_trigger)
+		trigger_la (pass);
+
+	memcpy (cap->blockdata, CACHEALIGN(blockaddr)-128, 3*128);
+	if (shadaddr) 
+		memcpy (cap->shaddata, CACHEALIGN(shadaddr)-128, 3*128);
+
+	if (k_stop_on_error) {
+		k_go = ST_ERRSTOP;
+	}
+
+ 	cap->size = size;
+	cap->blockaddr = blockaddr;
+	cap->shadaddr = shadaddr;
+
+	asm volatile ("fc %0" :: "r"(blockaddr) : "memory");
+	ia64_sync_i();
+	ia64_srlz_d();
+	memcpy (cap->blockdata_fc, CACHEALIGN(blockaddr)-128, 3*128);
+
+	if (shadaddr) {
+		asm volatile ("fc %0" :: "r"(shadaddr) : "memory");
+		ia64_sync_i();
+		ia64_srlz_d();
+		memcpy (cap->shaddata_fc, CACHEALIGN(shadaddr)-128, 3*128);
+	}
+}
+
+int             zranmult = 0x48c27395;
+
+static uint  
+zrandom (uint *seedp)
+{
+        *seedp = (*seedp * zranmult) & 0x7fffffff;
+        return (*seedp);
+}
+
+
+void
+set_autotest_params(void)
+{
+	static int	testnumber=-1;
+
+	if (llsctest_number >= 0) {
+		testnumber = llsctest_number;
+	} else {
+		testnumber++;
+		if (autotest_table[testnumber].passes == 0) {
+			testnumber = 0;
+			dump_block_addrs_opt = 0;
+		}
+	}
+	if (testnumber == 0 && l4_opt) testnumber = 9;
+
+	k_passes = autotest_table[testnumber].passes;
+	k_linepad = autotest_table[testnumber].linepad;
+	k_linecount = autotest_table[testnumber].linecount;
+	k_testnumber = testnumber;
+
+	if (IS_RUNNING_ON_SIMULATOR()) {
+		printk ("llsc start test %ld\n", k_testnumber);
+		k_passes = 1000;
+	}
+}
+
+
+static void
+set_leds(int errs)
+{
+	unsigned char	leds=0;
+
+	/*
+	 * Leds are:
+	 * 	ppppeee-  
+	 *   where
+	 *      pppp = test number
+	 *       eee = error count but top bit is stick
+	 */
+
+	leds =  ((errs&7)<<1) | ((k_testnumber&15)<<4) | (errs ? 0x08 : 0);
+	set_led_bits(leds, LED_MASK_AUTOTEST);
+}
+
+static void
+setup_block_addresses(void)
+{
+	int			i, stride, memmapi;
+	dataline_t		*dp;
+	long			*ip, *ipe;
+
+
+	stride = k_linepad + sizeof(dataline_t);
+	memmapi = 0;
+	for (i=0; i<memmapx; i++) {
+		memmap[i].nextaddr = memmap[i].vstart;
+		memmap[i].nextinit = memmap[i].vstart;
+		memmap[i].wrapcount = 0;
+	}
+
+	for (i=0; i<k_linecount; i++) {
+		blocks[i] = memmap[memmapi].nextaddr;
+		dp = (dataline_t*)blocks[i];
+		memmap[memmapi].nextaddr += (stride & 0xffff);
+		if (memmap[memmapi].nextaddr + sizeof(dataline_t) >= memmap[memmapi].vend) {
+			memmap[memmapi].wrapcount++;
+			memmap[memmapi].nextaddr = memmap[memmapi].vstart + 
+					memmap[memmapi].wrapcount * sizeof(dataline_t);
+		}
+
+		ip = (long*)((memmap[memmapi].nextinit+7)&~7);
+		ipe = (long*)(memmap[memmapi].nextaddr+2*sizeof(dataline_t)+8);
+		while(ip <= ipe && ip < ((long*)memmap[memmapi].vend-8))
+			*ip++ = (long)ip;
+		memmap[memmapi].nextinit = (long) ipe;
+		dp->guard1 = BGUARD(i);
+		dp->guard2 = EGUARD(i);
+		dp->lock[0] = dp->lock[1] = NOLOCK;
+		dp->share[0] = dp->share0 = 0x1111;
+		dp->share[1] = dp->share1 = 0x2222;
+		memcpy(dp->private, init_private, LLSC_MAXCPUS*sizeof(private_t));
+
+
+		if (stride > 16384) {
+			memmapi++;
+			if (memmapi == memmapx)
+				memmapi = 0;
+		}
+	}
+
+}
+
+static void
+dump_block_addrs(void)
+{
+	int	i;
+
+	printk("LLSC TestNumber %ld\n", k_testnumber);
+
+	for (i=0; i<k_linecount; i++) {
+		printk("  %lx", blocks[i]);
+		if (i%4 == 3)
+			printk("\n");
+	}
+	printk("\n");
+}
+
+
+static void
+set_thread_state(int cpuid, int state)
+{
+	if (k_threadprivate[cpuid]->threadstate == TS_KILLED) {
+		set_led_bits(LED_MASK_AUTOTEST, LED_MASK_AUTOTEST);
+		while(1);
+	}
+	k_threadprivate[cpuid]->threadstate = state;
+}
+
+#define MINBLK	(16*1024*1024)
+static int
+build_mem_map(unsigned long start, unsigned long end, void *arg)
+{
+	long	lstart, lend;
+	long	align = 8*MB;
+
+	printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", 
+		start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE));
+
+	if (memmapx >= MAPCHUNKS || (end-start) < MINBLK)
+		return 0;
+
+	/*
+	 * Start in the middle of the range & find the first non-free page in both directions
+	 * from the midpoint. This is likely to be the bigest free block.
+	 */
+	lend = lstart = start + (end-start)/2;
+	while (lend < end && !PageReserved(virt_to_page(lend)) && virt_to_page(lend)->count.counter == 0)
+		lend += PAGE_SIZE;
+	lend -= PAGE_SIZE;
+
+	while (lstart >= start && !PageReserved(virt_to_page(lstart)) && virt_to_page(lstart)->count.counter == 0)
+		lstart -= PAGE_SIZE;
+	lstart += PAGE_SIZE;
+
+	lstart = (lstart + align -1) /align * align;
+	end = end / align * align;
+	if (lstart >= end)
+		return 0;
+	printk ("     memmap: start 0x%lx, end 0x%lx\n", lstart, end);
+
+	memmap[memmapx].vstart = lstart;
+	memmap[memmapx].vend = end;
+	memmapx++;
+	return 0;
+}
+
+void int_test(void);
+
+int
+llsc_main (int cpuid)
+{
+	int		i, cpu, is_master, repeatcnt=0;
+	unsigned int	preverr=0, errs=0, pass=0;
+	int		automode=0;
+
+#ifdef INTTEST
+	if (inttest)
+		int_test();
+#endif
+
+	if (!autotest_enabled)
+		return 0;
+
+#ifdef CONFIG_SMP
+	is_master = !smp_processor_id();
+#else
+	is_master = 1;
+#endif
+
+
+	if (is_master) {
+		mbase = (control_t*) __get_free_pages(GFP_KERNEL, get_order(4096+THREADPRIVATESZ()*LLSC_MAXCPUS));
+		printk("LLSC: mbase 0x%lx\n", (long)mbase);
+		print_params();
+		if(!IS_RUNNING_ON_SIMULATOR())
+			spin(10);
+		k_currentpass = 0;
+		k_go = ST_IDLE;
+		k_passes = DEF_PASSES;
+		k_napticks = DEF_NAPTICKS;
+		k_stop_on_error = DEF_STOP_ON_ERROR;
+		k_verbose = DEF_VERBOSE;
+		k_linecount = DEF_LINECOUNT;
+		k_iter_msg = DEF_ITER_MSG;
+		k_vv = DEF_VV;
+		k_linepad = DEF_LINEPAD;
+		k_blocks = (void*)blocks;
+		efi_memmap_walk(build_mem_map, 0);
+	
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+		automode = 1;
+#endif
+
+		for (i=0; i<LLSC_MAXCPUS; i++) {
+			k_threadprivate[i] = THREADPRIVATE(i);
+			memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i]));
+			init_private[i] = i;
+		}
+		mb();
+		initialized = 1;
+	} else {
+		while (initialized == 0)
+			udelay(100);
+	}
+
+loop:
+	if (is_master) {
+		if (automode) {
+			if (!preverr || repeatcnt++ > 5) {
+				set_autotest_params();
+				repeatcnt = 0;
+			}
+		} else {
+			while (k_go == ST_IDLE);
+		}
+
+		k_go = ST_INIT;
+		if (k_linecount > MAX_LINECOUNT) k_linecount = MAX_LINECOUNT;
+		k_linecount = k_linecount & ~1;
+		setup_block_addresses();
+		if (!preverr && dump_block_addrs_opt)
+			dump_block_addrs();
+
+		k_currentpass = pass++;
+		k_go = ST_RUN;
+		if (fail_enabled)
+			fail_enabled--;
+
+	} else {
+		while (k_go != ST_RUN || k_currentpass != pass);
+		pass++;
+	}
+
+
+	set_leds(errs);
+	set_thread_state(cpuid, TS_RUNNING);
+
+	errs += ran_conf_llsc(cpuid);
+	preverr = (k_go == ST_ERRSTOP);
+
+	set_leds(errs);
+	set_thread_state(cpuid, TS_STOPPED);
+
+	if (is_master) {
+		Speedo();
+		for (i=0, cpu=0; cpu<LLSC_MAXCPUS; cpu++) {
+			while (k_threadprivate[cpu]->threadstate == TS_RUNNING) {
+				i++;
+				if (i == 10000) { 
+					k_go = ST_STOP;
+					printk ("  llsc master stopping test number %ld\n", k_testnumber);
+				}
+				if (i > 100000) {
+					k_threadprivate[cpu]->threadstate = TS_KILLED;
+					printk ("  llsc: master killing cpuid %d, running test number %ld\n", 
+							cpu, k_testnumber);
+				}
+				udelay(1000);
+			}
+		}
+	}
+
+	goto loop;
+}
+
+
+static void
+Speedo(void)
+{
+	static int i = 0;
+
+	switch (++i%4) {
+	case 0:
+		printk("|\b");
+		break;
+	case 1:
+		printk("\\\b");
+		break;
+	case 2:
+		printk("-\b");
+		break;
+	case 3:
+		printk("/\b");
+		break;
+	}
+}
+
+#ifdef INTTEST
+
+/* ======================================================================================================== 
+ *
+ * Some test code to verify that interrupts work
+ *
+ * Add the following to the arch/ia64/kernel/smp.c after the comment "Reschedule callback"
+ * 		if (zzzprint_resched) printk("  cpu %d got interrupt\n", smp_processor_id());
+ *
+ * Enable the code in arch/ia64/sn/sn1/smp.c to print sending IPIs.
+ *
+ */
+
+static int __init set_inttest(char *str)
+{
+        inttest = 1;
+	autotest_enabled = 1;
+
+	return 1;
+}	
+
+__setup("inttest=", set_inttest);
+
+int	zzzprint_resched=0;
+
+void
+int_test() {
+	int			mycpu, cpu;
+	static volatile int	control_cpu=0;
+
+	mycpu = smp_processor_id();
+	zzzprint_resched = 2;
+
+	printk("Testing cross interrupts\n");
+	
+	while (control_cpu != smp_num_cpus) {
+		if (mycpu == cpu_logical_map(control_cpu)) {
+			for (cpu=0; cpu<smp_num_cpus; cpu++) {
+				printk("Sending interrupt from %d to %d\n", mycpu, cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+				smp_send_reschedule(cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+				smp_send_reschedule(cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+			}
+			control_cpu++;
+		}
+	}
+
+	zzzprint_resched = 1;
+
+	if (mycpu == cpu_logical_map(smp_num_cpus-1)) {
+		printk("\nTight loop of cpu %d sending ints to cpu 0 (every 100 us)\n", mycpu);
+		udelay(IS_RUNNING_ON_SIMULATOR ? 1000 : 1000000);
+		__cli();
+		while (1) {
+			smp_send_reschedule(0);
+			udelay(100);
+		}
+
+	}
+
+	while(1);
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/llsc4.h linux/arch/ia64/sn/kernel/llsc4.h
--- linux.orig/arch/ia64/sn/kernel/llsc4.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/llsc4.h	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,107 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifdef STANDALONE
+#include "lock.h"
+#endif
+
+
+#define DEF_NAPTICKS		0
+#define DEF_PASSES		0
+#define DEF_AUTO_PASSES		1000000
+#define DEF_STOP_ON_ERROR	1
+#define DEF_VERBOSE		0
+#define DEF_LINECOUNT		2
+#define DEF_ITER_MSG		0
+#define DEF_VV			0xffffffff
+#define DEF_LINEPAD		0x234
+
+
+
+#define LLSC_MAXCPUS		64
+#define CACHELINE		64
+#define MAX_LINECOUNT		1024
+#define K			1024
+#define	MB			(K*K)
+
+
+#define	uint 		unsigned int
+#define	ushort		unsigned short
+#define	uchar		unsigned char
+#define vint		volatile int
+#define vlong		volatile long
+
+#define LOCKADDR(i)	&linep->lock[(i)]
+#define LOCK(i)		set_lock(LOCKADDR(i), lockpat)
+#define UNLOCK(i)	clr_lock(LOCKADDR(i), lockpat)
+#define GETLOCK(i)	*LOCKADDR(i)
+#define ZEROLOCK(i)	init_lock(LOCKADDR(i))
+
+#define CACHEALIGN(a)	((char*)((long)(a) & ~127L))
+
+typedef uint		guard_t;
+typedef uint		lock_t;
+typedef uint		share_t;
+typedef uchar		private_t;
+
+typedef struct {
+	guard_t		guard1;
+	lock_t		lock[2];
+	share_t		share[2];
+	private_t	private[LLSC_MAXCPUS];
+	share_t		share0;
+	share_t		share1;
+	guard_t		guard2;
+} dataline_t ;
+
+
+#define LINEPAD			k_linepad
+#define LINESTRIDE		(((sizeof(dataline_t)+CACHELINE-1)/CACHELINE)*CACHELINE + LINEPAD)
+
+
+typedef struct {
+	vint		threadstate;
+	uint		threadpasses;
+	private_t	private[MAX_LINECOUNT];
+} threadprivate_t;
+
+typedef struct {
+	vlong		sk_go;		/* 0=idle, 1=init, 2=run */
+	long		sk_linecount;
+	long		sk_passes;
+	long		sk_napticks;
+	long		sk_stop_on_error;
+	long		sk_verbose;
+	long		sk_iter_msg;
+	long		sk_vv;
+	long		sk_linepad;
+	long		sk_options;
+	long		sk_testnumber;
+	vlong		sk_currentpass;
+	void 		*sk_blocks;
+	threadprivate_t	*sk_threadprivate[LLSC_MAXCPUS];
+} control_t;
+
+/* Run state (k_go) constants */
+#define ST_IDLE		0
+#define ST_INIT		1
+#define ST_RUN		2
+#define ST_STOP		3
+#define ST_ERRSTOP	4
+
+
+/* Threadstate constants */
+#define TS_STOPPED	0
+#define	TS_RUNNING	1
+#define TS_KILLED	2
+
+
+
+int llsc_main (int cpuid);
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/machvec.c linux/arch/ia64/sn/kernel/machvec.c
--- linux.orig/arch/ia64/sn/kernel/machvec.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/machvec.c	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define MACHVEC_PLATFORM_NAME	sn1
+#else CONFIG_IA64_SGI_SN1
+#define MACHVEC_PLATFORM_NAME	sn2
+#else
+#error "unknown platform"
+#endif
+
+#include <asm/machvec_init.h>
+#include <asm/io.h>
+#include <linux/pci.h>
+void*
+sn_mk_io_addr_MACRO
+
+dma_addr_t
+sn_pci_map_single_MACRO
+
+int
+sn_pci_map_sg_MACRO
+
+unsigned long
+sn_virt_to_phys_MACRO
+
+void *
+sn_phys_to_virt_MACRO
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/mca.c linux/arch/ia64/sn/kernel/mca.c
--- linux.orig/arch/ia64/sn/kernel/mca.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/mca.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,280 @@
+/*
+ * File:	mca.c
+ * Purpose:	SN specific MCA code.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/smp_lock.h>
+#include <linux/kdb.h>
+
+#include <asm/machvec.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/mca.h>
+#include <asm/sn/mca.h>
+
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/acpi-ext.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+
+static char *shub_mmr_names[] = {
+	"sh_event_occurred",
+	"sh_first_error",
+	"sh_event_overflow",
+
+/* PI */
+	"sh_pi_first_error",
+	"sh_pi_error_summary",
+	"sh_pi_error_overflow",
+
+/* PI HW */
+	"sh_pi_error_detail_1",
+	"sh_pi_error_detail_2",
+	"sh_pi_hw_time_stamp",
+
+/* PI UCE */
+	"sh_pi_uncorrected_detail_1",
+	"sh_pi_uncorrected_detail_2",
+	"sh_pi_uncorrected_detail_3",
+	"sh_pi_uncorrected_detail_4",
+	"sh_pi_uncor_time_stamp",
+
+/* PI CE */
+	"sh_pi_corrected_detail_1",
+	"sh_pi_corrected_detail_2",
+	"sh_pi_corrected_detail_3",
+	"sh_pi_corrected_detail_4",
+	"sh_pi_cor_time_stamp",
+
+/* MD */
+	"sh_mem_error_summary",
+	"sh_mem_error_overflow",
+/* MD HW */
+	"sh_misc_err_hdr_upper",
+	"sh_misc_err_hdr_lower",
+	"sh_md_dqlp_mmr_xperr_val",
+	"sh_md_dqlp_mmr_yperr_val",
+	"sh_md_dqrp_mmr_xperr_val",
+	"sh_md_dqrp_mmr_yperr_val",
+	"sh_md_hw_time_stamp",
+
+/* MD UCE */
+	"sh_dir_uc_err_hdr_lower",
+	"sh_dir_uc_err_hdr_upper",
+	"sh_md_dqlp_mmr_xuerr1",
+	"sh_md_dqlp_mmr_xuerr2",
+	"sh_md_dqlp_mmr_yuerr1",
+	"sh_md_dqlp_mmr_yuerr2",
+	"sh_md_dqrp_mmr_xuerr1",
+	"sh_md_dqrp_mmr_xuerr2",
+	"sh_md_dqrp_mmr_yuerr1",
+	"sh_md_dqrp_mmr_yuerr2",
+	"sh_md_uncor_time_stamp",
+
+/* MD CE */
+	"sh_dir_cor_err_hdr_lower",
+	"sh_dir_cor_err_hdr_upper",
+	"sh_md_dqlp_mmr_xcerr1",
+	"sh_md_dqlp_mmr_xcerr2",
+	"sh_md_dqlp_mmr_ycerr1",
+	"sh_md_dqlp_mmr_ycerr2",
+	"sh_md_dqrp_mmr_xcerr1",
+	"sh_md_dqrp_mmr_xcerr2",
+	"sh_md_dqrp_mmr_ycerr1",
+	"sh_md_dqrp_mmr_ycerr2",
+	"sh_md_cor_time_stamp",
+
+/* MD CE, UCE */
+	"sh_md_dqls_mmr_xamopw_err",
+	"sh_md_dqrs_mmr_yamopw_err",
+
+/* XN */
+	"sh_xn_error_summary",
+	"sh_xn_first_error",
+	"sh_xn_error_overflow",
+
+/* XN HW */
+	"sh_xniilb_error_summary",
+	"sh_xniilb_first_error",
+	"sh_xniilb_error_overflow",
+	"sh_xniilb_error_detail_1",
+	"sh_xniilb_error_detail_2",
+	"sh_xniilb_error_detail_3",
+
+	"sh_ni0_error_summary_1",
+	"sh_ni0_first_error_1",
+	"sh_ni0_error_overflow_1",
+
+	"sh_ni0_error_summary_2",
+	"sh_ni0_first_error_2",
+	"sh_ni0_error_overflow_2",
+	"sh_ni0_error_detail_1",
+	"sh_ni0_error_detail_2",
+	"sh_ni0_error_detail_3",
+
+	"sh_ni1_error_summary_1",
+	"sh_ni1_first_error_1",
+	"sh_ni1_error_overflow_1",
+
+	"sh_ni1_error_summary_2",
+	"sh_ni1_first_error_2",
+	"sh_ni1_error_overflow_2",
+
+	"sh_ni1_error_detail_1",
+	"sh_ni1_error_detail_2",
+	"sh_ni1_error_detail_3",
+
+	"sh_xn_hw_time_stamp",
+
+/* XN HW & UCE & SBE */
+	"sh_xnpi_error_summary",
+	"sh_xnpi_first_error",
+	"sh_xnpi_error_overflow",
+	"sh_xnpi_error_detail_1",
+
+	"sh_xnmd_error_summary",
+	"sh_xnmd_first_error",
+	"sh_xnmd_error_overflow",
+	"sh_xnmd_ecc_err_report",
+	"sh_xnmd_error_detail_1",
+
+/* XN UCE */
+	"sh_xn_uncorrected_detail_1",
+	"sh_xn_uncorrected_detail_2",
+	"sh_xn_uncorrected_detail_3",
+	"sh_xn_uncorrected_detail_4",
+	"sh_xn_uncor_time_stamp",
+
+/* XN CE */
+	"sh_xn_corrected_detail_1",
+	"sh_xn_corrected_detail_2",
+	"sh_xn_corrected_detail_3",
+	"sh_xn_corrected_detail_4",
+	"sh_xn_cor_time_stamp",
+
+/* LB HW */
+	"sh_lb_error_summary",
+	"sh_lb_first_error",
+	"sh_lb_error_overflow",
+	"sh_lb_error_detail_1",
+	"sh_lb_error_detail_2",
+	"sh_lb_error_detail_3",
+	"sh_lb_error_detail_4",
+	"sh_lb_error_detail_5",
+	"sh_junk_error_status",
+};
+
+void 
+sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc) 
+{
+	sal_log_plat_info_t *sh_info = (sal_log_plat_info_t *) p_data;
+	u64 *mmr_val = (u64 *)&(sh_info->shub_state);
+	char **mmr_name = shub_mmr_names;
+	int mmr_count = sizeof(sal_log_shub_state_t)>>3;
+
+	while(mmr_count) {
+		if(*mmr_val) {
+			prfunc("%-40s: %#016lx\n",*mmr_name, *mmr_val);
+		}
+		mmr_name++;
+		mmr_val++;
+		mmr_count--;
+	}
+
+}
+
+sn_cpei_handler(int irq, void *devid, struct pt_regs *regs)
+{
+	struct ia64_sal_retval isrv;
+
+	/*
+	 * this function's sole purpose is to call SAL when we receive
+	 * a CE interrupt from SHUB or when the timer routine decides
+	 * we need to call SAL to check for CEs.
+	 */
+
+	/* CALL SAL_LOG_CE */
+	SAL_CALL(isrv, SN_SAL_LOG_CE, irq, 0, 0, 0, 0, 0, 0);
+}
+
+#include <linux/timer.h>
+
+#define CPEI_INTERVAL   (HZ/100)
+struct timer_list sn_cpei_timer;
+void sn_init_cpei_timer(void);
+
+void
+sn_cpei_timer_handler(unsigned long dummy) {
+        sn_cpei_handler(-1, NULL, NULL);
+        del_timer(&sn_cpei_timer);
+        sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
+        add_timer(&sn_cpei_timer);
+}
+
+void
+sn_init_cpei_timer() {
+        sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
+        sn_cpei_timer.function = sn_cpei_timer_handler;
+        add_timer(&sn_cpei_timer);
+}
+
+#ifdef ajmtestceintr
+
+struct timer_list sn_ce_timer;
+
+void
+sn_ce_timer_handler(long dummy) {
+        unsigned long *pi_ce_error_inject_reg = 0xc00000092fffff00;
+
+        *pi_ce_error_inject_reg = 0x0000000000000100;
+        del_timer(&sn_ce_timer);
+        sn_ce_timer.expires = jiffies + CPEI_INTERVAL;
+        add_timer(&sn_ce_timer);
+}
+
+sn_init_ce_timer() {
+        sn_ce_timer.expires = jiffies + CPEI_INTERVAL;
+        sn_ce_timer.function = sn_ce_timer_handler;
+        add_timer(&sn_ce_timer);
+}
+#endif /* ajmtestceintr */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/misctest.c linux/arch/ia64/sn/kernel/misctest.c
--- linux.orig/arch/ia64/sn/kernel/misctest.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/misctest.c	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,122 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/processor.h>
+#include <asm/pgtable.h>
+
+
+extern	int autotest_enabled;
+int	mcatest=0;
+
+
+
+/* 
+ * mcatest
+ *	1 = expected MCA
+ *	2 = unexpected MCA
+ *	3 = expected MCA + unexpected MCA
+ *	4 = INIT
+ *	5 = speculative load to garbage memory address
+ *	6 = speculative load with ld8.s (needs poison hack in PROM)
+ *	7 = speculative load from mis-predicted branch (needs poison hack in PROM)
+ */
+static int __init set_mcatest(char *str)
+{
+	get_option(&str, &mcatest);
+	return 1;
+}
+
+__setup("mcatest=", set_mcatest);
+
+void
+sgi_mcatest(void)
+{
+	if (mcatest == 1 || mcatest == 3) {
+		long	*p, result, adrs[] = {0xc0000a000f021004UL, 0xc0000a000f026004UL, 0x800000000, 0x500000, 0};
+		long	size[] = {1,2,4,8};
+		int	r, i, j;
+		p = (long*)0xc000000000000000UL;
+		ia64_fc(p);
+		*p = 0x0123456789abcdefL;
+		for (i=0; i<5; i++) {
+			for (j=0; j<4; j++) {
+				printk("Probing 0x%lx, size %ld\n", adrs[i], size[j]);
+				result = -1;
+				r = ia64_sn_probe_io_slot (adrs[i], size[j], &result);
+				printk("    status %d, val 0x%lx\n", r, result); 
+			}
+		}
+	}
+	if (mcatest == 2 || mcatest == 3) {
+		void zzzmca(int, int, int);
+		printk("About to cause unexpected MCA\n");
+		zzzmca(mcatest, 0x32dead, 0x33dead);
+	}
+	if (mcatest == 4) {
+		long	*p;
+		int	delivery_mode = 5;
+		printk("About to try to cause an INIT on cpu 0\n");
+		p = (long*)((0xc0000a0000000000LL | ((long)get_nasid())<<33) | 0x1800080);
+		*p = (delivery_mode << 8);
+		udelay(10000);
+		printk("Returned from INIT\n");
+	}
+	if (mcatest == 5) {
+		int zzzspec(long);
+		int	i;
+		long	flags, dcr, res, val, addr=0xff00000000UL;
+
+		dcr = ia64_get_dcr();
+		for (i=0; i<5; i++) {
+			printk("Default DCR: 0x%lx\n", ia64_get_dcr());
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(0);
+			printk("New     DCR: 0x%lx\n", ia64_get_dcr());
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(dcr);
+			res = ia64_sn_probe_io_slot(0xff00000000UL, 8, &val);
+			printk("zzzspec: probe %ld, 0x%lx\n", res, val);
+			ia64_clear_ic(flags);
+			ia64_itc(0x2, 0xe00000ff00000000UL,
+			          pte_val(mk_pte_phys(0xff00000000UL,
+				  __pgprot(__DIRTY_BITS|_PAGE_PL_0|_PAGE_AR_RW))), _PAGE_SIZE_256M);
+			local_irq_restore(flags);
+			ia64_srlz_i ();
+		}
+
+	}
+	if (mcatest == 6) {
+		int zzzspec(long);
+		int	i;
+		long	dcr, addr=0xe000000008000000UL;
+
+		dcr = ia64_get_dcr();
+		for (i=0; i<5; i++) {
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(0);
+		}
+		ia64_set_dcr(dcr);
+	}
+	if (mcatest == 7) {
+		int zzzspec2(long, long);
+		int	i;
+		long	addr=0xe000000008000000UL;
+		long	addr2=0xe000000007000000UL;
+
+		for (i=0; i<5; i++) {
+			printk("zzzspec2\n");
+			zzzspec2(addr, addr2);
+		}
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/probe.c linux/arch/ia64/sn/kernel/probe.c
--- linux.orig/arch/ia64/sn/kernel/probe.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/probe.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,81 @@
+/*
+ * Platform dependent support for IO probing.
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <asm/sn/sn_sal.h>
+
+/**
+ * ia64_sn_probe_io_slot - test a memory location for readability
+ * @paddr: physical address to probe
+ * @size: number bytes to read (1,2,4,8)
+ * @data_ptr: address to store value read by probe (-1 returned if probe fails)
+ *
+ * This function will probe a physical address to determine if
+ * the address can be read. If reading the address causes a BUS
+ * error, an error is returned. If the probe succeeds, the contents 
+ * of the memory location is returned.
+ *
+ * Return values:
+ *  0 - probe successful
+ *  1 - probe failed (generated MCA)
+ *  2 - Bad arg
+ * <0 - PAL error
+ */
+u64
+ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr)
+{
+	struct ia64_sal_retval isrv;
+
+	SAL_CALL(isrv, SN_SAL_PROBE, paddr, size, 0, 0, 0, 0, 0);
+
+	if (data_ptr) {
+		switch (size) {
+			case 1:
+				*((u8*)data_ptr) = (u8)isrv.v0;
+				break;
+			case 2:
+				*((u16*)data_ptr) = (u16)isrv.v0;
+				break;
+			case 4:
+				*((u32*)data_ptr) = (u32)isrv.v0;
+				break;
+			case 8:
+				*((u64*)data_ptr) = (u64)isrv.v0;
+				break;
+			default:
+				isrv.status = 2;	
+		}
+	}
+
+	return isrv.status;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/setup.c linux/arch/ia64/sn/kernel/setup.c
--- linux.orig/arch/ia64/sn/kernel/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/setup.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,415 @@
+/*
+ * Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/kdev_t.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/console.h>
+#include <linux/timex.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/serial.h>
+#include <linux/irq.h>
+#include <linux/bootmem.h>
+#include <linux/mmzone.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/sal.h>
+#include <asm/machvec.h>
+#include <asm/system.h>
+#ifdef CONFIG_IA64_MCA
+#include <asm/acpi-ext.h>
+#endif
+#include <asm/processor.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/leds.h>
+#include <asm/sn/bte.h>
+#include <asm/sn/clksupport.h>
+
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/shub.h>
+#endif
+
+extern void bte_init_node (nodepda_t *, cnodeid_t, char **);
+extern void bte_init_cpu (void);
+
+long sn_rtc_cycles_per_second;   
+
+/*
+ * This is the address of the RRegs in the HSpace of the global
+ * master.  It is used by a hack in serial.c (serial_[in|out],
+ * printk.c (early_printk), and kdb_io.c to put console output on that
+ * node's Bedrock UART.  It is initialized here to 0, so that
+ * early_printk won't try to access the UART before
+ * master_node_bedrock_address is properly calculated.
+ */
+u64 master_node_bedrock_address = 0UL;
+
+static void sn_init_pdas(char **);
+
+extern struct irq_desc *_sn_irq_desc[];
+
+#if defined(CONFIG_IA64_SGI_SN1)
+extern synergy_da_t	*Synergy_da_indr[];
+#endif
+
+static nodepda_t	*nodepdaindr[MAX_COMPACT_NODES];
+
+#ifdef CONFIG_IA64_SGI_SN2
+irqpda_t		*irqpdaindr[NR_CPUS];
+#endif /* CONFIG_IA64_SGI_SN2 */
+
+
+/*
+ * The format of "screen_info" is strange, and due to early i386-setup
+ * code. This is just enough to make the console code think we're on a
+ * VGA color display.
+ */
+struct screen_info sn_screen_info = {
+	orig_x:			 0,
+	orig_y:			 0,
+	orig_video_mode:	 3,
+	orig_video_cols:	80,
+	orig_video_ega_bx:	 3,
+	orig_video_lines:	25,
+	orig_video_isVGA:	 1,
+	orig_video_points:	16
+};
+
+/*
+ * This is here so we can use the CMOS detection in ide-probe.c to
+ * determine what drives are present.  In theory, we don't need this
+ * as the auto-detection could be done via ide-probe.c:do_probe() but
+ * in practice that would be much slower, which is painful when
+ * running in the simulator.  Note that passing zeroes in DRIVE_INFO
+ * is sufficient (the IDE driver will autodetect the drive geometry).
+ */
+char drive_info[4*16];
+
+/**
+ * sn_map_nr - return the mem_map entry for a given kernel address
+ * @addr: kernel address to query
+ *
+ * Finds the mem_map entry for the kernel address given.  Used by
+ * virt_to_page() (asm-ia64/page.h), among other things.
+ */
+unsigned long
+sn_map_nr (unsigned long addr)
+{
+	return MAP_NR_DISCONTIG(addr);
+}
+
+/**
+ * early_sn_setup - early setup routine for SN platforms
+ *
+ * Sets up an intial console to aid debugging.  Intended primarily
+ * for bringup, it's only called if %BRINGUP and %CONFIG_IA64_EARLY_PRINTK
+ * are turned on.  See start_kernel() in init/main.c.
+ */
+#if defined(CONFIG_IA64_EARLY_PRINTK) && defined(CONFIG_IA64_SGI_SN)
+void __init
+early_sn_setup(void)
+{
+	if ( IS_RUNNING_ON_SIMULATOR() ) {
+#if defined(CONFIG_IA64_SGI_SN1)
+		master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
+#else
+		master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0);
+#endif
+		printk(KERN_DEBUG "early_sn_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address);
+	}
+}
+#endif /* CONFIG_IA64_EARLY_PRINTK && CONFIG_IA64_SGI_SN */
+
+#ifdef NOT_YET_CONFIG_IA64_MCA
+extern void ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs);
+static struct irqaction mca_cpe_irqaction = { 
+	handler:    ia64_mca_cpe_int_handler,
+	flags:      SA_INTERRUPT,
+	name:       "cpe_hndlr"
+};
+#endif
+#ifdef CONFIG_IA64_MCA
+extern int platform_irq_list[];
+#endif
+
+extern nasid_t master_nasid;
+
+/**
+ * sn_setup - SN platform setup routine
+ * @cmdline_p: kernel command line
+ *
+ * Handles platform setup for SN machines.  This includes determining
+ * the RTC frequency (via a SAL call), initializing secondary CPUs, and
+ * setting up per-node data areas.  The console is also initialized here.
+ */
+void __init
+sn_setup(char **cmdline_p)
+{
+	long status, ticks_per_sec, drift;
+	int i;
+
+	master_nasid = get_nasid();
+	(void)get_console_nasid();
+
+	status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift);
+	if (status != 0 || ticks_per_sec < 100000)
+		printk(KERN_WARNING "unable to determine platform RTC clock frequency\n");
+	else
+		sn_rtc_cycles_per_second = ticks_per_sec;
+		
+	for (i=0;i<NR_CPUS;i++)
+		_sn_irq_desc[i] = _irq_desc;
+
+#ifdef CONFIG_IA64_MCA
+	platform_irq_list[ACPI20_ENTRY_PIS_CPEI] = IA64_PCE_VECTOR;
+#endif
+
+
+	if ( IS_RUNNING_ON_SIMULATOR() )
+	{
+#ifdef CONFIG_IA64_SGI_SN2
+		master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0);
+#else
+		master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
+#endif
+		printk(KERN_DEBUG "sn_setup: setting master_node_bedrock_address to 0x%lx\n",
+		       master_node_bedrock_address);
+	}
+
+	/*
+	 * we set the default root device to /dev/hda
+	 * to make simulation easy
+	 */
+	ROOT_DEV = to_kdev_t(0x0301);
+
+	/*
+	 * Create the PDAs and NODEPDAs for all the cpus.
+	 */
+	sn_init_pdas(cmdline_p);
+
+
+	/* 
+	 * For the bootcpu, we do this here. All other cpus will make the
+	 * call as part of cpu_init in slave cpu initialization.
+	 */
+	sn_cpu_init();
+
+
+#ifdef CONFIG_SMP
+	init_smp_config();
+#endif
+	screen_info = sn_screen_info;
+
+	/*
+	 * Turn off "floating-point assist fault" warnings by default.
+	 */
+	current->thread.flags |= IA64_THREAD_FPEMU_NOPRINT;
+}
+
+/**
+ * sn_init_pdas - setup node data areas
+ *
+ * One time setup for Node Data Area.  Called by sn_setup().
+ */
+void
+sn_init_pdas(char **cmdline_p)
+{
+	cnodeid_t	cnode;
+
+	/*
+	 * Make sure that the PDA fits entirely in the same page as the 
+	 * cpu_data area.
+	 */
+	if ((PDAADDR&~PAGE_MASK)+sizeof(pda_t) > PAGE_SIZE)
+		panic("overflow of cpu_data page");
+
+        /*
+         * Allocate & initalize the nodepda for each node.
+         */
+        for (cnode=0; cnode < numnodes; cnode++) {
+		nodepdaindr[cnode] = alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
+		memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
+
+#if defined(CONFIG_IA64_SGI_SN1)
+		Synergy_da_indr[cnode * 2] = (synergy_da_t *) alloc_bootmem_node(NODE_DATA(cnode), sizeof(synergy_da_t));
+		Synergy_da_indr[cnode * 2 + 1] = (synergy_da_t *) alloc_bootmem_node(NODE_DATA(cnode), sizeof(synergy_da_t));
+		memset(Synergy_da_indr[cnode * 2], 0, sizeof(synergy_da_t));
+		memset(Synergy_da_indr[cnode * 2 + 1], 0, sizeof(synergy_da_t));
+#endif
+        }
+
+	/*
+	 * Now copy the array of nodepda pointers to each nodepda.
+	 */
+        for (cnode=0; cnode < numnodes; cnode++)
+		memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr, sizeof(nodepdaindr));
+
+
+	/*
+	 * Set up IO related platform-dependent nodepda fields.
+	 * The following routine actually sets up the hubinfo struct
+	 * in nodepda.
+	 */
+	for (cnode = 0; cnode < numnodes; cnode++) {
+		init_platform_nodepda(nodepdaindr[cnode], cnode);
+		bte_init_node (nodepdaindr[cnode], cnode, cmdline_p);
+	}
+}
+
+/**
+ * sn_cpu_init - initialize per-cpu data areas
+ * @cpuid: cpuid of the caller
+ *
+ * Called during cpu initialization on each cpu as it starts.
+ * Currently, initializes the per-cpu data area for SNIA.
+ * Also sets up a few fields in the nodepda.  Also known as
+ * platform_cpu_init() by the ia64 machvec code.
+ */
+void __init
+sn_cpu_init(void)
+{
+	int	cpuid;
+	int	cpuphyid;
+	int	nasid;
+	int	slice;
+	int	cnode;
+
+	/*
+	 * The boot cpu makes this call again after platform initialization is
+	 * complete.
+	 */
+	if (nodepdaindr[0] == NULL)
+		return;
+
+	cpuid = smp_processor_id();
+	cpuphyid = ((ia64_get_lid() >> 16) & 0xffff);
+	nasid = cpu_physical_id_to_nasid(cpuphyid);
+	cnode = nasid_to_cnodeid(nasid);
+	slice = cpu_physical_id_to_slice(cpuphyid);
+
+	pda.p_nodepda = nodepdaindr[cnode];
+	pda.led_address = (long*) (LED0 + (slice<<LED_CPU_SHIFT));
+	pda.led_state = 0;
+	pda.hb_count = HZ/2;
+	pda.hb_state = 0;
+	pda.idle_flag = 0;
+	
+	if (local_node_data->active_cpu_count == 1)
+		nodepda->node_first_cpu = cpuid;
+
+#ifdef CONFIG_IA64_SGI_SN1
+	{
+		int	synergy;
+		synergy = cpu_physical_id_to_synergy(cpuphyid);
+		pda.p_subnodepda = &nodepdaindr[cnode]->snpda[synergy];
+	}
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN2
+
+	/*
+	 * We must use different memory allocators for first cpu (bootmem 
+	 * allocator) than for the other cpus (regular allocator).
+	 */
+	if (cpuid == 0)
+		irqpdaindr[cpuid] = alloc_bootmem_node(NODE_DATA(cpuid_to_cnodeid(cpuid)),sizeof(irqpda_t));
+	else
+		irqpdaindr[cpuid] = page_address(alloc_pages_node(local_cnodeid(), GFP_KERNEL, get_order(sizeof(irqpda_t))));
+	memset(irqpdaindr[cpuid], 0, sizeof(irqpda_t));
+	pda.p_irqpda = irqpdaindr[cpuid];
+	pda.pio_write_status_addr = (volatile unsigned long *)LOCAL_MMR_ADDR((slice < 2 ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ) );
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN1
+	pda.bedrock_rev_id = (volatile unsigned long *) LOCAL_HUB(LB_REV_ID);
+	if (cpuid_to_synergy(cpuid))
+		/* CPU B */
+		pda.pio_write_status_addr = (volatile unsigned long *) GBL_PERF_B_ADDR;
+	else
+		/* CPU A */
+		pda.pio_write_status_addr = (volatile unsigned long *) GBL_PERF_A_ADDR;
+#endif
+
+
+	bte_init_cpu();
+}
+
+
+/**
+ * cnodeid_to_cpuid - convert a cnode to a cpuid of a cpu on the node.
+ * @cnode: node to get a cpuid from
+ *	
+ * Returns -1 if no cpus exist on the node.
+ * NOTE:BRINGUP ZZZ This is NOT a good way to find cpus on the node.
+ * Need a better way!!
+ */
+int
+cnodeid_to_cpuid(int cnode) {
+	int cpu;
+
+	for (cpu = 0; cpu < smp_num_cpus; cpu++)
+		if (cpuid_to_cnodeid(cpu) == cnode)
+			break;
+
+	if (cpu == smp_num_cpus) 
+		cpu = -1;
+
+	return cpu;
+}
+
+#if 0 /* ##jh */
+/**
+ * get_cycles - return a non-decreasing timestamp
+ *
+ * On SN, we use an RTC read for this function
+ */
+cycles_t
+get_cycles (void)
+{
+	return GET_RTC_COUNTER();
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn1/Makefile linux/arch/ia64/sn/kernel/sn1/Makefile
--- linux.orig/arch/ia64/sn/kernel/sn1/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn1/Makefile	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,51 @@
+#
+# ia64/platform/sn/sn1/Makefile
+#
+# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it 
+# under the terms of version 2 of the GNU General Public License 
+# as published by the Free Software Foundation.
+# 
+# This program is distributed in the hope that it would be useful, but 
+# WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+# 
+# Further, this software is distributed without any warranty that it is 
+# free of the rightful claim of any third person regarding infringement 
+# or the like.  Any license provided herein, whether implied or 
+# otherwise, applies only to this software file.  Patent licenses, if 
+# any, provided herein do not apply to combinations of this program with 
+# other software, or any other product whatsoever.
+# 
+# You should have received a copy of the GNU General Public 
+# License along with this program; if not, write the Free Software 
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+# 
+# Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+# Mountain View, CA  94043, or:
+# 
+# http://www.sgi.com 
+# 
+# For further information regarding this notice, see: 
+# 
+# http://oss.sgi.com/projects/GenInfo/NoticeExplan
+#
+
+
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+all: sn1.a
+
+O_TARGET        = sn1.a
+
+obj-y          = cache.o error.o iomv.o synergy.o sn1_smp.o
+
+clean::
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn1/cache.c linux/arch/ia64/sn/kernel/sn1/cache.c
--- linux.orig/arch/ia64/sn/kernel/sn1/cache.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn1/cache.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,81 @@
+/*
+ * 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <asm/pgalloc.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/synergy.h>
+#include <asm/delay.h>
+
+#ifndef MB
+#define	MB	(1024*1024)
+#endif
+
+/*
+ * Lock for protecting SYN_TAG_DISABLE_WAY.
+ * Consider making this a per-FSB lock. 
+ */
+static spinlock_t flush_lock = SPIN_LOCK_UNLOCKED;
+
+/**
+ * sn_flush_all_caches - flush a range of addresses from all caches (incl. L4)
+ * @flush_addr: identity mapped region 7 address to start flushing
+ * @bytes: number of bytes to flush
+ *
+ * Flush a range of addresses from all caches including L4.  All addresses 
+ * fully or partially contained within @flush_addr to @flush_addr + @bytes 
+ * are flushed from the all caches.
+ */
+void
+sn_flush_all_caches(long flush_addr, long bytes)
+{
+	ulong 	addr, baddr, eaddr, bitbucket;
+	int	way, alias;
+
+	/*
+	 * Because of the way synergy implements "fc", this flushes the
+	 * data from all caches on all cpus & L4's on OTHER FSBs. It also
+	 * flushes both cpus on the local FSB. It does NOT flush it from 
+	 * the local FSB.
+	 */
+	flush_icache_range(flush_addr, flush_addr+bytes);
+
+	/*
+	 * Memory DIMMs are a minimum of 256MB and start on 256MB
+	 * boundaries. Convert the start address to an address
+	 * that is between +0MB & +128 of the same DIMM. 
+	 * Then add 8MB to skip the uncached MinState areas if the address
+	 * is on the master node.
+	 */
+	if (bytes > SYNERGY_L4_BYTES_PER_WAY)
+		bytes = SYNERGY_L4_BYTES_PER_WAY;
+	baddr = TO_NODE(smp_physical_node_id(), PAGE_OFFSET + (flush_addr & (128*MB-1)) + 8*MB); 
+	eaddr = (baddr+bytes+SYNERGY_BLOCK_SIZE-1) & ~(SYNERGY_BLOCK_SIZE-1);
+	baddr = baddr & ~(SYNERGY_BLOCK_SIZE-1);
+
+	/*
+	 * Now flush the local synergy.
+	 */
+	spin_lock(&flush_lock);
+	for(way=0; way<SYNERGY_L4_WAYS; way++) {
+		WRITE_LOCAL_SYNERGY_REG(SYN_TAG_DISABLE_WAY, 0xffL ^ (1L<<way));
+		mb();
+		for(alias=0; alias < 9; alias++)
+			for(addr=baddr; addr<eaddr; addr+=SYNERGY_BLOCK_SIZE)
+				bitbucket = *(volatile ulong *)(addr+alias*8*MB);
+		mb();
+	}
+	WRITE_LOCAL_SYNERGY_REG(SYN_TAG_DISABLE_WAY, 0);
+	spin_unlock(&flush_lock);
+
+}
+
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn1/error.c linux/arch/ia64/sn/kernel/sn1/error.c
--- linux.orig/arch/ia64/sn/kernel/sn1/error.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn1/error.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,187 @@
+/*
+ * SN1 Platform specific error Support
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/ptrace.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+
+/**
+ * snia_error_intr_handler - handle SN specific error interrupts
+ * @irq: error interrupt received
+ * @devid: device causing the interrupt
+ * @pt_regs: saved register state
+ *
+ * This routine is called when certain interrupts occur on SN systems.
+ * It will either recover from the situations that caused the interrupt
+ * or panic.
+ */
+void
+snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs)
+{
+	unsigned long long intpend_val;
+	unsigned long long bit;
+
+	switch (irq) {
+	case SGI_UART_IRQ:
+		/*
+		 * This isn't really an error interrupt.  We're just
+		 * here because we have to do something with them.
+		 * This is probably wrong, and this code will be
+		 * removed.
+		 */
+		intpend_val = LOCAL_HUB_L(PI_INT_PEND0);
+		if ( (bit = ~(1L<<GFX_INTR_A)) ==
+			(intpend_val & ~(1L<<GFX_INTR_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<GFX_INTR_B)) ==
+			(intpend_val & ~(1L<<GFX_INTR_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<PG_MIG_INTR)) ==
+			(intpend_val & ~(1L<<PG_MIG_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<UART_INTR)) ==
+			(intpend_val & ~(1L<<UART_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<CC_PEND_A)) ==
+			(intpend_val & ~(1L<<CC_PEND_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<CC_PEND_B)) ==
+			(intpend_val & ~(1L<<CC_PEND_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		printk("Received SGI_UART_IRQ (65), but no intpend0 bits were set???\n");
+		return;
+	case SGI_HUB_ERROR_IRQ:
+		/*
+		 * These are mostly error interrupts of various
+		 * sorts.  We need to do more than panic here, but
+		 * what the heck, this is bring up.
+		 */
+		intpend_val = LOCAL_HUB_L(PI_INT_PEND1);
+		
+		if ( (bit = ~(1L<<XB_ERROR)) ==
+			(intpend_val & ~(1L<<XB_ERROR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED XB_ERROR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<LB_ERROR)) ==
+			(intpend_val & ~(1L<<LB_ERROR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED LB_ERROR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NACK_INT_A)) ==
+			(intpend_val & ~(1L<<NACK_INT_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NACK_INT_A on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NACK_INT_B)) ==
+			(intpend_val & ~(1L<<NACK_INT_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NACK_INT_B on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<CLK_ERR_INTR)) ==
+			(intpend_val & ~(1L<<CLK_ERR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED CLK_ERR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<COR_ERR_INTR_A)) ==
+			(intpend_val & ~(1L<<COR_ERR_INTR_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED COR_ERR_INTR_A on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<COR_ERR_INTR_B)) ==
+			(intpend_val & ~(1L<<COR_ERR_INTR_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED COR_ERR_INTR_B on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<MD_COR_ERR_INTR)) ==
+			(intpend_val & ~(1L<<MD_COR_ERR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED MD_COR_ERR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NI_ERROR_INTR)) ==
+			(intpend_val & ~(1L<<NI_ERROR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NI_ERROR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<MSC_PANIC_INTR)) ==
+			(intpend_val & ~(1L<<MSC_PANIC_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED MSC_PANIC_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		printk("Received SGI_XB_ERROR_IRQ (182) but no intpend1 bits are set???\n");
+		return;
+	default:
+		printk("Received invalid irq in snia_error_intr_handler()\n");
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn1/iomv.c linux/arch/ia64/sn/kernel/sn1/iomv.c
--- linux.orig/arch/ia64/sn/kernel/sn1/iomv.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn1/iomv.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,65 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <asm/sn/simulator.h>
+#include <asm/delay.h>
+#include <asm/sn/pda.h>
+
+/**
+ * sn_io_addr - convert an in/out port to an i/o address
+ * @port: port to convert
+ *
+ * Legacy in/out instructions are converted to ld/st instructions
+ * on IA64.  This routine will convert a port number into a valid 
+ * SN i/o address.  Used by sn_in*() and sn_out*().
+ */
+void *
+sn_io_addr(unsigned long port)
+{
+	if (!IS_RUNNING_ON_SIMULATOR()) {
+		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
+	} else {
+		unsigned long io_base;
+		unsigned long addr;
+ 
+		/*
+ 		 * word align port, but need more than 10 bits
+ 		 * for accessing registers in bedrock local block
+ 		 * (so we don't do port&0xfff)
+ 		 */
+		if ((port >= 0x1f0 && port <= 0x1f7) ||
+			port == 0x3f6 || port == 0x3f7) {
+			io_base = __IA64_UNCACHED_OFFSET | 0x00000FFFFC000000;
+			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
+		} else {
+			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
+		}
+		return(void *) addr;
+	}
+}
+
+/**
+ * sn1_mmiob - I/O space memory barrier
+ *
+ * Acts as a memory mapped I/O barrier for platforms that queue writes to 
+ * I/O space.  This ensures that subsequent writes to I/O space arrive after
+ * all previous writes.  For most ia64 platforms, this is a simple
+ * 'mf.a' instruction.  For other platforms, mmiob() may have to read
+ * a chipset register to ensure ordering.
+ *
+ * On SN1, we wait for the PIO_WRITE_STATUS Bedrock register to clear.
+ */
+void
+sn1_mmiob (void)
+{
+	(volatile unsigned long) (*pda.bedrock_rev_id);
+	while (!(volatile unsigned long) (*pda.pio_write_status_addr))
+		udelay(5);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn1/sn1_smp.c linux/arch/ia64/sn/kernel/sn1/sn1_smp.c
--- linux.orig/arch/ia64/sn/kernel/sn1/sn1_smp.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn1/sn1_smp.c	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,474 @@
+/*
+ * SN1 Platform specific SMP Support
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mmzone.h>
+
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/sal.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/hw_irq.h>
+#include <asm/current.h>
+#include <asm/delay.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * The following structure is used to pass params thru smp_call_function
+ * to other cpus for flushing TLB ranges.
+ */
+typedef struct {
+	unsigned long	start;
+	unsigned long	end;
+	unsigned long	nbits;
+	unsigned int	rid;
+	atomic_t	unfinished_count;
+} ptc_params_t;
+
+#define NUMPTC	512
+
+static ptc_params_t	ptcParamArray[NUMPTC] __attribute__((__aligned__(128)));
+
+/* use separate cache lines on ptcParamsNextByCpu to avoid false sharing */
+static ptc_params_t	*ptcParamsNextByCpu[NR_CPUS*16] __attribute__((__aligned__(128)));
+static volatile ptc_params_t	*ptcParamsEmpty __cacheline_aligned;
+
+/*REFERENCED*/
+static spinlock_t ptcParamsLock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
+
+static int ptcInit = 0;
+#ifdef PTCDEBUG
+static int ptcParamsAllBusy = 0;		/* debugging/statistics */
+static int ptcCountBacklog = 0;
+static int ptcBacklog[NUMPTC+1];
+static char ptcParamsCounts[NR_CPUS][NUMPTC] __attribute__((__aligned__(128)));
+static char ptcParamsResults[NR_CPUS][NUMPTC] __attribute__((__aligned__(128)));
+#endif
+
+/*
+ * Make smp_send_flush_tlbsmp_send_flush_tlb() a weak reference,
+ * so that we get a clean compile with the ia64 patch without the
+ * actual SN1 specific code in arch/ia64/kernel/smp.c.
+ */
+extern void smp_send_flush_tlb (void) __attribute((weak));
+
+/*
+ * The following table/struct is for remembering PTC coherency domains. It
+ * is also used to translate sapicid into cpuids. We dont want to start 
+ * cpus unless we know their cache domain.
+ */
+#ifdef PTC_NOTYET
+sn_sapicid_info_t	sn_sapicid_info[NR_CPUS];
+#endif
+
+/**
+ * sn1_ptc_l_range - purge local translation cache
+ * @start: start of virtual address range
+ * @end: end of virtual address range
+ * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
+ *
+ * Purges the range specified from the local processor's translation cache
+ * (as opposed to the translation registers).  Note that more than the specified
+ * range *may* be cleared from the cache by some processors.
+ *
+ * This is probably not good enough, but I don't want to try to make it better 
+ * until I get some statistics on a running system. At a minimum, we should only 
+ * send IPIs to 1 processor in each TLB domain & have it issue a ptc.g on it's 
+ * own FSB. Also, we only have to serialize per FSB, not globally.
+ *
+ * More likely, we will have to do some work to reduce the frequency of calls to
+ * this routine.
+ */
+static inline void
+sn1_ptc_l_range(unsigned long start, unsigned long end, unsigned long nbits)
+{
+	do {
+		__asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
+		start += (1UL << nbits);
+	} while (start < end);
+	ia64_srlz_d();
+}
+
+/**
+ * sn1_received_flush_tlb - cpu tlb flush routine
+ *
+ * Flushes the TLB of a given processor.
+ */
+void
+sn1_received_flush_tlb(void)
+{
+	unsigned long	start, end, nbits;
+	unsigned int	rid, saved_rid;
+	int		cpu = smp_processor_id();
+	int		result;
+	ptc_params_t	*ptcParams;
+
+	ptcParams = ptcParamsNextByCpu[cpu*16];
+	if (ptcParams == ptcParamsEmpty)
+		return;
+
+	do {
+		start = ptcParams->start;
+		saved_rid = (unsigned int) ia64_get_rr(start);
+		end = ptcParams->end;
+		nbits = ptcParams->nbits;
+		rid = ptcParams->rid;
+
+		if (saved_rid != rid) {
+			ia64_set_rr(start, (unsigned long)rid);
+			ia64_srlz_d();
+		}
+
+		sn1_ptc_l_range(start, end, nbits);
+
+		if (saved_rid != rid) 
+			ia64_set_rr(start, (unsigned long)saved_rid);
+
+		ia64_srlz_i();
+
+		result = atomic_dec(&ptcParams->unfinished_count);
+#ifdef PTCDEBUG
+		{
+		    int i = ptcParams-&ptcParamArray[0];
+		    ptcParamsResults[cpu][i] = (char) result;
+		    ptcParamsCounts[cpu][i]++;
+		}
+#endif /* PTCDEBUG */
+
+		if (++ptcParams == &ptcParamArray[NUMPTC])
+			ptcParams = &ptcParamArray[0];
+
+	} while (ptcParams != ptcParamsEmpty);
+
+	ptcParamsNextByCpu[cpu*16] = ptcParams;
+}
+
+/**
+ * sn1_global_tlb_purge - flush a translation cache range on all processors
+ * @start: start of virtual address range to flush
+ * @end: end of virtual address range
+ * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
+ *
+ * Flushes the translation cache of all processors from @start to @end.
+ */
+void
+sn1_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
+{
+	ptc_params_t	*params;
+	ptc_params_t	*next;
+	unsigned long	irqflags;
+#ifdef PTCDEBUG
+	ptc_params_t	*nextnext;
+	int		backlog = 0;
+#endif
+
+	if (smp_num_cpus == 1) {
+		sn1_ptc_l_range(start, end, nbits);
+		return;
+	}
+
+	if (in_interrupt()) {
+		/*
+		 *  If at interrupt level and cannot get spinlock, 
+		 *  then do something useful by flushing own tlbflush queue
+		 *  so as to avoid a possible deadlock.
+		 */
+		while (!spin_trylock(&ptcParamsLock)) {
+			local_irq_save(irqflags);
+			sn1_received_flush_tlb();
+			local_irq_restore(irqflags);
+			udelay(10);	/* take it easier on the bus */	
+		}
+	} else {
+		spin_lock(&ptcParamsLock);
+	}
+
+	if (!ptcInit) {
+		int cpu;
+		ptcInit = 1;
+		memset(ptcParamArray, 0, sizeof(ptcParamArray));
+		ptcParamsEmpty = &ptcParamArray[0];
+		for (cpu=0; cpu<NR_CPUS; cpu++)
+			ptcParamsNextByCpu[cpu*16] = &ptcParamArray[0];
+
+#ifdef PTCDEBUG
+		memset(ptcBacklog, 0, sizeof(ptcBacklog));
+		memset(ptcParamsCounts, 0, sizeof(ptcParamsCounts));
+		memset(ptcParamsResults, 0, sizeof(ptcParamsResults));
+#endif	/* PTCDEBUG */
+	}
+
+	params = (ptc_params_t *) ptcParamsEmpty;
+	next = (ptc_params_t *) ptcParamsEmpty + 1;
+	if (next == &ptcParamArray[NUMPTC])
+		next = &ptcParamArray[0];
+
+#ifdef PTCDEBUG
+	nextnext = next + 1;
+	if (nextnext == &ptcParamArray[NUMPTC])
+		nextnext = &ptcParamArray[0];
+
+	if (ptcCountBacklog) {
+		/* quick count of backlog */
+		ptc_params_t *ptr;
+
+		/* check the current pointer to the beginning */
+		ptr = params;
+		while(--ptr >= &ptcParamArray[0]) {
+			if (atomic_read(&ptr->unfinished_count) == 0)
+				break;
+			++backlog;
+		}
+
+		if (backlog) {
+			/* check the end of the array */
+			ptr = &ptcParamArray[NUMPTC];
+			while (--ptr > params) {
+				if (atomic_read(&ptr->unfinished_count) == 0)
+					break;
+				++backlog;
+			}
+		}
+		ptcBacklog[backlog]++;
+	}
+#endif	/* PTCDEBUG */
+
+	/* wait for the next entry to clear...should be rare */
+	if (atomic_read(&next->unfinished_count) > 0) {
+#ifdef PTCDEBUG
+		ptcParamsAllBusy++;
+
+		if (atomic_read(&nextnext->unfinished_count) == 0) {
+		    if (atomic_read(&next->unfinished_count) > 0) {
+			panic("\nnonzero next zero nextnext %lx %lx\n",
+			    (long)next, (long)nextnext);
+		    }
+		}
+#endif
+
+		/* it could be this cpu that is behind */
+		local_irq_save(irqflags);
+		sn1_received_flush_tlb();
+		local_irq_restore(irqflags);
+
+		/* now we know it's not this cpu, so just wait */
+		while (atomic_read(&next->unfinished_count) > 0) {
+			barrier();
+		}
+	}
+
+	params->start = start;
+	params->end = end;
+	params->nbits = nbits;
+	params->rid = (unsigned int) ia64_get_rr(start);
+	atomic_set(&params->unfinished_count, smp_num_cpus);
+
+	/* The atomic_set above can hit memory *after* the update
+	 * to ptcParamsEmpty below, which opens a timing window
+	 * that other cpus can squeeze into!
+	 */
+	mb();
+
+	/* everything is ready to process:
+	 *	-- global lock is held
+	 *	-- new entry + 1 is free
+	 *	-- new entry is set up
+	 * so now:
+	 *	-- update the global next pointer
+	 *	-- unlock the global lock
+	 *	-- send IPI to notify other cpus
+	 *	-- process the data ourselves
+	 */
+	ptcParamsEmpty = next;
+	spin_unlock(&ptcParamsLock);
+	smp_send_flush_tlb();
+
+	local_irq_save(irqflags);
+	sn1_received_flush_tlb();
+	local_irq_restore(irqflags);
+
+	/* Currently we don't think global TLB purges need to be atomic.
+	 * All CPUs get sent IPIs, so if they haven't done the purge,
+	 * they're busy with interrupts that are at the IPI level, which is
+	 * priority 15.  We're asserting that any code at that level
+	 * shouldn't be using user TLB entries.  To change this to wait
+	 * for all the flushes to complete, enable the following code.
+	 */
+#ifdef SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE
+	/* this code is not tested */
+	/* wait for the flush to complete */
+	while (atomic_read(&params.unfinished_count) > 1)
+		barrier();
+
+	atomic_set(&params->unfinished_count, 0);
+#endif
+}
+
+/**
+ * sn_send_IPI_phys - send an IPI to a Nasid and slice
+ * @physid: physical cpuid to receive the interrupt.
+ * @vector: command to send
+ * @delivery_mode: delivery mechanism
+ *
+ * Sends an IPI (interprocessor interrupt) to the processor specified by
+ * @physid
+ *
+ * @delivery_mode can be one of the following
+ *
+ * %IA64_IPI_DM_INT - pend an interrupt
+ * %IA64_IPI_DM_PMI - pend a PMI
+ * %IA64_IPI_DM_NMI - pend an NMI
+ * %IA64_IPI_DM_INIT - pend an INIT interrupt
+ */
+void
+sn_send_IPI_phys(long physid, int vector, int delivery_mode)
+{
+	long		*p;
+	long		nasid, slice;
+
+	static int 	off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
+
+	nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+	p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
+
+#if defined(ZZZBRINGUP)
+	{
+	static int count=0;
+	if (count++ < 10) printk("ZZ sendIPI 0x%x vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
+		smp_processor_id(), vector, nasid, slice, (long)p);
+	}
+#endif
+	mb();
+	*p = (delivery_mode << 8) | (vector & 0xff);
+}
+
+
+/**
+ * sn1_send_IPI - send an IPI to a processor
+ * @cpuid: target of the IPI
+ * @vector: command to send
+ * @delivery_mode: delivery mechanism
+ * @redirect: redirect the IPI?
+ *
+ * Sends an IPI (interprocessor interrupt) to the processor specified by
+ * @cpuid.  @delivery_mode can be one of the following
+ *
+ * %IA64_IPI_DM_INT - pend an interrupt
+ * %IA64_IPI_DM_PMI - pend a PMI
+ * %IA64_IPI_DM_NMI - pend an NMI
+ * %IA64_IPI_DM_INIT - pend an INIT interrupt
+ */
+void
+sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
+{
+	long		physid;
+
+	physid = cpu_physical_id(cpuid);
+
+	sn_send_IPI_phys(physid, vector, delivery_mode);
+}
+#ifdef CONFIG_SMP
+
+#ifdef PTC_NOTYET
+static void __init
+process_sal_ptc_domain_info(ia64_sal_ptc_domain_info_t *di, int domain)
+{
+	ia64_sal_ptc_domain_proc_entry_t	*pe;
+	int 					i, sapicid, cpuid;
+
+	pe = __va(di->proc_list);
+	for (i=0; i<di->proc_count; i++, pe++) {
+		sapicid = id_eid_to_sapicid(pe->id, pe->eid);
+		cpuid = cpu_logical_id(sapicid);
+		sn_sapicid_info[cpuid].domain = domain;
+		sn_sapicid_info[cpuid].sapicid = sapicid;
+	}
+}
+
+
+static void __init
+process_sal_desc_ptc(ia64_sal_desc_ptc_t *ptc)
+{
+	ia64_sal_ptc_domain_info_t	*di;
+	int i;
+
+	di = __va(ptc->domain_info);
+	for (i=0; i<ptc->num_domains; i++, di++) {
+		process_sal_ptc_domain_info(di, i);	
+	}
+}
+#endif /* PTC_NOTYET */
+
+/**
+ * init_sn1_smp_config - setup PTC domains per processor
+ */
+void __init
+init_sn1_smp_config(void)
+{
+	if (!ia64_ptc_domain_info)  {
+		printk("SMP: Can't find PTC domain info. Forcing UP mode\n");
+		smp_num_cpus = 1;
+		return;
+	}
+
+#ifdef PTC_NOTYET
+	memset (sn_sapicid_info, -1, sizeof(sn_sapicid_info));
+	process_sal_desc_ptc(ia64_ptc_domain_info);
+#endif
+}
+
+#else /* CONFIG_SMP */
+
+void __init
+init_sn1_smp_config(void)
+{
+
+#ifdef PTC_NOTYET
+	sn_sapicid_info[0].sapicid = hard_smp_processor_id();
+#endif
+}
+
+#endif /* CONFIG_SMP */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn1/synergy.c linux/arch/ia64/sn/kernel/sn1/synergy.c
--- linux.orig/arch/ia64/sn/kernel/sn1/synergy.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn1/synergy.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,532 @@
+/*
+ * SN1 Platform specific synergy Support
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/proc_fs.h>
+
+#include <asm/ptrace.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/sn1/synergy.h>
+#include <asm/sn/sndrv.h>
+
+int bit_pos_to_irq(int bit);
+void setclear_mask_b(int irq, int cpuid, int set);
+void setclear_mask_a(int irq, int cpuid, int set);
+void * kmalloc(size_t size, int flags);
+
+static int synergy_perf_initialized = 0;
+
+void
+synergy_intr_alloc(int bit, int cpuid) {
+	return;
+}
+
+int
+synergy_intr_connect(int bit, 
+		int cpuid)
+{
+	int irq;
+	unsigned is_b;
+
+	irq = bit_pos_to_irq(bit);
+
+	is_b = (cpuid_to_slice(cpuid)) & 1;
+	if (is_b) {
+		setclear_mask_b(irq,cpuid,1);
+		setclear_mask_a(irq,cpuid, 0);
+	} else {
+		setclear_mask_a(irq, cpuid, 1);
+		setclear_mask_b(irq, cpuid, 0);
+	}
+	return 0;
+}
+void
+setclear_mask_a(int irq, int cpuid, int set)
+{
+	int synergy;
+	int nasid;
+	int reg_num;
+	unsigned long mask;
+	unsigned long addr;
+	unsigned long reg;
+	unsigned long val;
+	int my_cnode, my_synergy;
+	int target_cnode, target_synergy;
+
+        /*
+         * Perform some idiot checks ..
+         */
+        if ( (irq < 0) || (irq > 255) ||
+                (cpuid < 0) || (cpuid > 512) ) {
+                printk("clear_mask_a: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
+		return;
+	}
+
+	target_cnode = cpuid_to_cnodeid(cpuid);
+	target_synergy = cpuid_to_synergy(cpuid);
+	my_cnode = cpuid_to_cnodeid(smp_processor_id());
+	my_synergy = cpuid_to_synergy(smp_processor_id());
+
+	reg_num = irq / 64;
+	mask = 1;
+	mask <<= (irq % 64);
+	switch (reg_num) {
+		case 0: 
+			reg = VEC_MASK0A;
+			addr = VEC_MASK0A_ADDR;
+			break;
+		case 1: 
+			reg = VEC_MASK1A;
+			addr = VEC_MASK1A_ADDR;
+			break;
+		case 2: 
+			reg = VEC_MASK2A;
+			addr = VEC_MASK2A_ADDR;
+			break;
+		case 3: 
+			reg = VEC_MASK3A;
+			addr = VEC_MASK3A_ADDR;
+			break;
+		default:
+			reg = addr = 0;
+			break;
+	}
+	if (my_cnode == target_cnode && my_synergy == target_synergy) {
+		// local synergy
+		val = READ_LOCAL_SYNERGY_REG(addr);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		WRITE_LOCAL_SYNERGY_REG(addr, val);
+		val = READ_LOCAL_SYNERGY_REG(addr);
+	} else { /* remote synergy */
+		synergy = cpuid_to_synergy(cpuid);
+		nasid = cpuid_to_nasid(cpuid);
+		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
+	}
+}
+
+void
+setclear_mask_b(int irq, int cpuid, int set)
+{
+	int synergy;
+	int nasid;
+	int reg_num;
+	unsigned long mask;
+	unsigned long addr;
+	unsigned long reg;
+	unsigned long val;
+	int my_cnode, my_synergy;
+	int target_cnode, target_synergy;
+
+	/*
+	 * Perform some idiot checks ..
+	 */
+	if ( (irq < 0) || (irq > 255) ||
+		(cpuid < 0) || (cpuid > 512) ) {
+		printk("clear_mask_b: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
+		return;
+	}
+
+	target_cnode = cpuid_to_cnodeid(cpuid);
+	target_synergy = cpuid_to_synergy(cpuid);
+	my_cnode = cpuid_to_cnodeid(smp_processor_id());
+	my_synergy = cpuid_to_synergy(smp_processor_id());
+
+	reg_num = irq / 64;
+	mask = 1;
+	mask <<= (irq % 64);
+	switch (reg_num) {
+		case 0: 
+			reg = VEC_MASK0B;
+			addr = VEC_MASK0B_ADDR;
+			break;
+		case 1: 
+			reg = VEC_MASK1B;
+			addr = VEC_MASK1B_ADDR;
+			break;
+		case 2: 
+			reg = VEC_MASK2B;
+			addr = VEC_MASK2B_ADDR;
+			break;
+		case 3: 
+			reg = VEC_MASK3B;
+			addr = VEC_MASK3B_ADDR;
+			break;
+		default:
+			reg = addr = 0;
+			break;
+	}
+	if (my_cnode == target_cnode && my_synergy == target_synergy) {
+		// local synergy
+		val = READ_LOCAL_SYNERGY_REG(addr);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		WRITE_LOCAL_SYNERGY_REG(addr, val);
+		val = READ_LOCAL_SYNERGY_REG(addr);
+	} else { /* remote synergy */
+		synergy = cpuid_to_synergy(cpuid);
+		nasid = cpuid_to_nasid(cpuid);
+		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
+	}
+}
+
+/*
+ * Synergy perf stats. Multiplexed via timer_interrupt.
+ */
+
+static int
+synergy_perf_append(uint64_t modesel)
+{
+	int		cnode;
+	nodepda_t       *npdap;
+	synergy_perf_t	*p;
+	int		checked = 0;
+	int		err = 0;
+
+	/* bit 45 is enable */
+	modesel |= (1UL << 45);
+
+	for (cnode=0; cnode < numnodes; cnode++) {
+		/* for each node, insert a new synergy_perf entry */
+		if ((npdap = NODEPDA(cnode)) == NULL) {
+			printk("synergy_perf_append: cnode=%d NODEPDA(cnode)==NULL, nodepda=%p\n", cnode, (void *)nodepda);
+			continue;
+		}
+
+		if (npdap->synergy_perf_enabled) {
+			/* user must disable counting to append new events */
+			err = -EBUSY;
+			break;
+		}
+
+		if (!checked && npdap->synergy_perf_data != NULL) {
+			checked = 1;
+			for (p = npdap->synergy_perf_first; ;) {
+				if (p->modesel == modesel)
+					return 0; /* event already registered */
+				if ((p = p->next) == npdap->synergy_perf_first)
+					break;
+			}
+		}
+
+		/* XX use kmem_alloc_node() when it is implemented */
+		p = (synergy_perf_t *)kmalloc(sizeof(synergy_perf_t), GFP_KERNEL);
+		if ((((uint64_t)p) & 7UL) != 0)
+			BUG(); /* bad alignment */
+		if (p == NULL) {
+			err = -ENOMEM;
+			break;
+		}
+		else {
+			memset(p, 0, sizeof(synergy_perf_t));
+			p->modesel = modesel;
+
+			spin_lock_irq(&npdap->synergy_perf_lock);
+			if (npdap->synergy_perf_data == NULL) {
+				/* circular list */
+				p->next = p;
+				npdap->synergy_perf_first = p;
+				npdap->synergy_perf_data = p;
+			}
+			else {
+				p->next = npdap->synergy_perf_data->next;
+				npdap->synergy_perf_data->next = p;
+			}
+			spin_unlock_irq(&npdap->synergy_perf_lock);
+		}
+	}
+
+	return err;
+}
+
+static void
+synergy_perf_set_freq(int freq)
+{
+	int		cnode;
+	nodepda_t	*npdap;
+
+	for (cnode=0; cnode < numnodes; cnode++) {
+		if ((npdap = NODEPDA(cnode)) != NULL)
+			npdap->synergy_perf_freq = freq;
+	}
+}
+
+static void
+synergy_perf_set_enable(int enable)
+{
+	int		cnode;
+	nodepda_t	*npdap;
+
+	for (cnode=0; cnode < numnodes; cnode++) {
+		if ((npdap = NODEPDA(cnode)) != NULL)
+			npdap->synergy_perf_enabled = enable;
+	}
+	printk("NOTICE: synergy perf counting %sabled on all nodes\n", enable ? "en" : "dis");
+}
+
+static int
+synergy_perf_size(nodepda_t *npdap)
+{
+	synergy_perf_t	*p;
+	int		n;
+
+	if (npdap->synergy_perf_enabled == 0) {
+		/* no stats to return */
+		return 0;
+	}
+
+	spin_lock_irq(&npdap->synergy_perf_lock);
+	for (n=0, p = npdap->synergy_perf_first; p;) {
+		n++;
+		p = p->next;
+		if (p == npdap->synergy_perf_first)
+			break;
+	}
+	spin_unlock_irq(&npdap->synergy_perf_lock);
+
+	/* bytes == n pairs of {event,counter} */
+	return n * 2 * sizeof(uint64_t);
+}
+
+static int
+synergy_perf_ioctl(struct inode *inode, struct file *file,
+        unsigned int cmd, unsigned long arg)
+{
+	int             cnode;
+	nodepda_t       *npdap;
+	synergy_perf_t	*p;
+	int		intarg;
+	int		fsb;
+	uint64_t	longarg;
+	uint64_t	*stats;
+	int		n;
+	devfs_handle_t	d;
+	arbitrary_info_t info;
+	
+	if ((d = devfs_get_handle_from_inode(inode)) == NULL)
+		return -ENODEV;
+	info = hwgraph_fastinfo_get(d);
+
+	cnode = SYNERGY_PERF_INFO_CNODE(info);
+	fsb = SYNERGY_PERF_INFO_FSB(info);
+	npdap = NODEPDA(cnode);
+
+	switch (cmd) {
+	case SNDRV_GET_SYNERGY_VERSION:
+		/* return int, version of data structure for SNDRV_GET_SYNERGYINFO */
+		intarg = 1; /* version 1 */
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_GET_INFOSIZE:
+		/* return int, sizeof buf needed for SYNERGY_PERF_GET_STATS */
+		intarg = synergy_perf_size(npdap);
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_GET_SYNERGYINFO:
+		/* return array of event/value pairs, this node only */
+		if ((intarg = synergy_perf_size(npdap)) <= 0)
+			return -ENODATA;
+		if ((stats = (uint64_t *)kmalloc(intarg, GFP_KERNEL)) == NULL)
+			return -ENOMEM;
+		spin_lock_irq(&npdap->synergy_perf_lock);
+		for (n=0, p = npdap->synergy_perf_first; p;) {
+			stats[n++] = p->modesel;
+			if (p->intervals > 0)
+			    stats[n++] = p->counts[fsb] * p->total_intervals / p->intervals;
+			else
+			    stats[n++] = 0;
+			p = p->next;
+			if (p == npdap->synergy_perf_first)
+				break;
+		}
+		spin_unlock_irq(&npdap->synergy_perf_lock);
+
+		if (copy_to_user((void *)arg, stats, intarg)) {
+		    kfree(stats);
+		    return -EFAULT;
+		}
+
+		kfree(stats);
+		break;
+
+	case SNDRV_SYNERGY_APPEND:
+		/* reads 64bit event, append synergy perf event to all nodes  */
+		if (copy_from_user(&longarg, (void *)arg, sizeof(longarg)))
+		    return -EFAULT;
+		return synergy_perf_append(longarg);
+		break;
+
+	case SNDRV_GET_SYNERGY_STATUS:
+		/* return int, 1 if enabled else 0 */
+		intarg = npdap->synergy_perf_enabled;
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_SYNERGY_ENABLE:
+		/* read int, if true enable counting else disable */
+		if (copy_from_user(&intarg, (void *)arg, sizeof(intarg)))
+		    return -EFAULT;
+		synergy_perf_set_enable(intarg);
+		break;
+
+	case SNDRV_SYNERGY_FREQ:
+		/* read int, set jiffies per update */ 
+		if (copy_from_user(&intarg, (void *)arg, sizeof(intarg)))
+		    return -EFAULT;
+		if (intarg < 0 || intarg >= HZ)
+			return -EINVAL;
+		synergy_perf_set_freq(intarg);
+		break;
+
+	default:
+		printk("Warning: invalid ioctl %d on synergy mon for cnode=%d fsb=%d\n", cmd, cnode, fsb);
+		return -EINVAL;
+	}
+	return(0);
+}
+
+struct file_operations synergy_mon_fops = {
+        ioctl:		synergy_perf_ioctl,
+};
+
+void
+synergy_perf_update(int cpu)
+{
+	nasid_t		nasid;
+	cnodeid_t       cnode;
+	struct nodepda_s *npdap;
+
+	/*
+	 * synergy_perf_initialized is set by synergy_perf_init()
+	 * which is called last thing by sn_mp_setup(), i.e. well
+	 * after nodepda has been initialized.
+	 */
+	if (!synergy_perf_initialized)
+		return;
+
+	cnode = cpuid_to_cnodeid(cpu);
+	npdap = NODEPDA(cnode);
+
+	if (npdap == NULL || cnode < 0 || cnode >= numnodes)
+		/* this should not happen: still in early io init */
+		return;
+
+#if 0
+	/* use this to check nodepda initialization */
+	if (((uint64_t)npdap) & 0x7) {
+		printk("\nERROR on cpu %d : cnode=%d, npdap == %p, not aligned\n", cpu, cnode, npdap);
+		BUG();
+	}
+#endif
+
+	if (npdap->synergy_perf_enabled == 0 || npdap->synergy_perf_data == NULL) {
+		/* Not enabled, or no events to monitor */
+		return;
+	}
+
+	if (npdap->synergy_inactive_intervals++ % npdap->synergy_perf_freq != 0) {
+		/* don't multiplex on every timer interrupt */
+		return;
+	}
+
+	/*
+	 * Read registers for last interval and increment counters.
+	 * Hold the per-node synergy_perf_lock so concurrent readers get
+	 * consistent values.
+	 */
+	spin_lock_irq(&npdap->synergy_perf_lock);
+
+	nasid = cpuid_to_nasid(cpu);
+	npdap->synergy_active_intervals++;
+	npdap->synergy_perf_data->intervals++;
+	npdap->synergy_perf_data->total_intervals = npdap->synergy_active_intervals;
+
+	npdap->synergy_perf_data->counts[0] += 0xffffffffffUL &
+		REMOTE_SYNERGY_LOAD(nasid, 0, PERF_CNTR0_A);
+
+	npdap->synergy_perf_data->counts[1] += 0xffffffffffUL &
+		REMOTE_SYNERGY_LOAD(nasid, 1, PERF_CNTR0_B);
+
+	/* skip to next in circular list */
+	npdap->synergy_perf_data = npdap->synergy_perf_data->next;
+
+	spin_unlock_irq(&npdap->synergy_perf_lock);
+
+	/* set the counter 0 selection modes for both A and B */
+	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTL0_A, npdap->synergy_perf_data->modesel);
+	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTL0_B, npdap->synergy_perf_data->modesel);
+
+	/* and reset the counter registers to zero */
+	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTR0_A, 0UL);
+	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTR0_B, 0UL);
+}
+
+void
+synergy_perf_init(void)
+{
+	printk("synergy_perf_init(), counting is initially disabled\n");
+	synergy_perf_initialized++;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn2/Makefile linux/arch/ia64/sn/kernel/sn2/Makefile
--- linux.orig/arch/ia64/sn/kernel/sn2/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn2/Makefile	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,51 @@
+#
+# ia64/platform/sn/sn1/Makefile
+#
+# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it 
+# under the terms of version 2 of the GNU General Public License 
+# as published by the Free Software Foundation.
+# 
+# This program is distributed in the hope that it would be useful, but 
+# WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+# 
+# Further, this software is distributed without any warranty that it is 
+# free of the rightful claim of any third person regarding infringement 
+# or the like.  Any license provided herein, whether implied or 
+# otherwise, applies only to this software file.  Patent licenses, if 
+# any, provided herein do not apply to combinations of this program with 
+# other software, or any other product whatsoever.
+# 
+# You should have received a copy of the GNU General Public 
+# License along with this program; if not, write the Free Software 
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+# 
+# Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+# Mountain View, CA  94043, or:
+# 
+# http://www.sgi.com 
+# 
+# For further information regarding this notice, see: 
+# 
+# http://oss.sgi.com/projects/GenInfo/NoticeExplan
+#
+
+
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+all: sn2.a
+
+O_TARGET        = sn2.a
+
+obj-y          = cache.o iomv.o sn2_smp.o
+
+clean::
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn2/cache.c linux/arch/ia64/sn/kernel/sn2/cache.c
--- linux.orig/arch/ia64/sn/kernel/sn2/cache.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn2/cache.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,29 @@
+/*
+ * 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ *
+ */
+
+#include <asm/pgalloc.h>
+
+/**
+ * sn_flush_all_caches - flush a range of address from all caches (incl. L4)
+ * @flush_addr: identity mapped region 7 address to start flushing
+ * @bytes: number of bytes to flush
+ *
+ * Flush a range of addresses from all caches including L4. 
+ * All addresses fully or partially contained within 
+ * @flush_addr to @flush_addr + @bytes are flushed
+ * from the all caches.
+ */
+void
+sn_flush_all_caches(long flush_addr, long bytes)
+{
+	flush_icache_range(flush_addr, flush_addr+bytes);
+}
+
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn2/iomv.c linux/arch/ia64/sn/kernel/sn2/iomv.c
--- linux.orig/arch/ia64/sn/kernel/sn2/iomv.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn2/iomv.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,65 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/sn_cpuid.h>
+
+/**
+ * sn_io_addr - convert an in/out port to an i/o address
+ * @port: port to convert
+ *
+ * Legacy in/out instructions are converted to ld/st instructions
+ * on IA64.  This routine will convert a port number into a valid 
+ * SN i/o address.  Used by sn_in*() and sn_out*().
+ */
+void *
+sn_io_addr(unsigned long port)
+{
+	if (!IS_RUNNING_ON_SIMULATOR()) {
+		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
+	} else {
+		unsigned long io_base;
+		unsigned long addr;
+ 
+		/*
+ 		 * word align port, but need more than 10 bits
+ 		 * for accessing registers in bedrock local block
+ 		 * (so we don't do port&0xfff)
+ 		 */
+		if ((port >= 0x1f0 && port <= 0x1f7) ||
+			port == 0x3f6 || port == 0x3f7) {
+			io_base = (0xc000000fcc000000 | ((unsigned long)get_nasid() << 38));
+			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
+		} else {
+			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
+		}
+		return(void *) addr;
+	}
+}
+
+/**
+ * sn2_mmiob - I/O space memory barrier
+ *
+ * Acts as a memory mapped I/O barrier for platforms that queue writes to 
+ * I/O space.  This ensures that subsequent writes to I/O space arrive after
+ * all previous writes.  For most ia64 platforms, this is a simple
+ * 'mf.a' instruction.  For other platforms, mmiob() may have to read
+ * a chipset register to ensure ordering.
+ *
+ * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
+ */
+void
+sn2_mmiob (void)
+{
+	while ( !((volatile unsigned long) (*pda.pio_write_status_addr)) & 0x8000000000000000)
+		udelay(5);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn2/sn2_smp.c linux/arch/ia64/sn/kernel/sn2/sn2_smp.c
--- linux.orig/arch/ia64/sn/kernel/sn2/sn2_smp.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn2/sn2_smp.c	2002-08-01 06:42:30.000000000 +0000
@@ -0,0 +1,184 @@
+/*
+ * SN2 Platform specific SMP Support
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mmzone.h>
+
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/sal.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/hw_irq.h>
+#include <asm/current.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+
+/**
+ * sn2_global_tlb_purge - globally purge translation cache of virtual address range
+ * @start: start of virtual address range
+ * @end: end of virtual address range
+ * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
+ *
+ * Purges the translation caches of all processors of the given virtual address
+ * range.
+ */
+void
+sn2_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
+{
+	int		cnode, nasid;
+	volatile long	*ptc0, *ptc1, *piows;
+	unsigned long	ws, next, data0, data1;
+
+	piows = (long*)LOCAL_MMR_ADDR(get_slice() ? SH_PIO_WRITE_STATUS_1 : SH_PIO_WRITE_STATUS_0);
+	data0 = (1UL<<SH_PTC_0_A_SHFT) |
+		(nbits<<SH_PTC_0_PS_SHFT) |
+		((ia64_get_rr(start)>>8)<<SH_PTC_0_RID_SHFT) |
+		(1UL<<SH_PTC_0_START_SHFT);
+
+	ptc0 = (long*)GLOBAL_MMR_ADDR(0, SH_PTC_0);
+	ptc1 = (long*)GLOBAL_MMR_ADDR(0, SH_PTC_1);
+	do {
+		*(piows+1) = -1;	/* use alias address to clear bits*/
+		next = start;
+		do {
+			for (cnode = 0; cnode < numnodes; cnode++) {
+				nasid = cnodeid_to_nasid(cnode);
+				ptc0 = CHANGE_NASID(nasid, ptc0);
+				ptc1 = CHANGE_NASID(nasid, ptc1);
+				data1 = next | (1UL<<SH_PTC_1_START_SHFT);
+				*ptc0 = data0;
+				*ptc1 = data1;
+			}
+			next += (1UL << nbits);
+		} while (next < end);
+
+		while ((ws = *piows) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK)
+			;
+
+	} while (ws & SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK);
+
+	
+}
+
+/**
+ * sn_send_IPI_phys - send an IPI to a Nasid and slice
+ * @physid: physical cpuid to receive the interrupt.
+ * @vector: command to send
+ * @delivery_mode: delivery mechanism
+ *
+ * Sends an IPI (interprocessor interrupt) to the processor specified by
+ * @physid
+ *
+ * @delivery_mode can be one of the following
+ *
+ * %IA64_IPI_DM_INT - pend an interrupt
+ * %IA64_IPI_DM_PMI - pend a PMI
+ * %IA64_IPI_DM_NMI - pend an NMI
+ * %IA64_IPI_DM_INIT - pend an INIT interrupt
+ */
+void
+sn_send_IPI_phys(long physid, int vector, int delivery_mode)
+{
+	long		nasid, slice;
+	long		*p, val;
+
+	nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+	p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT);
+	val =   (1UL<<SH_IPI_INT_SEND_SHFT) | 
+		(physid<<SH_IPI_INT_PID_SHFT) | 
+	        ((long)delivery_mode<<SH_IPI_INT_TYPE_SHFT) | 
+		((long)vector<<SH_IPI_INT_IDX_SHFT) |
+		(0x000feeUL<<SH_IPI_INT_BASE_SHFT);
+
+#if defined(BRINGUP)
+	{
+	static int count=0;
+	if (count++ < 10) printk("ZZ sendIPI 0x%x vec %d, nasid 0x%lx, slice %ld, adr 0x%lx, val 0x%lx\n",
+		smp_processor_id(), vector, nasid, slice, (long)p, val);
+	}
+#endif
+	mb();
+	*p = val;
+	
+}
+
+/**
+ * sn2_send_IPI - send an IPI to a processor
+ * @cpuid: target of the IPI
+ * @vector: command to send
+ * @delivery_mode: delivery mechanism
+ * @redirect: redirect the IPI?
+ *
+ * Sends an IPI (InterProcessor Interrupt) to the processor specified by
+ * @cpuid.  @vector specifies the command to send, while @delivery_mode can 
+ * be one of the following
+ *
+ * %IA64_IPI_DM_INT - pend an interrupt
+ * %IA64_IPI_DM_PMI - pend a PMI
+ * %IA64_IPI_DM_NMI - pend an NMI
+ * %IA64_IPI_DM_INIT - pend an INIT interrupt
+ */
+void
+sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
+{
+	long		physid;
+
+	physid = cpu_physical_id(cpuid);
+
+	sn_send_IPI_phys(physid, vector, delivery_mode);
+}
+
+
+/**
+ * init_sn2_smp_config - initialize SN2 smp configuration
+ *
+ * currently a NOP.
+ */
+void __init
+init_sn2_smp_config(void)
+{
+
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn_asm.S linux/arch/ia64/sn/kernel/sn_asm.S
--- linux.orig/arch/ia64/sn/kernel/sn_asm.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn_asm.S	2002-08-01 06:42:30.000000000 +0000
@@ -0,0 +1,148 @@
+
+/*
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+
+// Testing only.
+// Routine will cause MCAs
+//   zzzmsa(n)
+//      n=0 MCA via duplicate TLB dropin
+//      n=0 MCA via read of garbage address
+//
+
+#define ITIR(key, ps)           ((key<<8) | (ps<<2))
+#define TLB_PAGESIZE            28                      // Use 256MB pages for now.
+
+                        .global zzzmca
+                        .proc   zzzmca
+zzzmca:
+                        alloc   loc4       = ar.pfs,2,8,1,0;;
+                        cmp.ne  p6,p0=r32,r0;;
+                        movl    r2=0x2dead
+                        movl    r3=0x3dead
+                        movl    r15=0x15dead
+                        movl    r16=0x16dead
+                        movl    r31=0x31dead
+                        movl    loc0=0x34beef
+                        movl    loc1=0x35beef
+                        movl    loc2=0x36beef
+                        movl    loc3=0x37beef
+                        movl    out0=0x42beef
+
+                        movl    r20=0x32feed;;
+                        mov     ar32=r20
+                        movl    r20=0x36feed;;
+                        mov     ar36=r20
+                        movl    r20=0x65feed;;
+                        mov     ar65=r20
+                        movl    r20=0x66feed;;
+                        mov     ar66=r20
+
+(p6)                    br.cond.sptk    1f
+
+                        rsm      0x2000;;
+                        srlz.d;
+                        mov      r11      = 1
+                        mov      r3       = ITIR(0,TLB_PAGESIZE);;
+                        mov      cr.itir  = r3
+                        mov      r10      = 0;;
+                        itr.d    dtr[r11] = r10;;
+                        mov      r11      = 2
+
+                        itr.d    dtr[r11] = r10;;
+                        br      9f
+
+1:                      movl    r8=0xfe00000048;;
+                        ld8     r9=[r8];;
+                        mf
+                        mf.a
+                        srlz.d
+
+9:                      mov     ar.pfs=loc4
+                        br.ret.sptk     rp
+
+                        .endp   zzzmca
+
+                        .global zzzspec
+                        .proc   zzzspec
+zzzspec:
+			mov	r8=r32
+			movl	r9=0xe000000000000000
+			movl	r10=0x4000;;
+			ld8.s	r16=[r8];;
+			ld8.s	r17=[r9];;
+			add	r8=r8,r10;;
+			ld8.s	r18=[r8];;
+			add	r8=r8,r10;;
+			ld8.s	r19=[r8];;
+			add	r8=r8,r10;;
+			ld8.s	r20=[r8];;
+			mov	r8=r0
+			tnat.nz	p6,p0=r16
+			tnat.nz	p7,p0=r17
+			tnat.nz	p8,p0=r18
+			tnat.nz	p9,p0=r19
+			tnat.nz	p10,p0=r20;;
+		(p6)	dep	r8=-1,r8,0,1;;
+		(p7)	dep	r8=-1,r8,1,1;;
+		(p8)	dep	r8=-1,r8,2,1;;
+		(p9)	dep	r8=-1,r8,3,1;;
+		(p10)	dep	r8=-1,r8,4,1;;
+                        br.ret.sptk     rp
+                        .endp   zzzspec
+
+                        .global zzzspec2
+                        .proc   zzzspec2
+zzzspec2:
+			cmp.eq	p6,p7=r2,r2
+			movl	r16=0xc0000a0001000020
+			;;
+			mf
+			;;
+			ld8	r9=[r16]
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			ld8	r9=[r16];;
+			cmp.ne	p6,p7=r9,r16
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			ld8	r9=[r33];;
+			cmp.ne	p6,p7=r9,r33
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			tpa	r23=r32
+			add	r20=512,r33
+			add	r21=1024,r33;;
+			ld8	r9=[r20]
+			ld8	r10=[r21];;
+			nop.i	0
+			{ .mib
+			nop.m 0
+			cmp.ne	p6,p7=r10,r33
+		(p6)	br.spnt	1f
+			}
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+			br.ret.sptk     rp
+
+                        .endp   zzzspec
+
+#endif
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sn_ksyms.c linux/arch/ia64/sn/kernel/sn_ksyms.c
--- linux.orig/arch/ia64/sn/kernel/sn_ksyms.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sn_ksyms.c	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,67 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+/*
+ * Architecture-specific kernel symbols
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <asm/machvec.h>
+#include <asm/sn/intr.h>
+
+/*
+ * other stuff (more to be added later, cleanup then)
+ */
+EXPORT_SYMBOL(sn_pci_map_sg);
+EXPORT_SYMBOL(sn_pci_unmap_sg);
+EXPORT_SYMBOL(sn_pci_alloc_consistent);
+EXPORT_SYMBOL(sn_pci_free_consistent);
+EXPORT_SYMBOL(sn_dma_address);
+
+#include <linux/mm.h>
+#include <linux/devfs_fs_kernel.h>
+extern devfs_handle_t          base_io_scsi_ctlr_vhdl[];
+#include <asm/sn/types.h>
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+#include <asm/sn/arch.h>
+EXPORT_SYMBOL(base_io_scsi_ctlr_vhdl);
+EXPORT_SYMBOL(master_node_get);
+
+
+/*
+ * symbols referenced by the PCIBA module
+ */
+#include <asm/sn/invent.h>
+#include <asm/sn/hack.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/pci/pciio.h>
+
+devfs_handle_t
+devfn_to_vertex(unsigned char busnum, unsigned int devfn);
+EXPORT_SYMBOL(devfn_to_vertex);
+EXPORT_SYMBOL(hwgraph_vertex_unref);
+EXPORT_SYMBOL(pciio_config_get);
+EXPORT_SYMBOL(pciio_info_slot_get);
+EXPORT_SYMBOL(hwgraph_edge_add);
+EXPORT_SYMBOL(pciio_info_master_get);
+EXPORT_SYMBOL(pciio_info_get);
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+EXPORT_SYMBOL(__pa_debug);
+EXPORT_SYMBOL(__va_debug);
+#endif
+
+/* Support IPIs for loaded modules. */
+EXPORT_SYMBOL(sn_send_IPI_phys);
+
+#include <linux/mmzone.h>
+EXPORT_SYMBOL(sn_pci_unmap_single);
+EXPORT_SYMBOL(sn_pci_map_single);
+EXPORT_SYMBOL(sn_pci_dma_sync_single);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/kernel/sv.c linux/arch/ia64/sn/kernel/sv.c
--- linux.orig/arch/ia64/sn/kernel/sv.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/ia64/sn/kernel/sv.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,552 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved
+ *
+ * This implemenation of synchronization variables is heavily based on
+ * one done by Steve Lord <lord@sgi.com>
+ *
+ * Paul Cassella <pwc@sgi.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/semaphore.h>
+#include <asm/hardirq.h>
+#include <asm/softirq.h>
+#include <asm/current.h>
+
+#include <asm/sn/sv.h>
+
+/* Define this to have sv_test() run some simple tests.
+   kernel_thread() must behave as expected when this is called.  */
+#undef RUN_SV_TEST
+
+#define DEBUG
+
+/* Set up some macros so sv_wait(), sv_signal(), and sv_broadcast()
+   can sanity check interrupt state on architectures where we know
+   how. */
+#ifdef DEBUG
+ #define SV_DEBUG_INTERRUPT_STATE
+ #ifdef __mips64
+  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x1) != 0)
+  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x1) == 0)
+  #define SV_INTERRUPT_TEST_WORKERS 31
+ #elif defined(__ia64)
+  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x4000) != 0)
+  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x4000) == 0)
+  #define SV_INTERRUPT_TEST_WORKERS 4 /* simulator's slow */
+ #else
+  #undef  SV_DEBUG_INTERRUPT_STATE
+  #define SV_INTERRUPT_TEST_WORKERS 4 /* reasonable? default. */
+ #endif /* __mips64 */
+#endif /* DEBUG */
+
+
+/* XXX FIXME hack hack hack.  Our mips64 tree is from before the
+   switch to WQ_FLAG_EXCLUSIVE, and our ia64 tree is from after it. */
+#ifdef TASK_EXCLUSIVE
+  #undef EXCLUSIVE_IN_QUEUE
+#else
+  #define EXCLUSIVE_IN_QUEUE
+  #define TASK_EXCLUSIVE 0 /* for the set_current_state() in sv_wait() */
+#endif
+
+
+static inline void sv_lock(sv_t *sv) {
+	spin_lock(&sv->sv_lock);
+}
+
+static inline void sv_unlock(sv_t *sv) {
+	spin_unlock(&sv->sv_lock);
+}
+
+/* up() is "extern inline", so we can't pass its address to sv_wait.
+   Use this function's address instead. */
+static void up_wrapper(struct semaphore *sem) {
+	up(sem);
+}
+
+/* spin_unlock() is sometimes a macro. */
+static void spin_unlock_wrapper(spinlock_t *s) {
+	spin_unlock(s);
+}
+
+/* XXX Perhaps sv_wait() should do the switch() each time and avoid
+   the extra indirection and the need for the _wrapper functions? */
+
+static inline void sv_set_mon_type(sv_t *sv, int type) {
+	switch (type) {
+	case SV_MON_SPIN:
+		sv->sv_mon_unlock_func =
+		  (sv_mon_unlock_func_t)spin_unlock_wrapper;
+		break;
+	case SV_MON_SEMA:
+		sv->sv_mon_unlock_func =
+		  (sv_mon_unlock_func_t)up_wrapper;
+		if(sv->sv_flags & SV_INTS) {
+			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
+			       "cannot be shared with interrupts if it is a "
+			       "semaphore!\n");
+			BUG();
+		}
+		if(sv->sv_flags & SV_BHS) {
+			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
+			       "cannot be shared with bottom-halves if it is "
+			       "a semaphore!\n");
+			BUG();
+		}
+		break;
+#if 0 
+	/*
+	 * If needed, and will need to think about interrupts.  This
+	 * may be needed, for example, if someone wants to use sv's
+	 * with something like dev_base; writers need to hold two
+	 * locks. 
+	 */
+	case SV_MON_CUSTOM: 
+		{
+		struct sv_mon_custom *c = lock;
+		sv->sv_mon_unlock_func = c->sv_mon_unlock_func;
+		sv->sv_mon_lock        = c->sv_mon_lock;
+		break;
+		}
+#endif
+		
+	default:
+		printk(KERN_ERR "sv_set_mon_type: unknown type %d (0x%x)! "
+		       "(flags 0x%x)\n", type, type, sv->sv_flags);
+		BUG();
+		break;
+	}
+	sv->sv_flags |= type;
+}
+
+static inline void sv_set_ord(sv_t *sv, int ord) {
+	if (!ord)
+		ord = SV_ORDER_DEFAULT;
+
+	if (ord != SV_ORDER_FIFO && ord != SV_ORDER_LIFO) {
+		printk(KERN_EMERG "sv_set_ord: unknown order %d (0x%x)! ",
+		       ord, ord);
+		BUG();
+	}
+
+	sv->sv_flags |= ord;
+}
+
+void sv_init(sv_t *sv, sv_mon_lock_t *lock, int flags) 
+{
+	int ord = flags & SV_ORDER_MASK;
+	int type = flags & SV_MON_MASK;
+
+	/* Copy all non-order, non-type flags */
+	sv->sv_flags = (flags & ~(SV_ORDER_MASK | SV_MON_MASK));
+
+	if((sv->sv_flags & (SV_INTS | SV_BHS)) == (SV_INTS | SV_BHS)) {
+	  printk(KERN_ERR "sv_init: do not set both SV_INTS and SV_BHS, only SV_INTS.\n");
+	  BUG();
+	}
+
+	sv_set_ord(sv, ord);
+	sv_set_mon_type(sv, type);
+
+	/* If lock is NULL, we'll get it from sv_wait_compat() (and
+           ignore it in sv_signal() and sv_broadcast()). */
+	sv->sv_mon_lock = lock;
+
+	spin_lock_init(&sv->sv_lock);
+	init_waitqueue_head(&sv->sv_waiters);
+}
+
+/*
+ * The associated lock must be locked on entry.  It is unlocked on return.
+ *
+ * Return values:
+ *
+ * n < 0 : interrupted,  -n jiffies remaining on timeout, or -1 if timeout == 0
+ * n = 0 : timeout expired
+ * n > 0 : sv_signal()'d, n jiffies remaining on timeout, or 1 if timeout == 0
+ */
+signed long sv_wait(sv_t *sv, int sv_wait_flags, unsigned long timeout) 
+{
+	DECLARE_WAITQUEUE( wait, current );
+	unsigned long flags;
+	signed long ret = 0;
+
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	{
+	unsigned long flags;
+	__save_flags(flags);
+
+	if(sv->sv_flags & SV_INTS) {
+		if(SV_TEST_INTERRUPTS_ENABLED(flags)) {
+			printk(KERN_ERR "sv_wait: SV_INTS and interrupts "
+			       "enabled (flags: 0x%lx)\n", flags);
+			BUG();
+		}
+	} else {
+		if (SV_TEST_INTERRUPTS_DISABLED(flags)) {
+			printk(KERN_WARNING "sv_wait: !SV_INTS and interrupts "
+			       "disabled! (flags: 0x%lx)\n", flags);
+		}
+	}
+	}
+#endif  /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+
+	sv->sv_mon_unlock_func(sv->sv_mon_lock);
+
+	/* Add ourselves to the wait queue and set the state before
+	 * releasing the sv_lock so as to avoid racing with the
+	 * wake_up() in sv_signal() and sv_broadcast(). 
+	 */
+
+	/* don't need the _irqsave part, but there is no wq_write_lock() */
+	wq_write_lock_irqsave(&sv->sv_waiters.lock, flags);
+
+#ifdef EXCLUSIVE_IN_QUEUE
+	wait.flags |= WQ_FLAG_EXCLUSIVE;
+#endif
+
+	switch(sv->sv_flags & SV_ORDER_MASK) {
+	case SV_ORDER_FIFO:
+		__add_wait_queue_tail(&sv->sv_waiters, &wait);
+		break;
+	case SV_ORDER_FILO:
+		__add_wait_queue(&sv->sv_waiters, &wait);
+		break;
+	default:
+		printk(KERN_ERR "sv_wait: unknown order!  (sv: 0x%p, flags: 0x%x)\n",
+					(void *)sv, sv->sv_flags);
+		BUG();
+	}
+	wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags);
+
+	if(sv_wait_flags & SV_WAIT_SIG)
+		set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE  );
+	else
+		set_current_state(TASK_EXCLUSIVE | TASK_UNINTERRUPTIBLE);
+
+	spin_unlock(&sv->sv_lock);
+
+	if(sv->sv_flags & SV_INTS)
+		local_irq_enable();
+	else if(sv->sv_flags & SV_BHS)
+		local_bh_enable();
+
+	if (timeout)
+		ret = schedule_timeout(timeout);
+	else
+		schedule();
+
+	if(current->state != TASK_RUNNING) /* XXX Is this possible? */ {
+		printk(KERN_ERR "sv_wait: state not TASK_RUNNING after "
+		       "schedule().\n");
+		set_current_state(TASK_RUNNING);
+	}
+
+	remove_wait_queue(&sv->sv_waiters, &wait);
+
+	/* Return cases:
+	   - woken by a sv_signal/sv_broadcast
+	   - woken by a signal
+	   - woken by timeout expiring
+	*/
+
+	/* XXX This isn't really accurate; we may have been woken
+           before the signal anyway.... */
+	if(signal_pending(current))
+		return timeout ? -ret : -1;
+	return timeout ? ret : 1;
+}
+
+
+void sv_signal(sv_t *sv) 
+{
+	/* If interrupts can acquire this lock, they can also acquire the
+	   sv_mon_lock, which we must already have to have called this, so
+	   interrupts must be disabled already.  If interrupts cannot
+	   contend for this lock, we don't have to worry about it. */
+
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	if(sv->sv_flags & SV_INTS) {
+		unsigned long flags;
+		__save_flags(flags);
+		if(SV_TEST_INTERRUPTS_ENABLED(flags))
+			printk(KERN_ERR "sv_signal: SV_INTS and "
+			"interrupts enabled! (flags: 0x%lx)\n", flags);
+	}
+#endif /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+	wake_up(&sv->sv_waiters);
+	sv_unlock(sv);
+}
+
+void sv_broadcast(sv_t *sv) 
+{
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	if(sv->sv_flags & SV_INTS) {
+		unsigned long flags;
+		__save_flags(flags);
+		if(SV_TEST_INTERRUPTS_ENABLED(flags))
+			printk(KERN_ERR "sv_broadcast: SV_INTS and "
+			       "interrupts enabled! (flags: 0x%lx)\n", flags);
+	}
+#endif /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+	wake_up_all(&sv->sv_waiters);
+	sv_unlock(sv);
+}
+
+void sv_destroy(sv_t *sv) 
+{
+	if(!spin_trylock(&sv->sv_lock)) {
+		printk(KERN_ERR "sv_destroy: someone else has sv 0x%p locked!\n", (void *)sv);
+		BUG();
+	}
+
+	/* XXX Check that the waitqueue is empty? 
+	       Mark the sv destroyed?
+	*/
+}
+
+
+#ifdef RUN_SV_TEST
+
+static DECLARE_MUTEX_LOCKED(talkback);
+static DECLARE_MUTEX_LOCKED(sem);
+sv_t sv;
+sv_t sv_filo;
+
+static int sv_test_1_w(void *arg) 
+{
+	printk("sv_test_1_w: acquiring spinlock 0x%p...\n", arg);
+
+	spin_lock((spinlock_t*)arg);
+	printk("sv_test_1_w: spinlock acquired, waking sv_test_1_s.\n");
+
+	up(&sem);
+
+	printk("sv_test_1_w: sv_spin_wait()'ing.\n");
+
+	sv_spin_wait(&sv, arg);
+
+	printk("sv_test_1_w: talkback.\n");
+	up(&talkback);
+
+	printk("sv_test_1_w: exiting.\n");
+	return 0;
+}
+
+static int sv_test_1_s(void *arg) 
+{
+	printk("sv_test_1_s: waiting for semaphore.\n");
+	down(&sem);
+	printk("sv_test_1_s: semaphore acquired.  Acquiring spinlock.\n");
+	spin_lock((spinlock_t*)arg);
+	printk("sv_test_1_s: spinlock acquired.  sv_signaling.\n");
+	sv_signal(&sv);
+	printk("sv_test_1_s: talkback.\n");
+	up(&talkback);
+	printk("sv_test_1_s: exiting.\n");
+	return 0;
+
+}
+
+static int count;
+static DECLARE_MUTEX(monitor);
+
+static int sv_test_2_w(void *arg) 
+{
+	int dummy = count++;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	up(&talkback);
+	printk("sv_test_2_w: thread %d started, sv_waiting.\n", dummy);
+	sv_sema_wait(sv, &monitor);
+	printk("sv_test_2_w: thread %d woken, exiting.\n", dummy);
+	up(&sem);
+	return 0;
+}
+
+static int sv_test_2_s_1(void *arg) 
+{
+	int i;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	for(i = 0; i < 3; i++) {
+		printk("sv_test_2_s_1: waking one thread.\n");
+		sv_signal(sv);
+		down(&sem);
+	}
+
+	printk("sv_test_2_s_1: signaling and broadcasting again.  Nothing should happen.\n");
+	sv_signal(sv);
+	sv_broadcast(sv);
+	sv_signal(sv);
+	sv_broadcast(sv);
+
+	printk("sv_test_2_s_1: talkbacking.\n");
+	up(&talkback);
+	up(&monitor);
+	return 0;
+}
+
+static int sv_test_2_s(void *arg) 
+{
+	int i;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	for(i = 0; i < 3; i++) {
+		printk("sv_test_2_s: waking one thread (should be %d.)\n", i);
+		sv_signal(sv);
+		down(&sem);
+	}
+
+	printk("sv_test_3_s: waking remaining threads with broadcast.\n");
+	sv_broadcast(sv);
+	for(; i < 10; i++)
+		down(&sem);
+
+	printk("sv_test_3_s: sending talkback.\n");
+	up(&talkback);
+
+	printk("sv_test_3_s: exiting.\n");
+	up(&monitor);
+	return 0;
+}
+
+
+static void big_test(sv_t *sv) 
+{
+	int i;
+
+	count = 0;
+
+	for(i = 0; i < 3; i++) {
+		printk("big_test: spawning thread %d.\n", i);
+		kernel_thread(sv_test_2_w, sv, 0);
+		down(&talkback);
+	}
+
+	printk("big_test: spawning first wake-up thread.\n");
+	kernel_thread(sv_test_2_s_1, sv, 0);
+
+	down(&talkback);
+	printk("big_test: talkback happened.\n");
+
+
+	for(i = 3; i < 13; i++) {
+		printk("big_test: spawning thread %d.\n", i);
+		kernel_thread(sv_test_2_w, sv, 0);
+		down(&talkback);
+	}
+
+	printk("big_test: spawning wake-up thread.\n");
+	kernel_thread(sv_test_2_s, sv, 0);
+
+	down(&talkback);
+}
+
+sv_t int_test_sv;
+spinlock_t int_test_spin = SPIN_LOCK_UNLOCKED;
+int int_test_ready;
+static int irqtestcount;
+
+static int interrupt_test_worker(void *unused) 
+{
+	int id = ++irqtestcount;
+	int it = 0;
+			unsigned long flags, flags2;
+
+	printk("ITW: thread %d started.\n", id);
+
+	while(1) {
+		__save_flags(flags2);
+		if(jiffies % 3) {
+			printk("ITW %2d %5d: irqsaving          (%lx)\n", id, it, flags2);
+			spin_lock_irqsave(&int_test_spin, flags);
+		} else {
+			printk("ITW %2d %5d: spin_lock_irqing   (%lx)\n", id, it, flags2);
+			spin_lock_irq(&int_test_spin);
+		}
+
+		__save_flags(flags2);
+		printk("ITW %2d %5d: locked, sv_waiting (%lx).\n", id, it, flags2);
+		sv_wait(&int_test_sv, 0, 0);
+
+		__save_flags(flags2);
+		printk("ITW %2d %5d: wait finished      (%lx), pausing\n", id, it, flags2);
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(jiffies & 0xf);
+		if(current->state != TASK_RUNNING)
+		  printk("ITW:  current->state isn't RUNNING after schedule!\n");
+		it++;
+	}
+}
+
+static void interrupt_test(void) 
+{
+	int i;
+
+	printk("interrupt_test: initing sv.\n");
+	sv_init(&int_test_sv, &int_test_spin, SV_MON_SPIN | SV_INTS);
+
+	for(i = 0; i < SV_INTERRUPT_TEST_WORKERS; i++) {
+		printk("interrupt_test: starting test thread %d.\n", i);
+		kernel_thread(interrupt_test_worker, 0, 0);
+	}
+	printk("interrupt_test: done with init part.\n");
+	int_test_ready = 1;
+}
+
+int sv_test(void) 
+{
+	spinlock_t s = SPIN_LOCK_UNLOCKED;
+
+	sv_init(&sv, &s, SV_MON_SPIN);
+	printk("sv_test: starting sv_test_1_w.\n");
+	kernel_thread(sv_test_1_w, &s, 0);
+	printk("sv_test: starting sv_test_1_s.\n");
+	kernel_thread(sv_test_1_s, &s, 0);
+
+	printk("sv_test: waiting for talkback.\n");
+	down(&talkback); down(&talkback);
+	printk("sv_test: talkback happened, sv_destroying.\n");
+	sv_destroy(&sv);
+
+	count = 0;
+
+	printk("sv_test: beginning big_test on sv.\n");
+
+	sv_init(&sv, &monitor, SV_MON_SEMA);
+	big_test(&sv);
+	sv_destroy(&sv);
+
+	printk("sv_test: beginning big_test on sv_filo.\n");
+	sv_init(&sv_filo, &monitor, SV_MON_SEMA | SV_ORDER_FILO);
+	big_test(&sv_filo);
+	sv_destroy(&sv_filo);
+
+	interrupt_test();
+
+	printk("sv_test: done.\n");
+	return 0;
+}
+
+__initcall(sv_test);
+
+#endif /* RUN_SV_TEST */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/Makefile linux/arch/ia64/sn/sn1/Makefile
--- linux.orig/arch/ia64/sn/sn1/Makefile	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,31 +0,0 @@
-#
-# ia64/platform/sn/sn1/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
-
-.S.s:
-	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
-.S.o:
-	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
-
-all: sn1.a
-
-O_TARGET        = sn1.a
-
-obj-y          = irq.o setup.o iomv.o mm.o smp.o synergy.o sn1_asm.o \
-		discontig.o probe.o error.o sv.o
-
-obj-$(CONFIG_IA64_SGI_AUTOTEST)	+= llsc4.o
-obj-$(CONFIG_IA64_GENERIC)	+= machvec.o
-obj-$(CONFIG_MODULES)		+= sn1_ksyms.o
-
-clean::
-
-include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/discontig.c linux/arch/ia64/sn/sn1/discontig.c
--- linux.orig/arch/ia64/sn/sn1/discontig.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/discontig.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,159 +0,0 @@
-/*
- * Copyright 2000, Silicon Graphics, sprasad@engr.sgi.com
- * Copyright 2000, Kanoj Sarcar, kanoj@sgi.com
- */
-
-/*
- * Contains common definitions and globals for NUMA platform
- * support. For now, SN-IA64 and SN-MIPS are the NUMA platforms.
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/sn/mmzone.h>
-#include <asm/efi.h>
-
-extern int numnodes ;
-
-plat_pg_data_t plat_node_data[MAXNODES];
-bootmem_data_t bdata[MAXNODES];
-int chunktonid[MAXCHUNKS];
-int nasid_map[MAXNASIDS];
-
-void __init
-init_chunktonid(void)
-{
-	memset(chunktonid, -1, sizeof(chunktonid)) ;
-}
-
-void __init
-init_nodeidmap(void)
-{
-	memset(nasid_map, -1, sizeof(nasid_map)) ;
-}
-
-int		cnodeid_map[MAXNODES] ;
-void __init
-init_cnodeidmap(void)
-{
-	memset(cnodeid_map, -1, sizeof(cnodeid_map)) ;
-}
-
-int
-numa_debug(void)
-{
-       panic("NUMA debug\n");
-       return(0);
-}
-
-int __init
-build_cnodeid_map(void)
-{
-	int	i,j ;
-
-	for (i=0,j=0;i<MAXNASIDS;i++) {
-		if (nasid_map[i] >= 0)
-			cnodeid_map[j++] = i ;
-	}
-	return j ;
-}
-
-/*
- * Since efi_memmap_walk merges contiguous banks, this code will need
- * to find all the nasids covered by the input memory descriptor.
- */
-static int __init
-build_nasid_map(unsigned long start, unsigned long end, void *arg)
-{
-	unsigned long vaddr = start;
-	int nasid = GetNasId(__pa(vaddr));
-
-	while (vaddr < end) {
-		if (nasid < MAXNASIDS)
-			nasid_map[nasid] = 0;
-		else
-			panic("build_nasid_map");
-		vaddr = (unsigned long)__va((unsigned long)(++nasid) << 
-							SN1_NODE_ADDR_SHIFT);
-	}
-	return 0;
-}
-
-void __init
-fix_nasid_map(void)
-{
-	int	i ;
-	int		j ;
-
-	/* For every nasid */
-	for (j=0;j<MAXNASIDS;j++) {
-		for (i=0;i<MAXNODES;i++) {
-			if (CNODEID_TO_NASID(i) == j)
-				break ;
-		}
-		if (i<MAXNODES)
-			nasid_map[j] = i ;
-	}
-}
-
-static void __init
-dump_bootmem_info(void)
-{
-        int     i;
-        struct bootmem_data *bdata ;
-
-	printk("CNODE INFO ....\n") ;
-        for (i=0;i<numnodes;i++) {
-		printk("%d ", CNODEID_TO_NASID(i)) ;
-	}
-	printk("\n") ;
-
-	printk("BOOT MEM INFO ....\n") ;
-        printk("Node   Start                LowPfn               BootmemMap\n") ;
-        for (i=0;i<numnodes;i++) {
-                bdata = NODE_DATA(i)->bdata ;
-                printk("%d      0x%016lx   0x%016lx   0x%016lx\n", i,
-                        bdata->node_boot_start, bdata->node_low_pfn,
-                        (unsigned long)bdata->node_bootmem_map) ;
-        }
-}
-
-void __init
-discontig_mem_init(void)
-{
-	extern void setup_sn1_bootmem(int);
-	int		maxnodes ;
-
-        init_chunktonid() ;
-	init_nodeidmap() ;
-	init_cnodeidmap() ;
-	efi_memmap_walk(build_nasid_map, 0) ;
-	maxnodes = build_cnodeid_map() ;
-	fix_nasid_map() ;
-#ifdef CONFIG_DISCONTIGMEM
-	setup_sn1_bootmem(maxnodes) ;
-#endif
-	numnodes = maxnodes;
-	dump_bootmem_info() ;
-}
-
-void
-dump_node_data(void)
-{
-        int     i;
-
-	printk("NODE DATA ....\n") ;
-	printk("Node, Start, Size, MemMap, BitMap, StartP, Mapnr, Size, Id\n") ;
-        for (i=0;i<numnodes;i++) {
-		printk("%d, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, %d\n", 
-			CNODEID_TO_NASID(i), NODE_START(i), NODE_SIZE(i), 
-			(long)NODE_MEM_MAP(i), (long)NODE_DATA(i)->valid_addr_bitmap, 
-			NODE_DATA(i)->node_start_paddr, 
-			NODE_DATA(i)->node_start_mapnr,
-			NODE_DATA(i)->node_size,
-			NODE_DATA(i)->node_id)  ;
-	}
-}
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/error.c linux/arch/ia64/sn/sn1/error.c
--- linux.orig/arch/ia64/sn/sn1/error.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/error.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,149 +0,0 @@
-
-
-/*
- * SN1 Platform specific error Support
- *
- * Copyright (C) 2001 Silicon Graphics, Inc.
- * Copyright (C) 2001 Alan Mayer (ajm@sgi.com)
- */
-
-
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-
-#include <asm/ptrace.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/smp.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-
-void
-snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs) {
-	unsigned long long intpend_val;
-	unsigned long long bit;
-
-	switch (irq) {
-	case SGI_UART_IRQ:
-		// This isn't really an error interrupt.  We're just
-		// here because we have to do something with them.
-		// This is probably wrong, and this code will be
-		// removed.
-		intpend_val = LOCAL_HUB_L(PI_INT_PEND0);
-		if ( (bit = ~(1L<<GFX_INTR_A)) ==
-			(intpend_val & ~(1L<<GFX_INTR_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<GFX_INTR_B)) ==
-			(intpend_val & ~(1L<<GFX_INTR_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<PG_MIG_INTR)) ==
-			(intpend_val & ~(1L<<PG_MIG_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<UART_INTR)) ==
-			(intpend_val & ~(1L<<UART_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<CC_PEND_A)) ==
-			(intpend_val & ~(1L<<CC_PEND_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<CC_PEND_B)) ==
-			(intpend_val & ~(1L<<CC_PEND_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		printk("Received SGI_UART_IRQ (65), but no intpend0 bits were set???\n");
-		return;
-	case SGI_HUB_ERROR_IRQ:
-		// These are mostly error interrupts of various
-		// sorts.  We need to do more than panic here, but
-		// what the heck, this is bring up.
-		intpend_val = LOCAL_HUB_L(PI_INT_PEND1);
-		
-		if ( (bit = ~(1L<<XB_ERROR)) ==
-			(intpend_val & ~(1L<<XB_ERROR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED XB_ERROR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<LB_ERROR)) ==
-			(intpend_val & ~(1L<<LB_ERROR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED LB_ERROR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NACK_INT_A)) ==
-			(intpend_val & ~(1L<<NACK_INT_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NACK_INT_A on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NACK_INT_B)) ==
-			(intpend_val & ~(1L<<NACK_INT_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NACK_INT_B on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<CLK_ERR_INTR)) ==
-			(intpend_val & ~(1L<<CLK_ERR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED CLK_ERR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<COR_ERR_INTR_A)) ==
-			(intpend_val & ~(1L<<COR_ERR_INTR_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED COR_ERR_INTR_A on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<COR_ERR_INTR_B)) ==
-			(intpend_val & ~(1L<<COR_ERR_INTR_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED COR_ERR_INTR_B on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<MD_COR_ERR_INTR)) ==
-			(intpend_val & ~(1L<<MD_COR_ERR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED MD_COR_ERR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NI_ERROR_INTR)) ==
-			(intpend_val & ~(1L<<NI_ERROR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NI_ERROR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<MSC_PANIC_INTR)) ==
-			(intpend_val & ~(1L<<MSC_PANIC_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED MSC_PANIC_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		printk("Received SGI_XB_ERROR_IRQ (182) but no intpend1 bits are set???\n");
-		return;
-	default:
-		printk("Received invalid irq in snia_error_intr_handler()/n");
-	}
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/iomv.c linux/arch/ia64/sn/sn1/iomv.c
--- linux.orig/arch/ia64/sn/sn1/iomv.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/iomv.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,97 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <asm/io.h>
-#include <linux/pci.h>
-
-static inline void *
-sn1_io_addr(unsigned long port)
-{
-	if (!IS_RUNNING_ON_SIMULATOR()) {
-		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
-	} else {
-		unsigned long io_base;
-		unsigned long addr;
- 
-		/*
- 		 * word align port, but need more than 10 bits
- 		 * for accessing registers in bedrock local block
- 		 * (so we don't do port&0xfff)
- 		 */
-		if (port >= 0x1f0 && port <= 0x1f7 ||
-			port == 0x3f6 || port == 0x3f7) {
-			io_base = __IA64_UNCACHED_OFFSET | 0x00000FFFFC000000;
-			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
-		} else {
-			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
-		}
-		return(void *) addr;
-	}
-}
-
-unsigned int
-sn1_inb (unsigned long port)
-{
-	volatile unsigned char *addr = sn1_io_addr(port);
-	unsigned char ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-unsigned int
-sn1_inw (unsigned long port)
-{
-	volatile unsigned short *addr = sn1_io_addr(port);
-	unsigned short ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-unsigned int
-sn1_inl (unsigned long port)
-{
-	volatile unsigned int *addr = sn1_io_addr(port);
-	unsigned int ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-void
-sn1_outb (unsigned char val, unsigned long port)
-{
-	volatile unsigned char *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
-
-void
-sn1_outw (unsigned short val, unsigned long port)
-{
-	volatile unsigned short *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
-
-void
-sn1_outl (unsigned int val, unsigned long port)
-{
-	volatile unsigned int *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/irq.c linux/arch/ia64/sn/sn1/irq.c
--- linux.orig/arch/ia64/sn/sn1/irq.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/irq.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,183 +0,0 @@
-/*
- * Platform dependent support for SGI SN1
- *
- * Copyright (C) 2000   Silicon Graphics
- * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
- * Copyright (C) 2000   Alan Mayer (ajm@sgi.com)
- * Copyright (C) 2000   Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <asm/current.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/types.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pciio_private.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn1/addrs.h>
-#include <asm/sn/iobus.h>
-#include <asm/sn/sn1/arch.h>
-#include <asm/sn/synergy.h>
-
-#define IRQ_BIT_OFFSET 64
-
-int bit_pos_to_irq(int bit)
-{
-	if (bit > 118)
-		bit = 118;
-	return (bit + IRQ_BIT_OFFSET);
-}
-
-static inline int irq_to_bit_pos(int irq)
-{
-	int bit = irq - IRQ_BIT_OFFSET;
-
-	if (bit > 63)
-		bit -= 64;
-	return bit;
-}
-
-static unsigned int
-sn1_startup_irq(unsigned int irq)
-{
-        return(0);
-}
-
-static void
-sn1_shutdown_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_disable_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_enable_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_ack_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_end_irq(unsigned int irq)
-{
-	int bit;
-
-	bit = irq_to_bit_pos(irq);
-	LOCAL_HUB_CLR_INTR(bit);
-}
-
-static void
-sn1_set_affinity_irq(unsigned int irq, unsigned long mask)
-{
-}
-
-struct hw_interrupt_type irq_type_sn1 = {
-        "sn1_irq",
-        sn1_startup_irq,
-        sn1_shutdown_irq,
-        sn1_enable_irq,
-        sn1_disable_irq,
-        sn1_ack_irq,
-        sn1_end_irq,
-        sn1_set_affinity_irq
-};
-
-
-void
-sn1_irq_init (void)
-{
-	int i;
-
-	for (i = 0; i <= NR_IRQS; ++i) {
-		if (idesc_from_vector(i)->handler == &no_irq_type) {
-			idesc_from_vector(i)->handler = &irq_type_sn1;
-		}
-	}
-}
-
-
-
-#if !defined(CONFIG_IA64_SGI_SN1)
-void
-sn1_pci_fixup(int arg)
-{
-}
-#endif
-
-#ifdef CONFIG_PERCPU_IRQ
-
-extern irq_desc_t irq_descX[NR_IRQS];
-irq_desc_t *irq_desc_ptr[NR_CPUS] = { irq_descX };
-
-/*
- * Each slave AP allocates its own irq table.
- */
-int __init cpu_irq_init(void)
-{
-	irq_desc_ptr[smp_processor_id()] = (irq_desc_t *)kmalloc(sizeof(irq_descX), GFP_KERNEL);
-	if (irq_desc_ptr[smp_processor_id()] == 0)
-		return(-1);
-	memcpy(irq_desc_ptr[smp_processor_id()], irq_desc_ptr[0], 
-							sizeof(irq_descX));
-	return(0);
-}
-
-/*
- * This can also allocate the irq tables for the other cpus, specifically
- * on their nodes.
- */
-int __init master_irq_init(void)
-{
-	return(0);
-}
-
-/*
- * The input is an ivt level.
- */
-irq_desc_t *idesc_from_vector(unsigned int ivnum)
-{
-	return(irq_desc_ptr[smp_processor_id()] + ivnum);
-}
-
-/*
- * The input is a "soft" level, that we encoded in.
- */
-irq_desc_t *idesc_from_irq(unsigned int irq)
-{
-	return(irq_desc_ptr[irq >> 8] + (irq & 0xff));
-}
-
-unsigned int ivector_from_irq(unsigned int irq)
-{
-	return(irq & 0xff);
-}
-
-/*
- * This should return the Linux irq # for the i/p vector on the
- * i/p cpu. We currently do not track this.
- */
-unsigned int irq_from_cpuvector(int cpunum, unsigned int vector)
-{
-	return (vector);
-}
-
-#endif /* CONFIG_PERCPU_IRQ */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/llsc4.c linux/arch/ia64/sn/sn1/llsc4.c
--- linux.orig/arch/ia64/sn/sn1/llsc4.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/sn/sn1/llsc4.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,952 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <linux/kernel_stat.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <asm/efi.h>
-#include <asm/page.h>
-#include <linux/threads.h>
-
-extern void bringup_set_led_bits(u8 bits, u8 mask);
-
-#include "llsc4.h"
-
-
-#ifdef STANDALONE
-#include "lock.h"
-#endif
-
-#ifdef INTTEST
-static int	inttest=0;
-#endif
-
-/*
- * Test parameter table for AUTOTEST
- */
-typedef struct {
-	int	passes;
-	int	linecount;
-	int	linepad;
-} autotest_table_t;
-
-autotest_table_t autotest_table[] = {
-	{5000000,	2,	0x2b4		},
-	{5000000,	16,	0,		},
-	{5000000,	16,	4,		},
-	{5000000,	128,	0x44		},
-	{5000000,	128,	0x84		},
-	{5000000,	128,	0x200		},
-	{5000000,	128,	0x204		},
-	{5000000,	128,	0x2b4		},
-	{5000000,	2,	8*MB+0x2b4	},
-	{5000000,	16,	8*MB+0		},
-	{5000000,	16,	8*MB+4		},
-	{5000000,	128,	8*MB+0x44	},
-	{5000000,	128,	8*MB+0x84	},
-	{5000000,	128,	8*MB+0x200	},
-	{5000000,	128,	8*MB+0x204	},
-	{5000000,	128,	8*MB+0x2b4	},
-	{0}};
-
-/*
- * Array of virtual addresses available for test purposes.
- */
-
-typedef struct {
-	long	vstart;
-	long	vend;
-	long	nextaddr;
-	int	wrapcount;
-} memmap_t;
-
-memmap_t 	memmap[MAXCHUNKS];
-int		memmapx=0;
-
-typedef struct {
-	void	*addr;
-	long	data[16];
-	long	data_fc[16];
-} capture_line_t;
-
-typedef struct {
-	int	size;
-	void	*blockaddr;
-	void	*shadaddr;
-	long	blockdata[16];
-	long	shaddata[16];
-	long	blockdata_fc[16];
-	long	shaddata_fc[16];
-	long	synerr;
-} capture_t;
-
-/*
- * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and
- * the rest of the tables have to start at 1MB to skip PROM tables.
- */
-#define THREADPRIVATE(t)	((threadprivate_t*)(((long)mbase)+1024*1024+t*((sizeof(threadprivate_t)+511)/512*512)))
-
-#define k_capture		mbase->sk_capture
-#define k_go			mbase->sk_go
-#define k_linecount		mbase->sk_linecount
-#define k_passes		mbase->sk_passes
-#define k_napticks		mbase->sk_napticks
-#define k_stop_on_error		mbase->sk_stop_on_error
-#define k_verbose		mbase->sk_verbose
-#define k_threadprivate		mbase->sk_threadprivate
-#define k_blocks		mbase->sk_blocks
-#define k_iter_msg		mbase->sk_iter_msg
-#define k_vv			mbase->sk_vv
-#define k_linepad		mbase->sk_linepad
-#define k_options		mbase->sk_options
-#define k_testnumber		mbase->sk_testnumber
-#define k_currentpass		mbase->sk_currentpass
-
-static long		blocks[MAX_LINECOUNT];		/* addresses of data blocks */
-static control_t	*mbase;
-static vint		initialized=0;
-
-static unsigned int ran_conf_llsc(int);
-static int  rerr(capture_t *, char *, void *, void *, int, int, int, int, int, int);
-static void dumpline(void *, char *, char *, void *, void *, int);
-static int  checkstop(int, int, uint);
-static void spin(int);
-static void capturedata(capture_t *, uint, void *, void *, int);
-static int  randn(uint max, uint *seed);
-static uint zrandom (uint *zranseed);
-static int  set_lock(uint *, uint);
-static int  clr_lock(uint *, uint);
-static void Speedo(void);
-
-int autotest_enabled=0;
-static int llsctest_number=-1;
-static int errstop_enabled=0;
-static int fail_enabled=0;
-static int selective_trigger=0;
-static int dump_block_addrs_opt=0;
-static uint errlock=0;
-
-static int __init autotest_enable(char *str)
-{
-        autotest_enabled = 1;
-	return 1;
-}
-static int __init set_llscblkadr(char *str)
-{
-	dump_block_addrs_opt = 1;
-	return 1;
-}
-static int __init set_llscselt(char *str)
-{
-	selective_trigger = 1;
-	return 1;
-}
-static int __init set_llsctest(char *str)
-{
-        llsctest_number = simple_strtol(str, &str, 10);
-	if (llsctest_number < 0 || llsctest_number > 15)
-		llsctest_number = -1;
-	return 1;
-}
-static int __init set_llscerrstop(char *str)
-{
-        errstop_enabled = 1;
-	return 1;
-}
-static int __init set_llscfail(char *str)
-{
-        fail_enabled = 8;
-	return 1;
-}
-
-static void print_params(void)
-{
-	printk ("********* Enter AUTOTEST facility on master cpu *************\n");
-	printk ("  Test options:\n");
-	printk ("     llsctest=<n>\t%d\tTest number to run (all = -1)\n", llsctest_number);
-	printk ("     llscerrstop \t%s\tStop on error\n", errstop_enabled ? "on" : "off");
-	printk ("     llscfail    \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off");
-	printk ("     llscselt    \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off");
-	printk ("     llscblkadr  \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off");
-	printk ("\n");
-}
-__setup("autotest", autotest_enable);
-__setup("llsctest=", set_llsctest);
-__setup("llscerrstop", set_llscerrstop);
-__setup("llscfail", set_llscfail);
-__setup("llscselt", set_llscselt);
-__setup("llscblkadr", set_llscblkadr);
-
-
-extern inline int
-set_lock(uint *lock, uint id)
-{
-	uint	old;
-	old = cmpxchg_acq(lock, 0, id);
-	return (old == 0);
-}
-
-extern inline int
-clr_lock(uint *lock, uint id)
-{
-	uint	old;
-	old = cmpxchg_rel(lock, id, 0);
-	return (old == id);
-}
-
-extern inline void
-zero_lock(uint *lock)
-{
-	*lock = 0;
-}
-
-/*------------------------------------------------------------------------+
-| Routine  :  ran_conf_llsc - ll/sc shared data test                      |
-| Description: This test checks the coherency of shared data              |
-+------------------------------------------------------------------------*/
-static unsigned int
-ran_conf_llsc(int thread)
-{
-	private_t	pval;
-	share_t		sval, sval2;
-	uint		vv, linei, slinei, sharei, pass;
-	long		t;
-	lock_t		lockpat;
-	share_t		*sharecopy;
-	long		verbose, napticks, passes, linecount, lcount;
-	dataline_t	*linep, *slinep;
-	int		s, seed;
-	threadprivate_t	*tp;
-	uint		iter_msg, iter_msg_i=0;
-	int		vv_mask;
-	int		correct_errors;
-	int		errs=0;
-	int		stillbad;
-	capture_t	capdata;
-	private_t	*privp;
-	share_t		*sharep;
-
-
-	linecount = k_linecount;
-	napticks = k_napticks;
-	verbose = k_verbose;
-	passes = k_passes;
-	iter_msg = k_iter_msg;
-	seed = (thread + 1) * 647;
-	tp = THREADPRIVATE(thread);
-	vv_mask = (k_vv>>((thread%16)*4)) & 0xf;
-	correct_errors = k_options&0xff;
-
-	memset (&tp->private, 0, sizeof(tp->private));
-	memset (&capdata, 0, sizeof(capdata));
-
-	for (pass = 1; passes == 0 || pass < passes; pass++) {
-		lockpat = (pass & 0x0fffffff) + (thread <<28);
-		tp->threadpasses = pass;
-		if (checkstop(thread, pass, lockpat))
-			return 0;
-		iter_msg_i++;
-		if (iter_msg && iter_msg_i > iter_msg) {
-			printk("Thread %d, Pass %d\n", thread, pass);
-			iter_msg_i = 0;
-		}
-		lcount = 0;
-
-		/*
-		 * Select line to perform operations on.
-		 */
-		linei = randn(linecount, &seed);
-		sharei = randn(2, &seed);
-		slinei = (linei + (linecount/2))%linecount;		/* I dont like this - fix later */
-
-		linep = (dataline_t *)blocks[linei];
-		slinep = (dataline_t *)blocks[slinei];
-		if (sharei == 0)
-			sharecopy = &slinep->share0;
-		else
-			sharecopy = &slinep->share1;
-
-
-		vv = randn(4, &seed);
-		if ((vv_mask & (1<<vv)) == 0)
-			continue;
-
-		if (napticks) {
-			t = randn(napticks, &seed);
-			udelay(t);
-		}
-		privp = &linep->private[thread];
-		sharep = &linep->share[sharei];
-		
-		switch(vv) {
-		case 0:
-			/* Read and verify private count on line. */
-			pval = *privp;
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
-			if (pval != tp->private[linei]) {
-				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
-				stillbad = (*privp != tp->private[linei]);
-				if (rerr(&capdata, "Private count", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
-					return 1;
-				}
-				if (correct_errors) {
-					tp->private[linei] = *privp;
-				}
-				errs++;
-			}
-			break;
-
-		case 1:
-			/* Read, verify, and increment private count on line. */
-			pval = *privp;
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
-			if (pval != tp->private[linei]) {
-				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
-				stillbad = (*privp != tp->private[linei]);
-				if (rerr(&capdata, "Private count & inc", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
-					return 1;
-				}
-				errs++;
-			}
-			pval++;
-			*privp = pval;
-			tp->private[linei] = pval;
-			break;
-
-		case 2:
-			/* Lock line, read and verify shared data. */
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
-			lcount = 0;
-			while (LOCK(sharei) != 1) {
-				if (checkstop(thread, pass, lockpat))
-					return 0;
-				if (lcount++>1000000) {
-					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
-					stillbad = (GETLOCK(sharei) != 0);
-					rerr(&capdata, "Shared data lock", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
-					return 1;
-				}
-				if ((lcount&0x3fff) == 0)
-					udelay(1000);
-			}
-
-			sval = *sharep;
-			sval2 = *sharecopy;
-			if (pass > 12 && thread == 0 && fail_enabled == 1)
-				sval++;
-			if (sval != sval2) {
-				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
-				stillbad = (*sharep != *sharecopy);
-				if (!stillbad && *sharep != sval && *sharecopy == sval2)
-					stillbad = 2;
-				if (rerr(&capdata, "Shared data", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
-					return 1;
-				}
-				if (correct_errors)
-					*sharep = *sharecopy;
-				errs++;
-			}
-
-
-			if ( (s=UNLOCK(sharei)) != 1) {
-				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
-				stillbad = (GETLOCK(sharei) != lockpat);
-				if (rerr(&capdata, "Shared data unlock", linep, slinep, thread, pass, linei, lockpat, GETLOCK(sharei), stillbad))
-					return 1;
-				if (correct_errors)
-					ZEROLOCK(sharei);	
-				errs++;
-			}
-			break;
-
-		case 3:
-			/* Lock line, read and verify shared data, modify shared data. */
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
-			lcount = 0;
-			while (LOCK(sharei) != 1) {
-				if (checkstop(thread, pass, lockpat))
-					return 0;
-				if (lcount++>1000000) {
-					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
-					stillbad = (GETLOCK(sharei) != 0);
-					rerr(&capdata, "Shared data lock & inc", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
-					return 1;
-				}
-				if ((lcount&0x3fff) == 0)
-					udelay(1000);
-			}
-			sval = *sharep;
-			sval2 = *sharecopy;
-			if (sval != sval2) {
-				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
-				stillbad = (*sharep != *sharecopy);
-				if (!stillbad && *sharep != sval && *sharecopy == sval2)
-					stillbad = 2;
-				if (rerr(&capdata, "Shared data & inc", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
-					return 1;
-				}
-				errs++;
-			}
-
-			*sharep = lockpat;
-			*sharecopy = lockpat;
-
-
-			if ( (s=UNLOCK(sharei)) != 1) {
-				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
-				stillbad = (GETLOCK(sharei) != lockpat);
-				if (rerr(&capdata, "Shared data & inc unlock", linep, slinep, thread, pass, linei, thread, GETLOCK(sharei), stillbad))
-					return 1;
-				if (correct_errors)
-					ZEROLOCK(sharei);	
-				errs++;
-			}
-			break;
-		}
-	}
-
-	return (errs > 0);
-}
-
-static void
-trigger_la(long val)
-{
-	long	*p;
-
-	p = (long*)0xc0000a0001000020L; /* PI_CPU_NUM */
-	*p = val;
-}
-
-static long
-getsynerr(void)
-{
-	long	err, *errp;
-
-	errp = (long*)0xc0000e0000000340L;	/* SYN_ERR */
-	err = *errp;
-	if (err)
-		*errp = -1L;
-	return (err & ~0x60);
-}
-
-static int
-rerr(capture_t *cap, char *msg, void *lp, void *slp, int thread, int pass, int linei, int exp, int found, int stillbad)
-{
-	int		cpu, i;
-	long 		synerr;
-	int		selt;
-
-
-	selt = selective_trigger && stillbad > 1 && 
-			memcmp(cap->blockdata, cap->blockdata_fc, 128) != 0 &&
-			memcmp(cap->shaddata, cap->shaddata_fc, 128) == 0;
-	if (selt) {
-		trigger_la(pass);
-	} else if (selective_trigger) {
-		k_go = ST_STOP;
-		return k_stop_on_error;;
-	}
-
-	spin(1);
-	i = 100;
-	while (i && set_lock(&errlock, 1) != 1) {
-		spin(1);
-		i--;
-	}
-	printk ("\nDataError!: %-20s, test %ld, thread %d, line:%d, pass %d (0x%x), time %ld expected:%x, found:%x\n",
-	    msg, k_testnumber, thread, linei, pass, pass, jiffies, exp, found);
-
-	dumpline (lp, "Corrupted data", "D ", cap->blockaddr, cap->blockdata, cap->size);
-	if (memcmp(cap->blockdata, cap->blockdata_fc, 128))
-		dumpline (lp, "Corrupted data", "DF", cap->blockaddr, cap->blockdata_fc, cap->size);
-
-	if (cap->shadaddr) {
-		dumpline (slp, "Shadow    data", "S ", cap->shadaddr, cap->shaddata, cap->size);
-		if (memcmp(cap->shaddata, cap->shaddata_fc, 128))
-			dumpline (slp, "Shadow    data", "SF", cap->shadaddr, cap->shaddata_fc, cap->size);
-	}
-	
-	printk("Threadpasses: ");
-	for (cpu=0; cpu<MAXCPUS; cpu++)
-		if (k_threadprivate[cpu]->threadpasses)
-			printk("  %d:0x%x", cpu, k_threadprivate[cpu]->threadpasses);
-
-
-	printk("\nData was %sfixed by flushcache\n", (stillbad == 1 ? "**** NOT **** " : " "));
-	synerr = getsynerr();
-	if (synerr)
-		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
-	spin(2);
-	printk("\n\n");
-	clr_lock(&errlock, 1);
-
-	if (errstop_enabled) {
-		local_irq_disable();
-		while(1);
-	}
-	return k_stop_on_error;
-}
-
-
-static void
-dumpline(void *lp, char *str1, char *str2, void *addr, void *data, int size)
-{
-	long *p;
-	int i, off;
-
-	printk("%s at 0x%lx, size %d, block starts at 0x%lx\n", str1, (long)addr, size, (long)lp);
-	p = (long*) data;
-	for (i=0; i<16; i++, p++) {
-		if (i==0) printk("%2s", str2);
-		if (i==8) printk("  ");
-		printk(" %016lx", *p);
-		if ((i&7)==7) printk("\n");
-	}
-	printk("   ");
-	off = (((long)addr) ^ size) & 63L;
-	for (i=0; i<off+size; i++) {
-		printk("%s", (i>=off) ? "--" : "  ");
-		if ((i%8) == 7)
-			printk(" ");
-	}
-
-	off = ((long)addr) & 127;
-	printk(" (line %d)\n", off/64+1);
-}
-
-
-static int
-randn(uint max, uint *seedp)
-{
-	if (max == 1)
-		return(0);
-	else
-		return((int)(zrandom(seedp)>>10) % max);
-}
-
-
-static int
-checkstop(int thread, int pass, uint lockpat)
-{
-	long	synerr;
-
-	if (k_go == ST_RUN)
-		return 0;
-	if (k_go == ST_STOP)
-		return 1;
-
-	if (errstop_enabled) {
-		local_irq_disable();
-		while(1);
-	}
-	synerr = getsynerr();
-	spin(2);
-	if (k_go == ST_STOP)
-		return 1;
-	if (synerr)
-		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
-	return 1;
-}
-
-
-static void
-spin(int j)
-{
-	udelay(j * 500000);
-}
-
-static void
-capturedata(capture_t *cap, uint pass, void *blockaddr, void *shadaddr, int size)
-{
-
-	if (!selective_trigger)
-		trigger_la (pass);
-
-	memcpy (cap->blockdata, CACHEALIGN(blockaddr), 128);
-	if (shadaddr) 
-		memcpy (cap->shaddata, CACHEALIGN(shadaddr), 128);
-
-	if (k_stop_on_error) {
-		k_go = ST_ERRSTOP;
-	}
-
- 	cap->size = size;
-	cap->blockaddr = blockaddr;
-	cap->shadaddr = shadaddr;
-
-	asm volatile ("fc %0" :: "r"(blockaddr) : "memory");
-	ia64_sync_i();
-	ia64_srlz_d();
-	memcpy (cap->blockdata_fc, CACHEALIGN(blockaddr), 128);
-
-	if (shadaddr) {
-		asm volatile ("fc %0" :: "r"(shadaddr) : "memory");
-		ia64_sync_i();
-		ia64_srlz_d();
-		memcpy (cap->shaddata_fc, CACHEALIGN(shadaddr), 128);
-	}
-}
-
-int             zranmult = 0x48c27395;
-
-static uint  
-zrandom (uint *seedp)
-{
-        *seedp = (*seedp * zranmult) & 0x7fffffff;
-        return (*seedp);
-}
-
-
-void
-set_autotest_params(void)
-{
-	static int	testnumber=-1;
-
-	if (llsctest_number >= 0) {
-		testnumber = llsctest_number;
-	} else {
-		testnumber++;
-		if (autotest_table[testnumber].passes == 0) {
-			testnumber = 0;
-			dump_block_addrs_opt = 0;
-		}
-	}
-	k_passes = autotest_table[testnumber].passes;
-	k_linepad = autotest_table[testnumber].linepad;
-	k_linecount = autotest_table[testnumber].linecount;
-	k_testnumber = testnumber;
-
-	if (IS_RUNNING_ON_SIMULATOR()) {
-		printk ("llsc start test %ld\n", k_testnumber);
-		k_passes = 1000;
-	}
-}
-
-
-static void
-set_leds(int errs)
-{
-	unsigned char	leds=0;
-
-	/*
-	 * Leds are:
-	 * 	ppppeee-  
-	 *   where
-	 *      pppp = test number
-	 *       eee = error count but top bit is stick
-	 */
-
-	leds =  ((errs&7)<<1) | ((k_testnumber&15)<<4) | (errs ? 0x08 : 0);
-	bringup_set_led_bits(leds, 0xfe);
-}
-
-static void
-setup_block_addresses(void)
-{
-	int		i, stride, memmapi;
-
-	stride = LINESTRIDE;
-	memmapi = 0;
-	for (i=0; i<memmapx; i++) {
-		memmap[i].nextaddr = memmap[i].vstart;
-		memmap[i].wrapcount = 0;
-	}
-
-	for (i=0; i<k_linecount; i++) {
-		blocks[i] = memmap[memmapi].nextaddr;
-		memmap[memmapi].nextaddr += stride;
-		if (memmap[memmapi].nextaddr + sizeof(dataline_t) >= memmap[memmapi].vend) {
-			memmap[memmapi].wrapcount++;
-			memmap[memmapi].nextaddr = memmap[memmapi].vstart + 
-					memmap[memmapi].wrapcount * sizeof(dataline_t);
-		}
-
-		memset((void*)blocks[i], 0, sizeof(dataline_t));
-
-		if (stride > 16384) {
-			memmapi++;
-			if (memmapi == memmapx)
-				memmapi = 0;
-		}
-	}
-
-}
-
-static void
-dump_block_addrs(void)
-{
-	int	i;
-
-	printk("LLSC TestNumber %ld\n", k_testnumber);
-
-	for (i=0; i<k_linecount; i++) {
-		printk("  %lx", blocks[i]);
-		if (i%4 == 3)
-			printk("\n");
-	}
-	printk("\n");
-}
-
-
-static void
-set_thread_state(int cpuid, int state)
-{
-	if (k_threadprivate[cpuid]->threadstate == TS_KILLED) {
-		bringup_set_led_bits(0xfe, 0xfe);
-		while(1);
-	}
-	k_threadprivate[cpuid]->threadstate = state;
-}
-
-static int
-build_mem_map(unsigned long start, unsigned long end, void *arg)
-{
-	long	lstart;
-	long	align = 8*MB;
-	/*
-	 * HACK - skip the kernel on the first node 
-	 */
-
-	printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", 
-		start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE));
-
-	while (end > start && (PageReserved(virt_to_page(end-PAGE_SIZE)) || virt_to_page(end-PAGE_SIZE)->count.counter > 0))
-		end -= PAGE_SIZE;
-
-	lstart = end;
-	while (lstart > start && (!PageReserved(virt_to_page(lstart-PAGE_SIZE)) && virt_to_page(lstart-PAGE_SIZE)->count.counter == 0))
-		lstart -= PAGE_SIZE;
-
-	lstart = (lstart + align -1) /align * align;
-	end = end / align * align;
-	if (lstart >= end)
-		return 0;
-	printk ("     memmap: start 0x%lx, end 0x%lx\n", lstart, end);
-
-	memmap[memmapx].vstart = lstart;
-	memmap[memmapx].vend = end;
-	memmapx++;
-	return 0;
-}
-
-void int_test(void);
-
-int
-llsc_main (int cpuid, long mbasex)
-{
-	int		i, cpu, is_master, repeatcnt=0;
-	unsigned int	preverr=0, errs=0, pass=0;
-	int		automode=0;
-
-#ifdef INTTEST
-	if (inttest)
-		int_test();
-#endif
-
-	if (!autotest_enabled)
-		return 0;
-
-#ifdef CONFIG_SMP
-	is_master = !smp_processor_id();
-#else
-	is_master = 1;
-#endif
-
-
-	if (is_master) {
-		print_params();
-		if(!IS_RUNNING_ON_SIMULATOR())
-			spin(10);
-		mbase = (control_t*)mbasex;
-		k_currentpass = 0;
-		k_go = ST_IDLE;
-		k_passes = DEF_PASSES;
-		k_napticks = DEF_NAPTICKS;
-		k_stop_on_error = DEF_STOP_ON_ERROR;
-		k_verbose = DEF_VERBOSE;
-		k_linecount = DEF_LINECOUNT;
-		k_iter_msg = DEF_ITER_MSG;
-		k_vv = DEF_VV;
-		k_linepad = DEF_LINEPAD;
-		k_blocks = (void*)blocks;
-		efi_memmap_walk(build_mem_map, 0);
-	
-#ifdef CONFIG_IA64_SGI_AUTOTEST
-		automode = 1;
-#endif
-
-		for (i=0; i<MAXCPUS; i++) {
-			k_threadprivate[i] = THREADPRIVATE(i);
-			memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i]));
-		}
-		initialized = 1;
-	} else {
-		while (initialized == 0)
-			udelay(100);
-	}
-
-loop:
-	if (is_master) {
-		if (automode) {
-			if (!preverr || repeatcnt++ > 5) {
-				set_autotest_params();
-				repeatcnt = 0;
-			}
-		} else {
-			while (k_go == ST_IDLE);
-		}
-
-		k_go = ST_INIT;
-		if (k_linecount > MAX_LINECOUNT) k_linecount = MAX_LINECOUNT;
-		k_linecount = k_linecount & ~1;
-		setup_block_addresses();
-		if (dump_block_addrs_opt)
-			dump_block_addrs();
-
-		k_currentpass = pass++;
-		k_go = ST_RUN;
-		if (fail_enabled)
-			fail_enabled--;
-
-	} else {
-		while (k_go != ST_RUN || k_currentpass != pass);
-		pass++;
-	}
-
-
-	set_leds(errs);
-	set_thread_state(cpuid, TS_RUNNING);
-
-	errs += ran_conf_llsc(cpuid);
-	preverr = (k_go == ST_ERRSTOP);
-
-	set_leds(errs);
-	set_thread_state(cpuid, TS_STOPPED);
-
-	if (is_master) {
-		Speedo();
-		for (i=0, cpu=0; cpu<MAXCPUS; cpu++) {
-			while (k_threadprivate[cpu]->threadstate == TS_RUNNING) {
-				i++;
-				if (i == 10000) { 
-					k_go = ST_STOP;
-					printk ("  llsc master stopping test number %ld\n", k_testnumber);
-				}
-				if (i > 100000) {
-					k_threadprivate[cpu]->threadstate = TS_KILLED;
-					printk ("  llsc: master killing cpuid %d, running test number %ld\n", 
-							cpu, k_testnumber);
-				}
-				udelay(1000);
-			}
-		}
-	}
-
-	goto loop;
-}
-
-
-static void
-Speedo(void)
-{
-	static int i = 0;
-
-	switch (++i%4) {
-	case 0:
-		printk("|\b");
-		break;
-	case 1:
-		printk("\\\b");
-		break;
-	case 2:
-		printk("-\b");
-		break;
-	case 3:
-		printk("/\b");
-		break;
-	}
-}
-
-#ifdef INTTEST
-
-/* ======================================================================================================== 
- *
- * Some test code to verify that interrupts work
- *
- * Add the following to the arch/ia64/kernel/smp.c after the comment "Reschedule callback"
- * 		if (zzzprint_resched) printk("  cpu %d got interrupt\n", smp_processor_id());
- *
- * Enable the code in arch/ia64/sn/sn1/smp.c to print sending IPIs.
- *
- */
-
-static int __init set_inttest(char *str)
-{
-        inttest = 1;
-	autotest_enabled = 1;
-
-	return 1;
-}	
-
-__setup("inttest=", set_inttest);
-
-int	zzzprint_resched=0;
-
-void
-int_test() {
-	int			mycpu, cpu;
-	static volatile int	control_cpu=0;
-
-	mycpu = smp_processor_id();
-	zzzprint_resched = 2;
-
-	printk("Testing cross interrupts\n");
-	
-	while (control_cpu != smp_num_cpus) {
-		if (mycpu == cpu_logical_map(control_cpu)) {
-			for (cpu=0; cpu<smp_num_cpus; cpu++) {
-				printk("Sending interrupt from %d to %d\n", mycpu, cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-				smp_send_reschedule(cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-				smp_send_reschedule(cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-			}
-			control_cpu++;
-		}
-	}
-
-	zzzprint_resched = 1;
-
-	if (mycpu == cpu_logical_map(smp_num_cpus-1)) {
-		printk("\nTight loop of cpu %d sending ints to cpu 0 (every 100 us)\n", mycpu);
-		udelay(IS_RUNNING_ON_SIMULATOR ? 1000 : 1000000);
-		__cli();
-		while (1) {
-			smp_send_reschedule(0);
-			udelay(100);
-		}
-
-	}
-
-	while(1);
-}
-#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/llsc4.h linux/arch/ia64/sn/sn1/llsc4.h
--- linux.orig/arch/ia64/sn/sn1/llsc4.h	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/sn1/llsc4.h	1970-01-01 00:00:00.000000000 +0000
@@ -1,104 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-#ifdef STANDALONE
-#include "lock.h"
-#endif
-
-
-#define DEF_NAPTICKS		0
-#define DEF_PASSES		0
-#define DEF_AUTO_PASSES		1000000
-#define DEF_STOP_ON_ERROR	1
-#define DEF_VERBOSE		0
-#define DEF_LINECOUNT		2
-#define DEF_ITER_MSG		0
-#define DEF_VV			0xffffffff
-#define DEF_LINEPAD		0x234
-
-
-
-#define MAXCPUS			16
-#define CACHELINE		64
-#define MAX_LINECOUNT		1024
-#define K			1024
-#define	MB			(K*K)
-
-
-#define	uint 		unsigned int
-#define	ushort		unsigned short
-#define vint		volatile int
-#define vlong		volatile long
-
-#define LOCKADDR(i)	&linep->lock[(i)]
-#define LOCK(i)		set_lock(LOCKADDR(i), lockpat)
-#define UNLOCK(i)	clr_lock(LOCKADDR(i), lockpat)
-#define GETLOCK(i)	*LOCKADDR(i)
-#define ZEROLOCK(i)	zero_lock(LOCKADDR(i))
-
-#define CACHEALIGN(a)	((void*)((long)(a) & ~127L))
-
-typedef uint		lock_t;
-typedef uint		share_t;
-typedef uint		private_t;
-
-typedef struct {
-	lock_t		lock[2];
-	share_t		share[2];
-	private_t	private[MAXCPUS];
-	share_t		share0;
-	share_t		share1;
-} dataline_t ;
-
-
-#define LINEPAD			k_linepad
-#define LINESTRIDE		(((sizeof(dataline_t)+CACHELINE-1)/CACHELINE)*CACHELINE + LINEPAD)
-
-
-typedef struct {
-	vint		threadstate;
-	uint		threadpasses;
-	private_t	private[MAX_LINECOUNT];
-} threadprivate_t;
-
-typedef struct {
-	vlong		sk_go;		/* 0=idle, 1=init, 2=run */
-	long		sk_linecount;
-	long		sk_passes;
-	long		sk_napticks;
-	long		sk_stop_on_error;
-	long		sk_verbose;
-	long		sk_iter_msg;
-	long		sk_vv;
-	long		sk_linepad;
-	long		sk_options;
-	long		sk_testnumber;
-	vlong		sk_currentpass;
-	void 		*sk_blocks;
-	threadprivate_t	*sk_threadprivate[MAXCPUS];
-} control_t;
-
-/* Run state (k_go) constants */
-#define ST_IDLE		0
-#define ST_INIT		1
-#define ST_RUN		2
-#define ST_STOP		3
-#define ST_ERRSTOP	4
-
-
-/* Threadstate constants */
-#define TS_STOPPED	0
-#define	TS_RUNNING	1
-#define TS_KILLED	2
-
-
-
-int llsc_main (int cpuid, long mbasex);
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/machvec.c linux/arch/ia64/sn/sn1/machvec.c
--- linux.orig/arch/ia64/sn/sn1/machvec.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/machvec.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,18 +0,0 @@
-#define MACHVEC_PLATFORM_NAME	sn1
-#include <asm/machvec_init.h>
-#include <asm/io.h>
-#include <linux/pci.h>
-void*
-sn1_mk_io_addr_MACRO
-
-dma_addr_t
-sn1_pci_map_single_MACRO
-
-int
-sn1_pci_map_sg_MACRO
-
-unsigned long
-sn1_virt_to_phys_MACRO
-
-void *
-sn1_phys_to_virt_MACRO
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/mm.c linux/arch/ia64/sn/sn1/mm.c
--- linux.orig/arch/ia64/sn/sn1/mm.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/mm.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,394 +0,0 @@
-/*
- * Copyright, 2000-2001, Silicon Graphics.
- * Copyright Srinivasa Thirumalachar (sprasad@engr.sgi.com)
- * Copyright 2000-2001 Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/page.h>
-#include <asm/efi.h>
-#include <asm/sn/mmzone_sn1.h>
-
-#define MIN(a,b)	((a) < (b) ? (a) : (b))
-#define MAX(a,b)	((a) > (b) ? (a) : (b))
-
-#define DONE_NOTHING	0
-#define DONE_FINDING	1
-#define DONE_BUILDING	2
-
-struct nodemem_s {
-        u64     start;	/* start of kernel usable memory */
-        u64     end;	/* end of kernel usable memory */
-	u64	mtot;	/* total kernel usable memory */
-	u64	done;	/* state of bootmem initialization */
-	u64	bstart;	/* where should the bootmem area be */
-	u64	bsize;	/* bootmap size */
-        u64 	hole[SN1_MAX_BANK_PER_NODE];
-} nodemem[MAXNODES];
-
-static int nodemem_valid = 0;
-
-static int __init
-free_unused_memmap_hole(int nid, unsigned long start, unsigned long end)
-{
-        struct page * page, *pageend;
-        unsigned long count = 0;
-
-	if (start >= end)
-		return 0;
-
-	/*
-	 * Get the memmap ptrs to the start and end of the holes.
-	 * virt_to_page(start) will panic, if start is in hole.
-	 * Can we do virt_to_page(end), if end is on the next node?
-	 */
-
-	page = virt_to_page(start - 1);
-	page++;
-	pageend = virt_to_page(end);
-
-	printk("hpage=0x%lx, hpageend=0x%lx\n", (u64)page, (u64)pageend) ;
-	free_bootmem_node(NODE_DATA(nid), __pa(page), (u64)pageend - (u64)page);
-
-	return count;
-}
-
-static void __init
-free_unused_memmap_node(int nid)
-{
-	u64	i = 0;
-	u64	holestart = -1;
-	u64	start = nodemem[nid].start;
-
-	start = ((start >> SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	do {
-		holestart = nodemem[nid].hole[i];
-		i++;
-		while ((i < SN1_MAX_BANK_PER_NODE) && 
-					(nodemem[nid].hole[i] == (u64)-1))
-			i++;
-		if (i < SN1_MAX_BANK_PER_NODE)
-			free_unused_memmap_hole(nid, holestart, 
-				start + (i<<SN1_BANK_ADDR_SHIFT));
-	} while (i<SN1_MAX_BANK_PER_NODE);
-}
-
-/*
- * Since efi_memmap_walk merges contiguous banks, this code will need
- * to find all the nasid/banks covered by the input memory descriptor.
- */
-static int __init
-build_nodemem_map(unsigned long start, unsigned long end, void *arg)
-{
-	unsigned long vaddr = start;
-	unsigned long nvaddr;
-	int nasid = GetNasId(__pa(vaddr));
-	int cnodeid, bankid;
-
-	while (vaddr < end) {
-		cnodeid = NASID_TO_CNODEID(nasid);
-		bankid = GetBankId(__pa(vaddr));
-		nodemem[cnodeid].start = MIN(nodemem[cnodeid].start, vaddr);
-		nvaddr = (unsigned long)__va((unsigned long)(++nasid) << 
-							SN1_NODE_ADDR_SHIFT);
-		nodemem[cnodeid].end = MAX(nodemem[cnodeid].end, MIN(end, nvaddr));
-		while ((bankid < SN1_MAX_BANK_PER_NODE) && 
-					(vaddr < nodemem[cnodeid].end)) {
-			nvaddr = nodemem[cnodeid].start + 
-			  ((unsigned long)(bankid + 1) << SN1_BANK_ADDR_SHIFT);
-			nodemem[cnodeid].hole[bankid++] = MIN(nvaddr, end);
-			vaddr = nvaddr;
-		}
-	}
-
-	return 0;
-}
-
-static int __init
-pgtbl_size_ok(int nid)
-{
-	unsigned long numpfn, bank0size, nodesize ;
-	unsigned long start = nodemem[nid].start;
-
-	start = ((start >> SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	
-	nodesize 	= nodemem[nid].end - start ;
-	numpfn 		= nodesize >> PAGE_SHIFT;
-
-	bank0size 	= nodemem[nid].hole[0] - start ;
-	/* If nid == master node && no kernel text replication */
-	bank0size      -= 0xA00000 ;	/* Kernel text + stuff */
-	bank0size      -= ((numpfn + 7) >> 3);
-
-	if ((numpfn * sizeof(mem_map_t)) > bank0size) {
-		printk("nid = %d, ns=0x%lx, npfn=0x%lx, bank0size=0x%lx\n", 
-			nid, nodesize, numpfn, bank0size) ;
-		return 0 ;
-	}
-
-	return 1 ;
-}
-
-static void __init
-check_pgtbl_size(int nid)
-{
-	int	bank = SN1_MAX_BANK_PER_NODE - 1 ;
-
-	/* Find highest bank with valid memory */
-        while ((nodemem[nid].hole[bank] == -1) && (bank))
-               bank-- ;
-
-	while (!pgtbl_size_ok(nid)) {
-		/* Remove that bank of memory */
-		/* Collect some numbers later */
-		printk("Ignoring node %d bank %d\n", nid, bank) ;
-		nodemem[nid].hole[bank--] = -1 ;
-		/* Get to the next populated bank */
-		while ((nodemem[nid].hole[bank] == -1) && (bank))
-			bank-- ;
-		printk("Using only upto bank %d on node %d\n", bank,nid) ;
-		nodemem[nid].end = nodemem[nid].hole[bank] ; 
-		if (!bank) break ;
-	}
-}
-
-void dump_nodemem_map(int) ;
-
-#ifdef CONFIG_DISCONTIGMEM
-
-extern bootmem_data_t bdata[];
-
-/*
- * This assumes there will be a hole in kernel-usable memory between nodes
- * (due to prom). The memory descriptors invoked via efi_memmap_walk are 
- * in increasing order. It tries to identify first suitable free area to 
- * put the bootmem for the node in. When presented with the md holding
- * the kernel, it only searches at the end of the kernel area.
- */
-static int __init
-find_node_bootmem(unsigned long start, unsigned long end, void *arg)
-{
-	int nasid = GetNasId(__pa(start));
-	int cnodeid = NASID_TO_CNODEID(nasid);
-	unsigned long nodesize;
-	extern char _end;
-	unsigned long kaddr = (unsigned long)&_end;
-
-	/*
-	 * Track memory available to kernel.
-	 */
-	nodemem[cnodeid].mtot += ((end - start) >> PAGE_SHIFT);
-	if (nodemem[cnodeid].done != DONE_NOTHING)
-		return(0);
-	nodesize = nodemem[cnodeid].end - ((nodemem[cnodeid].start >> 
-				SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	nodesize >>= PAGE_SHIFT;
-
-	/*
-	 * Adjust limits for the md holding the kernel.
-	 */
-	if ((start < kaddr) && (end > kaddr))
-		start = PAGE_ALIGN(kaddr);
-
-	/*
-	 * We need space for mem_map, bootmem map plus a few more pages
-	 * to satisfy alloc_bootmems out of node 0.
-	 */
-	if ((end - start) > ((nodesize * sizeof(struct page)) + (nodesize/8)
-						+ (10 * PAGE_SIZE))) {
-		nodemem[cnodeid].bstart = start;
-		nodemem[cnodeid].done = DONE_FINDING;
-	}
-	return(0);
-}
-
-/*
- * This assumes there will be a hole in kernel-usable memory between nodes
- * (due to prom). The memory descriptors invoked via efi_memmap_walk are 
- * in increasing order.
- */
-static int __init
-build_node_bootmem(unsigned long start, unsigned long end, void *arg)
-{
-	int nasid = GetNasId(__pa(start));
-	int curnodeid = NASID_TO_CNODEID(nasid);
-	int i;
-	unsigned long pstart, pend;
-	extern char _end, _stext;
-	unsigned long kaddr = (unsigned long)&_end;
-
-	if (nodemem[curnodeid].done == DONE_FINDING) {
-		/*
-		 * This is where we come to know the node is present.
-		 * Do node wide tasks.
-		 */
-		nodemem[curnodeid].done = DONE_BUILDING;
-		NODE_DATA(curnodeid)->bdata = &(bdata[curnodeid]);
-
-		/*
-	 	 * Update the chunktonid array as a node wide task. There
-		 * are too many smalls mds on first node to do this per md.
-	 	 */
-		pstart = __pa(nodemem[curnodeid].start);
-		pend = __pa(nodemem[curnodeid].end);
-		pstart &= CHUNKMASK;
-		pend = (pend + CHUNKSZ - 1) & CHUNKMASK;
-		/* Possible check point to enforce minimum node size */
-		if (nodemem[curnodeid].bstart == -1) {
-			printk("No valid bootmem area on node %d\n", curnodeid);
-			while(1);
-		}
-		for (i = PCHUNKNUM(pstart); i <= PCHUNKNUM(pend - 1); i++)
-			chunktonid[i] = curnodeid;
-		if ((CHUNKTONID(PCHUNKNUM(pend)) > MAXCHUNKS) || 
-				(PCHUNKNUM(pstart) >= PCHUNKNUM(pend))) {
-			printk("Ign 0x%lx-0x%lx, ", __pa(start), __pa(end));
-			return(0);
-		}
-
-		/*
-		 * NODE_START and NODE_SIZE determine the physical range
-		 * on the node that mem_map array needs to be set up for.
-		 */
-		NODE_START(curnodeid) = ((nodemem[curnodeid].start >> 
-				SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-		NODE_SIZE(curnodeid) = (nodemem[curnodeid].end - 
-							NODE_START(curnodeid));
-
-        	nodemem[curnodeid].bsize = 
-			init_bootmem_node(NODE_DATA(curnodeid),
-			(__pa(nodemem[curnodeid].bstart) >> PAGE_SHIFT),
-			(__pa((nodemem[curnodeid].start >> SN1_NODE_ADDR_SHIFT)
-			<< SN1_NODE_ADDR_SHIFT) >> PAGE_SHIFT),
-			(__pa(nodemem[curnodeid].end) >> PAGE_SHIFT));
-
-	} else if (nodemem[curnodeid].done == DONE_NOTHING) {
-		printk("build_node_bootmem: node %d weirdness\n", curnodeid);
-		while(1);		/* Paranoia */
-	}
-
-	/*
-	 * Free the entire md.
-	 */
-	free_bootmem_node(NODE_DATA(curnodeid), __pa(start), (end - start));
-
-	/*
-	 * Reclaim back the bootmap and kernel areas.
-	 */
-	if ((start <= nodemem[curnodeid].bstart) && (end >
-						nodemem[curnodeid].bstart))
-		reserve_bootmem_node(NODE_DATA(curnodeid),
-		    __pa(nodemem[curnodeid].bstart), nodemem[curnodeid].bsize);
-	if ((start <= kaddr) && (end > kaddr))
-		reserve_bootmem_node(NODE_DATA(curnodeid),
-		    __pa(&_stext), (&_end - &_stext));
-
-	return(0);
-}
-
-void __init
-setup_sn1_bootmem(int maxnodes)
-{
-        int     i;
-
-        for (i = 0; i < MAXNODES; i++) {
-                nodemem[i].start = nodemem[i].bstart = -1;
-                nodemem[i].end = nodemem[i].bsize = nodemem[i].mtot = 0;
-		nodemem[i].done = DONE_NOTHING;
-		memset(&nodemem[i].hole, -1, sizeof(nodemem[i].hole));
-        }
-        efi_memmap_walk(build_nodemem_map, 0);
-
-	nodemem_valid = 1;
-
-	/* 
-	 * After building the nodemem map, check if the node memmap
-	 * will fit in the first bank of each node. If not change
-	 * the node end addr till it fits.
- 	 */
-
-        for (i = 0; i < maxnodes; i++)
-		check_pgtbl_size(i);
-
-	dump_nodemem_map(maxnodes);
-
-	efi_memmap_walk(find_node_bootmem, 0);
-	efi_memmap_walk(build_node_bootmem, 0);
-}
-#endif
-
-void __init
-discontig_paging_init(void)
-{
-	int i;
-	unsigned long max_dma, zones_size[MAX_NR_ZONES], holes_size[MAX_NR_ZONES];
-	extern void dump_node_data(void);
-
-	max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-	for (i = 0; i < numnodes; i++) {
-		unsigned long startpfn = __pa((void *)NODE_START(i)) >> PAGE_SHIFT;
-		unsigned long numpfn = NODE_SIZE(i) >> PAGE_SHIFT;
-		memset(zones_size, 0, sizeof(zones_size));
-		memset(holes_size, 0, sizeof(holes_size));
-		holes_size[ZONE_DMA] = numpfn - nodemem[i].mtot;
-
-		if ((startpfn + numpfn) < max_dma) {
-			zones_size[ZONE_DMA] = numpfn;
-		} else if (startpfn > max_dma) {
-			zones_size[ZONE_NORMAL] = numpfn;
-			panic("discontig_paging_init: %d\n", i);
-		} else {
-			zones_size[ZONE_DMA] = (max_dma - startpfn);
-			zones_size[ZONE_NORMAL] = numpfn - zones_size[ZONE_DMA];
-			panic("discontig_paging_init: %d\n", i);
-		}
-		free_area_init_node(i, NODE_DATA(i), NULL, zones_size, startpfn<<PAGE_SHIFT, holes_size);
-		free_unused_memmap_node(i);
-	}
-	dump_node_data();
-}
-
-/*
- * This used to be invoked from an SN1 specific hack in efi_memmap_walk.
- * It tries to ignore banks which the kernel is ignoring because bank 0 
- * is too small to hold the memmap entries for this bank.
- * The current SN1 efi_memmap_walk callbacks do not need this. That 
- * leaves the generic ia64 callbacks find_max_pfn, count_pages and
- * count_reserved_pages, of which the first can probably get by without
- * this, the last two probably need this, although they also can probably
- * get by. 
- */
-int
-sn1_bank_ignore(u64 start, u64 end)
-{
-	int 	nid = NASID_TO_CNODEID(GetNasId(__pa(end))) ;
-	int	bank = GetBankId(__pa(end)) ;
-
-	if (!nodemem_valid)
-		return 0 ;
-
-	if (nodemem[nid].hole[bank] == -1)
-		return 1 ;
-	else
-		return 0 ;
-}
-
-void
-dump_nodemem_map(int maxnodes)
-{
-	int	i,j;
-
-        printk("NODEMEM_S info ....\n") ;
-        printk("Node         start                end\n");
-        for (i=0;i<maxnodes;i++) {
-                printk("%d      0x%lx   0x%lx\n",
-                       i, nodemem[i].start, nodemem[i].end);
-                printk("Holes -> ") ;
-                for (j=0;j<SN1_MAX_BANK_PER_NODE;j++)
-                        printk("0x%lx ", nodemem[i].hole[j]) ;
-		printk("\n");
-        }
-}
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/probe.c linux/arch/ia64/sn/sn1/probe.c
--- linux.orig/arch/ia64/sn/sn1/probe.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/probe.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,62 +0,0 @@
-/*
- * Platform dependent support for IO probing.
- *
- * Copyright (C) 2000   Silicon Graphics
- * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
- */
-
-#include <asm/sn/sn_sal.h>
-
-/*
- * ia64_sn_probe_io_slot
- *	This function will probe a physical address to determine if
- *	the address can be read. If reading the address causes a BUS
- *	error, an error is returned. If the probe succeeds, the contents 
- *	of the memory location is returned.
- *
- *   Calling sequence:
- *		ia64_probe_io_slot(paddr, size, data_ptr)
- *
- *   Input:
- *	paddr		Physical address to probe
- *	size		Number bytes to read (1,2,4,8)
- *	data_ptr	Address to store value read by probe
- *		          (-1 returned if probe fails)
- *
- *   Output:
- *	Status
- *		 0 - probe successful
- *		 1 - probe failed (generated MCA)
- *		 2 - Bad arg
- *		<0 - PAL error
- */
-
-
-u64
-ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr)
-{
-	struct ia64_sal_retval isrv;
-
-	SAL_CALL(isrv, SN_SAL_PROBE, paddr, size, 0, 0, 0, 0, 0);
-
-	if (data_ptr) {
-		switch (size) {
-			case 1:
-				*((u8*)data_ptr) = (u8)isrv.v0;
-				break;
-			case 2:
-				*((u16*)data_ptr) = (u16)isrv.v0;
-				break;
-			case 4:
-				*((u32*)data_ptr) = (u32)isrv.v0;
-				break;
-			case 8:
-				*((u64*)data_ptr) = (u64)isrv.v0;
-				break;
-			default:
-				isrv.status = 2;	
-		}
-	}
-
-	return isrv.status;
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/setup.c linux/arch/ia64/sn/sn1/setup.c
--- linux.orig/arch/ia64/sn/sn1/setup.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/setup.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,254 +0,0 @@
-/*
- *
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/kdev_t.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-#include <linux/console.h>
-#include <linux/timex.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/serial.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-#include <asm/machvec.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <asm-ia64/sn/arch.h>
-#include <asm-ia64/sn/addrs.h>
-
-
-/*
- * This is the address of the RRegs in the HSpace of the global
- * master.  It is used by a hack in serial.c (serial_[in|out],
- * printk.c (early_printk), and kdb_io.c to put console output on that
- * node's Bedrock UART.  It is initialized here to 0, so that
- * early_printk won't try to access the UART before
- * master_node_bedrock_address is properly calculated.
- */
-u64 master_node_bedrock_address = 0UL;
-
-static void sn_fix_ivt_for_partitioned_system(void);
-
-
-/*
- * The format of "screen_info" is strange, and due to early i386-setup
- * code. This is just enough to make the console code think we're on a
- * VGA color display.
- */
-struct screen_info sn1_screen_info = {
-	orig_x:			 0,
-	orig_y:			 0,
-	orig_video_mode:	 3,
-	orig_video_cols:	80,
-	orig_video_ega_bx:	 3,
-	orig_video_lines:	25,
-	orig_video_isVGA:	 1,
-	orig_video_points:	16
-};
-
-/*
- * This is here so we can use the CMOS detection in ide-probe.c to
- * determine what drives are present.  In theory, we don't need this
- * as the auto-detection could be done via ide-probe.c:do_probe() but
- * in practice that would be much slower, which is painful when
- * running in the simulator.  Note that passing zeroes in DRIVE_INFO
- * is sufficient (the IDE driver will autodetect the drive geometry).
- */
-char drive_info[4*16];
-
-unsigned long
-sn1_map_nr (unsigned long addr)
-{
-#ifdef CONFIG_DISCONTIGMEM
-	return MAP_NR_SN1(addr);
-#else
-	return MAP_NR_DENSE(addr);
-#endif
-}
-
-#if defined(BRINGUP) && defined(CONFIG_IA64_EARLY_PRINTK)
-void __init
-early_sn1_setup(void)
-{
-	master_node_bedrock_address = 
-		(u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
-	printk("early_sn1_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address);
-}
-#endif /* BRINGUP && CONFIG_IA64_EARLY_PRINTK */
-
-void __init
-sn1_setup(char **cmdline_p)
-{
-#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-	struct serial_struct req;
-#endif
-
-	MAX_DMA_ADDRESS = PAGE_OFFSET + 0x10000000000UL;
-	master_node_bedrock_address = 
-		(u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
-	printk("sn1_setup: setting master_node_bedrock_address to 0x%lx\n",
-		   master_node_bedrock_address);
-
-#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-	/*
-	 * We do early_serial_setup() to clean out the rs-table[] from the
-	 * statically compiled in version.
-	 */
-	memset(&req, 0, sizeof(struct serial_struct));
-	req.line = 0;
-	req.baud_base = 124800;
-	req.port = 0;
-	req.port_high = 0;
-	req.irq = 0;
-	req.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST);
-	req.io_type = SERIAL_IO_MEM;
-	req.hub6 = 0;
-	req.iomem_base = (u8 *)(master_node_bedrock_address + 0x80);
-	req.iomem_reg_shift = 3;
-	req.type = 0;
-	req.xmit_fifo_size = 0;
-	req.custom_divisor = 0;
-	req.closing_wait = 0;
-	early_serial_setup(&req);
-#endif /* CONFIG_SERIAL && !CONFIG_SERIAL_SGI_L1_PROTOCOL */
-
-	ROOT_DEV = to_kdev_t(0x0301);		/* default to first IDE drive */
-	sn_fix_ivt_for_partitioned_system();
-
-#ifdef CONFIG_SMP
-	init_smp_config();
-#endif
-	screen_info = sn1_screen_info;
-}
-
-
-/* 
- * sn_fix_ivt_for_partitioned_system
- *
- * This is an ugly hack that is needed for partitioned systems.
- *
- * On a partitioned system, most partitions do NOT have a physical address 0.
- * Unfortunately, the exception handling code in ivt.S has a couple of physical
- * addresses of kernel structures hardcoded into "movl" instructions.
- * These addresses are correct on partition 0 only. On all other partitions,
- * the addresses must be changed to reference the correct address.
- *
- * This routine scans the ivt code and replaces the hardcoded addresses with 
- * the correct address.
- *
- * Note that we could have made the ivt.S code dynamically determine the correct
- * address but this would add code to performance critical pathes. This option
- * was rejected.
- */
-
-#define TEMP_mlx	4		/* template type that contains movl instruction */
-#define TEMP_mlX	5		/* template type that contains movl instruction */
-
-typedef union {				/* Instruction encoding for movl instruction */
-	struct {
-		unsigned long	qp:6;
-		unsigned long	r1:7;
-		unsigned long	imm7b:7;
-		unsigned long	vc:1;
-		unsigned long	ic:1;
-		unsigned long	imm5c:5;
-		unsigned long	imm9d:9;
-		unsigned long	i:1;
-		unsigned long	op:4;
-		unsigned long	fill:23;
-	} b;
-	unsigned long	l;
-} movl_instruction_t;
-
-#define MOVL_OPCODE	6
-#define MOVL_ARG(a,b)	(((long)a.i<<63) | ((long)b<<22) | ((long)a.ic<<21) | \
-			((long)a.imm5c<<16) | ((long)a.imm9d<<7) | ((long)a.imm7b))
-
-typedef struct {				/* Instruction bundle */
-	unsigned long template:5;
-	unsigned long ins2:41;
-	unsigned long ins1l:18;
-	unsigned long ins1u:23;
-	unsigned long ins0:41;
-} instruction_bundle_t;
-
-
-static void __init
-sn_fix_ivt_for_partitioned_system(void)
-{
-	extern int		ia64_ivt;
-	instruction_bundle_t	*p, *pend;
-	movl_instruction_t	ins0, ins1, ins2;
-	long			new_ins1, phys_offset;
-	unsigned long		val;
-
-	/*
-	 * Setup to scan the ivt code.
-	 */
-	p = (instruction_bundle_t*)&ia64_ivt;
-	pend = p + 0x8000/sizeof(instruction_bundle_t);
-	phys_offset = __pa(p) & ~0x1ffffffffUL;
-
-	/*
-	 * Hunt for movl instructions that contain the node 0 physical address 
-	 * of "SWAPPER_PGD_ADDR".  These addresses must be relocated to reference the 
-	 * actual node that the kernel is loaded on.
-	 */
-	for (; p < pend; p++) {
-		if (p->template != TEMP_mlx && p->template != TEMP_mlX)
-			continue;
-		ins0.l =  p->ins0;
-		if (ins0.b.op != MOVL_OPCODE)
-			continue;
-		ins1.l =  ((long)p->ins1u<<18) | p->ins1l;
-		ins2.l =  p->ins2;
-		val = MOVL_ARG(ins0.b, ins1.l);
-
-		/*
-		 * Test for correct address. SWAPPER_PGD_ADDR will
-		 * always be a node 0 virtual address. Note that we cant
-		 * use the __pa or __va macros here since they may contain
-		 * debug code that gets fooled here.
-		 */
-		if ((PAGE_OFFSET | val)  != SWAPPER_PGD_ADDR)
-			continue;
-
-		/*
-		 * We found an instruction that needs to be fixed. The following
-		 * inserts the NASID of the ivt into the movl instruction.
-		 */
-		new_ins1 = ins1.l | (phys_offset>>22);
-		p->ins1l = new_ins1 & 0x3ffff;
-		p->ins1u = (new_ins1>>18) & 0x7fffff;
-		ia64_fc(p);
-	}
-
-	/*
-	 * Do necessary serialization.
-	 */
-	ia64_sync_i();
-	ia64_srlz_i();
-
-}
-
-int
-IS_RUNNING_ON_SIMULATOR(void)
-{
-#ifdef CONFIG_IA64_SGI_SN1_SIM
-	long sn;
-	asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2));
-	return(sn == SNMAGIC);
-#else
-	return(0);
-#endif
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/smp.c linux/arch/ia64/sn/sn1/smp.c
--- linux.orig/arch/ia64/sn/sn1/smp.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/smp.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,186 +0,0 @@
-/*
- * SN1 Platform specific SMP Support
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Jack Steiner <steiner@sgi.com>
- */
-
-
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/threads.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/sal.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <asm/current.h>
-#include <asm/sn/sn_cpuid.h>
-
-
-
-
-/*
- * The following structure is used to pass params thru smp_call_function
- * to other cpus for flushing TLB ranges.
- */
-typedef struct {
-	unsigned long	start;
-	unsigned long	end;
-	unsigned long	nbits;
-} ptc_params_t;
-
-
-/*
- * The following table/struct is for remembering PTC coherency domains. It
- * is also used to translate sapicid into cpuids. We dont want to start 
- * cpus unless we know their cache domain.
- */
-#ifdef PTC_NOTYET
-sn_sapicid_info_t	sn_sapicid_info[NR_CPUS];
-#endif
-
-
-
-#ifdef PTC_NOTYET
-/*
- * NOTE: This is probably not good enough, but I dont want to try to make
- * it better until I get some statistics on a running system. 
- * At a minimum, we should only send IPIs to 1 processor in each TLB domain
- * & have it issue a ptc.g on it's own FSB. Also, serialize per FSB, not 
- * globally.
- *
- * More likely, we will have to do some work to reduce the frequency of calls to
- * this routine.
- */
-
-static void
-sn1_ptc_local(void *arg)
-{
-	ptc_params_t	*params = arg;
-	unsigned long	start, end, nbits;
-
-	start = params->start;
-	end = params->end;
-	nbits = params->nbits;
-
-	do {
-		__asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
-		start += (1UL << nbits);
-	} while (start < end);
-}
-
-
-void
-sn1_ptc_global (unsigned long start, unsigned long end, unsigned long nbits)
-{
-	ptc_params_t	params;
-
-	params.start = start;
-	params.end = end;
-	params.nbits = nbits;
-
-	if (smp_call_function(sn1_ptc_local, &params, 1, 0) != 0)
-		panic("Unable to do ptc_global - timed out");
-
-	sn1_ptc_local(&params);
-}
-#endif
-
-
-
-
-void
-sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
-{
-	long		*p, nasid, slice;
-	static int 	off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
-
-	/*
-	 * ZZZ - Replace with standard macros when available.
-	 */
-	nasid = cpuid_to_nasid(cpuid);
-	slice = cpuid_to_slice(cpuid);
-	p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
-
-#if defined(ZZZBRINGUP)
-	{
-	static int count=0;
-	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
-		smp_processor_id(), cpuid, vector, nasid, slice, (long)p);
-	}
-#endif
-	mb();
-	*p = (delivery_mode << 8) | (vector & 0xff);
-	
-}
-
-
-#ifdef CONFIG_SMP
-
-#ifdef PTC_NOTYET
-static void __init
-process_sal_ptc_domain_info(ia64_sal_ptc_domain_info_t *di, int domain)
-{
-	ia64_sal_ptc_domain_proc_entry_t	*pe;
-	int 					i, sapicid, cpuid;
-
-	pe = __va(di->proc_list);
-	for (i=0; i<di->proc_count; i++, pe++) {
-		sapicid = id_eid_to_sapicid(pe->id, pe->eid);
-		cpuid = cpu_logical_id(sapicid);
-		sn_sapicid_info[cpuid].domain = domain;
-		sn_sapicid_info[cpuid].sapicid = sapicid;
-	}
-}
-
-
-static void __init
-process_sal_desc_ptc(ia64_sal_desc_ptc_t *ptc)
-{
-	ia64_sal_ptc_domain_info_t	*di;
-	int i;
-
-	di = __va(ptc->domain_info);
-	for (i=0; i<ptc->num_domains; i++, di++) {
-		process_sal_ptc_domain_info(di, i);	
-	}
-}
-#endif
-
-
-void __init
-init_sn1_smp_config(void)
-{
-
-	if (!ia64_ptc_domain_info)  {
-		printk("SMP: Can't find PTC domain info. Forcing UP mode\n");
-		smp_num_cpus = 1;
-		return;
-	}
-
-#ifdef PTC_NOTYET
-	memset (sn_sapicid_info, -1, sizeof(sn_sapicid_info));
-	process_sal_desc_ptc(ia64_ptc_domain_info);
-#endif
-
-}
-
-#else /* CONFIG_SMP */
-
-void __init
-init_sn1_smp_config(void)
-{
-
-#ifdef PTC_NOTYET
-	sn_sapicid_info[0].sapicid = hard_smp_processor_id();
-#endif
-}
-
-#endif /* CONFIG_SMP */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/sn1_asm.S linux/arch/ia64/sn/sn1/sn1_asm.S
--- linux.orig/arch/ia64/sn/sn1/sn1_asm.S	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/sn1_asm.S	1970-01-01 00:00:00.000000000 +0000
@@ -1,149 +0,0 @@
-
-/*
- * Copyright (C) 2000 Silicon Graphics
- * Copyright (C) 2000 Jack Steiner (steiner@sgi.com)
- */
-
-#include <linux/config.h>
-#ifdef CONFIG_IA64_SGI_AUTOTEST
-
-// Testing only.
-// Routine will cause MCAs
-//   zzzmsa(n)
-//      n=0 MCA via duplicate TLB dropin
-//      n=0 MCA via read of garbage address
-//
-
-#define ITIR(key, ps)           ((key<<8) | (ps<<2))
-#define TLB_PAGESIZE            28                      // Use 256MB pages for now.
-
-                        .global zzzmca
-                        .proc   zzzmca
-zzzmca:
-                        alloc   loc4       = ar.pfs,2,8,1,0;;
-                        cmp.ne  p6,p0=r32,r0;;
-                        movl    r2=0x2dead
-                        movl    r3=0x3dead
-                        movl    r15=0x15dead
-                        movl    r16=0x16dead
-                        movl    r31=0x31dead
-                        movl    loc0=0x34beef
-                        movl    loc1=0x35beef
-                        movl    loc2=0x36beef
-                        movl    loc3=0x37beef
-                        movl    out0=0x42beef
-
-                        movl    r20=0x32feed;;
-                        mov     ar32=r20
-                        movl    r20=0x36feed;;
-                        mov     ar36=r20
-                        movl    r20=0x65feed;;
-                        mov     ar65=r20
-                        movl    r20=0x66feed;;
-                        mov     ar66=r20
-
-(p6)                    br.cond.sptk    1f
-
-                        rsm      0x2000;;
-                        srlz.d;
-                        mov      r11      = 1
-                        mov      r3       = ITIR(0,TLB_PAGESIZE);;
-                        mov      cr.itir  = r3
-                        mov      r10      = 0;;
-                        itr.d    dtr[r11] = r10;;
-                        mov      r11      = 2
-
-                        itr.d    dtr[r11] = r10;;
-                        br      9f
-
-1:                      movl    r8=0xfe00000048;;
-                        ld8     r9=[r8];;
-                        mf
-                        mf.a
-                        srlz.d
-
-9:                      mov     ar.pfs=loc4
-                        br.ret.sptk     rp
-
-                        .endp   zzzmca
-
-                        .global zzzspec
-                        .proc   zzzspec
-zzzspec:
-			mov	r8=r32
-			movl	r9=0xe000000000000000
-			movl	r10=0x4000;;
-			ld8.s	r16=[r8];;
-			ld8.s	r17=[r9];;
-			add	r8=r8,r10;;
-			ld8.s	r18=[r8];;
-			add	r8=r8,r10;;
-			ld8.s	r19=[r8];;
-			add	r8=r8,r10;;
-			ld8.s	r20=[r8];;
-			mov	r8=r0
-			tnat.nz	p6,p0=r16
-			tnat.nz	p7,p0=r17
-			tnat.nz	p8,p0=r18
-			tnat.nz	p9,p0=r19
-			tnat.nz	p10,p0=r20;;
-		(p6)	dep	r8=-1,r8,0,1;;
-		(p7)	dep	r8=-1,r8,1,1;;
-		(p8)	dep	r8=-1,r8,2,1;;
-		(p9)	dep	r8=-1,r8,3,1;;
-		(p10)	dep	r8=-1,r8,4,1;;
-                        br.ret.sptk     rp
-                        .endp   zzzspec
-
-                        .global zzzspec2
-                        .proc   zzzspec2
-zzzspec2:
-			cmp.eq	p6,p7=r2,r2
-			movl	r16=0xc0000a0001000020
-			;;
-			mf
-			;;
-			ld8	r9=[r16]
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			ld8	r9=[r16];;
-			cmp.ne	p6,p7=r9,r16
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			ld8	r9=[r33];;
-			cmp.ne	p6,p7=r9,r33
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			tpa	r23=r32
-			add	r20=512,r33
-			add	r21=1024,r33;;
-			ld8	r9=[r20]
-			ld8	r10=[r21];;
-			nop.i	0
-			{ .mib
-			nop.m 0
-			cmp.ne	p6,p7=r10,r33
-		(p6)	br.spnt	1f
-			}
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-			br.ret.sptk     rp
-
-                        .endp   zzzspec
-
-#endif
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/sn1_ksyms.c linux/arch/ia64/sn/sn1/sn1_ksyms.c
--- linux.orig/arch/ia64/sn/sn1/sn1_ksyms.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/sn1_ksyms.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,39 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Jesse Barnes (jbarnes@sgi.com)
- */
-
-
-/*
- * Architecture-specific kernel symbols
- */
-
-#include <linux/module.h>
-
-#include <asm/machvec.h>
-
-/*
- * I/O routines
- */
-EXPORT_SYMBOL(sn1_outb);
-EXPORT_SYMBOL(sn1_outl);
-EXPORT_SYMBOL(sn1_outw);
-EXPORT_SYMBOL(sn1_inw);
-EXPORT_SYMBOL(sn1_inb);
-EXPORT_SYMBOL(sn1_inl);
-
-/*
- * other stuff (more to be added later, cleanup then)
- */
-EXPORT_SYMBOL(sn1_pci_map_sg);
-EXPORT_SYMBOL(sn1_pci_unmap_sg);
-EXPORT_SYMBOL(sn1_pci_alloc_consistent);
-EXPORT_SYMBOL(sn1_pci_free_consistent);
-EXPORT_SYMBOL(sn1_dma_address);
-
-#include <linux/mm.h>
-EXPORT_SYMBOL(alloc_pages);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/sv.c linux/arch/ia64/sn/sn1/sv.c
--- linux.orig/arch/ia64/sn/sn1/sv.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/sv.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,551 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.  All rights reserved
- *
- * This implemenation of synchronization variables is heavily based on
- * one done by Steve Lord <lord@sgi.com>
- *
- * Paul Cassella <pwc@sgi.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-
-#include <asm/semaphore.h>
-#include <asm/hardirq.h>
-#include <asm/softirq.h>
-#include <asm/current.h>
-
-#include <asm/sn/sv.h>
-
-/* Define this to have sv_test() run some simple tests.
-   kernel_thread() must behave as expected when this is called.  */
-#undef RUN_SV_TEST
-
-#define DEBUG
-
-/* Set up some macros so sv_wait(), sv_signal(), and sv_broadcast()
-   can sanity check interrupt state on architectures where we know
-   how. */
-#ifdef DEBUG
- #define SV_DEBUG_INTERRUPT_STATE
- #ifdef __mips64
-  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x1) != 0)
-  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x1) == 0)
-  #define SV_INTERRUPT_TEST_WORKERS 31
- #elif defined(__ia64)
-  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x4000) != 0)
-  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x4000) == 0)
-  #define SV_INTERRUPT_TEST_WORKERS 4 /* simulator's slow */
- #else
-  #undef  SV_DEBUG_INTERRUPT_STATE
-  #define SV_INTERRUPT_TEST_WORKERS 4 /* reasonable? default. */
- #endif /* __mips64 */
-#endif /* DEBUG */
-
-
-/* XXX FIXME hack hack hack.  Our mips64 tree is from before the
-   switch to WQ_FLAG_EXCLUSIVE, and our ia64 tree is from after it. */
-#ifdef TASK_EXCLUSIVE
-  #undef EXCLUSIVE_IN_QUEUE
-#else
-  #define EXCLUSIVE_IN_QUEUE
-  #define TASK_EXCLUSIVE 0 /* for the set_current_state() in sv_wait() */
-#endif
-
-
-static inline void sv_lock(sv_t *sv) {
-	spin_lock(&sv->sv_lock);
-}
-
-static inline void sv_unlock(sv_t *sv) {
-	spin_unlock(&sv->sv_lock);
-}
-
-/* up() is "extern inline", so we can't pass its address to sv_wait.
-   Use this function's address instead. */
-static void up_wrapper(struct semaphore *sem) {
-	up(sem);
-}
-
-/* spin_unlock() is sometimes a macro. */
-static void spin_unlock_wrapper(spinlock_t *s) {
-	spin_unlock(s);
-}
-
-/* XXX Perhaps sv_wait() should do the switch() each time and avoid
-   the extra indirection and the need for the _wrapper functions? */
-
-static inline void sv_set_mon_type(sv_t *sv, int type) {
-	switch (type) {
-	case SV_MON_SPIN:
-		sv->sv_mon_unlock_func =
-		  (sv_mon_unlock_func_t)spin_unlock_wrapper;
-		break;
-	case SV_MON_SEMA:
-		sv->sv_mon_unlock_func =
-		  (sv_mon_unlock_func_t)up_wrapper;
-		if(sv->sv_flags & SV_INTS) {
-			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
-			       "cannot be shared with interrupts if it is a "
-			       "semaphore!\n");
-			BUG();
-		}
-		if(sv->sv_flags & SV_BHS) {
-			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
-			       "cannot be shared with bottom-halves if it is "
-			       "a semaphore!\n");
-			BUG();
-		}
-		break;
-#if 0 
-	/*
-	 * If needed, and will need to think about interrupts.  This
-	 * may be needed, for example, if someone wants to use sv's
-	 * with something like dev_base; writers need to hold two
-	 * locks. 
-	 */
-	case SV_MON_CUSTOM: 
-		{
-		struct sv_mon_custom *c = lock;
-		sv->sv_mon_unlock_func = c->sv_mon_unlock_func;
-		sv->sv_mon_lock        = c->sv_mon_lock;
-		break;
-		}
-#endif
-		
-	default:
-		printk(KERN_ERR "sv_set_mon_type: unknown type %d (0x%x)! "
-		       "(flags 0x%x)\n", type, type, sv->sv_flags);
-		BUG();
-		break;
-	}
-	sv->sv_flags |= type;
-}
-
-static inline void sv_set_ord(sv_t *sv, int ord) {
-	if (!ord)
-		ord = SV_ORDER_DEFAULT;
-
-	if (ord != SV_ORDER_FIFO && ord != SV_ORDER_LIFO) {
-		printk(KERN_EMERG "sv_set_ord: unknown order %d (0x%x)! ",
-		       ord, ord);
-		BUG();
-	}
-
-	sv->sv_flags |= ord;
-}
-
-void sv_init(sv_t *sv, sv_mon_lock_t *lock, int flags) 
-{
-	int ord = flags & SV_ORDER_MASK;
-	int type = flags & SV_MON_MASK;
-
-	/* Copy all non-order, non-type flags */
-	sv->sv_flags = (flags & ~(SV_ORDER_MASK | SV_MON_MASK));
-
-	if((sv->sv_flags & (SV_INTS | SV_BHS)) == (SV_INTS | SV_BHS)) {
-	  printk(KERN_ERR "sv_init: do not set both SV_INTS and SV_BHS, only SV_INTS.\n");
-	  BUG();
-	}
-
-	sv_set_ord(sv, ord);
-	sv_set_mon_type(sv, type);
-
-	/* If lock is NULL, we'll get it from sv_wait_compat() (and
-           ignore it in sv_signal() and sv_broadcast()). */
-	sv->sv_mon_lock = lock;
-
-	spin_lock_init(&sv->sv_lock);
-	init_waitqueue_head(&sv->sv_waiters);
-}
-
-/*
- * The associated lock must be locked on entry.  It is unlocked on return.
- *
- * Return values:
- *
- * n < 0 : interrupted,  -n jiffies remaining on timeout, or -1 if timeout == 0
- * n = 0 : timeout expired
- * n > 0 : sv_signal()'d, n jiffies remaining on timeout, or 1 if timeout == 0
- */
-signed long sv_wait(sv_t *sv, int sv_wait_flags, unsigned long timeout) 
-{
-	DECLARE_WAITQUEUE( wait, current );
-	unsigned long flags;
-	signed long ret = 0;
-
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	{
-	unsigned long flags;
-	__save_flags(flags);
-
-	if(sv->sv_flags & SV_INTS) {
-		if(SV_TEST_INTERRUPTS_ENABLED(flags)) {
-			printk(KERN_ERR "sv_wait: SV_INTS and interrupts "
-			       "enabled (flags: 0x%lx)\n", flags);
-			BUG();
-		}
-	} else {
-		if (SV_TEST_INTERRUPTS_DISABLED(flags)) {
-			printk(KERN_WARNING "sv_wait: !SV_INTS and interrupts "
-			       "disabled! (flags: 0x%lx)\n", flags);
-		}
-	}
-	}
-#endif  /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-
-	sv->sv_mon_unlock_func(sv->sv_mon_lock);
-
-	/* Add ourselves to the wait queue and set the state before
-	 * releasing the sv_lock so as to avoid racing with the
-	 * wake_up() in sv_signal() and sv_broadcast(). 
-	 */
-
-	/* don't need the _irqsave part, but there is no wq_write_lock() */
-	wq_write_lock_irqsave(&sv->sv_waiters.lock, flags);
-
-#ifdef EXCLUSIVE_IN_QUEUE
-	wait.flags |= WQ_FLAG_EXCLUSIVE;
-#endif
-
-	switch(sv->sv_flags & SV_ORDER_MASK) {
-	case SV_ORDER_FIFO:
-		__add_wait_queue_tail(&sv->sv_waiters, &wait);
-		break;
-	case SV_ORDER_FILO:
-		__add_wait_queue(&sv->sv_waiters, &wait);
-		break;
-	default:
-		printk(KERN_ERR "sv_wait: unknown order!  (sv: 0x%p, flags: 0x%x)\n",
-					sv, sv->sv_flags);
-		BUG();
-	}
-	wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags);
-
-	if(sv_wait_flags & SV_WAIT_SIG)
-		set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE  );
-	else
-		set_current_state(TASK_EXCLUSIVE | TASK_UNINTERRUPTIBLE);
-
-	spin_unlock(&sv->sv_lock);
-
-	if(sv->sv_flags & SV_INTS)
-		local_irq_enable();
-	else if(sv->sv_flags & SV_BHS)
-		local_bh_enable();
-
-	if (timeout)
-		ret = schedule_timeout(timeout);
-	else
-		schedule();
-
-	if(current->state != TASK_RUNNING) /* XXX Is this possible? */ {
-		printk(KERN_ERR "sv_wait: state not TASK_RUNNING after "
-		       "schedule().\n");
-		set_current_state(TASK_RUNNING);
-	}
-
-	remove_wait_queue(&sv->sv_waiters, &wait);
-
-	/* Return cases:
-	   - woken by a sv_signal/sv_broadcast
-	   - woken by a signal
-	   - woken by timeout expiring
-	*/
-
-	/* XXX This isn't really accurate; we may have been woken
-           before the signal anyway.... */
-	if(signal_pending(current))
-		return timeout ? -ret : -1;
-	return timeout ? ret : 1;
-}
-
-
-void sv_signal(sv_t *sv) 
-{
-	/* If interrupts can acquire this lock, they can also acquire the
-	   sv_mon_lock, which we must already have to have called this, so
-	   interrupts must be disabled already.  If interrupts cannot
-	   contend for this lock, we don't have to worry about it. */
-
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	if(sv->sv_flags & SV_INTS) {
-		unsigned long flags;
-		__save_flags(flags);
-		if(SV_TEST_INTERRUPTS_ENABLED(flags))
-			printk(KERN_ERR "sv_signal: SV_INTS and "
-			"interrupts enabled! (flags: 0x%lx)\n", flags);
-	}
-#endif /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-	wake_up(&sv->sv_waiters);
-	sv_unlock(sv);
-}
-
-void sv_broadcast(sv_t *sv) 
-{
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	if(sv->sv_flags & SV_INTS) {
-		unsigned long flags;
-		__save_flags(flags);
-		if(SV_TEST_INTERRUPTS_ENABLED(flags))
-			printk(KERN_ERR "sv_broadcast: SV_INTS and "
-			       "interrupts enabled! (flags: 0x%lx)\n", flags);
-	}
-#endif /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-	wake_up_all(&sv->sv_waiters);
-	sv_unlock(sv);
-}
-
-void sv_destroy(sv_t *sv) 
-{
-	if(!spin_trylock(&sv->sv_lock)) {
-		printk(KERN_ERR "sv_destroy: someone else has sv 0x%p locked!\n", sv);
-		BUG();
-	}
-
-	/* XXX Check that the waitqueue is empty? 
-	       Mark the sv destroyed?
-	*/
-}
-
-
-#ifdef RUN_SV_TEST
-
-static DECLARE_MUTEX_LOCKED(talkback);
-static DECLARE_MUTEX_LOCKED(sem);
-sv_t sv;
-sv_t sv_filo;
-
-static int sv_test_1_w(void *arg) 
-{
-	printk("sv_test_1_w: acquiring spinlock 0x%p...\n", arg);
-
-	spin_lock((spinlock_t*)arg);
-	printk("sv_test_1_w: spinlock acquired, waking sv_test_1_s.\n");
-
-	up(&sem);
-
-	printk("sv_test_1_w: sv_spin_wait()'ing.\n");
-
-	sv_spin_wait(&sv, arg);
-
-	printk("sv_test_1_w: talkback.\n");
-	up(&talkback);
-
-	printk("sv_test_1_w: exiting.\n");
-	return 0;
-}
-
-static int sv_test_1_s(void *arg) 
-{
-	printk("sv_test_1_s: waiting for semaphore.\n");
-	down(&sem);
-	printk("sv_test_1_s: semaphore acquired.  Acquiring spinlock.\n");
-	spin_lock((spinlock_t*)arg);
-	printk("sv_test_1_s: spinlock acquired.  sv_signaling.\n");
-	sv_signal(&sv);
-	printk("sv_test_1_s: talkback.\n");
-	up(&talkback);
-	printk("sv_test_1_s: exiting.\n");
-	return 0;
-
-}
-
-static int count;
-static DECLARE_MUTEX(monitor);
-
-static int sv_test_2_w(void *arg) 
-{
-	int dummy = count++;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	up(&talkback);
-	printk("sv_test_2_w: thread %d started, sv_waiting.\n", dummy);
-	sv_sema_wait(sv, &monitor);
-	printk("sv_test_2_w: thread %d woken, exiting.\n", dummy);
-	up(&sem);
-	return 0;
-}
-
-static int sv_test_2_s_1(void *arg) 
-{
-	int i;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	for(i = 0; i < 3; i++) {
-		printk("sv_test_2_s_1: waking one thread.\n");
-		sv_signal(sv);
-		down(&sem);
-	}
-
-	printk("sv_test_2_s_1: signaling and broadcasting again.  Nothing should happen.\n");
-	sv_signal(sv);
-	sv_broadcast(sv);
-	sv_signal(sv);
-	sv_broadcast(sv);
-
-	printk("sv_test_2_s_1: talkbacking.\n");
-	up(&talkback);
-	up(&monitor);
-	return 0;
-}
-
-static int sv_test_2_s(void *arg) 
-{
-	int i;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	for(i = 0; i < 3; i++) {
-		printk("sv_test_2_s: waking one thread (should be %d.)\n", i);
-		sv_signal(sv);
-		down(&sem);
-	}
-
-	printk("sv_test_3_s: waking remaining threads with broadcast.\n");
-	sv_broadcast(sv);
-	for(; i < 10; i++)
-		down(&sem);
-
-	printk("sv_test_3_s: sending talkback.\n");
-	up(&talkback);
-
-	printk("sv_test_3_s: exiting.\n");
-	up(&monitor);
-	return 0;
-}
-
-
-static void big_test(sv_t *sv) 
-{
-	int i;
-
-	count = 0;
-
-	for(i = 0; i < 3; i++) {
-		printk("big_test: spawning thread %d.\n", i);
-		kernel_thread(sv_test_2_w, sv, 0);
-		down(&talkback);
-	}
-
-	printk("big_test: spawning first wake-up thread.\n");
-	kernel_thread(sv_test_2_s_1, sv, 0);
-
-	down(&talkback);
-	printk("big_test: talkback happened.\n");
-
-
-	for(i = 3; i < 13; i++) {
-		printk("big_test: spawning thread %d.\n", i);
-		kernel_thread(sv_test_2_w, sv, 0);
-		down(&talkback);
-	}
-
-	printk("big_test: spawning wake-up thread.\n");
-	kernel_thread(sv_test_2_s, sv, 0);
-
-	down(&talkback);
-}
-
-sv_t int_test_sv;
-spinlock_t int_test_spin = SPIN_LOCK_UNLOCKED;
-int int_test_ready;
-static int irqtestcount;
-
-static int interrupt_test_worker(void *unused) 
-{
-	int id = ++irqtestcount;
-	int it = 0;
-			unsigned long flags, flags2;
-
-	printk("ITW: thread %d started.\n", id);
-
-	while(1) {
-		__save_flags(flags2);
-		if(jiffies % 3) {
-			printk("ITW %2d %5d: irqsaving          (%lx)\n", id, it, flags2);
-			spin_lock_irqsave(&int_test_spin, flags);
-		} else {
-			printk("ITW %2d %5d: spin_lock_irqing   (%lx)\n", id, it, flags2);
-			spin_lock_irq(&int_test_spin);
-		}
-
-		__save_flags(flags2);
-		printk("ITW %2d %5d: locked, sv_waiting (%lx).\n", id, it, flags2);
-		sv_wait(&int_test_sv, 0, 0);
-
-		__save_flags(flags2);
-		printk("ITW %2d %5d: wait finished      (%lx), pausing\n", id, it, flags2);
-		set_current_state(TASK_INTERRUPTIBLE);
-		schedule_timeout(jiffies & 0xf);
-		if(current->state != TASK_RUNNING)
-		  printk("ITW:  current->state isn't RUNNING after schedule!\n");
-		it++;
-	}
-}
-
-static void interrupt_test(void) 
-{
-	int i;
-
-	printk("interrupt_test: initing sv.\n");
-	sv_init(&int_test_sv, &int_test_spin, SV_MON_SPIN | SV_INTS);
-
-	for(i = 0; i < SV_INTERRUPT_TEST_WORKERS; i++) {
-		printk("interrupt_test: starting test thread %d.\n", i);
-		kernel_thread(interrupt_test_worker, 0, 0);
-	}
-	printk("interrupt_test: done with init part.\n");
-	int_test_ready = 1;
-}
-
-int sv_test(void) 
-{
-	spinlock_t s = SPIN_LOCK_UNLOCKED;
-
-	sv_init(&sv, &s, SV_MON_SPIN);
-	printk("sv_test: starting sv_test_1_w.\n");
-	kernel_thread(sv_test_1_w, &s, 0);
-	printk("sv_test: starting sv_test_1_s.\n");
-	kernel_thread(sv_test_1_s, &s, 0);
-
-	printk("sv_test: waiting for talkback.\n");
-	down(&talkback); down(&talkback);
-	printk("sv_test: talkback happened, sv_destroying.\n");
-	sv_destroy(&sv);
-
-	count = 0;
-
-	printk("sv_test: beginning big_test on sv.\n");
-
-	sv_init(&sv, &monitor, SV_MON_SEMA);
-	big_test(&sv);
-	sv_destroy(&sv);
-
-	printk("sv_test: beginning big_test on sv_filo.\n");
-	sv_init(&sv_filo, &monitor, SV_MON_SEMA | SV_ORDER_FILO);
-	big_test(&sv_filo);
-	sv_destroy(&sv_filo);
-
-	interrupt_test();
-
-	printk("sv_test: done.\n");
-	return 0;
-}
-
-__initcall(sv_test);
-
-#endif /* RUN_SV_TEST */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/sn1/synergy.c linux/arch/ia64/sn/sn1/synergy.c
--- linux.orig/arch/ia64/sn/sn1/synergy.c	2001-04-05 19:51:47.000000000 +0000
+++ linux/arch/ia64/sn/sn1/synergy.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,429 +0,0 @@
-
-/*
- * SN1 Platform specific synergy Support
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
- */
-
-
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/spinlock.h>
-#include <linux/proc_fs.h>
-
-#include <asm/ptrace.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/smp.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/synergy.h>
-
-int bit_pos_to_irq(int bit);
-void setclear_mask_b(int irq, int cpuid, int set);
-void setclear_mask_a(int irq, int cpuid, int set);
-void * kmalloc(size_t size, int flags);
-
-
-void
-synergy_intr_alloc(int bit, int cpuid) {
-	return;
-}
-
-int
-synergy_intr_connect(int bit, 
-		int cpuid)
-{
-	int irq;
-	unsigned is_b;
-
-	irq = bit_pos_to_irq(bit);
-
-	is_b = (cpuid_to_slice(cpuid)) & 1;
-	if (is_b) {
-		setclear_mask_b(irq,cpuid,1);
-		setclear_mask_a(irq,cpuid, 0);
-	} else {
-		setclear_mask_a(irq, cpuid, 1);
-		setclear_mask_b(irq, cpuid, 0);
-	}
-	return 0;
-}
-void
-setclear_mask_a(int irq, int cpuid, int set)
-{
-	int synergy;
-	int nasid;
-	int reg_num;
-	unsigned long mask;
-	unsigned long addr;
-	unsigned long reg;
-	unsigned long val;
-	int my_cnode, my_synergy;
-	int target_cnode, target_synergy;
-
-        /*
-         * Perform some idiot checks ..
-         */
-        if ( (irq < 0) || (irq > 255) ||
-                (cpuid < 0) || (cpuid > 512) ) {
-                printk("clear_mask_a: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
-		return;
-	}
-
-	target_cnode = cpuid_to_cnodeid(cpuid);
-	target_synergy = cpuid_to_synergy(cpuid);
-	my_cnode = cpuid_to_cnodeid(smp_processor_id());
-	my_synergy = cpuid_to_synergy(smp_processor_id());
-
-	reg_num = irq / 64;
-	mask = 1;
-	mask <<= (irq % 64);
-	switch (reg_num) {
-		case 0: 
-			reg = VEC_MASK0A;
-			addr = VEC_MASK0A_ADDR;
-			break;
-		case 1: 
-			reg = VEC_MASK1A;
-			addr = VEC_MASK1A_ADDR;
-			break;
-		case 2: 
-			reg = VEC_MASK2A;
-			addr = VEC_MASK2A_ADDR;
-			break;
-		case 3: 
-			reg = VEC_MASK3A;
-			addr = VEC_MASK3A_ADDR;
-			break;
-		default:
-			reg = addr = 0;
-			break;
-	}
-	if (my_cnode == target_cnode && my_synergy == target_synergy) {
-		// local synergy
-		val = READ_LOCAL_SYNERGY_REG(addr);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		WRITE_LOCAL_SYNERGY_REG(addr, val);
-		val = READ_LOCAL_SYNERGY_REG(addr);
-	} else { /* remote synergy */
-		synergy = cpuid_to_synergy(cpuid);
-		nasid = cpuid_to_nasid(cpuid);
-		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
-	}
-}
-
-void
-setclear_mask_b(int irq, int cpuid, int set)
-{
-	int synergy;
-	int nasid;
-	int reg_num;
-	unsigned long mask;
-	unsigned long addr;
-	unsigned long reg;
-	unsigned long val;
-	int my_cnode, my_synergy;
-	int target_cnode, target_synergy;
-
-	/*
-	 * Perform some idiot checks ..
-	 */
-	if ( (irq < 0) || (irq > 255) ||
-		(cpuid < 0) || (cpuid > 512) ) {
-		printk("clear_mask_b: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
-		return;
-	}
-
-	target_cnode = cpuid_to_cnodeid(cpuid);
-	target_synergy = cpuid_to_synergy(cpuid);
-	my_cnode = cpuid_to_cnodeid(smp_processor_id());
-	my_synergy = cpuid_to_synergy(smp_processor_id());
-
-	reg_num = irq / 64;
-	mask = 1;
-	mask <<= (irq % 64);
-	switch (reg_num) {
-		case 0: 
-			reg = VEC_MASK0B;
-			addr = VEC_MASK0B_ADDR;
-			break;
-		case 1: 
-			reg = VEC_MASK1B;
-			addr = VEC_MASK1B_ADDR;
-			break;
-		case 2: 
-			reg = VEC_MASK2B;
-			addr = VEC_MASK2B_ADDR;
-			break;
-		case 3: 
-			reg = VEC_MASK3B;
-			addr = VEC_MASK3B_ADDR;
-			break;
-		default:
-			reg = addr = 0;
-			break;
-	}
-	if (my_cnode == target_cnode && my_synergy == target_synergy) {
-		// local synergy
-		val = READ_LOCAL_SYNERGY_REG(addr);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		WRITE_LOCAL_SYNERGY_REG(addr, val);
-		val = READ_LOCAL_SYNERGY_REG(addr);
-	} else { /* remote synergy */
-		synergy = cpuid_to_synergy(cpuid);
-		nasid = cpuid_to_nasid(cpuid);
-		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
-	}
-}
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-
-/*
- * Synergy perf registers. Multiplexed via timer_interrupt
- */
-static struct proc_dir_entry *synergy_perf_proc = NULL;
-
-/*
- * read handler for /proc/synergy
- */
-static int
-synergy_perf_read_proc (char *page, char **start, off_t off,
-                                 int count, int *eof, void *data)
-{
-	cnodeid_t       cnode;
-	nodepda_t       *npdap;
-	synergy_perf_t	*p;
-	int		len = 0;
-
-	len += sprintf(page+len, "# cnode module slot event synergy-A synergy-B\n");
-
-	/* walk the event list for each node */
-	for (cnode=0; cnode < numnodes; cnode++) {
-		npdap = NODEPDA(cnode);
-		if (npdap->synergy_perf_enabled == 0) {
-			len += sprintf(page+len, "# DISABLED\n");
-			break;
-		}
-
-		spin_lock_irq(&npdap->synergy_perf_lock);
-		for (p = npdap->synergy_perf_first; p;) {
-			uint64_t cnt_a=0, cnt_b=0;
-
-			if (p->intervals > 0) {
-				cnt_a = p->counts[0] * npdap->synergy_active_intervals / p->intervals;
-				cnt_b = p->counts[1] * npdap->synergy_active_intervals / p->intervals;
-			}
-
-			len += sprintf(page+len, "%d %d %d %12lx %lu %lu\n",
-				(int)cnode, (int)npdap->module_id, (int)npdap->slotdesc,
-				p->modesel, cnt_a, cnt_b);
-
-			p = p->next;
-			if (p == npdap->synergy_perf_first)
-				break;
-		}
-		spin_unlock_irq(&npdap->synergy_perf_lock);
-	}
-
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return len;
-}
-
-static int
-synergy_perf_append(uint64_t modesel)
-{
-	int		cnode;
-	nodepda_t       *npdap;
-	synergy_perf_t	*p;
-	int		err = 0;
-
-	/* bit 45 is enable */
-	modesel |= (1UL << 45);
-
-	for (cnode=0; cnode < numnodes; cnode++) {
-		/* for each node, insert a new synergy_perf entry */
-		if ((npdap = NODEPDA(cnode)) == NULL) {
-			printk("synergy_perf_append: cnode=%d NODEPDA(cnode)==NULL, nodepda=%p\n", cnode, nodepda);
-			continue;
-		}
-
-		/* XX use kmem_alloc_node() when it is implemented */
-		p = (synergy_perf_t *)kmalloc(sizeof(synergy_perf_t), GFP_KERNEL);
-		if (p == NULL)
-			err = -ENOMEM;
-		else {
-			memset(p, 0, sizeof(synergy_perf_t));
-			p->modesel = modesel;
-			if (npdap->synergy_perf_data == NULL) {
-				/* circular list */
-				p->next = p;
-				npdap->synergy_perf_data = p;
-				npdap->synergy_perf_first = p;
-			}
-			else {
-				/*
-				 * Jumble up the insertion order so we get better sampling.
-				 * Once the list is complete, "first" stays the same so the
-				 * reporting order is consistent.
-				 */
-				p->next = npdap->synergy_perf_first->next;
-				npdap->synergy_perf_first->next = p;
-				npdap->synergy_perf_first = p->next;
-			}
-		}
-	}
-
-	return err;
-}
-
-static int
-synergy_perf_write_proc (struct file *file, const char *buffer,
-                                unsigned long count, void *data)
-{
-	int		cnode;
-	nodepda_t       *npdap;
-	uint64_t	modesel;
-	char		cmd[64];
-	extern long	atoi(char *);
-    
-	if (count == sizeof(uint64_t)) {
-	    if (copy_from_user(&modesel, buffer, sizeof(uint64_t)))
-		    return -EFAULT;
-	    synergy_perf_append(modesel);
-	}
-	else {
-	    if (copy_from_user(cmd, buffer, count < sizeof(cmd) ? count : sizeof(cmd)))
-		    return -EFAULT;
-	    if (strncmp(cmd, "enable", 6) == 0) {
-		/* enable counting */
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_enabled = 1;
-		}
-		printk("NOTICE: synergy perf counting enabled\n");
-	    }
-	    else
-	    if (strncmp(cmd, "disable", 7) == 0) {
-		/* disable counting */
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_enabled = 0;
-		}
-		printk("NOTICE: synergy perf counting disabled\n");
-	    }
-	    else
-	    if (strncmp(cmd, "frequency", 9) == 0) {
-		/* set the update frequency (timer-interrupts per update) */
-		int freq;
-
-		if (count < 12)
-			return -EINVAL;
-		freq = atoi(cmd + 10);
-		if (freq <= 0 || freq > 100)
-			return -EINVAL;
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_freq = (uint64_t)freq;
-		}
-		printk("NOTICE: synergy perf freq set to %d\n", freq);
-	    }
-	    else
-		return -EINVAL;
-	}
-	
-	return count;
-}
-
-void
-synergy_perf_update(int cpu)
-{
-	nasid_t		nasid;
-	cnodeid_t       cnode = cpuid_to_cnodeid(cpu);
-	struct nodepda_s *npdap;
-	extern struct nodepda_s *nodepda;
-
-	if (nodepda == NULL || (npdap=NODEPDA(cnode)) == NULL || npdap->synergy_perf_enabled == 0 ||
-		npdap->synergy_perf_data == NULL) {
-		/* I/O not initialized, or not enabled, or no events to monitor */
-		return;
-	}
-
-	if (npdap->synergy_inactive_intervals++ % npdap->synergy_perf_freq != 0) {
-		/* don't multiplex on every timer interrupt */
-		return;
-	}
-
-	/*
-	 * Read registers for last interval and increment counters.
-	 * Hold the per-node synergy_perf_lock so concurrent readers get
-	 * consistent values.
-	 */
-	spin_lock_irq(&npdap->synergy_perf_lock);
-
-	nasid = cpuid_to_nasid(cpu);
-	npdap->synergy_active_intervals++;
-	npdap->synergy_perf_data->intervals++;
-
-	npdap->synergy_perf_data->counts[0] += 0xffffffffffUL &
-		REMOTE_SYNERGY_LOAD(nasid, 0, PERF_CNTR0_A);
-
-	npdap->synergy_perf_data->counts[1] += 0xffffffffffUL &
-		REMOTE_SYNERGY_LOAD(nasid, 1, PERF_CNTR0_B);
-
-	/* skip to next in circular list */
-	npdap->synergy_perf_data = npdap->synergy_perf_data->next;
-
-	spin_unlock_irq(&npdap->synergy_perf_lock);
-
-	/* set the counter 0 selection modes for both A and B */
-	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTL0_A, npdap->synergy_perf_data->modesel);
-	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTL0_B, npdap->synergy_perf_data->modesel);
-
-	/* and reset the counter registers to zero */
-	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTR0_A, 0UL);
-	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTR0_B, 0UL);
-}
-
-void
-synergy_perf_init(void)
-{
-        if ((synergy_perf_proc = create_proc_entry("synergy", 0644, NULL)) != NULL) {
-                synergy_perf_proc->read_proc = synergy_perf_read_proc;
-                synergy_perf_proc->write_proc = synergy_perf_write_proc;
-                printk("markgw: synergy_perf_init()\n");
-        }
-}
-
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/sn/tools/make_textsym linux/arch/ia64/sn/tools/make_textsym
--- linux.orig/arch/ia64/sn/tools/make_textsym	2001-01-04 21:00:15.000000000 +0000
+++ linux/arch/ia64/sn/tools/make_textsym	2002-08-01 06:42:28.000000000 +0000
@@ -1,5 +1,14 @@
 #!/bin/sh
+#
 # Build a textsym file for use in the Arium ITP probe.
+#
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+#
 
 help() {
 cat <<END
@@ -30,108 +39,132 @@
 
 LINUX=${1:-vmlinux}
 TEXTSYM=${2:-${LINUX}.sym}
+TMPSYM=${2:-${LINUX}.sym.tmp}
+trap "/bin/rm -f $TMPSYM" 0
 
 [ -f $VMLINUX ] || help
 
+$OBJDUMP -t $LINUX | sort > $TMPSYM
+SN1=`egrep "dig_setup|Synergy_da_indr" $TMPSYM|wc -l`
+
+# Dataprefix and textprefix correspond to the VGLOBAL_BASE and VPERNODE_BASE.
+# Eventually, these values should be:
+#	dataprefix	ffffffff
+#	textprefix	fffffffe
+# but right now they're still changing, so make them dynamic.
+dataprefix=`awk ' / \.data	/ { print substr($1, 0, 8) ; exit ; }' $TMPSYM`
+textprefix=`awk ' / \.text	/ { print substr($1, 0, 8) ; exit ; }' $TMPSYM`
 
 # pipe everything thru sort
 echo "TEXTSYM V1.0"
 (cat <<END 
-GLOBAL | e000000000500000 | CODE | VEC_VHPT_Translation_0000
-GLOBAL | e000000000500400 | CODE | VEC_ITLB_0400
-GLOBAL | e000000000500800 | CODE | VEC_DTLB_0800
-GLOBAL | e000000000500c00 | CODE | VEC_Alt_ITLB_0c00
-GLOBAL | e000000000501000 | CODE | VEC_Alt_DTLB_1000
-GLOBAL | e000000000501400 | CODE | VEC_Data_nested_TLB_1400
-GLOBAL | e000000000501800 | CODE | VEC_Instruction_Key_Miss_1800
-GLOBAL | e000000000501c00 | CODE | VEC_Data_Key_Miss_1c00
-GLOBAL | e000000000502000 | CODE | VEC_Dirty-bit_2000
-GLOBAL | e000000000502400 | CODE | VEC_Instruction_Access-bit_2400
-GLOBAL | e000000000502800 | CODE | VEC_Data_Access-bit_2800
-GLOBAL | e000000000502c00 | CODE | VEC_Break_instruction_2c00
-GLOBAL | e000000000503000 | CODE | VEC_External_Interrupt_3000
-GLOBAL | e000000000503400 | CODE | VEC_Reserved_3400
-GLOBAL | e000000000503800 | CODE | VEC_Reserved_3800
-GLOBAL | e000000000503c00 | CODE | VEC_Reserved_3c00
-GLOBAL | e000000000504000 | CODE | VEC_Reserved_4000
-GLOBAL | e000000000504400 | CODE | VEC_Reserved_4400
-GLOBAL | e000000000504800 | CODE | VEC_Reserved_4800
-GLOBAL | e000000000504c00 | CODE | VEC_Reserved_4c00
-GLOBAL | e000000000505000 | CODE | VEC_Page_Not_Present_5000
-GLOBAL | e000000000505100 | CODE | VEC_Key_Permission_5100
-GLOBAL | e000000000505200 | CODE | VEC_Instruction_Access_Rights_5200
-GLOBAL | e000000000505300 | CODE | VEC_Data_Access_Rights_5300
-GLOBAL | e000000000505400 | CODE | VEC_General_Exception_5400
-GLOBAL | e000000000505500 | CODE | VEC_Disabled_FP-Register_5500
-GLOBAL | e000000000505600 | CODE | VEC_Nat_Consumption_5600
-GLOBAL | e000000000505700 | CODE | VEC_Speculation_5700
-GLOBAL | e000000000505800 | CODE | VEC_Reserved_5800
-GLOBAL | e000000000505900 | CODE | VEC_Debug_5900
-GLOBAL | e000000000505a00 | CODE | VEC_Unaligned_Reference_5a00
-GLOBAL | e000000000505b00 | CODE | VEC_Unsupported_Data_Reference_5b00
-GLOBAL | e000000000505c00 | CODE | VEC_Floating-Point_Fault_5c00
-GLOBAL | e000000000505d00 | CODE | VEC_Floating_Point_Trap_5d00
-GLOBAL | e000000000505e00 | CODE | VEC_Lower_Privilege_Tranfer_Trap_5e00
-GLOBAL | e000000000505f00 | CODE | VEC_Taken_Branch_Trap_5f00
-GLOBAL | e000000000506000 | CODE | VEC_Single_Step_Trap_6000
-GLOBAL | e000000000506100 | CODE | VEC_Reserved_6100
-GLOBAL | e000000000506200 | CODE | VEC_Reserved_6200
-GLOBAL | e000000000506300 | CODE | VEC_Reserved_6300
-GLOBAL | e000000000506400 | CODE | VEC_Reserved_6400
-GLOBAL | e000000000506500 | CODE | VEC_Reserved_6500
-GLOBAL | e000000000506600 | CODE | VEC_Reserved_6600
-GLOBAL | e000000000506700 | CODE | VEC_Reserved_6700
-GLOBAL | e000000000506800 | CODE | VEC_Reserved_6800
-GLOBAL | e000000000506900 | CODE | VEC_IA-32_Exeception_6900
-GLOBAL | e000000000506a00 | CODE | VEC_IA-32_Intercept_6a00
-GLOBAL | e000000000506b00 | CODE | VEC_IA-32_Interrupt_6b00
-GLOBAL | e000000000506c00 | CODE | VEC_Reserved_6c00
-GLOBAL | e000000000506d00 | CODE | VEC_Reserved_6d00
-GLOBAL | e000000000506e00 | CODE | VEC_Reserved_6e00
-GLOBAL | e000000000506f00 | CODE | VEC_Reserved_6f00
-GLOBAL | e000000000507000 | CODE | VEC_Reserved_7000
-GLOBAL | e000000000507100 | CODE | VEC_Reserved_7100
-GLOBAL | e000000000507200 | CODE | VEC_Reserved_7200
-GLOBAL | e000000000507300 | CODE | VEC_Reserved_7300
-GLOBAL | e000000000507400 | CODE | VEC_Reserved_7400
-GLOBAL | e000000000507500 | CODE | VEC_Reserved_7500
-GLOBAL | e000000000507600 | CODE | VEC_Reserved_7600
-GLOBAL | e000000000507700 | CODE | VEC_Reserved_7700
-GLOBAL | e000000000507800 | CODE | VEC_Reserved_7800
-GLOBAL | e000000000507900 | CODE | VEC_Reserved_7900
-GLOBAL | e000000000507a00 | CODE | VEC_Reserved_7a00
-GLOBAL | e000000000507b00 | CODE | VEC_Reserved_7b00
-GLOBAL | e000000000507c00 | CODE | VEC_Reserved_7c00
-GLOBAL | e000000000507d00 | CODE | VEC_Reserved_7d00
-GLOBAL | e000000000507e00 | CODE | VEC_Reserved_7e00
-GLOBAL | e000000000507f00 | CODE | VEC_Reserved_7f00
+GLOBAL | ${textprefix}00400000 | CODE | VEC_VHPT_Translation_0000
+GLOBAL | ${textprefix}00400400 | CODE | VEC_ITLB_0400
+GLOBAL | ${textprefix}00400800 | CODE | VEC_DTLB_0800
+GLOBAL | ${textprefix}00400c00 | CODE | VEC_Alt_ITLB_0c00
+GLOBAL | ${textprefix}00401000 | CODE | VEC_Alt_DTLB_1000
+GLOBAL | ${textprefix}00401400 | CODE | VEC_Data_nested_TLB_1400
+GLOBAL | ${textprefix}00401800 | CODE | VEC_Instruction_Key_Miss_1800
+GLOBAL | ${textprefix}00401c00 | CODE | VEC_Data_Key_Miss_1c00
+GLOBAL | ${textprefix}00402000 | CODE | VEC_Dirty-bit_2000
+GLOBAL | ${textprefix}00402400 | CODE | VEC_Instruction_Access-bit_2400
+GLOBAL | ${textprefix}00402800 | CODE | VEC_Data_Access-bit_2800
+GLOBAL | ${textprefix}00402c00 | CODE | VEC_Break_instruction_2c00
+GLOBAL | ${textprefix}00403000 | CODE | VEC_External_Interrupt_3000
+GLOBAL | ${textprefix}00403400 | CODE | VEC_Reserved_3400
+GLOBAL | ${textprefix}00403800 | CODE | VEC_Reserved_3800
+GLOBAL | ${textprefix}00403c00 | CODE | VEC_Reserved_3c00
+GLOBAL | ${textprefix}00404000 | CODE | VEC_Reserved_4000
+GLOBAL | ${textprefix}00404400 | CODE | VEC_Reserved_4400
+GLOBAL | ${textprefix}00404800 | CODE | VEC_Reserved_4800
+GLOBAL | ${textprefix}00404c00 | CODE | VEC_Reserved_4c00
+GLOBAL | ${textprefix}00405000 | CODE | VEC_Page_Not_Present_5000
+GLOBAL | ${textprefix}00405100 | CODE | VEC_Key_Permission_5100
+GLOBAL | ${textprefix}00405200 | CODE | VEC_Instruction_Access_Rights_5200
+GLOBAL | ${textprefix}00405300 | CODE | VEC_Data_Access_Rights_5300
+GLOBAL | ${textprefix}00405400 | CODE | VEC_General_Exception_5400
+GLOBAL | ${textprefix}00405500 | CODE | VEC_Disabled_FP-Register_5500
+GLOBAL | ${textprefix}00405600 | CODE | VEC_Nat_Consumption_5600
+GLOBAL | ${textprefix}00405700 | CODE | VEC_Speculation_5700
+GLOBAL | ${textprefix}00405800 | CODE | VEC_Reserved_5800
+GLOBAL | ${textprefix}00405900 | CODE | VEC_Debug_5900
+GLOBAL | ${textprefix}00405a00 | CODE | VEC_Unaligned_Reference_5a00
+GLOBAL | ${textprefix}00405b00 | CODE | VEC_Unsupported_Data_Reference_5b00
+GLOBAL | ${textprefix}00405c00 | CODE | VEC_Floating-Point_Fault_5c00
+GLOBAL | ${textprefix}00405d00 | CODE | VEC_Floating_Point_Trap_5d00
+GLOBAL | ${textprefix}00405e00 | CODE | VEC_Lower_Privilege_Tranfer_Trap_5e00
+GLOBAL | ${textprefix}00405f00 | CODE | VEC_Taken_Branch_Trap_5f00
+GLOBAL | ${textprefix}00406000 | CODE | VEC_Single_Step_Trap_6000
+GLOBAL | ${textprefix}00406100 | CODE | VEC_Reserved_6100
+GLOBAL | ${textprefix}00406200 | CODE | VEC_Reserved_6200
+GLOBAL | ${textprefix}00406300 | CODE | VEC_Reserved_6300
+GLOBAL | ${textprefix}00406400 | CODE | VEC_Reserved_6400
+GLOBAL | ${textprefix}00406500 | CODE | VEC_Reserved_6500
+GLOBAL | ${textprefix}00406600 | CODE | VEC_Reserved_6600
+GLOBAL | ${textprefix}00406700 | CODE | VEC_Reserved_6700
+GLOBAL | ${textprefix}00406800 | CODE | VEC_Reserved_6800
+GLOBAL | ${textprefix}00406900 | CODE | VEC_IA-32_Exeception_6900
+GLOBAL | ${textprefix}00406a00 | CODE | VEC_IA-32_Intercept_6a00
+GLOBAL | ${textprefix}00406b00 | CODE | VEC_IA-32_Interrupt_6b00
+GLOBAL | ${textprefix}00406c00 | CODE | VEC_Reserved_6c00
+GLOBAL | ${textprefix}00406d00 | CODE | VEC_Reserved_6d00
+GLOBAL | ${textprefix}00406e00 | CODE | VEC_Reserved_6e00
+GLOBAL | ${textprefix}00406f00 | CODE | VEC_Reserved_6f00
+GLOBAL | ${textprefix}00407000 | CODE | VEC_Reserved_7000
+GLOBAL | ${textprefix}00407100 | CODE | VEC_Reserved_7100
+GLOBAL | ${textprefix}00407200 | CODE | VEC_Reserved_7200
+GLOBAL | ${textprefix}00407300 | CODE | VEC_Reserved_7300
+GLOBAL | ${textprefix}00407400 | CODE | VEC_Reserved_7400
+GLOBAL | ${textprefix}00407500 | CODE | VEC_Reserved_7500
+GLOBAL | ${textprefix}00407600 | CODE | VEC_Reserved_7600
+GLOBAL | ${textprefix}00407700 | CODE | VEC_Reserved_7700
+GLOBAL | ${textprefix}00407800 | CODE | VEC_Reserved_7800
+GLOBAL | ${textprefix}00407900 | CODE | VEC_Reserved_7900
+GLOBAL | ${textprefix}00407a00 | CODE | VEC_Reserved_7a00
+GLOBAL | ${textprefix}00407b00 | CODE | VEC_Reserved_7b00
+GLOBAL | ${textprefix}00407c00 | CODE | VEC_Reserved_7c00
+GLOBAL | ${textprefix}00407d00 | CODE | VEC_Reserved_7d00
+GLOBAL | ${textprefix}00407e00 | CODE | VEC_Reserved_7e00
+GLOBAL | ${textprefix}00407f00 | CODE | VEC_Reserved_7f00
 END
 
-$OBJDUMP -t $LINUX | sort | awk '
-/empty_zero_page/ {start=1}
-/e0000000/ {
+
+awk '
+/__start_gate_section/ {start=1}
+/^'${dataprefix}\|${textprefix}'/ {
 	if ($4 == ".kdb")
 		next
 	if (start && substr($NF,1,1) != "0") {
 		type = substr($0,26,5)
 		if (type == ".text")
 			printf "GLOBAL | %s | CODE | %s\n", $1, $NF
-		else
-			printf "GLOBAL | %s | DATA | %s | %d\n", $1, $NF, $(NF-1)
+		else {
+			n = 0
+			s = $(NF-1)
+			while (length(s) > 0) {
+				n = n*16 + substr(s,1,1)
+				s = substr(s,2)
+			}
+			printf "GLOBAL | %s | DATA | %s | %d\n", $1, $NF, n
+		}
 	}
 	if($NF == "_end") 
 		exit
 
 }
-' ) | egrep -v " __device| __vendor" | awk '
+' $TMPSYM ) | egrep -v " __device| __vendor" | awk -v sn1="$SN1" '
 /GLOBAL/ {
 	print $0
-	print substr($0,1,9) substr($0,18,18) "Phy_" substr($0,36)
+	if (sn1 != 0) {
+		/* 32 bits of sn1 physical addrs, */
+		print substr($0,1,9) substr($0,18,18) "Phy_" substr($0,36)
+	} else {
+		/* 38 bits of sn2 physical addrs, need addr space bits */
+		print substr($0,1,9) "30" substr($0,18,18) "Phy_" substr($0,36)
+	}
 
 } ' | sort -k3
 
-
-
 N=`wc -l $TEXTSYM|awk '{print $1}'`
 echo "Generated TEXTSYM file" >&2
 echo "  $LINUX --> $TEXTSYM" >&2
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/tools/print_offsets.c linux/arch/ia64/tools/print_offsets.c
--- linux.orig/arch/ia64/tools/print_offsets.c	2001-11-09 22:26:17.000000000 +0000
+++ linux/arch/ia64/tools/print_offsets.c	2002-08-01 06:42:47.000000000 +0000
@@ -2,7 +2,7 @@
  * Utility to generate asm-ia64/offsets.h.
  *
  * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Note that this file has dual use: when building the kernel
  * natively, the file is translated into a binary and executed.  When
@@ -58,7 +58,7 @@
     { "IA64_TASK_THREAD_OFFSET",	offsetof (struct task_struct, thread) },
     { "IA64_TASK_THREAD_KSP_OFFSET",	offsetof (struct task_struct, thread.ksp) },
 #ifdef CONFIG_PERFMON
-    { "IA64_TASK_PFM_MUST_BLOCK_OFFSET",offsetof(struct task_struct, thread.pfm_must_block) },
+    { "IA64_TASK_PFM_OVFL_BLOCK_RESET_OFFSET",offsetof(struct task_struct, thread.pfm_ovfl_block_reset) },
 #endif
     { "IA64_TASK_PID_OFFSET",		offsetof (struct task_struct, pid) },
     { "IA64_TASK_MM_OFFSET",		offsetof (struct task_struct, mm) },
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/ia64/vmlinux.lds.S linux/arch/ia64/vmlinux.lds.S
--- linux.orig/arch/ia64/vmlinux.lds.S	2001-07-31 17:30:09.000000000 +0000
+++ linux/arch/ia64/vmlinux.lds.S	2002-08-01 06:42:38.000000000 +0000
@@ -13,6 +13,8 @@
 	*(.text.exit)
 	*(.data.exit)
 	*(.exitcall.exit)
+	*(.IA_64.unwind.text.exit)
+	*(.IA_64.unwind_info.text.exit)
 	}
 
   v = PAGE_OFFSET;	/* this symbol is here to make debugging easier... */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/amiga/config.c linux/arch/m68k/amiga/config.c
--- linux.orig/arch/m68k/amiga/config.c	2001-09-13 22:21:32.000000000 +0000
+++ linux/arch/m68k/amiga/config.c	2002-08-01 06:42:29.000000000 +0000
@@ -18,6 +18,7 @@
 #include <linux/mm.h>
 #include <linux/tty.h>
 #include <linux/console.h>
+#include <linux/rtc.h>
 #include <linux/init.h>
 #ifdef CONFIG_ZORRO
 #include <linux/zorro.h>
@@ -91,14 +92,13 @@
 static unsigned long amiga_gettimeoffset (void);
 static void a3000_gettod (int *, int *, int *, int *, int *, int *);
 static void a2000_gettod (int *, int *, int *, int *, int *, int *);
-static int amiga_hwclk (int, struct hwclk_time *);
+static int amiga_hwclk (int, struct rtc_time *);
 static int amiga_set_clock_mmss (unsigned long);
 extern void amiga_mksound( unsigned int count, unsigned int ticks );
 #ifdef CONFIG_AMIGA_FLOPPY
 extern void amiga_floppy_setup(char *, int *);
 #endif
 static void amiga_reset (void);
-static int amiga_wait_key (struct console *co);
 extern void amiga_init_sound(void);
 static void amiga_savekmsg_init(void);
 static void amiga_mem_console_write(struct console *co, const char *b,
@@ -112,7 +112,6 @@
 
 static struct console amiga_console_driver = {
 	name:		"debug",
-	wait_key:	amiga_wait_key,
 	flags:		CON_PRINTBUFFER,
 	index:		-1,
 };
@@ -615,7 +614,7 @@
 	tod->cntrl1 &= ~TOD2000_CNTRL1_HOLD;
 }
 
-static int amiga_hwclk(int op, struct hwclk_time *t)
+static int amiga_hwclk(int op, struct rtc_time *t)
 {
 	if (AMIGAHW_PRESENT(A3000_CLK)) {
 		volatile struct tod3000 *tod = TOD_3000;
@@ -623,32 +622,32 @@
 		tod->cntrl1 = TOD3000_CNTRL1_HOLD;
 
 		if (!op) { /* read */
-			t->sec  = tod->second1 * 10 + tod->second2;
-			t->min  = tod->minute1 * 10 + tod->minute2;
-			t->hour = tod->hour1   * 10 + tod->hour2;
-			t->day  = tod->day1    * 10 + tod->day2;
-			t->wday = tod->weekday;
-			t->mon  = tod->month1  * 10 + tod->month2 - 1;
-			t->year = tod->year1   * 10 + tod->year2;
-			if (t->year <= 69)
-				t->year += 100;
+			t->tm_sec  = tod->second1 * 10 + tod->second2;
+			t->tm_min  = tod->minute1 * 10 + tod->minute2;
+			t->tm_hour = tod->hour1   * 10 + tod->hour2;
+			t->tm_mday = tod->day1    * 10 + tod->day2;
+			t->tm_wday = tod->weekday;
+			t->tm_mon  = tod->month1  * 10 + tod->month2 - 1;
+			t->tm_year = tod->year1   * 10 + tod->year2;
+			if (t->tm_year <= 69)
+				t->tm_year += 100;
 		} else {
-			tod->second1 = t->sec / 10;
-			tod->second2 = t->sec % 10;
-			tod->minute1 = t->min / 10;
-			tod->minute2 = t->min % 10;
-			tod->hour1   = t->hour / 10;
-			tod->hour2   = t->hour % 10;
-			tod->day1    = t->day / 10;
-			tod->day2    = t->day % 10;
-			if (t->wday != -1)
-				tod->weekday = t->wday;
-			tod->month1  = (t->mon + 1) / 10;
-			tod->month2  = (t->mon + 1) % 10;
-			if (t->year >= 100)
-				t->year -= 100;
-			tod->year1   = t->year / 10;
-			tod->year2   = t->year % 10;
+			tod->second1 = t->tm_sec / 10;
+			tod->second2 = t->tm_sec % 10;
+			tod->minute1 = t->tm_min / 10;
+			tod->minute2 = t->tm_min % 10;
+			tod->hour1   = t->tm_hour / 10;
+			tod->hour2   = t->tm_hour % 10;
+			tod->day1    = t->tm_mday / 10;
+			tod->day2    = t->tm_mday % 10;
+			if (t->tm_wday != -1)
+				tod->weekday = t->tm_wday;
+			tod->month1  = (t->tm_mon + 1) / 10;
+			tod->month2  = (t->tm_mon + 1) % 10;
+			if (t->tm_year >= 100)
+				t->tm_year -= 100;
+			tod->year1   = t->tm_year / 10;
+			tod->year2   = t->tm_year % 10;
 		}
 
 		tod->cntrl1 = TOD3000_CNTRL1_FREE;
@@ -661,45 +660,45 @@
 			;
 
 		if (!op) { /* read */
-			t->sec  = tod->second1     * 10 + tod->second2;
-			t->min  = tod->minute1     * 10 + tod->minute2;
-			t->hour = (tod->hour1 & 3) * 10 + tod->hour2;
-			t->day  = tod->day1        * 10 + tod->day2;
-			t->wday = tod->weekday;
-			t->mon  = tod->month1      * 10 + tod->month2 - 1;
-			t->year = tod->year1       * 10 + tod->year2;
-			if (t->year <= 69)
-				t->year += 100;
+			t->tm_sec  = tod->second1     * 10 + tod->second2;
+			t->tm_min  = tod->minute1     * 10 + tod->minute2;
+			t->tm_hour = (tod->hour1 & 3) * 10 + tod->hour2;
+			t->tm_mday = tod->day1        * 10 + tod->day2;
+			t->tm_wday = tod->weekday;
+			t->tm_mon  = tod->month1      * 10 + tod->month2 - 1;
+			t->tm_year = tod->year1       * 10 + tod->year2;
+			if (t->tm_year <= 69)
+				t->tm_year += 100;
 
 			if (!(tod->cntrl3 & TOD2000_CNTRL3_24HMODE)){
-				if (!(tod->hour1 & TOD2000_HOUR1_PM) && t->hour == 12)
-					t->hour = 0;
-				else if ((tod->hour1 & TOD2000_HOUR1_PM) && t->hour != 12)
-					t->hour += 12;
+				if (!(tod->hour1 & TOD2000_HOUR1_PM) && t->tm_hour == 12)
+					t->tm_hour = 0;
+				else if ((tod->hour1 & TOD2000_HOUR1_PM) && t->tm_hour != 12)
+					t->tm_hour += 12;
 			}
 		} else {
-			tod->second1 = t->sec / 10;
-			tod->second2 = t->sec % 10;
-			tod->minute1 = t->min / 10;
-			tod->minute2 = t->min % 10;
+			tod->second1 = t->tm_sec / 10;
+			tod->second2 = t->tm_sec % 10;
+			tod->minute1 = t->tm_min / 10;
+			tod->minute2 = t->tm_min % 10;
 			if (tod->cntrl3 & TOD2000_CNTRL3_24HMODE)
-				tod->hour1 = t->hour / 10;
-			else if (t->hour >= 12)
+				tod->hour1 = t->tm_hour / 10;
+			else if (t->tm_hour >= 12)
 				tod->hour1 = TOD2000_HOUR1_PM +
-					(t->hour - 12) / 10;
+					(t->tm_hour - 12) / 10;
 			else
-				tod->hour1 = t->hour / 10;
-			tod->hour2   = t->hour % 10;
-			tod->day1    = t->day / 10;
-			tod->day2    = t->day % 10;
-			if (t->wday != -1)
-				tod->weekday = t->wday;
-			tod->month1  = (t->mon + 1) / 10;
-			tod->month2  = (t->mon + 1) % 10;
-			if (t->year >= 100)
-				t->year -= 100;
-			tod->year1   = t->year / 10;
-			tod->year2   = t->year % 10;
+				tod->hour1 = t->tm_hour / 10;
+			tod->hour2   = t->tm_hour % 10;
+			tod->day1    = t->tm_mday / 10;
+			tod->day2    = t->tm_mday % 10;
+			if (t->tm_wday != -1)
+				tod->weekday = t->tm_wday;
+			tod->month1  = (t->tm_mon + 1) / 10;
+			tod->month2  = (t->tm_mon + 1) % 10;
+			if (t->tm_year >= 100)
+				t->tm_year -= 100;
+			tod->year1   = t->tm_year / 10;
+			tod->year2   = t->tm_year % 10;
 		}
 
 		tod->cntrl1 &= ~TOD2000_CNTRL1_HOLD;
@@ -742,33 +741,6 @@
 	return 0;
 }
 
-static int amiga_wait_key (struct console *co)
-{
-    int i;
-
-    while (1) {
-	while (ciaa.pra & 0x40);
-
-	/* debounce */
-	for (i = 0; i < 1000; i++);
-
-	if (!(ciaa.pra & 0x40))
-	    break;
-    }
-
-    /* wait for button up */
-    while (1) {
-	while (!(ciaa.pra & 0x40));
-
-	/* debounce */
-	for (i = 0; i < 1000; i++);
-
-	if (ciaa.pra & 0x40)
-	    break;
-    }
-    return 0;
-}
-
 static NORET_TYPE void amiga_reset( void )
     ATTRIB_NORET;
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/apollo/config.c linux/arch/m68k/apollo/config.c
--- linux.orig/arch/m68k/apollo/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/apollo/config.c	2002-08-01 06:42:38.000000000 +0000
@@ -4,6 +4,7 @@
 #include <linux/mm.h>
 #include <linux/tty.h>
 #include <linux/console.h>
+#include <linux/rtc.h>
 
 #include <asm/setup.h>
 #include <asm/bootinfo.h>
@@ -34,7 +35,7 @@
 extern int dn_get_irq_list(char *);
 extern unsigned long dn_gettimeoffset(void);
 extern void dn_gettod(int *, int *, int *, int *, int *, int *);
-extern int dn_dummy_hwclk(int, struct hwclk_time *);
+extern int dn_dummy_hwclk(int, struct rtc_time *);
 extern int dn_dummy_set_clock_mmss(unsigned long);
 extern void dn_mksound(unsigned int count, unsigned int ticks);
 extern void dn_dummy_reset(void);
@@ -254,26 +255,26 @@
 
 }
 
-int dn_dummy_hwclk(int op, struct hwclk_time *t) {
+int dn_dummy_hwclk(int op, struct rtc_time *t) {
 
 
   if(!op) { /* read */
-    t->sec=rtc->second;
-    t->min=rtc->minute;
-    t->hour=rtc->hours;
-    t->day=rtc->day_of_month;
-    t->wday=rtc->day_of_week;
-    t->mon=rtc->month;
-    t->year=rtc->year;
+    t->tm_sec=rtc->second;
+    t->tm_min=rtc->minute;
+    t->tm_hour=rtc->hours;
+    t->tm_mday=rtc->day_of_month;
+    t->tm_wday=rtc->day_of_week;
+    t->tm_mon=rtc->month;
+    t->tm_year=rtc->year;
   } else {
-    rtc->second=t->sec;
-    rtc->minute=t->min;
-    rtc->hours=t->hour;
-    rtc->day_of_month=t->day;
-    if(t->wday!=-1)
-      rtc->day_of_week=t->wday;
-    rtc->month=t->mon;
-    rtc->year=t->year;
+    rtc->second=t->tm_sec;
+    rtc->minute=t->tm_min;
+    rtc->hours=t->tm_hour;
+    rtc->day_of_month=t->tm_mday;
+    if(t->tm_wday!=-1)
+      rtc->day_of_week=t->tm_wday;
+    rtc->month=t->tm_mon;
+    rtc->year=t->tm_year;
   }
 
   return 0;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/atari/ataints.c linux/arch/m68k/atari/ataints.c
--- linux.orig/arch/m68k/atari/ataints.c	2000-08-04 23:15:37.000000000 +0000
+++ linux/arch/m68k/atari/ataints.c	2002-08-01 06:42:34.000000000 +0000
@@ -168,7 +168,7 @@
 void atari_slow_irq_##n##_dummy (void) {				   \
 __asm__ (__ALIGN_STR "\n"						   \
 SYMBOL_NAME_STR(atari_slow_irq_) #n "_handler:\t"			   \
-"	addql	#1,"SYMBOL_NAME_STR(irq_stat)"+8\n" /* local_irq_count */  \
+"	addql	#1,%5\n"		/* local_irq_count++ */		   \
 	SAVE_ALL_INT "\n"						   \
 	GET_CURRENT(%%d0) "\n"						   \
 "	andb	#~(1<<(%c3&7)),%a4:w\n"	/* mask this interrupt */	   \
@@ -193,8 +193,10 @@
 	 : : "i" (&kstat.irqs[0][n+8]), "i" (&irq_handler[n+8]),	   \
 	     "n" (PT_OFF_SR), "n" (n),					   \
 	     "i" (n & 8 ? (n & 16 ? &tt_mfp.int_mk_a : &mfp.int_mk_a)	   \
-		        : (n & 16 ? &tt_mfp.int_mk_b : &mfp.int_mk_b))	   \
+		        : (n & 16 ? &tt_mfp.int_mk_b : &mfp.int_mk_b)),	   \
+	     "m" (local_irq_count(0))					   \
 );									   \
+	for (;;);			/* fake noreturn */		   \
 }
 
 BUILD_SLOW_IRQ(0);
@@ -274,7 +276,7 @@
 SYMBOL_NAME_STR(atari_fast_irq_handler) ":
 	orw 	#0x700,%%sr		/* disable all interrupts */
 "SYMBOL_NAME_STR(atari_prio_irq_handler) ":\t
-	addql	#1,"SYMBOL_NAME_STR(irq_stat)"+8\n" /* local_irq_count */
+	addql	#1,%2\n"		/* local_irq_count++ */
 	SAVE_ALL_INT "\n"
 	GET_CURRENT(%%d0) "
 	/* get vector number from stack frame and convert to source */
@@ -294,8 +296,10 @@
 	addql	#8,%%sp
 	addql	#4,%%sp
 	jbra	"SYMBOL_NAME_STR(ret_from_interrupt)
-	 : : "i" (&kstat.irqs[0]), "n" (PT_OFF_FORMATVEC)
+	 : : "i" (&kstat.irqs[0]), "n" (PT_OFF_FORMATVEC),
+	     "m" (local_irq_count(0))
 );
+	for (;;);
 }
 
 /* GK:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/atari/config.c linux/arch/m68k/atari/config.c
--- linux.orig/arch/m68k/atari/config.c	2000-11-28 01:57:34.000000000 +0000
+++ linux/arch/m68k/atari/config.c	2002-08-01 06:42:31.000000000 +0000
@@ -38,6 +38,7 @@
 #include <asm/atariints.h>
 #include <asm/atari_stram.h>
 #include <asm/system.h>
+#include <asm/keyboard.h>
 #include <asm/machdep.h>
 #include <asm/hwtest.h>
 #include <asm/io.h>
@@ -81,8 +82,8 @@
 extern unsigned long atari_gettimeoffset (void);
 extern void atari_mste_gettod (int *, int *, int *, int *, int *, int *);
 extern void atari_tt_gettod (int *, int *, int *, int *, int *, int *);
-extern int atari_mste_hwclk (int, struct hwclk_time *);
-extern int atari_tt_hwclk (int, struct hwclk_time *);
+extern int atari_mste_hwclk (int, struct rtc_time *);
+extern int atari_tt_hwclk (int, struct rtc_time *);
 extern int atari_mste_set_clock_mmss (unsigned long);
 extern int atari_tt_set_clock_mmss (unsigned long);
 
@@ -256,7 +257,9 @@
     mach_keyb_init       = atari_keyb_init;
     mach_kbdrate         = atari_kbdrate;
     mach_kbd_translate   = atari_kbd_translate;
+#ifdef CONFIG_MAGIC_SYSRQ
     SYSRQ_KEY            = 0xff;
+#endif
     mach_kbd_leds        = atari_kbd_leds;
     mach_init_IRQ        = atari_init_IRQ;
     mach_request_irq     = atari_request_irq;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/atari/stram.c linux/arch/m68k/atari/stram.c
--- linux.orig/arch/m68k/atari/stram.c	2001-02-09 19:29:44.000000000 +0000
+++ linux/arch/m68k/atari/stram.c	2002-08-01 06:42:35.000000000 +0000
@@ -236,8 +236,8 @@
 static void do_stram_request(request_queue_t *);
 static int stram_open( struct inode *inode, struct file *filp );
 static int stram_release( struct inode *inode, struct file *filp );
-#endif
 static void reserve_region(void *start, void *end);
+#endif
 static BLOCK *add_region( void *addr, unsigned long size );
 static BLOCK *find_region( void *addr );
 static int remove_region( BLOCK *block );
@@ -296,7 +296,7 @@
 		max_swap_size =
 			(!MACH_IS_HADES &&
 			 (N_PAGES(stram_end-stram_start)*MAX_STRAM_FRACTION_DENOM <=
-			  (high_memory>>PAGE_SHIFT)*MAX_STRAM_FRACTION_NOM)) ? 16*1024*1024 : 0;
+			  ((unsigned long)high_memory>>PAGE_SHIFT)*MAX_STRAM_FRACTION_NOM)) ? 16*1024*1024 : 0;
 	DPRINTK( "atari_stram_reserve_pages: max_swap_size = %d\n", max_swap_size );
 #endif
 
@@ -759,7 +759,7 @@
 			/* Get a page for the entry, using the existing
 			   swap cache page if there is one.  Otherwise,
 			   get a clean page and read the swap into it. */
-			page = read_swap_cache(entry);
+			page = read_swap_cache_async(entry);
 			if (!page) {
 				swap_free(entry);
 				return -ENOMEM;
@@ -768,7 +768,7 @@
 			for_each_task(p)
 				unswap_process(p->mm, entry, page);
 			read_unlock(&tasklist_lock);
-			shm_unuse(entry, page);
+			shmem_unuse(entry, page);
 			/* Now get rid of the extra reference to the
 			   temporary page we've been using. */
 			if (PageSwapCache(page))
@@ -1072,7 +1072,6 @@
 	return( 0 );
 }
 
-#endif /* CONFIG_STRAM_SWAP */
 
 
 /* ------------------------------------------------------------------------ */
@@ -1085,6 +1084,7 @@
 	reserve_bootmem (virt_to_phys(start), end - start);
 }
 
+#endif /* CONFIG_STRAM_SWAP */
 
 
 /* ------------------------------------------------------------------------ */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/atari/time.c linux/arch/m68k/atari/time.c
--- linux.orig/arch/m68k/atari/time.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/atari/time.c	2002-08-01 06:42:36.000000000 +0000
@@ -14,6 +14,7 @@
 #include <linux/mc146818rtc.h>
 #include <linux/interrupt.h>
 #include <linux/init.h>
+#include <linux/rtc.h>
 
 #include <asm/rtc.h>
 
@@ -83,14 +84,14 @@
 
 #define	RTC_READ(reg)				\
     ({	unsigned char	__val;			\
-		(void) writeb(reg,&tt_rtc.regsel);	\
+		(void) atari_writeb(reg,&tt_rtc.regsel);	\
 		__val = tt_rtc.data;		\
 		__val;				\
 	})
 
 #define	RTC_WRITE(reg,val)			\
     do {					\
-		writeb(reg,&tt_rtc.regsel);	\
+		atari_writeb(reg,&tt_rtc.regsel);	\
 		tt_rtc.data = (val);		\
 	} while(0)
 
@@ -164,7 +165,7 @@
 
 #define HWCLK_POLL_INTERVAL	5
 
-int atari_mste_hwclk( int op, struct hwclk_time *t )
+int atari_mste_hwclk( int op, struct rtc_time *t )
 {
     int hour, year;
     int hr24=0;
@@ -177,11 +178,11 @@
     if (op) {
         /* write: prepare values */
         
-        val.sec_ones = t->sec % 10;
-        val.sec_tens = t->sec / 10;
-        val.min_ones = t->min % 10;
-        val.min_tens = t->min / 10;
-        hour = t->hour;
+        val.sec_ones = t->tm_sec % 10;
+        val.sec_tens = t->tm_sec / 10;
+        val.min_ones = t->tm_min % 10;
+        val.min_tens = t->tm_min / 10;
+        hour = t->tm_hour;
         if (!hr24) {
 	    if (hour > 11)
 		hour += 20 - 12;
@@ -190,14 +191,14 @@
         }
         val.hr_ones = hour % 10;
         val.hr_tens = hour / 10;
-        val.day_ones = t->day % 10;
-        val.day_tens = t->day / 10;
-        val.mon_ones = (t->mon+1) % 10;
-        val.mon_tens = (t->mon+1) / 10;
-        year = t->year - 80;
+        val.day_ones = t->tm_mday % 10;
+        val.day_tens = t->tm_mday / 10;
+        val.mon_ones = (t->tm_mon+1) % 10;
+        val.mon_tens = (t->tm_mon+1) / 10;
+        year = t->tm_year - 80;
         val.year_ones = year % 10;
         val.year_tens = year / 10;
-        val.weekday = t->wday;
+        val.weekday = t->tm_wday;
         mste_write(&val);
         mste_rtc.mode=(mste_rtc.mode | 1);
         val.year_ones = (year % 4);	/* leap year register */
@@ -205,8 +206,8 @@
     }
     else {
         mste_read(&val);
-        t->sec = val.sec_ones + val.sec_tens * 10;
-        t->min = val.min_ones + val.min_tens * 10;
+        t->tm_sec = val.sec_ones + val.sec_tens * 10;
+        t->tm_min = val.min_ones + val.min_tens * 10;
         hour = val.hr_ones + val.hr_tens * 10;
 	if (!hr24) {
 	    if (hour == 12 || hour == 12 + 20)
@@ -214,16 +215,16 @@
 	    if (hour >= 20)
                 hour += 12 - 20;
         }
-	t->hour = hour;
-	t->day = val.day_ones + val.day_tens * 10;
-        t->mon = val.mon_ones + val.mon_tens * 10 - 1;
-        t->year = val.year_ones + val.year_tens * 10 + 80;
-        t->wday = val.weekday;
+	t->tm_hour = hour;
+	t->tm_mday = val.day_ones + val.day_tens * 10;
+        t->tm_mon  = val.mon_ones + val.mon_tens * 10 - 1;
+        t->tm_year = val.year_ones + val.year_tens * 10 + 80;
+        t->tm_wday = val.weekday;
     }
     return 0;
 }
 
-int atari_tt_hwclk( int op, struct hwclk_time *t )
+int atari_tt_hwclk( int op, struct rtc_time *t )
 {
     int sec=0, min=0, hour=0, day=0, mon=0, year=0, wday=0; 
     unsigned long 	flags;
@@ -236,13 +237,13 @@
     if (op) {
         /* write: prepare values */
         
-        sec  = t->sec;
-        min  = t->min;
-        hour = t->hour;
-        day  = t->day;
-        mon  = t->mon + 1;
-        year = t->year - atari_rtc_year_offset;
-        wday = t->wday + (t->wday >= 0);
+        sec  = t->tm_sec;
+        min  = t->tm_min;
+        hour = t->tm_hour;
+        day  = t->tm_mday;
+        mon  = t->tm_mon + 1;
+        year = t->tm_year - atari_rtc_year_offset;
+        wday = t->tm_wday + (t->tm_wday >= 0);
         
         if (!(ctrl & RTC_24H)) {
 	    if (hour > 11) {
@@ -331,13 +332,13 @@
 		hour += 12;
         }
 
-        t->sec  = sec;
-        t->min  = min;
-        t->hour = hour;
-        t->day  = day;
-        t->mon  = mon - 1;
-        t->year = year + atari_rtc_year_offset;
-        t->wday = wday - 1;
+        t->tm_sec  = sec;
+        t->tm_min  = min;
+        t->tm_hour = hour;
+        t->tm_mday = day;
+        t->tm_mon  = mon - 1;
+        t->tm_year = year + atari_rtc_year_offset;
+        t->tm_wday = wday - 1;
     }
 
     return( 0 );
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/bvme6000/config.c linux/arch/m68k/bvme6000/config.c
--- linux.orig/arch/m68k/bvme6000/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/bvme6000/config.c	2002-08-01 06:42:30.000000000 +0000
@@ -22,6 +22,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <linux/major.h>
+#include <linux/rtc.h>
 
 #include <asm/bootinfo.h>
 #include <asm/system.h>
@@ -48,7 +49,7 @@
 extern unsigned long bvme6000_gettimeoffset (void);
 extern void bvme6000_gettod (int *year, int *mon, int *day, int *hour,
                            int *min, int *sec);
-extern int bvme6000_hwclk (int, struct hwclk_time *);
+extern int bvme6000_hwclk (int, struct rtc_time *);
 extern int bvme6000_set_clock_mmss (unsigned long);
 extern void bvme6000_check_partition (struct gendisk *hd, unsigned int dev);
 extern void bvme6000_mksound( unsigned int count, unsigned int ticks );
@@ -181,8 +182,8 @@
         unsigned long *old = (unsigned long *)0xf8000000;
 
         /* Wait for button release */
-	while (*config_reg_ptr & BVME_ABORT_STATUS)
-		;
+        while (*(volatile unsigned char *)BVME_LOCAL_IRQ_STAT & BVME_ABORT_STATUS)
+                ;
 
         *(new+4) = *(old+4);            /* Illegal instruction */
         *(new+9) = *(old+9);            /* Trace */
@@ -330,7 +331,7 @@
  * };
  */
 
-int bvme6000_hwclk(int op, struct hwclk_time *t)
+int bvme6000_hwclk(int op, struct rtc_time *t)
 {
 	volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
 	unsigned char msr = rtc->msr & 0xc0;
@@ -339,31 +340,31 @@
 				 * are accessible */
 	if (op)
 	{	/* Write.... */
-		rtc->t0cr_rtmr = t->year%4;
+		rtc->t0cr_rtmr = t->tm_year%4;
 		rtc->bcd_tenms = 0;
-		rtc->bcd_sec = bin2bcd(t->sec);
-		rtc->bcd_min = bin2bcd(t->min);
-		rtc->bcd_hr  = bin2bcd(t->hour);
-		rtc->bcd_dom = bin2bcd(t->day);
-		rtc->bcd_mth = bin2bcd(t->mon + 1);
-		rtc->bcd_year = bin2bcd(t->year%100);
-		if (t->wday >= 0)
-			rtc->bcd_dow = bin2bcd(t->wday+1);
-		rtc->t0cr_rtmr = t->year%4 | 0x08;
+		rtc->bcd_sec = bin2bcd(t->tm_sec);
+		rtc->bcd_min = bin2bcd(t->tm_min);
+		rtc->bcd_hr  = bin2bcd(t->tm_hour);
+		rtc->bcd_dom = bin2bcd(t->tm_mday);
+		rtc->bcd_mth = bin2bcd(t->tm_mon + 1);
+		rtc->bcd_year = bin2bcd(t->tm_year%100);
+		if (t->tm_wday >= 0)
+			rtc->bcd_dow = bin2bcd(t->tm_wday+1);
+		rtc->t0cr_rtmr = t->tm_year%4 | 0x08;
 	}
 	else
 	{	/* Read....  */
 		do {
-			t->sec =  bcd2bin(rtc->bcd_sec);
-			t->min =  bcd2bin(rtc->bcd_min);
-			t->hour = bcd2bin(rtc->bcd_hr);
-			t->day =  bcd2bin(rtc->bcd_dom);
-			t->mon =  bcd2bin(rtc->bcd_mth)-1;
-			t->year = bcd2bin(rtc->bcd_year);
-			if (t->year < 70)
-				t->year += 100;
-			t->wday = bcd2bin(rtc->bcd_dow)-1;
-		} while (t->sec != bcd2bin(rtc->bcd_sec));
+			t->tm_sec  = bcd2bin(rtc->bcd_sec);
+			t->tm_min  = bcd2bin(rtc->bcd_min);
+			t->tm_hour = bcd2bin(rtc->bcd_hr);
+			t->tm_mday = bcd2bin(rtc->bcd_dom);
+			t->tm_mon  = bcd2bin(rtc->bcd_mth)-1;
+			t->tm_year = bcd2bin(rtc->bcd_year);
+			if (t->tm_year < 70)
+				t->tm_year += 100;
+			t->tm_wday = bcd2bin(rtc->bcd_dow)-1;
+		} while (t->tm_sec != bcd2bin(rtc->bcd_sec));
 	}
 
 	rtc->msr = msr;
@@ -419,55 +420,3 @@
 {
 	return 0;
 }
-
-/*-------------------  Serial console stuff ------------------------*/
-
-static void bvme_scc_write(struct console *co, const char *str, unsigned cnt);
-
-
-void bvme6000_init_console_port (struct console *co, int cflag)
-{
-        co->write = bvme_scc_write;
-}
-
-
-static void scc_delay (void)
-{
-        int n;
-	volatile int trash;
-
-        for (n = 0; n < 20; n++)
-		trash = n;
-}
-
-static void scc_write (char ch)
-{
-        volatile char *p = (volatile char *)BVME_SCC_A_ADDR;
-
-        do {
-                scc_delay();
-        }
-        while (!(*p & 4));
-        scc_delay();
-        *p = 8;
-        scc_delay();
-        *p = ch;
-}
-
-
-static void bvme_scc_write (struct console *co, const char *str, unsigned count)
-{
-        unsigned long   flags;
-
-        save_flags(flags);
-        cli();
-
-        while (count--)
-        {
-                if (*str == '\n')
-                        scc_write ('\r');
-                scc_write (*str++);
-        }
-        restore_flags(flags);
-}
-
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/bvme6000/rtc.c linux/arch/m68k/bvme6000/rtc.c
--- linux.orig/arch/m68k/bvme6000/rtc.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/bvme6000/rtc.c	2002-08-01 06:42:29.000000000 +0000
@@ -14,7 +14,7 @@
 #include <linux/fcntl.h>
 #include <linux/init.h>
 #include <linux/poll.h>
-#include <linux/mc146818rtc.h>	/* For struct rtc_time and ioctls, etc */
+#include <linux/rtc.h>	/* For struct rtc_time and ioctls, etc */
 #include <linux/smp_lock.h>
 #include <asm/bvme6000hw.h>
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/config.in linux/arch/m68k/config.in
--- linux.orig/arch/m68k/config.in	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/config.in	2002-08-01 06:42:46.000000000 +0000
@@ -26,7 +26,6 @@
 mainmenu_option next_comment
 comment 'Platform dependent setup'
 
-define_bool CONFIG_ISA n
 define_bool CONFIG_EISA n
 define_bool CONFIG_MCA n
 define_bool CONFIG_PCMCIA n
@@ -146,11 +145,18 @@
    fi
 fi
 
+if [ "$CONFIG_Q40" = "y" -o "$CONFIG_AMIGA_PCMCIA" = "y" \
+      -o "$CONFIG_GG2" = "y" ]; then
+   define_bool CONFIG_ISA y
+else
+   define_bool CONFIG_ISA n
+fi
+
 source drivers/pci/Config.in
 source drivers/zorro/Config.in
 
 if [ "$CONFIG_Q40" = "y" ]; then
-source drivers/pnp/Config.in
+   source drivers/pnp/Config.in
 fi
 
 endmenu
@@ -297,9 +303,17 @@
 	 bool '    Keepalive and linefill' CONFIG_SLIP_SMART
 	 bool '    Six bit SLIP encapsulation' CONFIG_SLIP_MODE_SLIP6
       fi
-      tristate '  PPP (point-to-point) support' CONFIG_PPP
+      tristate 'PPP (point-to-point protocol) support' CONFIG_PPP
       if [ ! "$CONFIG_PPP" = "n" ]; then
-	 comment 'CCP compressors for PPP are only built as modules.'
+         dep_bool '  PPP multilink support (EXPERIMENTAL)' CONFIG_PPP_MULTILINK $CONFIG_EXPERIMENTAL
+         dep_bool '  PPP filtering' CONFIG_PPP_FILTER $CONFIG_FILTER
+         dep_tristate '  PPP support for async serial ports' CONFIG_PPP_ASYNC $CONFIG_PPP
+         dep_tristate '  PPP support for sync tty ports' CONFIG_PPP_SYNC_TTY $CONFIG_PPP
+         dep_tristate '  PPP Deflate compression' CONFIG_PPP_DEFLATE $CONFIG_PPP
+         dep_tristate '  PPP BSD-Compress compression' CONFIG_PPP_BSDCOMP $CONFIG_PPP
+         if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
+             dep_tristate '  PPP over Ethernet (EXPERIMENTAL)' CONFIG_PPPOE $CONFIG_PPP
+         fi
       fi
       tristate '  EQL (serial line load balancing) support' CONFIG_EQUALIZER
       if [ "$CONFIG_ZORRO" = "y" ]; then
@@ -352,7 +366,7 @@
          if [  "$CONFIG_PARPORT" != "n" ]; then
 	    dep_tristate '  PLIP (parallel port) support' CONFIG_PLIP $CONFIG_PARPORT
 	 fi
-         tristate 'NE2000/NE1000 support' CONFIG_NE2000
+         dep_tristate 'NE2000/NE1000 support' CONFIG_NE2000 m
       fi
    fi
    endmenu
@@ -367,7 +381,6 @@
 fi
 
 if [ "$CONFIG_SERIAL" = "y" ]; then
-   bool '  Support for console on serial port' CONFIG_SERIAL_CONSOLE
    bool '  Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED
 fi
 
@@ -477,7 +490,8 @@
         "$CONFIG_ATARI_MIDI" = "y" -o "$CONFIG_MAC_SCC" = "y" -o \
         "$CONFIG_AMIGA_BUILTIN_SERIAL" = "y" -o \
         "$CONFIG_GVPIOEXT" = "y" -o "$CONFIG_MULTIFACE_III_TTY" = "y" -o \
-        "$CONFIG_HPDCA" = "y" -o "$CONFIG_SUN3X_ZS" = "y" ]; then
+        "$CONFIG_HPDCA" = "y" -o "$CONFIG_SUN3X_ZS" = "y" -o \
+	"$CONFIG_SERIAL" = "y" ]; then
       bool 'Support for serial port console' CONFIG_SERIAL_CONSOLE
    fi
 fi
@@ -543,6 +557,11 @@
 mainmenu_option next_comment
 comment 'Kernel hacking'
 
-#bool 'Debug kmalloc/kfree' CONFIG_DEBUG_MALLOC
-bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ
+bool 'Kernel debugging' CONFIG_DEBUG_KERNEL
+if [ "$CONFIG_DEBUG_KERNEL" != "n" ]; then
+   bool '  Magic SysRq key' CONFIG_MAGIC_SYSRQ
+   bool '  Debug memory allocations' CONFIG_DEBUG_SLAB
+   bool '  Verbose BUG() reporting' CONFIG_DEBUG_BUGVERBOSE
+fi
+
 endmenu
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/hp300/time.c linux/arch/m68k/hp300/time.c
--- linux.orig/arch/m68k/hp300/time.c	1999-08-26 19:42:31.000000000 +0000
+++ linux/arch/m68k/hp300/time.c	2002-08-01 06:42:47.000000000 +0000
@@ -41,7 +41,7 @@
   unsigned long tmp;
   void (*vector)(int, void *, struct pt_regs *) = dev_id;
   readb(CLOCKBASE + CLKSR);
-  asm volatile ("movpw %1@(5),%0" : "=r" (tmp) : "a" (CLOCKBASE));
+  asm volatile ("movpw %1@(5),%0" : "=d" (tmp) : "a" (CLOCKBASE));
   vector(irq, NULL, regs);
 }
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/entry.S linux/arch/m68k/kernel/entry.S
--- linux.orig/arch/m68k/kernel/entry.S	2001-10-08 17:39:18.000000000 +0000
+++ linux/arch/m68k/kernel/entry.S	2002-08-01 06:42:29.000000000 +0000
@@ -184,7 +184,7 @@
 #if 0
 #if CONFIG_AMIGA
 SYMBOL_NAME_LABEL(ami_inthandler)
-	addql	#1,SYMBOL_NAME(irq_stat)+8	| local_irq_count
+	addql	#1,SYMBOL_NAME(irq_stat)+4	| local_irq_count
 	SAVE_ALL_INT
 	GET_CURRENT(%d0)
 
@@ -216,7 +216,7 @@
 SYMBOL_NAME_LABEL(inthandler)
 	SAVE_ALL_INT
 	GET_CURRENT(%d0)
-	addql	#1,SYMBOL_NAME(irq_stat)+8	| local_irq_count
+	addql	#1,SYMBOL_NAME(irq_stat)+4	| local_irq_count
 					|  put exception # in d0
 	bfextu %sp@(PT_VECTOR){#4,#10},%d0
 
@@ -235,7 +235,7 @@
 3:     	addql	#8,%sp			|  pop parameters off stack
 
 SYMBOL_NAME_LABEL(ret_from_interrupt)
-	subql	#1,SYMBOL_NAME(irq_stat)+8	| local_irq_count
+	subql	#1,SYMBOL_NAME(irq_stat)+4	| local_irq_count
 	jeq	1f
 2:
 	RESTORE_ALL
@@ -248,11 +248,8 @@
 	jhi	2b
 #endif
 	/* check if we need to do software interrupts */
-
-	movel	SYMBOL_NAME(irq_stat),%d0	| softirq_active
-	andl	SYMBOL_NAME(irq_stat)+4,%d0	| softirq_mask
+	tstl	SYMBOL_NAME(irq_stat)	| softirq_pending ?
 	jeq	SYMBOL_NAME(ret_from_exception)
-
 	pea	SYMBOL_NAME(ret_from_exception)
 	jra	SYMBOL_NAME(do_softirq)
 
@@ -642,10 +639,12 @@
 	.long SYMBOL_NAME(sys_setgid)
 	.long SYMBOL_NAME(sys_setfsuid)		/* 215 */
 	.long SYMBOL_NAME(sys_setfsgid)
-	.long SYMBOL_NAME(sys_ni_syscall)
+	.long SYMBOL_NAME(sys_pivot_root)
 	.long SYMBOL_NAME(sys_ni_syscall)
 	.long SYMBOL_NAME(sys_ni_syscall)
 	.long SYMBOL_NAME(sys_getdents64)	/* 220 */
+	.long SYMBOL_NAME(sys_gettid)
+	.long SYMBOL_NAME(sys_tkill)
 
 	.rept NR_syscalls-(.-SYMBOL_NAME(sys_call_table))/4
 		.long SYMBOL_NAME(sys_ni_syscall)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/process.c linux/arch/m68k/kernel/process.c
--- linux.orig/arch/m68k/kernel/process.c	2001-09-30 19:26:08.000000000 +0000
+++ linux/arch/m68k/kernel/process.c	2002-08-01 06:42:44.000000000 +0000
@@ -136,6 +136,7 @@
 	register long retval __asm__ ("d0");
 	register long clone_arg __asm__ ("d1") = flags | CLONE_VM;
 
+	retval = __NR_clone;
 	__asm__ __volatile__
 	  ("clrl %%d2\n\t"
 	   "trap #0\n\t"		/* Linux/m68k system call */
@@ -145,14 +146,15 @@
 	   "movel %3,%%sp@-\n\t"	/* push argument */
 	   "jsr %4@\n\t"		/* call fn */
 	   "movel %0,%%d1\n\t"		/* pass exit value */
-	   "movel %2,%0\n\t"		/* exit */
+	   "movel %2,%%d0\n\t"		/* exit */
 	   "trap #0\n"
 	   "1:"
-	   : "=d" (retval)
-	   : "0" (__NR_clone), "i" (__NR_exit),
+	   : "+d" (retval)
+	   : "i" (__NR_clone), "i" (__NR_exit),
 	     "r" (arg), "a" (fn), "d" (clone_arg), "r" (current),
 	     "i" (-KTHREAD_SIZE)
-	   : "d0", "d2");
+	   : "d2");
+
 	pid = retval;
 	}
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/ptrace.c linux/arch/m68k/kernel/ptrace.c
--- linux.orig/arch/m68k/kernel/ptrace.c	2001-09-19 00:03:51.000000000 +0000
+++ linux/arch/m68k/kernel/ptrace.c	2002-08-01 06:42:37.000000000 +0000
@@ -103,7 +103,6 @@
 asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
 {
 	struct task_struct *child;
-	unsigned long flags;
 	int ret;
 
 	lock_kernel();
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/setup.c linux/arch/m68k/kernel/setup.c
--- linux.orig/arch/m68k/kernel/setup.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/kernel/setup.c	2002-08-01 06:42:47.000000000 +0000
@@ -21,6 +21,7 @@
 #include <linux/string.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/seq_file.h>
 #include <linux/module.h>
 
 #include <asm/bootinfo.h>
@@ -85,7 +86,7 @@
 /* machine dependent timer functions */
 unsigned long (*mach_gettimeoffset) (void);
 void (*mach_gettod) (int*, int*, int*, int*, int*, int*);
-int (*mach_hwclk) (int, struct hwclk_time*) = NULL;
+int (*mach_hwclk) (int, struct rtc_time*) = NULL;
 int (*mach_set_clock_mmss) (unsigned long) = NULL;
 void (*mach_reset)( void );
 void (*mach_halt)( void ) = NULL;
@@ -93,7 +94,6 @@
 long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */
 #if defined(CONFIG_AMIGA_FLOPPY) || defined(CONFIG_ATARI_FLOPPY) 
 void (*mach_floppy_setup) (char *, int *) __initdata = NULL;
-void (*mach_floppy_eject) (void) = NULL;
 #endif
 #ifdef CONFIG_HEARTBEAT
 void (*mach_heartbeat) (int) = NULL;
@@ -110,7 +110,7 @@
 char *mach_sysrq_xlate = NULL;
 #endif
 
-#if defined(CONFIG_ISA)
+#if defined(CONFIG_ISA) && defined(MULTI_ISA)
 int isa_type;
 int isa_sex;
 #endif
@@ -388,7 +388,7 @@
 	paging_init();
 
 /* set ISA defs early as possible */
-#if defined(CONFIG_ISA)
+#if defined(CONFIG_ISA) && defined(MULTI_ISA)
 #if defined(CONFIG_Q40) 
 	if (MACH_IS_Q40) {
 	    isa_type = Q40_ISA;
@@ -408,7 +408,7 @@
 #endif
 }
 
-int get_cpuinfo(char * buffer)
+static int show_cpuinfo(struct seq_file *m, void *v)
 {
     const char *cpu, *mmu, *fpu;
     unsigned long clockfreq, clockfactor;
@@ -469,7 +469,7 @@
 
     clockfreq = loops_per_jiffy*HZ*clockfactor;
 
-    return(sprintf(buffer, "CPU:\t\t%s\n"
+    seq_printf(m, "CPU:\t\t%s\n"
 		   "MMU:\t\t%s\n"
 		   "FPU:\t\t%s\n"
 		   "Clocking:\t%lu.%1luMHz\n"
@@ -478,9 +478,28 @@
 		   cpu, mmu, fpu,
 		   clockfreq/1000000,(clockfreq/100000)%10,
 		   loops_per_jiffy/(500000/HZ),(loops_per_jiffy/(5000/HZ))%100,
-		   loops_per_jiffy));
+		   loops_per_jiffy);
+    return 0;
+}
 
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+	return *pos < 1 ? (void *)1 : NULL;
+}
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+	++*pos;
+	return NULL;
 }
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+struct seq_operations cpuinfo_op = {
+	start:	c_start,
+	next:	c_next,
+	stop:	c_stop,
+	show:	show_cpuinfo,
+};
 
 int get_hardware_list(char *buffer)
 {
@@ -495,7 +514,7 @@
 	strcpy(model, "Unknown m68k");
 
     len += sprintf(buffer+len, "Model:\t\t%s\n", model);
-    len += get_cpuinfo(buffer+len);
+    //len += get_cpuinfo(buffer+len);
     for (mem = 0, i = 0; i < m68k_num_memory; i++)
 	mem += m68k_memory[i].size;
     len += sprintf(buffer+len, "System Memory:\t%ldK\n", mem>>10);
@@ -514,11 +533,6 @@
 		mach_floppy_setup (str, ints);
 }
 
-void floppy_eject(void)
-{
-	if (mach_floppy_eject)
-		mach_floppy_eject();
-}
 #endif
 
 /* for "kbd-reset" cmdline param */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/signal.c linux/arch/m68k/kernel/signal.c
--- linux.orig/arch/m68k/kernel/signal.c	2001-01-24 23:21:28.000000000 +0000
+++ linux/arch/m68k/kernel/signal.c	2002-08-01 06:42:34.000000000 +0000
@@ -38,6 +38,7 @@
 #include <linux/unistd.h>
 #include <linux/stddef.h>
 #include <linux/highuid.h>
+#include <linux/personality.h>
 
 #include <asm/setup.h>
 #include <asm/uaccess.h>
@@ -1118,14 +1119,17 @@
 					continue;
 				/* FALLTHRU */
 
-			case SIGSTOP:
+			case SIGSTOP: {
+				struct signal_struct *sig;
 				current->state = TASK_STOPPED;
 				current->exit_code = signr;
-				if (!(current->p_pptr->sig->action[SIGCHLD-1]
-				      .sa.sa_flags & SA_NOCLDSTOP))
-					notify_parent(current, SIGCHLD);
+                                sig = current->p_pptr->sig;
+                                if (sig && !(sig->action[SIGCHLD-1].sa.sa_flags 
+& SA_NOCLDSTOP))
+                                        notify_parent(current, SIGCHLD);
 				schedule();
 				continue;
+			}
 
 			case SIGQUIT: case SIGILL: case SIGTRAP:
 			case SIGIOT: case SIGFPE: case SIGSEGV:
@@ -1135,10 +1139,7 @@
 				/* FALLTHRU */
 
 			default:
-				sigaddset(&current->pending.signal, signr);
-				recalc_sigpending(current);
-				current->flags |= PF_SIGNALED;
-				do_exit(exit_code);
+				sig_exit(signr, exit_code, &info);
 				/* NOTREACHED */
 			}
 		}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/sun3-head.S linux/arch/m68k/kernel/sun3-head.S
--- linux.orig/arch/m68k/kernel/sun3-head.S	2000-12-29 22:07:20.000000000 +0000
+++ linux/arch/m68k/kernel/sun3-head.S	2002-08-01 06:42:27.000000000 +0000
@@ -15,9 +15,6 @@
 .globl SYMBOL_NAME(bootup_user_stack)
 .globl SYMBOL_NAME(bootup_kernel_stack)
 .globl SYMBOL_NAME(pg0)
-.globl SYMBOL_NAME(empty_bad_page)
-.globl SYMBOL_NAME(empty_bad_page_table)
-.globl SYMBOL_NAME(empty_zero_page)
 .globl SYMBOL_NAME(swapper_pg_dir)
 .globl SYMBOL_NAME(kernel_pmd_table)
 .globl SYMBOL_NAME(availmem)
@@ -26,10 +23,7 @@
 | todo: all these should be in bss!
 SYMBOL_NAME(swapper_pg_dir):                .skip 0x2000
 SYMBOL_NAME(pg0):                           .skip 0x2000
-SYMBOL_NAME(empty_bad_page):                .skip 0x2000
-SYMBOL_NAME(empty_bad_page_table):          .skip 0x2000
 SYMBOL_NAME(kernel_pmd_table):              .skip 0x2000
-SYMBOL_NAME(empty_zero_page):               .skip 0x2000
 
 .globl SYMBOL_NAME(kernel_pg_dir)
 .equ    SYMBOL_NAME(kernel_pg_dir),SYMBOL_NAME(kernel_pmd_table)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/kernel/traps.c linux/arch/m68k/kernel/traps.c
--- linux.orig/arch/m68k/kernel/traps.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/kernel/traps.c	2002-08-01 06:42:44.000000000 +0000
@@ -23,7 +23,7 @@
 #include <linux/signal.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
-#include <linux/types.h>
+#include <linux/module.h>
 #include <linux/a.out.h>
 #include <linux/user.h>
 #include <linux/string.h>
@@ -224,7 +224,7 @@
 		unsigned long addr = fp->un.fmt4.effaddr;
 
 		if (fslw & MMU060_MA)
-			addr = (addr + 7) & -8;
+			addr = (addr + PAGE_SIZE - 1) & PAGE_MASK;
 
 		errorcode = 1;
 		if (fslw & MMU060_DESC_ERR) {
@@ -258,16 +258,12 @@
 
 	set_fs(MAKE_MM_SEG(wbs));
 
-	asm volatile (".chip 68040");
-
 	if (iswrite)
-		asm volatile ("ptestw (%0)" : : "a" (addr));
+                asm volatile (".chip 68040; ptestw (%0); .chip 68k" : : "a" (addr));
 	else
-		asm volatile ("ptestr (%0)" : : "a" (addr));
+                asm volatile (".chip 68040; ptestr (%0); .chip 68k" : : "a" (addr));
 
-	asm volatile ("movec %%mmusr,%0" : "=r" (mmusr));
-
-	asm volatile (".chip 68k");
+        asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr));
 
 	set_fs(old_fs); 
 
@@ -816,15 +812,71 @@
 
 
 int kstack_depth_to_print = 48;
+extern struct module kernel_module;
+
+static inline int kernel_text_address(unsigned long addr)
+{
+	struct module *mod;
+	int retval = 0;
+	extern char _stext, _etext;
+
+	if (addr >= (unsigned long) &_stext &&
+	    addr <= (unsigned long) &_etext)
+		return 1;
+
+#ifdef CONFIG_MODULES
+	for (mod = module_list; mod != &kernel_module; mod = mod->next) {
+		/* mod_bound tests for addr being inside the vmalloc'ed
+		 * module area. Of course it'd be better to test only
+		 * for the .text subset... */
+		if (mod_bound(addr, 0, mod)) {
+			retval = 1;
+			break;
+		}
+	}
+#endif
+
+	return retval;
+}
+
+void show_trace(unsigned long *stack)
+{
+	unsigned long *endstack;
+	unsigned long addr;
+	int i;
+
+	printk("Call Trace:");
+	addr = (unsigned long)stack + THREAD_SIZE - 1;
+	endstack = (unsigned long *)(addr & -THREAD_SIZE);
+	i = 0;
+	while (stack + 1 <= endstack) {
+		addr = *stack++;
+		/*
+		 * If the address is either in the text segment of the
+		 * kernel, or in the region which contains vmalloc'ed
+		 * memory, it *may* be the address of a calling
+		 * routine; if so, print it so that someone tracing
+		 * down the cause of the crash will be able to figure
+		 * out the call path that was taken.
+		 */
+		if (kernel_text_address(addr)) {
+			if (i % 4 == 0)
+				printk("\n       ");
+			printk(" [<%08lx>]", addr);
+			i++;
+		}
+	}
+	printk("\n");
+}
 
-/* MODULE_RANGE is a guess of how much space is likely to be
-   vmalloced.  */
-#define MODULE_RANGE (8*1024*1024)
+void show_trace_task(struct task_struct *tsk)
+{
+	show_trace((unsigned long *)tsk->thread.esp0);
+}
 
 static void dump_stack(struct frame *fp)
 {
-	unsigned long *stack, *endstack, addr, module_start, module_end;
-	extern char _start, _etext;
+	unsigned long *stack, *endstack, addr;
 	int i;
 
 	addr = (unsigned long)&fp->un;
@@ -881,7 +933,7 @@
 	}
 
 	stack = (unsigned long *)addr;
-	endstack = (unsigned long *)PAGE_ALIGN(addr);
+	endstack = (unsigned long *)((addr + THREAD_SIZE - 1) & -THREAD_SIZE);
 
 	printk("Stack from %08lx:", (unsigned long)stack);
 	for (i = 0; i < kstack_depth_to_print; i++) {
@@ -891,32 +943,10 @@
 			printk("\n       ");
 		printk(" %08lx", *stack++);
 	}
+	printk("\n");
+	show_trace((unsigned long *)addr);
 
-	printk ("\nCall Trace:");
-	stack = (unsigned long *) addr;
-	i = 0;
-	module_start = VMALLOC_START;
-	module_end = module_start + MODULE_RANGE;
-	while (stack + 1 <= endstack) {
-		addr = *stack++;
-		/*
-		 * If the address is either in the text segment of the
-		 * kernel, or in the region which contains vmalloc'ed
-		 * memory, it *may* be the address of a calling
-		 * routine; if so, print it so that someone tracing
-		 * down the cause of the crash will be able to figure
-		 * out the call path that was taken.
-		 */
-		if (((addr >= (unsigned long) &_start) &&
-		     (addr <= (unsigned long) &_etext)) ||
-		    ((addr >= module_start) && (addr <= module_end))) {
-			if (i % 4 == 0)
-				printk("\n       ");
-			printk(" [<%08lx>]", addr);
-			i++;
-		}
-	}
-	printk("\nCode: ");
+	printk("Code: ");
 	for (i = 0; i < 10; i++)
 		printk("%04x ", 0xffff & ((short *) fp->ptregs.pc)[i]);
 	printk ("\n");
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mac/config.c linux/arch/m68k/mac/config.c
--- linux.orig/arch/m68k/mac/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/mac/config.c	2002-08-01 06:42:42.000000000 +0000
@@ -64,7 +64,7 @@
 /* Mac specific timer functions */
 extern void mac_gettod (int *, int *, int *, int *, int *, int *);
 extern unsigned long mac_gettimeoffset (void);
-extern int mac_hwclk (int, struct hwclk_time *);
+extern int mac_hwclk (int, struct rtc_time *);
 extern int mac_set_clock_mmss (unsigned long);
 extern int mac_get_irq_list(char *);
 extern void iop_preinit(void);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mac/debug.c linux/arch/m68k/mac/debug.c
--- linux.orig/arch/m68k/mac/debug.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/mac/debug.c	2002-08-01 06:42:48.000000000 +0000
@@ -235,32 +235,6 @@
     }
 }
 
-#if defined(CONFIG_SERIAL_CONSOLE) || defined(DEBUG_SERIAL)
-int mac_sccb_console_wait_key(struct console *co)
-{
-    int i;
-    do {
-	for( i = uSEC; i > 0; --i )
-		barrier();
-    } while( !(scc.cha_b_ctrl & 0x01) ); /* wait for rx buf filled */
-    for( i = uSEC; i > 0; --i )
-	barrier();
-    return( scc.cha_b_data );
-}
-
-int mac_scca_console_wait_key(struct console *co)
-{
-    int i;
-    do {
-	for( i = uSEC; i > 0; --i )
-		barrier();
-    } while( !(scc.cha_a_ctrl & 0x01) ); /* wait for rx buf filled */
-    for( i = uSEC; i > 0; --i )
-	barrier();
-    return( scc.cha_a_data );
-}
-#endif
-
 /* The following two functions do a quick'n'dirty initialization of the MFP or
  * SCC serial ports. They're used by the debugging interface, kgdb, and the
  * serial console code. */
@@ -395,18 +369,12 @@
 	/* Mac modem port */
 	mac_init_scc_port( B9600|CS8, 0 );
 	mac_console_driver.write = mac_scca_console_write;
-#ifdef CONFIG_SERIAL_CONSOLE
-	mac_console_driver.wait_key = mac_scca_console_wait_key;
-#endif
 	scc_port = 0;
     }
     else if (!strcmp( m68k_debug_device, "ser2" )) {
 	/* Mac printer port */
 	mac_init_scc_port( B9600|CS8, 1 );
 	mac_console_driver.write = mac_sccb_console_write;
-#ifdef CONFIG_SERIAL_CONSOLE
-	mac_console_driver.wait_key = mac_sccb_console_wait_key;
-#endif
 	scc_port = 1;
     }
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mac/misc.c linux/arch/m68k/mac/misc.c
--- linux.orig/arch/m68k/mac/misc.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/mac/misc.c	2002-08-01 06:42:45.000000000 +0000
@@ -11,7 +11,7 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/time.h>
-
+#include <linux/rtc.h>
 #include <linux/mm.h>
 
 #include <linux/adb.h>
@@ -595,7 +595,7 @@
  * Read/write the hardware clock.
  */
 
-int mac_hwclk(int op, struct hwclk_time *t)
+int mac_hwclk(int op, struct rtc_time *t)
 {
 	unsigned long now;
 
@@ -613,19 +613,19 @@
 			now = 0;
 		}
 
-		t->wday = 0;
+		t->tm_wday = 0;
 		unmktime(now, 0,
-			 &t->year, &t->mon, &t->day,
-			 &t->hour, &t->min, &t->sec);
+			 &t->tm_year, &t->tm_mon, &t->tm_mday,
+			 &t->tm_hour, &t->tm_min, &t->tm_sec);
 		printk("mac_hwclk: read %04d-%02d-%-2d %02d:%02d:%02d\n",
-			t->year + 1900, t->mon + 1, t->day, t->hour, t->min, t->sec);
+			t->tm_year + 1900, t->tm_mon + 1, t->tm_mday, t->tm_hour, t->tm_min, t->tm_sec);
 	} else { /* write */
 		printk("mac_hwclk: tried to write %04d-%02d-%-2d %02d:%02d:%02d\n",
-			t->year + 1900, t->mon + 1, t->day, t->hour, t->min, t->sec);
+			t->tm_year + 1900, t->tm_mon + 1, t->tm_mday, t->tm_hour, t->tm_min, t->tm_sec);
 
 #if 0	/* it trashes my rtc */
-		now = mktime(t->year + 1900, t->mon + 1, t->day,
-			     t->hour, t->min, t->sec);
+		now = mktime(t->tm_year + 1900, t->tm_mon + 1, t->tm_mday,
+			     t->tm_hour, t->tm_min, t->tm_sec);
 
 		if (macintosh_config->adb_type == MAC_ADB_II) {
 			via_write_time(now);
@@ -648,11 +648,11 @@
 
 int mac_set_clock_mmss (unsigned long nowtime)
 {
-	struct hwclk_time now;
+	struct rtc_time now;
 
 	mac_hwclk(0, &now);
-	now.sec = nowtime % 60;
-	now.min = (nowtime / 60) % 60;
+	now.tm_sec = nowtime % 60;
+	now.tm_min = (nowtime / 60) % 60;
 	mac_hwclk(1, &now);
 
 	return 0;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/math-emu/fp_emu.h linux/arch/m68k/math-emu/fp_emu.h
--- linux.orig/arch/m68k/math-emu/fp_emu.h	2001-02-13 22:13:43.000000000 +0000
+++ linux/arch/m68k/math-emu/fp_emu.h	2002-08-01 06:42:28.000000000 +0000
@@ -38,7 +38,9 @@
 #ifndef _FP_EMU_H
 #define _FP_EMU_H
 
+#ifdef __ASSEMBLY__
 #include "../kernel/m68k_defs.h"
+#endif
 #include <asm/math-emu.h>
 
 #ifndef __ASSEMBLY__
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/math-emu/multi_arith.h linux/arch/m68k/math-emu/multi_arith.h
--- linux.orig/arch/m68k/math-emu/multi_arith.h	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/math-emu/multi_arith.h	2002-08-01 06:42:41.000000000 +0000
@@ -376,7 +376,7 @@
 	asm ("divu.l %2,%1:%0" : "=d" (quot), "=d" (rem)		\
 		: "dm" (div), "1" (srch), "0" (srcl))
 #define fp_add64(dest1, dest2, src1, src2) ({				\
-	asm ("add.l %1,%0" : "=d,=dm" (dest2)				\
+	asm ("add.l %1,%0" : "=d,dm" (dest2)				\
 		: "dm,d" (src2), "0,0" (dest2));			\
 	asm ("addx.l %1,%0" : "=d" (dest1)				\
 		: "d" (src1), "0" (dest1));				\
@@ -391,14 +391,14 @@
 		: "d" (0), "0" (dest->m32[0]));				\
 })
 #define fp_sub64(dest, src) ({						\
-	asm ("sub.l %1,%0" : "=d,=dm" (dest.m32[1])			\
+	asm ("sub.l %1,%0" : "=d,dm" (dest.m32[1])			\
 		: "dm,d" (src.m32[1]), "0,0" (dest.m32[1]));		\
 	asm ("subx.l %1,%0" : "=d" (dest.m32[0])			\
 		: "d" (src.m32[0]), "0" (dest.m32[0]));			\
 })
 #define fp_sub96c(dest, srch, srcm, srcl) ({				\
 	char carry;							\
-	asm ("sub.l %1,%0" : "=d,=dm" (dest.m32[2])			\
+	asm ("sub.l %1,%0" : "=d,dm" (dest.m32[2])			\
 		: "dm,d" (srcl), "0,0" (dest.m32[2]));			\
 	asm ("subx.l %1,%0" : "=d" (dest.m32[1])			\
 		: "d" (srcm), "0" (dest.m32[1]));			\
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mm/fault.c linux/arch/m68k/mm/fault.c
--- linux.orig/arch/m68k/mm/fault.c	2001-03-19 20:35:10.000000000 +0000
+++ linux/arch/m68k/mm/fault.c	2002-08-01 06:42:42.000000000 +0000
@@ -152,22 +152,25 @@
 	 * make sure we exit gracefully rather than endlessly redo
 	 * the fault.
 	 */
+
+ survive:
 	fault = handle_mm_fault(mm, vma, address, write);
 #ifdef DEBUG
  	printk("handle_mm_fault returns %d\n",fault);
 #endif
-	if (fault < 0)
-		goto out_of_memory;
-	if (!fault)
+	switch (fault) {
+	case 1:
+		current->min_flt++;
+		break;
+	case 2:
+		current->maj_flt++;
+		break;
+	case 0:
 		goto bus_err;
+	default:
+		goto out_of_memory;
+	}
 
-	/* There seems to be a missing invalidate somewhere in do_no_page.
-	 * Until I found it, this one cures the problem and makes
-	 * 1.2 run on the 68040 (Martin Apel).
-	 */
-	#warning should be obsolete now...
-	if (CPU_IS_040_OR_060)
-		flush_tlb_page(vma, address);
 	up_read(&mm->mmap_sem);
 	return 0;
 
@@ -176,6 +179,14 @@
  * us unable to handle the page fault gracefully.
  */
 out_of_memory:
+	up_read(&mm->mmap_sem);
+	if (current->pid == 1) {
+		current->policy |= SCHED_YIELD;
+		schedule();
+		down_read(&mm->mmap_sem);
+		goto survive;
+	}
+	
 	printk("VM: killing process %s\n", current->comm);
 	if (user_mode(regs))
 		do_exit(SIGKILL);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mm/memory.c linux/arch/m68k/mm/memory.c
--- linux.orig/arch/m68k/mm/memory.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/mm/memory.c	2002-08-01 06:42:32.000000000 +0000
@@ -253,10 +253,6 @@
 	if (voff == 0)
 		return m68k_memory[i-1].addr + m68k_memory[i-1].size;
 
-	/* As a special case allow `__pa(high_memory)'.  */
-	if (voff == 0)
-		return m68k_memory[i-1].addr + m68k_memory[i-1].size;
-
 	return mm_vtop_fallback(vaddr);
 }
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mvme147/config.c linux/arch/m68k/mvme147/config.c
--- linux.orig/arch/m68k/mvme147/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/mvme147/config.c	2002-08-01 06:42:36.000000000 +0000
@@ -48,7 +48,7 @@
 extern unsigned long mvme147_gettimeoffset (void);
 extern void mvme147_gettod (int *year, int *mon, int *day, int *hour,
                            int *min, int *sec);
-extern int mvme147_hwclk (int, struct hwclk_time *);
+extern int mvme147_hwclk (int, struct rtc_time *);
 extern int mvme147_set_clock_mmss (unsigned long);
 extern void mvme147_check_partition (struct gendisk *hd, unsigned int dev);
 extern void mvme147_reset (void);
@@ -184,7 +184,7 @@
 	return ((b>>4)*10 + (b&15));
 }
 
-int mvme147_hwclk(int op, struct hwclk_time *t)
+int mvme147_hwclk(int op, struct rtc_time *t)
 {
 	return 0;
 }
@@ -241,31 +241,7 @@
 	restore_flags(flags);
 }
 
-
-static int m147_scc_wait_key (struct console *co)
-{
-	volatile unsigned char *p = (volatile char *)M147_SCC_A_ADDR;
-	unsigned long	flags;
-	int		c;
-
-	/* wait for rx buf filled */
-	while ((*p & 0x01) == 0)
-		;
-
-	save_flags(flags);
-	cli();
-
-	*p = 8;
-	scc_delay();
-	c = *p;
-
-	restore_flags(flags);
-	return c;
-}
-
-
 void mvme147_init_console_port (struct console *co, int cflag)
 {
 	co->write    = m147_scc_write;
-	co->wait_key = m147_scc_wait_key;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/mvme16x/config.c linux/arch/m68k/mvme16x/config.c
--- linux.orig/arch/m68k/mvme16x/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/mvme16x/config.c	2002-08-01 06:42:38.000000000 +0000
@@ -52,7 +52,7 @@
 extern unsigned long mvme16x_gettimeoffset (void);
 extern void mvme16x_gettod (int *year, int *mon, int *day, int *hour,
                            int *min, int *sec);
-extern int mvme16x_hwclk (int, struct hwclk_time *);
+extern int mvme16x_hwclk (int, struct rtc_time *);
 extern int mvme16x_set_clock_mmss (unsigned long);
 extern void mvme16x_check_partition (struct gendisk *hd, unsigned int dev);
 extern void mvme16x_mksound( unsigned int count, unsigned int ticks );
@@ -291,7 +291,7 @@
 	return ((b>>4)*10 + (b&15));
 }
 
-int mvme16x_hwclk(int op, struct hwclk_time *t)
+int mvme16x_hwclk(int op, struct rtc_time *t)
 {
 	return 0;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/q40/config.c linux/arch/m68k/q40/config.c
--- linux.orig/arch/m68k/q40/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/q40/config.c	2002-08-01 06:42:44.000000000 +0000
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/major.h>
 #include <linux/serial_reg.h>
+#include <linux/rtc.h>
 
 #include <asm/io.h>
 #include <asm/rtc.h>
@@ -36,7 +37,6 @@
 #include <asm/q40_master.h>
 #include <asm/keyboard.h>
 
-extern void floppy_eject(void);
 extern void floppy_setup(char *str, int *ints);
 
 extern int q40kbd_translate(unsigned char scancode, unsigned char *keycode,
@@ -56,7 +56,7 @@
 extern unsigned long q40_gettimeoffset (void);
 extern void q40_gettod (int *year, int *mon, int *day, int *hour,
                            int *min, int *sec);
-extern int q40_hwclk (int, struct hwclk_time *);
+extern int q40_hwclk (int, struct rtc_time *);
 extern int q40_set_clock_mmss (unsigned long);
 extern void q40_reset (void);
 void q40_halt(void);
@@ -73,10 +73,8 @@
 
 extern int ql_ticks;
 
-static int q40_wait_key(struct console *co){return 0;}
 static struct console q40_console_driver = {
 	name:		"debug",
-	wait_key:	q40_wait_key,
 	flags:		CON_PRINTBUFFER,
 	index:		-1,
 };
@@ -298,14 +296,14 @@
 extern void q40_gettod (int *year, int *mon, int *day, int *hour,
                            int *min, int *sec)
 {
-	RTC_CTRL |= RTC_READ;
-	*year = bcd2bin (RTC_YEAR);
-	*mon = bcd2bin (RTC_MNTH);
-	*day = bcd2bin (RTC_DATE);
-	*hour = bcd2bin (RTC_HOUR);
-	*min = bcd2bin (RTC_MINS);
-	*sec = bcd2bin (RTC_SECS);
-	RTC_CTRL &= ~(RTC_READ);
+	Q40_RTC_CTRL |= Q40_RTC_READ;
+	*year = bcd2bin (Q40_RTC_YEAR);
+	*mon = bcd2bin (Q40_RTC_MNTH);
+	*day = bcd2bin (Q40_RTC_DATE);
+	*hour = bcd2bin (Q40_RTC_HOUR);
+	*min = bcd2bin (Q40_RTC_MINS);
+	*sec = bcd2bin (Q40_RTC_SECS);
+	Q40_RTC_CTRL &= ~(Q40_RTC_READ);
 
 }
 
@@ -326,39 +324,39 @@
  * };
  */
 
-int q40_hwclk(int op, struct hwclk_time *t)
+int q40_hwclk(int op, struct rtc_time *t)
 {
         if (op)
 	{	/* Write.... */
-	        RTC_CTRL |= RTC_WRITE;
+	        Q40_RTC_CTRL |= Q40_RTC_WRITE;
 
-		RTC_SECS = bin2bcd(t->sec);
-		RTC_MINS = bin2bcd(t->min);
-		RTC_HOUR = bin2bcd(t->hour);
-		RTC_DATE = bin2bcd(t->day);
-		RTC_MNTH = bin2bcd(t->mon + 1);
-		RTC_YEAR = bin2bcd(t->year%100);
-		if (t->wday >= 0)
-			RTC_DOW = bin2bcd(t->wday+1);
+		Q40_RTC_SECS = bin2bcd(t->tm_sec);
+		Q40_RTC_MINS = bin2bcd(t->tm_min);
+		Q40_RTC_HOUR = bin2bcd(t->tm_hour);
+		Q40_RTC_DATE = bin2bcd(t->tm_mday);
+		Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
+		Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
+		if (t->tm_wday >= 0)
+			Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
 
-	        RTC_CTRL &= ~(RTC_WRITE);
+	        Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 	}
 	else
 	{	/* Read....  */
-	  RTC_CTRL |= RTC_READ;
+	  Q40_RTC_CTRL |= Q40_RTC_READ;
 
-	  t->year = bcd2bin (RTC_YEAR);
-	  t->mon  = bcd2bin (RTC_MNTH)-1;
-	  t->day  = bcd2bin (RTC_DATE);
-	  t->hour = bcd2bin (RTC_HOUR);
-	  t->min  = bcd2bin (RTC_MINS);
-	  t->sec  = bcd2bin (RTC_SECS);
+	  t->tm_year = bcd2bin (Q40_RTC_YEAR);
+	  t->tm_mon  = bcd2bin (Q40_RTC_MNTH)-1;
+	  t->tm_mday = bcd2bin (Q40_RTC_DATE);
+	  t->tm_hour = bcd2bin (Q40_RTC_HOUR);
+	  t->tm_min  = bcd2bin (Q40_RTC_MINS);
+	  t->tm_sec  = bcd2bin (Q40_RTC_SECS);
 
-	  RTC_CTRL &= ~(RTC_READ);
+	  Q40_RTC_CTRL &= ~(Q40_RTC_READ);
 	  
-	  if (t->year < 70)
-	    t->year += 100;
-	  t->wday = bcd2bin(RTC_DOW)-1;
+	  if (t->tm_year < 70)
+	    t->tm_year += 100;
+	  t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
 
 	}
 
@@ -378,16 +376,16 @@
 	int rtc_minutes;
 
 
-	rtc_minutes = bcd2bin (RTC_MINS);
+	rtc_minutes = bcd2bin (Q40_RTC_MINS);
 
 	if ((rtc_minutes < real_minutes
 		? real_minutes - rtc_minutes
 			: rtc_minutes - real_minutes) < 30)
 	{	   
-	        RTC_CTRL |= RTC_WRITE;
-		RTC_MINS = bin2bcd(real_minutes);
-		RTC_SECS = bin2bcd(real_seconds);
-		RTC_CTRL &= ~(RTC_WRITE);
+	        Q40_RTC_CTRL |= Q40_RTC_WRITE;
+		Q40_RTC_MINS = bin2bcd(real_minutes);
+		Q40_RTC_SECS = bin2bcd(real_seconds);
+		Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 	}
 	else
 		retval = -1;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/q40/q40ints.c linux/arch/m68k/q40/q40ints.c
--- linux.orig/arch/m68k/q40/q40ints.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/q40/q40ints.c	2002-08-01 06:42:39.000000000 +0000
@@ -231,7 +231,6 @@
 
 static void q40_timer_int (int irq, void * dev, struct pt_regs * regs)
 {
-#if (HZ==100)
     ql_ticks = ql_ticks ? 0 : 1;
     if (sound_ticks)
       {
@@ -240,16 +239,9 @@
 	*DAC_LEFT=sval;
 	*DAC_RIGHT=sval;
       }
-#if defined(CONFIG_Q40RTC) || defined(CONFIG_GEN_RTC)
-    if (gen_rtc_irq_ctrl && (q40rtc_oldsecs != RTC_SECS))
-      {
-	q40rtc_oldsecs = RTC_SECS;
-	gen_rtc_irq_flags = RTC_UIE;
-	gen_rtc_interrupt(0);
-      }
-#endif
+
     if (ql_ticks) return;
-#endif
+
     q40_timer_routine(irq, dev, regs);
 }
 
@@ -258,30 +250,14 @@
     int timer_irq;
 
     q40_timer_routine = timer_routine;
-
-#if (HZ==10000)
-    timer_irq=Q40_IRQ_SAMPLE;
-#else
     timer_irq=Q40_IRQ_FRAME;
-#endif
-
-    /*printk("registering sched/timer IRQ %d, handler %p\n", timer_irq,q40_timer_int);*/
-    /*printk("timer routine %p\n",q40_timer_routine);*/
 
     if (request_irq(timer_irq, q40_timer_int, 0,
 				"timer", q40_timer_int))
 	panic ("Couldn't register timer int");
 
-#if (HZ==10000)
-    master_outb(SAMPLE_LOW,SAMPLE_RATE_REG);
-    master_outb(-1,SAMPLE_CLEAR_REG);
-    master_outb(1,SAMPLE_ENABLE_REG);
-#else
-    master_outb(-1,FRAME_CLEAR_REG);   /* not necessary ? */
-#if (HZ==100)
+    master_outb(-1,FRAME_CLEAR_REG);
     master_outb( 1,FRAME_RATE_REG);
-#endif
-#endif
 }
 
 
@@ -294,20 +270,20 @@
 struct IRQ_TABLE{ unsigned mask; int irq ;};
 #if 0
 static struct IRQ_TABLE iirqs[]={
-  {IRQ_FRAME_MASK,Q40_IRQ_FRAME},
-  {IRQ_KEYB_MASK,Q40_IRQ_KEYBOARD},
+  {Q40_IRQ_FRAME_MASK,Q40_IRQ_FRAME},
+  Q40_{IRQ_KEYB_MASK,Q40_IRQ_KEYBOARD},
   {0,0}};
 #endif
 static struct IRQ_TABLE eirqs[]={
-  {IRQ3_MASK,3},                   /* ser 1 */
-  {IRQ4_MASK,4},                   /* ser 2 */
-  {IRQ14_MASK,14},                 /* IDE 1 */
-  {IRQ15_MASK,15},                 /* IDE 2 */
-  {IRQ6_MASK,6},                   /* floppy */
-  {IRQ7_MASK,7},                   /* par */
+  {Q40_IRQ3_MASK,3},                   /* ser 1 */
+  {Q40_IRQ4_MASK,4},                   /* ser 2 */
+  {Q40_IRQ14_MASK,14},                 /* IDE 1 */
+  {Q40_IRQ15_MASK,15},                 /* IDE 2 */
+  {Q40_IRQ6_MASK,6},                   /* floppy, handled elsewhere */
+  {Q40_IRQ7_MASK,7},                   /* par */
 
-  {IRQ5_MASK,5},
-  {IRQ10_MASK,10},
+  {Q40_IRQ5_MASK,5},
+  {Q40_IRQ10_MASK,10},
 
 
 
@@ -322,7 +298,7 @@
 
 #define IRQ_INPROGRESS 1
 /*static unsigned short saved_mask;*/
-static int do_tint=0;
+//static int do_tint=0;
 
 #define DEBUG_Q40INT
 /*#define IP_USE_DISABLE *//* would be nice, but crashes ???? */
@@ -334,101 +310,82 @@
 /* got level 2 interrupt, dispatch to ISA or keyboard/timer IRQs */
 void q40_irq2_handler (int vec, void *devname, struct pt_regs *fp)
 {
-  unsigned mir;
-	unsigned mer;
-	int irq,i;
+  unsigned mir, mer;
+  int irq,i;
 
  repeat:
   mir=master_inb(IIRQ_REG);
-  if (mir&IRQ_FRAME_MASK) 
-    { /* dont loose  ticks */
-      do_tint++;
-      master_outb(-1,FRAME_CLEAR_REG);
-    }
-	if ((mir&IRQ_SER_MASK) || (mir&IRQ_EXT_MASK)) 
-	  {
-	    /* some ISA dev caused the int */
-	    mer=master_inb(EIRQ_REG);
-	    for (i=0; eirqs[i].mask; i++)
-	      {
-		if (mer&(eirqs[i].mask)) 
-		  {
-		    irq=eirqs[i].irq;
+  if (mir&Q40_IRQ_FRAME_MASK) {
+	  irq_tab[Q40_IRQ_FRAME].count++;
+	  irq_tab[Q40_IRQ_FRAME].handler(Q40_IRQ_FRAME,irq_tab[Q40_IRQ_FRAME].dev_id,fp);   
+	  master_outb(-1,FRAME_CLEAR_REG);
+  }
+  if ((mir&Q40_IRQ_SER_MASK) || (mir&Q40_IRQ_EXT_MASK)) {
+	  mer=master_inb(EIRQ_REG);
+	  for (i=0; eirqs[i].mask; i++) {
+		  if (mer&(eirqs[i].mask)) {
+			  irq=eirqs[i].irq;
 /*
  * There is a little mess wrt which IRQ really caused this irq request. The
  * main problem is that IIRQ_REG and EIRQ_REG reflect the state when they
  * are read - which is long after the request came in. In theory IRQs should
  * not just go away but they occassionally do
  */
-	      if (irq>4 && irq<=15 && mext_disabled) 
-		{
-		  /*aliased_irq++;*/
-		  goto iirq;
-		}
-		    if (irq_tab[irq].handler == q40_defhand )
-		      {
-			printk("handler for IRQ %d not defined\n",irq);
-			continue; /* ignore uninited INTs :-( */
-		      }
-		    if ( irq_tab[irq].state & IRQ_INPROGRESS )
-		      {
-		  /* some handlers do sti() for irq latency reasons, */
-		  /* however reentering an active irq handler is not permitted */
+			  if (irq>4 && irq<=15 && mext_disabled) {
+				  /*aliased_irq++;*/
+				  goto iirq;
+			  }
+			  if (irq_tab[irq].handler == q40_defhand ) {
+				  printk("handler for IRQ %d not defined\n",irq);
+				  continue; /* ignore uninited INTs :-( */
+			  }
+			  if ( irq_tab[irq].state & IRQ_INPROGRESS ) {
+				  /* some handlers do sti() for irq latency reasons, */
+				  /* however reentering an active irq handler is not permitted */
 #ifdef IP_USE_DISABLE
-		  /* in theory this is the better way to do it because it still */
-		  /* lets through eg the serial irqs, unfortunately it crashes */
-		  disable_irq(irq);
-		  disabled=1;
+				  /* in theory this is the better way to do it because it still */
+				  /* lets through eg the serial irqs, unfortunately it crashes */
+				  disable_irq(irq);
+				  disabled=1;
 #else
-			/*printk("IRQ_INPROGRESS detected for irq %d, disabling - %s disabled\n",irq,disabled ? "already" : "not yet"); */
-		  fp->sr = (((fp->sr) & (~0x700))+0x200);
-			disabled=1;
-#endif
-		  goto iirq;
-		      }
-	      irq_tab[irq].count++; 
-		    irq_tab[irq].state |= IRQ_INPROGRESS;
-		    irq_tab[irq].handler(irq,irq_tab[irq].dev_id,fp);
-	      irq_tab[irq].state &= ~IRQ_INPROGRESS;
-
-		    /* naively enable everything, if that fails than    */
-		    /* this function will be reentered immediately thus */
-		    /* getting another chance to disable the IRQ        */
-
-		    if ( disabled ) 
-		      {
+				  /*printk("IRQ_INPROGRESS detected for irq %d, disabling - %s disabled\n",irq,disabled ? "already" : "not yet"); */
+				  fp->sr = (((fp->sr) & (~0x700))+0x200);
+				  disabled=1;
+#endif
+				  goto iirq;
+			  }
+			  irq_tab[irq].count++; 
+			  irq_tab[irq].state |= IRQ_INPROGRESS;
+			  irq_tab[irq].handler(irq,irq_tab[irq].dev_id,fp);
+			  irq_tab[irq].state &= ~IRQ_INPROGRESS;
+			  
+			  /* naively enable everything, if that fails than    */
+			  /* this function will be reentered immediately thus */
+			  /* getting another chance to disable the IRQ        */
+			  
+			  if ( disabled ) {
 #ifdef IP_USE_DISABLE
-			if (irq>4){
-			  disabled=0;
-			  enable_irq(irq);}
+				  if (irq>4){
+					  disabled=0;
+					  enable_irq(irq);}
 #else
-			disabled=0;
-			/*printk("reenabling irq %d\n",irq); */
+				  disabled=0;
+				  /*printk("reenabling irq %d\n",irq); */
 #endif
-		      }
-	      goto repeat;  /* return;  */
+			  }
+// used to do 'goto repeat;' her, this delayed bh processing too long
+			  return;
 		  }
-	      }
-	    if (mer && ccleirq>0 && !aliased_irq) 
-	      printk("ISA interrupt from unknown source? EIRQ_REG = %x\n",mer),ccleirq--;
-	  } 
- iirq:
-	mir=master_inb(IIRQ_REG);
-	if (mir&IRQ_FRAME_MASK) 
-	  {
-	    do_tint++;
-	    master_outb(-1,FRAME_CLEAR_REG);
-	  }
-	for(;do_tint>0;do_tint--) 
-	  {
-	    irq_tab[Q40_IRQ_FRAME].count++;
-	    irq_tab[Q40_IRQ_FRAME].handler(Q40_IRQ_FRAME,irq_tab[Q40_IRQ_FRAME].dev_id,fp);    
-	  }
-	if (mir&IRQ_KEYB_MASK) /* may handle it even if actually disabled*/
-	  {
-	    irq_tab[Q40_IRQ_KEYBOARD].count++;
-	    irq_tab[Q40_IRQ_KEYBOARD].handler(Q40_IRQ_KEYBOARD,irq_tab[Q40_IRQ_KEYBOARD].dev_id,fp);
 	  }
+	  if (mer && ccleirq>0 && !aliased_irq) 
+		  printk("ISA interrupt from unknown source? EIRQ_REG = %x\n",mer),ccleirq--;
+  } 
+ iirq:
+  mir=master_inb(IIRQ_REG);
+  if (mir&Q40_IRQ_KEYB_MASK) {
+	  irq_tab[Q40_IRQ_KEYBOARD].count++;
+	  irq_tab[Q40_IRQ_KEYBOARD].handler(Q40_IRQ_KEYBOARD,irq_tab[Q40_IRQ_KEYBOARD].dev_id,fp);
+  }
 }
 
 int q40_get_irq_list (char *buf)
@@ -451,25 +408,16 @@
 
 static void q40_defhand (int irq, void *dev_id, struct pt_regs *fp)
 {
-#if 0
 	printk ("Unknown q40 interrupt 0x%02x\n", irq);
-#endif
 }
 static void sys_default_handler(int lev, void *dev_id, struct pt_regs *regs)
 {
-#if 0
-        if (ints_inited)
-#endif
-	  printk ("Uninitialised interrupt level %d\n", lev);
-#if 0
-	else
-	  printk ("Interrupt before interrupt initialisation\n");
-#endif
+	printk ("Uninitialised interrupt level %d\n", lev);
 }
 
  void (*q40_sys_default_handler[SYS_IRQS]) (int, void *, struct pt_regs *) = {
-   sys_default_handler,sys_default_handler,sys_default_handler,sys_default_handler,
-   sys_default_handler,sys_default_handler,sys_default_handler,sys_default_handler
+	 sys_default_handler,sys_default_handler,sys_default_handler,sys_default_handler,
+	 sys_default_handler,sys_default_handler,sys_default_handler,sys_default_handler
  };
 
 
@@ -489,16 +437,15 @@
 void q40_disable_irq (unsigned int irq)
 {
   /* disable ISA iqs : only do something if the driver has been
-  * verified to be Q40 "compatible" - right now IDE, NE2K
-  * Any driver should not attempt to sleep accross disable_irq !!
-  */
+   * verified to be Q40 "compatible" - right now IDE, NE2K
+   * Any driver should not attempt to sleep accross disable_irq !!
+   */
 
-  if ( irq>=5 && irq<=15 ) 
-    {
+  if ( irq>=5 && irq<=15 ) {
     master_outb(0,EXT_ENABLE_REG);
-      mext_disabled++;
-      if (mext_disabled>1) printk("disable_irq nesting count %d\n",mext_disabled);
-    }
+    mext_disabled++;
+    if (mext_disabled>1) printk("disable_irq nesting count %d\n",mext_disabled);
+  }
 }
 
 unsigned long q40_probe_irq_on (void)
@@ -513,4 +460,5 @@
 /*
  * Local variables:
  * compile-command: "m68k-linux-gcc -D__KERNEL__ -I/home/rz/lx/linux-2.2.6/include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -ffixed-a2 -m68040   -c -o q40ints.o q40ints.c"
+ * End:
  */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/sun3/config.c linux/arch/m68k/sun3/config.c
--- linux.orig/arch/m68k/sun3/config.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/sun3/config.c	2002-08-01 06:42:46.000000000 +0000
@@ -42,7 +42,7 @@
 extern void idprom_init (void);
 extern void sun3_gettod (int *yearp, int *monp, int *dayp,
                    int *hourp, int *minp, int *secp);
-extern int sun3_hwclk(int set, struct hwclk_time *t);
+extern int sun3_hwclk(int set, struct rtc_time *t);
 
 extern void sun_serial_setup(void);
 volatile char* clock_va; 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/sun3/intersil.c linux/arch/m68k/sun3/intersil.c
--- linux.orig/arch/m68k/sun3/intersil.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/sun3/intersil.c	2002-08-01 06:42:29.000000000 +0000
@@ -11,6 +11,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/rtc.h>
 
 #include <asm/system.h>
 #include <asm/rtc.h>
@@ -57,7 +58,7 @@
 
 /* get/set hwclock */
 
-int sun3_hwclk(int set, struct hwclk_time *t)
+int sun3_hwclk(int set, struct rtc_time *t)
 {
 	volatile struct intersil_dt *todintersil;
 	unsigned long flags;
@@ -71,23 +72,23 @@
 	/* set or read the clock */
 	if(set) {
 		todintersil->csec = 0;
-		todintersil->hour = t->hour;
-		todintersil->minute = t->min;
-		todintersil->second = t->sec;
-		todintersil->month = t->mon;
-		todintersil->day = t->day;
-		todintersil->year = t->year - 68;
-		todintersil->weekday = t->wday;
+		todintersil->hour = t->tm_hour;
+		todintersil->minute = t->tm_min;
+		todintersil->second = t->tm_sec;
+		todintersil->month = t->tm_mon;
+		todintersil->day = t->tm_mday;
+		todintersil->year = t->tm_year - 68;
+		todintersil->weekday = t->tm_wday;
 	} else {
 		/* read clock */
-		t->sec = todintersil->csec;
-		t->hour = todintersil->hour;
-		t->min = todintersil->minute;
-		t->sec = todintersil->second;
-		t->mon = todintersil->month;
-		t->day = todintersil->day;
-		t->year = todintersil->year + 68;
-		t->wday = todintersil->weekday;
+		t->tm_sec = todintersil->csec;
+		t->tm_hour = todintersil->hour;
+		t->tm_min = todintersil->minute;
+		t->tm_sec = todintersil->second;
+		t->tm_mon = todintersil->month;
+		t->tm_mday = todintersil->day;
+		t->tm_year = todintersil->year + 68;
+		t->tm_wday = todintersil->weekday;
 	}
 
 	intersil_clock->cmd_reg = START_VAL;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/sun3/sun3dvma.c linux/arch/m68k/sun3/sun3dvma.c
--- linux.orig/arch/m68k/sun3/sun3dvma.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/sun3/sun3dvma.c	2002-08-01 06:42:35.000000000 +0000
@@ -14,6 +14,8 @@
 #include <asm/pgtable.h>
 #include <asm/dvma.h>
 
+#undef DVMA_DEBUG
+
 #ifdef CONFIG_SUN3X
 extern void dvma_unmap_iommu(unsigned long baddr, int len);
 #else
@@ -22,6 +24,10 @@
 }
 #endif
 
+#ifdef CONFIG_SUN3
+extern void sun3_dvma_init(void);
+#endif
+
 unsigned long iommu_use[IOMMU_TOTAL_ENTRIES];
 
 #define dvma_index(baddr) ((baddr - DVMA_START) >> DVMA_PAGE_SHIFT)
@@ -39,6 +45,60 @@
 static struct list_head hole_cache;
 static struct hole initholes[64];
 
+#ifdef DVMA_DEBUG
+
+static unsigned long dvma_allocs = 0;
+static unsigned long dvma_frees = 0;
+static unsigned long long dvma_alloc_bytes = 0;
+static unsigned long long dvma_free_bytes = 0;
+
+static void print_use(void) 
+{
+	
+	int i;
+	int j = 0;
+
+	printk("dvma entry usage:\n");
+	
+	for(i = 0; i < IOMMU_TOTAL_ENTRIES; i++) {
+		if(!iommu_use[i])
+			continue;
+		
+		j++;
+
+		printk("dvma entry: %08lx len %08lx\n", 
+		       ( i << DVMA_PAGE_SHIFT) + DVMA_START,
+		       iommu_use[i]);
+	}
+
+	printk("%d entries in use total\n", j);
+
+	printk("allocation/free calls: %lu/%lu\n", dvma_allocs, dvma_frees);
+	printk("allocation/free bytes: %Lx/%Lx\n", dvma_alloc_bytes, 
+	       dvma_free_bytes);
+}
+
+static void print_holes(struct list_head *holes)
+{
+	
+	struct list_head *cur;
+	struct hole *hole;
+
+	printk("listing dvma holes\n");
+	list_for_each(cur, holes) {
+		hole = list_entry(cur, struct hole, list);
+		
+		if((hole->start == 0) && (hole->end == 0) && (hole->size == 0))
+			continue;
+		
+		printk("hole: start %08lx end %08lx size %08lx\n", hole->start, hole->end, hole->size);
+	}
+	
+	printk("end of hole listing...\n");
+	
+}
+#endif DVMA_DEBUG
+
 static inline int refill(void)
 {
 
@@ -93,7 +153,11 @@
 	struct hole *hole;
 
 	if(list_empty(&hole_list)) {
-		printk("out of dvma holes!\n");
+#ifdef DVMA_DEBUG
+		printk("out of dvma holes! (printing hole cache)\n");
+		print_holes(&hole_cache);
+		print_use();
+#endif
 		BUG();
 	}
 
@@ -111,11 +175,19 @@
 			hole->end -= newlen;
 			hole->size -= newlen;
 			dvma_entry_use(hole->end) = newlen;
+#ifdef DVMA_DEBUG
+			dvma_allocs++;
+			dvma_alloc_bytes += newlen;
+#endif
 			return hole->end;
 		} else if(hole->size == newlen) {
 			list_del(&(hole->list));
 			list_add(&(hole->list), &hole_cache);
 			dvma_entry_use(hole->start) = newlen;
+#ifdef DVMA_DEBUG
+			dvma_allocs++;
+			dvma_alloc_bytes += newlen;
+#endif
 			return hole->start;
 		}
 
@@ -140,6 +212,11 @@
 	baddr &= DVMA_PAGE_MASK;
 	dvma_unmap_iommu(baddr, len);
 
+#ifdef DVMA_DEBUG
+	dvma_frees++;
+	dvma_free_bytes += len;
+#endif
+
 	list_for_each(cur, &hole_list) {
 		hole = list_entry(cur, struct hole, list);
 		
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/sun3x/prom.c linux/arch/m68k/sun3x/prom.c
--- linux.orig/arch/m68k/sun3x/prom.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/sun3x/prom.c	2002-08-01 06:42:42.000000000 +0000
@@ -96,7 +96,6 @@
 	sun3x_prom_write,  	/* write */
 	NULL,			/* read */
 	NULL,			/* device */
-	NULL,			/* wait_key */
 	NULL,			/* unblank */
 	NULL,			/* setup */
 	CON_PRINTBUFFER,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/sun3x/time.c linux/arch/m68k/sun3x/time.c
--- linux.orig/arch/m68k/sun3x/time.c	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/sun3x/time.c	2002-08-01 06:42:30.000000000 +0000
@@ -10,6 +10,7 @@
 #include <linux/sched.h>
 #include <linux/kernel_stat.h>
 #include <linux/interrupt.h>
+#include <linux/rtc.h>
 
 #include <asm/irq.h>
 #include <asm/io.h>
@@ -59,7 +60,7 @@
     *(eeprom + M_CONTROL) &= ~C_READ;
 }
 
-int sun3x_hwclk(int set, struct hwclk_time *t)
+int sun3x_hwclk(int set, struct rtc_time *t)
 {
 	volatile struct mostek_dt *h = 
 		(unsigned char *)(SUN3X_EEPROM+M_CONTROL);
@@ -69,23 +70,23 @@
 	
 	if(set) {
 		h->csr |= C_WRITE;
-		h->sec = BIN_TO_BCD(t->sec);
-		h->min = BIN_TO_BCD(t->min);
-		h->hour = BIN_TO_BCD(t->hour);
-		h->wday = BIN_TO_BCD(t->wday);
-		h->mday = BIN_TO_BCD(t->day);
-		h->month = BIN_TO_BCD(t->mon);
-		h->year = BIN_TO_BCD(t->year);
+		h->sec = BIN_TO_BCD(t->tm_sec);
+		h->min = BIN_TO_BCD(t->tm_min);
+		h->hour = BIN_TO_BCD(t->tm_hour);
+		h->wday = BIN_TO_BCD(t->tm_wday);
+		h->mday = BIN_TO_BCD(t->tm_mday);
+		h->month = BIN_TO_BCD(t->tm_mon);
+		h->year = BIN_TO_BCD(t->tm_year);
 		h->csr &= ~C_WRITE;
 	} else {
 		h->csr |= C_READ;
-		t->sec = BCD_TO_BIN(h->sec);
-		t->min = BCD_TO_BIN(h->min);
-		t->hour = BCD_TO_BIN(h->hour);
-		t->wday = BCD_TO_BIN(h->wday);
-		t->day = BCD_TO_BIN(h->mday);
-		t->mon = BCD_TO_BIN(h->month);
-		t->year = BCD_TO_BIN(h->year);
+		t->tm_sec = BCD_TO_BIN(h->sec);
+		t->tm_min = BCD_TO_BIN(h->min);
+		t->tm_hour = BCD_TO_BIN(h->hour);
+		t->tm_wday = BCD_TO_BIN(h->wday);
+		t->tm_mday = BCD_TO_BIN(h->mday);
+		t->tm_mon = BCD_TO_BIN(h->month);
+		t->tm_year = BCD_TO_BIN(h->year);
 		h->csr &= ~C_READ;
 	}
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/m68k/sun3x/time.h linux/arch/m68k/sun3x/time.h
--- linux.orig/arch/m68k/sun3x/time.h	2001-06-12 02:15:27.000000000 +0000
+++ linux/arch/m68k/sun3x/time.h	2002-08-01 06:42:46.000000000 +0000
@@ -3,7 +3,7 @@
 
 extern void sun3x_gettod (int *yearp, int *monp, int *dayp,
                    int *hourp, int *minp, int *secp);
-extern int sun3x_hwclk(int set, struct hwclk_time *t);
+extern int sun3x_hwclk(int set, struct rtc_time *t);
 unsigned long sun3x_gettimeoffset (void);
 void sun3x_sched_init(void (*vector)(int, void *, struct pt_regs *));
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/Makefile linux/arch/mips/Makefile
--- linux.orig/arch/mips/Makefile	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/Makefile	2002-08-01 06:42:28.000000000 +0000
@@ -5,6 +5,7 @@
 #
 # Copyright (C) 1994, 1995, 1996 by Ralf Baechle
 # DECStation modifications by Paul M. Antoine, 1996
+# Copyright (C) 2002  Maciej W. Rozycki
 #
 # This file is included by the global makefile so that you can add your own
 # architecture-specific flags and dependencies. Remember to do have actions
@@ -22,7 +23,7 @@
 endif
 
 ifdef CONFIG_CROSSCOMPILE
-CROSS_COMPILE  = $(tool-prefix)
+CROSS_COMPILE	= $(tool-prefix)
 endif
 
 #
@@ -35,13 +36,13 @@
 # machines may also.  Since BFD is incredibly buggy with respect to
 # crossformat linking we rely on the elf2ecoff tool for format conversion.
 #
-GCCFLAGS	:= -G 0 -mno-abicalls -fno-pic
-LINKFLAGS	+= -static
+GCCFLAGS	:= -I $(TOPDIR)/include/asm/gcc
+GCCFLAGS	+= -G 0 -mno-abicalls -fno-pic -pipe
+LINKFLAGS	+= -G 0 -static # -N
 MODFLAGS	+= -mlong-calls
-LD		:= $(LD) -G 0
 
 ifdef CONFIG_REMOTE_DEBUG
-CFLAGS		:= $(CFLAGS) -g
+GCCFLAGS	+= -g
 endif
 
 #
@@ -50,6 +51,9 @@
 ifdef CONFIG_CPU_R3000
 GCCFLAGS	+= -mcpu=r3000 -mips1
 endif
+ifdef CONFIG_CPU_TX39XX
+GCCFLAGS	+= -mcpu=r3000 -mips1
+endif
 ifdef CONFIG_CPU_R6000
 GCCFLAGS	+= -mcpu=r6000 -mips2 -Wa,--trap
 endif
@@ -62,6 +66,9 @@
 ifdef CONFIG_CPU_R4X00
 GCCFLAGS	+= -mcpu=r4600 -mips2 -Wa,--trap
 endif
+ifdef CONFIG_CPU_TX49XX
+GCCFLAGS	+= -mcpu=r4600 -mips2 -Wa,--trap
+endif
 ifdef CONFIG_CPU_MIPS32
 GCCFLAGS	+= -mcpu=r4600 -mips2 -Wa,--trap
 endif
@@ -72,7 +79,7 @@
 GCCFLAGS	+= -mcpu=r5000 -mips2 -Wa,--trap
 endif
 ifdef CONFIG_CPU_R5432
-GCCFLAGS        += -mcpu=r5000 -mips2 -Wa,--trap
+GCCFLAGS	+= -mcpu=r5000 -mips2 -Wa,--trap
 endif
 ifdef CONFIG_CPU_NEVADA
 # Cannot use -mmad with currently recommended tools
@@ -83,184 +90,296 @@
 endif
 ifdef CONFIG_CPU_SB1
 GCCFLAGS	+= -mcpu=sb1 -mips2 -Wa,--trap
+ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+MODFLAGS	+= -msb1-pass1-workarounds
+endif
 endif
 
-GCCFLAGS	+= -pipe
-
-CFLAGS		:= -I $(TOPDIR)/include/asm/gcc $(CFLAGS) $(GCCFLAGS)
 AFLAGS		+= $(GCCFLAGS)
-ASFLAGS		+= $(GCCFLAGS)
+CFLAGS		+= $(GCCFLAGS)
+
 
 #
 # We unconditionally build the math emulator
 #
-CORE_FILES	+=arch/mips/math-emu/fpu_emulator.o
-SUBDIRS		+=arch/mips/math-emu
+CORE_FILES	+= arch/mips/math-emu/fpu_emulator.o
+SUBDIRS		+= arch/mips/math-emu
+
+#
+# ramdisk/initrd support
+# You need a compressed ramdisk image, named ramdisk.gz in
+# arch/mips/ramdisk
+#
+ifdef CONFIG_EMBEDDED_RAMDISK
+CORE_FILES	+= arch/mips/ramdisk/ramdisk.o
+SUBDIRS		+= arch/mips/ramdisk
+endif
+
 
 #
 # Board-dependent options and extra files
 #
+
+#
+# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+#
+ifdef CONFIG_MIPS_JAZZ
+CORE_FILES	+= arch/mips/jazz/jazz.o
+SUBDIRS		+= arch/mips/jazz arch/mips/arc
+LIBS		+= arch/mips/arc/arclib.a
+LOADADDR	:= 0x80080000
+endif
+
+#
+# Au1000 (Alchemy Semi PB1000) eval board
+#
+ifdef CONFIG_MIPS_PB1000
+LIBS		+= arch/mips/au1000/pb1000/pb1000.o \
+		   arch/mips/au1000/common/au1000.o
+SUBDIRS		+= arch/mips/au1000/pb1000 arch/mips/au1000/common
+LOADADDR	:= 0x80100000
+endif
+
+#
+# Au1000 (Alchemy Semi PB1500) eval board
+#
+ifdef CONFIG_MIPS_PB1500
+LIBS		+= arch/mips/au1000/pb1500/pb1500.o \
+		   arch/mips/au1000/common/au1000.o
+SUBDIRS		+= arch/mips/au1000/pb1500 arch/mips/au1000/common
+LOADADDR	:= 0x80100000
+endif
+
+#
+# Algorithmics P4032
+#
 ifdef CONFIG_ALGOR_P4032
-CORE_FILES    += arch/mips/algor/algor.o
-SUBDIRS       += arch/mips/algor
-LOADADDR      += 0x80000000
+CORE_FILES	+= arch/mips/algor/algor.o
+SUBDIRS		+= arch/mips/algor
+LOADADDR	:= 0x80000000
+endif
+
+#
+# Baget/MIPS
+#
+ifdef CONFIG_BAGET_MIPS
+SUBDIRS		+= arch/mips/baget arch/mips/baget/prom
+LIBS		+= arch/mips/baget/baget.a arch/mips/baget/prom/bagetlib.a
+LOADADDR	:= 0x80001000
+endif
+
+#
+# Cobalt Server
+#
+ifdef CONFIG_MIPS_COBALT
+SUBDIRS		+= arch/mips/cobalt
+CORE_FILES	+= arch/mips/cobalt/cobalt.o
+LOADADDR	:= 0x80080000
 endif
 
 #
 # DECstation family
 #
 ifdef CONFIG_DECSTATION
-CORE_FILES    += arch/mips/dec/dec.o
-SUBDIRS       += arch/mips/dec arch/mips/dec/prom
-LIBS          += arch/mips/dec/prom/rexlib.a
-LOADADDR      += 0x80040000
+CORE_FILES	+= arch/mips/dec/dec.o
+SUBDIRS		+= arch/mips/dec arch/mips/dec/prom
+LIBS		+= arch/mips/dec/prom/rexlib.a
+LOADADDR	:= 0x80040000
 endif
 
-ifdef CONFIG_MIPS_ATLAS
-LIBS          += arch/mips/mips-boards/atlas/atlas.o arch/mips/mips-boards/generic/mipsboards.o
-SUBDIRS       += arch/mips/mips-boards/generic arch/mips/mips-boards/atlas
-LOADADDR      += 0x80100000
+#
+# Galileo EV64120 Board
+#
+ifdef CONFIG_MIPS_EV64120
+LIBS		+= arch/mips/galileo-boards/ev64120/ev64120.o
+SUBDIRS		+= arch/mips/galileo-boards/ev64120
+LOADADDR	:= 0x80100000
 endif
 
-ifdef CONFIG_MIPS_MALTA
-LIBS          += arch/mips/mips-boards/malta/malta.o arch/mips/mips-boards/generic/mipsboards.o
-SUBDIRS       += arch/mips/mips-boards/malta arch/mips/mips-boards/generic
-LOADADDR      += 0x80100000
+#
+# Galileo EV96100 Board
+#
+ifdef CONFIG_MIPS_EV96100
+LIBS		+= arch/mips/galileo-boards/ev96100/ev96100.o \
+		   arch/mips/galileo-boards/generic/galboards.o
+SUBDIRS		+= arch/mips/galileo-boards/generic \
+		   arch/mips/galileo-boards/ev96100
+LOADADDR	:= 0x80100000
 endif
 
 #
-# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+# Globespan IVR eval board with QED 5231 CPU
 #
-ifdef CONFIG_MIPS_JAZZ
-CORE_FILES    += arch/mips/jazz/jazz.o
-SUBDIRS       += arch/mips/jazz arch/mips/arc
-LIBS          += arch/mips/arc/arclib.a
-LOADADDR      += 0x80080000
+ifdef CONFIG_MIPS_IVR
+LIBS		+= arch/mips/ite-boards/ivr/ivr.o \
+		   arch/mips/ite-boards/generic/it8172.o
+SUBDIRS		+= arch/mips/ite-boards/generic arch/mips/ite-boards/ivr
+LOADADDR	:= 0x80100000
 endif
 
-ifdef CONFIG_SNI_RM200_PCI
-CORE_FILES    += arch/mips/sni/sni.o
-SUBDIRS       += arch/mips/sni arch/mips/arc
-LIBS          += arch/mips/arc/arclib.a
-LOADADDR      += 0x80080000
+#
+# HP LaserJet
+#
+ifdef CONFIG_HP_LASERJET
+SUBDIRS		+= arch/mips/hp-lj
+LIBS		+= arch/mips/hp-lj/hp-lj.o
+LOADADDR	:= 0x80030000
 endif
 
-ifdef CONFIG_SGI_IP22
-CORE_FILES    += arch/mips/sgi/kernel/ip22-kern.o
-LIBS          += arch/mips/arc/arclib.a
-SUBDIRS       += arch/mips/sgi/kernel arch/mips/arc
 #
-# Set LOADADDR to >= 0x88069000 if you want to leave space for symmon,
-# 0x88002000 for production kernels.  Note that the value must be
-# 8kb aligned or the handling of the current variable will break.
+# ITE 8172 eval board with QED 5231 CPU
 #
-LOADADDR      += 0x88002000
+ifdef CONFIG_MIPS_ITE8172
+LIBS		+= arch/mips/ite-boards/qed-4n-s01b/ite.o \
+		   arch/mips/ite-boards/generic/it8172.o
+SUBDIRS		+= arch/mips/ite-boards/generic arch/mips/ite-boards/qed-4n-s01b
+LOADADDR	:= 0x80100000
 endif
 
 #
-# Baget/MIPS
+# MIPS Atlas board
 #
-ifdef CONFIG_BAGET_MIPS
-SUBDIRS       += arch/mips/baget arch/mips/baget/prom
-LIBS          += arch/mips/baget/baget.a arch/mips/baget/prom/bagetlib.a
-LOADADDR      += 0x80001000
+ifdef CONFIG_MIPS_ATLAS
+LIBS		+= arch/mips/mips-boards/atlas/atlas.o \
+		   arch/mips/mips-boards/generic/mipsboards.o
+SUBDIRS		+= arch/mips/mips-boards/generic arch/mips/mips-boards/atlas
+LOADADDR	:= 0x80100000
+endif
+
+#
+# MIPS Malta board
+#
+ifdef CONFIG_MIPS_MALTA
+LIBS		+= arch/mips/mips-boards/malta/malta.o \
+		   arch/mips/mips-boards/generic/mipsboards.o
+SUBDIRS		+= arch/mips/mips-boards/malta arch/mips/mips-boards/generic
+LOADADDR	:= 0x80100000
+endif
+
+#
+# Momentum Ocelot board
+#
+ifdef CONFIG_MOMENCO_OCELOT
+# The Ocelot setup.o must be linked early - it does the ioremap() for the
+# mips_io_port_base.
+CORE_FILES	+= arch/mips/gt64120/common/gt64120.o \
+		   arch/mips/gt64120/momenco_ocelot/momenco_ocelot.o
+SUBDIRS		+= arch/mips/gt64120/common arch/mips/gt64120/momenco_ocelot
+LOADADDR	:= 0x80100000
 endif
 
 #
 # NEC DDB Vrc-5074
 #
 ifdef CONFIG_DDB5074
-SUBDIRS       += arch/mips/ddb5074
-LIBS          += arch/mips/ddb5074/ddb5074.a
-LOADADDR      += 0x80080000
+SUBDIRS		+= arch/mips/ddb5074
+LIBS		+= arch/mips/ddb5074/ddb5074.a
+LOADADDR	:= 0x80080000
 endif
 
 #
-#
 # NEC DDB Vrc-5476
 #
 ifdef CONFIG_DDB5476
-SUBDIRS       += arch/mips/ddb5476
-LIBS          += arch/mips/ddb5476/ddb5476.a
-LOADADDR      += 0x80080000
+SUBDIRS		+= arch/mips/ddb5xxx/common arch/mips/ddb5xxx/ddb5476
+LIBS		+= arch/mips/ddb5xxx/common/ddb5xxx.o \
+		   arch/mips/ddb5xxx/ddb5476/ddb5476.o
+LOADADDR	:= 0x80080000
 endif
 
 #
-#
 # NEC DDB Vrc-5477
 #
 ifdef CONFIG_DDB5477
-SUBDIRS       += arch/mips/ddb5xxx/common arch/mips/ddb5xxx/ddb5477
-LIBS          += arch/mips/ddb5xxx/common/ddb5xxx.o \
-                 arch/mips/ddb5xxx/ddb5477/ddb5477.o
-LOADADDR      += 0x80080000
+SUBDIRS		+= arch/mips/ddb5xxx/common arch/mips/ddb5xxx/ddb5477
+LIBS		+= arch/mips/ddb5xxx/common/ddb5xxx.o \
+		   arch/mips/ddb5xxx/ddb5477/ddb5477.o
+LOADADDR	:= 0x80080000
 endif
 
 #
-# Galileo EV64120 Board
+# NEC Osprey (vr4181) board
 #
-ifdef CONFIG_MIPS_EV64120
-LIBS          += arch/mips/galileo-boards/ev64120/ev64120.o
-SUBDIRS       += arch/mips/galileo-boards/ev64120
-LOADADDR      += 0x80100000
+ifdef CONFIG_NEC_OSPREY
+SUBDIRS		+= arch/mips/vr4181/common arch/mips/vr4181/osprey
+LIBS		+= arch/mips/vr4181/common/vr4181.o \
+		   arch/mips/vr4181/osprey/osprey.o
+LOADADDR	:= 0x80002000
 endif
 
 #
-# Galileo EV96100 Board
+# Philips Nino
 #
-ifdef CONFIG_MIPS_EV96100
-LIBS          += arch/mips/galileo-boards/ev96100/ev96100.o arch/mips/galileo-boards/generic/galboards.o
-SUBDIRS       += arch/mips/galileo-boards/generic arch/mips/galileo-boards/ev96100
-LOADADDR      += 0x80100000
+ifdef CONFIG_NINO
+CORE_FILES	+= arch/mips/philips/nino/nino.o
+SUBDIRS		+= arch/mips/philips/nino
+LOADADDR	:= 0x80000000
 endif
 
 #
-# Momentum Ocelot board
+# SGI IP22 (Indy/Indigo2)
 #
-ifdef CONFIG_MOMENCO_OCELOT
-# The Ocelot setup.o must be linked early - it does the ioremap() for the
-# mips_io_port_base.
-CORE_FILES    += arch/mips/gt64120/common/gt64120.o arch/mips/gt64120/momenco_ocelot/momenco_ocelot.o
-SUBDIRS       += arch/mips/gt64120/common arch/mips/gt64120/momenco_ocelot
-LOADADDR      += 0x80100000
+ifdef CONFIG_SGI_IP22
+CORE_FILES	+= arch/mips/sgi-ip22/ip22-kern.o
+LIBS		+= arch/mips/arc/arclib.a
+SUBDIRS		+= arch/mips/sgi-ip22 arch/mips/arc
+#
+# Set LOADADDR to >= 0x88069000 if you want to leave space for symmon,
+# 0x88002000 for production kernels.  Note that the value must be
+# 8kb aligned or the handling of the current variable will break.
+#
+LOADADDR	:= 0x88002000
 endif
 
 #
-# Philips Nino
+# Sibyte SB1250 SOC
 #
-ifdef CONFIG_NINO
-CORE_FILES    += arch/mips/philips/nino/nino.o
-SUBDIRS       += arch/mips/philips/nino
-LOADADDR      += 0x80000000
+ifdef CONFIG_SIBYTE_SB1250
+# This is a LIB so that it links at the end, and initcalls are later
+# the sequence; but it is built as an object so that modules don't get
+# removed (as happens, even if they have __initcall/module_init)
+LIBS		+= arch/mips/sibyte/sb1250/sb1250.o
+SUBDIRS		+= arch/mips/sibyte/sb1250
 endif
 
 #
-# ITE 8172 eval board with QED 5231 CPU
+# Sibyte SWARM board
 #
-ifdef CONFIG_MIPS_ITE8172
-LIBS          += arch/mips/ite-boards/qed-4n-s01b/ite.o arch/mips/ite-boards/generic/it8172.o
-SUBDIRS       += arch/mips/ite-boards/generic arch/mips/ite-boards/qed-4n-s01b
-LOADADDR      += 0x80100000
+ifdef CONFIG_SIBYTE_SWARM
+LIBS		+= arch/mips/sibyte/swarm/sbswarm.a
+SUBDIRS		+= arch/mips/sibyte/swarm
+LOADADDR	:= 0x80100000
 endif
 
 #
-# Globespan IVR eval board with QED 5231 CPU
+# SB1 Cache Error handler
 #
-ifdef CONFIG_MIPS_IVR
-LIBS          += arch/mips/ite-boards/ivr/ivr.o arch/mips/ite-boards/generic/it8172.o
-SUBDIRS       += arch/mips/ite-boards/generic arch/mips/ite-boards/ivr
-LOADADDR      += 0x80100000
+ifdef CONFIG_SB1_CACHE_ERROR
+LIBS		+= arch/mips/sibyte/sb1/sb1kern.a
+SUBDIRS		+= arch/mips/sibyte/sb1
 endif
 
 #
-# Au1000 eval board
+# SNI RM200 PCI
 #
-ifdef CONFIG_MIPS_PB1000
-LIBS          += arch/mips/au1000/pb1000/pb1000.o arch/mips/au1000/common/au1000.o
-SUBDIRS       += arch/mips/au1000/pb1000 arch/mips/au1000/common
-LOADADDR      += 0x80100000
+ifdef CONFIG_SNI_RM200_PCI
+CORE_FILES	+= arch/mips/sni/sni.o
+SUBDIRS		+= arch/mips/sni arch/mips/arc
+LIBS		+= arch/mips/arc/arclib.a
+LOADADDR	:= 0x80080000
+endif
+
+#
+# Toshiba JMR-TX3927 board
+#
+ifdef CONFIG_TOSHIBA_JMR3927
+CORE_FILES	+= arch/mips/jmr3927/rbhma3100/jmr3927.o \
+		   arch/mips/jmr3927/common/tx3927.o
+SUBDIRS		+= arch/mips/jmr3927/rbhma3100 arch/mips/jmr3927/common
+LOADADDR	:= 0x80050000
 endif
 
+
 #
 # Choosing incompatible machines durings configuration will result in
 # error messages during linking.  Select a default linkscript if
@@ -282,7 +401,7 @@
 
 BAGETBOOT = $(MAKE) -C arch/$(ARCH)/baget
 
-balo:  vmlinux
+balo: vmlinux
 	$(BAGETBOOT) balo
 
 endif
@@ -291,7 +410,7 @@
 GALILEOBOOT = $(MAKE) -C arch/$(ARCH)/galileo-boards/ev64120
 
 gboot: vmlinux
-	$(MAKE) -C arch/$(ARCH)/galileo-boards/ev64120/compressed 
+	$(MAKE) -C arch/$(ARCH)/galileo-boards/ev64120/compressed
 endif
 
 MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot
@@ -311,6 +430,6 @@
 
 archdep:
 	if [ ! -f $(TOPDIR)/include/asm-$(ARCH)/offset.h ]; then \
-	 touch $(TOPDIR)/include/asm-$(ARCH)/offset.h; \
+		touch $(TOPDIR)/include/asm-$(ARCH)/offset.h; \
 	fi;
 	@$(MAKEBOOT) dep
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/cmdline.c linux/arch/mips/arc/cmdline.c
--- linux.orig/arch/mips/arc/cmdline.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/arc/cmdline.c	2002-08-01 06:42:48.000000000 +0000
@@ -12,7 +12,7 @@
 
 #undef DEBUG_CMDLINE
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
 
 char * __init prom_getcmdline(void)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/console.c linux/arch/mips/arc/console.c
--- linux.orig/arch/mips/arc/console.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/arc/console.c	2002-08-01 06:42:43.000000000 +0000
@@ -6,7 +6,6 @@
  * Copyright (C) 1996 David S. Miller (dm@sgi.com)
  * Compability with board caches, Ulf Carlsson
  */
-#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <asm/sgialib.h>
@@ -31,7 +30,7 @@
 	char it = c;
 
 	bc_disable();
-	romvec->write(1, &it, 1, &cnt);
+	ArcWrite(1, &it, 1, &cnt);
 	bc_enable();
 }
 
@@ -41,7 +40,7 @@
 	char c;
 
 	bc_disable();
-	romvec->read(0, &c, 1, &cnt);
+	ArcRead(0, &c, 1, &cnt);
 	bc_enable();
 
 	return c;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/env.c linux/arch/mips/arc/env.c
--- linux.orig/arch/mips/arc/env.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/arc/env.c	2002-08-01 06:42:33.000000000 +0000
@@ -1,24 +1,27 @@
 /*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
  * env.c: ARCS environment variable routines.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- * $Id: env.c,v 1.2 1999/10/09 00:00:57 ralf Exp $
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 
+#include <asm/arc/types.h>
 #include <asm/sgialib.h>
 
 PCHAR __init
 ArcGetEnvironmentVariable(CHAR *name)
 {
-	return romvec->get_evar(name);
+	return (CHAR *) ARC_CALL1(get_evar, name);
 }
 
 LONG __init
 ArcSetEnvironmentVariable(PCHAR name, PCHAR value)
 {
-	return romvec->set_evar(name, value);
+	return ARC_CALL2(set_evar, name, value);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/file.c linux/arch/mips/arc/file.c
--- linux.orig/arch/mips/arc/file.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/arc/file.c	2002-08-01 06:42:33.000000000 +0000
@@ -1,59 +1,75 @@
 /*
- * file.c: ARCS firmware interface to files.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * ARC firmware interface.
  *
- * $Id: file.c,v 1.1 1998/10/18 13:32:08 tsbogend Exp $
+ * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
  */
 #include <linux/init.h>
+
+#include <asm/arc/types.h>
 #include <asm/sgialib.h>
 
-long __init prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt)
+LONG __init
+ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer,
+                     ULONG N, ULONG *Count)
 {
-	return romvec->get_vdirent(fd, ent, num, cnt);
+	return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count);
 }
 
-long __init prom_open(char *name, enum linux_omode md, unsigned long *fd)
+LONG __init
+ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID)
 {
-	return romvec->open(name, md, fd);
+	return ARC_CALL3(open, Path, OpenMode, FileID);
 }
 
-long __init prom_close(unsigned long fd)
+LONG __init
+ArcClose(ULONG FileID)
 {
-	return romvec->close(fd);
+	return ARC_CALL1(close, FileID);
 }
 
-long __init prom_read(unsigned long fd, void *buf, unsigned long num, unsigned long *cnt)
+LONG __init
+ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count)
 {
-	return romvec->read(fd, buf, num, cnt);
+	return ARC_CALL4(read, FileID, Buffer, N, Count);
 }
 
-long __init prom_getrstatus(unsigned long fd)
+LONG __init
+ArcGetReadStatus(ULONG FileID)
 {
-	return romvec->get_rstatus(fd);
+	return ARC_CALL1(get_rstatus, FileID);
 }
 
-long __init prom_write(unsigned long fd, void *buf, unsigned long num, unsigned long *cnt)
+LONG __init
+ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count)
 {
-	return romvec->write(fd, buf, num, cnt);
+	return ARC_CALL4(write, FileID, Buffer, N, Count);
 }
 
-long __init prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm)
+LONG __init
+ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode)
 {
-	return romvec->seek(fd, off, sm);
+	return ARC_CALL3(seek, FileID, Position, SeekMode);
 }
 
-long __init prom_mount(char *name, enum linux_mountops op)
+LONG __init
+ArcMount(char *name, enum linux_mountops op)
 {
-	return romvec->mount(name, op);
+	return ARC_CALL2(mount, name, op);
 }
 
-long __init prom_getfinfo(unsigned long fd, struct linux_finfo *buf)
+LONG __init
+ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information)
 {
-	return romvec->get_finfo(fd, buf);
+	return ARC_CALL2(get_finfo, FileID, Information);
 }
 
-long __init prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk)
+LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,
+                                  ULONG AttributeMask)
 {
-	return romvec->set_finfo(fd, flags, msk);
+	return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/identify.c linux/arch/mips/arc/identify.c
--- linux.orig/arch/mips/arc/identify.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/arc/identify.c	2002-08-01 06:42:35.000000000 +0000
@@ -7,6 +7,7 @@
  * 
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  */
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
@@ -17,49 +18,81 @@
 #include <asm/bootinfo.h>
 
 struct smatch {
-	char *name;
+	char *arcname;
+	char *liname;
 	int group;
 	int type;
 	int flags;
 };
 
 static struct smatch mach_table[] = {
-	{"SGI-IP22", MACH_GROUP_SGI, MACH_SGI_INDY, PROM_FLAG_ARCS},
-	{"Microsoft-Jazz", MACH_GROUP_JAZZ, MACH_MIPS_MAGNUM_4000, 0},
-	{"PICA-61", MACH_GROUP_JAZZ, MACH_ACER_PICA_61, 0},
-	{"RM200PCI", MACH_GROUP_SNI_RM, MACH_SNI_RM200_PCI, 0}
+	{	"SGI-IP22",
+		"SGI Indy",
+		MACH_GROUP_SGI,
+		MACH_SGI_INDY,
+		PROM_FLAG_ARCS
+	}, {	"Microsoft-Jazz",
+		"Jazz MIPS_Magnum_4000",
+		MACH_GROUP_JAZZ,
+		MACH_MIPS_MAGNUM_4000,
+		0
+	}, {	"PICA-61",
+		"Jazz Acer_PICA_61",
+		MACH_GROUP_JAZZ,
+		MACH_ACER_PICA_61,
+		0
+	}, {	"RM200PCI",
+		"SNI RM200_PCI",
+		MACH_GROUP_SNI_RM,
+		MACH_SNI_RM200_PCI,
+		0
+	}
 };
 
 int prom_flags;
 
-static struct smatch *__init string_to_mach(char *s)
+static struct smatch *__init string_to_mach(const char *s)
 {
 	int i;
 
 	for (i = 0; i < (sizeof(mach_table) / sizeof (mach_table[0])); i++) {
-		if (!strcmp(s, mach_table[i].name))
+		if (!strcmp(s, mach_table[i].arcname))
 			return &mach_table[i];
 	}
-	prom_printf("\nYeee, could not determine architecture type <%s>\n",
-		    s);
-	prom_printf("press a key to reboot\n");
-	prom_getchar();
-	romvec->imode();
-	return NULL;
+
+	panic("Yeee, could not determine architecture type <%s>", s);
+}
+
+char *system_type;
+
+const char *get_system_type(void)
+{
+	return system_type;
 }
 
 void __init prom_identify_arch(void)
 {
 	pcomponent *p;
 	struct smatch *mach;
+	const char *iname;
 
 	/*
 	 * The root component tells us what machine architecture we
 	 * have here.
 	 */
-	p = prom_getchild(PROM_NULL_COMPONENT);
-	printk("ARCH: %s\n", p->iname);
-	mach = string_to_mach(p->iname);
+	p = ArcGetChild(PROM_NULL_COMPONENT);
+	if (p == NULL) {
+#ifdef CONFIG_SGI_IP27
+	/* IP27 PROM bisbehaves, seems to not implement ARC
+	   GetChild().  So we just assume it's an IP27.  */
+		iname = "SGI-IP27";
+#endif
+	} else
+		iname = (char *) (long) p->iname;
+
+	printk(KERN_INFO "ARCH: %s\n", iname);
+	mach = string_to_mach(iname);
+	system_type = mach->liname;
 
 	mips_machgroup = mach->group;
 	mips_machtype = mach->type;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/init.c linux/arch/mips/arc/init.c
--- linux.orig/arch/mips/arc/init.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/arc/init.c	2002-08-01 06:42:42.000000000 +0000
@@ -16,38 +16,22 @@
 
 /* Master romvec interface. */
 struct linux_romvec *romvec;
-struct linux_promblock *sgi_pblock;
 int prom_argc;
 char **prom_argv, **prom_envp;
-unsigned short prom_vers, prom_rev;
 
 extern void prom_testtree(void);
 
-extern void arc_setup_console(void);
-
 void __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
 {
-	struct linux_promblock *pb;
+	PSYSTEM_PARAMETER_BLOCK pb;
+	unsigned short prom_vers, prom_rev;
 
 	romvec = ROMVECTOR;
-	pb = sgi_pblock = PROMBLOCK;
+	pb = PROMBLOCK;
 	prom_argc = argc;
 	prom_argv = argv;
 	prom_envp = envp;
 
-#if 0
-	/* arc_printf should not use prom_printf as soon as we free
-	 * the prom buffers - This horribly breaks on Indys with framebuffer
-	 * as it simply stops after initialising swap - On the Indigo2 serial
-	 * console you will get A LOT illegal instructions - Only enable
-	 * this for early init crashes - This also brings up artefacts of
-	 * printing everything twice on serial console and on GFX Console
-	 * this has the effect of having the prom printing everything
-	 * in the small rectangle and the kernel printing around.
-	 */
-
-	arc_setup_console();
-#endif
 	if (pb->magic != 0x53435241) {
 		prom_printf("Aieee, bad prom vector magic %08lx\n", pb->magic);
 		while(1)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/memory.c linux/arch/mips/arc/memory.c
--- linux.orig/arch/mips/arc/memory.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/arc/memory.c	2002-08-01 06:42:32.000000000 +0000
@@ -22,7 +22,7 @@
 struct linux_mdesc * __init
 ArcGetMemoryDescriptor(struct linux_mdesc *Current)
 {
-	return romvec->get_mdesc(Current);
+	return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current);
 }
 
 #ifdef DEBUG /* convenient for debugging */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/misc.c linux/arch/mips/arc/misc.c
--- linux.orig/arch/mips/arc/misc.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/arc/misc.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,13 +1,21 @@
 /*
- * misc.c: Miscellaneous ARCS PROM routines.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Miscellaneous ARCS PROM routines.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999 Silicon Graphics, Inc.
  */
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 
 #include <asm/bcache.h>
+
+#include <asm/arc/types.h>
 #include <asm/sgialib.h>
 #include <asm/bootinfo.h>
 #include <asm/system.h>
@@ -15,68 +23,81 @@
 extern void *sgiwd93_host;
 extern void reset_wd33c93(void *instance);
 
-void prom_halt(void)
+VOID
+ArcHalt(VOID)
 {
 	bc_disable();
 	cli();
 #if CONFIG_SCSI_SGIWD93
 	reset_wd33c93(sgiwd93_host);
 #endif
-	romvec->halt();
+	ARC_CALL0(halt);
+never:	goto never;
 }
 
-void prom_powerdown(void)
+VOID
+ArcPowerDown(VOID)
 {
 	bc_disable();
 	cli();
 #if CONFIG_SCSI_SGIWD93
 	reset_wd33c93(sgiwd93_host);
 #endif
-	romvec->pdown();
+	ARC_CALL0(pdown);
+never:	goto never;
 }
 
 /* XXX is this a soft reset basically? XXX */
-void prom_restart(void)
+VOID
+ArcRestart(VOID)
 {
 	bc_disable();
 	cli();
 #if CONFIG_SCSI_SGIWD93
 	reset_wd33c93(sgiwd93_host);
 #endif
-	romvec->restart();
+	ARC_CALL0(restart);
+never:	goto never;
 }
 
-void prom_reboot(void)
+VOID
+ArcReboot(VOID)
 {
 	bc_disable();
 	cli();
 #if CONFIG_SCSI_SGIWD93
 	reset_wd33c93(sgiwd93_host);
 #endif
-	romvec->reboot();
+	ARC_CALL0(reboot);
+never:	goto never;
 }
 
-void ArcEnterInteractiveMode(void)
+VOID
+ArcEnterInteractiveMode(VOID)
 {
 	bc_disable();
 	cli();
 #if CONFIG_SCSI_SGIWD93
 	reset_wd33c93(sgiwd93_host);
 #endif
-	romvec->imode();
+	ARC_CALL0(imode);
+never:	goto never;
 }
 
-long prom_cfgsave(void)
+LONG
+ArcSaveConfiguration(VOID)
 {
-	return romvec->cfg_save();
+	return ARC_CALL0(cfg_save);
 }
 
-struct linux_sysid *prom_getsysid(void)
+struct linux_sysid *
+ArcGetSystemId(VOID)
 {
-	return romvec->get_sysid();
+	return (struct linux_sysid *) ARC_CALL0(get_sysid);
 }
 
-void __init prom_cacheflush(void)
+VOID __init
+ArcFlushAllCaches(VOID)
 {
-	romvec->cache_flush();
+	ARC_CALL0(cache_flush);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/salone.c linux/arch/mips/arc/salone.c
--- linux.orig/arch/mips/arc/salone.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/arc/salone.c	2002-08-01 06:42:48.000000000 +0000
@@ -3,8 +3,6 @@
  *           program images using ARCS PROM firmware.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- * $Id: salone.c,v 1.1 1998/10/18 13:32:09 tsbogend Exp $
  */
 #include <linux/init.h>
 #include <asm/sgialib.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/time.c linux/arch/mips/arc/time.c
--- linux.orig/arch/mips/arc/time.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/arc/time.c	2002-08-01 06:42:42.000000000 +0000
@@ -1,19 +1,25 @@
 /*
- * time.c: Extracting time information from ARCS prom.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Extracting time information from ARCS prom.
  *
- * $Id: time.c,v 1.1 1998/10/18 13:32:10 tsbogend Exp $
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  */
 #include <linux/init.h>
+
+#include <asm/arc/types.h>
 #include <asm/sgialib.h>
 
-struct linux_tinfo * __init prom_gettinfo(void)
+struct linux_tinfo * __init
+ArcGetTime(VOID)
 {
-	return romvec->get_tinfo();
+	return (struct linux_tinfo *) ARC_CALL0(get_tinfo);
 }
 
-unsigned long __init prom_getrtime(void)
+ULONG __init
+ArcGetRelativeTime(VOID)
 {
-	return romvec->get_rtime();
+	return ARC_CALL0(get_rtime);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/arc/tree.c linux/arch/mips/arc/tree.c
--- linux.orig/arch/mips/arc/tree.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/arc/tree.c	2002-08-01 06:42:28.000000000 +0000
@@ -1,72 +1,88 @@
 /*
- * tree.c: PROM component device tree code.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * PROM component device tree code.
  *
- * $Id: tree.c,v 1.1 1998/10/18 13:32:10 tsbogend Exp $
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999 Silicon Graphics, Inc.
  */
 #include <linux/init.h>
+#include <asm/arc/types.h>
 #include <asm/sgialib.h>
 
-#define DEBUG_PROM_TREE
+#undef DEBUG_PROM_TREE
 
-pcomponent * __init prom_getsibling(pcomponent *this)
+pcomponent * __init
+ArcGetPeer(pcomponent *Current)
 {
-	if(this == PROM_NULL_COMPONENT)
+	if (Current == PROM_NULL_COMPONENT)
 		return PROM_NULL_COMPONENT;
-	return romvec->next_component(this);
+
+	return (pcomponent *) ARC_CALL1(next_component, Current);
 }
 
-pcomponent * __init prom_getchild(pcomponent *this)
+pcomponent * __init
+ArcGetChild(pcomponent *Current)
 {
-	return romvec->child_component(this);
+	return (pcomponent *) ARC_CALL1(child_component, Current);
 }
 
-pcomponent * __init prom_getparent(pcomponent *child)
+pcomponent * __init
+ArcGetParent(pcomponent *Current)
 {
-	if(child == PROM_NULL_COMPONENT)
+	if (Current == PROM_NULL_COMPONENT)
 		return PROM_NULL_COMPONENT;
-	return romvec->parent_component(child);
+
+	return (pcomponent *) ARC_CALL1(parent_component, Current);
 }
 
-long __init prom_getcdata(void *buffer, pcomponent *this)
+LONG __init
+ArcGetConfigurationData(VOID *Buffer, pcomponent *Current)
 {
-	return romvec->component_data(buffer, this);
+	return ARC_CALL2(component_data, Buffer, Current);
 }
 
-pcomponent * __init prom_childadd(pcomponent *this, pcomponent *tmp, void *data)
+pcomponent * __init
+ArcAddChild(pcomponent *Current, pcomponent *Template, VOID *ConfigurationData)
 {
-	return romvec->child_add(this, tmp, data);
+	return (pcomponent *)
+	       ARC_CALL3(child_add, Current, Template, ConfigurationData);
 }
 
-long __init prom_delcomponent(pcomponent *this)
+LONG __init
+ArcDeleteComponent(pcomponent *ComponentToDelete)
 {
-	return romvec->comp_del(this);
+	return ARC_CALL1(comp_del, ComponentToDelete);
 }
 
-pcomponent * __init prom_componentbypath(char *path)
+pcomponent * __init
+ArcGetComponent(CHAR *Path)
 {
-	return romvec->component_by_path(path);
+	return (pcomponent *)ARC_CALL1(component_by_path, Path);
 }
 
 #ifdef DEBUG_PROM_TREE
+
 static char *classes[] = {
 	"system", "processor", "cache", "adapter", "controller", "peripheral",
 	"memory"
 };
 
 static char *types[] = {
-	"arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache", "sccache",
-	"memdev", "eisa adapter", "tc adapter", "scsi adapter", "dti adapter",
-	"multi-func adapter", "disk controller", "tp controller",
-	"cdrom controller", "worm controller", "serial controller",
-	"net controller", "display controller", "parallel controller",
-	"pointer controller", "keyboard controller", "audio controller",
-	"misc controller", "disk peripheral", "floppy peripheral",
-	"tp peripheral", "modem peripheral", "monitor peripheral",
-	"printer peripheral", "pointer peripheral", "keyboard peripheral",
-	"terminal peripheral", "line peripheral", "net peripheral",
-	"misc peripheral", "anonymous"
+	"arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache",
+	"sccache", "memdev", "eisa adapter", "tc adapter", "scsi adapter",
+	"dti adapter", "multi-func adapter", "disk controller",
+	"tp controller", "cdrom controller", "worm controller",
+	"serial controller", "net controller", "display controller",
+	"parallel controller", "pointer controller", "keyboard controller",
+	"audio controller", "misc controller", "disk peripheral",
+	"floppy peripheral", "tp peripheral", "modem peripheral",
+	"monitor peripheral", "printer peripheral", "pointer peripheral",
+	"keyboard peripheral", "terminal peripheral", "line peripheral",
+	"net peripheral", "misc peripheral", "anonymous"
 };
 
 static char *iflags[] = {
@@ -74,7 +90,8 @@
 	"input", "output"
 };
 
-static void __init dump_component(pcomponent *p)
+static void __init
+dump_component(pcomponent *p)
 {
 	prom_printf("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>",
 		    p, classes[p->class], types[p->type],
@@ -83,27 +100,28 @@
 		    p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname);
 }
 
-static void __init traverse(pcomponent *p, int op)
+static void __init
+traverse(pcomponent *p, int op)
 {
 	dump_component(p);
-	if(prom_getchild(p))
-		traverse(prom_getchild(p), 1);
-	if(prom_getsibling(p) && op)
-		traverse(prom_getsibling(p), 1);
+	if(ArcGetChild(p))
+		traverse(ArcGetChild(p), 1);
+	if(ArcGetPeer(p) && op)
+		traverse(ArcGetPeer(p), 1);
 }
 
-void __init prom_testtree(void)
+void __init
+prom_testtree(void)
 {
 	pcomponent *p;
 
-	p = prom_getchild(PROM_NULL_COMPONENT);
+	p = ArcGetChild(PROM_NULL_COMPONENT);
 	dump_component(p);
-	p = prom_getchild(p);
+	p = ArcGetChild(p);
 	while(p) {
 		dump_component(p);
-		p = prom_getsibling(p);
+		p = ArcGetPeer(p);
 	}
-	prom_printf("press a key\n");
-	prom_getchar();
 }
-#endif
+
+#endif /* DEBUG_PROM_TREE  */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/Makefile linux/arch/mips/au1000/common/Makefile
--- linux.orig/arch/mips/au1000/common/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/Makefile	2002-08-01 06:42:48.000000000 +0000
@@ -19,13 +19,13 @@
 
 O_TARGET := au1000.o
 
-obj-y := prom.o dbg_io.o int-handler.o irq.o puts.o time.o reset.o
+export-objs		= prom.o serial.o clocks.o
+
+obj-y := prom.o int-handler.o dma.o irq.o puts.o time.o reset.o power.o clocks.o
 
 obj-$(CONFIG_AU1000_UART) += serial.o             
+obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
 obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o             
-obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
-
-ramdisk.o: 
-	mkramobj ramdisk ramdisk.o
+obj-$(CONFIG_RTC) += rtc.o
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/clocks.c linux/arch/mips/au1000/common/clocks.c
--- linux.orig/arch/mips/au1000/common/clocks.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/common/clocks.c	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,98 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Simple Au1000 clocks routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *		ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <asm/au1000.h>
+
+static unsigned int au1000_clock; // Hz
+static unsigned int lcd_clock;    // KHz
+static unsigned long uart_baud_base;
+
+/*
+ * Set the au1000_clock
+ */
+void set_au1000_speed(unsigned int new_freq)
+{
+	au1000_clock = new_freq;
+}
+
+unsigned int get_au1000_speed(void)
+{
+	return au1000_clock;
+}
+
+
+
+/*
+ * The UART baud base is not known at compile time ... if
+ * we want to be able to use the same code on different
+ * speed CPUs.
+ */
+unsigned long get_au1000_uart_baud_base(void)
+{
+	return uart_baud_base;
+}
+
+void set_au1000_uart_baud_base(unsigned long new_baud_base)
+{
+	uart_baud_base = new_baud_base;
+}
+
+/*
+ * Calculate the Au1000's LCD clock based on the current
+ * cpu clock and the system bus clock, and try to keep it
+ * below 40 MHz (the Pb1000 board can lock-up if the LCD
+ * clock is over 40 MHz).
+ */
+void set_au1000_lcd_clock(void)
+{
+	unsigned int static_cfg0;
+	unsigned int sys_busclk =
+		(get_au1000_speed()/1000) /
+		((int)(inl(SYS_POWERCTRL)&0x03) + 2);
+
+	static_cfg0 = inl(MEM_STCFG0);
+
+	if (static_cfg0 & (1<<11))
+		lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
+	else
+		lcd_clock = sys_busclk / 4;
+
+	if (lcd_clock > 50000) /* Epson MAX */
+			printk(__FUNCTION__
+			       ": warning: LCD clock too high (%d KHz)\n",
+			       lcd_clock);
+}
+
+unsigned int get_au1000_lcd_clock(void)
+{
+	return lcd_clock;
+}
+
+EXPORT_SYMBOL(get_au1000_lcd_clock);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/dbg_io.c linux/arch/mips/au1000/common/dbg_io.c
--- linux.orig/arch/mips/au1000/common/dbg_io.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/dbg_io.c	2002-08-01 06:42:41.000000000 +0000
@@ -53,8 +53,11 @@
 #define UART_MOD_CNTRL	0x100	/* Module Control */
 
 /* memory-mapped read/write of the port */
-#define UART16550_READ(y)    (inl(DEBUG_BASE + y) & 0xff)
-#define UART16550_WRITE(y,z) (outl(z&0xff, DEBUG_BASE + y))
+#define UART16550_READ(y)    (readl(DEBUG_BASE + y) & 0xff)
+#define UART16550_WRITE(y,z) (writel(z&0xff, DEBUG_BASE + y))
+
+extern unsigned long get_au1000_uart_baud_base(void);
+extern unsigned long cal_r4koff(void);
 
 void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 {
@@ -72,12 +75,12 @@
 		uint32 divisor;
 
 		/* set divisor */
-		divisor = get_au1000_uart_baud() / baud;
+		divisor = get_au1000_uart_baud_base() / baud;
 		UART16550_WRITE(UART_CLK, divisor & 0xffff);
 	}
 
 	/* set data format */
-	UART16550_WRITE(UART_LCR, data | parity | stop);
+	UART16550_WRITE(UART_LCR, (data | parity | stop));
 }
 
 static int remoteDebugInitialized = 0;
@@ -99,7 +102,8 @@
 
 int putDebugChar(uint8 byte)
 {
-	int i;
+//	int i;
+
 	if (!remoteDebugInitialized) {
 		remoteDebugInitialized = 1;
 		debugInit(UART16550_BAUD_115200,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/dma.c linux/arch/mips/au1000/common/dma.c
--- linux.orig/arch/mips/au1000/common/dma.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/common/dma.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,195 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      A DMA channel allocator for Au1000. API is modeled loosely off of
+ *      linux/kernel/dma.c.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	stevel@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <asm/au1000.h>
+#include <asm/au1000_dma.h>
+#include <asm/system.h>
+
+
+
+/*
+ * A note on resource allocation:
+ *
+ * All drivers needing DMA channels, should allocate and release them
+ * through the public routines `request_dma()' and `free_dma()'.
+ *
+ * In order to avoid problems, all processes should allocate resources in
+ * the same sequence and release them in the reverse order.
+ *
+ * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
+ * When releasing them, first release the IRQ, then release the DMA. The
+ * main reason for this order is that, if you are requesting the DMA buffer
+ * done interrupt, you won't know the irq number until the DMA channel is
+ * returned from request_dma.
+ */
+
+
+spinlock_t au1000_dma_spin_lock = SPIN_LOCK_UNLOCKED;
+
+struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
+      {dev_id:-1,},
+      {dev_id:-1,},
+      {dev_id:-1,},
+      {dev_id:-1,},
+      {dev_id:-1,},
+      {dev_id:-1,},
+      {dev_id:-1,},
+      {dev_id:-1,}
+};
+
+// Device FIFO addresses and default DMA modes
+static const struct {
+	unsigned int fifo_addr;
+	unsigned int dma_mode;
+} dma_dev_table[DMA_NUM_DEV] = {
+	{
+	UART0_ADDR + UART_TX, 0}, {
+	UART0_ADDR + UART_RX, 0}, {
+	0, 0}, {
+	0, 0}, {
+	AC97C_DATA, DMA_DW16 | DMA_NC}, {
+	AC97C_DATA, DMA_DR | DMA_DW16 | DMA_NC}, {
+	UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, {
+	UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, {
+	USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, {
+	USBD_EP0WR, DMA_DW8 | DMA_NC}, {
+	USBD_EP2WR, DMA_DW8 | DMA_NC}, {
+	USBD_EP3WR, DMA_DW8 | DMA_NC}, {
+	USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC}, {
+	USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC}, {
+	I2S_DATA, DMA_DW32 | DMA_NC}, {
+	I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC}
+};
+
+
+int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
+			 int length, int *eof, void *data)
+{
+	int i, len = 0;
+	struct dma_chan *chan;
+
+	for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
+		if ((chan = get_dma_chan(i)) != NULL) {
+			len +=
+			    sprintf(buf + len, "%2d: %s\n", i,
+				    chan->dev_str);
+		}
+	}
+
+	if (fpos >= len) {
+		*start = buf;
+		*eof = 1;
+		return 0;
+	}
+	*start = buf + fpos;
+	if ((len -= fpos) > length)
+		return length;
+	*eof = 1;
+	return len;
+}
+
+
+void dump_au1000_dma_channel(unsigned int dmanr)
+{
+	struct dma_chan *chan;
+
+	if (dmanr > NUM_AU1000_DMA_CHANNELS)
+		return;
+	chan = &au1000_dma_table[dmanr];
+
+	printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
+	printk(KERN_INFO "  mode = 0x%08x\n",
+	       inl(chan->io + DMA_MODE_SET));
+	printk(KERN_INFO "  addr = 0x%08x\n",
+	       inl(chan->io + DMA_PERIPHERAL_ADDR));
+	printk(KERN_INFO "  start0 = 0x%08x\n",
+	       inl(chan->io + DMA_BUFFER0_START));
+	printk(KERN_INFO "  start1 = 0x%08x\n",
+	       inl(chan->io + DMA_BUFFER1_START));
+	printk(KERN_INFO "  count0 = 0x%08x\n",
+	       inl(chan->io + DMA_BUFFER0_COUNT));
+	printk(KERN_INFO "  count1 = 0x%08x\n",
+	       inl(chan->io + DMA_BUFFER1_COUNT));
+}
+
+
+/*
+ * Finds a free channel, and binds the requested device to it.
+ * Returns the allocated channel number, or negative on error.
+ */
+int request_au1000_dma(int dev_id, const char *dev_str)
+{
+	struct dma_chan *chan;
+	int i;
+
+	if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
+		return -EINVAL;
+
+	for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
+		if (au1000_dma_table[i].dev_id < 0)
+			break;
+	}
+	if (i == NUM_AU1000_DMA_CHANNELS)
+		return -ENODEV;
+
+	chan = &au1000_dma_table[i];
+
+	// fill it in
+	chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
+	chan->irq = AU1000_DMA_INT_BASE + i;
+	chan->dev_id = dev_id;
+	chan->dev_str = dev_str;
+	chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
+	chan->mode = dma_dev_table[dev_id].dma_mode;
+
+	return i;
+}
+
+
+void free_au1000_dma(unsigned int dmanr)
+{
+	struct dma_chan *chan = get_dma_chan(dmanr);
+	if (!chan) {
+		printk("Trying to free DMA%d\n", dmanr);
+		return;
+	}
+
+	disable_dma(dmanr);
+
+	chan->dev_id = -1;
+}				/* free_dma */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/int-handler.S linux/arch/mips/au1000/common/int-handler.S
--- linux.orig/arch/mips/au1000/common/int-handler.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/int-handler.S	2002-08-01 06:42:38.000000000 +0000
@@ -65,7 +65,5 @@
 
 5:	
 	move	a0, sp
-	jal	mips_spurious_interrupt
-done:
-	j	ret_from_irq
+	j	spurious_interrupt
 END(au1000_IRQ)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/irq.c linux/arch/mips/au1000/common/irq.c
--- linux.orig/arch/mips/au1000/common/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/irq.c	2002-08-01 06:42:40.000000000 +0000
@@ -47,7 +47,13 @@
 #include <asm/system.h>
 #include <asm/au1000.h>
 
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+#if defined(CONFIG_MIPS_PB1000)
+#include <asm/pb1000.h>
+#elif defined(CONFIG_MIPS_PB1500)
+#include <asm/pb1500.h>
+#else
+#error unsupported alchemy board
+#endif
 
 #undef DEBUG_IRQ
 #ifdef DEBUG_IRQ
@@ -68,11 +74,8 @@
 #endif
 
 extern asmlinkage void au1000_IRQ(void);
-
 extern void set_debug_traps(void);
-extern irq_cpustat_t irq_stat [];
-extern irq_desc_t irq_desc[NR_IRQS];
-
+extern irq_cpustat_t irq_stat [NR_CPUS];
 unsigned int local_bh_count[NR_CPUS];
 unsigned int local_irq_count[NR_CPUS];
 
@@ -82,147 +85,106 @@
 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
-static inline void local_enable_irq(unsigned int irq_nr);
-static inline void local_disable_irq(unsigned int irq_nr);
+inline void local_enable_irq(unsigned int irq_nr);
+inline void local_disable_irq(unsigned int irq_nr);
 
-unsigned long spurious_interrupts;
 extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
 extern void __init init_generic_irq(void);
 
-static inline void sync(void)
-{
-	__asm volatile ("sync");
-}
-
-
-/* Function for careful CP0 interrupt mask access */
-static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
-{
-	unsigned long status = read_32bit_cp0_register(CP0_STATUS);
-	status &= ~((clr_mask & 0xFF) << 8);
-	status |=   (set_mask & 0xFF) << 8;
-	write_32bit_cp0_register(CP0_STATUS, status);
-}
-
-
-static inline void mask_cpu_irq_input(unsigned int irq_nr)
-{
-	modify_cp0_intmask(irq_nr, 0);
-}
-
-
-static inline void unmask_cpu_irq_input(unsigned int irq_nr)
-{
-	modify_cp0_intmask(0, irq_nr);
-}
-
-
-static void disable_cpu_irq_input(unsigned int irq_nr)
-{
-	unsigned long flags;
-
-	save_and_cli(flags);
-	mask_cpu_irq_input(irq_nr);
-	restore_flags(flags);
-}
-
-
-static void enable_cpu_irq_input(unsigned int irq_nr)
-{
-	unsigned long flags;
-
-	save_and_cli(flags);
-	unmask_cpu_irq_input(irq_nr);
-	restore_flags(flags);
-}
+#ifdef CONFIG_PM
+extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
+#endif
 
 
 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
 {
+	if (irq_nr > AU1000_MAX_INTR) return;
 	/* Config2[n], Config1[n], Config0[n] */
 	if (irq_nr > AU1000_LAST_INTC0_INT) {
 		switch (type) {
 			case INTC_INT_RISE_EDGE: /* 0:0:1 */
-				outl(1<<irq_nr,INTC1_CONFIG2_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG0_SET);
+				outl(1<<(irq_nr-32), IC1_CFG2CLR);
+				outl(1<<(irq_nr-32), IC1_CFG1CLR);
+				outl(1<<(irq_nr-32), IC1_CFG0SET);
 				break;
 			case INTC_INT_FALL_EDGE: /* 0:1:0 */
-				outl(1<<irq_nr, INTC1_CONFIG2_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG1_SET);
-				outl(1<<irq_nr, INTC1_CONFIG0_CLEAR);
+				outl(1<<(irq_nr-32), IC1_CFG2CLR);
+				outl(1<<(irq_nr-32), IC1_CFG1SET);
+				outl(1<<(irq_nr-32), IC1_CFG0CLR);
 				break;
 			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
-				outl(1<<irq_nr, INTC1_CONFIG2_SET);
-				outl(1<<irq_nr, INTC1_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG0_SET);
+				outl(1<<(irq_nr-32), IC1_CFG2SET);
+				outl(1<<(irq_nr-32), IC1_CFG1CLR);
+				outl(1<<(irq_nr-32), IC1_CFG0SET);
 				break;
 			case INTC_INT_LOW_LEVEL: /* 1:1:0 */
-				outl(1<<irq_nr, INTC1_CONFIG2_SET);
-				outl(1<<irq_nr, INTC1_CONFIG1_SET);
-				outl(1<<irq_nr, INTC1_CONFIG0_CLEAR);
+				outl(1<<(irq_nr-32), IC1_CFG2SET);
+				outl(1<<(irq_nr-32), IC1_CFG1SET);
+				outl(1<<(irq_nr-32), IC1_CFG0CLR);
 				break;
 			case INTC_INT_DISABLED: /* 0:0:0 */
-				outl(1<<irq_nr, INTC1_CONFIG0_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG2_CLEAR);
+				outl(1<<(irq_nr-32), IC1_CFG0CLR);
+				outl(1<<(irq_nr-32), IC1_CFG1CLR);
+				outl(1<<(irq_nr-32), IC1_CFG2CLR);
 				break;
 			default: /* disable the interrupt */
 				printk("unexpected int type %d (irq %d)\n", type, irq_nr);
-				outl(1<<irq_nr, INTC1_CONFIG0_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC1_CONFIG2_CLEAR);
+				outl(1<<(irq_nr-32), IC1_CFG0CLR);
+				outl(1<<(irq_nr-32), IC1_CFG1CLR);
+				outl(1<<(irq_nr-32), IC1_CFG2CLR);
 				return;
 		}
 		if (int_req) /* assign to interrupt request 1 */
-			outl(1<<irq_nr, INTC1_ASSIGN_REQ_CLEAR);
+			outl(1<<(irq_nr-32), IC1_ASSIGNCLR);
 		else	     /* assign to interrupt request 0 */
-			outl(1<<irq_nr, INTC1_ASSIGN_REQ_SET);
-		outl(1<<irq_nr, INTC1_SOURCE_SET);
-		outl(1<<irq_nr, INTC1_MASK_CLEAR);
+			outl(1<<(irq_nr-32), IC1_ASSIGNSET);
+		outl(1<<(irq_nr-32), IC1_SRCSET);
+		outl(1<<(irq_nr-32), IC1_MASKCLR);
+		outl(1<<(irq_nr-32), IC1_WAKECLR);
 	}
 	else {
 		switch (type) {
 			case INTC_INT_RISE_EDGE: /* 0:0:1 */
-				outl(1<<irq_nr,INTC0_CONFIG2_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG0_SET);
+				outl(1<<irq_nr, IC0_CFG2CLR);
+				outl(1<<irq_nr, IC0_CFG1CLR);
+				outl(1<<irq_nr, IC0_CFG0SET);
 				break;
 			case INTC_INT_FALL_EDGE: /* 0:1:0 */
-				outl(1<<irq_nr, INTC0_CONFIG2_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG1_SET);
-				outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
+				outl(1<<irq_nr, IC0_CFG2CLR);
+				outl(1<<irq_nr, IC0_CFG1SET);
+				outl(1<<irq_nr, IC0_CFG0CLR);
 				break;
 			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
-				outl(1<<irq_nr, INTC0_CONFIG2_SET);
-				outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG0_SET);
+				outl(1<<irq_nr, IC0_CFG2SET);
+				outl(1<<irq_nr, IC0_CFG1CLR);
+				outl(1<<irq_nr, IC0_CFG0SET);
 				break;
 			case INTC_INT_LOW_LEVEL: /* 1:1:0 */
-				outl(1<<irq_nr, INTC0_CONFIG2_SET);
-				outl(1<<irq_nr, INTC0_CONFIG1_SET);
-				outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
+				outl(1<<irq_nr, IC0_CFG2SET);
+				outl(1<<irq_nr, IC0_CFG1SET);
+				outl(1<<irq_nr, IC0_CFG0CLR);
 				break;
 			case INTC_INT_DISABLED: /* 0:0:0 */
-				outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG2_CLEAR);
+				outl(1<<irq_nr, IC0_CFG0CLR);
+				outl(1<<irq_nr, IC0_CFG1CLR);
+				outl(1<<irq_nr, IC0_CFG2CLR);
 				break;
 			default: /* disable the interrupt */
 				printk("unexpected int type %d (irq %d)\n", type, irq_nr);
-				outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
-				outl(1<<irq_nr, INTC0_CONFIG2_CLEAR);
+				outl(1<<irq_nr, IC0_CFG0CLR);
+				outl(1<<irq_nr, IC0_CFG1CLR);
+				outl(1<<irq_nr, IC0_CFG2CLR);
 				return;
 		}
 		if (int_req) /* assign to interrupt request 1 */
-			outl(1<<irq_nr, INTC0_ASSIGN_REQ_CLEAR);
+			outl(1<<irq_nr, IC0_ASSIGNCLR);
 		else	     /* assign to interrupt request 0 */
-			outl(1<<irq_nr, INTC0_ASSIGN_REQ_SET);
-		outl(1<<irq_nr, INTC0_SOURCE_SET);
-		outl(1<<irq_nr, INTC0_MASK_CLEAR);
+			outl(1<<irq_nr, IC0_ASSIGNSET);
+		outl(1<<irq_nr, IC0_SRCSET);
+		outl(1<<irq_nr, IC0_MASKCLR);
+		outl(1<<irq_nr, IC0_WAKECLR);
 	}
-	sync();
+	au_sync();
 }
 
 
@@ -240,71 +202,136 @@
 }
 
 
-static inline void local_enable_irq(unsigned int irq_nr)
+inline void local_enable_irq(unsigned int irq_nr)
 {
 	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		outl(1<<irq_nr, INTC1_MASK_SET);
+		outl(1<<(irq_nr-32), IC1_MASKSET);
+		outl(1<<(irq_nr-32), IC1_WAKESET);
 	}
 	else {
-		outl(1<<irq_nr, INTC0_MASK_SET);
+		outl(1<<irq_nr, IC0_MASKSET);
+		outl(1<<irq_nr, IC0_WAKESET);
 	}
-	sync();
+	au_sync();
 }
 
 
-static inline void local_disable_irq(unsigned int irq_nr)
+inline void local_disable_irq(unsigned int irq_nr)
 {
 	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		outl(1<<irq_nr, INTC1_MASK_CLEAR);
+		outl(1<<(irq_nr-32), IC1_MASKCLR);
+		outl(1<<(irq_nr-32), IC1_WAKECLR);
 	}
 	else {
-		outl(1<<irq_nr, INTC0_MASK_CLEAR);
+		outl(1<<irq_nr, IC0_MASKCLR);
+		outl(1<<irq_nr, IC0_WAKECLR);
 	}
-	sync();
+	au_sync();
 }
 
 
 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
 {
 	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		outl(1<<irq_nr, INTC1_R_EDGE_DETECT_CLEAR);
-		outl(1<<irq_nr, INTC1_MASK_CLEAR);
+		outl(1<<(irq_nr-32), IC1_RISINGCLR);
+		outl(1<<(irq_nr-32), IC1_MASKCLR);
 	}
 	else {
-		outl(1<<irq_nr, INTC0_R_EDGE_DETECT_CLEAR);
-		outl(1<<irq_nr, INTC0_MASK_CLEAR);
+		outl(1<<irq_nr, IC0_RISINGCLR);
+		outl(1<<irq_nr, IC0_MASKCLR);
 	}
-	sync();
+	au_sync();
 }
 
 
 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
 {
 	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		outl(1<<irq_nr, INTC1_F_EDGE_DETECT_CLEAR);
-		outl(1<<irq_nr, INTC1_MASK_CLEAR);
+		outl(1<<(irq_nr-32), IC1_FALLINGCLR);
+		outl(1<<(irq_nr-32), IC1_MASKCLR);
 	}
 	else {
-		outl(1<<irq_nr, INTC0_F_EDGE_DETECT_CLEAR);
-		outl(1<<irq_nr, INTC0_MASK_CLEAR);
+		outl(1<<irq_nr, IC0_FALLINGCLR);
+		outl(1<<irq_nr, IC0_MASKCLR);
 	}
+	au_sync();
 }
 
 
 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
 {
+
 	local_disable_irq(irq_nr);
-	sync();
+	au_sync();
+#if defined(CONFIG_MIPS_PB1000)
+	if (irq_nr == AU1000_GPIO_15) {
+		writew(0x8000, PB1000_MDR); /* ack int */
+		au_sync();
+	}
+#endif
 	return;
 }
 
 
 static void end_irq(unsigned int irq_nr)
 {
-	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 		local_enable_irq(irq_nr);
+	}
+	else {
+		printk("warning: end_irq %d did not enable (%x)\n", 
+				irq_nr, irq_desc[irq_nr].status);
+	}
+#if defined(CONFIG_MIPS_PB1000)
+	if (irq_nr == AU1000_GPIO_15) {
+		writew(0x4000, PB1000_MDR); /* enable int */
+		au_sync();
+	}
+#endif
+}
+
+unsigned long save_local_and_disable(int controller)
+{
+	int i;
+	unsigned long flags, mask;
+	save_and_cli(flags);
+
+	if (controller) {
+		mask = readl(IC1_MASKSET);
+		for (i=32; i<64; i++) {
+			local_disable_irq(i);
+		}
+	}
+	else {
+		mask = readl(IC0_MASKSET);
+		for (i=0; i<32; i++) {
+			local_disable_irq(i);
+		}
+	}
+	restore_flags(flags);
+	return mask;
+}
+
+void restore_local_and_enable(int controller, unsigned long mask)
+{
+	int i;
+	unsigned long flags, new_mask;
+	save_and_cli(flags);
+
+	for (i=0; i<32; i++) {
+		if (mask & (1<<i)) {
+			if (controller)
+				local_enable_irq(i+32);
+			else
+				local_enable_irq(i);
+		}
+	}
+	if (controller)
+		new_mask = readl(IC1_MASKSET);
 	else
-		printk("warning: end_irq %d did not enable\n", irq_nr);
+		new_mask = readl(IC0_MASKSET);
+
+	restore_flags(flags);
 }
 
 
@@ -343,37 +370,104 @@
 	NULL
 };
 
-
-void enable_cpu_timer(void)
+#ifdef CONFIG_PM
+void startup_match20_interrupt(void)
 {
-	enable_cpu_irq_input(1<<MIPS_TIMER_IP); /* timer interrupt */
+	local_enable_irq(AU1000_TOY_MATCH2_INT);
 }
+#endif
 
 
 void __init init_IRQ(void)
 {
 	int i;
 	unsigned long cp0_status;
+	extern char except_vec0_au1000;
 
 	cp0_status = read_32bit_cp0_register(CP0_STATUS);
 	memset(irq_desc, 0, sizeof(irq_desc));
 	set_except_vector(0, au1000_IRQ);
 
 	init_generic_irq();
+
+	/* override the generic vec0 handler */
+	memcpy((void *)KSEG0, &except_vec0_au1000, 0x80);
+	flush_icache_range(KSEG0, KSEG0 + 0x200);
 	
-	/* 
-	 * Setup high priority interrupts on int_request0; low priority on
-	 * int_request1
-	 */
-	for (i = 0; i <= NR_IRQS; i++) {
+	for (i = 0; i <= AU1000_MAX_INTR; i++) {
 		switch (i) {
+			case AU1000_UART0_INT:
+			case AU1000_UART3_INT:
+#ifdef CONFIG_MIPS_PB1000
+			case AU1000_UART1_INT:
+			case AU1000_UART2_INT:
+
+			case AU1000_SSI0_INT:
+			case AU1000_SSI1_INT:
+#endif
+
+		        case AU1000_DMA_INT_BASE:
+		        case AU1000_DMA_INT_BASE+1:
+		        case AU1000_DMA_INT_BASE+2:
+		        case AU1000_DMA_INT_BASE+3:
+		        case AU1000_DMA_INT_BASE+4:
+		        case AU1000_DMA_INT_BASE+5:
+		        case AU1000_DMA_INT_BASE+6:
+		        case AU1000_DMA_INT_BASE+7:
+
+			case AU1000_IRDA_TX_INT:
+			case AU1000_IRDA_RX_INT:
+
 			case AU1000_MAC0_DMA_INT:
 			case AU1000_MAC1_DMA_INT:
+
+			case AU1500_GPIO_204:
 				setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
 				irq_desc[i].handler = &level_irq_type;
 				break;
+
+#ifdef CONFIG_MIPS_PB1000
+			case AU1000_GPIO_15:
+#endif
+		        case AU1000_USB_HOST_INT:
+#ifdef CONFIG_MIPS_PB1500
+			case AU1000_PCI_INTA:
+			case AU1000_PCI_INTB:
+			case AU1000_PCI_INTC:
+			case AU1000_PCI_INTD:
+			case AU1500_GPIO_201:
+			case AU1500_GPIO_202:
+			case AU1500_GPIO_203:
+			case AU1500_GPIO_205:
+			case AU1500_GPIO_207:
+#endif
+				setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
+				irq_desc[i].handler = &level_irq_type;
+                                break;
+			case AU1000_ACSYNC_INT:
+			case AU1000_AC97C_INT:
+		        case AU1000_USB_DEV_REQ_INT:
+		        case AU1000_USB_DEV_SUS_INT:
+			case AU1000_TOY_INT:
+			case AU1000_TOY_MATCH0_INT:
+			case AU1000_TOY_MATCH1_INT:
+			case AU1000_RTC_INT:
+			case AU1000_RTC_MATCH0_INT:
+			case AU1000_RTC_MATCH1_INT:
+			case AU1000_RTC_MATCH2_INT:
+			        setup_local_irq(i, INTC_INT_RISE_EDGE, 0);
+                                irq_desc[i].handler = &rise_edge_irq_type;
+                                break;
+
+				 // Careful if you change match 2 request!
+				 // The interrupt handler is called directly
+				 // from the low level dispatch code.
+			case AU1000_TOY_MATCH2_INT:
+				 setup_local_irq(i, INTC_INT_RISE_EDGE, 1);
+				 irq_desc[i].handler = &rise_edge_irq_type;
+				  break;
 			default: /* active high, level interrupt */
-				setup_local_irq(i, INTC_INT_HIGH_LEVEL, 1);
+				setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
 				irq_desc[i].handler = &level_irq_type;
 				break;
 		}
@@ -389,27 +483,28 @@
 }
 
 
-void mips_spurious_interrupt(struct pt_regs *regs)
-{
-	spurious_interrupts++;
-}
-
+/*
+ * Interrupts are nested. Even if an interrupt handler is registered
+ * as "fast", we might get another interrupt before we return from
+ * intcX_reqX_irqdispatch().
+ */
 
 void intc0_req0_irqdispatch(struct pt_regs *regs)
 {
 	int irq = 0, i;
-	unsigned long int_request;
+	static unsigned long intc0_req0 = 0;
 
-	int_request = inl(INTC0_REQ0_INT);
+	intc0_req0 |= inl(IC0_REQ0INT);
 
-	if (!int_request) return;
+	if (!intc0_req0) return;
 
 	for (i=0; i<32; i++) {
-		if ((int_request & 0x1)) {
+		if ((intc0_req0 & (1<<i))) {
+			intc0_req0 &= ~(1<<i);
 			do_IRQ(irq, regs);
+			break;
 		}
 		irq++;
-		int_request >>= 1;
 	}
 }
 
@@ -417,55 +512,86 @@
 void intc0_req1_irqdispatch(struct pt_regs *regs)
 {
 	int irq = 0, i;
-	unsigned long int_request;
+	static unsigned long intc0_req1 = 0;
 
-	int_request = inl(INTC0_REQ1_INT);
+	intc0_req1 = inl(IC0_REQ1INT);
 
-	if (!int_request) return;
+	if (!intc0_req1) return;
 
 	for (i=0; i<32; i++) {
-		if ((int_request & 0x1)) {
-			do_IRQ(irq, regs);
+		if ((intc0_req1 & (1<<i))) {
+			intc0_req1 &= ~(1<<i);
+#ifdef CONFIG_PM
+			if (i == AU1000_TOY_MATCH2_INT) {
+				mask_and_ack_rise_edge_irq(irq);
+				counter0_irq(irq, NULL, regs);
+				local_enable_irq(irq);
+			}
+			else 
+#endif
+			{
+				do_IRQ(irq, regs);
+			}
+			break;
 		}
 		irq++;
-		int_request >>= 1;
 	}
 }
 
 
+/*
+ * Interrupt Controller 1:
+ * interrupts 32 - 63
+ */
 void intc1_req0_irqdispatch(struct pt_regs *regs)
 {
 	int irq = 0, i;
-	unsigned long int_request;
+	static unsigned long intc1_req0 = 0;
+	volatile unsigned short levels, mdr;
+	unsigned char ide_status;
 
-	int_request = inl(INTC1_REQ0_INT);
+	intc1_req0 |= inl(IC1_REQ0INT);
 
-	if (!int_request) return;
+	if (!intc1_req0) return;
 
+#ifdef CONFIG_MIPS_PB1000
+	writew(1, CPLD_AUX0); /* debug led 0 */
+#endif
 	for (i=0; i<32; i++) {
-		if ((int_request & 0x1)) {
-			do_IRQ(irq, regs);
+		if ((intc1_req0 & (1<<i))) {
+			intc1_req0 &= ~(1<<i);
+#ifdef CONFIG_MIPS_PB1000
+			writew(2, CPLD_AUX0); /* turn on debug led 1  */
+			do_IRQ(irq+32, regs);
+			writew(0, CPLD_AUX0); /* turn off debug led 1 */
+#else
+			do_IRQ(irq+32, regs);
+#endif
+			break;
 		}
 		irq++;
-		int_request >>= 1;
 	}
+#ifdef CONFIG_MIPS_PB1000
+	writew(0, CPLD_AUX0);
+#endif
 }
 
 
 void intc1_req1_irqdispatch(struct pt_regs *regs)
 {
 	int irq = 0, i;
-	unsigned long int_request;
+	static unsigned long intc1_req1 = 0;
 
-	int_request = inl(INTC1_REQ1_INT);
+	intc1_req1 |= inl(IC1_REQ1INT);
 
-	if (!int_request) return;
+	if (!intc1_req1) return;
 
 	for (i=0; i<32; i++) {
-		if ((int_request & 0x1)) {
-			do_IRQ(irq, regs);
+		if ((intc1_req1 & (1<<i))) {
+			intc1_req1 &= ~(1<<i);
+			do_IRQ(irq+32, regs);
+			break;
 		}
 		irq++;
-		int_request >>= 1;
 	}
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/power.c linux/arch/mips/au1000/common/power.c
--- linux.orig/arch/mips/au1000/common/power.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/common/power.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,341 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Au1000 Power Management routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *		ppopov@mvista.com or source@mvista.com
+ *
+ *  Some of the routines are right out of init/main.c, whose
+ *  copyrights apply here.
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/sysctl.h>
+#include <linux/acpi.h>
+
+#include <asm/string.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/au1000.h>
+
+#define DEBUG 1
+#ifdef DEBUG
+#  define DPRINTK(fmt, args...)	printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#  define DPRINTK(fmt, args...)
+#endif
+
+inline void au1_wait(void);
+static void calibrate_delay(void);
+
+extern void set_au1000_speed(unsigned int new_freq);
+extern unsigned int get_au1000_speed(void);
+extern unsigned long get_au1000_uart_baud_base(void);
+extern void set_au1000_uart_baud_base(unsigned long new_baud_base);
+extern unsigned long save_local_and_disable(int controller);
+extern void restore_local_and_enable(int controller, unsigned long mask);
+extern void local_enable_irq(unsigned int irq_nr);
+
+/* Quick acpi hack. This will have to change! */
+#define	CTL_ACPI 9999
+#define	ACPI_S1_SLP_TYP 19
+#define	ACPI_SLEEP 21
+
+#ifdef CONFIG_PM
+
+unsigned long suspend_mode;
+
+void wakeup_from_suspend(void)
+{
+	suspend_mode = 0;
+}
+
+int au_sleep(void)
+{
+	unsigned long wakeup, flags;
+	save_and_cli(flags);
+
+	flush_cache_all();
+	/* pin 6 is gpio */
+	writel(readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
+
+	/* gpio 6 can cause a wake up event */
+	wakeup = readl(SYS_WAKEMSK);
+	wakeup &= ~(1 << 8);	/* turn off match20 wakeup */
+	wakeup |= 1 << 6;	/* turn on gpio 6 wakeup   */
+	writel(wakeup, SYS_WAKEMSK);
+
+	writel(1, SYS_WAKESRC);	/* clear cause */
+	writel(1, SYS_SLPPWR);	/* prepare to sleep */
+
+	__asm__("la $4, 1f\n\t"
+		"lui $5, 0xb190\n\t"
+		"ori $5, 0x18\n\t"
+		"sw $4, 0($5)\n\t"
+		"li $4, 1\n\t"
+		"lui $5, 0xb190\n\t"
+		"ori $5, 0x7c\n\t"
+		"sw $4, 0($5)\n\t" "sync\n\t" "1:\t\n\t" "nop\n\t");
+
+	/* after a wakeup, the cpu vectors back to 0x1fc00000 so
+	 * it's up to the boot code to get us back here.
+	 */
+	restore_flags(flags);
+	return 0;
+}
+
+static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
+		       void *buffer, size_t * len)
+{
+	int retval = 0;
+
+	if (!write) {
+		*len = 0;
+	} else {
+		retval = pm_send_all(PM_SUSPEND, (void *) 2);
+		if (retval)
+			return retval;
+
+		au_sleep();
+		retval = pm_send_all(PM_RESUME, (void *) 0);
+	}
+	return retval;
+}
+
+static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
+			 void *buffer, size_t * len)
+{
+	int retval = 0;
+
+	if (!write) {
+		*len = 0;
+	} else {
+		retval = pm_send_all(PM_SUSPEND, (void *) 2);
+		if (retval)
+			return retval;
+		suspend_mode = 1;
+		au1_wait();
+		retval = pm_send_all(PM_RESUME, (void *) 0);
+	}
+	return retval;
+}
+
+
+static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
+		      void *buffer, size_t * len)
+{
+	int retval = 0, i;
+	unsigned long val, pll;
+#define TMPBUFLEN 64
+#define MAX_CPU_FREQ 396
+	char buf[8], *p;
+	unsigned long flags, intc0_mask, intc1_mask;
+	unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
+	    old_refresh;
+	unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
+
+	save_and_cli(flags);
+	if (!write) {
+		*len = 0;
+	} else {
+		/* Parse the new frequency */
+		if (*len > TMPBUFLEN - 1) {
+			restore_flags(flags);
+			return -EFAULT;
+		}
+		if (copy_from_user(buf, buffer, *len)) {
+			restore_flags(flags);
+			return -EFAULT;
+		}
+		buf[*len] = 0;
+		p = buf;
+		val = simple_strtoul(p, &p, 0);
+		if (val > MAX_CPU_FREQ) {
+			restore_flags(flags);
+			return -EFAULT;
+		}
+
+		pll = val / 12;
+		if ((pll > 33) || (pll < 7)) {	/* 396 MHz max, 84 MHz min */
+			/* revisit this for higher speed cpus */
+			restore_flags(flags);
+			return -EFAULT;
+		}
+
+		old_baud_base = get_au1000_uart_baud_base();
+		old_cpu_freq = get_au1000_speed();
+
+		new_cpu_freq = pll * 12 * 1000000;
+		new_baud_base = (new_cpu_freq / 4) / 16;
+		set_au1000_speed(new_cpu_freq);
+		set_au1000_uart_baud_base(new_baud_base);
+
+		old_refresh = readl(MEM_SDREFCFG) & 0x1ffffff;
+		new_refresh =
+		    ((old_refresh * new_cpu_freq) /
+		     old_cpu_freq) | (readl(MEM_SDREFCFG) & ~0x1ffffff);
+
+		writel(pll, SYS_CPUPLL);
+		au_sync_delay(1);
+		writel(new_refresh, MEM_SDREFCFG);
+		au_sync_delay(1);
+
+		for (i = 0; i < 4; i++) {
+			if (readl
+			    (UART_BASE + UART_MOD_CNTRL +
+			     i * 0x00100000) == 3) {
+				old_clk =
+				    readl(UART_BASE + UART_CLK +
+					  i * 0x00100000);
+				// baud_rate = baud_base/clk
+				baud_rate = old_baud_base / old_clk;
+				/* we won't get an exact baud rate and the error
+				 * could be significant enough that our new
+				 * calculation will result in a clock that will
+				 * give us a baud rate that's too far off from
+				 * what we really want.
+				 */
+				if (baud_rate > 100000)
+					baud_rate = 115200;
+				else if (baud_rate > 50000)
+					baud_rate = 57600;
+				else if (baud_rate > 30000)
+					baud_rate = 38400;
+				else if (baud_rate > 17000)
+					baud_rate = 19200;
+				else
+					(baud_rate = 9600);
+				// new_clk = new_baud_base/baud_rate
+				new_clk = new_baud_base / baud_rate;
+				writel(new_clk,
+				       UART_BASE + UART_CLK +
+				       i * 0x00100000);
+				au_sync_delay(10);
+			}
+		}
+	}
+
+
+	/* We don't want _any_ interrupts other than
+	 * match20. Otherwise our calibrate_delay()
+	 * calculation will be off, potentially a lot.
+	 */
+	intc0_mask = save_local_and_disable(0);
+	intc1_mask = save_local_and_disable(1);
+	local_enable_irq(AU1000_TOY_MATCH2);
+	restore_flags(flags);
+	calibrate_delay();
+	restore_local_and_enable(0, intc0_mask);
+	restore_local_and_enable(1, intc1_mask);
+	return retval;
+}
+
+
+static struct ctl_table pm_table[] = {
+	{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
+	{ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
+	{CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
+	{0}
+};
+
+static struct ctl_table pm_dir_table[] = {
+	{CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
+	{0}
+};
+
+/*
+ * Initialize power interface
+ */
+static int __init pm_init(void)
+{
+	register_sysctl_table(pm_dir_table, 1);
+	return 0;
+}
+
+__initcall(pm_init);
+
+inline void au1_wait(void)
+{
+	__asm__(".set\tmips3\n\t"
+		"wait\n\t"
+		"nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" ".set\tmips0");
+}
+
+
+/*
+ * This is right out of init/main.c
+ */
+
+/* This is the number of bits of precision for the loops_per_jiffy.  Each
+   bit takes on average 1.5/HZ seconds.  This (like the original) is a little
+   better than 1% */
+#define LPS_PREC 8
+
+static void calibrate_delay(void)
+{
+	unsigned long ticks, loopbit;
+	int lps_precision = LPS_PREC;
+
+	loops_per_jiffy = (1 << 12);
+
+	while (loops_per_jiffy <<= 1) {
+		/* wait for "start of" clock tick */
+		ticks = jiffies;
+		while (ticks == jiffies)
+			/* nothing */ ;
+		/* Go .. */
+		ticks = jiffies;
+		__delay(loops_per_jiffy);
+		ticks = jiffies - ticks;
+		if (ticks)
+			break;
+	}
+
+/* Do a binary approximation to get loops_per_jiffy set to equal one clock
+   (up to lps_precision bits) */
+	loops_per_jiffy >>= 1;
+	loopbit = loops_per_jiffy;
+	while (lps_precision-- && (loopbit >>= 1)) {
+		loops_per_jiffy |= loopbit;
+		ticks = jiffies;
+		while (ticks == jiffies);
+		ticks = jiffies;
+		__delay(loops_per_jiffy);
+		if (jiffies != ticks)	/* longer than 1 tick */
+			loops_per_jiffy &= ~loopbit;
+	}
+}
+
+
+#else				/* CONFIG_PM */
+
+void au1_wait(void)
+{
+	__asm__("nop\n\t" "nop\n\t");
+}
+
+#endif				/* CONFIG_PM */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/prom.c linux/arch/mips/au1000/common/prom.c
--- linux.orig/arch/mips/au1000/common/prom.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/prom.c	2002-08-01 06:42:33.000000000 +0000
@@ -4,7 +4,7 @@
  *    PROM library initialisation code, assuming a version of
  *    pmon is the boot code.
  *
- * Copyright 2000 MontaVista Software Inc.
+ * Copyright 2000,2001 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *         	ppopov@mvista.com or source@mvista.com
  *
@@ -35,7 +35,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/config.h>
+#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/string.h>
@@ -44,22 +44,23 @@
 
 /* #define DEBUG_CMDLINE */
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
-int prom_argc;
-char **prom_argv, **prom_envp;
+char arcs_cmdline[CL_SIZE];
+extern int prom_argc;
+extern char **prom_argv, **prom_envp;
 
-typedef struct {
-	char *name;
-/*	char *val; */
-} t_env_var;
+typedef struct
+{
+    char *name;
+/*    char *val; */
+}t_env_var;
 
 
-char * __init prom_getcmdline(void)
+char * prom_getcmdline(void)
 {
 	return &(arcs_cmdline[0]);
 }
 
-void  __init prom_init_cmdline(void)
+void  prom_init_cmdline(void)
 {
 	char *cp;
 	int actr;
@@ -101,7 +102,7 @@
 	return(NULL);
 }
 
-static inline unsigned char str2hexnum(unsigned char c)
+inline unsigned char str2hexnum(unsigned char c)
 {
 	if(c >= '0' && c <= '9')
 	return c - '0';
@@ -110,11 +111,43 @@
 	return 0; /* foo */
 }
 
-int __init page_is_ram(unsigned long pagenr)
+inline void str2eaddr(unsigned char *ea, unsigned char *str)
 {
-	return 1;
-}
+	int i;
 
-void prom_free_prom_memory (void)
+	for(i = 0; i < 6; i++) {
+		unsigned char num;
+
+		if((*str == '.') || (*str == ':'))
+			str++;
+		num = str2hexnum(*str++) << 4;
+		num |= (str2hexnum(*str++));
+		ea[i] = num;
+	}
+}
+ 
+int get_ethernet_addr(char *ethernet_addr)
 {
+	int i;
+        char *ethaddr_str;
+
+        ethaddr_str = prom_getenv("ethaddr");
+	if (!ethaddr_str) {
+	        printk("ethaddr not set in boot prom\n");
+		return -1;
+	}
+	str2eaddr(ethernet_addr, ethaddr_str);
+
+#if 0
+	printk("get_ethernet_addr: ");
+	for (i=0; i<5; i++)
+		printk("%02x:", (unsigned char)*(ethernet_addr+i));
+	printk("%02x\n", *(ethernet_addr+i));
+#endif
+
+	return 0;
 }
+
+void prom_free_prom_memory (void) {}
+EXPORT_SYMBOL(prom_getcmdline);
+EXPORT_SYMBOL(get_ethernet_addr);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/reset.c linux/arch/mips/au1000/common/reset.c
--- linux.orig/arch/mips/au1000/common/reset.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/reset.c	2002-08-01 06:42:31.000000000 +0000
@@ -36,8 +36,56 @@
 #include <asm/reboot.h>
 #include <asm/system.h>
 
+extern int au_sleep(void);
+
 void au1000_restart(char *command)
 {
+	/* Set all integrated peripherals to disabled states */
+	u32 prid = read_32bit_cp0_register(CP0_PRID);
+
+	printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
+	switch (prid & 0xFF000000)
+	{
+	case 0x00000000: /* Au1000 */
+		outl(0x02, 0xb0000010); /* ac97_enable */
+		outl(0x08, 0xb017fffc); /* usbh_enable - early errata */
+		asm("sync");
+		outl(0x00, 0xb017fffc); /* usbh_enable */
+		outl(0x00, 0xb0200058); /* usbd_enable */
+		outl(0x00, 0xb0300040); /* ir_enable */
+		outl(0x00, 0xb0520000); /* macen0 */
+		outl(0x00, 0xb0520004); /* macen1 */
+		outl(0x00, 0xb1000008); /* i2s_enable  */
+		outl(0x00, 0xb1100100); /* uart0_enable */
+		outl(0x00, 0xb1200100); /* uart1_enable */
+		outl(0x00, 0xb1300100); /* uart2_enable */
+		outl(0x00, 0xb1400100); /* uart3_enable */
+		outl(0x02, 0xb1600100); /* ssi0_enable */
+		outl(0x02, 0xb1680100); /* ssi1_enable */
+		outl(0x00, 0xb1900020); /* sys_freqctrl0 */
+		outl(0x00, 0xb1900024); /* sys_freqctrl1 */
+		outl(0x00, 0xb1900028); /* sys_clksrc */
+		outl(0x00, 0xb1900100); /* sys_pininputen */
+		break;
+	case 0x01000000: /* Au1500 */
+		outl(0x02, 0xb0000010); /* ac97_enable */
+		outl(0x08, 0xb017fffc); /* usbh_enable - early errata */
+		asm("sync");
+		outl(0x00, 0xb017fffc); /* usbh_enable */
+		outl(0x00, 0xb0200058); /* usbd_enable */
+		outl(0x00, 0xb1520000); /* macen0 */
+		outl(0x00, 0xb1520004); /* macen1 */
+		outl(0x00, 0xb1100100); /* uart0_enable */
+		outl(0x00, 0xb1400100); /* uart3_enable */
+		outl(0x00, 0xb1900020); /* sys_freqctrl0 */
+		outl(0x00, 0xb1900024); /* sys_freqctrl1 */
+		outl(0x00, 0xb1900028); /* sys_clksrc */
+		outl(0x00, 0xb1900100); /* sys_pininputen */
+
+	default:
+		break;
+	}
+
 	set_cp0_status(ST0_BEV | ST0_ERL);
 	set_cp0_config(CONF_CM_UNCACHED);
 	flush_cache_all();
@@ -48,10 +96,18 @@
 void au1000_halt(void)
 {
 	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+#ifdef CONFIG_PM
+	au_sleep();
+
+	/* should not get here */
+	printk(KERN_ERR "Unable to put cpu in sleep mode\n");
+	while(1);
+#else
 	while (1)
 		__asm__(".set\tmips3\n\t"
 	                "wait\n\t"
 			".set\tmips0");
+#endif
 }
 
 void au1000_power_off(void)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/rtc.c linux/arch/mips/au1000/common/rtc.c
--- linux.orig/arch/mips/au1000/common/rtc.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/common/rtc.c	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * RTC routines for PC style attached Dallas chip.
+ *
+ * Copyright (C) 1998, 2001 by Ralf Baechle
+ */
+#include <linux/mc146818rtc.h>
+#include <asm/io.h>
+
+#define PB1500_RTC_ADDR 0xAC000000
+
+static unsigned char std_rtc_read_data(unsigned long addr)
+{
+	addr <<= 2;
+	return readb(addr + PB1500_RTC_ADDR);
+}
+
+static void std_rtc_write_data(unsigned char data, unsigned long addr)
+{
+	addr <<= 2;
+	writeb(data, addr + PB1500_RTC_ADDR);
+}
+
+static int std_rtc_bcd_mode(void)
+{
+	return 1;
+}
+
+struct rtc_ops pb1500_rtc_ops = {
+	&std_rtc_read_data,
+	&std_rtc_write_data,
+	&std_rtc_bcd_mode
+};
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/serial.c linux/arch/mips/au1000/common/serial.c
--- linux.orig/arch/mips/au1000/common/serial.c	2001-10-05 19:06:51.000000000 +0000
+++ linux/arch/mips/au1000/common/serial.c	2002-08-01 06:42:38.000000000 +0000
@@ -131,7 +131,7 @@
 
 static struct timer_list serial_timer;
 
-extern unsigned long get_au1000_uart_baud(void);
+extern unsigned long get_au1000_uart_baud_base(void);
 
 /* serial subtype definitions */
 #ifndef SERIAL_TYPE_NORMAL
@@ -241,12 +241,12 @@
 
 static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
 {
-	return (inl(info->port+offset) & 0xff);
+	return (inl(info->port+offset) & 0xffff);
 }
 
 static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
 {
-	outl(value & 0xff, info->port+offset);
+	outl(value & 0xffff, info->port+offset);
 }
 
 
@@ -752,6 +752,7 @@
 
 	if (inl(UART_MOD_CNTRL + state->port) != 0x3) {
 		outl(3, UART_MOD_CNTRL + state->port);
+		au_sync_delay(10);
 	}
 #ifdef SERIAL_DEBUG_OPEN
 	printk("starting up ttys%d (irq %d)...", info->line, state->irq);
@@ -986,6 +987,10 @@
 		set_bit(TTY_IO_ERROR, &info->tty->flags);
 
 	info->flags &= ~ASYNC_INITIALIZED;
+#ifndef CONFIG_REMOTE_DEBUG
+	outl(0, UART_MOD_CNTRL + state->port);
+	au_sync_delay(10);
+#endif
 	restore_flags(flags);
 }
 
@@ -1037,7 +1042,8 @@
 	if (!baud) {
 		baud = 9600;	/* B0 transition handled in rs_set_termios */
 	}
-	baud_base = info->state->baud_base;
+	baud_base = get_au1000_uart_baud_base();
+
 	//if (baud == 38400 &&
 	if (((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) {
 		quot = info->state->custom_divisor;
@@ -2511,6 +2517,7 @@
 
 	if (inl(UART_MOD_CNTRL + state->port) != 0x3) {
 		outl(3, UART_MOD_CNTRL + state->port);
+		au_sync_delay(10);
 	}
 		
 	state->type = PORT_16550;
@@ -2541,7 +2548,11 @@
 	serial_outp(info, UART_FCR, 0);
 	(void)serial_in(info, UART_RX);
 	serial_outp(info, UART_IER, 0);
-	
+
+#ifndef CONFIG_REMOTE_DEBUG
+	outl(0, UART_MOD_CNTRL + state->port);
+	au_sync_delay(10);
+#endif
 	restore_flags(flags);
 }
 
@@ -2643,12 +2654,12 @@
 	callout_driver.proc_entry = 0;
 
 	if (tty_register_driver(&serial_driver))
-		panic("Couldn't register serial driver\n");
+		panic("Couldn't register serial driver");
 	if (tty_register_driver(&callout_driver))
-		panic("Couldn't register callout driver\n");
+		panic("Couldn't register callout driver");
 	
 	for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
-		state->baud_base = get_au1000_uart_baud();
+		state->baud_base = get_au1000_uart_baud_base();
 		state->magic = SSTATE_MAGIC;
 		state->line = i;
 		state->type = PORT_UNKNOWN;
@@ -2922,35 +2933,6 @@
 	serial_out(info, UART_IER, ier);
 }
 
-/*
- *	Receive character from the serial port
- */
-static int serial_console_wait_key(struct console *co)
-{
-	static struct async_struct *info;
-	int ier, c;
-
-	info = &async_sercons;
-
-	/*
-	 *	First save the IER then disable the interrupts so
-	 *	that the real driver for the port does not get the
-	 *	character.
-	 */
-	ier = serial_in(info, UART_IER);
-	serial_out(info, UART_IER, 0x00);
- 
-	while ((serial_in(info, UART_LSR) & UART_LSR_DR) == 0);
-	c = serial_in(info, UART_RX);
-
-	/*
-	 *	Restore the interrupts
-	 */
-	serial_out(info, UART_IER, ier);
-
-	return c;
-}
-
 static kdev_t serial_console_device(struct console *c)
 {
 	return MKDEV(TTY_MAJOR, 64 + c->index);
@@ -3044,7 +3026,7 @@
 	info->io_type = state->io_type;
 	info->iomem_base = state->iomem_base;
 	info->iomem_reg_shift = state->iomem_reg_shift;
-	state->baud_base = get_au1000_uart_baud();
+	state->baud_base = get_au1000_uart_baud_base();
 	quot = state->baud_base / baud;
 
 	cval = cflag & (CSIZE | CSTOPB);
@@ -3075,7 +3057,6 @@
 	name:		"ttyS",
 	write:		serial_console_write,
 	device:		serial_console_device,
-	wait_key:	serial_console_wait_key,
 	setup:		serial_console_setup,
 	flags:		CON_PRINTBUFFER,
 	index:		-1,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/time.c linux/arch/mips/au1000/common/time.c
--- linux.orig/arch/mips/au1000/common/time.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/common/time.c	2002-08-01 06:42:39.000000000 +0000
@@ -1,4 +1,5 @@
 /*
+ * 
  * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
  * Copied and modified Carsten Langgaard's time.c
  *
@@ -23,7 +24,10 @@
  * ########################################################################
  *
  * Setting up the clock on the MIPS boards.
+ *
  */
+
+#include <linux/types.h>
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
@@ -32,28 +36,38 @@
 
 #include <asm/mipsregs.h>
 #include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
 #include <asm/div64.h>
 #include <asm/au1000.h>
 
 #include <linux/mc146818rtc.h>
 #include <linux/timex.h>
 
+extern void startup_match20_interrupt(void);
+
 extern volatile unsigned long wall_jiffies;
 unsigned long missed_heart_beats = 0;
-unsigned long uart_baud_base;
 
 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
 static unsigned long r4k_cur;    /* What counter should be at next timer irq */
 extern rwlock_t xtime_lock;
+unsigned int mips_counter_frequency = 0;
+
+/* Cycle counter value at the previous timer interrupt.. */
+static unsigned int timerhi = 0, timerlo = 0;
 
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+#ifdef CONFIG_PM
+#define MATCH20_INC 328
+extern void startup_match20_interrupt(void);
+static unsigned long last_pc0, last_match20;
+#endif
 
 static inline void ack_r4ktimer(unsigned long newval)
 {
 	write_32bit_cp0_register(CP0_COMPARE, newval);
 }
 
-
 /*
  * There are a lot of conceptually broken versions of the MIPS timer interrupt
  * handler floating around.  This one is rather different, but the algorithm
@@ -62,12 +76,27 @@
 unsigned long wtimer;
 void mips_timer_interrupt(struct pt_regs *regs)
 {
-	int irq = 7;
+	int irq = 63;
+	unsigned long count;
+	int cpu = smp_processor_id();
+
+	irq_enter(cpu, irq);
+	kstat.irqs[cpu][irq]++;
+
+#ifdef CONFIG_PM
+	printk(KERN_ERR "Unexpected CP0 interrupt\n");
+	regs->cp0_status &= ~IE_IRQ5; /* disable CP0 interrupt */
+	return;
+#endif
 
 	if (r4k_offset == 0)
 		goto null;
 
 	do {
+		count = read_32bit_cp0_register(CP0_COUNT);
+		timerhi += (count < timerlo);   /* Wrap around */
+		timerlo = count;
+
 		kstat.irqs[0][irq]++;
 		do_timer(regs);
 		r4k_cur += r4k_offset;
@@ -76,12 +105,61 @@
 	} while (((unsigned long)read_32bit_cp0_register(CP0_COUNT)
 	         - r4k_cur) < 0x7fffffff);
 
+	irq_exit(cpu, irq);
+
+	if (softirq_pending(cpu))
+		do_softirq();
 	return;
 
 null:
 	ack_r4ktimer(0);
 }
 
+#ifdef CONFIG_PM
+void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+	unsigned long pc0;
+	int time_elapsed;
+	static int jiffie_drift = 0;
+
+	kstat.irqs[0][irq]++;
+	if (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
+		/* should never happen! */
+		printk(KERN_WARNING "counter 0 w status eror\n");
+		return;
+	}
+
+	pc0 = inl(SYS_TOYREAD);
+	if (pc0 < last_match20) {
+		/* counter overflowed */
+		time_elapsed = (0xffffffff - last_match20) + pc0;
+	}
+	else {
+		time_elapsed = pc0 - last_match20;
+	}
+
+	while (time_elapsed > 0) {
+		do_timer(regs);
+		time_elapsed -= MATCH20_INC;
+		last_match20 += MATCH20_INC;
+		jiffie_drift++;
+	}
+
+	last_pc0 = pc0;
+	outl(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+	au_sync();
+
+	/* our counter ticks at 10.009765625 ms/tick, we we're running
+	 * almost 10uS too slow per tick.
+	 */
+	 
+	if (jiffie_drift >= 999) {
+		jiffie_drift -= 999;
+		do_timer(regs); /* increment jiffies by one */
+	}
+}
+#endif
+
 /* 
  * Figure out the r4k offset, the amount to increment the compare
  * register for each time tick. 
@@ -90,49 +168,48 @@
 unsigned long cal_r4koff(void)
 {
 	unsigned long count;
-	unsigned long cpu_pll;
 	unsigned long cpu_speed;
 	unsigned long start, end;
 	unsigned long counter;
-	int i;
 	int trim_divide = 16;
+	unsigned long flags;
 
-	counter = inl(PC_COUNTER_CNTRL);
-	outl(counter | PC_CNTRL_EN1, PC_COUNTER_CNTRL);
+	save_and_cli(flags);
 
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T1S);
-	outl(trim_divide-1, PC1_TRIM);    /* RTC now ticks at 32.768/16 kHz */
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T1S);
-
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_C1S);
-	outl (0, PC1_COUNTER_WRITE);
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_C1S);
+	counter = inl(SYS_COUNTER_CNTRL);
+	outl(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
 
-	start = inl(PC1_COUNTER_READ);
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+	outl(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+	outl (0, SYS_TOYWRITE);
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+
+	start = inl(SYS_RTCREAD);
 	start += 2;
 	/* wait for the beginning of a new tick */
-	while (inl(PC1_COUNTER_READ) < start);
+	while (inl(SYS_RTCREAD) < start);
 
 	/* Start r4k counter. */
 	write_32bit_cp0_register(CP0_COUNT, 0);
 	end = start + (32768 / trim_divide)/2; /* wait 0.5 seconds */
 
-	while (end > inl(PC1_COUNTER_READ));
+	while (end > inl(SYS_RTCREAD));
 
 	count = read_32bit_cp0_register(CP0_COUNT);
 	cpu_speed = count * 2;
-	uart_baud_base = (((cpu_speed) / 4) / 16);
+	mips_counter_frequency = count;
+	set_au1000_uart_baud_base(((cpu_speed) / 4) / 16);
+	restore_flags(flags);
 	return (cpu_speed / HZ);
 }
 
-static unsigned long __init get_mips_time(void)
-{
-	return inl(PC0_COUNTER_READ);
-}
 
 void __init time_init(void)
 {
-        unsigned int est_freq, flags;
+        unsigned int est_freq;
 
 	printk("calculating r4koff... ");
 	r4k_offset = cal_r4koff();
@@ -144,25 +221,51 @@
 	est_freq -= est_freq%10000;
 	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
 	       (est_freq%1000000)*100/1000000);
+	set_au1000_speed(est_freq);
+	set_au1000_lcd_clock(); // program the LCD clock
 	r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
 
 	write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
-	set_cp0_status(ALLINTS);
 
-	/* Read time from the RTC chipset. */
-	write_lock_irqsave (&xtime_lock, flags);
-	xtime.tv_sec = get_mips_time();
+	/* no RTC on the pb1000 */
+	xtime.tv_sec = 0;
 	xtime.tv_usec = 0;
-	write_unlock_irqrestore(&xtime_lock, flags);
+
+#ifdef CONFIG_PM
+	/*
+	 * setup counter 0, since it keeps ticking after a
+	 * 'wait' instruction has been executed. The CP0 timer and
+	 * counter 1 do NOT continue running after 'wait'
+	 *
+	 * It's too early to call request_irq() here, so we handle
+	 * counter 0 interrupt as a special irq and it doesn't show
+	 * up under /proc/interrupts.
+	 */
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+	writel(0, SYS_TOYWRITE);
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+
+	writel(readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
+	writel(~0, SYS_WAKESRC);
+	au_sync();
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
+
+	/* setup match20 to interrupt once every 10ms */
+	last_pc0 = last_match20 = readl(SYS_TOYREAD);
+	writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+	au_sync();
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
+	startup_match20_interrupt();
+#endif
+
+	//set_cp0_status(ALLINTS);
+	au_sync();
 }
 
 /* This is for machines which generate the exact clock. */
 #define USECS_PER_JIFFY (1000000/HZ)
-#define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff)
-
-/* Cycle counter value at the previous timer interrupt.. */
+#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
 
-static unsigned int timerhi = 0, timerlo = 0;
 
 static unsigned long
 div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
@@ -173,11 +276,28 @@
 }
 
 
-/*
- * FIXME: Does playing with the RP bit in c0_status interfere with this code?
- */
 static unsigned long do_fast_gettimeoffset(void)
 {
+#ifdef CONFIG_PM
+	unsigned long pc0;
+	unsigned long offset;
+
+	pc0 = readl(SYS_TOYREAD);
+	if (pc0 < last_pc0) {
+		offset = 0xffffffff - last_pc0 + pc0;
+		printk("offset over: %x\n", (unsigned)offset);
+	}
+	else {
+		offset = (unsigned long)(((pc0 - last_pc0) * 305) / 10);
+	}
+	if ((pc0-last_pc0) > 2*MATCH20_INC) {
+		printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", 
+				(unsigned)offset, (unsigned)last_pc0, 
+				(unsigned)last_match20, (unsigned)pc0);
+	}
+	au_sync();
+	return offset;
+#else
 	u32 count;
 	unsigned long res, tmp;
 	unsigned long r0;
@@ -225,6 +345,7 @@
 		res = USECS_PER_JIFFY-1;
 
 	return res;
+#endif
 }
 
 void do_gettimeofday(struct timeval *tv)
@@ -274,13 +395,3 @@
 
 	write_unlock_irq (&xtime_lock);
 }
-
-/*
- * The UART baud base is not known at compile time ... if
- * we want to be able to use the same code on different
- * speed CPUs.
- */
-unsigned long get_au1000_uart_baud()
-{
-	return uart_baud_base;
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/common/usbdev.c linux/arch/mips/au1000/common/usbdev.c
--- linux.orig/arch/mips/au1000/common/usbdev.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/common/usbdev.c	2002-08-01 06:42:30.000000000 +0000
@@ -0,0 +1,1844 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Au1000 USB Device-Side Serial TTY Driver
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *		stevel@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/fcntl.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/smp_lock.h>
+#define DEBUG
+#include <linux/usb.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/au1000.h>
+#include <asm/au1000_dma.h>
+
+/* Module information */
+MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
+MODULE_DESCRIPTION("Au1000 USB Device-Side Serial TTY Driver");
+
+#undef USBDEV_PIO
+
+#define SERIAL_TTY_MAJOR 189
+
+#define MAX(a,b)	(((a)>(b))?(a):(b))
+
+#define ALLOC_FLAGS (in_interrupt () ? GFP_ATOMIC : GFP_KERNEL)
+
+#define MAX_NUM_PORTS 2
+
+#define NUM_PORTS 1
+#define NUM_EP 2*NUM_PORTS
+
+#define EP0_MAX_PACKET_SIZE 64
+#define EP2_MAX_PACKET_SIZE 64
+#define EP3_MAX_PACKET_SIZE 64
+#define EP4_MAX_PACKET_SIZE 64
+#define EP5_MAX_PACKET_SIZE 64
+
+#ifdef USBDEV_PIO
+#define EP_FIFO_DEPTH 8
+#endif
+
+typedef enum {
+	ATTACHED = 0,
+	POWERED,
+	DEFAULT,
+	ADDRESS,
+	CONFIGURED
+} dev_state_t;
+
+/* local function prototypes */
+static int serial_open(struct tty_struct *tty, struct file *filp);
+static void serial_close(struct tty_struct *tty, struct file *filp);
+static int serial_write(struct tty_struct *tty, int from_user,
+			const unsigned char *buf, int count);
+static int serial_write_room(struct tty_struct *tty);
+static int serial_chars_in_buffer(struct tty_struct *tty);
+static void serial_throttle(struct tty_struct *tty);
+static void serial_unthrottle(struct tty_struct *tty);
+static int serial_ioctl(struct tty_struct *tty, struct file *file,
+			unsigned int cmd, unsigned long arg);
+static void serial_set_termios (struct tty_struct *tty, struct termios * old);
+
+typedef struct {
+	int read_fifo;
+	int write_fifo;
+	int ctrl_stat;
+	int read_fifo_status;
+	int write_fifo_status;
+} endpoint_reg_t;
+
+typedef struct pkt {
+	int size;
+	u8 *bufptr;
+	struct pkt *next;
+	u8 buf[0];
+} pkt_t;
+
+typedef struct {
+	pkt_t *head;
+	pkt_t *tail;
+	int count;
+} pkt_list_t;
+
+typedef struct {
+	struct usb_endpoint_descriptor *desc;
+	endpoint_reg_t *reg;
+	// Only one of these are used, unless this is a control ep
+	pkt_list_t inlist;
+	pkt_list_t outlist;
+	unsigned int indma, outdma;	// DMA channel numbers for IN, OUT
+	int inirq, outirq;	// DMA buffer done irq numbers
+	int max_pkt_size;
+	spinlock_t lock;
+} endpoint_t;
+
+struct usb_serial_port {
+	struct usb_serial *serial;	/* ptr back to the owner of this port */
+	struct tty_struct *tty;	/* the coresponding tty for this port */
+	unsigned char number;
+	char active;		/* someone has this device open */
+	spinlock_t port_lock;
+
+	endpoint_t ep_bulkin;
+	endpoint_t ep_bulkout;
+
+	wait_queue_head_t write_wait;
+
+	/* task queue for line discipline waking up on send packet complete */
+	struct tq_struct send_complete_tq;
+	/* task queue for line discipline wakeup on receive packet complete */
+	struct tq_struct receive_complete_tq;
+
+	int open_count;		/* number of times this port has been opened */
+};
+
+struct usb_serial {
+	struct tty_driver *tty_driver;	/* the tty_driver for this device */
+	unsigned char minor;	/* the minor number for this device */
+
+	endpoint_t ep_ctrl;
+
+	struct usb_device_descriptor *dev_desc;
+	struct usb_interface_descriptor *if_desc;
+	struct usb_config_descriptor *conf_desc;
+	struct usb_string_descriptor *str_desc[6];
+
+	struct usb_serial_port port[NUM_PORTS];
+
+	dev_state_t state;	// device state
+	int suspended;		// suspended flag
+	int address;		// device address
+	int interface;
+	u8 alternate_setting;
+	u8 configuration;	// configuration value
+	int remote_wakeup_en;
+};
+
+
+static struct usb_device_descriptor dev_desc = {
+	bLength:USB_DT_DEVICE_SIZE,
+	bDescriptorType:USB_DT_DEVICE,
+	bcdUSB:0x0110,		//usb rev 1.0
+	bDeviceClass:USB_CLASS_PER_INTERFACE,	//class    (none)
+	bDeviceSubClass:0x00,	//subclass (none)
+	bDeviceProtocol:0x00,	//protocol (none)
+	bMaxPacketSize0:EP0_MAX_PACKET_SIZE,	//max packet size for ep0
+	idVendor:0x6d04,	//vendor  id
+	idProduct:0x0bc0,	//product id
+	bcdDevice:0x0001,	//BCD rev 0.1
+	iManufacturer:0x01,	//manufactuer string index
+	iProduct:0x02,		//product string index
+	iSerialNumber:0x03,	//serial# string index
+	bNumConfigurations:0x01	//num configurations
+};
+
+static struct usb_endpoint_descriptor ep_desc[] = {
+	{
+	 // EP2, Bulk IN for Port 0
+	      bLength:USB_DT_ENDPOINT_SIZE,
+	      bDescriptorType:USB_DT_ENDPOINT,
+	      bEndpointAddress:USB_DIR_IN | 0x02,
+	      bmAttributes:USB_ENDPOINT_XFER_BULK,
+	      wMaxPacketSize:EP2_MAX_PACKET_SIZE,
+	      bInterval:0x00	// ignored for bulk
+	 },
+	{
+	 // EP4, Bulk OUT for Port 0
+	      bLength:USB_DT_ENDPOINT_SIZE,
+	      bDescriptorType:USB_DT_ENDPOINT,
+	      bEndpointAddress:USB_DIR_OUT | 0x04,
+	      bmAttributes:USB_ENDPOINT_XFER_BULK,
+	      wMaxPacketSize:EP4_MAX_PACKET_SIZE,
+	      bInterval:0x00	// ignored for bulk
+	 },
+	{
+	 // EP3, Bulk IN for Port 1
+	      bLength:USB_DT_ENDPOINT_SIZE,
+	      bDescriptorType:USB_DT_ENDPOINT,
+	      bEndpointAddress:USB_DIR_IN | 0x03,
+	      bmAttributes:USB_ENDPOINT_XFER_BULK,
+	      wMaxPacketSize:EP3_MAX_PACKET_SIZE,
+	      bInterval:0x00	// ignored for bulk
+	 },
+	{
+	 // EP5, Bulk OUT for Port 1
+	      bLength:USB_DT_ENDPOINT_SIZE,
+	      bDescriptorType:USB_DT_ENDPOINT,
+	      bEndpointAddress:USB_DIR_OUT | 0x05,
+	      bmAttributes:USB_ENDPOINT_XFER_BULK,
+	      wMaxPacketSize:EP5_MAX_PACKET_SIZE,
+	      bInterval:0x00	// ignored for bulk
+	 },
+};
+
+static struct usb_interface_descriptor if_desc = {
+	bLength:USB_DT_INTERFACE_SIZE,
+	bDescriptorType:USB_DT_INTERFACE,
+	bInterfaceNumber:0x00,
+	bAlternateSetting:0x00,
+	bNumEndpoints:NUM_EP,
+	bInterfaceClass:0xff,
+	bInterfaceSubClass:0xab,
+	bInterfaceProtocol:0x00,
+	iInterface:0x05
+};
+
+#define CONFIG_DESC_LEN \
+ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
+
+static struct usb_config_descriptor config_desc = {
+	bLength:USB_DT_CONFIG_SIZE,
+	bDescriptorType:USB_DT_CONFIG,
+	wTotalLength:CONFIG_DESC_LEN,
+	bNumInterfaces:0x01,
+	bConfigurationValue:0x01,
+	iConfiguration:0x04,	// configuration string
+	bmAttributes:0xc0,	// self-powered
+	MaxPower:20		// 40 mA
+};
+
+// These strings will be converted to Unicode before sending
+static char *strings[5] = {
+	"Alchemy Semiconductor",
+	"Alchemy Au1000",
+	"1.0",
+	"Au1000 UART Config",
+	"Au1000 UART Interface"
+};
+
+// String[0] is a list of Language IDs supported by this device
+static struct usb_string_descriptor string_desc0 = {
+	bLength:4,
+	bDescriptorType:USB_DT_STRING,
+	wData:{0x0409}		// English, US
+};
+
+
+static endpoint_reg_t ep_reg[] = {
+	// FIFO's 0 and 1 are EP0 default control
+	{USBD_EP0RD, USBD_EP0WR, USBD_EP0CS, USBD_EP0RDSTAT, USBD_EP0WRSTAT},
+	// FIFO 2 is EP2, Port 0, bulk IN
+	{ -1, USBD_EP2WR, USBD_EP2CS, -1, USBD_EP2WRSTAT },
+	// FIFO 4 is EP4, Port 0, bulk OUT
+	    {USBD_EP4RD, -1, USBD_EP4CS, USBD_EP3WR, -1},
+	// FIFO 3 is EP3, Port 1, bulk IN
+	{ -1, USBD_EP3WRSTAT, USBD_EP3CS, -1, USBD_EP3WRSTAT },
+	// FIFO 5 is EP5, Port 1, bulk OUT
+	    {USBD_EP5RD, -1, USBD_EP5CS, USBD_EP5RDSTAT, -1}
+};
+
+static struct {
+	unsigned int id;
+	const char *str;
+} ep_dma_id[] = {
+	{ DMA_ID_USBDEV_EP0_TX, "USBDev EP0 IN" },
+	{ DMA_ID_USBDEV_EP0_RX, "USBDev EP0 OUT" },
+	{ DMA_ID_USBDEV_EP2_TX, "USBDev EP2 IN" },
+	{ DMA_ID_USBDEV_EP4_RX, "USBDev EP4 OUT" },
+	{ DMA_ID_USBDEV_EP3_TX, "USBDev EP3 IN" },
+	{ DMA_ID_USBDEV_EP5_RX, "USBDev EP5 OUT" }
+};
+
+static int serial_refcount;
+static struct tty_driver serial_tty_driver;
+static struct tty_struct *serial_tty[1];
+static struct termios *serial_termios[1];
+static struct termios *serial_termios_locked[1];
+static struct usb_serial usbserial;
+
+#define DIR_OUT 0
+#define DIR_IN  (1<<3)
+
+static const u32 au1000_config_table[25] __devinitdata = {
+	0x00,
+	    ((EP0_MAX_PACKET_SIZE & 0x380) >> 7) |
+	    (USB_ENDPOINT_XFER_CONTROL << 4),
+	(EP0_MAX_PACKET_SIZE & 0x7f) << 1,
+	0x00,
+	0x01,
+
+	0x10,
+	    ((EP2_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_IN |
+	    (USB_ENDPOINT_XFER_BULK << 4),
+	(EP2_MAX_PACKET_SIZE & 0x7f) << 1,
+	0x00,
+	0x02,
+
+	0x20,
+	    ((EP3_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_IN |
+	    (USB_ENDPOINT_XFER_BULK << 4),
+	(EP3_MAX_PACKET_SIZE & 0x7f) << 1,
+	0x00,
+	0x03,
+
+	0x30,
+	    ((EP4_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_OUT |
+	    (USB_ENDPOINT_XFER_BULK << 4),
+	(EP4_MAX_PACKET_SIZE & 0x7f) << 1,
+	0x00,
+	0x04,
+
+	0x40,
+	    ((EP5_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_OUT |
+	    (USB_ENDPOINT_XFER_BULK << 4),
+	(EP5_MAX_PACKET_SIZE & 0x7f) << 1,
+	0x00,
+	0x05
+};
+
+static inline endpoint_t *
+fifonum_to_ep(struct usb_serial* serial, int fifo_num)
+{
+	switch (fifo_num) {
+	case 0:
+	case 1:
+		return &serial->ep_ctrl;
+	case 2:
+		return &serial->port[0].ep_bulkin;
+	case 3:
+		return &serial->port[1].ep_bulkin;
+	case 4:
+		return &serial->port[0].ep_bulkout;
+	case 5:
+		return &serial->port[1].ep_bulkout;
+	}
+
+	return NULL;
+}
+
+static inline struct usb_serial_port *
+fifonum_to_port(struct usb_serial* serial, int fifo_num)
+{
+	switch (fifo_num) {
+	case 2:
+	case 4:
+		return &serial->port[0];
+	case 3:
+	case 5:
+		return &serial->port[1];
+	}
+
+	return NULL;
+}
+
+static inline endpoint_t *
+epnum_to_ep(struct usb_serial* serial, int ep_num)
+{
+	switch (ep_num) {
+	case 0:
+		return &serial->ep_ctrl;
+	case 2:
+		return &serial->port[0].ep_bulkin;
+	case 3:
+		return &serial->port[1].ep_bulkin;
+	case 4:
+		return &serial->port[0].ep_bulkout;
+	case 5:
+		return &serial->port[1].ep_bulkout;
+	}
+
+	return NULL;
+}
+
+
+static inline int
+port_paranoia_check(struct usb_serial_port *port, const char *function)
+{
+	if (!port) {
+		dbg("%s - port == NULL", function);
+		return -1;
+	}
+	if (!port->serial) {
+		dbg("%s - port->serial == NULL", function);
+		return -1;
+	}
+	if (!port->tty) {
+		dbg("%s - port->tty == NULL", function);
+		return -1;
+	}
+
+	return 0;
+}
+
+static inline struct usb_serial*
+get_usb_serial (struct usb_serial_port *port, const char *function)
+{
+	/* if no port was specified, or it fails a paranoia check */
+	if (!port || port_paranoia_check(port, function)) {
+		/* then say that we dont have a valid usb_serial thing,
+		 * which will end up genrating -ENODEV return values */
+		return NULL;
+	}
+
+	return port->serial;
+}
+
+
+static inline pkt_t *
+alloc_packet(int data_size)
+{
+	pkt_t* pkt = (pkt_t *)kmalloc(sizeof(pkt_t) + data_size, ALLOC_FLAGS);
+	if (!pkt)
+		return NULL;
+	pkt->size = data_size;
+	pkt->bufptr = pkt->buf;
+#ifndef USBDEV_PIO
+	pkt->bufptr = KSEG1ADDR(pkt->bufptr);
+#endif
+	pkt->next = NULL;
+	return pkt;
+}
+
+
+/*
+ * Link a packet to the tail of the enpoint's packet list.
+ */
+static void
+link_packet(endpoint_t * ep, pkt_list_t * list, pkt_t * pkt)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	if (!list->tail) {
+		list->head = list->tail = pkt;
+		list->count = 1;
+	} else {
+		list->tail->next = pkt;
+		list->tail = pkt;
+		list->count++;
+	}
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+}
+
+/*
+ * Unlink and return a packet from the head of the enpoint's packet list.
+ */
+static pkt_t *
+unlink_packet(endpoint_t * ep, pkt_list_t * list)
+{
+	unsigned long flags;
+	pkt_t *pkt;
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	pkt = list->head;
+	if (!pkt || !list->count) {
+		spin_unlock_irqrestore(&ep->lock, flags);
+		return NULL;
+	}
+
+	list->head = pkt->next;
+	if (!list->head) {
+		list->head = list->tail = NULL;
+		list->count = 0;
+	} else
+		list->count--;
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+
+	return pkt;
+}
+
+/*
+ * Create and attach a new packet to the tail of the enpoint's
+ * packet list.
+ */
+static pkt_t *
+add_packet(endpoint_t * ep, pkt_list_t * list, int size)
+{
+	pkt_t *pkt = alloc_packet(size);
+	if (!pkt)
+		return NULL;
+
+	link_packet(ep, list, pkt);
+	return pkt;
+}
+
+
+/*
+ * Unlink and free a packet from the head of the enpoint's
+ * packet list.
+ */
+static inline void
+free_packet(endpoint_t * ep, pkt_list_t * list)
+{
+	kfree(unlink_packet(ep, list));
+}
+
+static inline void
+flush_pkt_list(endpoint_t * ep, pkt_list_t * list)
+{
+	while (list->count)
+		free_packet(ep, list);
+}
+
+
+static inline void
+flush_write_fifo(endpoint_t * ep)
+{
+	if (ep->reg->write_fifo_status >= 0) {
+		outl_sync(USBDEV_FSTAT_FLUSH, ep->reg->write_fifo_status);
+		udelay(100);
+		outl_sync(USBDEV_FSTAT_UF | USBDEV_FSTAT_OF,
+			  ep->reg->write_fifo_status);
+	}
+}
+
+
+static inline void
+flush_read_fifo(endpoint_t * ep)
+{
+	if (ep->reg->read_fifo_status >= 0) {
+		outl_sync(USBDEV_FSTAT_FLUSH, ep->reg->read_fifo_status);
+		udelay(100);
+		outl_sync(USBDEV_FSTAT_UF | USBDEV_FSTAT_OF,
+			  ep->reg->read_fifo_status);
+	}
+}
+
+
+static void
+endpoint_flush(endpoint_t * ep)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	// First, flush all packets
+	flush_pkt_list(ep, &ep->inlist);
+	flush_pkt_list(ep, &ep->outlist);
+
+	// Now flush the endpoint's h/w FIFO(s)
+	flush_write_fifo(ep);
+	flush_read_fifo(ep);
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+}
+
+
+static void
+endpoint_stall(endpoint_t * ep)
+{
+	unsigned long flags;
+	u32 cs;
+
+	dbg(__FUNCTION__);
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	cs = inl(ep->reg->ctrl_stat) | USBDEV_CS_STALL;
+	outl_sync(cs, ep->reg->ctrl_stat);
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+}
+
+static void
+endpoint_unstall(endpoint_t * ep)
+{
+	unsigned long flags;
+	u32 cs;
+
+	dbg(__FUNCTION__);
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	cs = inl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL;
+	outl_sync(cs, ep->reg->ctrl_stat);
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+}
+
+static void
+endpoint_reset_datatoggle(endpoint_t * ep)
+{
+	// FIXME: is this possible?
+}
+
+
+#ifdef USBDEV_PIO
+static int
+endpoint_fifo_read(endpoint_t * ep)
+{
+	unsigned long flags;
+	int read_count = 0;
+	u8 *bufptr;
+	pkt_t *pkt = ep->outlist.tail;
+
+	if (!pkt)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	bufptr = pkt->bufptr;
+	while (inl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) {
+		*bufptr++ = inl(ep->reg->read_fifo) & 0xff;
+		read_count++;
+		pkt->size++;
+	}
+	pkt->bufptr = bufptr;
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+	return read_count;
+}
+
+
+static int
+endpoint_fifo_write(endpoint_t * ep)
+{
+	unsigned long flags;
+	int write_count = 0;
+	u8 *bufptr;
+	pkt_t *pkt = ep->inlist.head;
+
+	if (!pkt)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	bufptr = pkt->bufptr;
+	while ((inl(ep->reg->write_fifo_status) & USBDEV_FSTAT_FCNT_MASK) <
+	       EP_FIFO_DEPTH) {
+		if (bufptr < pkt->buf + pkt->size) {
+			outl_sync(*bufptr++, ep->reg->write_fifo);
+			write_count++;
+		} else {
+			break;
+		}
+	}
+	pkt->bufptr = bufptr;
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+	return write_count;
+}
+#endif				// USBDEV_PIO
+
+/*
+ * This routine is called to restart transmission of a packet.
+ * The endpoint's TSIZE must be set to the new packet's size,
+ * and DMA to the write FIFO needs to be restarted.
+ */
+static void
+kickstart_send_packet(endpoint_t * ep)
+{
+	u32 cs;
+	pkt_t *pkt = ep->inlist.head;
+
+	dbg(__FUNCTION__ ": pkt=%p", pkt);
+
+	if (!pkt)
+		return;
+
+	/*
+	 * The write fifo should already be drained if things are
+	 * working right, but flush it anyway just in case.
+	 */
+	flush_write_fifo(ep);
+	cs = inl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
+	cs |= (pkt->size << USBDEV_CS_TSIZE_BIT);
+	outl_sync(cs, ep->reg->ctrl_stat);
+#ifdef USBDEV_PIO
+	endpoint_fifo_write(ep);
+#else
+	disable_dma(ep->indma);
+	if (get_dma_active_buffer(ep->indma)) {
+		set_dma_count1(ep->indma, pkt->size);
+		set_dma_addr1(ep->indma, virt_to_phys(pkt->bufptr));
+		enable_dma_buffer1(ep->indma);	// reenable
+	} else {
+		set_dma_count0(ep->indma, pkt->size);
+		set_dma_addr0(ep->indma, virt_to_phys(pkt->bufptr));
+		enable_dma_buffer0(ep->indma);	// reenable
+	}
+	enable_dma(ep->indma);
+#endif
+}
+
+
+/*
+ * This routine is called when a packet in the inlist has been
+ * completed. Frees the completed packet and starts sending the
+ * next.
+ */
+static void
+send_packet_complete(endpoint_t * ep)
+{
+	if (ep->inlist.head)
+		dbg(__FUNCTION__ ": pkt=%p, ab=%d",
+		    ep->inlist.head, get_dma_active_buffer(ep->indma));
+
+	outl_sync(inl(ep->reg->ctrl_stat) & USBDEV_CS_STALL,
+		  ep->reg->ctrl_stat);
+	//disable_dma(ep->indma);
+	free_packet(ep, &ep->inlist);
+	// begin transmitting next packet in the inlist
+	if (ep->inlist.count)
+		kickstart_send_packet(ep);
+}
+
+
+/*
+ * Unlink and return a packet from the head of the given ep's packet
+ * outlist. It is the responsibility of the caller to free the packet.
+ * The receive complete interrupt adds packets to the tail of this list. 
+ */
+static pkt_t *
+receive_packet(endpoint_t * ep)
+{
+	pkt_t *pkt = unlink_packet(ep, &ep->outlist);
+	//dma_cache_inv((unsigned long)pkt->buf, pkt->size);
+	return pkt;
+}
+
+/*
+ * This routine is called to restart reception of a packet.
+ */
+static void
+kickstart_receive_packet(endpoint_t * ep)
+{
+	pkt_t *pkt;
+
+	// get and link a new packet for next reception
+	if (!(pkt = add_packet(ep, &ep->outlist, ep->max_pkt_size))) {
+		err(__FUNCTION__ ": could not alloc new packet");
+		return;
+	}
+
+	/*
+	 * The read fifo should already be drained if things are
+	 * working right, but flush it anyway just in case.
+	 */
+	flush_read_fifo(ep);
+#ifndef USBDEV_PIO
+	if (get_dma_active_buffer(ep->outdma)) {
+		set_dma_count1(ep->outdma, ep->max_pkt_size);
+		set_dma_addr1(ep->outdma, virt_to_phys(pkt->bufptr));
+		enable_dma_buffer1(ep->outdma);	// reenable
+	} else {
+		set_dma_count0(ep->outdma, ep->max_pkt_size);
+		set_dma_addr0(ep->outdma, virt_to_phys(pkt->bufptr));
+		enable_dma_buffer0(ep->outdma);	// reenable
+	}
+	enable_dma(ep->outdma);
+#endif
+}
+
+
+/*
+ * This routine is called when a packet in the outlist has been
+ * completed (received) and we need to prepare for a new packet
+ * to be received. Halts DMA and computes the packet size from the
+ * remaining DMA counter. Then prepares a new packet for reception
+ * and restarts DMA. FIXME: what if another packet comes in
+ * on top of the completed packet? Counter would be wrong.
+ */
+static void
+receive_packet_complete(endpoint_t * ep)
+{
+	pkt_t *pkt = ep->outlist.tail;
+
+	if (!pkt)
+		return;
+
+	disable_dma(ep->outdma);
+	pkt->size = ep->max_pkt_size - get_dma_residue(ep->outdma);
+#ifdef USBDEV_PIO
+	pkt->bufptr = pkt->buf;	// reset bufptr
+#endif
+	dbg(__FUNCTION__ ": size=%d", pkt->size);
+
+	kickstart_receive_packet(ep);
+}
+
+
+
+/*
+ * Add a new packet to the tail of the given ep's packet
+ * inlist. The transmit complete interrupt frees packets from
+ * the head of this list.
+ */
+static int
+send_packet(endpoint_t * ep, u8 * data, int data_len, int from_user)
+{
+	unsigned long flags;
+	pkt_list_t *list = &ep->inlist;
+	pkt_t *pkt;
+
+	if (!data || !data_len)
+		return 0;
+
+	if (!(pkt = alloc_packet(data_len))) {
+		err(__FUNCTION__ ": could not alloc new packet");
+		return -ENOMEM;
+	}
+
+	if (from_user)
+		copy_from_user(pkt->bufptr, data, data_len);
+	else
+		memcpy(pkt->bufptr, data, data_len);
+	au_sync();
+
+	//dma_cache_wback_inv((unsigned long)pkt->buf, data_len);
+
+	link_packet(ep, list, pkt);
+
+	spin_lock_irqsave(&ep->lock, flags);
+
+	dbg(__FUNCTION__ ": size=%d, list count=%d", pkt->size, list->count);
+
+	if (list->count == 1) {
+		/*
+		 * if the packet count is one, it means the list was empty,
+		 * and no more data will go out this ep until we kick-start
+		 * it again.
+		 */
+		kickstart_send_packet(ep);
+	}
+
+	spin_unlock_irqrestore(&ep->lock, flags);
+	return data_len;
+}
+
+
+// SETUP packet request parser
+static void
+process_setup (struct usb_serial* serial, devrequest* setup)
+{
+	int desc_len, strnum;
+
+	dbg(__FUNCTION__ ": req %d", setup->request);
+
+	switch (setup->request) {
+	case USB_REQ_SET_ADDRESS:
+		serial->address = le16_to_cpu(setup->value);
+		dbg(__FUNCTION__ ": our address=%d", serial->address);
+		if (serial->address > 127 || serial->state == CONFIGURED) {
+			// usb spec doesn't tell us what to do, so just go to
+			// default state
+			serial->state = DEFAULT;
+			serial->address = 0;
+		} else if (serial->address)
+			serial->state = ADDRESS;
+		else
+			serial->state = DEFAULT;
+		break;
+	case USB_REQ_GET_DESCRIPTOR:
+		desc_len = le16_to_cpu(setup->length);
+		switch (le16_to_cpu(setup->value) >> 8) {
+		case USB_DT_DEVICE:
+			// send device descriptor!
+			desc_len = desc_len > serial->dev_desc->bLength ?
+			    serial->dev_desc->bLength : desc_len;
+			dbg("sending device desc, size=%d", desc_len);
+			send_packet(&serial->ep_ctrl, (u8*)serial->dev_desc,
+				    desc_len, 0);
+			break;
+		case USB_DT_CONFIG:
+			// If the config descr index in low-byte of
+			// setup->value	is valid, send config descr,
+			// otherwise stall ep0.
+			if ((le16_to_cpu(setup->value) & 0xff) == 0) {
+				// send config descriptor!
+				if (desc_len <= USB_DT_CONFIG_SIZE) {
+					dbg("sending partial config desc, size=%d",
+					     desc_len);
+					send_packet(&serial->ep_ctrl,
+						    (u8*)serial->conf_desc,
+						    desc_len, 0);
+				} else {
+					u8 full_conf_desc[CONFIG_DESC_LEN];
+					int i, index = 0;
+					memcpy(&full_conf_desc[index],
+					       serial->conf_desc,
+					       USB_DT_CONFIG_SIZE);
+					index += USB_DT_CONFIG_SIZE;
+					memcpy(&full_conf_desc[index],
+					       serial->if_desc,
+					       USB_DT_INTERFACE_SIZE);
+					index += USB_DT_INTERFACE_SIZE;
+					for (i = 0; i < NUM_PORTS; i++) {
+						memcpy(&full_conf_desc[index],
+						       serial->port[i].ep_bulkin.desc,
+						       USB_DT_ENDPOINT_SIZE);
+						index += USB_DT_ENDPOINT_SIZE;
+						memcpy(&full_conf_desc[index],
+						       serial->port[i].ep_bulkout.desc,
+						       USB_DT_ENDPOINT_SIZE);
+						index += USB_DT_ENDPOINT_SIZE;
+					}
+					dbg("sending whole config desc, size=%d, our size=%d",
+					     desc_len, CONFIG_DESC_LEN);
+					desc_len = desc_len > CONFIG_DESC_LEN ?
+					    CONFIG_DESC_LEN : desc_len;
+					send_packet(&serial->ep_ctrl,
+						    full_conf_desc, desc_len, 0);
+				}
+			} else
+				endpoint_stall(&serial->ep_ctrl);
+			break;
+		case USB_DT_STRING:
+			// If the string descr index in low-byte of setup->value
+			// is valid, send string descr, otherwise stall ep0.
+			strnum = le16_to_cpu(setup->value) & 0xff;
+			if (strnum >= 0 && strnum < 6) {
+				struct usb_string_descriptor *desc =
+				    serial->str_desc[strnum];
+				desc_len = desc_len > desc->bLength ?
+					desc->bLength : desc_len;
+				dbg("sending string desc %d", strnum);
+				send_packet(&serial->ep_ctrl, (u8 *) desc,
+					    desc_len, 0);
+			} else
+				endpoint_stall(&serial->ep_ctrl);
+			break;
+		default:	// Invalid request
+			dbg("invalid get desc=%d, stalled",
+			    le16_to_cpu(setup->value) >> 8);
+			endpoint_stall(&serial->ep_ctrl);	// Stall endpoint 0
+			break;
+		}
+		break;
+	case USB_REQ_SET_DESCRIPTOR:
+		// FIXME: anything to set here?
+		break;
+	case USB_REQ_GET_INTERFACE:
+		// interface must be zero.
+		if ((le16_to_cpu(setup->index) & 0xff) ||
+		    serial->state == ADDRESS) {
+			// FIXME: respond with "request error". how?
+		} else if (serial->state == CONFIGURED) {
+			// send serial->alternate_setting
+			dbg("sending alt setting");
+			send_packet(&serial->ep_ctrl,
+				    &serial->alternate_setting, 1, 0);
+		}
+		break;
+	case USB_REQ_SET_INTERFACE:
+		if (serial->state == ADDRESS) {
+			// FIXME: respond with "request error". how?
+		} else if (serial->state == CONFIGURED) {
+			serial->interface = le16_to_cpu(setup->index) & 0xff;
+			serial->alternate_setting =
+			    le16_to_cpu(setup->value) & 0xff;
+			// interface and alternate_setting must be zero
+			if (serial->interface || serial->alternate_setting) {
+				// FIXME: respond with "request error". how?
+			}
+		}
+		break;
+	case USB_REQ_SET_CONFIGURATION:
+		// set active config to low-byte of serial.value
+		serial->configuration = le16_to_cpu(setup->value) & 0xff;
+		dbg("set config, config=%d", serial->configuration);
+		if (!serial->configuration && serial->state > DEFAULT)
+			serial->state = ADDRESS;
+		else if (serial->configuration == 1)
+			serial->state = CONFIGURED;
+		else {
+			// FIXME: "respond with request error" - how?
+		}
+		break;
+	case USB_REQ_GET_CONFIGURATION:
+		// send serial->configuration
+		dbg("sending config");
+		send_packet(&serial->ep_ctrl, &serial->configuration, 1, 0);
+		break;
+	case USB_REQ_GET_STATUS:
+		// FIXME: looks like the h/w handles this one
+		switch (setup->requesttype) {
+		case 0x80:	// Device
+			// FIXME: send device status
+			break;
+		case 0x81:	// Interface
+			// FIXME: send interface status
+			break;
+		case 0x82:	// End Point
+			// FIXME: send endpoint status
+			break;
+		default:	// Invalid Command
+			endpoint_stall(&serial->ep_ctrl);	// Stall End Point 0
+			break;
+		}
+		break;
+	case USB_REQ_CLEAR_FEATURE:
+		switch (setup->requesttype) {
+		case 0x00:	// Device
+			if ((le16_to_cpu(setup->value) & 0xff) == 1)
+				serial->remote_wakeup_en = 0;
+			else
+				endpoint_stall(&serial->ep_ctrl);
+			break;
+		case 0x02:	// End Point
+			if ((le16_to_cpu(setup->value) & 0xff) == 0) {
+				endpoint_t *ep =
+				    epnum_to_ep(serial,
+						    le16_to_cpu(setup->index) & 0xff);
+
+				endpoint_unstall(ep);
+				endpoint_reset_datatoggle(ep);
+			} else
+				endpoint_stall(&serial->ep_ctrl);
+			break;
+		}
+		break;
+	case USB_REQ_SET_FEATURE:
+		switch (setup->requesttype) {
+		case 0x00:	// Device
+			if ((le16_to_cpu(setup->value) & 0xff) == 1)
+				serial->remote_wakeup_en = 1;
+			else
+				endpoint_stall(&serial->ep_ctrl);
+			break;
+		case 0x02:	// End Point
+			if ((le16_to_cpu(setup->value) & 0xff) == 0) {
+				endpoint_t *ep =
+				    epnum_to_ep(serial,
+						    le16_to_cpu(setup->index) & 0xff);
+
+				endpoint_stall(ep);
+			} else
+				endpoint_stall(&serial->ep_ctrl);
+			break;
+		}
+		break;
+	default:
+		endpoint_stall(&serial->ep_ctrl);	// Stall End Point 0
+		break;
+	}
+}
+
+
+/*
+ * A complete packet (SETUP, DATA0, or DATA1) has been received
+ * on the given endpoint's fifo.
+ */
+static void
+process_complete (struct usb_serial* serial, int fifo_num)
+{
+	endpoint_t *ep = fifonum_to_ep(serial, fifo_num);
+	struct usb_serial_port *port = NULL;
+	pkt_t *pkt = 0;
+	u32 cs;
+
+	cs = inl(ep->reg->ctrl_stat);
+
+	switch (fifo_num) {
+	case 0:
+		spin_lock(&ep->lock);
+		// complete packet and prepare a new packet
+		receive_packet_complete(ep);
+
+		// Get it immediately from endpoint.
+		if (!(pkt = receive_packet(ep))) {
+			spin_unlock(&ep->lock);
+			return;
+		}
+	
+		// SETUP packet received ?
+		//if (cs & USBDEV_CS_SU) { FIXME: uncomment!
+			if (pkt->size == sizeof(devrequest)) {
+				devrequest setup;
+			if ((cs & (USBDEV_CS_NAK | USBDEV_CS_ACK)) ==
+			    USBDEV_CS_ACK)
+					dbg("got SETUP");
+				else
+					dbg("got NAK SETUP, cs=%08x", cs);
+			memcpy(&setup, pkt->bufptr, sizeof(devrequest));
+				process_setup(serial, &setup);
+			//} else  FIXME: uncomment!
+			//dbg(__FUNCTION__ ": wrong size SETUP received");
+		} else {
+			// DATAx packet received on endpoint 0
+			// FIXME: will need a state machine for control
+			// OUT transactions
+			dbg("got DATAx on EP0, size=%d, cs=%08x",
+			    pkt->size, cs);
+		}
+
+		spin_unlock(&ep->lock);
+		// we're done processing the packet, free it
+		kfree(pkt);
+		break;
+
+	case 4:
+	case 5:
+		port = fifonum_to_port(serial, fifo_num);
+		dbg("got DATAx on port %d, cs=%08x", port->number, cs);
+		spin_lock(&ep->lock);
+		receive_packet_complete(ep);
+		spin_unlock(&ep->lock);
+		// mark a bh to push this data up to the tty
+		queue_task(&port->receive_complete_tq, &tq_immediate);
+		mark_bh(IMMEDIATE_BH);
+		break;
+
+	default:
+		break;
+	}
+}
+
+
+
+// This ISR needs to ack both the complete and suspend events
+static void
+req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct usb_serial *serial = (struct usb_serial *) dev_id;
+	int i;
+	u32 status;
+
+	status = inl(USB_DEV_INT_STATUS);
+	outl_sync(status, USB_DEV_INT_STATUS);	// ack'em
+
+#ifdef USBDEV_PIO
+	for (i = 0; i < 6; i++) {
+		if (status & (1 << (USBDEV_INT_HF_BIT + i))) {
+			endpoint_t *ep = fifonum_to_ep(serial, i);
+
+			if (ep->desc->bEndpointAddress & USB_DIR_IN)
+				endpoint_fifo_write(ep);
+			else
+				endpoint_fifo_read(ep);
+		}
+	}
+#endif
+
+	for (i = 0; i < 6; i++) {
+		if (status & (1 << i))
+			process_complete(serial, i);
+	}
+}
+
+
+static void
+dma_done_ctrl(struct usb_serial* serial)
+{
+	endpoint_t *ep = &serial->ep_ctrl;
+	u32 cs0, buff_done;
+
+	spin_lock(&ep->lock);
+	cs0 = inl(ep->reg->ctrl_stat);
+
+	// first check packet transmit done
+	if ((buff_done = get_dma_buffer_done(ep->indma)) != 0) {
+		// transmitted a DATAx packet on control endpoint 0
+		// clear DMA done bit
+		if (buff_done == DMA_D0)
+			clear_dma_done0(ep->indma);
+		else
+			clear_dma_done1(ep->indma);
+
+		send_packet_complete(ep);
+	}
+
+	/*
+	 * Now check packet receive done. Shouldn't get these,
+	 * the receive packet complete intr should happen
+	 * before the DMA done intr occurs.
+	 */
+	if ((buff_done = get_dma_buffer_done(ep->outdma)) != 0) {
+		// clear DMA done bit
+		if (buff_done == DMA_D0)
+			clear_dma_done0(ep->outdma);
+		else
+			clear_dma_done1(ep->outdma);
+	}
+
+	spin_unlock(&ep->lock);
+}
+
+static void
+dma_done_port(struct usb_serial_port * port)
+{
+	endpoint_t *ep;
+	u32 buff_done;
+
+	// first check packet transmit done (bulk IN ep)
+	ep = &port->ep_bulkin;
+	spin_lock(&ep->lock);
+	if ((buff_done = get_dma_buffer_done(ep->indma)) != 0) {
+		// transmitted a DATAx packet on the port's bulk IN endpoint
+		// clear DMA done bit
+		if (buff_done == DMA_D0)
+			clear_dma_done0(ep->indma);
+		else
+			clear_dma_done1(ep->indma);
+
+		send_packet_complete(ep);
+		// mark a bh to wakeup any tty write system call on the port.
+		queue_task(&port->send_complete_tq, &tq_immediate);
+		mark_bh(IMMEDIATE_BH);
+	}
+	spin_unlock(&ep->lock);
+
+	/*
+	 * Now check packet receive done (bulk OUT ep). Shouldn't
+	 * get these, the receive packet complete intr should happen
+	 * before the DMA done intr occurs.
+	 */
+	ep = &port->ep_bulkout;
+	spin_lock(&ep->lock);
+	if ((buff_done = get_dma_buffer_done(ep->outdma)) != 0) {
+		// received a DATAx packet on the port's bulk OUT endpoint
+		// clear DMA done bit
+		if (buff_done == DMA_D0)
+			clear_dma_done0(ep->outdma);
+		else
+			clear_dma_done1(ep->outdma);
+	}
+	spin_unlock(&ep->lock);
+}
+
+
+// This ISR needs to handle dma done events for ALL endpoints!
+static void
+dma_done_intr (int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct usb_serial *serial = (struct usb_serial *) dev_id;
+	int i;
+
+	dma_done_ctrl(serial);
+	for (i = 0; i < NUM_PORTS; i++)
+		dma_done_port(&serial->port[i]);
+}
+
+
+
+/*****************************************************************************
+ * Here begins the tty driver interface functions
+ *****************************************************************************/
+
+static int serial_open(struct tty_struct *tty, struct file *filp)
+{
+	int portNumber;
+	struct usb_serial_port *port;
+	struct usb_serial *serial = &usbserial;
+	unsigned long flags;
+
+	/* initialize the pointer incase something fails */
+	tty->driver_data = NULL;
+
+	MOD_INC_USE_COUNT;
+
+	/* set up our port structure making the tty driver remember
+	   our port object, and us it */
+	portNumber = MINOR(tty->device) - serial->minor;
+	port = &serial->port[portNumber];
+	tty->driver_data = port;
+	port->tty = tty;
+
+	if (port_paranoia_check(port, __FUNCTION__))
+		return -ENODEV;
+
+	dbg(__FUNCTION__ " - port %d", port->number);
+
+	spin_lock_irqsave(&port->port_lock, flags);
+
+	++port->open_count;
+
+	if (!port->active) {
+		port->active = 1;
+
+		/*
+		 * force low_latency on so that our tty_push actually forces
+		 * the data through, otherwise it is scheduled, and with high
+		 * data rates (like with OHCI) data can get lost.
+		 */
+		port->tty->low_latency = 1;
+
+	}
+
+	spin_unlock_irqrestore(&port->port_lock, flags);
+
+	return 0;
+}
+
+
+static void serial_close(struct tty_struct *tty, struct file *filp)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+	unsigned long flags;
+
+	if (!serial)
+		return;
+
+	dbg(__FUNCTION__ " - port %d", port->number);
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not opened");
+		return;
+	}
+
+	spin_lock_irqsave(&port->port_lock, flags);
+
+	--port->open_count;
+
+	if (port->open_count <= 0) {
+		port->active = 0;
+		port->open_count = 0;
+	}
+
+	spin_unlock_irqrestore(&port->port_lock, flags);
+	MOD_DEC_USE_COUNT;
+}
+
+
+static int serial_write(struct tty_struct *tty, int from_user,
+			const unsigned char *buf, int count)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+	endpoint_t *ep = &port->ep_bulkin;
+
+	if (!serial)
+		return -ENODEV;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not opened");
+		return -EINVAL;
+	}
+
+	if (count == 0) {
+		dbg(__FUNCTION__ " - write request of 0 bytes");
+		return (0);
+	}
+
+	count = (count > ep->max_pkt_size) ? ep->max_pkt_size : count;
+	send_packet(ep, (u8 *) buf, count, from_user);
+
+	return (count);
+}
+
+
+static int serial_write_room(struct tty_struct *tty)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+	endpoint_t *ep = &port->ep_bulkin;
+
+	if (!serial)
+		return -ENODEV;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return -EINVAL;
+	}
+
+	return ep->max_pkt_size;
+}
+
+
+static int serial_chars_in_buffer(struct tty_struct *tty)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+	endpoint_t *ep = &port->ep_bulkin;
+	pkt_list_t *list = &ep->inlist;
+	pkt_t *scan;
+	unsigned long flags;
+	int chars = 0;
+
+	if (!serial)
+		return -ENODEV;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&ep->lock, flags);
+	for (scan = list->head; scan; scan = scan->next)
+		chars += scan->size;
+	spin_unlock_irqrestore(&ep->lock, flags);
+
+	return (chars);
+}
+
+
+static void serial_throttle(struct tty_struct *tty)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+
+	if (!serial)
+		return;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return;
+	}
+	// FIXME: anything to do?
+}
+
+
+static void serial_unthrottle(struct tty_struct *tty)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+
+	if (!serial)
+		return;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return;
+	}
+	// FIXME: anything to do?
+}
+
+
+static int serial_ioctl(struct tty_struct *tty, struct file *file,
+			unsigned int cmd, unsigned long arg)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+
+	if (!serial)
+		return -ENODEV;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return -ENODEV;
+	}
+	// FIXME: need any IOCTLs?
+
+	return -ENOIOCTLCMD;
+}
+
+
+static void serial_set_termios(struct tty_struct *tty, struct termios *old)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+
+	if (!serial)
+		return;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return;
+	}
+	// FIXME: anything to do?
+}
+
+
+static void serial_break(struct tty_struct *tty, int break_state)
+{
+	struct usb_serial_port *port =
+	    (struct usb_serial_port *) tty->driver_data;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+
+	if (!serial)
+		return;
+
+	if (!port->active) {
+		dbg(__FUNCTION__ " - port not open");
+		return;
+	}
+	// FIXME: anything to do?
+}
+
+
+static void port_send_complete(void *private)
+{
+	struct usb_serial_port *port = (struct usb_serial_port *) private;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+	struct tty_struct *tty;
+
+	dbg(__FUNCTION__ " - port %d", port->number);
+
+	if (!serial) {
+		return;
+	}
+
+	tty = port->tty;
+	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
+	    tty->ldisc.write_wakeup) {
+		dbg(__FUNCTION__ " - write wakeup call.");
+		(tty->ldisc.write_wakeup) (tty);
+	}
+
+	wake_up_interruptible(&tty->write_wait);
+}
+
+
+static void port_receive_complete(void *private)
+{
+	struct usb_serial_port *port = (struct usb_serial_port *) private;
+	struct usb_serial *serial = get_usb_serial(port, __FUNCTION__);
+	struct tty_struct *tty = port->tty;
+	pkt_t *pkt;
+	int i;
+
+	dbg(__FUNCTION__ " - port %d", port->number);
+
+	if (!serial) {
+		return;
+	}
+
+	if (!(pkt = receive_packet(&port->ep_bulkout)))
+		return;
+
+	for (i = 0; i < pkt->size; i++) {
+		/* if we insert more than TTY_FLIPBUF_SIZE characters,
+		   we drop them. */
+		if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
+			tty_flip_buffer_push(tty);
+		}
+		/* this doesn't actually push the data through
+		   unless tty->low_latency is set */
+		tty_insert_flip_char(tty, pkt->bufptr[i], 0);
+	}
+	tty_flip_buffer_push(tty);
+
+	// we're done processing the packet, free it
+	kfree(pkt);
+}
+
+
+static struct tty_driver serial_tty_driver = {
+	magic:TTY_DRIVER_MAGIC,
+	driver_name:"usbdev-serial",
+	name:"usb/ttsdev/%d",
+	major:SERIAL_TTY_MAJOR,
+	minor_start:0,
+	num:1,
+	type:TTY_DRIVER_TYPE_SERIAL,
+	subtype:SERIAL_TYPE_NORMAL,
+	flags:TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS,
+	refcount:&serial_refcount,
+	table:serial_tty,
+	termios:serial_termios,
+	termios_locked:serial_termios_locked,
+
+	open:serial_open,
+	close:serial_close,
+	write:serial_write,
+	write_room:serial_write_room,
+	ioctl:serial_ioctl,
+	set_termios:serial_set_termios,
+	throttle:serial_throttle,
+	unthrottle:serial_unthrottle,
+	break_ctl:serial_break,
+	chars_in_buffer:serial_chars_in_buffer,
+};
+
+
+void usbdev_serial_exit(void)
+{
+	endpoint_t *ep;
+	int i;
+
+	outl_sync(0, USB_DEV_INT_ENABLE);	// disable usb dev ints
+	outl_sync(0, USB_DEV_ENABLE);	// disable usb dev
+
+	// first free all control endpoint resources
+	ep = &usbserial.ep_ctrl;
+	free_irq(AU1000_USB_DEV_REQ_INT, &usbserial);
+	free_irq(AU1000_USB_DEV_SUS_INT, &usbserial);
+	free_irq(ep->inirq, &usbserial);
+	//free_irq(ep->outirq, &usbserial);
+	free_au1000_dma(ep->indma);
+	free_au1000_dma(ep->outdma);
+	endpoint_flush(ep);
+
+	// now free all port resources
+	for (i = 0; i < NUM_PORTS; i++) {
+		// free port's bulk IN endpoint resources
+		ep = &usbserial.port[i].ep_bulkin;
+		free_irq(ep->inirq, &usbserial);
+		free_au1000_dma(ep->indma);
+		endpoint_flush(ep);
+
+		// free port's bulk OUT endpoint resources
+		ep = &usbserial.port[i].ep_bulkout;
+		//free_irq(ep->outirq, &usbserial);
+		free_au1000_dma(ep->outdma);
+		endpoint_flush(ep);
+
+		tty_unregister_devfs(&serial_tty_driver, i);
+		info("usbdev serial converter now disconnected from ttyUSBdev%d",
+		     i);
+	}
+
+	kfree(usbserial.str_desc[0]);
+	tty_unregister_driver(&serial_tty_driver);
+}
+
+int usbdev_serial_init(void)
+{
+	struct usb_serial_port *port;
+	endpoint_t *ep;
+	void *str_desc_buf;
+	int str_desc_len;
+	int i;
+
+	/* register the tty driver */
+	serial_tty_driver.init_termios = tty_std_termios;
+	serial_tty_driver.init_termios.c_cflag =
+	    B9600 | CS8 | CREAD | HUPCL | CLOCAL;
+
+	if (tty_register_driver(&serial_tty_driver)) {
+		err(__FUNCTION__ ": failed to register tty driver");
+		return -1;
+	}
+
+	memset(&usbserial, 0, sizeof(struct usb_serial));
+	usbserial.minor = 0;
+
+	usbserial.state = DEFAULT;
+
+	usbserial.dev_desc = &dev_desc;
+	usbserial.if_desc = &if_desc;
+	usbserial.conf_desc = &config_desc;
+
+	/*
+	 * initialize the string descriptors
+	 */
+
+	/* alloc buffer big enough for all string descriptors */
+	str_desc_len = string_desc0.bLength;
+	for (i = 0; i < 5; i++)
+		str_desc_len += 2 + 2 * strlen(strings[i]);
+	str_desc_buf = (void *) kmalloc(str_desc_len, ALLOC_FLAGS);
+	if (!str_desc_buf) {
+		err(__FUNCTION__ ": failed to alloc string descriptors");
+		return -1;
+	}
+
+	usbserial.str_desc[0] = (struct usb_string_descriptor *)str_desc_buf;
+	memcpy(usbserial.str_desc[0], &string_desc0, string_desc0.bLength);
+	usbserial.str_desc[1] = (struct usb_string_descriptor *)
+	    (str_desc_buf + string_desc0.bLength);
+	for (i = 1; i < 6; i++) {
+		struct usb_string_descriptor *desc = usbserial.str_desc[i];
+		char *str = strings[i - 1];
+		int j, str_len = strlen(str);
+
+		desc->bLength = 2 + 2 * str_len;
+		desc->bDescriptorType = USB_DT_STRING;
+		for (j = 0; j < str_len; j++) {
+			desc->wData[j] = (u16) str[j];
+		}
+		if (i < 5)
+			usbserial.str_desc[i + 1] =
+			    (struct usb_string_descriptor *)
+			    ((u8 *) desc + desc->bLength);
+	}
+
+	// request the USB device transfer complete interrupt
+	if (request_irq(AU1000_USB_DEV_REQ_INT, req_sus_intr, SA_SHIRQ,
+			"USBdev req", &usbserial)) {
+		err("Can't get device request intr\n");
+		goto err_out;
+	}
+	// request the USB device suspend interrupt
+	if (request_irq(AU1000_USB_DEV_SUS_INT, req_sus_intr, SA_SHIRQ,
+			"USBdev sus", &usbserial)) {
+		err("Can't get device suspend intr\n");
+		goto err_out;
+	}
+
+	// Initialize default control endpoint
+	ep = &usbserial.ep_ctrl;
+	spin_lock_init(&ep->lock);
+	ep->desc = NULL;	// ep0 has no ep descriptor
+	ep->reg = &ep_reg[0];
+	ep->max_pkt_size = usbserial.dev_desc->bMaxPacketSize0;
+	ep->indma = ep->outdma = -1;
+	if ((ep->indma = request_au1000_dma(ep_dma_id[0].id,
+					    ep_dma_id[0].str)) < 0) {
+		err("Can't get %s DMA\n", ep_dma_id[0].str);
+		goto err_out;
+	}
+	if ((ep->outdma = request_au1000_dma(ep_dma_id[1].id,
+					     ep_dma_id[1].str)) < 0) {
+		err("Can't get %s DMA\n", ep_dma_id[1].str);
+		goto err_out;
+	}
+	ep->inirq = get_dma_done_irq(ep->indma);
+	ep->outirq = get_dma_done_irq(ep->outdma);
+	// allocate EP0's DMA done interrupts.
+	if (request_irq(ep->inirq, dma_done_intr, SA_INTERRUPT,
+			"USBdev ep0 IN", &usbserial)) {
+		err("Can't get ep0 IN dma done irq\n");
+		goto err_out;
+	}
+#if 0
+	if (request_irq(ep->outirq, dma_done_intr, SA_INTERRUPT,
+			"USBdev ep0 OUT", &usbserial)) {
+		err("Can't get ep0 OUT dma done irq\n");
+		goto err_out;
+	}
+#endif
+
+	/* initialize the devfs nodes for this device and let the user
+	   know what ports we are bound to */
+	for (i = 0; i < NUM_PORTS; ++i) {
+		tty_register_devfs(&serial_tty_driver, 0, i);
+		info("usbdev serial attached to ttyUSBdev%d (or devfs usb/ttsdev/%d)", 
+		     i, i);
+		port = &usbserial.port[i];
+		port->serial = &usbserial;
+		port->number = i;
+		port->send_complete_tq.routine = port_send_complete;
+		port->send_complete_tq.data = port;
+		port->receive_complete_tq.routine = port_receive_complete;
+		port->receive_complete_tq.data = port;
+		spin_lock_init(&port->port_lock);
+
+		// Initialize the port's bulk IN endpoint
+		ep = &port->ep_bulkin;
+		spin_lock_init(&ep->lock);
+		ep->desc = &ep_desc[NUM_PORTS * i];
+		ep->reg = &ep_reg[1 + NUM_PORTS * i];
+		ep->max_pkt_size = ep->desc->wMaxPacketSize;
+		ep->indma = ep->outdma = -1;
+		if ((ep->indma =
+		     request_au1000_dma(ep_dma_id[2+NUM_PORTS*i].id,
+				 ep_dma_id[2 + NUM_PORTS * i].str)) < 0) {
+			err("Can't get %s DMA\n",
+			    ep_dma_id[2 + NUM_PORTS * i].str);
+			goto err_out;
+		}
+		ep->inirq = get_dma_done_irq(ep->indma);
+		if (request_irq(ep->inirq, dma_done_intr, SA_INTERRUPT,
+				"USBdev bulk IN", &usbserial)) {
+			err("Can't get port %d bulk IN dma done irq\n", i);
+			goto err_out;
+		}
+		// Initialize the port's bulk OUT endpoint
+		ep = &port->ep_bulkout;
+		spin_lock_init(&ep->lock);
+		ep->desc = &ep_desc[NUM_PORTS * i + 1];
+		ep->reg = &ep_reg[1 + NUM_PORTS * i + 1];
+		ep->max_pkt_size = ep->desc->wMaxPacketSize;
+		ep->indma = ep->outdma = -1;
+		if ((ep->outdma =
+		     request_au1000_dma(ep_dma_id[2+NUM_PORTS*i + 1].id,
+					ep_dma_id[2+NUM_PORTS*i + 1].str)) < 0) {
+			err("Can't get %s DMA\n",
+			    ep_dma_id[2 + NUM_PORTS * i + 1].str);
+			goto err_out;
+		}
+		ep->outirq = get_dma_done_irq(ep->outdma);
+#if 0
+		if (request_irq(ep->outirq, dma_done_intr, SA_INTERRUPT,
+				"USBdev bulk OUT", &usbserial)) {
+			err("Can't get port %d bulk OUT dma done irq\n", i);
+			goto err_out;
+		}
+#endif
+	}
+
+	// enable device controller
+	outl_sync(0x0002, USB_DEV_ENABLE);
+	udelay(100);
+	outl_sync(0x0003, USB_DEV_ENABLE);
+	udelay(100);
+	for (i = 0; i < sizeof(au1000_config_table) / sizeof(u32); ++i)
+		outl_sync(au1000_config_table[i], USB_DEV_CONFIG);
+
+	// Flush the endpoint buffers and FIFOs
+	ep = &usbserial.ep_ctrl;
+	endpoint_flush(ep);
+	// start packet reception on control ep
+	kickstart_receive_packet(ep);
+
+	for (i = 0; i < NUM_PORTS; ++i) {
+		struct usb_serial_port *port = &usbserial.port[i];
+		endpoint_flush(&port->ep_bulkin);
+		endpoint_flush(&port->ep_bulkout);
+		// start packet reception on bulk OUT endpoint
+		kickstart_receive_packet(&port->ep_bulkout);
+	}
+
+	/*
+	 * Enable Receive FIFO Complete interrupts only. Transmit
+	 * complete is being handled by the DMA done interrupts.
+	 */
+	outl_sync(0x31, USB_DEV_INT_ENABLE);
+
+	return 0;
+
+      err_out:
+	usbdev_serial_exit();
+	return -1;
+}
+
+
+module_init(usbdev_serial_init);
+module_exit(usbdev_serial_exit);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1000/Makefile linux/arch/mips/au1000/pb1000/Makefile
--- linux.orig/arch/mips/au1000/pb1000/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/pb1000/Makefile	2002-08-01 06:42:36.000000000 +0000
@@ -15,10 +15,10 @@
 .S.o:
 	$(CC) $(CFLAGS) -c $< -o $*.o
 
-all: pb1000.o
-
 O_TARGET := pb1000.o
 
 obj-y := init.o setup.o
 
+obj-$(CONFIG_PCI) += pci_fixup.o pci_ops.o
+
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1000/init.c linux/arch/mips/au1000/pb1000/init.c
--- linux.orig/arch/mips/au1000/pb1000/init.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/pb1000/init.c	2002-08-01 06:42:36.000000000 +0000
@@ -27,6 +27,7 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
+
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/sched.h>
@@ -38,12 +39,21 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 
-extern int prom_argc;
-extern char **prom_argv, **prom_envp;
+int prom_argc;
+char **prom_argv, **prom_envp;
 extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+	return "Alchemy Pb1000";
+}
 
 int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
 {
+	unsigned char *memsize_str;
+	unsigned long memsize;
+
 	prom_argc = argc;
 	prom_argv = argv;
 	prom_envp = envp;
@@ -52,8 +62,12 @@
 	mips_machtype = MACH_PB1000;  
 
 	prom_init_cmdline();
-
-	add_memory_region(1, 64 << 20, BOOT_MEM_RAM);
-
+	memsize_str = prom_getenv("memsize");
+	if (!memsize_str) {
+		memsize = 0x04000000;
+	} else {
+		memsize = simple_strtol(memsize_str, NULL, 0);
+	}
+	add_memory_region(0, memsize, BOOT_MEM_RAM);
 	return 0;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1000/pci_fixup.c linux/arch/mips/au1000/pb1000/pci_fixup.c
--- linux.orig/arch/mips/au1000/pb1000/pci_fixup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1000/pci_fixup.c	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,90 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Board specific pci fixups.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/au1000.h>
+#include <asm/pb1000.h>
+
+#undef	DEBUG
+#ifdef 	DEBUG
+#define	DBG(x...)	printk(x)
+#else
+#define	DBG(x...)	
+#endif
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+	/* will need to fixup IO resources */
+}
+
+void __init pcibios_fixup(void)
+{
+	unsigned long pci_mem_start = (unsigned long) PCI_MEM_START;
+
+	writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
+	writel(0, SDRAM_MBAR);        // set mbar to 0
+	writel(0x2, SDRAM_CMD);       // enable memory accesses
+	au_sync_delay(1);
+
+	// set extend byte to mbar of ext slot
+	writel(((pci_mem_start >> 24) & 0xff) |
+	       (1 << 8 | 1 << 9 | 1 << 10 | 1 << 27), PCI_BRIDGE_CONFIG);
+	DBG("Set bridge config to %x\n", readl(PCI_BRIDGE_CONFIG));
+}
+
+void __init pcibios_fixup_irqs(void)
+{
+	unsigned int slot, func;
+	unsigned char pin;
+	struct pci_dev *dev;
+
+	pci_for_each_dev(dev) {
+		if (dev->bus->number != 0)
+		return;
+
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+		slot = PCI_SLOT(dev->devfn);
+		func = PCI_FUNC(dev->devfn);
+		dev->irq = AU1000_GPIO_15;
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+		DBG("slot %d func %d irq %d\n", slot, func, dev->irq);
+	}
+}
+unsigned int pcibios_assign_all_busses(void)
+{
+	return 0;
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1000/pci_ops.c linux/arch/mips/au1000/pb1000/pci_ops.c
--- linux.orig/arch/mips/au1000/pb1000/pci_ops.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1000/pci_ops.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,200 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	PB1000 specific pci support.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/au1000.h>
+#include <asm/pb1000.h>
+#include <asm/pci_channel.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#undef DEBUG
+#ifdef 	DEBUG
+#define	DBG(x...)	printk(x)
+#else
+#define	DBG(x...)	
+#endif
+
+static struct resource pci_io_resource = {
+	"pci IO space", 
+	PCI_IO_START,
+	PCI_IO_END,
+	IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+	"pci memory space", 
+	PCI_MEM_START,
+	PCI_MEM_END,
+	IORESOURCE_MEM
+};
+
+extern struct pci_ops pb1000_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+	{&pb1000_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 1},
+	{(struct pci_ops *) NULL, (struct resource *) NULL,
+	 (struct resource *) NULL, (int) NULL, (int) NULL}
+};
+
+
+/*
+ * "Bus 2" is really the first and only external slot on the pb1000.
+ * We'll call that bus 0, and limit the accesses to that single 
+ * external slot only. The SDRAM is already initialized in setup.c.
+ */
+static int config_access(unsigned char access_type, struct pci_dev *dev, 
+			 unsigned char where, u32 * data)
+{
+	unsigned char bus = dev->bus->number;
+	unsigned char dev_fn = dev->devfn;
+	unsigned long config;
+
+	if (((dev_fn >> 3) != 0) || (bus != 0)) {
+		*data = 0xffffffff;
+		return -1;
+	}
+
+	config = PCI_CONFIG_BASE | (where & ~0x3);
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		outl(*data, config);
+	} else {
+		*data = inl(config);
+	}
+	au_sync_udelay(1);
+
+	DBG("config_access: %d bus %d dev_fn %x at %x *data %x, conf %x\n", 
+			access_type, bus, dev_fn, where, *data, config);
+
+	DBG("bridge config reg: %x (%x)\n", inl(PCI_BRIDGE_CONFIG), *data);
+
+	if (inl(PCI_BRIDGE_CONFIG) & (1 << 16)) {
+		*data = 0xffffffff;
+		return -1;
+	} else {
+		return PCIBIOS_SUCCESSFUL;
+	}
+}
+
+
+static int read_config_byte(struct pci_dev *dev, int where, u8 * val)
+{
+	u32 data;
+	int ret;
+
+	ret = config_access(PCI_ACCESS_READ, dev, where, &data);
+	*val = data & 0xff;
+	return ret; 
+}
+
+
+static int read_config_word(struct pci_dev *dev, int where, u16 * val)
+{
+	u32 data;
+	int ret;
+
+	ret = config_access(PCI_ACCESS_READ, dev, where, &data);
+	*val = data & 0xffff;
+	return ret; 
+}
+
+static int read_config_dword(struct pci_dev *dev, int where, u32 * val)
+{
+	int ret;
+
+	ret = config_access(PCI_ACCESS_READ, dev, where, val);
+	return ret; 
+}
+
+
+static int write_config_byte(struct pci_dev *dev, int where, u8 val)
+{
+	u32 data = 0;
+       
+	if (config_access(PCI_ACCESS_READ, dev, where, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((where & 3) << 3))) |
+	       (val << ((where & 3) << 3));
+
+	if (config_access(PCI_ACCESS_WRITE, dev, where, &data))
+		return -1;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_word(struct pci_dev *dev, int where, u16 val)
+{
+        u32 data = 0;
+
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+       
+        if (config_access(PCI_ACCESS_READ, dev, where, &data))
+	       return -1;
+
+	data = (data & ~(0xffff << ((where & 3) << 3))) | 
+	       (val << ((where & 3) << 3));
+
+	if (config_access(PCI_ACCESS_WRITE, dev, where, &data))
+	       return -1;
+
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_dword(struct pci_dev *dev, int where, u32 val)
+{
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	if (config_access(PCI_ACCESS_WRITE, dev, where, &val))
+	       return -1;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops pb1000_pci_ops = {
+	read_config_byte,
+        read_config_word,
+	read_config_dword,
+	write_config_byte,
+	write_config_word,
+	write_config_dword
+};
+#endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1000/setup.c linux/arch/mips/au1000/pb1000/setup.c
--- linux.orig/arch/mips/au1000/pb1000/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/au1000/pb1000/setup.c	2002-08-01 06:42:38.000000000 +0000
@@ -1,7 +1,7 @@
 /*
  *
  * BRIEF MODULE DESCRIPTION
- *	Au1000-based board setup.
+ *	Alchemy Pb1000 board setup.
  *
  * Copyright 2000 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
@@ -31,45 +31,51 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
+#include <linux/mm.h>
 #include <linux/console.h>
 #include <linux/mc146818rtc.h>
+#include <linux/delay.h>
 
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
+#include <asm/keyboard.h>
 #include <asm/mipsregs.h>
 #include <asm/reboot.h>
+#include <asm/pgtable.h>
 #include <asm/au1000.h>
+#include <asm/pb1000.h>
+
+#ifdef CONFIG_USB_OHCI
+// Enable the workaround for the OHCI DoneHead
+// register corruption problem.
+#define CONFIG_AU1000_OHCI_FIX
+#endif
 
 #if defined(CONFIG_AU1000_SERIAL_CONSOLE)
 extern void console_setup(char *, int *);
 char serial_console[20];
 #endif
 
+#ifdef CONFIG_BLK_DEV_INITRD
+extern unsigned long initrd_start, initrd_end;
+extern void * __rd_start, * __rd_end;
+#endif
+
+#ifdef CONFIG_BLK_DEV_IDE
+extern struct ide_ops std_ide_ops;
+extern struct ide_ops *ide_ops;
+#endif
+
 void (*__wbflush) (void);
 extern struct rtc_ops no_rtc_ops;
 extern char * __init prom_getcmdline(void);
-extern void au1000_restart(void);
+extern void au1000_restart(char *);
 extern void au1000_halt(void);
 extern void au1000_power_off(void);
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
 
-struct {
-    struct resource ram;
-    struct resource io;
-    struct resource sram;
-    struct resource flash;
-    struct resource boot;
-    struct resource pcmcia;
-    struct resource lcd;
-} au1000_resources = {
-    { "RAM",           0,          0x3FFFFFF,  IORESOURCE_MEM },
-    { "I/O",           0x10000000, 0x119FFFFF                 },
-    { "SRAM",          0x1e000000, 0x1E03FFFF                 },
-    { "System Flash",  0x1F800000, 0x1FBFFFFF                 },
-    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 },
-    { "PCMCIA",        0x20000000, 0x27FFFFFF                 },
-    { "LCD",           0x60000000, 0x603FFFFF                 },
-};
 
 void au1000_wbflush(void)
 {
@@ -79,39 +85,223 @@
 void __init au1000_setup(void)
 {
 	char *argptr;
-
+	u32 pin_func, static_cfg0;
+	u32 sys_freqctrl, sys_clksrc;
+	u32 prid = read_32bit_cp0_register(CP0_PRID);
+	
 	argptr = prom_getcmdline();
 
+	/* Various early Au1000 Errata corrected by this */
+	set_cp0_config(1<<19); /* Config[OD] */
+
 #ifdef CONFIG_AU1000_SERIAL_CONSOLE
-	if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) {
+	if ((argptr = strstr(argptr, "console=")) == NULL) {
 		argptr = prom_getcmdline();
 		strcat(argptr, " console=ttyS0,115200");
 	}
 #endif	  
 
-	//set_cp0_status(ST0_FR,0);
 	rtc_ops = &no_rtc_ops;
         __wbflush = au1000_wbflush;
 	_machine_restart = au1000_restart;
 	_machine_halt = au1000_halt;
 	_machine_power_off = au1000_power_off;
 
-	/*
-	 * IO/MEM resources. 
-	 */
-	mips_io_port_base = KSEG1;
-	ioport_resource.start = au1000_resources.io.start;
-	ioport_resource.end = au1000_resources.lcd.end;
+	// IO/MEM resources. 
+	set_io_port_base(0);
+	ioport_resource.start = 0x10000000;
+	ioport_resource.end = 0xffffffff;
+	iomem_resource.start = 0x10000000;
+	iomem_resource.end = 0xffffffff;
 
 #ifdef CONFIG_BLK_DEV_INITRD
 	ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
+	initrd_start = (unsigned long)&__rd_start;
+	initrd_end = (unsigned long)&__rd_end;
 #endif
 
-	outl(PC_CNTRL_E0 | PC_CNTRL_EN0 | PC_CNTRL_EN0, PC_COUNTER_CNTRL);
-	while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T0S);
-	outl(0x8000-1, PC0_TRIM);
+	// set AUX clock to 12MHz * 8 = 96 MHz
+	outl(8, SYS_AUXPLL);
+	outl(0, SYS_PINSTATERD);
+	udelay(100);
+
+#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
+#ifdef CONFIG_USB_OHCI
+	if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) {
+	        char usb_args[80];
+		argptr = prom_getcmdline();
+		memset(usb_args, 0, sizeof(usb_args));
+		sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d",
+			USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT);
+		strcat(argptr, usb_args);
+	}
+#endif
 
-	printk("Alchemy Semi PB1000 Board\n");
-	printk("Au1000/PB1000 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
-}
+	/* zero and disable FREQ2 */
+	sys_freqctrl = inl(SYS_FREQCTRL0);
+	sys_freqctrl &= ~0xFFF00000;
+	outl(sys_freqctrl, SYS_FREQCTRL0);
+
+	/* zero and disable USBH/USBD clocks */
+	sys_clksrc = inl(SYS_CLKSRC);
+	sys_clksrc &= ~0x00007FE0;
+	outl(sys_clksrc, SYS_CLKSRC);
+
+	sys_freqctrl = inl(SYS_FREQCTRL0);
+	sys_freqctrl &= ~0xFFF00000;
+
+	sys_clksrc = inl(SYS_CLKSRC);
+	sys_clksrc &= ~0x00007FE0;
+
+	switch (prid & 0x000000FF)
+	{
+	case 0x00: /* DA */
+	case 0x01: /* HA */
+	case 0x02: /* HB */
+	/* CPU core freq to 48MHz to slow it way down... */
+	outl(4, SYS_CPUPLL);
+
+	/*
+	 * Setup 48MHz FREQ2 from CPUPLL for USB Host
+	 */
+	/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
+	sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
+	outl(sys_freqctrl, SYS_FREQCTRL0);
+
+	/* CPU core freq to 384MHz */
+	outl(0x20, SYS_CPUPLL);
+
+	printk("Au1000: 48MHz OHCI workaround enabled\n");
+		break;
+
+	default:  /* HC and newer */
+	// FREQ2 = aux/2 = 48 MHz
+	sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
+	outl(sys_freqctrl, SYS_FREQCTRL0);
+		break;
+	}
 
+	/*
+	 * Route 48MHz FREQ2 into USB Host and/or Device
+	 */
+#ifdef CONFIG_USB_OHCI
+	sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
+#endif
+#ifdef CONFIG_AU1000_USB_DEVICE
+	sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
+#endif
+	outl(sys_clksrc, SYS_CLKSRC);
+
+#ifdef CONFIG_USB_OHCI
+	// enable host controller and wait for reset done
+	outl(0x08, USB_HOST_CONFIG);
+	udelay(1000);
+	outl(0x0E, USB_HOST_CONFIG);
+	udelay(1000);
+	inl(USB_HOST_CONFIG); // throw away first read
+	while (!(inl(USB_HOST_CONFIG) & 0x10))
+		inl(USB_HOST_CONFIG);
+#endif
+	
+	// configure pins GPIO[14:9] as GPIO
+	pin_func = inl(SYS_PINFUNC) & (u32)(~0x8080);
+
+#ifndef CONFIG_AU1000_USB_DEVICE
+	// 2nd USB port is USB host
+	pin_func |= 0x8000;
+#endif
+	outl(pin_func, SYS_PINFUNC);
+	outl(0x2800, SYS_TRIOUTCLR);
+	outl(0x0030, SYS_OUTPUTCLR);
+#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
+
+	// make gpio 15 an input (for interrupt line) 
+	pin_func = inl(SYS_PINFUNC) & (u32)(~0x100);
+	// we don't need I2S, so make it available for GPIO[31:29] 
+	pin_func |= (1<<5);
+	outl(pin_func, SYS_PINFUNC);
+
+	outl(0x8000, SYS_TRIOUTCLR);
+	
+#ifdef CONFIG_FB
+	conswitchp = &dummy_con;
+#endif
+
+	static_cfg0 = inl(MEM_STCFG0) & (u32)(~0xc00);
+	outl(static_cfg0, MEM_STCFG0);
+
+	// configure RCE2* for LCD
+	outl(0x00000004, MEM_STCFG2);
+
+	// MEM_STTIME2
+	outl(0x09000000, MEM_STTIME2);
+
+	// Set 32-bit base address decoding for RCE2*
+	outl(0x10003ff0, MEM_STADDR2);
+
+	// PCI CPLD setup
+	// expand CE0 to cover PCI
+	outl(0x11803e40, MEM_STADDR1);
+
+	// burst visibility on 
+	outl(inl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
+
+	outl(0x83, MEM_STCFG1);         // ewait enabled, flash timing
+	outl(0x33030a10, MEM_STTIME1);   // slower timing for FPGA
+
+#ifdef CONFIG_FB_E1356
+	if ((argptr = strstr(argptr, "video=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " video=e1356fb:system:pb1000,mmunalign:1");
+	}
+#endif // CONFIG_FB_E1356
+
+
+#ifdef CONFIG_PCI
+	outl(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
+	outl(0, SDRAM_MBAR);        // set mbar to 0
+	outl(0x2, SDRAM_CMD);       // enable memory accesses
+	au_sync_delay(1);
+#endif
+
+#ifndef CONFIG_SERIAL_NONSTANDARD
+	/* don't touch the default serial console */
+	outl(0, UART0_ADDR + UART_CLK);
+#endif
+	outl(0, UART1_ADDR + UART_CLK);
+	outl(0, UART2_ADDR + UART_CLK);
+	outl(0, UART3_ADDR + UART_CLK);
+
+#ifdef CONFIG_BLK_DEV_IDE
+	{
+		argptr = prom_getcmdline();
+		strcat(argptr, " ide0=noprobe");
+	}
+	ide_ops = &std_ide_ops;
+#endif
+
+	// setup irda clocks
+	// aux clock, divide by 2, clock from 2/4 divider
+	writel(readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC);
+	pin_func = inl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD
+	outl(pin_func, SYS_PINFUNC);
+
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+	outl(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+	au_sync();
+	while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+	outl(0, SYS_TOYTRIM);
+
+	/* Enable Au1000 BCLK switching - note: sed1356 must not use
+	 * its BCLK (Au1000 LCLK) for any timings */
+	switch (prid & 0x000000FF)
+	{
+	case 0x00: /* DA */
+	case 0x01: /* HA */
+	case 0x02: /* HB */
+		break;
+	default:  /* HC and newer */
+		outl(0x00000060, 0xb190003c);
+		break;
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1500/Makefile linux/arch/mips/au1000/pb1500/Makefile
--- linux.orig/arch/mips/au1000/pb1500/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1500/Makefile	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,24 @@
+#
+#  Copyright 2000,2001 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc.
+#     	ppopov@mvista.com or source@mvista.com
+#
+# Makefile for the Alchemy Semiconductor Pb1500 board.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+O_TARGET := pb1500.o
+
+obj-y := init.o setup.o
+
+obj-$(CONFIG_PCI) += pci_fixup.o pci_ops.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1500/init.c linux/arch/mips/au1000/pb1500/init.c
--- linux.orig/arch/mips/au1000/pb1500/init.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1500/init.c	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,73 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	PB1500 board setup
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+	return "Alchemy Pb1500";
+}
+
+int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
+{
+	unsigned char *memsize_str;
+	unsigned long memsize;
+
+	prom_argc = argc;
+	prom_argv = argv;
+	prom_envp = envp;
+
+	mips_machgroup = MACH_GROUP_ALCHEMY;
+	mips_machtype = MACH_PB1500;  
+
+	prom_init_cmdline();
+	memsize_str = prom_getenv("memsize");
+	if (!memsize_str) {
+		memsize = 0x04000000;
+	} else {
+		memsize = simple_strtol(memsize_str, NULL, 0);
+	}
+	add_memory_region(0, memsize, BOOT_MEM_RAM);
+	return 0;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1500/pci_fixup.c linux/arch/mips/au1000/pb1500/pci_fixup.c
--- linux.orig/arch/mips/au1000/pb1500/pci_fixup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1500/pci_fixup.c	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,119 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Board specific pci fixups.
+ *
+ * Copyright 2001,2002 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/au1000.h>
+#include <asm/pb1500.h>
+
+#undef	DEBUG
+#ifdef 	DEBUG
+#define	DBG(x...)	printk(x)
+#else
+#define	DBG(x...)	
+#endif
+
+static void fixup_resource(int r_num, struct pci_dev *dev) ;
+static unsigned long virt_io_addr;
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+	/* will need to fixup IO resources */
+}
+
+void __init pcibios_fixup(void)
+{
+	int i;
+	struct pci_dev *dev;
+	
+	virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, 
+			Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
+
+	if (!virt_io_addr) {
+		printk(KERN_ERR "Unable to ioremap pci space\n");
+		return;
+	}
+
+	pci_for_each_dev(dev) {
+		for (i=0; i < DEVICE_COUNT_RESOURCE; i++) {
+			if (dev->resource[i].start) {
+				fixup_resource(i, dev);
+			}
+		}
+	}
+}
+
+void __init pcibios_fixup_irqs(void)
+{
+	unsigned int slot, func;
+	unsigned char pin;
+	struct pci_dev *dev;
+
+	pci_for_each_dev(dev) {
+		if (dev->bus->number != 0)
+			return;
+
+		dev->irq = 0xff;
+		slot = PCI_SLOT(dev->devfn);
+		switch (slot) {
+			case 12:
+			case 13:
+				dev->irq = AU1000_PCI_INTA;
+				break;
+
+		}
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+		DBG("slot %d irq %d\n", slot, dev->irq);
+	}
+}
+unsigned int pcibios_assign_all_busses(void)
+{
+	return 0;
+}
+
+static void fixup_resource(int r_num, struct pci_dev *dev) 
+{
+	unsigned long start, size, new_start;
+
+	if (dev->resource[r_num].flags & IORESOURCE_IO) {
+		start = dev->resource[r_num].start;
+		size = dev->resource[r_num].end - start;
+		new_start = virt_io_addr + (start - Au1500_PCI_IO_START);
+		dev->resource[r_num].start = new_start;
+		dev->resource[r_num].end = new_start + size;
+	}
+}
+
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1500/pci_ops.c linux/arch/mips/au1000/pb1500/pci_ops.c
--- linux.orig/arch/mips/au1000/pb1500/pci_ops.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1500/pci_ops.c	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,241 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Pb1500 specific pci support.
+ *
+ * Copyright 2001,2002 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/au1000.h>
+#include <asm/pb1500.h>
+#include <asm/pci_channel.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#undef DEBUG
+#ifdef 	DEBUG
+#define	DBG(x...)	printk(x)
+#else
+#define	DBG(x...)	
+#endif
+
+/* TBD */
+static struct resource pci_io_resource = {
+	"pci IO space", 
+	Au1500_PCI_IO_START,
+	Au1500_PCI_IO_END,
+	IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+	"pci memory space", 
+	Au1500_PCI_MEM_START,
+	Au1500_PCI_MEM_END,
+	IORESOURCE_MEM
+};
+
+extern struct pci_ops pb1500_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+	{&pb1500_pci_ops, &pci_io_resource, &pci_mem_resource, (10<<3),(16<<3)},
+	{(struct pci_ops *) NULL, (struct resource *) NULL,
+	 (struct resource *) NULL, (int) NULL, (int) NULL}
+};
+
+static unsigned long cfg_addr;
+static int config_access(unsigned char access_type, struct pci_dev *dev, 
+			 unsigned char where, u32 * data)
+{
+	unsigned char bus = dev->bus->number;
+	unsigned int dev_fn = dev->devfn;
+	unsigned int device, function;
+	unsigned long config, status;
+	static int first = 1;
+
+	/* 
+ 	 * 7:3 = slot
+ 	 * 2:0 = function
+	 */
+
+	if (bus != 0) {
+		*data = 0xffffffff;
+		return -1;
+	}
+
+	if (first) {
+		first = 0;
+		cfg_addr = ioremap(Au1500_EXT_CFG, 0x10000000);
+		if (!cfg_addr) 
+			printk (KERN_ERR "PCI unable to ioremap cfg space\n");
+	}
+
+	device = (dev_fn >> 3) & 0x1f;
+	function = dev_fn & 0x7;
+
+#if 1
+	//if (!cfg_addr || (device < 10) || (device > 16)) {
+	if (!cfg_addr || (device > 16)) {
+		*data = 0xffffffff;
+		return -1;
+	}
+#endif
+
+	writel(((0x2000 << 16) | (readl(Au1500_PCI_STATCMD) & 0xffff)),
+			Au1500_PCI_STATCMD);
+	//writel(readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG);
+	au_sync_udelay(1);
+
+	/* setup the lower 31 bits of the 36 bit address */
+	config = cfg_addr | 
+		((1<<device)<<11) | (function << 8) | (where & ~0x3);
+
+#if 0
+	printk("cfg access: config %x, dev_fn %x, device %x function %x\n",
+			config, dev_fn, device, function);
+#endif
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		writel(*data, config);
+	} else {
+		*data = readl(config);
+	}
+	au_sync_udelay(1);
+
+	DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n", 
+			access_type, bus, device, where, *data, config);
+
+	/* check master abort */
+	status = readl(Au1500_PCI_STATCMD);
+	if (status & (1<<29)) { 
+		*data = 0xffffffff;
+		return -1;
+	} else if ((status >> 28) & 0xf) {
+		DBG("PCI ERR detected: status %x\n", status);
+		*data = 0xffffffff;
+		return -1;
+	}
+	else {
+		return PCIBIOS_SUCCESSFUL;
+	}
+}
+
+
+static int read_config_byte(struct pci_dev *dev, int where, u8 * val)
+{
+	u32 data;
+	int ret;
+
+	ret = config_access(PCI_ACCESS_READ, dev, where, &data);
+        if (where & 1) data >>= 8;
+        if (where & 2) data >>= 16;
+        *val = data & 0xff;
+	return ret; 
+}
+
+
+static int read_config_word(struct pci_dev *dev, int where, u16 * val)
+{
+	u32 data;
+	int ret;
+
+	ret = config_access(PCI_ACCESS_READ, dev, where, &data);
+        if (where & 2) data >>= 16;
+        *val = data & 0xffff;
+	return ret; 
+}
+
+static int read_config_dword(struct pci_dev *dev, int where, u32 * val)
+{
+	int ret;
+
+	ret = config_access(PCI_ACCESS_READ, dev, where, val);
+	return ret; 
+}
+
+
+static int write_config_byte(struct pci_dev *dev, int where, u8 val)
+{
+	u32 data = 0;
+       
+	if (config_access(PCI_ACCESS_READ, dev, where, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((where & 3) << 3))) |
+	       (val << ((where & 3) << 3));
+
+	if (config_access(PCI_ACCESS_WRITE, dev, where, &data))
+		return -1;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_word(struct pci_dev *dev, int where, u16 val)
+{
+        u32 data = 0;
+
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+       
+        if (config_access(PCI_ACCESS_READ, dev, where, &data))
+	       return -1;
+
+	data = (data & ~(0xffff << ((where & 3) << 3))) | 
+	       (val << ((where & 3) << 3));
+
+	if (config_access(PCI_ACCESS_WRITE, dev, where, &data))
+	       return -1;
+
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_dword(struct pci_dev *dev, int where, u32 val)
+{
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	if (config_access(PCI_ACCESS_WRITE, dev, where, &val))
+	       return -1;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops pb1500_pci_ops = {
+	read_config_byte,
+        read_config_word,
+	read_config_dword,
+	write_config_byte,
+	write_config_word,
+	write_config_dword
+};
+#endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/au1000/pb1500/setup.c linux/arch/mips/au1000/pb1500/setup.c
--- linux.orig/arch/mips/au1000/pb1500/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/au1000/pb1500/setup.c	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,256 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Alchemy Pb1000 board setup.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/mc146818rtc.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/keyboard.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/au1000.h>
+#include <asm/pb1500.h>
+
+#ifdef CONFIG_USB_OHCI
+// Enable the workaround for the OHCI DoneHead
+// register corruption problem.
+#define CONFIG_AU1000_OHCI_FIX
+#endif
+
+#if defined(CONFIG_AU1000_SERIAL_CONSOLE)
+extern void console_setup(char *, int *);
+char serial_console[20];
+#endif
+
+#ifdef CONFIG_BLK_DEV_INITRD
+extern unsigned long initrd_start, initrd_end;
+extern void * __rd_start, * __rd_end;
+#endif
+
+#ifdef CONFIG_BLK_DEV_IDE
+extern struct ide_ops std_ide_ops;
+extern struct ide_ops *ide_ops;
+#endif
+
+#ifdef CONFIG_RTC
+extern struct rtc_ops pb1500_rtc_ops;
+#endif
+
+void (*__wbflush) (void);
+extern char * __init prom_getcmdline(void);
+extern void au1000_restart(char *);
+extern void au1000_halt(void);
+extern void au1000_power_off(void);
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+
+
+void au1500_wbflush(void)
+{
+	__asm__ volatile ("sync");
+}
+
+void __init au1500_setup(void)
+{
+	char *argptr;
+	u32 pin_func, static_cfg0;
+	u32 sys_freqctrl, sys_clksrc;
+	
+	argptr = prom_getcmdline();
+
+	/* NOTE: The memory map is established by YAMON 2.08+ */
+
+	/* Various early Au1500 Errata corrected by this */
+	set_cp0_config(1<<19); /* Config[OD] */
+
+#ifdef CONFIG_AU1000_SERIAL_CONSOLE
+	if ((argptr = strstr(argptr, "console=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " console=ttyS0,115200");
+	}
+#endif	  
+
+#ifdef CONFIG_SOUND_AU1000
+	strcat(argptr, " au1000_audio=vra");
+	argptr = prom_getcmdline();
+#endif
+
+        __wbflush = au1500_wbflush;
+	_machine_restart = au1000_restart;
+	_machine_halt = au1000_halt;
+	_machine_power_off = au1000_power_off;
+
+	// IO/MEM resources. 
+	set_io_port_base(0);
+	ioport_resource.start = 0x10000000;
+	ioport_resource.end = 0xffffffff;
+	iomem_resource.start = 0x10000000;
+	iomem_resource.end = 0xffffffff;
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
+	initrd_start = (unsigned long)&__rd_start;
+	initrd_end = (unsigned long)&__rd_end;
+#endif
+
+	// set AUX clock to 12MHz * 8 = 96 MHz
+	writel(8, SYS_AUXPLL);
+	outl(0, SYS_PINSTATERD);
+	udelay(100);
+
+#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
+#ifdef CONFIG_USB_OHCI
+	if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) {
+	        char usb_args[80];
+		argptr = prom_getcmdline();
+		memset(usb_args, 0, sizeof(usb_args));
+		sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d",
+			USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT);
+		strcat(argptr, usb_args);
+	}
+#endif
+
+	/* zero and disable FREQ2 */
+	sys_freqctrl = readl(SYS_FREQCTRL0);
+	sys_freqctrl &= ~0xFFF00000;
+	writel(sys_freqctrl, SYS_FREQCTRL0);
+
+	/* zero and disable USBH/USBD clocks */
+	sys_clksrc = readl(SYS_CLKSRC);
+	sys_clksrc &= ~0x00007FE0;
+	writel(sys_clksrc, SYS_CLKSRC);
+
+	sys_freqctrl = readl(SYS_FREQCTRL0);
+	sys_freqctrl &= ~0xFFF00000;
+
+	sys_clksrc = readl(SYS_CLKSRC);
+	sys_clksrc &= ~0x00007FE0;
+
+	// FREQ2 = aux/2 = 48 MHz
+	sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
+	writel(sys_freqctrl, SYS_FREQCTRL0);
+
+	/*
+	 * Route 48MHz FREQ2 into USB Host and/or Device
+	 */
+#ifdef CONFIG_USB_OHCI
+	sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
+#endif
+#ifdef CONFIG_AU1000_USB_DEVICE
+	sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
+#endif
+	writel(sys_clksrc, SYS_CLKSRC);
+
+
+	pin_func = readl(SYS_PINFUNC) & (u32)(~0x8000);
+#ifndef CONFIG_AU1000_USB_DEVICE
+	// 2nd USB port is USB host
+	pin_func |= 0x8000;
+#endif
+	writel(pin_func, SYS_PINFUNC);
+#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
+
+
+#ifdef CONFIG_USB_OHCI
+	// enable host controller and wait for reset done
+	writel(0x08, USB_HOST_CONFIG);
+	udelay(1000);
+	writel(0x0c, USB_HOST_CONFIG);
+	udelay(1000);
+	readl(USB_HOST_CONFIG);
+	while (!(readl(USB_HOST_CONFIG) & 0x10))
+	    ;
+	readl(USB_HOST_CONFIG);
+#endif
+	
+#ifdef CONFIG_FB
+	conswitchp = &dummy_con;
+#endif
+
+#ifdef CONFIG_FB_E1356
+	if ((argptr = strstr(argptr, "video=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " video=e1356fb:system:pb1500,mmunalign:1");
+	}
+#endif // CONFIG_FB_E1356
+
+#ifndef CONFIG_SERIAL_NONSTANDARD
+	/* don't touch the default serial console */
+	writel(0, UART0_ADDR + UART_CLK);
+#endif
+	writel(0, UART3_ADDR + UART_CLK);
+
+#ifdef CONFIG_BLK_DEV_IDE
+	ide_ops = &std_ide_ops;
+#endif
+
+#ifdef CONFIG_PCI
+	// Setup PCI bus controller
+	writel(0, Au1500_PCI_CMEM);
+	writel(0x00003fff, Au1500_CFG_BASE);
+	writel(0xf, Au1500_PCI_CFG);
+	writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
+	writel(0, Au1500_PCI_MWBASE_REV_CCL);
+	writel(0x02a00356, Au1500_PCI_STATCMD);
+	writel(0x00003c04, Au1500_PCI_HDRTYPE);	
+	writel(0x00000008, Au1500_PCI_MBAR);
+	au_sync();
+#endif
+
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+	writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+	au_sync();
+	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+	outl(0, SYS_TOYTRIM);
+
+	/* Enable BCLK switching */
+	writel(0x00000060, 0xb190003c);
+
+#ifdef CONFIG_RTC
+	rtc_ops = &pb1500_rtc_ops;
+	// Enable the RTC if not already enabled 
+	if (!(readb(0xac000028) & 0x20)) {
+		writeb(readb(0xac000028) | 0x20, 0xac000028);
+	}
+	// Put the clock in BCD mode
+	if (readb(0xac00002C) & 0x4) { /* reg B */
+		writeb(readb(0xac00002c) & ~0x4, 0xac00002c);
+		au_sync();
+	}
+#endif
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/baget.c linux/arch/mips/baget/baget.c
--- linux.orig/arch/mips/baget/baget.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/baget/baget.c	2002-08-01 06:42:46.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: baget.c,v 1.1 1999/01/17 03:49:37 ralf Exp $
- *
+/*
  * baget.c: Baget low level stuff
  *
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/bagetIRQ.S linux/arch/mips/baget/bagetIRQ.S
--- linux.orig/arch/mips/baget/bagetIRQ.S	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/baget/bagetIRQ.S	2002-08-01 06:42:36.000000000 +0000
@@ -1,9 +1,8 @@
-/* $Id: bagetIRQ.S,v 1.1 1999/01/17 03:49:37 ralf Exp $
+/*
  * bagetIRQ.S: Interrupt exception dispatch code for Baget/MIPS
  *
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
  */
-
 #include <asm/asm.h>
 #include <asm/mipsregs.h>
 #include <asm/regdef.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/balo.c linux/arch/mips/baget/balo.c
--- linux.orig/arch/mips/baget/balo.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/baget/balo.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,9 +1,7 @@
-/* $Id$
- *
+/*
  * balo.c: BAget LOader
  *
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
- *
  */
 #include <linux/kernel.h>
 #include <asm/system.h>
@@ -42,27 +40,29 @@
 
 static __inline__ void reset_and_jump(int start, int mem_upper)
 {
+	unsigned long tmp;
+
 	__asm__ __volatile__(
                 ".set\tnoreorder\n\t"
                 ".set\tnoat\n\t"
-                "mfc0\t$1,$12\n\t"
+                "mfc0\t$1, $12\n\t"
                 "nop\n\t"
                 "nop\n\t"
                 "nop\n\t"
-                "ori\t$1,$1,0xff00\n\t"
-                "xori\t$1,$1,0xff00\n\t"
-                "mtc0\t$1,$12\n\t"
+                "ori\t$1, $1, 0xff00\n\t"
+                "xori\t$1, $1, 0xff00\n\t"
+                "mtc0\t$1, $12\n\t"
                 "nop\n\t"
                 "nop\n\t"
                 "nop\n\t"
-		"move\t$4,%1\n\t"
-		"jr\t%0\n\t"
+		"move\t%0, %2\n\t"
+		"jr\t%1\n\t"
 		"nop\n\t"
                 ".set\tat\n\t"
                 ".set\treorder"           
-                : /* no outputs */
-                :"Ir" (start), "Ir" (mem_upper)
-                :"$1", "$4", "memory");
+                : "=&r" (tmp)
+                : "Ir" (start), "Ir" (mem_upper)
+                : "memory");
 }
 
 static void start_kernel(void)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/balo_supp.S linux/arch/mips/baget/balo_supp.S
--- linux.orig/arch/mips/baget/balo_supp.S	2000-02-28 15:18:20.000000000 +0000
+++ linux/arch/mips/baget/balo_supp.S	2002-08-01 06:42:28.000000000 +0000
@@ -1,9 +1,8 @@
-/* $Id: balo_supp.S,v 1.1 1999/01/17 03:49:38 ralf Exp $
+/*
  * balo_supp.S: BAget Loader supplement
  *
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
  */
-
 #include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/irq.c linux/arch/mips/baget/irq.c
--- linux.orig/arch/mips/baget/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/baget/irq.c	2002-08-01 06:42:46.000000000 +0000
@@ -27,7 +27,7 @@
 
 #include <asm/baget/baget.h>
 
-unsigned long spurious_count = 0;
+volatile unsigned long irq_err_count;
 
 /*
  * This table is a correspondence between IRQ numbers and CPU PILs
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/print.c linux/arch/mips/baget/print.c
--- linux.orig/arch/mips/baget/print.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/baget/print.c	2002-08-01 06:42:44.000000000 +0000
@@ -1,9 +1,7 @@
-/* $Id: print.c,v 1.1 1999/01/17 03:49:38 ralf Exp $
- *
+/*
  * print.c: Simple print fascility
  *
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
- *
  */
 #include <stdarg.h>
 #include <linux/kernel.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/prom/init.c linux/arch/mips/baget/prom/init.c
--- linux.orig/arch/mips/baget/prom/init.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/baget/prom/init.c	2002-08-01 06:42:38.000000000 +0000
@@ -7,7 +7,13 @@
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
+
+const char *get_system_type(void)
+{
+	/* Should probably return one of "BT23-201", "BT23-202" */
+	return "Baget";
+}
 
 void __init prom_init(unsigned int mem_upper)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/setup.c linux/arch/mips/baget/setup.c
--- linux.orig/arch/mips/baget/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/baget/setup.c	2002-08-01 06:42:28.000000000 +0000
@@ -1,9 +1,7 @@
-/* $Id: setup.c,v 1.4 1999/10/09 00:00:57 ralf Exp $
- *
+/*
  * setup.c: Baget/MIPS specific setup, including init of the feature struct.
  *
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
- *
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/baget/vacserial.c linux/arch/mips/baget/vacserial.c
--- linux.orig/arch/mips/baget/vacserial.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/baget/vacserial.c	2002-08-01 06:42:31.000000000 +0000
@@ -1785,7 +1785,7 @@
 		schedule_timeout(char_time);
 		if (signal_pending(current))
 			break;
-		if (timeout && ((orig_jiffies + timeout) < jiffies))
+		if (timeout && time_after(jiffies, orig_jiffies + timeout))
 			break;
 	}
 	current->state = TASK_RUNNING;
@@ -2406,9 +2406,9 @@
 	callout_driver.proc_entry = 0;
 
 	if (tty_register_driver(&serial_driver))
-		panic("Couldn't register serial driver\n");
+		panic("Couldn't register serial driver");
 	if (tty_register_driver(&callout_driver))
-		panic("Couldn't register callout driver\n");
+		panic("Couldn't register callout driver");
 	
 	for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
 		state->magic = SSTATE_MAGIC;
@@ -2622,43 +2622,6 @@
 	serial_outp(&scr_info, VAC_UART_INT_MASK, ier);
 }
 
-/*
- *	Receive character from the serial port
- */
-static int serial_console_wait_key(struct console *co)
-{
-	struct serial_state *ser;
-	int ier;
-	int lsr;
-	int c;
-	struct async_struct scr_info; /* serial_{in,out} because HUB6 */
-
-	ser = rs_table + co->index;
-	scr_info.magic = SERIAL_MAGIC;
-	scr_info.port = ser->port;
-	scr_info.flags = ser->flags;
-
-	/*
-	 *	First save the IER then disable the interrupts so
-	 *	that the real driver for the port does not get the
-	 *	character.
-	 */
-	ier = serial_inp(&scr_info, VAC_UART_INT_MASK);
-	serial_outp(&scr_info, VAC_UART_INT_MASK, 0x00);
-
-	do {
-		lsr = serial_inp(&scr_info, VAC_UART_INT_STATUS);
-	} while (!(lsr & VAC_UART_STATUS_RX_READY));
-	c = serial_inp(&scr_info, VAC_UART_RX);
-
-	/*
-	 *	Restore the interrupts
-	 */
-	serial_outp(&scr_info, VAC_UART_INT_MASK, ier);
-
-	return c;
-}
-
 static kdev_t serial_console_device(struct console *c)
 {
 	return MKDEV(TTY_MAJOR, 64 + c->index);
@@ -2812,7 +2775,6 @@
 	name:		"ttyS",
 	write:		serial_console_write,
 	device:		serial_console_device,
-	wait_key:	serial_console_wait_key,
 	setup:		serial_console_setup,
 	flags:		CON_PRINTBUFFER,
 	index:		-1,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/boot/Makefile linux/arch/mips/boot/Makefile
--- linux.orig/arch/mips/boot/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/boot/Makefile	2002-08-01 06:42:35.000000000 +0000
@@ -6,10 +6,7 @@
 # Copyright (C) 1995, 1998, 2001 by Ralf Baechle
 #
 
-.S.s:
-	$(CPP) $(CFLAGS) $< -o $*.s
-.S.o:
-	$(CC) $(CFLAGS) -c $< -o $*.o
+USE_STANDARD_AS_RULE := true
 
 OBJS  = milo.o a.out.o
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/boot/addinitrd.c linux/arch/mips/boot/addinitrd.c
--- linux.orig/arch/mips/boot/addinitrd.c	1999-06-26 00:40:12.000000000 +0000
+++ linux/arch/mips/boot/addinitrd.c	2002-08-01 06:42:34.000000000 +0000
@@ -8,6 +8,8 @@
 #include <sys/stat.h>
 #include <fcntl.h>
 #include <unistd.h>
+#include <stdio.h>
+#include <netinet/in.h>
 
 #include "ecoff.h"
 
@@ -44,7 +46,7 @@
 	char buf[1024];
 	unsigned long loadaddr;
 	unsigned long initrd_header[2];
-	int i;
+	int i,cnt;
 	int swab = 0;
 
 	if (argc != 4) {
@@ -60,7 +62,6 @@
 		die ("read aout header");
 	if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
 		die ("read section headers");
-
 	/*
 	 * check whether the file is good for us
 	 */
@@ -98,9 +99,20 @@
 		die ("write aout header");
 	if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
 		die ("write section headers");
-	while ((i = read (fd_vmlinux, buf, sizeof buf)) > 0)
+	/* skip padding */
+	if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
+		die ("lseek vmlinux");
+	if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
+		die ("lseek outfile");
+	/* copy text segment */
+	cnt = SWAB(eaout.tsize);
+	while (cnt) {
+		if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
+			die ("read vmlinux");
 		if (write (fd_outfile, buf, i) != i)
 			die ("write vmlinux");
+		cnt -= i;
+	}
 	if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
 		die ("write initrd header");
 	while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/boot/elf2ecoff.c linux/arch/mips/boot/elf2ecoff.c
--- linux.orig/arch/mips/boot/elf2ecoff.c	2001-03-07 03:44:36.000000000 +0000
+++ linux/arch/mips/boot/elf2ecoff.c	2002-08-01 06:42:42.000000000 +0000
@@ -41,6 +41,8 @@
 #include <unistd.h>
 #include <elf.h>
 #include <limits.h>
+#include <netinet/in.h>
+#include <stdlib.h>
 
 #include "ecoff.h"
 
@@ -56,9 +58,10 @@
   unsigned long len;
 };
 
+void combine (struct sect* base, struct sect* new, int pad);
 int phcmp ();
 char *saveRead (int file, off_t offset, off_t len, char *name);
-int copy (int, int, off_t, off_t);
+void copy (int, int, off_t, off_t);
 int translate_syms (int, int, off_t, off_t, off_t, off_t);
 void convert_elf_hdr (Elf32_Ehdr *);
 void convert_elf_phdrs (Elf32_Phdr *, int);
@@ -71,14 +74,13 @@
 int must_convert_endian = 0;
 int format_bigendian = 0;
 
+int
 main (int argc, char **argv, char **envp)
 {
   Elf32_Ehdr ex;
   Elf32_Phdr *ph;
   Elf32_Shdr *sh;
-  Elf32_Sym *symtab;
   char *shstrtab;
-  int strtabix, symtabix;
   int i, pad;
   struct sect text, data, bss;
   struct filehdr efh;
@@ -168,7 +170,8 @@
       /* Section types we can't handle... */
       else if (ph [i].p_type != PT_LOAD)
         {
-	  fprintf (stderr, "Program header %d type %d can't be converted.\n");
+	  fprintf (stderr, "Program header %d type %d can't be converted.\n", 
+			  	ex.e_phnum, ph[i].p_type );
 	  exit (1);
 	}
       /* Writable (data) segment? */
@@ -330,7 +333,7 @@
 
     for (i = 0; i < nosecs; i++)
       {
-        printf ("Section %d: %s phys %x  size %x  file offset %x\n", 
+        printf ("Section %d: %s phys %lx  size %lx  file offset %lx\n", 
 	      i, esecs [i].s_name, esecs [i].s_paddr,
 	      esecs [i].s_size, esecs [i].s_scnptr);
       }
@@ -384,11 +387,11 @@
 	      char obuf [1024];
 	      if (gap > 65536)
 		{
-		  fprintf (stderr, "Intersegment gap (%d bytes) too large.\n",
+		  fprintf (stderr, "Intersegment gap (%ld bytes) too large.\n",
 			   gap);
 		  exit (1);
 		}
-	      fprintf (stderr, "Warning: %d byte intersegment gap.\n", gap);
+	      fprintf (stderr, "Warning: %ld byte intersegment gap.\n", gap);
 	      memset (obuf, 0, sizeof obuf);
 	      while (gap)
 		{
@@ -428,6 +431,7 @@
   exit (0);
 }
 
+void
 copy (out, in, offset, size)
      int out, in;
      off_t offset, size;
@@ -465,6 +469,7 @@
 
 /* Combine two segments, which must be contiguous.   If pad is true, it's
    okay for there to be padding between. */
+void
 combine (base, new, pad)
      struct sect *base, *new;
      int pad;
@@ -488,6 +493,7 @@
     }
 }
 
+int
 phcmp (h1, h2)
      Elf32_Phdr *h1, *h2;
 {
@@ -511,7 +517,7 @@
     }
   if (!(tmp = (char *)malloc (len)))
     {
-      fprintf (stderr, "%s: Can't allocate %d bytes.\n", name, len);
+      fprintf (stderr, "%s: Can't allocate %ld bytes.\n", name, len);
       exit (1);
     }
   count = read (file, tmp, len);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/Makefile linux/arch/mips/cobalt/Makefile
--- linux.orig/arch/mips/cobalt/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/Makefile	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,16 @@
+#
+# Makefile for the Cobalt micro systems family specific parts of the kernel
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+#
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET := cobalt.o
+
+obj-y	 := irq.o int-handler.o pci.o reset.o setup.o via.o promcon.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/int-handler.S linux/arch/mips/cobalt/int-handler.S
--- linux.orig/arch/mips/cobalt/int-handler.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/int-handler.S	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,103 @@
+/*
+ * Cobalt interrupt handler
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/cobalt/cobalt.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+/*
+ * cobalt_handle_int: Interrupt handler for Cobalt boards
+ */
+		.text
+		.set	noreorder
+		.set	noat
+		.align	5
+		NESTED(cobalt_handle_int, PT_SIZE, sp)
+		SAVE_ALL
+		CLI
+		.set	at
+	
+		/* 
+		 * Get pending Interrupts
+		 */
+		mfc0	s0,CP0_CAUSE	# get irq mask
+
+		andi	a0,s0,CAUSEF_IP2	/* Check for Galileo timer */
+		beq	a0,zero,1f
+		 andi	a0,s0,CAUSEF_IP6	/* Check for Via chip */
+
+		/* Galileo interrupt */
+		jal	galileo_irq
+		 move	a0,sp
+		j	ret_from_irq
+		 nop
+
+1:
+		beq	a0,zero,1f		/* Check IP6 */
+		 andi	a0,s0,CAUSEF_IP3
+
+		/* Via interrupt */
+		jal	via_irq
+		 move	a0,sp
+		j	ret_from_irq
+		 nop
+
+1:	
+		beq	a0,zero,1f		/* Check IP3 */
+		 andi	a0,s0,CAUSEF_IP4
+
+		/* Ethernet 0 interrupt */
+		li	a0,4
+		jal     do_IRQ
+		 move	a1,sp
+
+		j	ret_from_irq
+		 nop
+
+1:	
+		beq	a0,zero,1f		/* Check IP4 */
+		 andi	a0,s0,CAUSEF_IP5
+
+		/* Ethernet 1 interrupt */
+		li	a0,13
+		jal     do_IRQ
+		 move	a1,sp
+
+		j	ret_from_irq
+		 nop
+1:	
+		beq	a0,zero,1f		/* Check IP5 */
+		 andi	a0,s0,CAUSEF_IP7
+
+		/* Serial interrupt */
+		li	a0,7
+		jal     do_IRQ
+		 move	a1,sp
+
+		j	ret_from_irq
+		 nop
+1:	
+		beq	a0,zero,1f		/* Check IP7 */
+		  nop
+
+		/* PCI interrupt */
+		li	a0,9
+		jal     do_IRQ
+		 move	a1,sp
+
+1:
+		j	ret_from_irq
+		 nop
+
+		END(cobalt_handle_int)
+	
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/irq.c linux/arch/mips/cobalt/irq.c
--- linux.orig/arch/mips/cobalt/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/irq.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,223 @@
+/*
+ * IRQ vector handles
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include <asm/cobalt/cobalt.h>
+
+/* Cobalt Exception handler */
+extern void cobalt_handle_int(void);
+
+/* Via masking routines */
+extern void unmask_irq(unsigned int irqr);
+extern void mask_irq(unsigned int irq);
+
+
+/*
+ * We have two types of interrupts that we handle, ones that come
+ *  in through the CPU interrupt lines, and ones that come in on
+ *  the via chip. The CPU mappings are:
+ *    0,1 - S/W (ignored)
+ *    2   - Galileo chip (timer)
+ *    3   - Tulip 0 + NCR SCSI
+ *    4   - Tulip 1
+ *    5   - 16550 UART
+ *    6   - VIA southbridge PIC
+ *    7   - PCI
+ *
+ * The VIA chip is a master/slave 8259 setup and has the 
+ *  following interrupts
+ *    8   - RTC
+ *    14  - IDE0
+ *    15  - IDE1
+ *
+ * In the table we use a 1 to indicate that we use a VIA interrupt
+ *  line, and IE_IRQx to indicate that we use a CPU interrupt line
+ *
+ * We map all of these onto linux IRQ #s 0-15 and forget the rest
+ */
+#define NOINT_LINE	0
+#define CPUINT_LINE(x)	IE_IRQ##x
+#define VIAINT_LINE	1
+
+#define COBALT_IRQS	16
+
+static unsigned short irqnr_to_type[COBALT_IRQS] = 
+{ CPUINT_LINE(0),  NOINT_LINE,      VIAINT_LINE,  NOINT_LINE, 
+  CPUINT_LINE(1),  NOINT_LINE,      NOINT_LINE,   CPUINT_LINE(3),
+  VIAINT_LINE,     VIAINT_LINE,     NOINT_LINE,   NOINT_LINE,
+  NOINT_LINE,      CPUINT_LINE(2),  VIAINT_LINE,  VIAINT_LINE };
+
+/*
+ * Cobalt CPU irq
+ */
+
+static void enable_cpu_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	save_and_cli(flags);
+	change_cp0_status(irqnr_to_type[irq], irqnr_to_type[irq]);
+	restore_flags(flags);
+}
+
+static unsigned startup_cpu_irq(unsigned int irq)
+{
+	enable_cpu_irq(irq);
+
+	return 0;
+}
+
+static void disable_cpu_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	save_and_cli(flags);
+	change_cp0_status(irqnr_to_type[irq], ~(irqnr_to_type[irq]));
+	restore_flags(flags);
+}
+
+#define shutdown_cpu_irq	disable_cpu_irq
+#define mask_and_ack_cpu_irq	disable_cpu_irq
+
+static void end_cpu_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		enable_cpu_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_cpu_irq_type = {
+	"Cobalt CPU",
+	startup_cpu_irq,
+	shutdown_cpu_irq,
+	enable_cpu_irq,
+	disable_cpu_irq,
+	mask_and_ack_cpu_irq,
+	end_cpu_irq,
+	NULL
+};
+
+
+/*
+ * Cobalt VIA irq
+ */
+
+static void enable_via_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	save_and_cli(flags);
+	unmask_irq(irq);
+	restore_flags(flags);
+}
+
+static unsigned startup_via_irq(unsigned int irq)
+{
+	enable_via_irq(irq);
+
+	return 0;
+}
+
+static void disable_via_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	save_and_cli(flags);
+	mask_irq(irq);
+	restore_flags(flags);
+}
+
+#define shutdown_via_irq	disable_via_irq
+#define mask_and_ack_via_irq	disable_via_irq
+
+static void end_via_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		enable_via_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_via_irq_type = {
+	"Cobalt VIA",
+	startup_via_irq,
+	shutdown_via_irq,
+	enable_via_irq,
+	disable_via_irq,
+	mask_and_ack_via_irq,
+	end_via_irq,
+	NULL
+};
+
+
+static struct irqaction via_irq2 = {
+	no_action, 0, 0, "slave cascade", NULL, NULL
+};
+
+static struct resource pic1_io_resource = {
+	"VIA PIC Master", 0x20, 0x3f, IORESOURCE_BUSY
+};
+
+static struct resource pic2_io_resource = {
+	"VIA PIC Slave", 0xa0, 0xbf, IORESOURCE_BUSY
+};
+
+
+void __init init_IRQ(void)
+{
+	int i;
+
+	/* Initialise all of the IRQ descriptors */
+	init_generic_irq();
+
+	/* Map the irqnr to the type int we have */
+	for (i=0; i < COBALT_IRQS; i++) {
+		if (irqnr_to_type[i] >= CPUINT_LINE(0))
+			/* cobalt_cpu_irq_type */
+			irq_desc[i].handler = &cobalt_cpu_irq_type;
+		else if (irqnr_to_type[i] == VIAINT_LINE)
+			/* VIA/8259 irq_type */
+			irq_desc[i].handler = &cobalt_via_irq_type;
+		else {} /* Leave it as disabled/no handler */
+	}
+
+	/* Setup the VIA interrupts */
+	request_resource(&ioport_resource, &pic1_io_resource);
+	request_resource(&ioport_resource, &pic2_io_resource);
+	setup_irq(2, &via_irq2);
+
+	/* This may be too simple.. FIX it later */
+	VIA_PORT_WRITE(0x20, 0x10);
+	VIA_PORT_WRITE(0x21, 0x00);
+	VIA_PORT_WRITE(0x21, 0x00);
+
+	VIA_PORT_WRITE(0xa0, 0x10);
+	VIA_PORT_WRITE(0xa1, 0x00);
+	VIA_PORT_WRITE(0xa1, 0x00);
+
+	/* Mask all cpu interrupts
+	    (except IE4, we already masked those at VIA level) */
+	clear_cp0_status(ST0_IM);
+	set_cp0_status(IE_IRQ4);
+
+	cli();
+
+	set_except_vector(0, cobalt_handle_int);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/pci.c linux/arch/mips/cobalt/pci.c
--- linux.orig/arch/mips/cobalt/pci.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/pci.c	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,429 @@
+/*
+ * Cobalt Qube/Raq PCI support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/cobalt/cobalt.h>
+#include <asm/pci.h>
+#include <asm/io.h>
+ 
+#ifdef CONFIG_PCI
+
+static void qube_expansion_slot_bist(struct pci_dev *dev)
+{
+	unsigned char ctrl;
+	int timeout = 100000;
+
+	pci_read_config_byte(dev, PCI_BIST, &ctrl);
+	if(!(ctrl & PCI_BIST_CAPABLE))
+		return;
+
+	pci_write_config_byte(dev, PCI_BIST, ctrl|PCI_BIST_START);
+	do {
+		pci_read_config_byte(dev, PCI_BIST, &ctrl);
+		if(!(ctrl & PCI_BIST_START))
+			break;
+	} while(--timeout > 0);
+	if((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK))
+		printk("PCI: Expansion slot card failed BIST with code %x\n",
+		       (ctrl & PCI_BIST_CODE_MASK));
+}
+
+static void qube_expansion_slot_fixup(struct pci_dev *dev)
+{
+	unsigned short pci_cmd;
+	unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */
+	unsigned long memaddr_base = 0x12000000;
+	int i;
+
+	/* Enable bits in COMMAND so driver can talk to it. */
+	pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+	pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+
+	/* Give it a working IRQ. */
+	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_QUBE_SLOT_IRQ);
+
+	/* Fixup base addresses, we only support I/O at the moment. */
+	for(i = 0; i <= 5; i++) {
+		unsigned int regaddr = (PCI_BASE_ADDRESS_0 + (i * 4));
+		unsigned int rval, mask, size, alignme, aspace;
+		unsigned long *basep = &ioaddr_base;
+
+		/* Check type first, punt if non-IO. */
+		pci_read_config_dword(dev, regaddr, &rval);
+		aspace = (rval & PCI_BASE_ADDRESS_SPACE);
+		if(aspace != PCI_BASE_ADDRESS_SPACE_IO)
+			basep = &memaddr_base;
+
+		/* Figure out how much it wants, if anything. */
+		pci_write_config_dword(dev, regaddr, 0xffffffff);
+		pci_read_config_dword(dev, regaddr, &rval);
+
+		/* Unused? */
+		if(rval == 0)
+			continue;
+
+		rval &= PCI_BASE_ADDRESS_IO_MASK;
+		mask = (~rval << 1) | 0x1;
+		size = (mask & rval) & 0xffffffff;
+		alignme = size;
+		if(alignme < 0x400)
+			alignme = 0x400;
+		rval = ((*basep + (alignme - 1)) & ~(alignme - 1));
+		*basep = (rval + size);
+		pci_write_config_dword(dev, regaddr, rval | aspace);
+		dev->resource[i].start = rval;
+		dev->resource[i].end = *basep - 1;
+		if(aspace == PCI_BASE_ADDRESS_SPACE_IO) {
+			dev->resource[i].start -= 0x10000000;
+			dev->resource[i].end -= 0x10000000;
+		}
+	}
+	qube_expansion_slot_bist(dev);
+}
+
+static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
+{
+	unsigned short cfgword;
+	unsigned char lt;
+
+	/* Enable Bus Mastering and fast back to back. */
+	pci_read_config_word(dev, PCI_COMMAND, &cfgword);
+	cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
+	pci_write_config_word(dev, PCI_COMMAND, cfgword);
+
+	/* Enable both ide interfaces. ROM only enables primary one.  */
+	pci_write_config_byte(dev, 0x40, 0xb);
+
+	/* Set latency timer to reasonable value. */
+	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
+	if(lt < 64)
+		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+}
+
+static void qube_raq_tulip_fixup(struct pci_dev *dev)
+{
+	unsigned short pci_cmd;
+	extern int cobalt_is_raq;
+
+	/* Fixup the first tulip located at device PCICONF_ETH0 */
+	if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) {
+		/*
+		 * Now tell the Ethernet device that we expect an interrupt at
+		 * IRQ 13 and not the default 189.
+		 *
+		 * The IRQ of the first Tulip is different on Qube and RaQ
+		 */
+		if (!cobalt_is_raq) {
+			/* All Qube's route this the same way. */
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              COBALT_QUBE_ETH_IRQ);
+		} else {
+			/* Setup the first Tulip on the RAQ */
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                              COBALT_RAQ_ETH0_IRQ);
+		}
+		dev->resource[0].start = 0x100000;
+		dev->resource[0].end = 0x10007f;
+		if (dev->resource[1].start < 0x10000000) {
+			dev->resource[1].start = 0xe9ffec00;
+			dev->resource[1].end = 0xe9ffefff;
+			pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0xe9ffec00);
+		}
+	/* Fixup the second tulip located at device PCICONF_ETH1 */
+	} else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) {
+
+		/* Enable the second Tulip device. */
+		pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+		pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+		pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+
+		/* Give it it's IRQ. */
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+                                      COBALT_RAQ_ETH1_IRQ);
+
+		/* And finally, a usable I/O space allocation, right after what
+		 * the first Tulip uses.
+		 */
+		dev->resource[0].start = 0x101000;
+		dev->resource[0].end = 0x10107f;
+	}
+}
+
+static void qube_raq_scsi_fixup(struct pci_dev *dev)
+{
+	unsigned short pci_cmd;
+	extern int cobalt_is_raq;
+
+        /*
+         * Tell the SCSI device that we expect an interrupt at
+         * IRQ 7 and not the default 0.
+         */
+        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ);
+
+	if (cobalt_is_raq) {
+
+		/* Enable the device. */
+		pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+
+		pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+			| PCI_COMMAND_INVALIDATE);
+		pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+
+		/* Give it it's RAQ IRQ. */
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
+
+		/* And finally, a usable I/O space allocation, right after what
+		 * the second Tulip uses.
+		 */
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10102001);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x00002000);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0x00100000);
+	}
+}
+
+static void qube_raq_galileo_fixup(struct pci_dev *dev)
+{
+	unsigned short galileo_id;
+
+	/* Fix PCI latency-timer and cache-line-size values in Galileo
+	 * host bridge.
+	 */
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+
+	/* On all machines prior to Q2, we had the STOP line disconnected
+	 * from Galileo to VIA on PCI.  The new Galileo does not function
+	 * correctly unless we have it connected.
+	 *
+	 * Therefore we must set the disconnect/retry cycle values to
+	 * something sensible when using the new Galileo.
+	 */
+	pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
+	galileo_id &= 0xff;     /* mask off class info */
+	if (galileo_id == 0x10) {
+		/* New Galileo, assumes PCI stop line to VIA is connected. */
+		*((volatile unsigned int *)0xb4000c04) = 0x00004020;
+	} else if (galileo_id == 0x1 || galileo_id == 0x2) {
+		signed int timeo;
+		/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
+		timeo = *((volatile unsigned int *)0xb4000c04);
+		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
+		*((volatile unsigned int *)0xb4000c04) = 0x0000ffff;
+	}
+}
+
+static void
+qube_pcibios_fixup(struct pci_dev *dev)
+{
+	if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_PCISLOT) {
+		unsigned int tmp;
+
+		/* See if there is a device in the expansion slot, if so
+		 * discover its resources and fixup whatever we need to
+		 */
+		pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
+		if(tmp != 0xffffffff && tmp != 0x00000000)
+			qube_expansion_slot_fixup(dev);
+	}
+}
+
+struct pci_fixup pcibios_fixups[] = {
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup },
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup },
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup },
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup },
+	{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup }
+};
+
+
+static __inline__ int pci_range_ck(struct pci_dev *dev) 
+{
+       if ((dev->bus->number == 0) 
+           && ((PCI_SLOT (dev->devfn) == 0) 
+               || ((PCI_SLOT (dev->devfn) > 6) 
+                   && (PCI_SLOT (dev->devfn) <= 12))))
+		return 0;  /* OK device number  */
+
+	return -1;  /* NOT ok device number */
+}
+
+#define PCI_CFG_DATA	((volatile unsigned long *)0xb4000cfc)
+#define PCI_CFG_CTRL	((volatile unsigned long *)0xb4000cf8)
+
+#define PCI_CFG_SET(dev,where) \
+       ((*PCI_CFG_CTRL) = (0x80000000 | (PCI_SLOT ((dev)->devfn) << 11) | \
+                           (PCI_FUNC ((dev)->devfn) << 8) | (where)))
+
+static int qube_pci_read_config_dword (struct pci_dev *dev,
+                                          int where,
+                                          u32 *val)
+{
+	if (where & 0x3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck (dev)) {
+		*val = 0xFFFFFFFF;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	PCI_CFG_SET(dev, where);
+	*val = *PCI_CFG_DATA;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int qube_pci_read_config_word (struct pci_dev *dev,
+                                         int where,
+                                         u16 *val)
+{
+        if (where & 0x1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck (dev)) {
+		*val = 0xffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	PCI_CFG_SET(dev, (where & ~0x3));
+	*val = *PCI_CFG_DATA >> ((where & 3) * 8);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int qube_pci_read_config_byte (struct pci_dev *dev,
+                                         int where,
+                                         u8 *val)
+{
+	if (pci_range_ck (dev)) {
+		*val = 0xff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	PCI_CFG_SET(dev, (where & ~0x3));
+	*val = *PCI_CFG_DATA >> ((where & 3) * 8);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int qube_pci_write_config_dword (struct pci_dev *dev,
+                                           int where,
+                                           u32 val)
+{
+	if(where & 0x3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck (dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	PCI_CFG_SET(dev, where);
+	*PCI_CFG_DATA = val;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+qube_pci_write_config_word (struct pci_dev *dev,
+                                int where, 
+                               u16 val)
+{
+	unsigned long tmp;
+
+	if (where & 0x1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck (dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	PCI_CFG_SET(dev, (where & ~0x3));
+	tmp = *PCI_CFG_DATA;
+	tmp &= ~(0xffff << ((where & 0x3) * 8));
+	tmp |=  (val << ((where & 0x3) * 8));
+	*PCI_CFG_DATA = tmp;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+qube_pci_write_config_byte (struct pci_dev *dev,
+                                int where, 
+                               u8 val)
+{
+	unsigned long tmp;
+
+	if (pci_range_ck (dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	PCI_CFG_SET(dev, (where & ~0x3));
+	tmp = *PCI_CFG_DATA;
+	tmp &= ~(0xff << ((where & 0x3) * 8));
+	tmp |=  (val << ((where & 0x3) * 8));
+	*PCI_CFG_DATA = tmp;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+struct pci_ops qube_pci_ops = {
+	qube_pci_read_config_byte,
+	qube_pci_read_config_word,
+	qube_pci_read_config_dword,
+	qube_pci_write_config_byte,
+	qube_pci_write_config_word,
+	qube_pci_write_config_dword
+};
+
+void __init pcibios_init(void)
+{
+	printk("PCI: Probing PCI hardware\n");
+
+	ioport_resource.start = 0x00000000;
+	ioport_resource.end = 0x0fffffff;
+
+	iomem_resource.start = 0x01000000;
+	iomem_resource.end = 0xffffffff;
+
+	pci_scan_bus(0, &qube_pci_ops, NULL);
+}
+
+char *pcibios_setup(char *str)
+{
+	return str;
+}
+
+int pcibios_enable_device(struct pci_dev *dev)
+{
+	u16 cmd, status;
+	
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	pci_read_config_word(dev, PCI_STATUS, &status);
+	printk("PCI: Enabling device %s (%04x  %04x)\n", dev->slot_name, cmd, status);
+	/* We'll sort this out when we know it isn't enabled ;) */
+
+	return 0;
+}
+
+void pcibios_align_resource(void *data, struct resource *res,
+		unsigned long size)
+{
+
+	panic("Uhhoh called pcibios_align_resource\n");
+}
+
+void pcibios_update_resource(struct pci_dev *dev, struct resource *root, 
+		struct resource *res, int resource)
+{
+
+	panic("Uhhoh called pcibios_update_resource\n");
+}
+
+void __init pcibios_fixup_bus(struct pci_bus *bus)
+{
+	/* We don't have sub-busses to fixup here */
+}
+
+unsigned int __init pcibios_assign_all_busses(void)
+{
+	return 1;
+}
+
+#endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/promcon.c linux/arch/mips/cobalt/promcon.c
--- linux.orig/arch/mips/cobalt/promcon.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/promcon.c	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,91 @@
+/*
+ * PROM console for Cobalt Raq2
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/serial_reg.h>
+
+#include <asm/delay.h>
+#include <asm/serial.h>
+#include <asm/io.h>
+
+static unsigned long port = 0xc800000;
+
+static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
+{
+	char lsr;
+
+	do {
+		lsr = inb(ioaddr + UART_LSR);
+	} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
+	outb(ch, ioaddr + UART_TX);
+}
+
+static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
+{
+	while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
+		udelay(1);
+	return inb(ioaddr + UART_RX);
+}
+
+void ns16550_console_write(struct console *co, const char *s, unsigned count)
+{
+	char lsr, ier;
+	unsigned i;
+
+	ier = inb(port + UART_IER);
+	outb(0x00, port + UART_IER);
+	for (i=0; i < count; i++, s++) {
+
+		if(*s == '\n')
+			ns16550_cons_put_char('\r', port);
+		ns16550_cons_put_char(*s, port);
+	}
+
+	do {
+		lsr = inb(port + UART_LSR);
+   	} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
+
+	outb(ier, port + UART_IER);
+}
+
+char getDebugChar(void)
+{
+	return ns16550_cons_get_char(port);
+}
+
+void putDebugChar(char kgdb_char)
+{
+	ns16550_cons_put_char(kgdb_char, port);
+}
+
+static kdev_t 
+ns16550_console_dev(struct console *c)
+{
+	return MKDEV(TTY_MAJOR, 64 + c->index);
+}
+
+static struct console ns16550_console = {
+    name:	"prom",
+    setup:	NULL,
+    write:	ns16550_console_write,
+    device:	ns16550_console_dev,
+    flags:	CON_PRINTBUFFER,
+    index:	-1,
+};
+
+void __init ns16550_setup_console(void)
+{
+	register_console(&ns16550_console);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/reset.c linux/arch/mips/cobalt/reset.c
--- linux.orig/arch/mips/cobalt/reset.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/reset.c	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,69 @@
+/*
+ * Cobalt Reset operations
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/mipsregs.h>
+
+void cobalt_machine_restart(char *command)
+{
+	*(volatile char *)0xbc000000 = 0x0f;
+
+	/*
+	 * Ouch, we're still alive ... This time we take the silver bullet ...
+	 * ... and find that we leave the hardware in a state in which the
+	 * kernel in the flush locks up somewhen during of after the PCI
+	 * detection stuff.
+	 */
+	set_cp0_status(ST0_BEV | ST0_ERL);
+	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_32bit_cp0_register(CP0_WIRED, 0);
+	__asm__ __volatile__(
+		"jr\t%0"
+		:
+		: "r" (0xbfc00000));
+}
+
+extern int led_state;
+#define kLED            0xBC000000
+#define LEDSet(x)       (*(volatile unsigned char *) kLED) = (( unsigned char)x)
+
+void cobalt_machine_halt(void)
+{
+	int mark;
+
+	/* Blink our cute? little LED (number 3)... */
+	while (1) {
+		led_state = led_state | ( 1 << 3 );
+		LEDSet(led_state);  
+		mark = jiffies;
+		while (jiffies<(mark+HZ));
+		led_state = led_state & ~( 1 << 3 );
+		LEDSet(led_state);
+		mark = jiffies;
+		while (jiffies<(mark+HZ));
+	} 
+}
+
+/*
+ * This triggers the luser mode device driver for the power switch ;-)
+ */
+void cobalt_machine_power_off(void)
+{
+	printk("You can switch the machine off now.\n");
+	cobalt_machine_halt();
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/setup.c linux/arch/mips/cobalt/setup.c
--- linux.orig/arch/mips/cobalt/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/setup.c	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,127 @@
+/*
+ * Setup pointers to hardware dependent routines.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/mc146818rtc.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/cobalt/cobalt.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
+
+extern void cobalt_machine_restart(char *command);
+extern void cobalt_machine_halt(void);
+extern void cobalt_machine_power_off(void);
+
+extern struct rtc_ops std_rtc_ops;
+extern struct ide_ops std_ide_ops;
+
+
+char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 root=/dev/hda1" };
+
+const char *get_system_type(void)
+{
+	return "MIPS Cobalt";
+}
+
+
+#define GALILEO_T0_VAL		0xb4000850
+#define GALILEO_TIMER_CTRL	0xb4000864
+#define GALILEO_CPU_MASK	0xb4000c1c
+
+#define GALILEO_ENTC0		0x01
+#define GALILEO_SELTC0		0x02
+
+static void __init cobalt_time_init(void)
+{
+	rtc_ops = &std_rtc_ops;
+}
+
+static void __init cobalt_timer_setup(struct irqaction *irq)
+{
+	/* Load timer value for 150 Hz */
+	volatile unsigned long *timer_reg = (volatile unsigned long *)GALILEO_T0_VAL;
+
+	*timer_reg = 500000;
+
+	/* Register our timer interrupt */
+	setup_irq(0, irq);
+
+	/* Enable timer ints */
+	*((volatile unsigned long *) GALILEO_TIMER_CTRL) = 
+			(unsigned long) (GALILEO_ENTC0 | GALILEO_SELTC0);
+	/* Unmask timer int */
+	*((volatile unsigned long *) GALILEO_CPU_MASK) = (unsigned long) 0x00000100; 
+}
+
+
+void __init bus_error_init(void) { /* nothing */ }
+
+
+int cobalt_serial_present;
+int cobalt_serial_type;
+int cobalt_is_raq;
+
+void __init cobalt_setup(void)
+{
+
+	_machine_restart = cobalt_machine_restart;
+	_machine_halt = cobalt_machine_halt;
+	_machine_power_off = cobalt_machine_power_off;
+
+	board_time_init = cobalt_time_init;
+	board_timer_setup = cobalt_timer_setup;
+
+#ifdef CONFIG_BLK_DEV_IDE
+	ide_ops = &std_ide_ops;
+#endif
+        set_io_port_base(0xb0000000);
+
+	/* 
+	 * This is a prom style console. We just poke at the
+	 *  UART to make it talk.
+	 * Only use this console if you really screw up and can't
+	 *  get to the stage of setting up a real serial console.
+	 */
+	/*ns16550_setup_console();*/
+
+	/* We have to do this early, here, before the value could
+	 * possibly be overwritten by the bootup sequence.
+	 */
+	cobalt_serial_present = *((unsigned long *) 0xa020001c);
+	cobalt_serial_type    = *((unsigned long *) 0xa0200020);
+	cobalt_is_raq         = (cobalt_serial_present != 0x0
+				 && cobalt_serial_type == 0x1);
+}
+
+/* Prom init. We read our one and only communication with the
+    firmware. Grab the amount of installed memory */
+void __init prom_init(int argc)
+{
+	mips_machgroup = MACH_GROUP_COBALT;
+	
+	add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
+}
+
+void __init prom_free_prom_memory(void)
+{
+	/* Nothing to do! */
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/cobalt/via.c linux/arch/mips/cobalt/via.c
--- linux.orig/arch/mips/cobalt/via.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/cobalt/via.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,99 @@
+/*
+ * VIA chipset irq handling
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/kernel.h>
+#include <asm/cobalt/cobalt.h>
+#include <asm/ptrace.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+
+extern void do_IRQ(int irq, struct pt_regs * regs);
+
+/* Cached values of VIA PIC masks, we start with cascade enabled */
+static unsigned int cached_irq_mask = 0xfffb;
+
+#define __byte(x,y)	(((unsigned char *)&(y))[x])
+#define cached_21	(__byte(0,cached_irq_mask))
+#define cached_A1	(__byte(1,cached_irq_mask))
+
+
+void mask_irq(unsigned int irq)
+{
+	unsigned int mask = 1 << irq;
+
+	cached_irq_mask |= mask;
+	if (irq & 8) {
+		VIA_PORT_WRITE(0xA1, cached_A1);
+	} else {
+		VIA_PORT_WRITE(0x21, cached_21);
+	}
+}
+
+void unmask_irq(unsigned int irq)
+{
+	unsigned int mask = ~(1 << irq);
+
+	cached_irq_mask &= mask;
+	if (irq & 8) {
+		VIA_PORT_WRITE(0xA1, cached_A1);
+	} else {
+		VIA_PORT_WRITE(0x21, cached_21);
+	}
+}
+
+asmlinkage void via_irq(struct pt_regs *regs)
+{
+	char mstat, sstat;
+  
+	/* Read Master Status */
+	VIA_PORT_WRITE(0x20, 0x0C);
+	mstat = VIA_PORT_READ(0x20);
+ 
+	if (mstat < 0) {
+		mstat &= 0x7f;
+		if (mstat != 2) {     	
+			do_IRQ(mstat, regs);
+			VIA_PORT_WRITE(0x20, mstat | 0x20);
+		} else {
+			sstat = VIA_PORT_READ(0xA0);
+
+			/* Slave interrupt */
+			VIA_PORT_WRITE(0xA0, 0x0C);
+			sstat = VIA_PORT_READ(0xA0);
+   
+			if (sstat < 0) {
+				do_IRQ((sstat + 8) & 0x7f, regs);
+				VIA_PORT_WRITE(0x20, 0x22);       
+				VIA_PORT_WRITE(0xA0, (sstat & 0x7f) | 0x20);
+			} else {
+				printk("Spurious slave interrupt...\n");
+			}
+		}
+	} else
+		printk("Spurious master interrupt...");
+}
+
+#define GALILEO_INTCAUSE	0xb4000c18
+#define GALILEO_T0EXP		0x00000100
+
+asmlinkage void galileo_irq(struct pt_regs *regs)
+{
+	unsigned long irq_src = *((unsigned long *) GALILEO_INTCAUSE); 
+
+	/* Check for timer irq ... */
+	if (irq_src & GALILEO_T0EXP) {
+		/* Clear the int line */
+		*((volatile unsigned long *) GALILEO_INTCAUSE) = 0;
+		do_IRQ(0, regs);
+	} else
+		printk("Spurious Galileo interrupt...\n");
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/config.in linux/arch/mips/config.in
--- linux.orig/arch/mips/config.in	2001-10-15 20:41:34.000000000 +0000
+++ linux/arch/mips/config.in	2002-08-01 06:42:46.000000000 +0000
@@ -3,9 +3,9 @@
 # see Documentation/kbuild/config-language.txt.
 #
 define_bool CONFIG_MIPS y
-define_bool CONFIG_SMP n
+define_bool CONFIG_MIPS32 y
 
-mainmenu_name "Linux Kernel Configuration"
+mainmenu_name "Linux/MIPS Kernel Configuration"
 
 mainmenu_option next_comment
 comment 'Code maturity level options'
@@ -13,99 +13,181 @@
 endmenu
 
 mainmenu_option next_comment
+comment 'Loadable module support'
+bool 'Enable loadable module support' CONFIG_MODULES
+if [ "$CONFIG_MODULES" = "y" ]; then
+   bool '  Set version information on all module symbols' CONFIG_MODVERSIONS
+   bool '  Kernel module loader' CONFIG_KMOD
+fi
+endmenu
+
+mainmenu_option next_comment
 comment 'Machine selection'
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
-   bool 'Support for Acer PICA 1 chipset' CONFIG_ACER_PICA_61
-   bool 'Support for Algorithmics P4032 (EXPERIMENTAL)' CONFIG_ALGOR_P4032
-   bool 'Support for BAGET MIPS series (EXPERIMENTAL)' CONFIG_BAGET_MIPS
-   bool 'Support for DECstations (EXPERIMENTAL)' CONFIG_DECSTATION
-   bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074
-   bool 'Support for Galileo EV96100 Evaluation board' CONFIG_MIPS_EV96100
-   bool 'Support for Galileo EV64120 Evaluation board' CONFIG_MIPS_EV64120
-   if [ "$CONFIG_MIPS_EV64120" = "y" ]; then
-		  bool 'Enable Second PCI (PCI1)' CONFIG_EVB_PCI1
-      choice 'Galileo Chip Clock' \
-        "75 CONFIG_SYSCLK_75\
-         83.3 CONFIG_SYSCLK_83\
-         100 CONFIG_SYSCLK_100" CONFIG_SYSCLK_83
-   fi
-   bool 'Support for MIPS Atlas board' CONFIG_MIPS_ATLAS
-   bool 'Support for MIPS Malta board' CONFIG_MIPS_MALTA
-   bool 'Support for Philips Nino (EXPERIMENTAL)' CONFIG_NINO
-   if [ "$CONFIG_NINO" = "y" ]; then
-      choice 'Nino Model Number' \
-        "Model-300/301/302/319 CONFIG_NINO_4MB \
-         Model-200/210/312/320/325/350/390 CONFIG_NINO_8MB \
-         Model-500/510 CONFIG_NINO_16MB" CONFIG_NINO_8MB
-   fi
+dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
+bool 'Support for Alchemy Semi PB1000 board' CONFIG_MIPS_PB1000
+if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
+   bool '  Support for PCI AUTO Config' CONFIG_PCI_AUTO
+fi
+bool 'Support for Alchemy Semi PB1500 board' CONFIG_MIPS_PB1500
+dep_bool 'Support for Algorithmics P4032 (EXPERIMENTAL)' CONFIG_ALGOR_P4032 $CONFIG_EXPERIMENTAL
+dep_bool 'Support for BAGET MIPS series (EXPERIMENTAL)' CONFIG_BAGET_MIPS $CONFIG_EXPERIMENTAL
+dep_bool 'Support for Cobalt Server (EXPERIMENTAL)' CONFIG_MIPS_COBALT $CONFIG_EXPERIMENTAL
+bool 'Support for DECstations' CONFIG_DECSTATION
+dep_bool 'Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)' CONFIG_MIPS_EV64120 $CONFIG_EXPERIMENTAL
+if [ "$CONFIG_MIPS_EV64120" = "y" ]; then
+   bool '  Enable Second PCI (PCI1)' CONFIG_EVB_PCI1
+   choice '  Galileo Chip Clock' \
+	"75	CONFIG_SYSCLK_75 \
+	 83.3	CONFIG_SYSCLK_83 \
+	 100	CONFIG_SYSCLK_100" 83.3
+fi
+dep_bool 'Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)' CONFIG_MIPS_EV96100 $CONFIG_EXPERIMENTAL
+bool 'Support for Globespan IVR board' CONFIG_MIPS_IVR
+bool 'Support for Hewlett Packard LaserJet board' CONFIG_HP_LASERJET
+bool 'Support for ITE 8172G board' CONFIG_MIPS_ITE8172
+if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
+   bool '  Support for older IT8172 (Rev C)' CONFIG_IT8172_REVC
 fi
-bool 'Support for Mips Magnum 4000' CONFIG_MIPS_MAGNUM_4000
+dep_bool 'Support for MIPS Atlas board (EXPERIMENTAL)' CONFIG_MIPS_ATLAS $CONFIG_EXPERIMENTAL
+bool 'Support for MIPS Magnum 4000' CONFIG_MIPS_MAGNUM_4000
+dep_bool 'Support for MIPS Malta board (EXPERIMENTAL)' CONFIG_MIPS_MALTA $CONFIG_EXPERIMENTAL
 bool 'Support for Momentum Ocelot board' CONFIG_MOMENCO_OCELOT
+dep_bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074 $CONFIG_EXPERIMENTAL
 bool 'Support for NEC DDB Vrc-5476' CONFIG_DDB5476
 bool 'Support for NEC DDB Vrc-5477' CONFIG_DDB5477
+bool 'Support for NEC Osprey board' CONFIG_NEC_OSPREY
 bool 'Support for Olivetti M700-10' CONFIG_OLIVETTI_M700
-bool 'Support for SGI IP22' CONFIG_SGI_IP22
-bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
-bool 'Support for ITE 8172G board' CONFIG_MIPS_ITE8172
-   if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
-       bool '    Support for older IT8172 (Rev C)' CONFIG_IT8172_REVC
-       bool '    Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
-       if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
-	   define_bool CONFIG_IT8172_CIR y
-       else
-           bool '    Enable PS2 Keyboard Support ' CONFIG_PC_KEYB
-       fi
-       bool '    Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
-       bool '    Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
-   fi
-   bool 'Support for Globespan IVR board' CONFIG_MIPS_IVR
-   if [ "$CONFIG_MIPS_IVR" = "y" ]; then
-       bool '    Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
-       if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
-	   define_bool CONFIG_IT8172_CIR y
-       fi
-       bool '    Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
+dep_bool 'Support for Philips Nino (EXPERIMENTAL)' CONFIG_NINO $CONFIG_EXPERIMENTAL
+if [ "$CONFIG_NINO" = "y" ]; then
+   choice 'Nino Model Number' \
+	"Model-300/301/302/319			CONFIG_NINO_4MB \
+	 Model-200/210/312/320/325/350/390	CONFIG_NINO_8MB \
+	 Model-500/510				CONFIG_NINO_16MB" Model-200
+fi
+bool 'Support for SGI IP22 (Indy/Indigo2)' CONFIG_SGI_IP22
+dep_bool 'Support for SiByte SB1250 SOC (EXPERIMENTAL)' CONFIG_SIBYTE_SB1250 $CONFIG_EXPERIMENTAL
+if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
+   bool '  Support for SB1250 onchip PCI controller' CONFIG_PCI
+   bool '  Support for SB1250 profiling - SB1/SCD perf counters' CONFIG_SIBYTE_SB1250_PROF
+   bool '  Support for BCM1250 profiling using trace buffer' CONFIG_BCM1250_TBPROF
+   bool '  Remote debugging (kgdb over UART 1)' CONFIG_REMOTE_DEBUG
+   bool '  Support for SiByte SWARM board' CONFIG_SIBYTE_SWARM
+   if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
+      bool '    Running under simulation' CONFIG_SIMULATION
+      bool '    Configure for L3proc Demo' CONFIG_L3DEMO
+      int '    Maximum memory chunks' CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS 16
+      bool '    Multi-Processing support' CONFIG_SMP
    fi
-bool 'Support for Alchemy Semi PB1000 board' CONFIG_MIPS_PB1000
+fi
+bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
+bool 'Support for Toshiba JMR-TX3927 board' CONFIG_TOSHIBA_JMR3927
+
+dep_bool 'High Memory Support (EXPERIMENTAL)' CONFIG_HIGHMEM $CONFIG_EXPERIMENTAL
 
 define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y
 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
 
 #
-# Select some configuration options automatically for certain systems.
+# Select some configuration options automatically based on user selections.
 #
-unset CONFIG_ARC32
-unset CONFIG_BOARD_SCACHE
-unset CONFIG_COHERENT_IO
-unset CONFIG_HAVE_STD_PC_SERIAL_PORT
-unset CONFIG_I8259
-unset CONFIG_ISA
-unset CONFIG_PCI
-unset CONFIG_MIPS_JAZZ
-unset CONFIG_SWAP_IO_SPACE
-unset CONFIG_VIDEO_G364
-unset CONFIG_PC_KEYB
 
-define_bool CONFIG_MCA n
-define_bool CONFIG_SBUS n
-
-if [ "$CONFIG_MIPS_EV96100" = "y" ]; then
+if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
+   define_bool CONFIG_ARC32 y
+   define_bool CONFIG_I8259 y
+   define_bool CONFIG_ISA y
+   define_bool CONFIG_MIPS_JAZZ y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_ROTTEN_IRQ y
+   define_bool CONFIG_OLD_TIME_C y
+fi
+if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
+   define_bool CONFIG_MIPS_AU1000 y
+   define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_PCI y
-   define_bool CONFIG_MIPS_GT96100 y
-   define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PC_KEYB y
+   define_int  MAX_HWIFS 1
+fi
+if [ "$CONFIG_MIPS_PB1500" = "y" ]; then
+   define_bool CONFIG_MIPS_AU1000 y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_PCI y
    define_bool CONFIG_PCI_AUTO y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PC_KEYB y
+fi
+if [ "$CONFIG_ALGOR_P4032" = "y" ]; then
+   define_bool CONFIG_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_OLD_TIME_C y
+fi
+if [ "$CONFIG_MIPS_COBALT" = "y" ]; then
+   define_bool CONFIG_COBALT_LCD y
+   define_bool CONFIG_PCI y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
+fi
+if [ "$CONFIG_DECSTATION" = "y" ]; then
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NONCOHERENT_IO y
 fi
 if [ "$CONFIG_MIPS_EV64120" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_ISA n
    define_bool CONFIG_MIPS_GT64120 y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_OLD_TIME_C y
 fi
-
-if [ "$CONFIG_ALGOR_P4032" = "y" ]; then
+if [ "$CONFIG_MIPS_EV96100" = "y" ]; then
    define_bool CONFIG_PCI y
-   define_bool CONFIG_OLD_TIME_C y
+   define_bool CONFIG_MIPS_GT96100 y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PCI_AUTO y
+   define_bool CONFIG_SWAP_IO_SPACE y
+fi
+if [ "$CONFIG_MIPS_IVR" = "y" ]; then
+   define_bool CONFIG_PCI y
+   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PCI_AUTO y
+   define_bool CONFIG_IT8172_CIR y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+fi
+if [ "$CONFIG_HP_LASERJET" = "y" ]; then
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PCI y
+   #not yet define_bool CONFIG_PCI_AUTO y
+fi
+if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
+   define_bool CONFIG_PCI y
+   define_bool CONFIG_IT8712 y
+   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PCI_AUTO y
+   define_bool CONFIG_IT8172_CIR y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+fi
+if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PCI y
+   define_bool CONFIG_SWAP_IO_SPACE y
 fi
 if [ "$CONFIG_MIPS_MAGNUM_4000" = "y" -o \
      "$CONFIG_OLIVETTI_M700" = "y" ]; then
@@ -113,118 +195,120 @@
    define_bool CONFIG_I8259 y
    define_bool CONFIG_ISA y
    define_bool CONFIG_FB y
-   define_bool CONFIG_FB_G364 y	
-   define_bool CONFIG_MIPS_JAZZ y
-   define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_OLD_TIME_C y
-fi
-if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
-   define_bool CONFIG_ARC32 y
-   define_bool CONFIG_I8259 y
-   define_bool CONFIG_ISA y
+   define_bool CONFIG_FB_G364 y
    define_bool CONFIG_MIPS_JAZZ y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_ROTTEN_IRQ y
    define_bool CONFIG_OLD_TIME_C y
 fi
-if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
-   define_bool CONFIG_PCI y
-   define_bool CONFIG_SWAP_IO_SPACE y
-fi
 if [ "$CONFIG_MIPS_MALTA" = "y" ]; then
    define_bool CONFIG_I8259 y
    define_bool CONFIG_PCI y
    define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
    define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_SWAP_IO_SPACE y
+   define_bool CONFIG_PC_KEYB y
 fi
 if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; then
    define_bool CONFIG_PCI y
    define_bool CONFIG_SYSCLK_100 y
    define_bool CONFIG_SWAP_IO_SPACE y
    define_bool CONFIG_NEW_IRQ y
-   define_bool CONFIG_OLD_TIME_C y
-fi
-if [ "$CONFIG_SGI_IP22" = "y" ]; then
-   define_bool CONFIG_ARC32 y
-   define_bool CONFIG_BOARD_SCACHE y
-   define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_SGI y
-   define_bool CONFIG_NEW_IRQ y
-   define_bool CONFIG_OLD_TIME_C y
-fi
-if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
-   define_bool CONFIG_ARC32 y
-   define_bool CONFIG_I8259 y
-   define_bool CONFIG_ISA y
-   define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_PCI y
-   define_bool CONFIG_ROTTEN_IRQ y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_OLD_TIME_C y
 fi
 if [ "$CONFIG_DDB5074" = "y" ]; then
+   define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
    define_bool CONFIG_I8259 y
    define_bool CONFIG_ISA y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI y
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_ROTTEN_IRQ y
-   define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
    define_bool CONFIG_OLD_TIME_C y
 fi
 if [ "$CONFIG_DDB5476"  = "y" ]; then
    define_bool CONFIG_ISA y
    define_bool CONFIG_PCI y
    define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_ROTTEN_IRQ y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_I8259 y
    define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
 fi
 if [ "$CONFIG_DDB5477" = "y" ]; then
-   define_bool CONFIG_CPU_LITTLE_ENDIAN y
    define_bool CONFIG_PCI y
    define_bool CONFIG_NEW_TIME_C y
    define_bool CONFIG_NEW_IRQ y
-fi
-if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
-   define_bool CONFIG_PCI y
-   define_bool CONFIG_IT8712 y
-   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_IRQ_CPU y
    define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI_AUTO y
+   define_bool CONFIG_DUMMY_KEYB y
 fi
-if [ "$CONFIG_MIPS_IVR" = "y" ]; then
-   define_bool CONFIG_PCI y
-fi
-if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
-   define_bool CONFIG_MIPS_AU1000 y
+if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
+   define_bool CONFIG_VR4181 y
+   define_bool CONFIG_SERIAL y
+   define_bool CONFIG_SERIAL_MANY_PORTS y
    define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_DUMMY_KEYB y
+   define_bool CONFIG_SCSI n
 fi
 if [ "$CONFIG_NINO" = "y" ]; then
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
-
-if [ "$CONFIG_ISA" != "y" ]; then
-   define_bool CONFIG_ISA n
-   define_bool CONFIG_EISA n
-else
-   define_bool CONFIG_EISA y
+if [ "$CONFIG_SGI_IP22" = "y" ]; then
+   define_bool CONFIG_ARC32 y
+   define_bool CONFIG_BOARD_SCACHE y
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_SGI y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
 fi
-
-if [ "$CONFIG_PCI" != "y" ]; then
-   define_bool CONFIG_PCI n
+if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_DUMMY_KEYB y
+   define_bool CONFIG_SWAP_IO_SPACE y
 fi
-
-if [ "$CONFIG_I8259" != "y" ]; then
-   define_bool CONFIG_I8259 n
+if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
+   define_bool CONFIG_ARC32 y
+   define_bool CONFIG_I8259 y
+   define_bool CONFIG_ISA y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_OLD_TIME_C y
+   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_PCI y
+fi
+if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
+   define_bool CONFIG_TOSHIBA_BOARDS y
+   define_bool CONFIG_PCI y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_PCI_AUTO y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_SWAP_IO_SPACE y
+   define_bool CONFIG_PC_KEYB y
 fi
-endmenu
 
-mainmenu_option next_comment
-comment 'Loadable module support'
-bool 'Enable loadable module support' CONFIG_MODULES
-if [ "$CONFIG_MODULES" = "y" ]; then
-   bool '  Set version information on all module symbols' CONFIG_MODVERSIONS
-   bool '  Kernel module loader' CONFIG_KMOD
+if [ "$CONFIG_MIPS_AU1000" != "y" ]; then
+   define_bool CONFIG_MIPS_AU1000 n
 fi
 endmenu
 
@@ -232,29 +316,63 @@
 comment 'CPU selection'
 
 choice 'CPU type' \
-	"R3000 CONFIG_CPU_R3000	\
-	 R6000 CONFIG_CPU_R6000	\
-	 R41xx CONFIG_CPU_VR41XX \
-	 R4300 CONFIG_CPU_R4300	\
-	 R4x00 CONFIG_CPU_R4X00	\
-	 R5000 CONFIG_CPU_R5000	\
-	 R5432 CONFIG_CPU_R5432 \
-	 RM7000 CONFIG_CPU_RM7000 \
-	 R52xx CONFIG_CPU_NEVADA \
-	 R10000 CONFIG_CPU_R10000 \
-	 SB1    CONFIG_CPU_SB1    \
-	 MIPS32 CONFIG_CPU_MIPS32 \
-	 MIPS64 CONFIG_CPU_MIPS64" R4x00
+	"R3000	CONFIG_CPU_R3000 \
+	 R39XX	CONFIG_CPU_TX39XX \
+	 R6000	CONFIG_CPU_R6000 \
+	 R41xx	CONFIG_CPU_VR41XX \
+	 R4300	CONFIG_CPU_R4300 \
+	 R4x00	CONFIG_CPU_R4X00 \
+	 R49XX	CONFIG_CPU_TX49XX \
+	 R5000	CONFIG_CPU_R5000 \
+	 R5432	CONFIG_CPU_R5432 \
+	 RM7000	CONFIG_CPU_RM7000 \
+	 R52xx	CONFIG_CPU_NEVADA \
+	 R10000	CONFIG_CPU_R10000 \
+	 SB1	CONFIG_CPU_SB1 \
+	 MIPS32	CONFIG_CPU_MIPS32 \
+	 MIPS64	CONFIG_CPU_MIPS64" R4x00
+
+if [ "$CONFIG_CPU_MIPS32" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+   bool '  Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE
+fi
+
+if [ "$CONFIG_CPU_MIPS64" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+   bool '  Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE
+fi
+
+if [ "$CONFIG_CPU_RM7000" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+fi
+
+if [ "$CONFIG_CPU_SB1" = "y" ]; then
+   bool '  Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
+   bool '  Support for SB1 Cache Error handler' CONFIG_SB1_CACHE_ERROR
+   define_bool CONFIG_VTAG_ICACHE y
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+fi
+
+if [ "$CONFIG_CPU_R4X00"  = "y" -o \
+     "$CONFIG_CPU_R5000" = "y" -o \
+     "$CONFIG_CPU_RM7000" = "y" -o \
+     "$CONFIG_CPU_R10000" = "y" -o \
+     "$CONFIG_CPU_SB1" = "y" -o \
+     "$CONFIG_CPU_MIPS32" = "y" -o \
+     "$CONFIG_CPU_MIPS64" = "y" ]; then
+   bool '  Support for 64-bit physical address space' CONFIG_64BIT_PHYS_ADDR
+fi
 
 bool 'Override CPU Options' CONFIG_CPU_ADVANCED
-
 if [ "$CONFIG_CPU_ADVANCED" = "y" ]; then
    bool '  ll/sc Instructions available' CONFIG_CPU_HAS_LLSC
    bool '  lld/scd Instructions available' CONFIG_CPU_HAS_LLDSCD
    bool '  Writeback Buffer available' CONFIG_CPU_HAS_WB
 else
-   if [ "$CONFIG_CPU_R3000" = "y" -o "$CONFIG_CPU_VR41XX" = "y" ]; then
-      if [ "CONFIG_DECSTATION" = "y" ]; then
+   if [ "$CONFIG_CPU_R3000" = "y" -o \
+        "$CONFIG_CPU_VR41XX" = "y" -o    \
+        "$CONFIG_CPU_TX39XX" = "y" ]; then
+      if [ "$CONFIG_DECSTATION" = "y" ]; then
 	 define_bool CONFIG_CPU_HAS_LLSC n
 	 define_bool CONFIG_CPU_HAS_LLDSCD n
 	 define_bool CONFIG_CPU_HAS_WB y
@@ -281,64 +399,82 @@
 comment 'General setup'
 if [ "$CONFIG_DECSTATION" = "y" -o \
      "$CONFIG_DDB5074" = "y" -o    \
-     "$CONFIG_DDB5476" = "y" -o    \
-     "$CONFIG_NINO" = "y" ]; then
+     "$CONFIG_NINO" = "y" -o       \
+     "$CONFIG_MIPS_COBALT" = "y" ]; then
    define_bool CONFIG_CPU_LITTLE_ENDIAN y
 else
    bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN
 fi
 
-if [ "$CONFIG_PROC_FS" = "y" ]; then
-   define_bool CONFIG_KCORE_ELF y
+if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
+       bool 'DS1742 BRAM/RTC support' CONFIG_RTC_DS1742
 fi
-define_bool CONFIG_ELF_KERNEL y
 
 if [ "$CONFIG_CPU_LITTLE_ENDIAN" = "n" ]; then
-   bool 'Include IRIX binary compatibility' CONFIG_BINFMT_IRIX 
-   bool 'Include forward keyboard' CONFIG_FORWARD_KEYBOARD 
+   bool 'Include IRIX binary compatibility' CONFIG_BINFMT_IRIX
+   bool 'Include forward keyboard' CONFIG_FORWARD_KEYBOARD
 fi
 
 if [ "$CONFIG_ARC32" = "y" ]; then
    bool 'ARC console support' CONFIG_ARC_CONSOLE
 fi
 
-define_bool CONFIG_BINFMT_AOUT n
-define_bool CONFIG_BINFMT_ELF y
-tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
-
 bool 'Networking support' CONFIG_NET
 
+if [ "$CONFIG_PCI" != "y" ]; then
+   define_bool CONFIG_PCI n
+fi
+
 source drivers/pci/Config.in
 
+if [ "$CONFIG_ISA" != "y" ]; then
+   define_bool CONFIG_ISA n
+   define_bool CONFIG_EISA n
+else
+   define_bool CONFIG_EISA y
+fi
+
+dep_bool 'TURBOchannel support' CONFIG_TC $CONFIG_DECSTATION
+#dep_bool 'Access.Bus support' CONFIG_ACCESSBUS $CONFIG_TC
+
+define_bool CONFIG_MCA n
+define_bool CONFIG_SBUS n
+
 bool 'Support for hot-pluggable devices' CONFIG_HOTPLUG
 
 if [ "$CONFIG_HOTPLUG" = "y" ] ; then
    source drivers/pcmcia/Config.in
+   source drivers/hotplug/Config.in
 else
    define_bool CONFIG_PCMCIA n
+   define_bool CONFIG_HOTPLUG_PCI n
 fi
 
 bool 'System V IPC' CONFIG_SYSVIPC
 bool 'BSD Process Accounting' CONFIG_BSD_PROCESS_ACCT
 bool 'Sysctl support' CONFIG_SYSCTL
+define_bool CONFIG_KCORE_ELF y
+define_bool CONFIG_KCORE_AOUT n
+define_bool CONFIG_BINFMT_AOUT n
+define_bool CONFIG_BINFMT_ELF y
+tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
 
-if [ "$CONFIG_DECSTATION" = "y" ]; then
-    bool 'TURBOchannel support' CONFIG_TC
-#    if [ "$CONFIG_TC" = "y" ]; then
-#	bool ' Access.Bus support' CONFIG_ACCESSBUS
-#    fi
-fi
+dep_bool 'Power Management support (EXPERIMENTAL)' CONFIG_PM $CONFIG_EXPERIMENTAL $CONFIG_MIPS_AU1000
 endmenu
 
-if [ "$CONFIG_ISA" = "y" ]; then
-   source drivers/pnp/Config.in
-fi
-
 source drivers/mtd/Config.in
 
 source drivers/parport/Config.in
 
+source drivers/pnp/Config.in
+
 source drivers/block/Config.in
+if [ "$CONFIG_BLK_DEV_INITRD" = "y" ]; then
+   mainmenu_option next_comment
+   comment 'MIPS initrd options'
+   bool '  Embed root filesystem ramdisk into the kernel' CONFIG_EMBEDDED_RAMDISK
+   endmenu
+fi
 
 source drivers/md/Config.in
 
@@ -348,14 +484,13 @@
 
 source drivers/telephony/Config.in
 
-if [ "$CONFIG_SGI_IP22" != "y" -a \
-     "$CONFIG_DECSTATION" != "y" ]; then
+if [ "$CONFIG_ISA" = "y" -o "$CONFIG_PCI" = "y" ]; then
 
    mainmenu_option next_comment
    comment 'ATA/IDE/MFM/RLL support'
-    
+
    tristate 'ATA/IDE/MFM/RLL support' CONFIG_IDE
-    
+
    if [ "$CONFIG_IDE" != "n" ]; then
       source drivers/ide/Config.in
    else
@@ -375,8 +510,7 @@
 fi
 endmenu
 
-if [ "$CONFIG_DECSTATION" != "y" -a \
-     "$CONFIG_SGI_IP22" != "y" ]; then
+if [ "$CONFIG_PCI" = "y" ]; then
    source drivers/message/i2o/Config.in
 fi
 
@@ -388,7 +522,7 @@
    if [ "$CONFIG_NETDEVICES" = "y" ]; then
       source drivers/net/Config.in
       if [ "$CONFIG_ATM" = "y" ]; then
-         source drivers/atm/Config.in
+	 source drivers/atm/Config.in
       fi
    fi
    endmenu
@@ -398,77 +532,56 @@
 
 source net/irda/Config.in
 
-mainmenu_option next_comment
-comment 'ISDN subsystem'
 if [ "$CONFIG_NET" != "n" ]; then
+   mainmenu_option next_comment
+   comment 'ISDN subsystem'
+
    tristate 'ISDN support' CONFIG_ISDN
    if [ "$CONFIG_ISDN" != "n" ]; then
       source drivers/isdn/Config.in
    fi
+   endmenu
 fi
-endmenu
 
-mainmenu_option next_comment
-comment 'Old CD-ROM drivers (not SCSI, not IDE)'
+if [ "$CONFIG_ISA" = "y" ]; then
+   mainmenu_option next_comment
+   comment 'Old CD-ROM drivers (not SCSI, not IDE)'
 
-bool 'Support non-SCSI/IDE/ATAPI CDROM drives' CONFIG_CD_NO_IDESCSI
-if [ "$CONFIG_CD_NO_IDESCSI" != "n" ]; then
-   source drivers/cdrom/Config.in
+   bool 'Support non-SCSI/IDE/ATAPI CDROM drives' CONFIG_CD_NO_IDESCSI
+   if [ "$CONFIG_CD_NO_IDESCSI" != "n" ]; then
+      source drivers/cdrom/Config.in
+   fi
+   endmenu
 fi
-endmenu
 
 source drivers/char/Config.in
 
+#source drivers/misc/Config.in
+
 source drivers/media/Config.in
 
 if [ "$CONFIG_DECSTATION" = "y" ]; then
    mainmenu_option next_comment
    comment 'DECStation Character devices'
 
-   bool 'Virtual terminal' CONFIG_VT
-   if [ "$CONFIG_VT" = "y" ]; then
-      bool 'Support for console on virtual terminal' CONFIG_VT_CONSOLE
-   fi
    tristate 'Standard/generic (dumb) serial support' CONFIG_SERIAL
-   if [ "$CONFIG_SERIAL" = "y" ]; then
-      bool 'DZ11 Serial Support' CONFIG_DZ
-      if [ "$CONFIG_TC" = "y" ]; then
-	 bool 'Z85C30 Serial Support' CONFIG_ZS
-      fi
-   bool '   Support for console on serial port' CONFIG_SERIAL_CONSOLE
-   fi
-   bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
-   if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
-      int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
-   fi
-#   if [ "$CONFIG_ACCESSBUS" = "y" ]; then
-#      bool 'MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE
-#   fi
+   dep_bool '  DZ11 Serial Support' CONFIG_DZ $CONFIG_SERIAL
+   dep_bool '  Z85C30 Serial Support' CONFIG_ZS $CONFIG_SERIAL $CONFIG_TC
+   dep_bool '  Support for console on serial port' CONFIG_SERIAL_CONSOLE $CONFIG_SERIAL
+#   dep_bool 'MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
    bool 'Enhanced Real Time Clock Support' CONFIG_RTC
-
    endmenu
 fi
 
 if [ "$CONFIG_SGI_IP22" = "y" ]; then
    mainmenu_option next_comment
    comment 'SGI Character devices'
-   bool 'Virtual terminal' CONFIG_VT
    if [ "$CONFIG_VT" = "y" ]; then
-      bool 'Support for console on virtual terminal' CONFIG_VT_CONSOLE
       tristate 'SGI Newport Console support' CONFIG_SGI_NEWPORT_CONSOLE
-      if [ "$CONFIG_SGI_NEWPORT_CONSOLE" != "y" ]; then
-	 define_bool CONFIG_DUMMY_CONSOLE y
-      else
+      if [ "$CONFIG_SGI_NEWPORT_CONSOLE" = "y" ]; then
 	 define_bool CONFIG_FONT_8x16 y
       fi
-   fi
-   bool 'PS/2 mouse support' CONFIG_PSMOUSE
-   if [ "$CONFIG_PSMOUSE" != "n" ]; then
-      define_bool CONFIG_MOUSE y
-   fi
-   bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
-   if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
-      int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
+      define_bool CONFIG_DUMMY_CONSOLE y
    fi
    endmenu
 fi
@@ -486,22 +599,23 @@
    endmenu
 fi
 
-if [ "$CONFIG_DECSTATION" != "y" ]; then
-   mainmenu_option next_comment
-   comment 'Sound'
+mainmenu_option next_comment
+comment 'Sound'
 
-   tristate 'Sound card support' CONFIG_SOUND
-   if [ "$CONFIG_SOUND" != "n" ]; then
-      source drivers/sound/Config.in
-   fi
-   endmenu
+tristate 'Sound card support' CONFIG_SOUND
+if [ "$CONFIG_SOUND" != "n" ]; then
+   source drivers/sound/Config.in
 fi
+endmenu
 
 if [ "$CONFIG_SGI_IP22" = "y" ]; then
    source drivers/sgi/Config.in
 fi
 
 source drivers/usb/Config.in
+
+source net/bluetooth/Config.in
+
 source drivers/input/Config.in
 
 mainmenu_option next_comment
@@ -512,9 +626,7 @@
   bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
   dep_bool 'Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_REMOTE_DEBUG
 fi
-if [ "$CONFIG_SERIAL" = "y" ]; then
-  bool 'Low-level debugging' CONFIG_LL_DEBUG
-fi
+bool 'Enable run-time debugging' CONFIG_DEBUG
 bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ
 if [ "$CONFIG_SMP" != "y" ]; then
    bool 'Run uncached' CONFIG_MIPS_UNCACHED
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5074/prom.c linux/arch/mips/ddb5074/prom.c
--- linux.orig/arch/mips/ddb5074/prom.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5074/prom.c	2002-08-01 06:42:31.000000000 +0000
@@ -13,7 +13,12 @@
 #include <asm/bootinfo.h>
 
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
+
+const char *get_system_type(void)
+{
+	return "NEC DDB Vrc-5074";
+}
 
 void __init prom_init(const char *s)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5074/setup.c linux/arch/mips/ddb5074/setup.c
--- linux.orig/arch/mips/ddb5074/setup.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5074/setup.c	2002-08-01 06:42:35.000000000 +0000
@@ -96,7 +96,7 @@
 	extern int panic_timeout;
 
 	irq_setup = ddb_irq_setup;
-	mips_io_port_base = NILE4_PCI_IO_BASE;
+	set_io_port_base(NILE4_PCI_IO_BASE);
 	isa_slot_offset = NILE4_PCI_MEM_BASE;
 	request_region(0x00, 0x20, "dma1");
 	request_region(0x40, 0x20, "timer");
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/Makefile linux/arch/mips/ddb5476/Makefile
--- linux.orig/arch/mips/ddb5476/Makefile	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5476/Makefile	1970-01-01 00:00:00.000000000 +0000
@@ -1,23 +0,0 @@
-#
-# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
-# under Linux.
-#
-# Note! Dependencies are done automagically by 'make dep', which also
-# removes any old dependencies. DON'T put your own dependencies here
-# unless it's something special (ie not a .c file).
-#
-# Note 2! The CFLAGS definitions are now in the main makefile...
-#
-
-.S.s:
-	$(CPP) $(CFLAGS) $< -o $*.s
-.S.o:
-	$(CC) $(CFLAGS) -c $< -o $*.o
-
-O_TARGET = ddb5476.a
-
-obj-y				+= setup.o irq.o time.o prom.o pci.o \
-				   int-handler.o nile4.o
-obj-$(CONFIG_REMOTE_DEBUG)	+= dbg_io.o
-
-include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/dbg_io.c linux/arch/mips/ddb5476/dbg_io.c
--- linux.orig/arch/mips/ddb5476/dbg_io.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5476/dbg_io.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,125 +0,0 @@
-
-#include <linux/config.h>
-
-#if (defined(CONFIG_DDB5476) && defined(CONFIG_REMOTE_DEBUG))
-
-/* --- CONFIG --- */
-
-/* we need uint32 uint8 */
-/* #include "types.h" */
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-/* --- END OF CONFIG --- */
-
-#define         UART16550_BAUD_2400             2400
-#define         UART16550_BAUD_4800             4800
-#define         UART16550_BAUD_9600             9600
-#define         UART16550_BAUD_19200            19200
-#define         UART16550_BAUD_38400            38400
-#define         UART16550_BAUD_57600            57600
-#define         UART16550_BAUD_115200           115200
-
-#define         UART16550_PARITY_NONE           0
-#define         UART16550_PARITY_ODD            0x08
-#define         UART16550_PARITY_EVEN           0x18
-#define         UART16550_PARITY_MARK           0x28
-#define         UART16550_PARITY_SPACE          0x38
-
-#define         UART16550_DATA_5BIT             0x0
-#define         UART16550_DATA_6BIT             0x1
-#define         UART16550_DATA_7BIT             0x2
-#define         UART16550_DATA_8BIT             0x3
-
-#define         UART16550_STOP_1BIT             0x0
-#define         UART16550_STOP_2BIT             0x4
-
-/* ----------------------------------------------------- */
-
-/* === CONFIG === */
-
-/* [jsun] we use the second serial port for kdb */
-#define         BASE                    0xa60002f8
-#define         MAX_BAUD                115200
-
-/* === END OF CONFIG === */
-
-/* register offset */
-#define         OFS_RCV_BUFFER          0
-#define         OFS_TRANS_HOLD          0
-#define         OFS_SEND_BUFFER         0
-#define         OFS_INTR_ENABLE         1
-#define         OFS_INTR_ID             2
-#define         OFS_DATA_FORMAT         3
-#define         OFS_LINE_CONTROL        3
-#define         OFS_MODEM_CONTROL       4
-#define         OFS_RS232_OUTPUT        4
-#define         OFS_LINE_STATUS         5
-#define         OFS_MODEM_STATUS        6
-#define         OFS_RS232_INPUT         6
-#define         OFS_SCRATCH_PAD         7
-
-#define         OFS_DIVISOR_LSB         0
-#define         OFS_DIVISOR_MSB         1
-
-
-/* memory-mapped read/write of the port */
-#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
-#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
-	/* disable interrupts */
-	UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
-	/* set up buad rate */
-	{
-		uint32 divisor;
-
-		/* set DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-		/* set divisor */
-		divisor = MAX_BAUD / baud;
-		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
-		/* clear DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-	}
-
-	/* set data format */
-	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-static int remoteDebugInitialized = 0;
-
-uint8 getDebugChar(void)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-	return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_9600,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-	UART16550_WRITE(OFS_SEND_BUFFER, byte);
-	return 1;
-}
-
-#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/int-handler.S linux/arch/mips/ddb5476/int-handler.S
--- linux.orig/arch/mips/ddb5476/int-handler.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5476/int-handler.S	1970-01-01 00:00:00.000000000 +0000
@@ -1,136 +0,0 @@
-/*
- *  arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
- *
- *  Based on arch/mips/sgi/kernel/indyIRQ.S
- *
- *  Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-
-/*
- * A lot of complication here is taken away because:
- *
- * 1) We handle one interrupt and return, sitting in a loop and moving across
- *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
- *    common case is one pending IRQ so optimize in that direction.
- *
- * 2) We need not check against bits in the status register IRQ mask, that
- *    would make this routine slow as hell.
- *
- * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
- *    between like BSD spl() brain-damage.
- *
- * Furthermore, the IRQs on the INDY look basically (barring software IRQs
- * which we don't use at all) like:
- *
- *	MIPS IRQ	Source
- *      --------        ------
- *             0	Software (ignored)
- *             1        Software (ignored)
- *             2        Local IRQ level zero
- *             3        Local IRQ level one
- *             4        8254 Timer zero
- *             5        8254 Timer one
- *             6        Bus Error
- *             7        R4k timer (what we use)
- *
- * We handle the IRQ according to _our_ priority which is:
- *
- * Highest ----     R4k Timer
- *                  Local IRQ zero
- *                  Local IRQ one
- *                  Bus Error
- *                  8254 Timer zero
- * Lowest  ----     8254 Timer one
- *
- * then we just return, if multiple IRQs are pending then we will just take
- * another exception, big deal.
- */
-
-	.text
-	.set	noreorder
-	.set	noat
-	.align	5
-	NESTED(ddbIRQ, PT_SIZE, sp)
-	SAVE_ALL
-	CLI
-	.set	at
-	mfc0	s1, CP0_CAUSE		# get irq mask
-
-#if 1
-	mfc0	t2,CP0_STATUS		# get enabled interrupts
-	and	s0, s1, t2		# isolate allowed ones
-#endif
-	/* First we check for r4k counter/timer IRQ. */
-	andi	a0, s0, CAUSEF_IP7	# cpu timer */
-	bnez	a0, cpu_timer_irq
-	andi	a0, s0, CAUSEF_IP2	# delay slot, check local level zero
-	beq	a0, zero, 1f
-	 andi	a0, s0, CAUSEF_IP3	# delay slot, check local level one
-
-	/* Wheee, local level zero interrupt. */
-	jal	ddb_local0_irqdispatch
-	 move	a0, sp			# delay slot
-
-	j	ret_from_irq
-	 nop				# delay slot
-
-1:
-	beq	a0, zero, 1f
-	 andi	a0, s0, CAUSEF_IP6	# delay slot, check bus error
-
-	/* Wheee, local level one interrupt. */
-	move	a0, sp
-	jal	ddb_local1_irqdispatch
-	 nop
-
-	j	ret_from_irq
-	 nop
-
-1:
-	beq	a0, zero, 1f
-	 nop
-
-	/* Wheee, an asynchronous bus error... */
-	move	a0, sp
-	jal	ddb_buserror_irq
-	 nop
-
-	j	ret_from_irq
-	 nop
-
-1:
-	/* Here by mistake?  This is possible, what can happen
-	 * is that by the time we take the exception the IRQ
-	 * pin goes low, so just leave if this is the case.
-	 */
-	andi	a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
-	beq	a0, zero, 1f
-
-	/* Must be one of the 8254 timers... */
-	move	a0, sp
-	jal	ddb_8254timer_irq
-	 nop
-1:
-	/* phamtom interrupt */
-	move 	a0, s1
-	jal	ddb_phantom_irq
-	nop
-	j	ret_from_irq
-	nop
-
-cpu_timer_irq:
-	li	a0, 0
-	move	a1, sp
-	jal	do_IRQ 
-	/* jal	ll_timer_interrupt */
-	nop
-	j	ret_from_irq
-	nop
-	END(ddbIRQ)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/irq.c linux/arch/mips/ddb5476/irq.c
--- linux.orig/arch/mips/ddb5476/irq.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5476/irq.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,251 +0,0 @@
-/*
- *  arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/ptrace.h>
-#include <asm/nile4.h>
-
-extern void __init i8259_init(void);
-extern void i8259_disable_irq(unsigned int irq_nr);
-extern void i8259_enable_irq(unsigned int irq_nr);
-
-extern asmlinkage void ddbIRQ(void);
-extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs);
-extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
-
-
-void no_action(int cpl, void *dev_id, struct pt_regs *regs)
-{
-}
-
-
-#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
-#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
-#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */
-
-#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
-#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
-#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */
-
-#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
-#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */
-
-#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
-#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */
-
-#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
-#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */
-
-static struct {
-	struct resource m1543_config;
-	struct resource pic_elcr;
-} m1543_ioport = {
-	{ "M1543 config", M1543_PNP_CONFIG, M1543_PNP_CONFIG + 1,
-	  IORESOURCE_BUSY},
-	{ "pic ELCR", M1543_INT1_MASTER_ELCR, M1543_INT1_MASTER_ELCR + 1,
-	  IORESOURCE_BUSY}
-};
-
-static void m1543_irq_setup(void)
-{
-	/*
-	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
-	 *  the possible IO sources in the M1543 are in use by us.  We will
-	 *  use the following mapping:
-	 *
-	 *      IRQ1  - keyboard (default set by M1543)
-	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
-	 *              the schematics for the DDB Vrc-5476 board seem to 
-	 *              indicate that IRQ3 is connected to the DS1386 
-	 *              watchdog timer interrupt output so we might have 
-	 *              a conflict)
-	 *      IRQ4  - reserved for UART A (default set by M1543)
-	 *      IRQ5  - parallel (default set by M1543)
-	 *      IRQ8  - DS1386 time of day (RTC) interrupt
-	 *      IRQ9  - USB (hardwired in ddb_setup)
-	 *      IRQ10 - PMU (hardwired in ddb_setup)
-	 *      IRQ12 - mouse
-	 *      IRQ14,15 - IDE controller (need to be confirmed, jsun)
-	 */
-
-	/*
-	 *  Assing mouse interrupt to IRQ12 
-	 */
-
-	/* Enter configuration mode */
-	outb(0x51, M1543_PNP_CONFIG);
-	outb(0x23, M1543_PNP_CONFIG);
-
-	/* Select logical device 7 (Keyboard) */
-	outb(0x07, M1543_PNP_INDEX);
-	outb(0x07, M1543_PNP_DATA);
-
-	/* Select IRQ12 */
-	outb(0x72, M1543_PNP_INDEX);
-	outb(0x0c, M1543_PNP_DATA);
-
-	/* Leave configration mode */
-	outb(0xbb, M1543_PNP_CONFIG);
-
-
-	/* Initialize the 8259 PIC in the M1543 */
-	i8259_init();
-
-	/* Enable the interrupt cascade from M1543 */
-	nile4_enable_irq(NILE4_INT_INTC);
-
-	/* request io ports */
-	if (request_resource(&ioport_resource, &m1543_ioport.m1543_config)
-	    || request_resource(&ioport_resource, &m1543_ioport.pic_elcr)) {
-		printk("m1543_irq_setup : requesting io ports failed.\n");
-		for (;;);
-	}
-}
-
-static void nile4_irq_setup(void)
-{
-	int i;
-
-	/* Map all interrupts to CPU int #0 */
-	nile4_map_irq_all(0);
-
-	/* PCI INTA#-E# must be level triggered */
-	nile4_set_pci_irq_level_or_edge(0, 1);
-	nile4_set_pci_irq_level_or_edge(1, 1);
-	nile4_set_pci_irq_level_or_edge(2, 1);
-	nile4_set_pci_irq_level_or_edge(3, 1);
-
-	/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
-	nile4_set_pci_irq_polarity(0, 0);
-	nile4_set_pci_irq_polarity(1, 0);
-	nile4_set_pci_irq_polarity(2, 1);
-	nile4_set_pci_irq_polarity(3, 0);
-
-	for (i = 0; i < 16; i++)
-		nile4_clear_irq(i);
-
-	/* Enable CPU int #0 */
-	nile4_enable_irq_output(0);
-
-	/* memory resource acquire in ddb_setup */
-}
-
-
-/*
- * IRQ2 is cascade interrupt to second interrupt controller
- */
-static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL };
-
-
-void disable_irq(unsigned int irq_nr)
-{
-	if (is_i8259_irq(irq_nr))
-		i8259_disable_irq(irq_nr);
-	else
-		nile4_disable_irq(irq_to_nile4(irq_nr));
-}
-
-void enable_irq(unsigned int irq_nr)
-{
-	if (is_i8259_irq(irq_nr))
-		i8259_enable_irq(irq_nr);
-	else
-		nile4_enable_irq(irq_to_nile4(irq_nr));
-}
-
-int table[16] = { 0, };
-
-void ddb_local0_irqdispatch(struct pt_regs *regs)
-{
-	u32 mask;
-	int nile4_irq;
-#if 0
-	volatile static int nesting = 0;
-	if (nesting++ == 0)
-		ddb5476_led_d3(1);
-	ddb5476_led_hex(nesting < 16 ? nesting : 15);
-#endif
-
-	mask = nile4_get_irq_stat(0);
-	nile4_clear_irq_mask(mask);
-
-	/* Handle the timer interrupt first */
-	if (mask & (1 << NILE4_INT_GPT)) {
-		nile4_disable_irq(NILE4_INT_GPT);
-		do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
-		nile4_enable_irq(NILE4_INT_GPT);
-		mask &= ~(1 << NILE4_INT_GPT);
-	}
-	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
-		if (mask & 1) {
-			nile4_disable_irq(nile4_irq);
-			if (nile4_irq == NILE4_INT_INTC) {
-				int i8259_irq = nile4_i8259_iack();
-				i8259_do_irq(i8259_irq, regs);
-			} else {
-				do_IRQ(nile4_to_irq(nile4_irq), regs);
-			}
-			nile4_enable_irq(nile4_irq);
-		}
-#if 0
-	if (--nesting == 0)
-		ddb5476_led_d3(0);
-	ddb5476_led_hex(nesting < 16 ? nesting : 15);
-#endif
-}
-
-void ddb_local1_irqdispatch(void)
-{
-	printk("ddb_local1_irqdispatch called\n");
-}
-
-void ddb_buserror_irq(void)
-{
-	printk("ddb_buserror_irq called\n");
-}
-
-void ddb_8254timer_irq(void)
-{
-	printk("ddb_8254timer_irq called\n");
-}
-
-void ddb_phantom_irq(unsigned long cause)
-{
-	printk("phantom interrupts detected : \n");
-	printk("\tcause \t\t0x%08x\n", cause);
-	printk("\tcause reg\t0x%08x\n",
-	       read_32bit_cp0_register(CP0_CAUSE));
-	printk("\tstatus reg\t0x%08x\n",
-	       read_32bit_cp0_register(CP0_STATUS));
-}
-
-void __init ddb_irq_setup(void)
-{
-#ifdef CONFIG_REMOTE_DEBUG
-	printk("Wait for gdb client connection ...\n");
-	set_debug_traps();
-	breakpoint();		/* you may move this line to whereever you want :-) */
-#endif
-	i8259_setup_irq(2, &irq2);
-
-	nile4_irq_setup();
-	m1543_irq_setup();
-
-	/* we pin #0 - #4 (no internal timer) */
-	change_cp0_status(ST0_IM,
-	                  IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
-
-	set_except_vector(0, ddbIRQ);
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/nile4.c linux/arch/mips/ddb5476/nile4.c
--- linux.orig/arch/mips/ddb5476/nile4.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5476/nile4.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,293 +0,0 @@
-/*
- *  arch/mips/ddb5074/nile4.c -- NEC Vrc-5074 Nile 4 support routines
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <asm/nile4.h>
-
-
-/*
- *  Physical Device Address Registers
- *
- *  Note: 32 bit addressing only!
- */
-void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
-		    int on_memory_bus, int visible)
-{
-	u32 maskbits;
-	u32 widthbits;
-
-	if (pdar > NILE4_BOOTCS || (pdar & 7)) {
-		printk("nile4_set_pdar: invalid pdar %d\n", pdar);
-		return;
-	}
-	if (pdar == NILE4_INTCS && size != 0x00200000) {
-		printk("nile4_set_pdar: INTCS size must be 2 MB\n");
-		return;
-	}
-	switch (size) {
-#if 0				/* We don't support 4 GB yet */
-	case 0x100000000:	/* 4 GB */
-		maskbits = 4;
-		break;
-#endif
-	case 0x80000000:	/* 2 GB */
-		maskbits = 5;
-		break;
-	case 0x40000000:	/* 1 GB */
-		maskbits = 6;
-		break;
-	case 0x20000000:	/* 512 MB */
-		maskbits = 7;
-		break;
-	case 0x10000000:	/* 256 MB */
-		maskbits = 8;
-		break;
-	case 0x08000000:	/* 128 MB */
-		maskbits = 9;
-		break;
-	case 0x04000000:	/* 64 MB */
-		maskbits = 10;
-		break;
-	case 0x02000000:	/* 32 MB */
-		maskbits = 11;
-		break;
-	case 0x01000000:	/* 16 MB */
-		maskbits = 12;
-		break;
-	case 0x00800000:	/* 8 MB */
-		maskbits = 13;
-		break;
-	case 0x00400000:	/* 4 MB */
-		maskbits = 14;
-		break;
-	case 0x00200000:	/* 2 MB */
-		maskbits = 15;
-		break;
-	case 0:		/* OFF */
-		maskbits = 0;
-		break;
-	default:
-		printk("nile4_set_pdar: unsupported size %p\n",
-		       (void *) size);
-		return;
-	}
-	switch (width) {
-	case 8:
-		widthbits = 0;
-		break;
-	case 16:
-		widthbits = 1;
-		break;
-	case 32:
-		widthbits = 2;
-		break;
-	case 64:
-		widthbits = 3;
-		break;
-	default:
-		printk("nile4_set_pdar: unsupported width %d\n", width);
-		return;
-	}
-	nile4_out32(pdar, maskbits | (on_memory_bus ? 0x10 : 0) |
-		    (visible ? 0x20 : 0) | (widthbits << 6) |
-		    (phys & 0xffe00000));
-	nile4_out32(pdar + 4, 0);
-	/*
-	 * When programming a PDAR, the register should be read immediately
-	 * after writing it. This ensures that address decoders are properly
-	 * configured.
-	 */
-	nile4_in32(pdar);
-	nile4_in32(pdar + 4);
-}
-
-
-/*
- *  PCI Master Registers
- *
- *  Note: 32 bit addressing only!
- */
-void nile4_set_pmr(u32 pmr, u32 type, u32 addr)
-{
-	if (pmr != NILE4_PCIINIT0 && pmr != NILE4_PCIINIT1) {
-		printk("nile4_set_pmr: invalid pmr %d\n", pmr);
-		return;
-	}
-	switch (type) {
-	case NILE4_PCICMD_IACK:	/* PCI Interrupt Acknowledge */
-	case NILE4_PCICMD_IO:	/* PCI I/O Space */
-	case NILE4_PCICMD_MEM:	/* PCI Memory Space */
-	case NILE4_PCICMD_CFG:	/* PCI Configuration Space */
-		break;
-	default:
-		printk("nile4_set_pmr: invalid type %d\n", type);
-		return;
-	}
-	nile4_out32(pmr, (type << 1) | 0x10 | (addr & 0xffe00000));
-	nile4_out32(pmr + 4, 0);
-}
-
-
-/*
- *  Interrupt Programming
- */
-void nile4_map_irq(int nile4_irq, int cpu_irq)
-{
-	u32 offset, t;
-
-	offset = NILE4_INTCTRL;
-	if (nile4_irq >= 8) {
-		offset += 4;
-		nile4_irq -= 8;
-	}
-	t = nile4_in32(offset);
-	t &= ~(7 << (nile4_irq * 4));
-	t |= cpu_irq << (nile4_irq * 4);
-	nile4_out32(offset, t);
-}
-
-void nile4_map_irq_all(int cpu_irq)
-{
-	u32 all, t;
-
-	all = cpu_irq;
-	all |= all << 4;
-	all |= all << 8;
-	all |= all << 16;
-	t = nile4_in32(NILE4_INTCTRL);
-	t &= 0x88888888;
-	t |= all;
-	nile4_out32(NILE4_INTCTRL, t);
-	t = nile4_in32(NILE4_INTCTRL + 4);
-	t &= 0x88888888;
-	t |= all;
-	nile4_out32(NILE4_INTCTRL + 4, t);
-}
-
-void nile4_enable_irq(int nile4_irq)
-{
-	u32 offset, t;
-
-	offset = NILE4_INTCTRL;
-	if (nile4_irq >= 8) {
-		offset += 4;
-		nile4_irq -= 8;
-	}
-	t = nile4_in32(offset);
-	t |= 8 << (nile4_irq * 4);
-	nile4_out32(offset, t);
-}
-
-void nile4_disable_irq(int nile4_irq)
-{
-	u32 offset, t;
-
-	offset = NILE4_INTCTRL;
-	if (nile4_irq >= 8) {
-		offset += 4;
-		nile4_irq -= 8;
-	}
-	t = nile4_in32(offset);
-	t &= ~(8 << (nile4_irq * 4));
-	nile4_out32(offset, t);
-}
-
-void nile4_disable_irq_all(void)
-{
-	nile4_out32(NILE4_INTCTRL, 0);
-	nile4_out32(NILE4_INTCTRL + 4, 0);
-}
-
-u16 nile4_get_irq_stat(int cpu_irq)
-{
-	return nile4_in16(NILE4_INTSTAT0 + cpu_irq * 2);
-}
-
-void nile4_enable_irq_output(int cpu_irq)
-{
-	u32 t;
-
-	t = nile4_in32(NILE4_INTSTAT1 + 4);
-	t |= 1 << (16 + cpu_irq);
-	nile4_out32(NILE4_INTSTAT1, t);
-}
-
-void nile4_disable_irq_output(int cpu_irq)
-{
-	u32 t;
-
-	t = nile4_in32(NILE4_INTSTAT1 + 4);
-	t &= ~(1 << (16 + cpu_irq));
-	nile4_out32(NILE4_INTSTAT1, t);
-}
-
-void nile4_set_pci_irq_polarity(int pci_irq, int high)
-{
-	u32 t;
-
-	t = nile4_in32(NILE4_INTPPES);
-	if (high)
-		t &= ~(1 << (pci_irq * 2));
-	else
-		t |= 1 << (pci_irq * 2);
-	nile4_out32(NILE4_INTPPES, t);
-}
-
-void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
-{
-	u32 t;
-
-	t = nile4_in32(NILE4_INTPPES);
-	if (level)
-		t |= 2 << (pci_irq * 2);
-	else
-		t &= ~(2 << (pci_irq * 2));
-	nile4_out32(NILE4_INTPPES, t);
-}
-
-void nile4_clear_irq(int nile4_irq)
-{
-	nile4_out32(NILE4_INTCLR, 1 << nile4_irq);
-}
-
-void nile4_clear_irq_mask(u32 mask)
-{
-	nile4_out32(NILE4_INTCLR, mask);
-}
-
-u8 nile4_i8259_iack(void)
-{
-	u8 irq;
-
-	/* Set window 0 for interrupt acknowledge */
-	nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IACK, 0);
-	irq = *(volatile u8 *) NILE4_PCI_IACK_BASE;
-	/* Set window 0 for PCI I/O space */
-	nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0);
-	return irq;
-}
-
-#if 0
-void nile4_dump_irq_status(void)
-{
-	printk("CPUSTAT = %p:%p\n", (void *) nile4_in32(NILE4_CPUSTAT + 4),
-	       (void *) nile4_in32(NILE4_CPUSTAT));
-	printk("INTCTRL = %p:%p\n", (void *) nile4_in32(NILE4_INTCTRL + 4),
-	       (void *) nile4_in32(NILE4_INTCTRL));
-	printk("INTSTAT0 = %p:%p\n",
-	       (void *) nile4_in32(NILE4_INTSTAT0 + 4),
-	       (void *) nile4_in32(NILE4_INTSTAT0));
-	printk("INTSTAT1 = %p:%p\n",
-	       (void *) nile4_in32(NILE4_INTSTAT1 + 4),
-	       (void *) nile4_in32(NILE4_INTSTAT1));
-	printk("INTCLR = %p:%p\n", (void *) nile4_in32(NILE4_INTCLR + 4),
-	       (void *) nile4_in32(NILE4_INTCLR));
-	printk("INTPPES = %p:%p\n", (void *) nile4_in32(NILE4_INTPPES + 4),
-	       (void *) nile4_in32(NILE4_INTPPES));
-}
-#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/pci.c linux/arch/mips/ddb5476/pci.c
--- linux.orig/arch/mips/ddb5476/pci.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5476/pci.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,499 +0,0 @@
-/*
- *  arch/mips/ddb5476/pci.c -- NEC DDB Vrc-5074 PCI access routines
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Albert Dorofeev <albert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-
-#include <asm-mips/nile4.h>
-
-static u32 nile4_pre_pci_access0(int slot_num)
-{
-	u32 pci_addr = 0;
-	u32 virt_addr = NILE4_PCI_CFG_BASE;
-
-	/* work around the bug for Vrc5476 */
-	if (slot_num == 13)
-		return NILE4_BASE + NILE4_PCI_BASE;
-
-	/* Set window 1 address 08000000 - 32 bit - 128 MB (PCI config space) */
-	nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x08000000, 32, 0,
-		       0);
-
-	// [jsun] we start scanning from addr:10, 
-	// with 128M we can go up to addr:26 (slot 16)
-	if (slot_num <= 16) {
-		virt_addr += 0x00000400 << slot_num;
-	} else {
-		/* for high slot, we have to set higher PCI base addr */
-		pci_addr = 0x00000400 << slot_num;
-	}
-	nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr);
-	return virt_addr;
-}
-
-static void nile4_post_pci_access0(void)
-{
-	/*
-	 * Set window 1 back to address 08000000 - 32 bit - 128 MB
-	 * (PCI IO space)
-	 */
-	nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE),
-		       0x08000000, 32, 1, 1);
-	// nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
-	nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000);
-}
-
-
-static int nile4_pci_read_config_dword(struct pci_dev *dev,
-				       int where, u32 * val)
-{
-	int slot_num, func_num;
-	u32 base;
-	u32 addr;
-
-	/*
-	 *  Do we need to generate type 1 configure transaction?
-	 */
-	if (dev->bus->number) {
-		/* FIXME - not working yet */
-		return PCIBIOS_FUNC_NOT_SUPPORTED;
-
-		/*
-		 * the largest type 1 configuration addr is 16M, < 256M
-		 * config space
-		 */
-		slot_num = 0;
-		addr =
-		    (dev->bus->number << 16) | (dev->devfn <
-						8) | where | 1;
-	} else {
-		slot_num = PCI_SLOT(dev->devfn);
-		func_num = PCI_FUNC(dev->devfn);
-		addr = (func_num << 8) + where;
-	}
-
-	base = nile4_pre_pci_access0(slot_num);
-	*val = *(volatile u32 *) (base + addr);
-	nile4_post_pci_access0();
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int nile4_pci_write_config_dword(struct pci_dev *dev, int where,
-					u32 val)
-{
-	int slot_num, func_num;
-	u32 base;
-	u32 addr;
-
-	/*
-	 *  Do we need to generate type 1 configure transaction?
-	 */
-	if (dev->bus->number) {
-		/* FIXME - not working yet */
-		return PCIBIOS_FUNC_NOT_SUPPORTED;
-
-		/* the largest type 1 configuration addr is 16M, < 256M config space */
-		slot_num = 0;
-		addr =
-		    (dev->bus->number << 16) | (dev->devfn <
-						8) | where | 1;
-	} else {
-		slot_num = PCI_SLOT(dev->devfn);
-		func_num = PCI_FUNC(dev->devfn);
-		addr = (func_num << 8) + where;
-	}
-
-	base = nile4_pre_pci_access0(slot_num);
-	*(volatile u32 *) (base + addr) = val;
-	nile4_post_pci_access0();
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int nile4_pci_read_config_word(struct pci_dev *dev, int where,
-				      u16 * val)
-{
-	int status;
-	u32 result;
-
-	status = nile4_pci_read_config_dword(dev, where & ~3, &result);
-	if (status != PCIBIOS_SUCCESSFUL)
-		return status;
-	if (where & 2)
-		result >>= 16;
-	*val = result & 0xffff;
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int nile4_pci_read_config_byte(struct pci_dev *dev, int where,
-				      u8 * val)
-{
-	int status;
-	u32 result;
-
-	status = nile4_pci_read_config_dword(dev, where & ~3, &result);
-	if (status != PCIBIOS_SUCCESSFUL)
-		return status;
-	if (where & 1)
-		result >>= 8;
-	if (where & 2)
-		result >>= 16;
-	*val = result & 0xff;
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int nile4_pci_write_config_word(struct pci_dev *dev, int where,
-				       u16 val)
-{
-	int status, shift = 0;
-	u32 result;
-
-	status = nile4_pci_read_config_dword(dev, where & ~3, &result);
-	if (status != PCIBIOS_SUCCESSFUL)
-		return status;
-	if (where & 2)
-		shift += 16;
-	result &= ~(0xffff << shift);
-	result |= val << shift;
-	return nile4_pci_write_config_dword(dev, where & ~3, result);
-}
-
-static int nile4_pci_write_config_byte(struct pci_dev *dev, int where,
-				       u8 val)
-{
-	int status, shift = 0;
-	u32 result;
-
-	status = nile4_pci_read_config_dword(dev, where & ~3, &result);
-	if (status != PCIBIOS_SUCCESSFUL)
-		return status;
-	if (where & 2)
-		shift += 16;
-	if (where & 1)
-		shift += 8;
-	result &= ~(0xff << shift);
-	result |= val << shift;
-	return nile4_pci_write_config_dword(dev, where & ~3, result);
-}
-
-struct pci_ops nile4_pci_ops = {
-	nile4_pci_read_config_byte,
-	nile4_pci_read_config_word,
-	nile4_pci_read_config_dword,
-	nile4_pci_write_config_byte,
-	nile4_pci_write_config_word,
-	nile4_pci_write_config_dword
-};
-
-struct {
-	struct resource ram;
-	struct resource flash;
-	struct resource isa_io;
-	struct resource pci_io;
-	struct resource isa_mem;
-	struct resource pci_mem;
-	struct resource nile4;
-	struct resource boot;
-} ddb5476_resources = {
-	// { "RAM", 0x00000000, 0x03ffffff, IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 },
-	{
-	"RAM", 0x00000000, 0x03ffffff, IORESOURCE_MEM}, {
-	"Flash ROM", 0x04000000, 0x043fffff}, {
-	"Nile4 ISA I/O", 0x06000000, 0x060fffff}, {
-	"Nile4 PCI I/O", 0x06100000, 0x07ffffff}, {
-	"Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM}, {
-	"Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM},
-	    // { "Nile4 ctrl", 0x1fa00000, 0x1fbfffff, IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 },
-	{
-	"Nile4 ctrl", 0x1fa00000, 0x1fbfffff, IORESOURCE_MEM}, {
-	"Boot ROM", 0x1fc00000, 0x1fffffff}
-};
-
-struct resource M5229_resources[5] = {
-	{"M5229 BAR0", 0x1f0, 0x1f3, IORESOURCE_IO},
-	{"M5229 BAR1", 0x3f4, 0x3f7, IORESOURCE_IO},
-	{"M5229 BAR2", 0x170, 0x173, IORESOURCE_IO},
-	{"M5229 BAR3", 0x374, 0x377, IORESOURCE_IO},
-	{"M5229 BAR4", 0xf000, 0xf00f, IORESOURCE_IO}
-};
-
-static void __init ddb5476_pci_fixup(void)
-{
-	struct pci_dev *dev;
-
-	pci_for_each_dev(dev) {
-		if (dev->vendor == PCI_VENDOR_ID_NEC &&
-		    dev->device == PCI_DEVICE_ID_NEC_VRC5476) {
-			/*
-			 * The first 64-bit PCI base register should point to
-			 * the Nile4 control registers. Unfortunately this
-			 * isn't the case, so we fix it ourselves. This allows
-			 * the serial driver to find the UART.
-			 */
-			dev->resource[0] = ddb5476_resources.nile4;
-			request_resource(&iomem_resource,
-					 &dev->resource[0]);
-			/*
-			 * The second 64-bit PCI base register points to the
-			 * first memory bank. Unfortunately the address is
-			 * wrong, so we fix it (again).
-			 */
-
-			/* [jsun] We cannot request the resource anymore,
-			 * because kernel/setup.c has already reserved "System 
-			 * RAM" resource at the same spot.  
-			 * The fundamental problem here is that PCI host 
-			 * controller should not put system RAM mapping in BAR
-			 * and make subject to PCI resource assignement.
-			 * Current fix is a total hack.  We set parent to 1 so
-                         * so that PCI resource assignement code is fooled to 
-                         * think the resource is assigned, and will not attempt
-                         * to mess with it.
-			 */
-			dev->resource[2] = ddb5476_resources.ram;
-			if (request_resource(&iomem_resource,
-			                     &dev->resource[2]) ) {
-				dev->resource[2].parent = 0x1;
-                        }
-
-		} else if (dev->vendor == PCI_VENDOR_ID_AL
-			   && dev->device == PCI_DEVICE_ID_AL_M7101) {
-			/*
-			 * It's nice to have the LEDs on the GPIO pins
-			 * available for debugging
-			 */
-			extern struct pci_dev *pci_pmu;
-			u8 t8;
-
-			pci_pmu = dev;	/* for LEDs D2 and D3 */
-			/* Program the lines for LEDs D2 and D3 to output */
-			nile4_pci_read_config_byte(dev, 0x7d, &t8);
-			t8 |= 0xc0;
-			nile4_pci_write_config_byte(dev, 0x7d, t8);
-			/* Turn LEDs D2 and D3 off */
-			nile4_pci_read_config_byte(dev, 0x7e, &t8);
-			t8 |= 0xc0;
-			nile4_pci_write_config_byte(dev, 0x7e, t8);
-		} else if (dev->vendor == PCI_VENDOR_ID_AL &&
-			   dev->device == 0x5229) {
-			int i;
-			for (i = 0; i < 5; i++) {
-				dev->resource[i] = M5229_resources[i];
-				request_resource(&ioport_resource,
-						 &dev->resource[i]);
-			}
-		}
-	}
-}
-
-static void __init pcibios_fixup_irqs(void)
-{
-	struct pci_dev *dev;
-	int slot_num;
-
-	pci_for_each_dev(dev) {
-		slot_num = PCI_SLOT(dev->devfn);
-		switch (slot_num) {
-		case 3:	/* re-programmed to USB */
-			dev->irq = 9;	/* hard-coded; see irq.c */
-			break;
-		case 4:	/* re-programmed to PMU */
-			dev->irq = 10;	/* hard-coded; see irq.c */
-			break;
-		case 6:	/* on-board pci-pci bridge */
-			dev->irq = 0xff;
-			break;
-		case 7:	/* on-board ether */
-			dev->irq = nile4_to_irq(NILE4_INT_INTB);
-			break;
-		case 8:	/* ISA-PCI bridge  */
-			dev->irq = nile4_to_irq(NILE4_INT_INTC);
-			break;
-		case 9:	/* ext slot #3 */
-			dev->irq = nile4_to_irq(NILE4_INT_INTD);
-			break;
-		case 10:	/* ext slot #4 */
-			dev->irq = nile4_to_irq(NILE4_INT_INTA);
-			break;
-		case 13:	/* Vrc5476 */
-			dev->irq = 0xff;
-			break;
-		case 14:	/* HD controller, M5229 */
-			dev->irq = 14;
-			break;
-		default:
-			printk
-			    ("JSUN : in pcibios_fixup_irqs - unkown slot %d\n",
-			     slot_num);
-			panic
-			    ("JSUN : in pcibios_fixup_irqs - unkown slot.\n");
-		}
-	}
-}
-
-void __init pcibios_init(void)
-{
-	printk("PCI: Emulate bios initialization \n");
-	/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
-	*(long *) (NILE4_BASE + NILE4_BAR0) = 0x8;
-
-	printk("PCI: Probing PCI hardware\n");
-	ioport_resource.end = 0x1ffffff;	/*  32 MB */
-	iomem_resource.end = 0x1fffffff;	/* 512 MB */
-
-	/* `ram' and `nile4' are requested through the Nile4 pci_dev */
-	request_resource(&iomem_resource, &ddb5476_resources.flash);
-	request_resource(&iomem_resource, &ddb5476_resources.isa_io);
-	request_resource(&iomem_resource, &ddb5476_resources.pci_io);
-	request_resource(&iomem_resource, &ddb5476_resources.isa_mem);
-	request_resource(&iomem_resource, &ddb5476_resources.pci_mem);
-	request_resource(&iomem_resource, &ddb5476_resources.boot);
-
-	pci_scan_bus(0, &nile4_pci_ops, NULL);
-	ddb5476_pci_fixup();
-	pci_assign_unassigned_resources();
-	pcibios_fixup_irqs();
-}
-
-void __init pcibios_fixup_bus(struct pci_bus *bus)
-{
-	/* [jsun] we don't know how to fix sub-buses yet */
-	if (bus->number == 0) {
-		bus->resource[1] = &ddb5476_resources.pci_mem;
-	}
-}
-
-char *pcibios_setup(char *str)
-{
-	return str;
-}
-
-void __init pcibios_update_irq(struct pci_dev *dev, int irq)
-{
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-}
-
-void __init pcibios_fixup_pbus_ranges(struct pci_bus *bus,
-				      struct pbus_set_ranges_data *ranges)
-{
-	/*
-	 * our caller figure out range by going through the dev structures.  
-	 * I guess this is the place to fix things up if the bus is using a 
-	 * different view of the addressing space.
-	 */
-
-#if 0	/*  original DDB5074 code */
-	   if (bus->number == 0) {
-	   ranges->io_start -= bus->resource[0]->start;
-	   ranges->io_end -= bus->resource[0]->start;
-	   ranges->mem_start -= bus->resource[1]->start;
-	   ranges->mem_end -= bus->resource[1]->start;
-	   }
-#endif
-}
-
-int pcibios_enable_resources(struct pci_dev *dev)
-{
-	u16 cmd, old_cmd;
-	int idx;
-	struct resource *r;
-
-	/*
-	 *  Don't touch the Nile 4
-	 */
-	if (dev->vendor == PCI_VENDOR_ID_NEC &&
-	    dev->device == PCI_DEVICE_ID_NEC_VRC5476) return 0;
-
-	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-	old_cmd = cmd;
-	for (idx = 0; idx < 6; idx++) {
-		r = &dev->resource[idx];
-		if (!r->start && r->end) {
-			printk(KERN_ERR "PCI: Device %s not available because "
-			       "of resource collisions\n", dev->slot_name);
-			return -EINVAL;
-		}
-		if (r->flags & IORESOURCE_IO)
-			cmd |= PCI_COMMAND_IO;
-		if (r->flags & IORESOURCE_MEM)
-			cmd |= PCI_COMMAND_MEMORY;
-	}
-	if (cmd != old_cmd) {
-		printk("PCI: Enabling device %s (%04x -> %04x)\n",
-		       dev->slot_name, old_cmd, cmd);
-		pci_write_config_word(dev, PCI_COMMAND, cmd);
-	}
-	return 0;
-}
-
-int pcibios_enable_device(struct pci_dev *dev)
-{
-	return pcibios_enable_resources(dev);
-}
-
-void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
-			     struct resource *res, int resource)
-{
-	u32 new, check;
-	int reg;
-
-	new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
-	if (resource < 6) {
-		reg = PCI_BASE_ADDRESS_0 + 4 * resource;
-	} else if (resource == PCI_ROM_RESOURCE) {
-		res->flags |= PCI_ROM_ADDRESS_ENABLE;
-		reg = dev->rom_base_reg;
-	} else {
-		/*
-		 * Somebody might have asked allocation of a non-standard
-		 * resource
-		 */
-		return;
-	}
-
-	pci_write_config_dword(dev, reg, new);
-	pci_read_config_dword(dev, reg, &check);
-	if ((new ^ check) &
-	    ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
-	     PCI_BASE_ADDRESS_MEM_MASK)) {
-		printk(KERN_ERR "PCI: Error while updating region "
-		       "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
-		       new, check);
-	}
-}
-
-void pcibios_align_resource(void *data, struct resource *res,
-			    unsigned long size)
-{
-	struct pci_dev *dev = data;
-
-	if (res->flags & IORESOURCE_IO) {
-		unsigned long start = res->start;
-
-		/* We need to avoid collisions with `mirrored' VGA ports
-		   and other strange ISA hardware, so we always want the
-		   addresses kilobyte aligned.  */
-		if (size > 0x100) {
-			printk(KERN_ERR "PCI: I/O Region %s/%d too large"
-			       " (%ld bytes)\n", dev->slot_name,
-			       dev->resource - res, size);
-		}
-
-		start = (start + 1024 - 1) & ~(1024 - 1);
-		res->start = start;
-	}
-}
-
-unsigned __init int pcibios_assign_all_busses(void)
-{
-	return 1;
-}
-
-struct pci_fixup pcibios_fixups[] = { {0} };
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/prom.c linux/arch/mips/ddb5476/prom.c
--- linux.orig/arch/mips/ddb5476/prom.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5476/prom.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,43 +0,0 @@
-/*
- *  arch/mips/ddb5476/prom.c -- NEC DDB Vrc-5476 PROM routines
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- *
- *   	Jun Sun - modified for DDB5476.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-
-
-char arcs_cmdline[COMMAND_LINE_SIZE];
-
-/* [jsun@junsun.net] PMON passes arguments in C main() style */
-void __init prom_init(int argc, const char **arg)
-{
-	int i;
-
-	/* arg[0] is "g", the rest is boot parameters */
-	arcs_cmdline[0] = '\0';
-	for (i = 1; i < argc; i++) {
-		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
-		    >= sizeof(arcs_cmdline))
-			break;
-		strcat(arcs_cmdline, arg[i]);
-		strcat(arcs_cmdline, " ");
-	}
-
-	mips_machgroup = MACH_GROUP_NEC_DDB;
-	mips_machtype = MACH_NEC_DDB5476;
-	/* 64 MB non-upgradable */
-	add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/setup.c linux/arch/mips/ddb5476/setup.c
--- linux.orig/arch/mips/ddb5476/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5476/setup.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,393 +0,0 @@
-/*
- *  arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/kbd_ll.h>
-#include <linux/kernel.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/console.h>
-#include <linux/sched.h>
-#include <linux/mc146818rtc.h>
-#include <linux/pc_keyb.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-
-#include <asm/addrspace.h>
-#include <asm/bcache.h>
-#include <asm/keyboard.h>
-#include <asm/irq.h>
-#include <asm/reboot.h>
-#include <asm/gdb-stub.h>
-#include <asm/nile4.h>
-#include <asm/time.h>
-
-
-#ifdef CONFIG_REMOTE_DEBUG
-extern void rs_kgdb_hook(int);
-extern void breakpoint(void);
-#endif
-
-#if defined(CONFIG_SERIAL_CONSOLE)
-extern void console_setup(char *);
-#endif
-
-extern struct ide_ops std_ide_ops;
-extern struct rtc_ops ddb_rtc_ops;
-extern struct kbd_ops std_kbd_ops;
-
-static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
-
-static void ddb_machine_restart(char *command)
-{
-	u32 t;
-
-	/* PCI cold reset */
-	t = nile4_in32(NILE4_PCICTRL + 4);
-	t |= 0x40000000;
-	nile4_out32(NILE4_PCICTRL + 4, t);
-	/* CPU cold reset */
-	t = nile4_in32(NILE4_CPUSTAT);
-	t |= 1;
-	nile4_out32(NILE4_CPUSTAT, t);
-	/* Call the PROM */
-	back_to_prom();
-}
-
-static void ddb_machine_halt(void)
-{
-	printk("DDB Vrc-5476 halted.\n");
-	while (1);
-}
-
-static void ddb_machine_power_off(void)
-{
-	printk("DDB Vrc-5476 halted. Please turn off the power.\n");
-	while (1);
-}
-
-extern void ddb_irq_setup(void);
-
-static void __init ddb_time_init(struct irqaction *irq)
-{
-	printk("ddb_time_init invoked.\n");
-	mips_counter_frequency = 83000000;
-}
-
-static void __init ddb_timer_setup(struct irqaction *irq)
-{
-	unsigned int count;
-
-	/* we are using the cpu counter for timer interrupts */
-	i8259_setup_irq(0, irq);
-	set_cp0_status(IE_IRQ5);
-
-	/* to generate the first timer interrupt */
-	count = read_32bit_cp0_register(CP0_COUNT);
-	write_32bit_cp0_register(CP0_COMPARE, count + 1000);
-
-#if 0		/* the old way to do timer interrupt */
-	/* set the clock to 100 Hz */
-	nile4_out32(NILE4_T2CTRL, 830000);
-	/* enable the General-Purpose Timer */
-	nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
-	/* reset timer */
-	nile4_out32(NILE4_T2CNTR, 0);
-	/* enable interrupt */
-	nile4_enable_irq(NILE4_INT_GPT);
-	i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
-#endif
-}
-
-static struct {
-	struct resource dma1;
-	struct resource pic1;
-	struct resource timer;
-	struct resource rtc;
-	struct resource dma_page_reg;
-	struct resource pic2;
-	struct resource dma2;
-} ddb5476_ioport = {
-	{
-	"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
-	"pic1", 0x20, 0x3f, IORESOURCE_BUSY}, {
-	"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
-	"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
-	"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
-	"pic2", 0xa0, 0xbf, IORESOURCE_BUSY}, {
-	"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
-};
-
-static struct {
-	struct resource nile4;
-} ddb5476_iomem = {
-	{ "Nile 4", NILE4_BASE, NILE4_BASE + NILE4_SIZE - 1, IORESOURCE_BUSY}
-};
-
-void __init ddb_setup(void)
-{
-	extern int panic_timeout;
-
-	irq_setup = ddb_irq_setup;
-	mips_io_port_base = NILE4_PCI_IO_BASE;
-	isa_slot_offset = NILE4_PCI_MEM_BASE;
-
-	board_time_init = ddb_time_init;
-	board_timer_setup = ddb_timer_setup;
-
-	_machine_restart = ddb_machine_restart;
-	_machine_halt = ddb_machine_halt;
-	_machine_power_off = ddb_machine_power_off;
-
-	/* request io port/mem resources  */
-	if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
-	    request_resource(&ioport_resource, &ddb5476_ioport.pic1) ||
-	    request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
-	    request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
-	    request_resource(&ioport_resource,
-			     &ddb5476_ioport.dma_page_reg)
-	    || request_resource(&ioport_resource, &ddb5476_ioport.pic2)
-	    || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
-	    || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
-		printk
-		    ("ddb_setup - requesting oo port resources failed.\n");
-		for (;;);
-	}
-#ifdef CONFIG_BLK_DEV_IDE
-	ide_ops = &std_ide_ops;
-#endif
-	rtc_ops = &ddb_rtc_ops;
-
-#ifdef CONFIG_PC_KEYB
-	kbd_ops = &std_kbd_ops;
-#endif
-
-	/* Reboot on panic */
-	panic_timeout = 180;
-
-	/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
-	/* *(long*)0xbfa00218 = 0x8; */
-
-#ifdef CONFIG_FB
-	conswitchp = &dummy_con;
-#endif
-
-
-	/* board initialization stuff - non-fundamental, but need to be set
-	 * before kernel runs */
-
-	/* setup I/O space */
-	nile4_set_pdar(NILE4_PCIW0,
-		       PHYSADDR(NILE4_PCI_IO_BASE), 0x02000000, 32, 0, 0);
-	nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0);
-
-	/* map config space to 0xa8000000, 128MB */
-	nile4_set_pdar(NILE4_PCIW1,
-		       PHYSADDR(NILE4_PCI_CFG_BASE), 0x08000000, 32, 0, 0);
-	nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, 0x0);
-
-	/* ----- M1543 PCI setup ------ */
-
-	/* we know M1543 PCI-ISA controller is at addr:18 */
-	/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
-	*(volatile unsigned char *) 0xa8040072 &= 0xf0;
-	*(volatile unsigned char *) 0xa8040072 |= 0xa;
-
-	/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
-	 * no IOCHRDY signal, (bit 7 - 1)
-	 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
-	 * Bypass USB Master INTAJ level to edge conversion (bit 4 - 0)
-	 */
-	*(unsigned char *) 0xa8040074 = 0xc1;
-
-	/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
-	 * SCI routing to IRQ 13 disabled (bit 7 - 1)
-	 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
-	 */
-	*(unsigned char *) 0xa8040076 = 0x83;
-
-	/* setup IDE controller
-	 * enable IDE controller (bit 6 - 1)
-	 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
-	 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
-	 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
-	 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
-	 */
-	// *(unsigned char*)0xa8040058 = 0x71;
-	// *(unsigned char*)0xa8040058 = 0x79;
-	// *(unsigned char*)0xa8040058 = 0x74;              // use SIRQ, primary tri-state
-	*(unsigned char *) 0xa8040058 = 0x75;	// primary tri-state
-
-#if 0
-	/* this is not necessary if M5229 does not use SIRQ */
-	*(unsigned char *) 0xa8040044 = 0x0d;	// primary to IRQ 14
-	*(unsigned char *) 0xa8040075 = 0x0d;	// secondary to IRQ 14
-#endif
-
-	/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
-	/* M5229 IDSEL is addr:24; see above setting */
-	*(unsigned char *) 0xa9000050 |= 0x1;
-
-	/* enable bus master (bit 2)  and IO decoding  (bit 0) */
-	*(unsigned char *) 0xa9000004 |= 0x5;
-
-	/* enable native, copied from arch/ppc/k2boot/head.S */
-	/* TODO - need volatile, need to be portable */
-	*(unsigned char *) 0xa9000009 = 0xff;
-
-	/* ----- end of M1543 PCI setup ------ */
-
-	/* ----- reset on-board ether chip  ------ */
-	*((volatile u32 *) 0xa8020004) |= 1;	/* decode I/O */
-	*((volatile u32 *) 0xa8020010) = 0;	/* set BAR address */
-
-	/* send reset command */
-	*((volatile u32 *) 0xa6000000) = 1;	/* do a soft reset */
-
-	/* disable ether chip */
-	*((volatile u32 *) 0xa8020004) = 0;	/* disable any decoding */
-
-	/* put it into sleep */
-	*((volatile u32 *) 0xa8020040) = 0x80000000;
-
-	/* ----- end of reset on-board ether chip  ------ */
-
-	/* ----- set pci window 1 to pci memory space -------- */
-	nile4_set_pdar(NILE4_PCIW1,
-		       PHYSADDR(NILE4_PCI_MEM_BASE), 0x08000000, 32, 0, 0);
-	// nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
-	nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000);
-
-}
-
-#define USE_NILE4_SERIAL	0
-
-#if USE_NILE4_SERIAL
-#define ns16550_in(reg)		nile4_in8((reg)*8)
-#define ns16550_out(reg, val)	nile4_out8((reg)*8, (val))
-#else
-#define NS16550_BASE		(NILE4_PCI_IO_BASE+0x03f8)
-static inline u8 ns16550_in(u32 reg)
-{
-	return *(volatile u8 *) (NS16550_BASE + reg);
-}
-
-static inline void ns16550_out(u32 reg, u8 val)
-{
-	*(volatile u8 *) (NS16550_BASE + reg) = val;
-}
-#endif
-
-#define NS16550_RBR		0
-#define NS16550_THR		0
-#define NS16550_DLL		0
-#define NS16550_IER		1
-#define NS16550_DLM		1
-#define NS16550_FCR		2
-#define NS16550_IIR		2
-#define NS16550_LCR		3
-#define NS16550_MCR		4
-#define NS16550_LSR		5
-#define NS16550_MSR		6
-#define NS16550_SCR		7
-
-#define NS16550_LSR_DR		0x01	/* Data ready */
-#define NS16550_LSR_OE		0x02	/* Overrun */
-#define NS16550_LSR_PE		0x04	/* Parity error */
-#define NS16550_LSR_FE		0x08	/* Framing error */
-#define NS16550_LSR_BI		0x10	/* Break */
-#define NS16550_LSR_THRE	0x20	/* Xmit holding register empty */
-#define NS16550_LSR_TEMT	0x40	/* Xmitter empty */
-#define NS16550_LSR_ERR		0x80	/* Error */
-
-
-void _serinit(void)
-{
-#if USE_NILE4_SERIAL
-	ns16550_out(NS16550_LCR, 0x80);
-	ns16550_out(NS16550_DLM, 0x00);
-	ns16550_out(NS16550_DLL, 0x36);	/* 9600 baud */
-	ns16550_out(NS16550_LCR, 0x00);
-	ns16550_out(NS16550_LCR, 0x03);
-	ns16550_out(NS16550_FCR, 0x47);
-#else
-	/* done by PMON */
-#endif
-}
-
-void _putc(char c)
-{
-	while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
-	ns16550_out(NS16550_THR, c);
-	if (c == '\n') {
-		while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
-		ns16550_out(NS16550_THR, '\r');
-	}
-}
-
-void _puts(const char *s)
-{
-	char c;
-
-	while ((c = *s++))
-		_putc(c);
-}
-
-char _getc(void)
-{
-	while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
-
-	return ns16550_in(NS16550_RBR);
-}
-
-int _testc(void)
-{
-	return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
-}
-
-
-/*
- *  Hexadecimal 7-segment LED
- */
-void ddb5476_led_hex(int hex)
-{
-	outb(hex, 0x80);
-}
-
-
-/*
- *  LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
- */
-struct pci_dev *pci_pmu = NULL;
-
-void ddb5476_led_d2(int on)
-{
-	u8 t;
-
-	if (pci_pmu) {
-		pci_read_config_byte(pci_pmu, 0x7e, &t);
-		if (on)
-			t &= 0x7f;
-		else
-			t |= 0x80;
-		pci_write_config_byte(pci_pmu, 0x7e, t);
-	}
-}
-
-void ddb5476_led_d3(int on)
-{
-	u8 t;
-
-	if (pci_pmu) {
-		pci_read_config_byte(pci_pmu, 0x7e, &t);
-		if (on)
-			t &= 0xbf;
-		else
-			t |= 0x40;
-		pci_write_config_byte(pci_pmu, 0x7e, t);
-	}
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5476/time.c linux/arch/mips/ddb5476/time.c
--- linux.orig/arch/mips/ddb5476/time.c	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ddb5476/time.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,32 +0,0 @@
-/*
- *  arch/mips/ddb5074/time.c -- Timer routines
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <linux/init.h>
-
-#include <asm/mc146818rtc.h>
-
-static unsigned char ddb_rtc_read_data(unsigned long addr)
-{
-	outb_p(addr, RTC_PORT(0));
-	return inb_p(RTC_PORT(1));
-}
-
-static void ddb_rtc_write_data(unsigned char data, unsigned long addr)
-{
-	outb_p(addr, RTC_PORT(0));
-	outb_p(data, RTC_PORT(1));
-}
-
-static int ddb_rtc_bcd_mode(void)
-{
-	return 1;
-}
-
-struct rtc_ops ddb_rtc_ops = {
-	ddb_rtc_read_data,
-	ddb_rtc_write_data,
-	ddb_rtc_bcd_mode
-};
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/Makefile linux/arch/mips/ddb5xxx/common/Makefile
--- linux.orig/arch/mips/ddb5xxx/common/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/Makefile	2002-08-01 06:42:41.000000000 +0000
@@ -13,6 +13,6 @@
 
 O_TARGET:= ddb5xxx.o
 
-obj-y	 += irq.o irq_cpu.o nile4.o prom.o pci.o pci_auto.o rtc_ds1386.o
+obj-y	 += irq.o nile4.o prom.o rtc_ds1386.o
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/irq.c linux/arch/mips/ddb5xxx/common/irq.c
--- linux.orig/arch/mips/ddb5xxx/common/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/irq.c	2002-08-01 06:42:46.000000000 +0000
@@ -26,6 +26,8 @@
 	set_debug_traps();
 	breakpoint();
 #endif
+	/* set up default irq controller */
+	init_generic_irq();
 
 	/* invoke board-specific irq setup */
 	irq_setup();
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/irq_cpu.c linux/arch/mips/ddb5xxx/common/irq_cpu.c
--- linux.orig/arch/mips/ddb5xxx/common/irq_cpu.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/irq_cpu.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,115 +0,0 @@
-/***********************************************************************
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- *  arch/mips/ddb5xxx/common/irq_cpu.c
- *     This file define the irq handler for MIPS CPU interrupts.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- ***********************************************************************
- */
-
-/*
- * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
- * level triggered (i.e., cannot be cleared from CPU; must be cleared from
- * device).  The first two are software interrupts.  The last one is 
- * usually cpu timer interrupt if coutner register is present.
- *
- * This file exports one global function:
- *	mips_cpu_irq_init(u32 irq_base);
- */
-
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <asm/mipsregs.h>
-
-/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
-
-static int mips_cpu_irq_base=-1;
-
-static void 
-mips_cpu_irq_enable(unsigned int irq)
-{
-	MIPS_ASSERT(mips_cpu_irq_base != -1);
-	MIPS_ASSERT(irq >= mips_cpu_irq_base);
-	MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-
-	clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
-	set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
-}
-
-static void 
-mips_cpu_irq_disable(unsigned int irq)
-{
-	MIPS_ASSERT(mips_cpu_irq_base != -1);
-	MIPS_ASSERT(irq >= mips_cpu_irq_base);
-	MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-
-	clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
-}
-
-static unsigned int mips_cpu_irq_startup(unsigned int irq)
-{
-	mips_cpu_irq_enable(irq);
-	return 0;
-}
-
-#define	mips_cpu_irq_shutdown	mips_cpu_irq_disable
-
-static void
-mips_cpu_irq_ack(unsigned int irq)
-{
-	MIPS_ASSERT(mips_cpu_irq_base != -1);
-	MIPS_ASSERT(irq >= mips_cpu_irq_base);
-	MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-
-	/* although we attemp to clear the IP bit in cause reigster, I think
-	 * usually it is cleared by device (irq source)
-	 */
-	clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
-
-	/* I am not fully convinced that I should disable irq here */
-}
-
-static void
-mips_cpu_irq_end(unsigned int irq)
-{
-	MIPS_ASSERT(mips_cpu_irq_base != -1);
-	MIPS_ASSERT(irq >= mips_cpu_irq_base);
-	MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-	/* I am not fully convinced that I should enable irq here */
-}
-
-static hw_irq_controller mips_cpu_irq_controller = {
-	"CPU_irq",
-	mips_cpu_irq_startup,
-	mips_cpu_irq_shutdown,
-	mips_cpu_irq_enable,
-	mips_cpu_irq_disable,
-	mips_cpu_irq_ack,
-	mips_cpu_irq_end,
-	NULL			/* no affinity stuff for UP */
-};
-
-
-void 
-mips_cpu_irq_init(u32 irq_base)
-{
-	extern irq_desc_t irq_desc[];
-	u32 i;
-
-	for (i= irq_base; i< irq_base+8; i++) {
-		irq_desc[i].status = IRQ_DISABLED;
-		irq_desc[i].action = NULL;
-		irq_desc[i].depth = 1;
-		irq_desc[i].handler = &mips_cpu_irq_controller;
-	}
-
-	mips_cpu_irq_base = irq_base;
-} 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/nile4.c linux/arch/mips/ddb5xxx/common/nile4.c
--- linux.orig/arch/mips/ddb5xxx/common/nile4.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/nile4.c	2002-08-01 06:42:46.000000000 +0000
@@ -21,7 +21,6 @@
 #include <linux/kernel.h>
 
 #include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/ddb5xxx/debug.h>
 
 u32
 ddb_calc_pdar(u32 phys, u32 size, int width, 
@@ -73,7 +72,7 @@
                 maskbits = 0;
                 break;
         default:
-                panic("nile4_set_pdar: unsupported size %p\n", (void *) size);
+                panic("nile4_set_pdar: unsupported size %p", (void *) size);
         }
         switch (width) {
         case 8:
@@ -89,7 +88,7 @@
                 widthbits = 3;
                 break;
         default:
-                panic("nile4_set_pdar: unsupported width %d\n", width);
+                panic("nile4_set_pdar: unsupported width %d", width);
         }
 
 	return maskbits | (on_memory_bus ? 0x10 : 0) |
@@ -128,7 +127,7 @@
         case DDB_PCICMD_CFG:  /* PCI Configuration Space */
                 break;
         default:
-                panic("nile4_set_pmr: invalid type %d\n", type);
+                panic("nile4_set_pmr: invalid type %d", type);
         }
         ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
         ddb_out32(pmr + 4, 0);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/pci.c linux/arch/mips/ddb5xxx/common/pci.c
--- linux.orig/arch/mips/ddb5xxx/common/pci.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/pci.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,179 +0,0 @@
-/***********************************************************************
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/common/pci.c
- *     Common PCI routines for DDB5xxx - as a matter of fact, meant for all 
- *	MIPS machines.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- ***********************************************************************
- */
-
-/*
- * This file contains common PCI routines meant to be shared for
- * all MIPS machines.
- *
- * Strategies:
- *
- * . We rely on pci_auto.c file to assign PCI resources (MEM and IO)
- *   TODO: this shold be optional for some machines where they do have
- *   a real "pcibios" that does resource assignment.
- *
- * . We then use pci_scan_bus() to "discover" all the resources for
- *   later use by Linux.
- *
- * . We finally reply on a board supplied function, pcibios_fixup_irq(), to 
- *   to assign the interrupts.  We may use setup-irq.c under drivers/pci
- *   later.
- *
- * . Specifically, we will *NOT* use pci_assign_unassigned_resources(),
- *   because we assume all PCI devices should have the resources correctly
- *   assigned and recorded.
- *
- * Limitations:
- *
- * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus 
- *   into a contiguous range.  
- * 
- * . In the case of Memory space, the rnage is 1:1 mapping with CPU physical
- *   address space.
- *
- * . In the case of IO space, it starts from 0, and the beginning address
- *   is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address.
- *
- * . These are the current MIPS limitations (by ioremap, etc).  In the
- *   future, we may remove them.
- *
- * Credits:
- *	Most of the code are derived from the pci routines from PPC and Alpha,
- *	which were mostly writtne by
- *		Cort Dougan, cort@fsmlabs.com
- *		Matt Porter, mporter@mvista.com
- *		Dave Rusling david.rusling@reo.mts.dec.com
- *		David Mosberger davidm@cs.arizona.edu
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-
-#include <asm/ddb5xxx/pci.h>
-#include <asm/ddb5xxx/debug.h>
-
-
-struct pci_fixup pcibios_fixups[] = { {0} };
-
-
-extern int pciauto_assign_resources(int busno, struct pci_channel * hose);
-void __init pcibios_init(void)
-{
-	struct pci_channel *p;
-	struct pci_bus *bus;
-	int busno;
-
-	/* assign resources */
-	busno=0;
-	for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
-		busno = pciauto_assign_resources(busno, p) + 1;
-	}
-
-	/* scan the buses */
-	busno = 0;
-	for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
-		bus = pci_scan_bus(busno, p->pci_ops, p);
-		busno = bus->subordinate+1;
-	}
-
-	/* fixup irqs (board specific routines) */
-	pcibios_fixup_irqs();
-
-	/* 
-	 * should we do a fixup of ioport_resource and iomem_resource
-	 * based on mips_pci_channels?  
-	 * Let us wait and see if this is a common need and whether there
-	 * are exceptions.  Until then, each board should adjust them
-	 * perhaps in their setup() function.
-	 */
-}
-
-int pcibios_enable_device(struct pci_dev *dev)
-{
-	/* pciauto_assign_resources() will enable all devices found */
-	return 0;
-}
-
-unsigned long __init
-pci_bridge_check_io(struct pci_dev *bridge)
-{
-        u16 io;
-
-        pci_read_config_word(bridge, PCI_IO_BASE, &io);
-        if (!io) {
-                pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
-                pci_read_config_word(bridge, PCI_IO_BASE, &io);
-                pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
-        }
-        if (io)
-                return IORESOURCE_IO;
-        printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
-                                bridge->name);
-        return 0;
-}
-
-void __init pcibios_fixup_bus(struct pci_bus *bus)
-{
-        /* Propogate hose info into the subordinate devices.  */
-
-        struct pci_channel *hose = bus->sysdata;
-        struct pci_dev *dev = bus->self;
-
-        if (!dev) {
-                /* Root bus */
-                bus->resource[0] = hose->io_resource;
-                bus->resource[1] = hose->mem_resource;
-        } else {
-                /* This is a bridge. Do not care how it's initialized,
-                   just link its resources to the bus ones */
-                int i;
-
-                for(i=0; i<3; i++) {
-                        bus->resource[i] =
-                                &dev->resource[PCI_BRIDGE_RESOURCES+i];
-                        bus->resource[i]->name = bus->name;
-                }
-                bus->resource[0]->flags |= pci_bridge_check_io(dev);
-                bus->resource[1]->flags |= IORESOURCE_MEM;
-                /* For now, propogate hose limits to the bus;
-                   we'll adjust them later. */
-                bus->resource[0]->end = hose->io_resource->end;
-                bus->resource[1]->end = hose->mem_resource->end;
-                /* Turn off downstream PF memory address range by default */
-                bus->resource[2]->start = 1024*1024;
-                bus->resource[2]->end = bus->resource[2]->start - 1;
-        }
-}
-
-char *pcibios_setup(char *str)
-{
-	return str;
-}
-
-void
-pcibios_align_resource(void *data, struct resource *res, unsigned long size)
-{
-	/* this should not be called */
-	MIPS_ASSERT(1 == 0);
-}
-
-void
-pcibios_update_resource(struct pci_dev *dev, struct resource *root,
-                             struct resource *res, int resource)
-{
-	/* this should not be called */
-	MIPS_ASSERT(1 == 0);
-}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/pci_auto.c linux/arch/mips/ddb5xxx/common/pci_auto.c
--- linux.orig/arch/mips/ddb5xxx/common/pci_auto.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/pci_auto.c	1970-01-01 00:00:00.000000000 +0000
@@ -1,396 +0,0 @@
-/*
- * arch/ppc/kernel/pci_auto.c
- * 
- * PCI autoconfiguration library
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * Copyright 2000, 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/*
- * Modified for MIPS by Jun Sun, jsun@mvista.com
- *
- * . Simplify the interface between pci_auto and the rest: a single function.
- * . Assign resources from low address to upper address.
- * . change most int to u32.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-
-#include <asm/ddb5xxx/pci.h>
-#include <asm/ddb5xxx/debug.h>
-
-#define	DEBUG
-#ifdef 	DEBUG
-#define	DBG(x...)	printk(x)
-#else
-#define	DBG(x...)	
-#endif
-
-/* These are used for config access before all the PCI probing
-   has been done. */
-int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
-int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
-int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val);
-int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val);
-int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val);
-int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val);
-
-static u32 pciauto_lower_iospc;
-static u32 pciauto_upper_iospc;
-
-static u32 pciauto_lower_memspc;
-static u32 pciauto_upper_memspc;
-
-void __init 
-pciauto_setup_bars(struct pci_channel *hose,
-		   int current_bus,
-		   int pci_devfn)
-{
-	u32 bar_response, bar_size, bar_value;
-	u32 bar, addr_mask, bar_nr = 0;
-	u32 * upper_limit;
-	u32 * lower_limit;
-	int found_mem64 = 0;
-
-	DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
-	    current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
-
-	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4)
-	{
-		/* Tickle the BAR and get the response */
-		early_write_config_dword(hose,
-					 current_bus,
-					 pci_devfn,
-					 bar,
-					 0xffffffff);
-		early_read_config_dword(hose,
-					current_bus,
-					pci_devfn,
-					bar,
-					&bar_response);
-
-		/* If BAR is not implemented go to the next BAR */
-		if (!bar_response)
-			continue;
-
-		/* Check the BAR type and set our address mask */
-		if (bar_response & PCI_BASE_ADDRESS_SPACE)
-		{
-			addr_mask = PCI_BASE_ADDRESS_IO_MASK;
-			upper_limit = &pciauto_upper_iospc;
-			lower_limit = &pciauto_lower_iospc;
-			DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
-		}
-		else
-		{
-			if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
-			     PCI_BASE_ADDRESS_MEM_TYPE_64)
-				found_mem64 = 1;
-
-			addr_mask = PCI_BASE_ADDRESS_MEM_MASK;		
-			upper_limit = &pciauto_upper_memspc;
-			lower_limit = &pciauto_lower_memspc;
-			DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
-		}
-
-		/* Calculate requested size */
-		bar_size = ~(bar_response & addr_mask) + 1;
-
-		/* Allocate a base address */
-		bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
-		MIPS_ASSERT(bar_value + bar_size <= *upper_limit);
-
-		/* Write it out and update our limit */
-		early_write_config_dword(hose,
-					 current_bus,
-					 pci_devfn,
-					 bar,
-					 bar_value);
-
-		*lower_limit = bar_value + bar_size;
-
-		/*
-		 * If we are a 64-bit decoder then increment to the
-		 * upper 32 bits of the bar and force it to locate
-		 * in the lower 4GB of memory.
-		 */ 
-		if (found_mem64)
-		{
-			bar += 4;
-			early_write_config_dword(hose,
-						 current_bus,
-						 pci_devfn,
-						 bar,
-						 0x00000000);
-		}
-
-		bar_nr++;
-
-		DBG("size=0x%x, address=0x%x\n",
-		    bar_size, bar_value);
-	}
-
-}
-
-void __init
-pciauto_prescan_setup_bridge(struct pci_channel *hose,
-			     int current_bus,
-			     int pci_devfn,
-			     int sub_bus)
-{
-	int cmdstat;
-
-	/* Configure bus number registers */
-	early_write_config_byte(hose,
-				current_bus,
-				pci_devfn,
-				PCI_PRIMARY_BUS,
-				current_bus);
-	early_write_config_byte(hose,
-				current_bus,
-				pci_devfn,
-				PCI_SECONDARY_BUS,
-				sub_bus + 1);
-	early_write_config_byte(hose,
-				current_bus,
-				pci_devfn,
-				PCI_SUBORDINATE_BUS,
-				0xff);
-
-	/* Round memory allocator to 1MB boundary */
-	pciauto_upper_memspc &= ~(0x100000 - 1);
-
-	/* Round I/O allocator to 4KB boundary */
-	pciauto_upper_iospc &= ~(0x1000 - 1);
-
-	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
-	early_write_config_word(hose,
-				current_bus,
-				pci_devfn,
-				PCI_MEMORY_LIMIT,
-				((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
-	early_write_config_byte(hose,
-				current_bus,
-				pci_devfn,
-				PCI_IO_LIMIT,
-				((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
-	early_write_config_word(hose,
-				current_bus,
-				pci_devfn,
-				PCI_IO_LIMIT_UPPER16,
-				((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
-			
-	/* We don't support prefetchable memory for now, so disable */
-	early_write_config_word(hose,
-				current_bus,
-				pci_devfn,
-				PCI_PREF_MEMORY_BASE,
-				0x1000);
-	early_write_config_word(hose,
-				current_bus,
-				pci_devfn,
-				PCI_PREF_MEMORY_LIMIT,
-				0x1000);
-
-	/* Enable memory and I/O accesses, enable bus master */
-	early_read_config_dword(hose,
-				current_bus,
-				pci_devfn,
-				PCI_COMMAND,
-				&cmdstat);
-	early_write_config_dword(hose,
-				 current_bus,
-				 pci_devfn,
-				 PCI_COMMAND,
-				 cmdstat |
-				 PCI_COMMAND_IO |
-				 PCI_COMMAND_MEMORY |
-				 PCI_COMMAND_MASTER);
-}
-
-void __init
-pciauto_postscan_setup_bridge(struct pci_channel *hose,
-			      int current_bus,
-			      int pci_devfn,
-			      int sub_bus)
-{
-	/* Configure bus number registers */
-	early_write_config_byte(hose,
-				current_bus,
-				pci_devfn,
-				PCI_SUBORDINATE_BUS,
-				sub_bus);
-
-	/* Round memory allocator to 1MB boundary */
-	pciauto_upper_memspc &= ~(0x100000 - 1);
-	early_write_config_word(hose,
-				current_bus,
-				pci_devfn,
-				PCI_MEMORY_BASE,
-				pciauto_upper_memspc >> 16);
-
-	/* Round I/O allocator to 4KB boundary */
-	pciauto_upper_iospc &= ~(0x1000 - 1);
-	early_write_config_byte(hose,
-				current_bus,
-				pci_devfn,
-				PCI_IO_BASE,
-				(pciauto_upper_iospc & 0x0000f000) >> 8);
-	early_write_config_word(hose,
-				current_bus,
-				pci_devfn,
-				PCI_IO_BASE_UPPER16,
-				pciauto_upper_iospc >> 16);
-}
-
-#define      PCIAUTO_IDE_MODE_MASK           0x05
-
-int __init
-pciauto_bus_scan(struct pci_channel *hose, int current_bus)
-{
-	int sub_bus;
-	u32 pci_devfn, pci_class, cmdstat, found_multi=0;
-	unsigned short vid;
-	unsigned char header_type;
-
-	sub_bus = current_bus;
-	
-	for (pci_devfn=0; pci_devfn<0xff; pci_devfn++) {
-
-		if (PCI_FUNC(pci_devfn) && !found_multi)
-			continue;
-
-		early_read_config_byte(hose,
-				       current_bus,
-				       pci_devfn,
-				       PCI_HEADER_TYPE,
-				       &header_type);
-
-		if (!PCI_FUNC(pci_devfn))
-			found_multi = header_type & 0x80;
-
-		early_read_config_word(hose,
-				       current_bus,
-				       pci_devfn,
-				       PCI_VENDOR_ID,
-				       &vid);
-
-		if (vid == 0xffff) continue;
-
-		early_read_config_dword(hose,
-					current_bus,
-					pci_devfn,
-					PCI_CLASS_REVISION, &pci_class);
-		if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
-			DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
-			pciauto_prescan_setup_bridge(hose,
-						     current_bus,
-						     pci_devfn,
-						     sub_bus);
-			sub_bus = pciauto_bus_scan(hose, sub_bus+1);
-			pciauto_postscan_setup_bridge(hose,
-						      current_bus,
-						      pci_devfn,
-						      sub_bus);
-
-		} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
-
-			unsigned char prg_iface;
-
-			early_read_config_byte(hose,
-					       current_bus,
-					       pci_devfn,
-					       PCI_CLASS_PROG,
-					       &prg_iface);
-			if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
-				DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
-				continue;
-			}
-		}
-
-		/*
-		 * Found a peripheral, enable some standard
-		 * settings
-		 */
-		early_read_config_dword(hose,
-					current_bus,
-					pci_devfn,
-					PCI_COMMAND,
-					&cmdstat);
-		early_write_config_dword(hose,
-					 current_bus,
-					 pci_devfn,
-					 PCI_COMMAND,
-					 cmdstat |
-					 PCI_COMMAND_IO |
-					 PCI_COMMAND_MEMORY |
-					 PCI_COMMAND_MASTER);
-		early_write_config_byte(hose,
-					current_bus,
-					pci_devfn,
-					PCI_LATENCY_TIMER,
-					0x80);
-
-                /* Allocate PCI I/O and/or memory space */
-		pciauto_setup_bars(hose,
-				   current_bus,
-				   pci_devfn);
-	}
-	return sub_bus;
-}
-
-int __init
-pciauto_assign_resources(int busno, struct pci_channel *hose)
-{
-	/* setup resource limits */
-	pciauto_lower_iospc = hose->io_resource->start;
-	pciauto_upper_iospc = hose->io_resource->end + 1;
-	pciauto_lower_memspc = hose->mem_resource->start;
-	pciauto_upper_memspc = hose->mem_resource->end + 1;
-
-	return pciauto_bus_scan(hose, busno);
-}
-
-
-/*
- * These functions are used early on before PCI scanning is done
- * and all of the pci_dev and pci_bus structures have been created.
- */
-static struct pci_dev *
-fake_pci_dev(struct pci_channel *hose, int busnr, int devfn)
-{
-        static struct pci_dev dev;
-        static struct pci_bus bus;
-
-        dev.bus = &bus;
-        dev.sysdata = hose;
-        dev.devfn = devfn;
-        bus.number = busnr;
-        bus.ops = hose->pci_ops;
-        return &dev;
-}
-
-#define EARLY_PCI_OP(rw, size, type)                                    \
-int early_##rw##_config_##size(struct pci_channel *hose, int bus,    \
-                               int devfn, int offset, type value)       \
-{                                                                       \
-        return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
-                                        offset, value);                 \
-}
-
-EARLY_PCI_OP(read, byte, u8 *)
-EARLY_PCI_OP(read, word, u16 *)
-EARLY_PCI_OP(read, dword, u32 *)
-EARLY_PCI_OP(write, byte, u8)
-EARLY_PCI_OP(write, word, u16)
-EARLY_PCI_OP(write, dword, u32)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/prom.c linux/arch/mips/ddb5xxx/common/prom.c
--- linux.orig/arch/mips/ddb5xxx/common/prom.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/prom.c	2002-08-01 06:42:38.000000000 +0000
@@ -22,8 +22,19 @@
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
 #include <asm/ddb5xxx/ddb5xxx.h>
+#include <asm/debug.h>
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
+
+const char *get_system_type(void)
+{
+	switch (mips_machtype) {
+	case MACH_NEC_DDB5074:		return "NEC DDB Vrc-5074";
+	case MACH_NEC_DDB5476:		return "NEC DDB Vrc-5476";
+	case MACH_NEC_DDB5477:		return "NEC DDB Vrc-5477";
+	case MACH_NEC_ROCKHOPPER:	return "NEC Rockhopper";
+	}
+}
 
 /* [jsun@junsun.net] PMON passes arguments in C main() style */
 void __init prom_init(int argc, const char **arg)
@@ -40,19 +51,84 @@
 		strcat(arcs_cmdline, " ");
 	}
 
+	/* by default all these boards use dhcp/nfs root fs */
+	strcat(arcs_cmdline, "ip=bootp");
+
 	mips_machgroup = MACH_GROUP_NEC_DDB;
 
 #if defined(CONFIG_DDB5074)
 	mips_machtype = MACH_NEC_DDB5074;
+	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
 #elif defined(CONFIG_DDB5476)
 	mips_machtype = MACH_NEC_DDB5476;
+	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
 #elif defined(CONFIG_DDB5477)
-	mips_machtype = MACH_NEC_DDB5477;
+	ddb5477_runtime_detection();
+	add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
 #endif
-
-	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
 }
 
 void __init prom_free_prom_memory(void)
 {
 }
+
+#if defined(CONFIG_DDB5477)
+
+#define DEFAULT_LCS1_BASE 0x19000000
+#define TESTVAL1 'K'
+#define TESTVAL2 'S'
+
+int board_ram_size;
+void ddb5477_runtime_detection(void)
+{
+	volatile char *test_offset;
+	char saved_test_byte;
+
+        /* Determine if this is a DDB5477 board, or a BSB-VR0300
+           base board.  We can tell by checking for the location of
+           the NVRAM.  It lives at the beginning of LCS1 on the DDB5477,
+           and the beginning of LCS1 on the BSB-VR0300 is flash memory.
+           The first 2K of the NVRAM are reserved, so don't we'll poke
+           around just after that.
+         */
+
+        test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800);
+        saved_test_byte = *test_offset;
+
+        *test_offset = TESTVAL1;
+        if (*test_offset != TESTVAL1) {
+                /* We couldn't set our test value, so it must not be NVRAM,
+                   so it's a BSB_VR0300 */
+		mips_machtype = MACH_NEC_ROCKHOPPER;
+        } else {
+                /* We may have gotten lucky, and the TESTVAL1 was already
+                   stored at the test location, so we must check a second
+                   test value */
+                *test_offset = TESTVAL2;
+                if (*test_offset != TESTVAL2) {
+                        /* OK, we couldn't set this value either, so it must
+                           definately be a BSB_VR0300 */
+			mips_machtype = MACH_NEC_ROCKHOPPER;
+                } else {
+                        /* We could change the value twice, so it must be
+                        NVRAM, so it's a DDB_VRC5477 */
+			mips_machtype = MACH_NEC_DDB5477;
+                }
+        }
+        /* Restore the original byte */
+        *test_offset = saved_test_byte;
+
+	/* before we know a better way, we will trust PMON for getting
+	 * RAM size 
+	 */
+	board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf));
+
+	db_run(printk("DDB run-time detection : %s, %d MB RAM\n",
+				mips_machtype == MACH_NEC_DDB5477 ?
+				"DDB5477" : "Rockhopper",
+				board_ram_size >> 20));
+
+	/* we can't handle ram size > 128 MB */
+	db_assert(board_ram_size <= (128 << 20));
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/common/rtc_ds1386.c linux/arch/mips/ddb5xxx/common/rtc_ds1386.c
--- linux.orig/arch/mips/ddb5xxx/common/rtc_ds1386.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/common/rtc_ds1386.c	2002-08-01 06:42:37.000000000 +0000
@@ -24,7 +24,7 @@
 #include <asm/time.h>
 #include <asm/addrspace.h>
 
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
 
 #define	EPOCH		2000
 
@@ -101,7 +101,7 @@
 	}
 
 	temp = READ_RTC(0x9);
-	month = BIN_TO_BCD(tm.tm_mon);
+	month = BIN_TO_BCD(tm.tm_mon+1);	/* tm_mon starts from 0 to 11 */
 	if (month != (temp & 0x1f)) {
 		WRITE_RTC( 0x9,
 			   (month & 0x1f) | (temp & ~0x1f) );
@@ -147,7 +147,7 @@
 	
 	/* remember the base */
 	rtc_base = base;
-	MIPS_ASSERT((rtc_base & 0xe0000000) == KSEG1);
+	db_assert((rtc_base & 0xe0000000) == KSEG1);
 
 	/* turn on RTC if it is not on */
 	byte = READ_RTC(0x9);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/Makefile linux/arch/mips/ddb5xxx/ddb5476/Makefile
--- linux.orig/arch/mips/ddb5xxx/ddb5476/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/Makefile	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,23 @@
+#
+# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
+# under Linux.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+# Note 2! The CFLAGS definitions are now in the main makefile...
+#
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+O_TARGET = ddb5476.o
+
+obj-y				+= setup.o irq.o int-handler.o pci.o pci_ops.o \
+				   nile4_pic.o vrc5476_irq.o
+obj-$(CONFIG_REMOTE_DEBUG)	+= dbg_io.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/dbg_io.c linux/arch/mips/ddb5xxx/ddb5476/dbg_io.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/dbg_io.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/dbg_io.c	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,136 @@
+/*
+ * kgdb io functions for DDB5476.  We use the second serial port.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+/* ======================= CONFIG ======================== */
+
+/* [jsun] we use the second serial port for kdb */
+#define         BASE                    0xa60002f8
+#define         MAX_BAUD                115200
+
+/* distance in bytes between two serial registers */
+#define         REG_OFFSET              1
+
+/*
+ * 0 - kgdb does serial init
+ * 1 - kgdb skip serial init
+ */
+static int remoteDebugInitialized = 0;
+
+/*
+ * the default baud rate *if* kgdb does serial init
+ */
+#define		BAUD_DEFAULT		UART16550_BAUD_38400
+
+/* ======================= END OF CONFIG ======================== */
+
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+
+#define         UART16550_BAUD_2400             2400
+#define         UART16550_BAUD_4800             4800
+#define         UART16550_BAUD_9600             9600
+#define         UART16550_BAUD_19200            19200
+#define         UART16550_BAUD_38400            38400
+#define         UART16550_BAUD_57600            57600
+#define         UART16550_BAUD_115200           115200
+
+#define         UART16550_PARITY_NONE           0
+#define         UART16550_PARITY_ODD            0x08
+#define         UART16550_PARITY_EVEN           0x18
+#define         UART16550_PARITY_MARK           0x28
+#define         UART16550_PARITY_SPACE          0x38
+
+#define         UART16550_DATA_5BIT             0x0
+#define         UART16550_DATA_6BIT             0x1
+#define         UART16550_DATA_7BIT             0x2
+#define         UART16550_DATA_8BIT             0x3
+
+#define         UART16550_STOP_1BIT             0x0
+#define         UART16550_STOP_2BIT             0x4
+
+/* register offset */
+#define         OFS_RCV_BUFFER          0
+#define         OFS_TRANS_HOLD          0
+#define         OFS_SEND_BUFFER         0
+#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
+#define         OFS_INTR_ID             (2*REG_OFFSET)
+#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
+#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
+#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
+#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
+#define         OFS_LINE_STATUS         (5*REG_OFFSET)
+#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
+#define         OFS_RS232_INPUT         (6*REG_OFFSET)
+#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
+
+#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
+#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
+
+
+/* memory-mapped read/write of the port */
+#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+
+void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+        /* disable interrupts */
+        UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+        /* set up buad rate */
+        {
+                uint32 divisor;
+
+                /* set DIAB bit */
+                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+                /* set divisor */
+                divisor = MAX_BAUD / baud;
+                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+                /* clear DIAB bit */
+                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+        }
+
+        /* set data format */
+        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+uint8 getDebugChar(void)
+{
+        if (!remoteDebugInitialized) {
+                remoteDebugInitialized = 1;
+                debugInit(BAUD_DEFAULT,
+                          UART16550_DATA_8BIT,
+                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+        }
+
+        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+        return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+
+int putDebugChar(uint8 byte)
+{
+        if (!remoteDebugInitialized) {
+                remoteDebugInitialized = 1;
+                debugInit(BAUD_DEFAULT,
+                          UART16550_DATA_8BIT,
+                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+        }
+
+        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
+        UART16550_WRITE(OFS_SEND_BUFFER, byte);
+        return 1;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/int-handler.S linux/arch/mips/ddb5xxx/ddb5476/int-handler.S
--- linux.orig/arch/mips/ddb5xxx/ddb5476/int-handler.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/int-handler.S	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * First-level interrupt dispatcher for ddb5476
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+#include <asm/ddb5xxx/ddb5476.h>
+
+/*
+ * first level interrupt dispatcher for ocelot board -
+ * We check for the timer first, then check PCI ints A and D.
+ * Then check for serial IRQ and fall through.
+ */
+	.align	5
+	NESTED(ddb5476_handle_int, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+	.set	at
+	.set	noreorder
+	mfc0	t0, CP0_CAUSE  
+	mfc0	t2, CP0_STATUS
+
+	and	t0, t2
+
+        andi    t1, t0, STATUSF_IP7     /* cpu timer */
+        bnez    t1, ll_cpu_ip7
+        andi    t1, t0, STATUSF_IP2	/* vrc5476 & i8259 */
+        bnez    t1, ll_cpu_ip2
+        andi    t1, t0, STATUSF_IP3
+        bnez    t1, ll_cpu_ip3
+        andi    t1, t0, STATUSF_IP4
+        bnez    t1, ll_cpu_ip4
+        andi    t1, t0, STATUSF_IP5
+        bnez    t1, ll_cpu_ip5
+        andi    t1, t0, STATUSF_IP6
+        bnez    t1, ll_cpu_ip6
+        andi    t1, t0, STATUSF_IP0     /* software int 0 */
+        bnez    t1, ll_cpu_ip0
+        andi    t1, t0, STATUSF_IP1     /* software int 1 */
+        bnez    t1, ll_cpu_ip1
+        nop
+
+	.set	reorder
+
+	/* wrong alarm or masked ... */
+	// j	spurious_interrupt
+	move 	a0, sp
+	jal	vrc5476_irq_dispatch
+	j	ret_from_irq
+	nop
+
+	.align	5
+
+ll_cpu_ip0:	
+	li	a0, CPU_IRQ_BASE + 0
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+ll_cpu_ip1:	
+	li	a0, CPU_IRQ_BASE + 1
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+ll_cpu_ip2:		/* jump to second-level dispatching */
+	move	a0, sp
+	jal	vrc5476_irq_dispatch
+	j	ret_from_irq
+
+ll_cpu_ip3:	
+	li	a0, CPU_IRQ_BASE + 3
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+ll_cpu_ip4:	
+	li	a0, CPU_IRQ_BASE + 4
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+ll_cpu_ip5:	
+	li	a0, CPU_IRQ_BASE + 5
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+ll_cpu_ip6:	
+	li	a0, CPU_IRQ_BASE + 6
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+ll_cpu_ip7:
+	li	a0, CPU_IRQ_BASE + 7
+	move	a1, sp
+	jal	do_IRQ
+	j	ret_from_irq
+
+	END(ddb5476_handle_int)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/irq.c linux/arch/mips/ddb5xxx/ddb5476/irq.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/irq.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,148 @@
+/*
+ *  arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ *
+ * Re-write the whole thing to use new irq.c file.
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/ptrace.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
+#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
+#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */
+
+#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
+#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
+#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */
+
+#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
+#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */
+
+#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
+#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */
+
+#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
+#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */
+
+static void m1543_irq_setup(void)
+{
+	/*
+	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
+	 *  the possible IO sources in the M1543 are in use by us.  We will
+	 *  use the following mapping:
+	 *
+	 *      IRQ1  - keyboard (default set by M1543)
+	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
+	 *              the schematics for the DDB Vrc-5476 board seem to 
+	 *              indicate that IRQ3 is connected to the DS1386 
+	 *              watchdog timer interrupt output so we might have 
+	 *              a conflict)
+	 *      IRQ4  - reserved for UART A (default set by M1543)
+	 *      IRQ5  - parallel (default set by M1543)
+	 *      IRQ8  - DS1386 time of day (RTC) interrupt
+	 *      IRQ9  - USB (hardwired in ddb_setup)
+	 *      IRQ10 - PMU (hardwired in ddb_setup)
+	 *      IRQ12 - mouse
+	 *      IRQ14,15 - IDE controller (need to be confirmed, jsun)
+	 */
+
+	/*
+	 *  Assing mouse interrupt to IRQ12 
+	 */
+
+	/* Enter configuration mode */
+	outb(0x51, M1543_PNP_CONFIG);
+	outb(0x23, M1543_PNP_CONFIG);
+
+	/* Select logical device 7 (Keyboard) */
+	outb(0x07, M1543_PNP_INDEX);
+	outb(0x07, M1543_PNP_DATA);
+
+	/* Select IRQ12 */
+	outb(0x72, M1543_PNP_INDEX);
+	outb(0x0c, M1543_PNP_DATA);
+
+	/* Leave configration mode */
+	outb(0xbb, M1543_PNP_CONFIG);
+}
+
+static void nile4_irq_setup(void)
+{
+	int i;
+
+	/* Map all interrupts to CPU int #0 (IP2) */
+	nile4_map_irq_all(0);
+
+	/* PCI INTA#-E# must be level triggered */
+	nile4_set_pci_irq_level_or_edge(0, 1);
+	nile4_set_pci_irq_level_or_edge(1, 1);
+	nile4_set_pci_irq_level_or_edge(2, 1);
+	nile4_set_pci_irq_level_or_edge(3, 1);
+
+	/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
+	nile4_set_pci_irq_polarity(0, 0);
+	nile4_set_pci_irq_polarity(1, 0);
+	nile4_set_pci_irq_polarity(2, 1);
+	nile4_set_pci_irq_polarity(3, 0);
+
+	for (i = 0; i < 16; i++)
+		nile4_clear_irq(i);
+
+	/* Enable CPU int #0 */
+	nile4_enable_irq_output(0);
+
+	/* memory resource acquire in ddb_setup */
+}
+
+static void error_action(int irq, void *dev_id, struct pt_regs *regs)
+{
+	printk(KERN_ERR "Error interrupt happend: %d\n", irq);
+}
+
+static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
+static struct irqaction irq_error = { no_action, 0, 0, "error", NULL, NULL };
+
+extern asmlinkage void ddb5476_handle_int(void);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+extern void mips_cpu_irq_init(u32 irq_base);
+extern void vrc5476_irq_init(u32 irq_base);
+
+void __init ddb5476_irq_setup(void)
+{
+	/* hardware initialization */
+	nile4_irq_setup();
+	m1543_irq_setup();
+
+	/* controller setup */
+	init_i8259_irqs();
+	vrc5476_irq_init(VRC5476_IRQ_BASE);
+	mips_cpu_irq_init(CPU_IRQ_BASE);
+
+	/* setup cascade interrupts */
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
+	setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
+
+	/* setup error interrupts for debugging */
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
+	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
+
+	/* setup the grandpa intr vector */
+	set_except_vector(0, ddb5476_handle_int);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/nile4_pic.c linux/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/nile4_pic.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/nile4_pic.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,189 @@
+/*
+ *  arch/mips/ddb5476/nile4.c -- 
+ *  	low-level PIC code for NEC Vrc-5476 (Nile 4)
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ *
+ *  Copyright 2001 MontaVista Software Inc.
+ *  Author: jsun@mvista.com or jsun@junsun.net
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+
+/*
+ *  Interrupt Programming
+ */
+void nile4_map_irq(int nile4_irq, int cpu_irq)
+{
+	u32 offset, t;
+
+	offset = DDB_INTCTRL;
+	if (nile4_irq >= 8) {
+		offset += 4;
+		nile4_irq -= 8;
+	}
+	t = ddb_in32(offset);
+	t &= ~(7 << (nile4_irq * 4));
+	t |= cpu_irq << (nile4_irq * 4);
+	ddb_out32(offset, t);
+}
+
+void nile4_map_irq_all(int cpu_irq)
+{
+	u32 all, t;
+
+	all = cpu_irq;
+	all |= all << 4;
+	all |= all << 8;
+	all |= all << 16;
+	t = ddb_in32(DDB_INTCTRL);
+	t &= 0x88888888;
+	t |= all;
+	ddb_out32(DDB_INTCTRL, t);
+	t = ddb_in32(DDB_INTCTRL + 4);
+	t &= 0x88888888;
+	t |= all;
+	ddb_out32(DDB_INTCTRL + 4, t);
+}
+
+void nile4_enable_irq(int nile4_irq)
+{
+	u32 offset, t;
+
+	offset = DDB_INTCTRL;
+	if (nile4_irq >= 8) {
+		offset += 4;
+		nile4_irq -= 8;
+	}
+	t = ddb_in32(offset);
+	t |= 8 << (nile4_irq * 4);
+	ddb_out32(offset, t);
+}
+
+void nile4_disable_irq(int nile4_irq)
+{
+	u32 offset, t;
+
+	offset = DDB_INTCTRL;
+	if (nile4_irq >= 8) {
+		offset += 4;
+		nile4_irq -= 8;
+	}
+	t = ddb_in32(offset);
+	t &= ~(8 << (nile4_irq * 4));
+	ddb_out32(offset, t);
+}
+
+void nile4_disable_irq_all(void)
+{
+	ddb_out32(DDB_INTCTRL, 0);
+	ddb_out32(DDB_INTCTRL + 4, 0);
+}
+
+u16 nile4_get_irq_stat(int cpu_irq)
+{
+	return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
+}
+
+void nile4_enable_irq_output(int cpu_irq)
+{
+	u32 t;
+
+	t = ddb_in32(DDB_INTSTAT1 + 4);
+	t |= 1 << (16 + cpu_irq);
+	ddb_out32(DDB_INTSTAT1, t);
+}
+
+void nile4_disable_irq_output(int cpu_irq)
+{
+	u32 t;
+
+	t = ddb_in32(DDB_INTSTAT1 + 4);
+	t &= ~(1 << (16 + cpu_irq));
+	ddb_out32(DDB_INTSTAT1, t);
+}
+
+void nile4_set_pci_irq_polarity(int pci_irq, int high)
+{
+	u32 t;
+
+	t = ddb_in32(DDB_INTPPES);
+	if (high)
+		t &= ~(1 << (pci_irq * 2));
+	else
+		t |= 1 << (pci_irq * 2);
+	ddb_out32(DDB_INTPPES, t);
+}
+
+void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
+{
+	u32 t;
+
+	t = ddb_in32(DDB_INTPPES);
+	if (level)
+		t |= 2 << (pci_irq * 2);
+	else
+		t &= ~(2 << (pci_irq * 2));
+	ddb_out32(DDB_INTPPES, t);
+}
+
+void nile4_clear_irq(int nile4_irq)
+{
+	ddb_out32(DDB_INTCLR, 1 << nile4_irq);
+}
+
+void nile4_clear_irq_mask(u32 mask)
+{
+	ddb_out32(DDB_INTCLR, mask);
+}
+
+u8 nile4_i8259_iack(void)
+{
+	u8 irq;
+	u32 reg;
+
+	/* Set window 0 for interrupt acknowledge */
+	reg = ddb_in32(DDB_PCIINIT0);
+
+	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
+	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
+	/* restore window 0 for PCI I/O space */
+	// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+	ddb_out32(DDB_PCIINIT0, reg);
+
+	/* i8269.c set the base vector to be 0x0 */
+	return irq + I8259_IRQ_BASE;
+}
+
+#if defined(CONFIG_LL_DEBUG)
+void nile4_dump_irq_status(void)
+{
+	printk(KERN_DEBUG "
+	       CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
+	       (void *) ddb_in32(DDB_CPUSTAT));
+	printk(KERN_DEBUG "
+	       INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
+	       (void *) ddb_in32(DDB_INTCTRL));
+	printk(KERN_DEBUG
+	       "INTSTAT0 = %p:%p\n",
+	       (void *) ddb_in32(DDB_INTSTAT0 + 4),
+	       (void *) ddb_in32(DDB_INTSTAT0));
+	printk(KERN_DEBUG
+	       "INTSTAT1 = %p:%p\n",
+	       (void *) ddb_in32(DDB_INTSTAT1 + 4),
+	       (void *) ddb_in32(DDB_INTSTAT1));
+	printk(KERN_DEBUG
+	       "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
+	       (void *) ddb_in32(DDB_INTCLR));
+	printk(KERN_DEBUG
+	       "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
+	       (void *) ddb_in32(DDB_INTPPES));
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/pci.c linux/arch/mips/ddb5xxx/ddb5476/pci.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/pci.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/pci.c	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,138 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+#include <asm/pci_channel.h>
+#include <asm/debug.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+static struct resource extpci_io_resource = {
+	"pci IO space", 
+	0x1000,				/* leave some room for ISA bus */
+	DDB_PCI_IO_SIZE -1,
+	IORESOURCE_IO};
+
+static struct resource extpci_mem_resource = {
+	"pci memory space", 
+	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
+	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1,
+	IORESOURCE_MEM};
+
+extern struct pci_ops ddb5476_ext_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+	{ &ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource },
+	{ NULL, NULL, NULL}
+};
+
+
+/*
+ * we fix up irqs based on the slot number.
+ * The first entry is at AD:11.
+ * 
+ * This does not work for devices on sub-buses yet.
+ */
+
+/*
+ * temporary
+ */
+
+#define		PCI_EXT_INTA		8
+#define		PCI_EXT_INTB		9
+#define		PCI_EXT_INTC		10
+#define		PCI_EXT_INTD		11
+#define		PCI_EXT_INTE		12
+
+/*
+ * based on ddb5477 manual page 11
+ */
+#define		MAX_SLOT_NUM		21
+static unsigned char irq_map[MAX_SLOT_NUM] = {
+	/* SLOT:  0, AD:11 */ 0xff,
+	/* SLOT:  1, AD:12 */ 0xff,
+	/* SLOT:  2, AD:13 */ 9,		/* USB */
+	/* SLOT:  3, AD:14 */ 10,		/* PMU */
+	/* SLOT:  4, AD:15 */ 0xff,
+	/* SLOT:  5, AD:16 */ 0x0,		/* P2P bridge */
+	/* SLOT:  6, AD:17 */ nile4_to_irq(PCI_EXT_INTB),
+	/* SLOT:  7, AD:18 */ nile4_to_irq(PCI_EXT_INTC),
+	/* SLOT:  8, AD:19 */ nile4_to_irq(PCI_EXT_INTD),
+	/* SLOT:  9, AD:20 */ nile4_to_irq(PCI_EXT_INTA),
+	/* SLOT: 10, AD:21 */ 0xff,
+	/* SLOT: 11, AD:22 */ 0xff,
+	/* SLOT: 12, AD:23 */ 0xff,
+	/* SLOT: 13, AD:24 */ 14,		/* HD controller, M5229 */
+	/* SLOT: 14, AD:25 */ 0xff,
+	/* SLOT: 15, AD:26 */ 0xff,
+	/* SLOT: 16, AD:27 */ 0xff,
+	/* SLOT: 17, AD:28 */ 0xff,
+	/* SLOT: 18, AD:29 */ 0xff,
+	/* SLOT: 19, AD:30 */ 0xff,
+	/* SLOT: 20, AD:31 */ 0xff
+};
+
+extern int vrc5477_irq_to_irq(int irq);
+void __init pcibios_fixup_irqs(void)
+{
+        struct pci_dev *dev;
+        int slot_num;
+
+	pci_for_each_dev(dev) {
+		slot_num = PCI_SLOT(dev->devfn);
+
+		/* we don't do IRQ fixup for sub-bus yet */
+		if (dev->bus->parent != NULL) {
+			db_run(printk("Don't know how to fixup irq for PCI device %d on sub-bus %d\n",
+				slot_num, dev->bus->number));
+			continue;
+		}
+
+		db_assert(slot_num < MAX_SLOT_NUM);
+		db_assert(irq_map[slot_num] != 0xff);
+
+		pci_write_config_byte(dev, 
+				      PCI_INTERRUPT_LINE,
+				      irq_map[slot_num]);
+		dev->irq = irq_map[slot_num];
+	}
+}
+
+#if defined(CONFIG_DEBUG)
+extern void jsun_scan_pci_bus(void);
+#endif
+
+void __init ddb_pci_reset_bus(void)
+{	
+	u32 temp;
+
+	/*
+	 * I am not sure about the "official" procedure, the following
+	 * steps work as far as I know:
+	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
+	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
+	 * The same is true for both PCI channels.
+	 */
+	temp = ddb_in32(DDB_PCICTRL+4);
+	temp |= 0x80000000;
+	ddb_out32(DDB_PCICTRL+4, temp);
+	temp &= ~0xc0000000;
+	ddb_out32(DDB_PCICTRL+4, temp);
+
+}
+
+unsigned __init int pcibios_assign_all_busses(void)
+{
+	/* we hope pci_auto has assigned the bus numbers to all buses */
+	return 1;
+}
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/pci_ops.c linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/pci_ops.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,357 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5476/pci_ops.c
+ *     Define the pci_ops for DB5477.
+ *
+ * Much of the code is derived from the original DDB5074 port by 
+ * Geert Uytterhoeven <geert@sonycom.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+#include <asm/debug.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+/*
+ * config_swap structure records what set of pdar/pmr are used
+ * to access pci config space.  It also provides a place hold the
+ * original values for future restoring.
+ */
+struct pci_config_swap {
+	u32 	pdar;
+	u32	pmr;
+	u32	config_base;
+	u32	config_size;
+	u32	pdar_backup;
+	u32	pmr_backup;
+};
+
+/*
+ * On DDB5476, we have one set of swap registers
+ */
+struct pci_config_swap ext_pci_swap = {
+	DDB_PCIW0,  
+	DDB_PCIINIT0,
+	DDB_PCI_CONFIG_BASE,
+	DDB_PCI_CONFIG_SIZE
+};
+
+static int pci_config_workaround=1;
+
+/*
+ * access config space
+ */	
+static inline u32 ddb_access_config_base(struct pci_config_swap *swap,
+					 u32 bus,/* 0 means top level bus */
+					 u32 slot_num)
+{
+	u32 pci_addr = 0;
+	u32 pciinit_offset = 0;
+        u32 virt_addr = swap->config_base;
+	u32 option;
+
+	if (pci_config_workaround) {
+		/* [jsun] work around Vrc5476 controller itself, returnning
+		 * slot 0 essentially makes vrc5476 invisible
+		 */ 
+		if (slot_num == 12) slot_num = 0;
+
+#if 0
+		/* BUG : skip P2P bridge for now */
+		if (slot_num == 5) slot_num = 0;
+#endif
+
+	} else {
+		/* now we have to be hornest, returning the true
+		 * PCI config headers for vrc5476
+		 */ 
+		if (slot_num == 12) {
+			swap->pdar_backup = ddb_in32(swap->pdar);
+			swap->pmr_backup = ddb_in32(swap->pmr);
+			return DDB_BASE + DDB_PCI_BASE;
+		}
+	}
+
+	/* minimum pdar (window) size is 2MB */
+	db_assert(swap->config_size >= (2 << 20));
+
+	db_assert(slot_num < (1 << 5));
+	db_assert(bus < (1 << 8));
+
+	/* backup registers */
+	swap->pdar_backup = ddb_in32(swap->pdar);
+	swap->pmr_backup = ddb_in32(swap->pmr);
+
+	/* set the pdar (pci window) register */
+	ddb_set_pdar(swap->pdar,
+		     swap->config_base,
+		     swap->config_size,
+		     32,	/* 32 bit wide */
+		     0,		/* not on local memory bus */
+		     0);	/* not visible from PCI bus (N/A) */
+
+	/* 
+	 * calcuate the absolute pci config addr; 
+	 * according to the spec, we start scanning from adr:11 (0x800)
+	 */ 
+	if (bus == 0) {
+		/* type 0 config */
+		pci_addr = 0x800 << slot_num;
+	} else {
+		/* type 1 config */
+		pci_addr = (bus << 16) | (slot_num << 11);
+		/* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
+	}
+
+	/*
+	 * if pci_addr is less than pci config window size,  we set
+	 * pciinit_offset to 0 and adjust the virt_address.
+	 * Otherwise we will try to adjust pciinit_offset.
+	 */
+	if (pci_addr < swap->config_size) {
+		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
+		pciinit_offset = 0;
+	} else {
+		db_assert( (pci_addr & (swap->config_size - 1)) == 0);
+		virt_addr = KSEG1ADDR(swap->config_base);
+		pciinit_offset = pci_addr;
+	}
+
+	/* set the pmr register */
+	option = DDB_PCI_ACCESS_32;
+	if (bus != 0) option |= DDB_PCI_CFGTYPE1;
+	ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
+
+	return virt_addr;
+}
+
+static inline void ddb_close_config_base(struct pci_config_swap *swap)
+{
+	ddb_out32(swap->pdar, swap->pdar_backup);
+	ddb_out32(swap->pmr, swap->pmr_backup);
+}
+
+static int read_config_dword(struct pci_config_swap *swap,
+			     struct pci_dev *dev,
+			     u32 where,
+			     u32 *val)
+{
+	u32 bus, slot_num, func_num;
+	u32 base;
+
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}
+
+	slot_num = PCI_SLOT(dev->devfn);
+	func_num = PCI_FUNC(dev->devfn);
+	base = ddb_access_config_base(swap, bus, slot_num);
+	*val = *(volatile u32*) (base + (func_num << 8) + where);
+	ddb_close_config_base(swap);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int read_config_word(struct pci_config_swap *swap,
+			    struct pci_dev *dev,
+			    u32 where,
+			    u16 *val)
+{
+        int status;
+        u32 result;
+
+	db_assert((where & 1) == 0);
+
+        status = read_config_dword(swap, dev, where & ~3, &result);
+        if (where & 2) result >>= 16;
+        *val = result & 0xffff;
+        return status;
+}
+
+static int read_config_byte(struct pci_config_swap *swap,
+			    struct pci_dev *dev,
+			    u32 where,
+			    u8 *val)
+{
+        int status;
+        u32 result;
+
+        status = read_config_dword(swap, dev, where & ~3, &result);
+        if (where & 1) result >>= 8;
+        if (where & 2) result >>= 16;
+        *val = result & 0xff;
+        return status;
+}
+
+static int write_config_dword(struct pci_config_swap *swap,
+			      struct pci_dev *dev,
+			      u32 where,
+			      u32 val)
+{
+	u32 bus, slot_num, func_num;
+	u32 base;
+
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}
+
+	slot_num = PCI_SLOT(dev->devfn);
+	func_num = PCI_FUNC(dev->devfn);
+	base = ddb_access_config_base(swap, bus, slot_num);
+	*(volatile u32*) (base + (func_num << 8) + where) = val; 
+	ddb_close_config_base(swap);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_word(struct pci_config_swap *swap,
+			     struct pci_dev *dev,
+			     u32 where,
+			     u16 val)
+{
+	int status, shift=0;
+	u32 result;
+
+	db_assert((where & 1) == 0);
+
+	status = read_config_dword(swap, dev, where & ~3, &result);
+	if (status != PCIBIOS_SUCCESSFUL) return status;
+
+        if (where & 2)
+                shift += 16;
+        result &= ~(0xffff << shift);
+        result |= val << shift;
+        return write_config_dword(swap, dev, where & ~3, result);
+}
+
+static int write_config_byte(struct pci_config_swap *swap,
+			     struct pci_dev *dev,
+			     u32 where,
+			     u8 val)
+{
+	int status, shift=0;
+	u32 result;
+
+	status = read_config_dword(swap, dev, where & ~3, &result);
+	if (status != PCIBIOS_SUCCESSFUL) return status;
+
+        if (where & 2)
+                shift += 16;
+        if (where & 1)
+                shift += 8;
+        result &= ~(0xff << shift);
+        result |= val << shift;
+        return write_config_dword(swap, dev, where & ~3, result);
+}
+
+#define	MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
+static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
+{ \
+     return rw##_config_##unitname(pciswap, \
+                                   dev, \
+                                   where, \
+                                   val); \
+}
+
+MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
+
+MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
+
+struct pci_ops ddb5476_ext_pci_ops ={
+	extpci_read_config_byte,
+	extpci_read_config_word,
+	extpci_read_config_dword,
+	extpci_write_config_byte,
+	extpci_write_config_word,
+	extpci_write_config_dword
+};
+
+
+#if defined(CONFIG_DEBUG)
+void jsun_scan_pci_bus(void)
+{
+	struct pci_bus bus;
+	struct pci_dev dev;
+	unsigned int devfn;
+	int j;
+
+	pci_config_workaround = 0;
+
+	bus.parent = NULL;	/* we scan the top level only */
+	dev.bus = &bus;
+	dev.sysdata = NULL;
+
+	/* scan ext pci bus and io pci bus*/
+	for (j=0; j< 1; j++) {
+		printk(KERN_INFO "scan ddb5476 external PCI bus:\n");
+		bus.ops = &ddb5476_ext_pci_ops;
+	
+		for (devfn = 0; devfn < 0x100; devfn += 8) {
+			u32 temp;
+			u16 temp16;
+			u8 temp8;
+			int i;
+
+			dev.devfn = devfn;
+			db_verify(pci_read_config_dword(&dev, 0, &temp),
+				    == PCIBIOS_SUCCESSFUL);
+			if (temp == 0xffffffff) continue;
+
+			printk(KERN_INFO "slot %d: (addr %d) \n", devfn/8,
+			       11+devfn/8);
+
+			/* verify read word and byte */
+			db_verify(pci_read_config_word(&dev, 2, &temp16),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp16 == (temp >> 16));
+			db_verify(pci_read_config_byte(&dev, 3, &temp8),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp8 == (temp >> 24));
+			db_verify(pci_read_config_byte(&dev, 1, &temp8),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp8 == ((temp >> 8) & 0xff));
+
+			for (i=0; i < 16; i++) {
+				if ((i%4) == 0)
+					printk(KERN_INFO);
+				db_verify(pci_read_config_dword(&dev, i*4, &temp),
+					  == PCIBIOS_SUCCESSFUL);
+				printk("\t%08X", temp);
+				if ((i%4) == 3)
+					printk("\n");
+			}
+		}
+	}
+
+	pci_config_workaround = 1;
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/setup.c linux/arch/mips/ddb5xxx/ddb5476/setup.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/setup.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,331 @@
+/*
+ *  arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kbd_ll.h>
+#include <linux/kernel.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/console.h>
+#include <linux/sched.h>
+#include <linux/mc146818rtc.h>
+#include <linux/pc_keyb.h>
+#include <linux/pci.h>
+#include <linux/ide.h>
+
+#include <asm/addrspace.h>
+#include <asm/bcache.h>
+#include <asm/keyboard.h>
+#include <asm/irq.h>
+#include <asm/reboot.h>
+#include <asm/gdb-stub.h>
+#include <asm/time.h>
+#include <asm/debug.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+// #define USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
+
+#ifdef USE_CPU_COUNTER_TIMER
+
+#define CPU_COUNTER_FREQUENCY           83000000
+#else
+/* otherwise we use general purpose timer */
+#define TIMER_FREQUENCY			83000000
+#define TIMER_BASE			DDB_T2CTRL
+#define TIMER_IRQ			(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
+#endif
+
+#ifdef CONFIG_REMOTE_DEBUG
+extern void breakpoint(void);
+#endif
+
+extern struct ide_ops std_ide_ops;
+extern struct kbd_ops std_kbd_ops;
+
+static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
+
+static void ddb_machine_restart(char *command)
+{
+	u32 t;
+
+	/* PCI cold reset */
+	t = ddb_in32(DDB_PCICTRL + 4);
+	t |= 0x40000000;
+	ddb_out32(DDB_PCICTRL + 4, t);
+	/* CPU cold reset */
+	t = ddb_in32(DDB_CPUSTAT);
+	t |= 1;
+	ddb_out32(DDB_CPUSTAT, t);
+	/* Call the PROM */
+	back_to_prom();
+}
+
+static void ddb_machine_halt(void)
+{
+	printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
+	while (1);
+}
+
+static void ddb_machine_power_off(void)
+{
+	printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
+	while (1);
+}
+
+extern void ddb_irq_setup(void);
+extern void rtc_ds1386_init(unsigned long base);
+
+static void __init ddb_time_init(void)
+{
+#if defined(USE_CPU_COUNTER_TIMER)
+	mips_counter_frequency = CPU_COUNTER_FREQUENCY;
+#endif
+
+	/* we have ds1396 RTC chip */
+	rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
+}
+
+
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+static void __init ddb_timer_setup(struct irqaction *irq)
+{
+#if defined(USE_CPU_COUNTER_TIMER)
+
+	unsigned int count;
+
+	/* we are using the cpu counter for timer interrupts */
+	setup_irq(CPU_IRQ_BASE + 7, irq);
+
+	/* to generate the first timer interrupt */
+	count = read_32bit_cp0_register(CP0_COUNT);
+	write_32bit_cp0_register(CP0_COMPARE, count + 1000);
+
+#else
+
+	ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
+	ddb_out32(TIMER_BASE+4, 0x1);	/* enable timer */
+	setup_irq(TIMER_IRQ, irq);
+#endif
+}
+
+static struct {
+	struct resource dma1;
+	struct resource pic1;
+	struct resource timer;
+	struct resource rtc;
+	struct resource dma_page_reg;
+	struct resource pic2;
+	struct resource dma2;
+} ddb5476_ioport = {
+	{
+	"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
+	"pic1", 0x20, 0x3f, IORESOURCE_BUSY}, {
+	"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
+	"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
+	"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
+	"pic2", 0xa0, 0xbf, IORESOURCE_BUSY}, {
+	"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
+};
+
+static struct {
+	struct resource nile4;
+} ddb5476_iomem = {
+	{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
+};
+
+static void ddb5476_board_init(void);
+extern void ddb5476_irq_setup(void);
+extern void (*irq_setup)(void);
+
+void __init 
+ddb_setup(void)
+{
+	extern int panic_timeout;
+
+	irq_setup = ddb5476_irq_setup;
+	set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
+
+	board_time_init = ddb_time_init;
+	board_timer_setup = ddb_timer_setup;
+
+	_machine_restart = ddb_machine_restart;
+	_machine_halt = ddb_machine_halt;
+	_machine_power_off = ddb_machine_power_off;
+
+	/* request io port/mem resources  */
+	if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
+	    request_resource(&ioport_resource, &ddb5476_ioport.pic1) ||
+	    request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
+	    request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
+	    request_resource(&ioport_resource,
+			     &ddb5476_ioport.dma_page_reg)
+	    || request_resource(&ioport_resource, &ddb5476_ioport.pic2)
+	    || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
+	    || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
+		printk
+		    ("ddb_setup - requesting oo port resources failed.\n");
+		for (;;);
+	}
+#ifdef CONFIG_BLK_DEV_IDE
+	ide_ops = &std_ide_ops;
+#endif
+
+#ifdef CONFIG_PC_KEYB
+	kbd_ops = &std_kbd_ops;
+#endif
+
+	/* Reboot on panic */
+	panic_timeout = 180;
+
+	/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
+	/* *(long*)0xbfa00218 = 0x8; */
+
+#ifdef CONFIG_FB
+	conswitchp = &dummy_con;
+#endif
+
+	/* board initialization stuff */
+	ddb5476_board_init();
+}
+
+/*
+ * We don't trust bios.  We essentially does hardware re-initialization
+ * as complete as possible, as far as we know we can safely do.
+ */
+static void 
+ddb5476_board_init(void)
+{
+	/* ----------- setup PDARs ------------ */
+	/* check SDRAM0, whether we are on MEM bus does not matter */
+	db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
+		  ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
+
+	/* SDRAM1 should be turned off.  What is this for anyway ? */
+	db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+
+	/* flash 1&2, DDB status, DDB control */
+	ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
+	ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
+	ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
+	ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
+
+	/* shut off other pdar so they don't accidentally get into the way */
+	ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
+	ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
+	ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
+
+	/* verify VRC5477 base addr */
+	/* don't care about some details */
+	db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
+		  ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
+
+	/* verify BOOT ROM addr */
+	/* don't care about some details */
+	db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
+		  ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+
+	/* setup PCI windows - window1 for MEM/config, window0 for IO */
+	ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
+	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+
+	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
+	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
+
+	/* ----------- setup PDARs ------------ */
+	/* this is problematic - it will reset Aladin which cause we loose
+	 * serial port, and we don't know how to set up Aladin chip again.
+	 */
+	// ddb_pci_reset_bus(); 
+
+	ddb_out32(DDB_BAR0, 0x00000008);
+
+	ddb_out32(DDB_BARC, 0xffffffff);
+	ddb_out32(DDB_BARB, 0xffffffff);
+	ddb_out32(DDB_BAR1, 0xffffffff);
+	ddb_out32(DDB_BAR2, 0xffffffff);
+	ddb_out32(DDB_BAR3, 0xffffffff);
+	ddb_out32(DDB_BAR4, 0xffffffff);
+	ddb_out32(DDB_BAR5, 0xffffffff);
+	ddb_out32(DDB_BAR6, 0xffffffff);
+	ddb_out32(DDB_BAR7, 0xffffffff);
+	ddb_out32(DDB_BAR8, 0xffffffff);
+
+	/* ----------- switch PCI1 to PCI CONFIG space  ------------ */
+	ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
+	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
+
+	/* ----- M1543 PCI setup ------ */
+
+	/* we know M1543 PCI-ISA controller is at addr:18 */
+	/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
+	*(volatile unsigned char *) 0xa8040072 &= 0xf0;
+	*(volatile unsigned char *) 0xa8040072 |= 0xa;
+
+	/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
+	 * no IOCHRDY signal, (bit 7 - 1)
+	 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
+	 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
+	 */
+	*(unsigned char *) 0xa8040074 = 0xd1;
+
+	/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
+	 * SCI routing to IRQ 13 disabled (bit 7 - 1)
+	 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
+	 */
+	*(unsigned char *) 0xa8040076 = 0x83;
+
+	/* setup IDE controller
+	 * enable IDE controller (bit 6 - 1)
+	 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
+	 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
+	 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
+	 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
+	 */
+	// *(unsigned char*)0xa8040058 = 0x71;
+	// *(unsigned char*)0xa8040058 = 0x79;
+	// *(unsigned char*)0xa8040058 = 0x74;              // use SIRQ, primary tri-state
+	*(unsigned char *) 0xa8040058 = 0x75;	// primary tri-state
+
+#if 0
+	/* this is not necessary if M5229 does not use SIRQ */
+	*(unsigned char *) 0xa8040044 = 0x0d;	// primary to IRQ 14
+	*(unsigned char *) 0xa8040075 = 0x0d;	// secondary to IRQ 14
+#endif
+
+	/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
+	/* M5229 IDSEL is addr:24; see above setting */
+	*(unsigned char *) 0xa9000050 |= 0x1;
+
+	/* enable bus master (bit 2)  and IO decoding  (bit 0) */
+	*(unsigned char *) 0xa9000004 |= 0x5;
+
+	/* enable native, copied from arch/ppc/k2boot/head.S */
+	/* TODO - need volatile, need to be portable */
+	*(unsigned char *) 0xa9000009 = 0xff;
+
+	/* ----- end of M1543 PCI setup ------ */
+
+	/* ----- reset on-board ether chip  ------ */
+	*((volatile u32 *) 0xa8020004) |= 1;	/* decode I/O */
+	*((volatile u32 *) 0xa8020010) = 0;	/* set BAR address */
+
+	/* send reset command */
+	*((volatile u32 *) 0xa6000000) = 1;	/* do a soft reset */
+
+	/* disable ether chip */
+	*((volatile u32 *) 0xa8020004) = 0;	/* disable any decoding */
+
+	/* put it into sleep */
+	*((volatile u32 *) 0xa8020040) = 0x80000000;
+
+	/* ----- end of reset on-board ether chip  ------ */
+
+	/* ----------- switch PCI1 back to PCI MEM space  ------------ */
+	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
+	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
--- linux.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,113 @@
+/*
+ * The irq controller for vrc5476.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+#include <asm/system.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+static int irq_base;
+
+static void vrc5476_irq_enable(uint irq)
+{
+	nile4_enable_irq(irq - irq_base);
+}
+
+static void vrc5476_irq_disable(uint irq)
+{
+	nile4_disable_irq(irq - irq_base);
+}
+
+static unsigned int vrc5476_irq_startup(uint irq)
+{
+	nile4_enable_irq(irq - irq_base);
+	return 0;
+}
+
+#define vrc5476_irq_shutdown	vrc5476_irq_disable
+
+static void vrc5476_irq_ack(uint irq)
+{
+	nile4_clear_irq(irq - irq_base);
+	nile4_disable_irq(irq - irq_base);
+}
+
+static void vrc5476_irq_end(uint irq)
+{
+	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		vrc5476_irq_enable(irq);
+}
+
+static hw_irq_controller vrc5476_irq_controller = {
+	"vrc5476",
+	vrc5476_irq_startup,
+	vrc5476_irq_shutdown,
+	vrc5476_irq_enable,
+	vrc5476_irq_disable,
+	vrc5476_irq_ack,
+	vrc5476_irq_end,
+	NULL				/* no affinity stuff for UP */
+};
+
+void __init 
+vrc5476_irq_init(u32 base)
+{
+	extern irq_desc_t irq_desc[];
+	u32 i;
+
+	irq_base = base;
+	for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = NULL;
+		 irq_desc[i].depth = 1;
+		 irq_desc[i].handler = &vrc5476_irq_controller;
+	}
+}
+
+
+asmlinkage void 
+vrc5476_irq_dispatch(struct pt_regs *regs)
+{
+	extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
+	extern void spurious_interrupt(void);
+
+	u32 mask;
+	int nile4_irq;
+
+	mask = nile4_get_irq_stat(0);
+
+	/* quick check for possible time interrupt */
+	if (mask & (1 << VRC5476_IRQ_GPT)) {
+		do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
+		return;
+	}
+
+	/* check for i8259 interrupts */
+	if (mask & (1 << VRC5476_I8259_CASCADE)) {
+		int i8259_irq = nile4_i8259_iack();
+		do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
+		return;
+	}
+
+	/* regular nile4 interrupts (we should not really have any */
+	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
+		if (mask & 1) {
+			do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
+			return;
+		}
+	}
+	spurious_interrupt();
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/Makefile linux/arch/mips/ddb5xxx/ddb5477/Makefile
--- linux.orig/arch/mips/ddb5xxx/ddb5477/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/Makefile	2002-08-01 06:42:38.000000000 +0000
@@ -13,9 +13,9 @@
 
 O_TARGET:= ddb5477.o
 
-obj-y	 += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o
+obj-y	 += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o lcd44780.o
 
-obj-$(CONFIG_LL_DEBUG) 		+= debug.o
+obj-$(CONFIG_DEBUG) 		+= debug.o
 obj-$(CONFIG_REMOTE_DEBUG)	+= kgdb_io.o
 obj-$(CONFIG_BLK_DEV_INITRD)	+= ramdisk.o
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/debug.c linux/arch/mips/ddb5xxx/ddb5477/debug.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/debug.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/debug.c	2002-08-01 06:42:34.000000000 +0000
@@ -15,8 +15,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/signal.h>		/* SA_INTERRUPT */
 
 #include <asm/mipsregs.h>
 #include <asm/ddb5xxx/ddb5xxx.h>
@@ -64,9 +62,9 @@
 static Register pdar_regs[] = {
         {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
         {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
-        {"DDB_LDCS0", DDB_BASE + DDB_LDCS0},
-        {"DDB_LDCS1", DDB_BASE + DDB_LDCS1},
-        {"DDB_LDCS2", DDB_BASE + DDB_LDCS2},
+        {"DDB_LCS0", DDB_BASE + DDB_LCS0},
+        {"DDB_LCS1", DDB_BASE + DDB_LCS1},
+        {"DDB_LCS2", DDB_BASE + DDB_LCS2},
         {"DDB_INTCS", DDB_BASE + DDB_INTCS},
         {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
         {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/irq.c linux/arch/mips/ddb5xxx/ddb5477/irq.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/irq.c	2002-08-01 06:42:32.000000000 +0000
@@ -12,16 +12,16 @@
  */
 #include <linux/config.h>
 #include <linux/init.h>
-#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/types.h>
 #include <linux/ptrace.h>
 
 #include <asm/system.h>
 #include <asm/mipsregs.h>
+#include <asm/debug.h>
+
 #include <asm/ddb5xxx/ddb5xxx.h>
 
-/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
 
 /*
  * IRQ mapping
@@ -76,7 +76,7 @@
 void
 ddb5477_irq_setup(void)
 {
-	MIPS_DEBUG(printk("ddb5477_irq_setup invoked.\n"));
+	db_run(printk("ddb5477_irq_setup invoked.\n"));
 
 	/* by default, we disable all interrupts and route all vrc5477 
 	 * interrupts to pin 0 (irq 2) */
@@ -141,16 +141,16 @@
 	u32 bitmask;
 	u32 i;
 
-	MIPS_ASSERT(ddb_in32(DDB_INT2STAT) == 0);
-	MIPS_ASSERT(ddb_in32(DDB_INT3STAT) == 0);
-	MIPS_ASSERT(ddb_in32(DDB_INT4STAT) == 0);
-	MIPS_ASSERT(ddb_in32(DDB_NMISTAT) == 0);
+	db_assert(ddb_in32(DDB_INT2STAT) == 0);
+	db_assert(ddb_in32(DDB_INT3STAT) == 0);
+	db_assert(ddb_in32(DDB_INT4STAT) == 0);
+	db_assert(ddb_in32(DDB_NMISTAT) == 0);
 
 	if (ddb_in32(DDB_INT1STAT) != 0) {
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
 		vrc5477_show_int_regs();
 #endif
-		panic("error interrupt has happened.\n");
+		panic("error interrupt has happened.");
 	}
 
 	intStatus = ddb_in32(DDB_INT0STAT);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/irq_5477.c linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/irq_5477.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c	2002-08-01 06:42:36.000000000 +0000
@@ -1,4 +1,4 @@
-/***********************************************************************
+/*
  * Copyright 2001 MontaVista Software Inc.
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *
@@ -9,7 +9,7 @@
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
- ***********************************************************************
+ *
  */
 
 /*
@@ -18,28 +18,26 @@
  * This file exports one function:
  *	vrc5477_irq_init(u32 irq_base);
  */
-
-#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/types.h>
 #include <linux/ptrace.h>
 
-#include <asm/ddb5xxx/ddb5xxx.h>
+#include <asm/debug.h>
 
-/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
 
 /* number of total irqs supported by Vrc5477 */
 #define	NUM_5477_IRQ		32
 
-static int vrc5477_irq_base=-1;
+static int vrc5477_irq_base = -1;
 
 
 static void 
 vrc5477_irq_enable(unsigned int irq)
 {
-	MIPS_ASSERT(vrc5477_irq_base != -1);
-	MIPS_ASSERT(irq >= vrc5477_irq_base);
-	MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+	db_assert(vrc5477_irq_base != -1);
+	db_assert(irq >= vrc5477_irq_base);
+	db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
 
 	ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
 }
@@ -47,9 +45,9 @@
 static void 
 vrc5477_irq_disable(unsigned int irq)
 {
-	MIPS_ASSERT(vrc5477_irq_base != -1);
-	MIPS_ASSERT(irq >= vrc5477_irq_base);
-	MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
+	db_assert(vrc5477_irq_base != -1);
+	db_assert(irq >= vrc5477_irq_base);
+	db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
 
 	ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
 }
@@ -65,9 +63,9 @@
 static void
 vrc5477_irq_ack(unsigned int irq)
 {
-	MIPS_ASSERT(vrc5477_irq_base != -1);
-	MIPS_ASSERT(irq >= vrc5477_irq_base);
-	MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+	db_assert(vrc5477_irq_base != -1);
+	db_assert(irq >= vrc5477_irq_base);
+	db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
 
 	/* clear the interrupt bit */
 	/* some irqs require the driver to clear the sources */
@@ -82,11 +80,12 @@
 static void
 vrc5477_irq_end(unsigned int irq)
 {
-	MIPS_ASSERT(vrc5477_irq_base != -1);
-	MIPS_ASSERT(irq >= vrc5477_irq_base);
-	MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
+	db_assert(vrc5477_irq_base != -1);
+	db_assert(irq >= vrc5477_irq_base);
+	db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
 
-	ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
+	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
 }
 
 hw_irq_controller vrc5477_irq_controller = {
@@ -119,8 +118,8 @@
 
 int vrc5477_irq_to_irq(int irq)
 {
-	MIPS_ASSERT(irq >= 0);
-	MIPS_ASSERT(irq < NUM_5477_IRQ);
+	db_assert(irq >= 0);
+	db_assert(irq < NUM_5477_IRQ);
 
 	return irq + vrc5477_irq_base;
 }
@@ -131,10 +130,10 @@
 	u32 reg_bitmask;
 	u32 reg_index;
 
-	MIPS_ASSERT(vrc5477_irq >= 0);
-	MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
-	MIPS_ASSERT(ip >= 0);
-	MIPS_ASSERT((ip < 5) || (ip == 6));
+	db_assert(vrc5477_irq >= 0);
+	db_assert(vrc5477_irq < NUM_5477_IRQ);
+	db_assert(ip >= 0);
+	db_assert((ip < 5) || (ip == 6));
 
 	reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
 	reg_value = ddb_in32(reg_index);
@@ -150,13 +149,13 @@
 	u32 reg_bitmask;
 	u32 reg_index;
 
-	MIPS_ASSERT(vrc5477_irq >= 0);
-	MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+	db_assert(vrc5477_irq >= 0);
+	db_assert(vrc5477_irq < NUM_5477_IRQ);
 
 	reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
 	reg_value = ddb_in32(reg_index);
 	reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
-	MIPS_ASSERT((reg_value & reg_bitmask) == 0);
+	db_assert((reg_value & reg_bitmask) == 0);
 	ddb_out32(reg_index, reg_value | reg_bitmask);
 }
 
@@ -166,14 +165,14 @@
 	u32 reg_bitmask;
 	u32 reg_index;
 
-	MIPS_ASSERT(vrc5477_irq >= 0);
-	MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+	db_assert(vrc5477_irq >= 0);
+	db_assert(vrc5477_irq < NUM_5477_IRQ);
 
 	reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
 	reg_value = ddb_in32(reg_index);
 	reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
 
 	/* we assert that the interrupt is enabled (perhaps over-zealous) */
-	MIPS_ASSERT( (reg_value & reg_bitmask) != 0);
+	db_assert( (reg_value & reg_bitmask) != 0);
 	ddb_out32(reg_index, reg_value & ~reg_bitmask);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/kgdb_io.c linux/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/kgdb_io.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/kgdb_io.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,17 +1,41 @@
+/*
+ * kgdb io functions for DDB5477.  We use the second serial port (upper one).
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
 
-#include <linux/config.h>
+/* ======================= CONFIG ======================== */
 
-#if (defined(CONFIG_DDB5477) && defined(CONFIG_REMOTE_DEBUG))
+/* [jsun] we use the second serial port for kdb */
+#define         BASE                    0xbfa04240
+#define         MAX_BAUD                115200
 
-/* --- CONFIG --- */
+/* distance in bytes between two serial registers */
+#define         REG_OFFSET              8
+
+/*
+ * 0 - kgdb does serial init
+ * 1 - kgdb skip serial init
+ */
+static int remoteDebugInitialized = 0;
+
+/*
+ * the default baud rate *if* kgdb does serial init
+ */
+#define		BAUD_DEFAULT		UART16550_BAUD_38400
+
+/* ======================= END OF CONFIG ======================== */
 
-/* we need uint32 uint8 */
-/* #include "types.h" */
 typedef unsigned char uint8;
 typedef unsigned int uint32;
 
-/* --- END OF CONFIG --- */
-
 #define         UART16550_BAUD_2400             2400
 #define         UART16550_BAUD_4800             4800
 #define         UART16550_BAUD_9600             9600
@@ -34,21 +58,10 @@
 #define         UART16550_STOP_1BIT             0x0
 #define         UART16550_STOP_2BIT             0x4
 
-/* ----------------------------------------------------- */
-
-/* === CONFIG === */
-
-/* [jsun] we use the second serial port for kdb */
-#define         BASE                    0xbfa04240
-#define         MAX_BAUD                115200
-#define		REG_OFFSET		8
-
-/* === END OF CONFIG === */
-
 /* register offset */
-#define         OFS_RCV_BUFFER          (0*REG_OFFSET)
-#define         OFS_TRANS_HOLD          (0*REG_OFFSET)
-#define         OFS_SEND_BUFFER         (0*REG_OFFSET)
+#define         OFS_RCV_BUFFER          0
+#define         OFS_TRANS_HOLD          0
+#define         OFS_SEND_BUFFER         0
 #define         OFS_INTR_ENABLE         (1*REG_OFFSET)
 #define         OFS_INTR_ID             (2*REG_OFFSET)
 #define         OFS_DATA_FORMAT         (3*REG_OFFSET)
@@ -70,73 +83,54 @@
 
 void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 {
-	/* disable interrupts */
-	UART16550_WRITE(OFS_INTR_ENABLE, 0);
+        /* disable interrupts */
+        UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-	/* set up buad rate */
-	{
-		uint32 divisor;
-
-		/* set DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-		/* set divisor */
-		divisor = MAX_BAUD / baud;
-		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
-		/* clear DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-	}
+        /* set up buad rate */
+        {
+                uint32 divisor;
+
+                /* set DIAB bit */
+                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+                /* set divisor */
+                divisor = MAX_BAUD / baud;
+                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+                /* clear DIAB bit */
+                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+        }
 
-	/* set data format */
-	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+        /* set data format */
+        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
 }
 
-static int remoteDebugInitialized = 0;
-
-int debug_state = -1;
 
 uint8 getDebugChar(void)
 {
-	uint8 c;
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
+        if (!remoteDebugInitialized) {
+                remoteDebugInitialized = 1;
+                debugInit(BAUD_DEFAULT,
+                          UART16550_DATA_8BIT,
+                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+        }
 
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-	c= UART16550_READ(OFS_RCV_BUFFER);
-/*
-	if (state != 1) {
-		state = 1;
-		debug_out("\ngetDebugChar: ", 15);
-	}
-	debug_out(&c, 1);
-*/
-	return c;
+        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+        return UART16550_READ(OFS_RCV_BUFFER);
 }
 
 
 int putDebugChar(uint8 byte)
 {
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_9600,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-	UART16550_WRITE(OFS_SEND_BUFFER, byte);
-	if (debug_state != 2) {
-		debug_state = 2;
-		// debug_out("\nputDebugChar: ", 15);
-	}
-	// debug_out(&byte, 1);
-	return 1;
+        if (!remoteDebugInitialized) {
+                remoteDebugInitialized = 1;
+                debugInit(BAUD_DEFAULT,
+                          UART16550_DATA_8BIT,
+                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+        }
+
+        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
+        UART16550_WRITE(OFS_SEND_BUFFER, byte);
+        return 1;
 }
-
-#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/lcd44780.c linux/arch/mips/ddb5xxx/ddb5477/lcd44780.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/lcd44780.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/lcd44780.c	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,92 @@
+/*
+ * lcd44780.c
+ * Simple "driver" for a memory-mapped 44780-style LCD display.
+ *
+ * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#define LCD44780_COMMAND   ((volatile unsigned char *)0xbe020000)
+#define LCD44780_DATA      ((volatile unsigned char *)0xbe020001)
+
+#define LCD44780_4BIT_1LINE        0x20
+#define LCD44780_4BIT_2LINE        0x28
+#define LCD44780_8BIT_1LINE        0x30
+#define LCD44780_8BIT_2LINE        0x38
+#define LCD44780_MODE_DEC          0x04
+#define LCD44780_MODE_DEC_SHIFT    0x05
+#define LCD44780_MODE_INC          0x06
+#define LCD44780_MODE_INC_SHIFT    0x07
+#define LCD44780_SCROLL_LEFT       0x18
+#define LCD44780_SCROLL_RIGHT      0x1e
+#define LCD44780_CURSOR_UNDERLINE  0x0e
+#define LCD44780_CURSOR_BLOCK      0x0f
+#define LCD44780_CURSOR_OFF        0x0c
+#define LCD44780_CLEAR             0x01
+#define LCD44780_BLANK             0x08
+#define LCD44780_RESTORE           0x0c  // Same as CURSOR_OFF
+#define LCD44780_HOME              0x02
+#define LCD44780_LEFT              0x10
+#define LCD44780_RIGHT             0x14
+
+void lcd44780_wait(void)
+{
+	int i, j;
+	for(i=0; i < 400; i++)
+		for(j=0; j < 10000; j++);
+}
+
+void lcd44780_command(unsigned char c)
+{
+	*LCD44780_COMMAND = c;
+	lcd44780_wait();
+}
+
+void lcd44780_data(unsigned char c)
+{
+	*LCD44780_DATA = c;
+	lcd44780_wait();
+}
+
+void lcd44780_puts(const char* s)
+{
+	int i,j;
+	int pos = 0;
+
+	lcd44780_command(LCD44780_CLEAR);
+	while(*s) {
+		lcd44780_data(*s);
+		s++;
+		pos++;
+		if (pos == 8) {
+		  /* We must write 32 of spaces to get cursor to 2nd line */
+		  for (j=0; j<32; j++) {
+		    lcd44780_data(' ');
+		  }
+		}
+		if (pos == 16) {
+		  /* We have filled all 16 character positions, so stop
+		     outputing data */
+		  break;
+		}
+	}
+#ifdef LCD44780_PUTS_PAUSE
+	for(i = 1; i < 2000; i++)
+		lcd44780_wait();
+#endif
+}
+
+void lcd44780_init(void)
+{
+	// The display on the RockHopper is physically a single
+	// 16 char line (two 8 char lines concatenated).  bdl
+	lcd44780_command(LCD44780_8BIT_2LINE);
+	lcd44780_command(LCD44780_MODE_INC);
+	lcd44780_command(LCD44780_CURSOR_BLOCK);
+	lcd44780_command(LCD44780_CLEAR);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/lcd44780.h linux/arch/mips/ddb5xxx/ddb5477/lcd44780.h
--- linux.orig/arch/mips/ddb5xxx/ddb5477/lcd44780.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/lcd44780.h	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,15 @@
+/*
+ * lcd44780.h
+ * Simple "driver" for a memory-mapped 44780-style LCD display.
+ *
+ * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+void lcd44780_puts(const char* s);
+void lcd44780_init(void);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/pci.c linux/arch/mips/ddb5xxx/ddb5477/pci.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/pci.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/pci.c	2002-08-01 06:42:44.000000000 +0000
@@ -1,11 +1,25 @@
+/*
+ * PCI code for DDB5477.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 
+#include <asm/pci_channel.h>
+#include <asm/debug.h>
+
 #include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/ddb5xxx/debug.h>
-#include <asm/ddb5xxx/pci.h>
 
 static struct resource extpci_io_resource = {
 	"ext pci IO space", 
@@ -103,8 +117,16 @@
 
 	pci_for_each_dev(dev) {
 		slot_num = PCI_SLOT(dev->devfn);
-		MIPS_ASSERT(slot_num < MAX_SLOT_NUM);
-		MIPS_ASSERT(irq_map[slot_num] != 0xff);
+
+               /* we don't do IRQ fixup for sub-bus yet */
+               if (dev->bus->parent != NULL) {
+                       db_run(printk("Don't know how to fixup irq for PCI device %d on sub-bus %d\n",
+                                       slot_num, dev->bus->number));
+                       continue;
+               }
+
+		db_assert(slot_num < MAX_SLOT_NUM);
+		db_assert(irq_map[slot_num] != 0xff);
 
 		pci_write_config_byte(dev, 
 				      PCI_INTERRUPT_LINE,
@@ -113,7 +135,7 @@
 	}
 }
 
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
 extern void jsun_scan_pci_bus(void);
 extern void jsun_assign_pci_resource(void);
 #endif
@@ -143,5 +165,15 @@
 
 unsigned __init int pcibios_assign_all_busses(void)
 {
+	/* we hope pci_auto has assigned the bus numbers to all buses */
 	return 1;
 }
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/pci_ops.c linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/pci_ops.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c	2002-08-01 06:42:28.000000000 +0000
@@ -26,7 +26,8 @@
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
+
 #include <asm/ddb5xxx/ddb5xxx.h>
 
 /*
@@ -72,14 +73,11 @@
         u32 virt_addr = swap->config_base;
 	u32 option;
 
-	/* [jsun] hack for testing */
-	// if (slot_num == 4) slot_num = 0;
-
 	/* minimum pdar (window) size is 2MB */
-	MIPS_ASSERT(swap->config_size >= (2 << 20));
+	db_assert(swap->config_size >= (2 << 20));
 
-	MIPS_ASSERT(slot_num < (1 << 5));
-	MIPS_ASSERT(bus < (1 << 8));
+	db_assert(slot_num < (1 << 5));
+	db_assert(bus < (1 << 8));
 
 	/* backup registers */
 	swap->pdar_backup = ddb_in32(swap->pdar);
@@ -103,7 +101,6 @@
 	} else {
 		/* type 1 config */
 		pci_addr = (bus << 16) | (slot_num << 11);
-		panic("ddb_access_config_base: we don't support type 1 config Yet");
 	}
 
 	/*
@@ -115,7 +112,7 @@
 		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
 		pciinit_offset = 0;
 	} else {
-		MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
+		db_assert( (pci_addr & (swap->config_size - 1)) == 0);
 		virt_addr = KSEG1ADDR(swap->config_base);
 		pciinit_offset = pci_addr;
 	}
@@ -142,13 +139,13 @@
 	u32 bus, slot_num, func_num;
 	u32 base;
 
-	MIPS_ASSERT((where & 3) == 0);
-	MIPS_ASSERT(where < (1 << 8));
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));
 
 	/* check if the bus is top-level */
 	if (dev->bus->parent != NULL) {
 		bus = dev->bus->number;
-		MIPS_ASSERT(bus != 0);
+		db_assert(bus != 0);
 	} else {
 		bus = 0;
 	}
@@ -169,7 +166,7 @@
         int status;
         u32 result;
 
-	MIPS_ASSERT((where & 1) == 0);
+	db_assert((where & 1) == 0);
 
         status = read_config_dword(swap, dev, where & ~3, &result);
         if (where & 2) result >>= 16;
@@ -200,13 +197,13 @@
 	u32 bus, slot_num, func_num;
 	u32 base;
 
-	MIPS_ASSERT((where & 3) == 0);
-	MIPS_ASSERT(where < (1 << 8));
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));
 
 	/* check if the bus is top-level */
 	if (dev->bus->parent != NULL) {
 		bus = dev->bus->number;
-		MIPS_ASSERT(bus != 0);
+		db_assert(bus != 0);
 	} else {
 		bus = 0;
 	}
@@ -227,7 +224,7 @@
 	int status, shift=0;
 	u32 result;
 
-	MIPS_ASSERT((where & 1) == 0);
+	db_assert((where & 1) == 0);
 
 	status = read_config_dword(swap, dev, where & ~3, &result);
 	if (status != PCIBIOS_SUCCESSFUL) return status;
@@ -303,7 +300,7 @@
 	iopci_write_config_dword
 };
 
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
 void jsun_scan_pci_bus(void)
 {
 	struct pci_bus bus;
@@ -332,26 +329,26 @@
 			int i;
 
 			dev.devfn = devfn;
-			MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
-				    == PCIBIOS_SUCCESSFUL);
+			db_verify(pci_read_config_dword(&dev, 0, &temp),
+				  == PCIBIOS_SUCCESSFUL);
 			if (temp == 0xffffffff) continue;
 
 			printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8);
 
 			/* verify read word and byte */
-			MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
-				    == PCIBIOS_SUCCESSFUL);
-			MIPS_ASSERT(temp16 == (temp >> 16));
-			MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
-				    == PCIBIOS_SUCCESSFUL);
-			MIPS_ASSERT(temp8 == (temp >> 24));
-			MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
-				    == PCIBIOS_SUCCESSFUL);
-			MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));
+			db_verify(pci_read_config_word(&dev, 2, &temp16),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp16 == (temp >> 16));
+			db_verify(pci_read_config_byte(&dev, 3, &temp8),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp8 == (temp >> 24));
+			db_verify(pci_read_config_byte(&dev, 1, &temp8),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp8 == ((temp >> 8) & 0xff));
 
 			for (i=0; i < 16; i++) {
-				MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
-					    == PCIBIOS_SUCCESSFUL);
+				db_verify(pci_read_config_dword(&dev, i*4, &temp),
+					  == PCIBIOS_SUCCESSFUL);
 				printk("\t%08X", temp);
 				if ((i%4) == 3) printk("\n");
 			}
@@ -374,7 +371,7 @@
 	/* for slot 5 (ext pci 1) eepro card */
 	dev.devfn = 5*8;
 	pci_read_config_dword(&dev, 0, &temp);
-	MIPS_ASSERT(temp == 0x12298086);
+	db_assert(temp == 0x12298086);
 
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE);
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0);
@@ -396,7 +393,7 @@
 	/* for slot 4 on board ether chip */
 	dev.devfn = 4*8;
 	pci_read_config_dword(&dev, 0, &temp);
-	MIPS_ASSERT(temp == 0x00191011);
+	db_assert(temp == 0x00191011);
 
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000);
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ddb5xxx/ddb5477/setup.c linux/arch/mips/ddb5xxx/ddb5477/setup.c
--- linux.orig/arch/mips/ddb5xxx/ddb5477/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ddb5xxx/ddb5477/setup.c	2002-08-01 06:42:38.000000000 +0000
@@ -10,10 +10,7 @@
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
- *
- ***********************************************************************
  */
-
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -27,18 +24,21 @@
 #include <linux/ioport.h>
 #include <linux/param.h>	/* for HZ */
 
+#include <asm/bootinfo.h>
 #include <asm/addrspace.h>
 #include <asm/time.h>
 #include <asm/bcache.h>
 #include <asm/irq.h>
 #include <asm/reboot.h>
 #include <asm/gdb-stub.h>
+#include <asm/debug.h>
 
 #include <asm/ddb5xxx/ddb5xxx.h>
 
+#include "lcd44780.h"
 
 
-#define	USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
+// #define	USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
 
 #ifdef USE_CPU_COUNTER_TIMER
 #define	CPU_COUNTER_FREQUENCY		83000000
@@ -60,7 +60,7 @@
 
 	/* CPU cold reset */
 	t = ddb_in32(DDB_CPUSTAT);
-	MIPS_ASSERT((t&1));
+	db_assert((t&1));
 	ddb_out32(DDB_CPUSTAT, t);
 
 	/* Call the PROM */
@@ -87,13 +87,13 @@
 #endif
 
 	/* we have ds1396 RTC chip */
-	rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE));
+	if (mips_machtype == MACH_NEC_ROCKHOPPER) {
+		rtc_ds1386_init(KSEG1ADDR(DDB_LCS2_BASE));
+	} else {
+		rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE));
+	}
 }
 
-#if defined(CONFIG_LL_DEBUG)
-int  board_init_done_flag = 0;
-#endif
-
 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 static void __init ddb_timer_setup(struct irqaction *irq)
 {
@@ -115,9 +115,6 @@
 	setup_irq(SP_TIMER_IRQ, irq);
 
 #endif
-	
-	/* this is the last board dependent code */
-	MIPS_DEBUG(board_init_done_flag = 1);
 }
 
 static void ddb5477_board_init(void);
@@ -132,7 +129,7 @@
 	extern int panic_timeout;
 
 	irq_setup = ddb5477_irq_setup;
-	mips_io_port_base = KSEG1ADDR(DDB_PCI_IO_BASE);
+	set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
 
 	board_time_init = ddb_time_init;
 	board_timer_setup = ddb_timer_setup;
@@ -148,6 +145,10 @@
 	/* Reboot on panic */
 	panic_timeout = 180;
 
+#ifdef CONFIG_FB
+	conswitchp = &dummy_con;
+#endif
+
 	/* initialize board - we don't trust the loader */
 	ddb5477_board_init();
 
@@ -156,7 +157,6 @@
 	initrd_start = (unsigned long)&__rd_start;
 	initrd_end = (unsigned long)&__rd_end;
 #endif
-
 }
 
 static void __init ddb5477_board_init()
@@ -164,27 +164,41 @@
 	/* ----------- setup PDARs ------------ */
 
 	/* SDRAM should have been set */
-	MIPS_ASSERT(ddb_in32(DDB_SDRAM0) == 
-		    ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
+	db_assert(ddb_in32(DDB_SDRAM0) == 
+		    ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
 
 	/* SDRAM1 should be turned off.  What is this for anyway ? */
-	MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+	db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+
+	/* Setup local bus. */
 
-	/* Set LDCSs */
-	/* flash */
+	/* Flash U12 PDAR and timing. */
 	ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
-	/* misc */
-	ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
-	/* mezzanie (?) */
-	ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
+	ddb_out32(DDB_LCST0, 0x00090842);
+
+	/* We need to setup LCS1 and LCS2 differently based on the
+	   board_version */
+	if (mips_machtype == MACH_NEC_ROCKHOPPER) {
+		/* Flash U13 PDAR and timing. */
+		ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
+		ddb_out32(DDB_LCST1, 0x00090842);
+
+		/* EPLD (NVRAM, switch, LCD, and mezzanie). */
+		ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
+	} else {
+		/* misc */
+		ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
+		/* mezzanie (?) */
+		ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
+	}
 
 	/* verify VRC5477 base addr */
-	MIPS_ASSERT(ddb_in32(DDB_VRC5477) == 
-		    ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
+	db_assert(ddb_in32(DDB_VRC5477) == 
+		  ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
 	
 	/* verify BOOT ROM addr */
-	MIPS_ASSERT(ddb_in32(DDB_BOOTCS) == 
-		    ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+	db_assert(ddb_in32(DDB_BOOTCS) == 
+		  ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
 
 	/* setup PCI windows - window0 for MEM/config, window1 for IO */
 	ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
@@ -248,4 +262,10 @@
 	/* For dual-function pins, make them all non-GPIO */
 	ddb_out32(DDB_GIUFUNSEL, 0x0);
 	// ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff);  /* NEC recommanded value */
+
+	if (mips_machtype == MACH_NEC_ROCKHOPPER) {
+		printk("lcd44780: initializing\n");
+		lcd44780_init();
+		lcd44780_puts("Linux/MIPS rolls");
+	}
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/Makefile linux/arch/mips/dec/Makefile
--- linux.orig/arch/mips/dec/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/Makefile	2002-08-01 06:42:38.000000000 +0000
@@ -6,17 +6,15 @@
 # unless it's something special (ie not a .c file).
 #
 
-.S.s:
-	$(CPP) $(AFLAGS) $< -o $@
-.S.o:
-	$(CC) $(AFLAGS) -c $< -o $@
+USE_STANDARD_AS_RULE := true
 
 O_TARGET := dec.o
 
 all: dec.o
 
-export-objs := wbflush.o
-obj-y	 := int-handler.o setup.o irq.o time.o reset.o rtc-dec.o wbflush.o
+export-objs := setup.o wbflush.o
+obj-y	 := int-handler.o ioasic-irq.o kn02-irq.o reset.o rtc-dec.o setup.o \
+	time.o wbflush.o
 
 obj-$(CONFIG_PROM_CONSOLE)	+= promcon.o
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/boot/Makefile linux/arch/mips/dec/boot/Makefile
--- linux.orig/arch/mips/dec/boot/Makefile	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/dec/boot/Makefile	2002-08-01 06:42:45.000000000 +0000
@@ -6,10 +6,7 @@
 # unless it's something special (ie not a .c file).
 #
 
-.S.s:
-	$(CPP) $(CFLAGS) $< -o $*.s
-.S.o:
-	$(CC) $(CFLAGS) -c $< -o $*.o
+USE_STANDARD_AS_RULE := true
 
 netboot: all
 	mipsel-linux-ld -N -G 0 -T ld.ecoff ../../boot/zImage \
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/int-handler.S linux/arch/mips/dec/int-handler.S
--- linux.orig/arch/mips/dec/int-handler.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/int-handler.S	2002-08-01 06:42:33.000000000 +0000
@@ -2,7 +2,7 @@
  * arch/mips/dec/int-handler.S
  *
  * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
- * Copyright (C) 2000  Maciej W. Rozycki
+ * Copyright (C) 2000, 2001, 2002  Maciej W. Rozycki
  *
  * Written by Ralf Baechle and Andreas Busse, modified for DECStation
  * support by Paul Antoine and Harald Koerfgen.
@@ -10,6 +10,8 @@
  * completly rewritten:
  * Copyright (C) 1998 Harald Koerfgen
  *
+ * Rewritten extensively for controller-driven IRQ support
+ * by Maciej W. Rozycki.
  */
 #include <asm/asm.h>
 #include <asm/regdef.h>
@@ -17,12 +19,13 @@
 #include <asm/stackframe.h>
 #include <asm/addrspace.h>
 
+#include <asm/dec/interrupts.h>
+#include <asm/dec/ioasic_addrs.h>
+#include <asm/dec/ioasic_ints.h>
 #include <asm/dec/kn01.h>
 #include <asm/dec/kn02.h>
 #include <asm/dec/kn02xa.h>
 #include <asm/dec/kn03.h>
-#include <asm/dec/ioasic_addrs.h>
-#include <asm/dec/interrupts.h>
 
 
 		.text
@@ -84,7 +87,7 @@
  *             4        TurboChannel Slot 2
  *             5        TurboChannel Slot 3 (ASIC)
  *             6        Halt button
- *             7        FPU
+ *             7        FPU/R4k timer
  *
  * DS5000/2x's, aka kn02ca, aka maxine:
  *
@@ -97,7 +100,7 @@
  *             4        I/O write timeout
  *             5        TurboChannel (ASIC)
  *             6        Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER)
- *             7        FPU
+ *             7        FPU/R4k timer
  *
  * DS5000/2xx's, aka kn03, aka 3maxplus:
  *
@@ -110,22 +113,11 @@
  *             4        Reserved
  *             5        Memory
  *             6        Halt Button
- *             7        FPU
- *
- * We handle the IRQ according to _our_ priority.
- * Priority is:
- *
- * Highest ----     RTC
- *                  SCSI (if separate from TC)
- *                  Ethernet (if separate from TC)
- *		    Serial (if separate from TC)
- *                  TurboChannel (if there is one!)
- *                  Memory Controller (execept kmin)
- * Lowest  ----     Halt (if there is one!)
- *
- * then we just return, if multiple IRQs are pending then we will just take
- * another exception, big deal.
+ *             7        FPU/R4k timer
  *
+ * We handle the IRQ according to _our_ priority (see setup.c),
+ * then we just return.  If multiple IRQs are pending then we will
+ * just take another exception, big deal.
  */
 		.align	5
 		NESTED(decstation_handle_int, PT_SIZE, ra)
@@ -139,226 +131,157 @@
 		 * Get pending Interrupts
 		 */
 		mfc0	t0,CP0_CAUSE		# get pending interrupts
-		mfc0	t2,CP0_STATUS
-		la	t1,cpu_mask_tbl
-		and	t0,t2			# isolate allowed ones
+		mfc0	t1,CP0_STATUS
+		lw	t2,cpu_fpu_mask
+		andi	t0,ST0_IM		# CAUSE.CE may be non-zero!
+		and	t0,t1			# isolate allowed ones
 
 		beqz	t0,spurious
 
+		 and	t2,t0
+		bnez	t2,fpu			# handle FPU immediately
+
 		/*
 		 * Find irq with highest priority
 		 */
-1:		 lw	t2,(t1)
-		move	t3,t0
-		and	t3,t2
-		beq	t3,zero,1b
-		 addu	t1,PTRSIZE		# delay slot
+		 la	t1,cpu_mask_nr_tbl
+1:		lw	t2,(t1)
+		nop
+		and	t2,t0
+		beqz	t2,1b
+		 addu	t1,2*PTRSIZE		# delay slot
 
 		/*
 		 * Do the low-level stuff
 		 */
-		lw	a0,%lo(cpu_irq_nr-cpu_mask_tbl-PTRSIZE)(t1)
-		lw	t0,%lo(cpu_ivec_tbl-cpu_mask_tbl-PTRSIZE)(t1)
-		bgez	a0, handle_it		# irq_nr >= 0?
-						# irq_nr < 0: t0 contains an address
+		lw	a0,(-PTRSIZE)(t1)
+		nop
+		bgez	a0,handle_it		# irq_nr >= 0?
+						# irq_nr < 0: it is an address
 		 nop
-		jr	t0
-		 nop				# delay slot
+		jr	a0
+						# a trick to save a branch:
+		 lui	t2,KN03_IOASIC_BASE>>16	# upper part of IOASIC Address
 
 /*
  * Handle "IRQ Controller" Interrupts
  * Masked Interrupts are still visible and have to be masked "by hand".
  */
-		EXPORT(kn02_io_int)
-kn02_io_int:					# 3max
+		FEXPORT(kn02_io_int)		# 3max
 		lui	t0,KN02_CSR_ADDR>>16	# get interrupt status and mask
 		lw	t0,(t0)
-		la	t1,asic_mask_tbl
-		move	t3,t0
-		sll	t3,16			# shift interrupt status
-		b	find_int
-		 and	t0,t3			# mask out allowed ones
-
-		EXPORT(kn03_io_int)
-kn03_io_int:					# 3max+
-		lui	t2,KN03_IOASIC_BASE>>16	# upper part of IOASIC Address
-		lw	t0,SIR(t2)		# get status: IOASIC isr
-		lw	t3,SIMR(t2)		# get mask:   IOASIC isrm
-		la	t1,asic_mask_tbl
-		b	find_int
-		 and	t0,t3			# mask out allowed ones
-
-		EXPORT(kn02xa_io_int)
-kn02xa_io_int:					# 3min/maxine
-		lui	t2,KN02XA_IOASIC_BASE>>16		
-						# upper part of IOASIC Address
+		nop
+		andi	t1,t0,KN02_IRQ_ALL
+		b	1f
+		 srl	t0,16			# shift interrupt mask
+
+		FEXPORT(kn02xa_io_int)		# 3min/maxine
+		lui	t2,KN02XA_IOASIC_BASE>>16 # upper part of IOASIC Address
+
+		FEXPORT(kn03_io_int)		# 3max+ (t2 loaded earlier)
 		lw	t0,SIR(t2)		# get status: IOASIC isr
-		lw	t3,SIMR(t2)		# get mask:   IOASIC isrm
-		la	t1,asic_mask_tbl
-		and	t0,t3
+		lw	t1,SIMR(t2)		# get mask:   IOASIC isrm
+		nop
+
+1:		and	t0,t1			# mask out allowed ones
+
+		beqz	t0,spurious
 
 		/*
 		 * Find irq with highest priority
 		 */
-find_int:	beqz	t0,spurious
-
-1:		 lw	t2,(t1)
-		move	t3,t0
-		and	t3,t2
-		beq	zero,t3,1b
-		 addu	t1,PTRSIZE		# delay slot
+		 la	t1,asic_mask_nr_tbl
+2:		lw	t2,(t1)
+		nop
+		and	t2,t0
+		beq	zero,t2,2b
+		 addu	t1,2*PTRSIZE		# delay slot
 
 		/*
 		 * Do the low-level stuff
 		 */
-		lw	a0,%lo(asic_irq_nr-asic_mask_tbl-PTRSIZE)(t1)
-                nop
+		lw	a0,%lo(-PTRSIZE)(t1)
+		nop
+		bgez	a0,handle_it		# irq_nr >= 0?
+						# irq_nr < 0: it is an address
+		 nop
+		jr	a0
+		 nop				# delay slot
+
+/*
+ * Dispatch low-priority interrupts.  We reconsider all status
+ * bits again, which looks like a lose, but it makes the code
+ * simple and O(log n), so it gets compensated.
+ */
+		FEXPORT(cpu_all_int)		# HALT, timers, software junk
+		li	a0,DEC_CPU_IRQ_BASE
+		srl	t0,CAUSEB_IP
+		li	t1,CAUSEF_IP>>CAUSEB_IP	# mask
+		b	1f
+		 li	t2,4			# nr of bits / 2
+
+		FEXPORT(kn02_all_int)		# impossible ?
+		li	a0,KN02_IRQ_BASE
+		li	t1,KN02_IRQ_ALL		# mask
+		b	1f
+		 li	t2,4			# nr of bits / 2
+
+		FEXPORT(asic_all_int)		# various I/O ASIC junk
+		li	a0,IO_IRQ_BASE
+		li	t1,IO_IRQ_ALL		# mask
+		b	1f
+		 li	t2,8			# nr of bits / 2
+
+/*
+ * Dispatch DMA interrupts -- O(log n).
+ */
+		FEXPORT(asic_dma_int)		# I/O ASIC DMA events
+		li	a0,IO_IRQ_BASE+IO_INR_DMA
+		srl	t0,IO_INR_DMA
+		li	t1,IO_IRQ_DMA>>IO_INR_DMA # mask
+		li	t2,8			# nr of bits / 2
+		
+		/*
+		 * Find irq with highest priority.
+		 * Highest irq number takes precedence.
+		 */
+1:		srlv	t3,t1,t2
+2:		xor	t1,t3
+		and	t3,t0,t1
+		beqz	t3,3f
+		 nop
+		move	t0,t3
+		addu	a0,t2
+3:		srl	t2,1
+		bnez	t2,2b
+		 srlv	t3,t1,t2
 
-handle_it:	jal	do_IRQ
+handle_it:
+		jal	do_IRQ
 		 move	a1,sp
+
 		j	ret_from_irq
 		 nop
 
+fpu:
+		j	handle_fpe_int
+		 nop
+
 spurious:
 		j	spurious_interrupt
 		 nop
 		END(decstation_handle_int)
-/*
-  * Interrupt routines common to all DECStations first.
- */
-		EXPORT(dec_intr_fpu)
-dec_intr_fpu:	PANIC("Unimplemented FPU interrupt handler")
 
 /*
- * Generic unimplemented interrupt routines - ivec_tbl is initialised to
- * point all interrupts here.  The table is then filled in by machine-specific
- * initialisation in dec_setup().
+ * Generic unimplemented interrupt routines -- cpu_mask_nr_tbl
+ * and asic_mask_nr_tbl are initialized to point all interrupts here.
+ * The tables are then filled in by machine-specific initialisation
+ * in dec_setup().
  */
-		EXPORT(dec_intr_unimplemented)
-dec_intr_unimplemented:
-		mfc0	a1,CP0_CAUSE		# cheats way of printing an arg!
-		nop				# to be sure...
-		PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%x");
-
-		EXPORT(asic_intr_unimplemented)
-asic_intr_unimplemented:
+		FEXPORT(dec_intr_unimplemented)
 		move	a1,t0			# cheats way of printing an arg!
-		PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%x");
+		PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x");
 
-/*
- * FIXME: This interrupt vector table is experimental.  It is initialised with 
- *	  *_intr_unimplemented and filled in with the addresses of
- *	  machine-specific interrupt routines in dec_setup()  Paul 10/5/97.
- *
- *	  The mask_tbls contain the interrupt masks which are used. It is 
- *	  initialised with all possible interrupt status bits set, so that 
- * 	  unused Interrupts are catched.				Harald
- */
-		.data
-		EXPORT(cpu_mask_tbl)
-cpu_mask_tbl:
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000		# these two are unlikely 
-		.word	0x00000000		# to be used
-		.word	0x0000ff00		# End of list
-
-		EXPORT(cpu_irq_nr)
-cpu_irq_nr:
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000
-		.word	0x00000000		# these two are unlikely 
-		.word	0x00000000		# to be used
-		.word	0x00ffffff		# End of list
-
-		EXPORT(cpu_ivec_tbl)
-cpu_ivec_tbl:
-		PTR	dec_intr_unimplemented
-		PTR	dec_intr_unimplemented
-		PTR	dec_intr_unimplemented
-		PTR	dec_intr_unimplemented
-		PTR	dec_intr_unimplemented
-		PTR	dec_intr_unimplemented
-		PTR	dec_intr_unimplemented	# these two are unlikely
-		PTR	dec_intr_unimplemented	# to be used
-		PTR	dec_intr_unimplemented	# EOL
-
-		EXPORT(asic_mask_tbl)
-asic_mask_tbl:
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0xffffffff			# EOL
-
-		EXPORT(asic_irq_nr)
-asic_irq_nr:
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0
-		.word	0xffffffff		# EOL
+		FEXPORT(asic_intr_unimplemented)
+		move	a1,t0			# cheats way of printing an arg!
+		PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x");
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/ioasic-irq.c linux/arch/mips/dec/ioasic-irq.c
--- linux.orig/arch/mips/dec/ioasic-irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/dec/ioasic-irq.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,160 @@
+/*
+ *	linux/arch/mips/dec/ioasic-irq.c
+ *
+ *	DEC I/O ASIC interrupts.
+ *
+ *	Copyright (c) 2002  Maciej W. Rozycki
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <asm/dec/ioasic.h>
+#include <asm/dec/ioasic_addrs.h>
+#include <asm/dec/ioasic_ints.h>
+
+
+static spinlock_t ioasic_lock = SPIN_LOCK_UNLOCKED;
+
+static int ioasic_irq_base;
+
+
+static inline void unmask_ioasic_irq(unsigned int irq)
+{
+	u32 simr;
+
+	simr = ioasic_read(SIMR);
+	simr |= (1 << (irq - ioasic_irq_base));
+	ioasic_write(SIMR, simr);
+}
+
+static inline void mask_ioasic_irq(unsigned int irq)
+{
+	u32 simr;
+
+	simr = ioasic_read(SIMR);
+	simr &= ~(1 << (irq - ioasic_irq_base));
+	ioasic_write(SIMR, simr);
+}
+
+static inline void clear_ioasic_irq(unsigned int irq)
+{
+	u32 sir;
+
+	sir = ~(1 << (irq - ioasic_irq_base));
+	ioasic_write(SIR, sir);
+}
+
+static inline void enable_ioasic_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&ioasic_lock, flags);
+	unmask_ioasic_irq(irq);
+	spin_unlock_irqrestore(&ioasic_lock, flags);
+}
+
+static inline void disable_ioasic_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&ioasic_lock, flags);
+	mask_ioasic_irq(irq);
+	spin_unlock_irqrestore(&ioasic_lock, flags);
+}
+
+
+static inline unsigned int startup_ioasic_irq(unsigned int irq)
+{
+	enable_ioasic_irq(irq);
+	return 0;
+}
+
+#define shutdown_ioasic_irq disable_ioasic_irq
+
+static inline void ack_ioasic_irq(unsigned int irq)
+{
+	spin_lock(&ioasic_lock);
+	mask_ioasic_irq(irq);
+	spin_unlock(&ioasic_lock);
+}
+
+static inline void end_ioasic_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		enable_ioasic_irq(irq);
+}
+
+#define set_ioasic_affinity NULL
+
+static struct hw_interrupt_type ioasic_irq_type = {
+	"IO-ASIC",
+	startup_ioasic_irq,
+	shutdown_ioasic_irq,
+	enable_ioasic_irq,
+	disable_ioasic_irq,
+	ack_ioasic_irq,
+	end_ioasic_irq,
+	set_ioasic_affinity,
+};
+
+
+#define startup_ioasic_dma_irq startup_ioasic_irq
+
+#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
+
+#define enable_ioasic_dma_irq enable_ioasic_irq
+
+#define disable_ioasic_dma_irq disable_ioasic_irq
+
+#define ack_ioasic_dma_irq ack_ioasic_irq
+
+static inline void end_ioasic_dma_irq(unsigned int irq)
+{
+	clear_ioasic_irq(irq);
+	end_ioasic_irq(irq);
+}
+
+#define set_ioasic_dma_affinity set_ioasic_affinity
+
+static struct hw_interrupt_type ioasic_dma_irq_type = {
+	"IO-ASIC-DMA",
+	startup_ioasic_dma_irq,
+	shutdown_ioasic_dma_irq,
+	enable_ioasic_dma_irq,
+	disable_ioasic_dma_irq,
+	ack_ioasic_dma_irq,
+	end_ioasic_dma_irq,
+	set_ioasic_dma_affinity,
+};
+
+
+void __init init_ioasic_irqs(int base)
+{
+	int i;
+
+	/* Mask interrupts. */
+	ioasic_write(SIMR, 0);
+
+	for (i = base; i < base + IO_INR_DMA; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = 0;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &ioasic_irq_type;
+	}
+	for (; i < base + IO_IRQ_LINES; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = 0;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &ioasic_dma_irq_type;
+	}
+
+	ioasic_irq_base = base;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/irq.c linux/arch/mips/dec/irq.c
--- linux.orig/arch/mips/dec/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/irq.c	2002-08-01 06:42:29.000000000 +0000
@@ -19,7 +19,6 @@
 #include <asm/bitops.h>
 #include <asm/bootinfo.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
@@ -34,48 +33,52 @@
 
 extern asmlinkage void decstation_handle_int(void);
 
-unsigned long spurious_count = 0;
+atomic_t irq_err_count;
 
 static inline void mask_irq(unsigned int irq_nr)
 {
-    unsigned int dummy;
+	unsigned int dummy;
 
-    if (dec_interrupt[irq_nr].iemask) {		/* This is an ASIC interrupt    */
-	*imr &= ~dec_interrupt[irq_nr].iemask;
-	dummy = *imr;
-	dummy = *imr;
-    } else			/* This is a cpu interrupt        */
-	change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) & ~dec_interrupt[irq_nr].cpu_mask);
+	if (dec_interrupt[irq_nr].iemask) {	/* This is an ASIC interrupt    */
+		*imr &= ~dec_interrupt[irq_nr].iemask;
+		dummy = *imr;
+		dummy = *imr;
+	} else			/* This is a cpu interrupt        */
+		change_cp0_status(ST0_IM,
+				  read_32bit_cp0_register(CP0_STATUS) &
+				  ~dec_interrupt[irq_nr].cpu_mask);
 }
 
 static inline void unmask_irq(unsigned int irq_nr)
 {
-    unsigned int dummy;
+	unsigned int dummy;
 
-    if (dec_interrupt[irq_nr].iemask) {		/* This is an ASIC interrupt    */
-	*imr |= dec_interrupt[irq_nr].iemask;
-	dummy = *imr;
-	dummy = *imr;
-    }
-    change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) | dec_interrupt[irq_nr].cpu_mask);
+	if (dec_interrupt[irq_nr].iemask) {	/* This is an ASIC interrupt    */
+		*imr |= dec_interrupt[irq_nr].iemask;
+		dummy = *imr;
+		dummy = *imr;
+	}
+	change_cp0_status(ST0_IM,
+			  read_32bit_cp0_register(CP0_STATUS) |
+			  dec_interrupt[irq_nr].cpu_mask);
 }
 
 void disable_irq(unsigned int irq_nr)
 {
-    unsigned long flags;
+	unsigned long flags;
 
-    save_and_cli(flags);
-    mask_irq(irq_nr);
-    restore_flags(flags);
+	save_and_cli(flags);
+	mask_irq(irq_nr);
+	restore_flags(flags);
 }
 
 void enable_irq(unsigned int irq_nr)
 {
-    unsigned long flags;
+	unsigned long flags;
 
-    save_and_cli(flags);
-    unmask_irq(irq_nr);
-    restore_flags(flags);
+	save_and_cli(flags);
+	unmask_irq(irq_nr);
+	restore_flags(flags);
 }
 
 /*
@@ -84,35 +87,35 @@
  */
 extern void interrupt(void);
 
-static struct irqaction *irq_action[32] =
-{
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+static struct irqaction *irq_action[32] = {
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
 };
 
 int get_irq_list(char *buf)
 {
-    int i, len = 0;
-    struct irqaction *action;
+	int i, len = 0;
+	struct irqaction *action;
 
-    for (i = 0; i < 32; i++) {
-	action = irq_action[i];
-	if (!action)
-	    continue;
-	len += sprintf(buf + len, "%2d: %8d %c %s",
-		       i, kstat.irqs[0][i],
-		       (action->flags & SA_INTERRUPT) ? '+' : ' ',
-		       action->name);
-	for (action = action->next; action; action = action->next) {
-	    len += sprintf(buf + len, ",%s %s",
-			   (action->flags & SA_INTERRUPT) ? " +" : "",
-			   action->name);
+	for (i = 0; i < 32; i++) {
+		action = irq_action[i];
+		if (!action)
+			continue;
+		len += sprintf(buf + len, "%2d: %8d %c %s",
+			       i, kstat.irqs[0][i],
+			       (action->flags & SA_INTERRUPT) ? '+' : ' ',
+			       action->name);
+		for (action = action->next; action; action = action->next) {
+			len += sprintf(buf + len, ",%s %s",
+				       (action->
+					flags & SA_INTERRUPT) ? " +" : "",
+				       action->name);
+		}
+		len += sprintf(buf + len, "\n");
 	}
-	len += sprintf(buf + len, "\n");
-    }
-    return len;
+	return len;
 }
 
 /*
@@ -124,33 +127,34 @@
  */
 asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
 {
-    struct irqaction *action;
-    int do_random, cpu;
+	struct irqaction *action;
+	int do_random, cpu;
 
-    cpu = smp_processor_id();
-    irq_enter(cpu, irq);
-    kstat.irqs[cpu][irq]++;
-
-    mask_irq(irq);
-    action = *(irq + irq_action);
-    if (action) {
-	if (!(action->flags & SA_INTERRUPT))
-	    __sti();
+	cpu = smp_processor_id();
+	irq_enter(cpu, irq);
+	kstat.irqs[cpu][irq]++;
+
+	mask_irq(irq);
 	action = *(irq + irq_action);
-	do_random = 0;
-	do {
-	    do_random |= action->flags;
-	    action->handler(irq, action->dev_id, regs);
-	    action = action->next;
-	} while (action);
-	if (do_random & SA_SAMPLE_RANDOM)
-	    add_interrupt_randomness(irq);
-	__cli();
-	unmask_irq(irq);
-    }
-    irq_exit(cpu, irq);
+	if (action) {
+		if (!(action->flags & SA_INTERRUPT))
+			__sti();
+		action = *(irq + irq_action);
+		do_random = 0;
+		do {
+			do_random |= action->flags;
+			action->handler(irq, action->dev_id, regs);
+			action = action->next;
+		} while (action);
+		if (do_random & SA_SAMPLE_RANDOM)
+			add_interrupt_randomness(irq);
+		__cli();
+		unmask_irq(irq);
+	}
+	irq_exit(cpu, irq);
 
-    /* unmasking and bottom half handling is done magically for us. */
+	if (softirq_pending(cpu))
+		do_softirq();
 }
 
 /*
@@ -159,139 +163,145 @@
  */
 int setup_dec_irq(int irq, struct irqaction *new)
 {
-    int shared = 0;
-    struct irqaction *old, **p;
-    unsigned long flags;
-
-    p = irq_action + irq;
-    if ((old = *p) != NULL) {
-	/* Can't share interrupts unless both agree to */
-	if (!(old->flags & new->flags & SA_SHIRQ))
-	    return -EBUSY;
-
-	/* Can't share interrupts unless both are same type */
-	if ((old->flags ^ new->flags) & SA_INTERRUPT)
-	    return -EBUSY;
-
-	/* add new interrupt at end of irq queue */
-	do {
-	    p = &old->next;
-	    old = *p;
-	} while (old);
-	shared = 1;
-    }
-    if (new->flags & SA_SAMPLE_RANDOM)
-	rand_initialize_irq(irq);
-
-    save_and_cli(flags);
-    *p = new;
-
-    if (!shared) {
-	unmask_irq(irq);
-    }
-    restore_flags(flags);
-    return 0;
+	int shared = 0;
+	struct irqaction *old, **p;
+	unsigned long flags;
+
+	p = irq_action + irq;
+	if ((old = *p) != NULL) {
+		/* Can't share interrupts unless both agree to */
+		if (!(old->flags & new->flags & SA_SHIRQ))
+			return -EBUSY;
+
+		/* Can't share interrupts unless both are same type */
+		if ((old->flags ^ new->flags) & SA_INTERRUPT)
+			return -EBUSY;
+
+		/* add new interrupt at end of irq queue */
+		do {
+			p = &old->next;
+			old = *p;
+		} while (old);
+		shared = 1;
+	}
+	if (new->flags & SA_SAMPLE_RANDOM)
+		rand_initialize_irq(irq);
+
+	save_and_cli(flags);
+	*p = new;
+
+	if (!shared) {
+		unmask_irq(irq);
+	}
+	restore_flags(flags);
+	return 0;
 }
 
 int request_irq(unsigned int irq,
 		void (*handler) (int, void *, struct pt_regs *),
-		unsigned long irqflags,
-		const char *devname,
-		void *dev_id)
-{
-    int retval;
-    struct irqaction *action;
-
-    if (irq >= 32)
-	return -EINVAL;
-    if (!handler)
-	return -EINVAL;
-
-    action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
-    if (!action)
-	return -ENOMEM;
-
-    action->handler = handler;
-    action->flags = irqflags;
-    action->mask = 0;
-    action->name = devname;
-    action->next = NULL;
-    action->dev_id = dev_id;
-
-    retval = setup_dec_irq(irq, action);
-
-    if (retval)
-	kfree(action);
-    return retval;
+		unsigned long irqflags, const char *devname, void *dev_id)
+{
+	int retval;
+	struct irqaction *action;
+
+	if (irq >= 32)
+		return -EINVAL;
+	if (!handler)
+		return -EINVAL;
+
+	action =
+	    (struct irqaction *) kmalloc(sizeof(struct irqaction),
+					 GFP_KERNEL);
+	if (!action)
+		return -ENOMEM;
+
+	action->handler = handler;
+	action->flags = irqflags;
+	action->mask = 0;
+	action->name = devname;
+	action->next = NULL;
+	action->dev_id = dev_id;
+
+	retval = setup_dec_irq(irq, action);
+
+	if (retval)
+		kfree(action);
+	return retval;
 }
 
 void free_irq(unsigned int irq, void *dev_id)
 {
-    struct irqaction *action, **p;
-    unsigned long flags;
-
-    if (irq > 39) {
-	printk("Trying to free IRQ%d\n", irq);
-	return;
-    }
-    for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) {
-	if (action->dev_id != dev_id)
-	    continue;
+	struct irqaction *action, **p;
+	unsigned long flags;
 
-	/* Found it - now free it */
-	save_and_cli(flags);
-	*p = action->next;
-	if (!irq[irq_action])
-	    mask_irq(irq);
-	restore_flags(flags);
-	kfree(action);
-	return;
-    }
-    printk("Trying to free free IRQ%d\n", irq);
+	if (irq > 39) {
+		printk("Trying to free IRQ%d\n", irq);
+		return;
+	}
+	for (p = irq + irq_action; (action = *p) != NULL;
+	     p = &action->next) {
+		if (action->dev_id != dev_id)
+			continue;
+
+		/* Found it - now free it */
+		save_and_cli(flags);
+		*p = action->next;
+		if (!irq[irq_action])
+			mask_irq(irq);
+		restore_flags(flags);
+		kfree(action);
+		return;
+	}
+	printk("Trying to free free IRQ%d\n", irq);
 }
 
 unsigned long probe_irq_on(void)
 {
-    /* TODO */
-    return 0;
+	/* TODO */
+	return 0;
 }
 
 int probe_irq_off(unsigned long irqs)
 {
-    /* TODO */
-    return 0;
+	/* TODO */
+	return 0;
+}
+
+void init_irq_proc(void)
+{
+	/* Nothing, for now.  */
 }
 
 void __init init_IRQ(void)
 {
-    switch (mips_machtype) {
-    case MACH_DS23100:
-	dec_init_kn01();
-	break;
-    case MACH_DS5100:		/*  DS5100 MIPSMATE */
-	dec_init_kn230();
-	break;
-    case MACH_DS5000_200:	/* DS5000 3max */
-	dec_init_kn02();
-	break;
-    case MACH_DS5000_1XX:	/* DS5000/100 3min */
-	dec_init_kn02ba();
-	break;
-    case MACH_DS5000_2X0:	/* DS5000/240 3max+ */
-	dec_init_kn03();
-	break;
-    case MACH_DS5000_XX:	/* Personal DS5000/2x */
-	dec_init_kn02ca();
-	break;
-    case MACH_DS5800:		/* DS5800 Isis */
-	panic("Don't know how to set this up!");
-	break;
-    case MACH_DS5400:		/* DS5400 MIPSfair */
-	panic("Don't know how to set this up!");
-	break;
-    case MACH_DS5500:		/* DS5500 MIPSfair-2 */
-	panic("Don't know how to set this up!");
-	break;
-    }
-    set_except_vector(0, decstation_handle_int);
+	switch (mips_machtype) {
+	case MACH_DS23100:
+		dec_init_kn01();
+		break;
+	case MACH_DS5100:	/*  DS5100 MIPSMATE */
+		dec_init_kn230();
+		break;
+	case MACH_DS5000_200:	/* DS5000 3max */
+		dec_init_kn02();
+		break;
+	case MACH_DS5000_1XX:	/* DS5000/100 3min */
+		dec_init_kn02ba();
+		break;
+	case MACH_DS5000_2X0:	/* DS5000/240 3max+ */
+		dec_init_kn03();
+		break;
+	case MACH_DS5000_XX:	/* Personal DS5000/2x */
+		dec_init_kn02ca();
+		break;
+	case MACH_DS5800:	/* DS5800 Isis */
+		panic("Don't know how to set this up!");
+		break;
+	case MACH_DS5400:	/* DS5400 MIPSfair */
+		panic("Don't know how to set this up!");
+		break;
+	case MACH_DS5500:	/* DS5500 MIPSfair-2 */
+		panic("Don't know how to set this up!");
+		break;
+	}
+	set_except_vector(0, decstation_handle_int);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/kn02-irq.c linux/arch/mips/dec/kn02-irq.c
--- linux.orig/arch/mips/dec/kn02-irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/dec/kn02-irq.c	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,125 @@
+/*
+ *	linux/arch/mips/dec/kn02-irq.c
+ *
+ *	DECstation 5000/200 (KN02) Control and Status Register
+ *	interrupts.
+ *
+ *	Copyright (c) 2002  Maciej W. Rozycki
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <asm/dec/kn02.h>
+
+
+/*
+ * Bits 7:0 of the Control Register are write-only -- the
+ * corresponding bits of the Status Register have a different
+ * meaning.  Hence we use a cache.  It speeds up things a bit
+ * as well.
+ *
+ * There is no default value -- it has to be initialized.
+ */
+u32 cached_kn02_csr;
+spinlock_t kn02_lock = SPIN_LOCK_UNLOCKED;
+
+
+static int kn02_irq_base;
+
+
+static inline void unmask_kn02_irq(unsigned int irq)
+{
+	volatile u32 *csr = (volatile u32 *)KN02_CSR_ADDR;
+
+	cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
+	*csr = cached_kn02_csr;
+}
+
+static inline void mask_kn02_irq(unsigned int irq)
+{
+	volatile u32 *csr = (volatile u32 *)KN02_CSR_ADDR;
+
+	cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
+	*csr = cached_kn02_csr;
+}
+
+static inline void enable_kn02_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&kn02_lock, flags);
+	unmask_kn02_irq(irq);
+	spin_unlock_irqrestore(&kn02_lock, flags);
+}
+
+static inline void disable_kn02_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&kn02_lock, flags);
+	mask_kn02_irq(irq);
+	spin_unlock_irqrestore(&kn02_lock, flags);
+}
+
+
+static unsigned int startup_kn02_irq(unsigned int irq)
+{
+	enable_kn02_irq(irq);
+	return 0;
+}
+
+#define shutdown_kn02_irq disable_kn02_irq
+
+static void ack_kn02_irq(unsigned int irq)
+{
+	spin_lock(&kn02_lock);
+	mask_kn02_irq(irq);
+	spin_unlock(&kn02_lock);
+}
+
+static void end_kn02_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		enable_kn02_irq(irq);
+}
+
+#define set_kn02_affinity NULL
+
+static struct hw_interrupt_type kn02_irq_type = {
+	"KN02-CSR",
+	startup_kn02_irq,
+	shutdown_kn02_irq,
+	enable_kn02_irq,
+	disable_kn02_irq,
+	ack_kn02_irq,
+	end_kn02_irq,
+	set_kn02_affinity,
+};
+
+
+void __init init_kn02_irqs(int base)
+{
+	volatile u32 *csr = (volatile u32 *)KN02_CSR_ADDR;
+	int i;
+
+	/* Mask interrupts and preset write-only bits. */
+	cached_kn02_csr = (*csr & ~0xff0000) | 0xff;
+	*csr = cached_kn02_csr;
+
+	for (i = base; i < base + KN02_IRQ_LINES; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = 0;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &kn02_irq_type;
+	}
+
+	kn02_irq_base = base;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/prom/Makefile linux/arch/mips/dec/prom/Makefile
--- linux.orig/arch/mips/dec/prom/Makefile	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/dec/prom/Makefile	2002-08-01 06:42:40.000000000 +0000
@@ -1,4 +1,4 @@
-# $Id: Makefile,v 1.1 1999/01/17 03:49:44 ralf Exp $
+#
 # Makefile for the DECstation prom monitor library routines
 # under Linux.
 #
@@ -8,22 +8,10 @@
 #
 # Note 2! The CFLAGS definitions are now in the main makefile...
 
-.S.s:
-	$(CPP) $(CFLAGS) $< -o $*.s
-.S.o:
-	$(CC) $(CFLAGS) -c $< -o $*.o
-
-OBJS  = init.o memory.o cmdline.o identify.o locore.o
-
-all: 	rexlib.a
-
-rexlib.a: $(OBJS)
-	$(AR) rcs rexlib.a $(OBJS)
-	sync
+USE_STANDARD_AS_RULE := true
 
-locore.o: locore.S
+L_TARGET  = rexlib.a
 
-dep:
-	$(CPP) $(CPPFLAGS) -M *.c > .depend
+obj-y +=  init.o memory.o cmdline.o identify.o locore.o
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/prom/cmdline.c linux/arch/mips/dec/prom/cmdline.c
--- linux.orig/arch/mips/dec/prom/cmdline.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/prom/cmdline.c	2002-08-01 06:42:36.000000000 +0000
@@ -17,7 +17,7 @@
 extern int (*prom_printf)(char *, ...);
 #endif
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
 
 void __init prom_init_cmdline(int argc, char **argv, unsigned long magic)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/prom/identify.c linux/arch/mips/dec/prom/identify.c
--- linux.orig/arch/mips/dec/prom/identify.c	2000-02-28 15:18:20.000000000 +0000
+++ linux/arch/mips/dec/prom/identify.c	2002-08-01 06:42:40.000000000 +0000
@@ -2,8 +2,6 @@
  * identify.c: machine identification code.
  *
  * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
- *
- * $Id: identify.c,v 1.2 1999/10/09 00:00:58 ralf Exp $
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -21,6 +19,26 @@
 extern unsigned long mips_machgroup;
 extern unsigned long mips_machtype;
 
+extern unsigned long mips_machtype;
+const char *get_system_type(void)
+{ 
+	static char system[32];
+	int called = 0;
+	const char *dec_system_strings[] = { "unknown", "DECstation 2100/3100",
+        	"DECstation 5100", "DECstation 5000/200", "DECstation 5000/1xx",
+		"Personal DECstation 5000/xx", "DECstation 5000/2x0",
+		"DECstation 5400", "DECstation 5500", "DECstation 5800"
+	};
+
+	if (called == 0) {
+		called = 1;
+		strcpy(system, "Digital ");
+		strcat(system, dec_system_strings[mips_machtype]);
+	}
+
+	return system;
+}
+
 void __init prom_identify_arch (unsigned int magic)
 {
 	unsigned char dec_cpunum, dec_firmrev, dec_etc;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/prom/memory.c linux/arch/mips/dec/prom/memory.c
--- linux.orig/arch/mips/dec/prom/memory.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/prom/memory.c	2002-08-01 06:42:27.000000000 +0000
@@ -3,8 +3,6 @@
  *
  * Copyright (C) 1998 Harald Koerfgen, Frieder Streffer and Paul M. Antoine
  * Copyright (C) 2000 Maciej W. Rozycki
- *
- * $Id: memory.c,v 1.3 1999/10/09 00:00:58 ralf Exp $
  */
 #include <linux/init.h>
 #include <linux/config.h>
@@ -118,7 +116,7 @@
 	 * the first page reserved for the exception handlers.
 	 */
 
-#ifdef CONFIG_DECLANCE
+#if defined(CONFIG_DECLANCE) || defined(CONFIG_DECLANCE_MODULE)
 	/*
 	 * Leave 128 KB reserved for Lance memory for
 	 * IOASIC DECstations.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/promcon.c linux/arch/mips/dec/promcon.c
--- linux.orig/arch/mips/dec/promcon.c	2000-10-12 21:20:48.000000000 +0000
+++ linux/arch/mips/dec/promcon.c	2002-08-01 06:42:45.000000000 +0000
@@ -30,11 +30,6 @@
     }
 }
 
-static int prom_console_wait_key(struct console *co)
-{
-    return prom_getchar();
-}
-
 static int __init prom_console_setup(struct console *co, char *options)
 {
     return 0;
@@ -50,7 +45,6 @@
     name:	"ttyS",
     write:	prom_console_write,
     device:	prom_console_device,
-    wait_key:	prom_console_wait_key,
     setup:	prom_console_setup,
     flags:	CON_PRINTBUFFER,
     index:	-1,
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/reset.c linux/arch/mips/dec/reset.c
--- linux.orig/arch/mips/dec/reset.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/reset.c	2002-08-01 06:42:36.000000000 +0000
@@ -1,8 +1,5 @@
 /*
- *  $Id: $
- *
- *  Reset a DECstation machine.
- *
+ * Reset a DECstation machine.
  */
 
 void (*back_to_prom)(void) = (void (*)(void))0xBFC00000;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/setup.c linux/arch/mips/dec/setup.c
--- linux.orig/arch/mips/dec/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/setup.c	2002-08-01 06:42:40.000000000 +0000
@@ -6,478 +6,758 @@
  * for more details.
  *
  * Copyright (C) 1998 Harald Koerfgen
- * Copyright (C) 2000 Maciej W. Rozycki
+ * Copyright (C) 2000, 2001, 2002  Maciej W. Rozycki
  */
+#include <linux/config.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/mc146818rtc.h>
 #include <linux/param.h>
 #include <linux/console.h>
-#include <asm/mipsregs.h>
-#include <asm/bootinfo.h>
 #include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
 #include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
 #include <asm/reboot.h>
+#include <asm/traps.h>
 
 #include <asm/dec/interrupts.h>
 #include <asm/dec/kn01.h>
 #include <asm/dec/kn02.h>
-#include <asm/dec/kn02xa.h>
+#include <asm/dec/kn02ba.h>
+#include <asm/dec/kn02ca.h>
 #include <asm/dec/kn03.h>
+#include <asm/dec/kn230.h>
 #include <asm/dec/ioasic.h>
 #include <asm/dec/ioasic_addrs.h>
 #include <asm/dec/ioasic_ints.h>
 
 
-char *dec_rtc_base = (void *) KN01_RTC_BASE;	/* Assume DS2100/3100 initially */
+extern void dec_machine_restart(char *command);
+extern void dec_machine_halt(void);
+extern void dec_machine_power_off(void);
+extern void dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
+
+extern asmlinkage void decstation_handle_int(void);
 
-volatile unsigned int *ioasic_base;
 
-decint_t dec_interrupt[NR_INTS];
+char *dec_rtc_base = (void *) KN01_RTC_BASE; /* Assume DS2100/3100 initially */
+
+volatile u32 *ioasic_base;
 
 /*
- * Information regarding the IRQ Controller
+ * IRQ routing and priority tables.  Priorites are set as follows:
+ *
+ * 		KN01	KN230	KN02	KN02-BA	KN02-CA	KN03
+ *
+ * MEMORY	CPU	CPU	CPU	ASIC	CPU	CPU
+ * RTC		CPU	CPU	CPU	ASIC	CPU	CPU
+ * DMA		-	-	-	ASIC	ASIC	ASIC
+ * SERIAL0	CPU	CPU	CSR	ASIC	ASIC	ASIC
+ * SERIAL1	-	-	-	ASIC	-	ASIC
+ * SCSI		CPU	CPU	CSR	ASIC	ASIC	ASIC
+ * ETHERNET	CPU	*	CSR	ASIC	ASIC	ASIC
+ * other	-	-	-	ASIC	-	-
+ * TC2		-	-	CSR	CPU	ASIC	ASIC
+ * TC1		-	-	CSR	CPU	ASIC	ASIC
+ * TC0		-	-	CSR	CPU	ASIC	ASIC
+ * other	-	CPU	-	CPU	ASIC	ASIC
+ * other	-	-	-	-	CPU	CPU
+ *
+ * * -- shared with SCSI
  */
+ 
+int dec_interrupt[DEC_NR_INTS] = {
+	[0 ... DEC_NR_INTS - 1] = -1
+};
+int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
+	{ { i: ~0 }, { p: dec_intr_unimplemented } },
+};
+int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
+	{ { i: ~0 }, { p: asic_intr_unimplemented } },
+};
+int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
 
-volatile unsigned int *isr = 0L;	/* address of the interrupt status register     */
-volatile unsigned int *imr = 0L;	/* address of the interrupt mask register       */
+static struct irqaction ioirq = {NULL, 0, 0, "cascade", NULL, NULL};
+static struct irqaction fpuirq = {NULL, 0, 0, "fpu", NULL, NULL};
+
+static struct irqaction haltirq = {dec_intr_halt, 0, 0, "halt", NULL, NULL};
 
-extern void dec_machine_restart(char *command);
-extern void dec_machine_halt(void);
-extern void dec_machine_power_off(void);
-extern void dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
 
 extern void wbflush_setup(void);
 
 extern struct rtc_ops dec_rtc_ops;
 
-extern int setup_dec_irq(int, struct irqaction *);
-
 void (*board_time_init) (struct irqaction * irq);
 
-static struct irqaction irq10 = {dec_intr_halt, 0, 0, "halt", NULL, NULL};
 
 /*
  * enable the periodic interrupts
  */
 static void __init dec_time_init(struct irqaction *irq)
 {
-    /*
-     * Here we go, enable periodic rtc interrupts.
-     */
+	/*
+	* Here we go, enable periodic rtc interrupts.
+	*/
 
 #ifndef LOG_2_HZ
 #  define LOG_2_HZ 7
 #endif
 
-    CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
-    CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
-    setup_dec_irq(CLOCK, irq);
+	CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
+	CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
+	setup_irq(dec_interrupt[DEC_IRQ_RTC], irq);
 }
 
+
 /*
- * Enable the halt interrupt.
+ * Bus error (DBE/IBE exceptions and memory interrupts) handling
+ * setup.  Nothing for now.
  */
-static void __init dec_halt_init(struct irqaction *irq)
+void __init bus_error_init(void)
 {
-    setup_dec_irq(HALT, irq);
 }
 
+
 void __init decstation_setup(void)
 {
-    board_time_init = dec_time_init;
+	board_time_init = dec_time_init;
 
-    wbflush_setup();
+	wbflush_setup();
 
-    _machine_restart = dec_machine_restart;
-    _machine_halt = dec_machine_halt;
-    _machine_power_off = dec_machine_power_off;
+	_machine_restart = dec_machine_restart;
+	_machine_halt = dec_machine_halt;
+	_machine_power_off = dec_machine_power_off;
 
 #ifdef CONFIG_FB
-    conswitchp = &dummy_con;
+	conswitchp = &dummy_con;
 #endif
 
-    rtc_ops = &dec_rtc_ops;
+	rtc_ops = &dec_rtc_ops;
 }
 
+
 /*
- * Machine-specific initialisation for kn01, aka Pmax, aka DS2100, DS3100,
- * and possibly also the DS5100.
+ * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
+ * or DS3100 (aka Pmax).
  */
+static int kn01_interrupt[DEC_NR_INTS] __initdata = {
+	[DEC_IRQ_CASCADE]	= -1,
+	[DEC_IRQ_AB_RECV]	= -1,
+	[DEC_IRQ_AB_XMIT]	= -1,
+	[DEC_IRQ_DZ11]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
+	[DEC_IRQ_ASC]		= -1,
+	[DEC_IRQ_FLOPPY]	= -1,
+	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
+	[DEC_IRQ_HALT]		= -1,
+	[DEC_IRQ_ISDN]		= -1,
+	[DEC_IRQ_LANCE]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
+	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN01_CPU_INR_MEMORY),
+	[DEC_IRQ_PSU]		= -1,
+	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
+	[DEC_IRQ_SCC0]		= -1,
+	[DEC_IRQ_SCC1]		= -1,
+	[DEC_IRQ_SII]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
+	[DEC_IRQ_TC0]		= -1,
+	[DEC_IRQ_TC1]		= -1,
+	[DEC_IRQ_TC2]		= -1,
+	[DEC_IRQ_TIMER]		= -1,
+	[DEC_IRQ_VIDEO]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
+	[DEC_IRQ_ASC_MERR]	= -1,
+	[DEC_IRQ_ASC_ERR]	= -1,
+	[DEC_IRQ_ASC_DMA]	= -1,
+	[DEC_IRQ_FLOPPY_ERR]	= -1,
+	[DEC_IRQ_ISDN_ERR]	= -1,
+	[DEC_IRQ_ISDN_RXDMA]	= -1,
+	[DEC_IRQ_ISDN_TXDMA]	= -1,
+	[DEC_IRQ_LANCE_MERR]	= -1,
+	[DEC_IRQ_SCC0A_RXERR]	= -1,
+	[DEC_IRQ_SCC0A_RXDMA]	= -1,
+	[DEC_IRQ_SCC0A_TXERR]	= -1,
+	[DEC_IRQ_SCC0A_TXDMA]	= -1,
+	[DEC_IRQ_SCC0B_RXERR]	= -1,
+	[DEC_IRQ_SCC0B_RXDMA]	= -1,
+	[DEC_IRQ_SCC0B_TXERR]	= -1,
+	[DEC_IRQ_SCC0B_TXDMA]	= -1,
+	[DEC_IRQ_SCC1A_RXERR]	= -1,
+	[DEC_IRQ_SCC1A_RXDMA]	= -1,
+	[DEC_IRQ_SCC1A_TXERR]	= -1,
+	[DEC_IRQ_SCC1A_TXDMA]	= -1,
+};
+
+static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
+	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_MEMORY) },
+		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_MEMORY) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
+		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
+		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
+		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
+		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
+	{ { i: DEC_CPU_IRQ_ALL },
+		{ p: cpu_all_int } },
+};
+
 void __init dec_init_kn01(void)
 {
-    /*
-     * Setup some memory addresses.
-     */
-    dec_rtc_base = (char *) KN01_RTC_BASE;
-
-    /*
-     * Setup interrupt structure
-     */
-    dec_interrupt[CLOCK].cpu_mask = IE_IRQ3;
-    dec_interrupt[CLOCK].iemask = 0;
-    cpu_mask_tbl[0] = IE_IRQ3;
-    cpu_irq_nr[0] = CLOCK;
-
-    dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
-    dec_interrupt[SCSI_INT].iemask = 0;
-    cpu_mask_tbl[1] = IE_IRQ0;
-    cpu_irq_nr[1] = SCSI_INT;
-
-    dec_interrupt[ETHER].cpu_mask = IE_IRQ1;
-    dec_interrupt[ETHER].iemask = 0;
-    cpu_mask_tbl[2] = IE_IRQ1;
-    cpu_irq_nr[2] = ETHER;
-
-    dec_interrupt[SERIAL].cpu_mask = IE_IRQ2;
-    dec_interrupt[SERIAL].iemask = 0;
-    cpu_mask_tbl[3] = IE_IRQ2;
-    cpu_irq_nr[3] = SERIAL;
-
-    dec_interrupt[MEMORY].cpu_mask = IE_IRQ4;
-    dec_interrupt[MEMORY].iemask = 0;
-    cpu_mask_tbl[4] = IE_IRQ4;
-    cpu_irq_nr[4] = MEMORY;
-
-    dec_interrupt[FPU].cpu_mask = IE_IRQ5;
-    dec_interrupt[FPU].iemask = 0;
-    cpu_mask_tbl[5] = IE_IRQ5;
-    cpu_irq_nr[5] = FPU;
+	/* Setup some memory addresses. */
+	dec_rtc_base = (char *) KN01_RTC_BASE;
+
+	/* IRQ routing. */
+	memcpy(&dec_interrupt, &kn01_interrupt,
+		sizeof(kn01_interrupt));
+
+	/* CPU IRQ priorities. */
+	memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
+		sizeof(kn01_cpu_mask_nr_tbl));
+
+	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+
 }				/* dec_init_kn01 */
 
+
 /*
- * Machine-specific initialisation for kn230, aka MIPSmate, aka DS5100
- *
- * There are a lot of experiments to do, this is definitely incomplete.
+ * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
  */
+static int kn230_interrupt[DEC_NR_INTS] __initdata = {
+	[DEC_IRQ_CASCADE]	= -1,
+	[DEC_IRQ_AB_RECV]	= -1,
+	[DEC_IRQ_AB_XMIT]	= -1,
+	[DEC_IRQ_DZ11]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
+	[DEC_IRQ_ASC]		= -1,
+	[DEC_IRQ_FLOPPY]	= -1,
+	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
+	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
+	[DEC_IRQ_ISDN]		= -1,
+	[DEC_IRQ_LANCE]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
+	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN230_CPU_INR_MEMORY),
+	[DEC_IRQ_PSU]		= -1,
+	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
+	[DEC_IRQ_SCC0]		= -1,
+	[DEC_IRQ_SCC1]		= -1,
+	[DEC_IRQ_SII]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
+	[DEC_IRQ_TC0]		= -1,
+	[DEC_IRQ_TC1]		= -1,
+	[DEC_IRQ_TC2]		= -1,
+	[DEC_IRQ_TIMER]		= -1,
+	[DEC_IRQ_VIDEO]		= -1,
+	[DEC_IRQ_ASC_MERR]	= -1,
+	[DEC_IRQ_ASC_ERR]	= -1,
+	[DEC_IRQ_ASC_DMA]	= -1,
+	[DEC_IRQ_FLOPPY_ERR]	= -1,
+	[DEC_IRQ_ISDN_ERR]	= -1,
+	[DEC_IRQ_ISDN_RXDMA]	= -1,
+	[DEC_IRQ_ISDN_TXDMA]	= -1,
+	[DEC_IRQ_LANCE_MERR]	= -1,
+	[DEC_IRQ_SCC0A_RXERR]	= -1,
+	[DEC_IRQ_SCC0A_RXDMA]	= -1,
+	[DEC_IRQ_SCC0A_TXERR]	= -1,
+	[DEC_IRQ_SCC0A_TXDMA]	= -1,
+	[DEC_IRQ_SCC0B_RXERR]	= -1,
+	[DEC_IRQ_SCC0B_RXDMA]	= -1,
+	[DEC_IRQ_SCC0B_TXERR]	= -1,
+	[DEC_IRQ_SCC0B_TXDMA]	= -1,
+	[DEC_IRQ_SCC1A_RXERR]	= -1,
+	[DEC_IRQ_SCC1A_RXDMA]	= -1,
+	[DEC_IRQ_SCC1A_TXERR]	= -1,
+	[DEC_IRQ_SCC1A_TXDMA]	= -1,
+};
+
+static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
+	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_MEMORY) },
+		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_MEMORY) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
+		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
+		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
+		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
+	{ { i: DEC_CPU_IRQ_ALL },
+		{ p: cpu_all_int } },
+};
+
 void __init dec_init_kn230(void)
 {
-    /*
-     * Setup some memory addresses.
-     */
-    dec_rtc_base = (char *) KN01_RTC_BASE;
-
-    /*
-     * Setup interrupt structure
-     */
-    dec_interrupt[CLOCK].cpu_mask = IE_IRQ2;
-    dec_interrupt[CLOCK].iemask = 0;
-    cpu_mask_tbl[0] = IE_IRQ2;
-    cpu_irq_nr[0] = CLOCK;
-
-    dec_interrupt[FPU].cpu_mask = IE_IRQ5;
-    dec_interrupt[FPU].iemask = 0;
-    cpu_mask_tbl[5] = IE_IRQ5;
-    cpu_irq_nr[5] = FPU;
+	/* Setup some memory addresses. */
+	dec_rtc_base = (char *) KN01_RTC_BASE;
+
+	/* IRQ routing. */
+	memcpy(&dec_interrupt, &kn230_interrupt,
+		sizeof(kn230_interrupt));
+
+	/* CPU IRQ priorities. */
+	memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
+		sizeof(kn230_cpu_mask_nr_tbl));
+
+	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+
 }				/* dec_init_kn230 */
 
+
 /*
- * Machine-specific initialisation for kn02, aka 3max, aka DS5000/2xx.
+ * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
  */
+static int kn02_interrupt[DEC_NR_INTS] __initdata = {
+	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
+	[DEC_IRQ_AB_RECV]	= -1,
+	[DEC_IRQ_AB_XMIT]	= -1,
+	[DEC_IRQ_DZ11]		= KN02_IRQ_NR(KN02_CSR_INR_DZ11),
+	[DEC_IRQ_ASC]		= KN02_IRQ_NR(KN02_CSR_INR_ASC),
+	[DEC_IRQ_FLOPPY]	= -1,
+	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
+	[DEC_IRQ_HALT]		= -1,
+	[DEC_IRQ_ISDN]		= -1,
+	[DEC_IRQ_LANCE]		= KN02_IRQ_NR(KN02_CSR_INR_LANCE),
+	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN02_CPU_INR_MEMORY),
+	[DEC_IRQ_PSU]		= -1,
+	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
+	[DEC_IRQ_SCC0]		= -1,
+	[DEC_IRQ_SCC1]		= -1,
+	[DEC_IRQ_SII]		= -1,
+	[DEC_IRQ_TC0]		= KN02_IRQ_NR(KN02_CSR_INR_TC0),
+	[DEC_IRQ_TC1]		= KN02_IRQ_NR(KN02_CSR_INR_TC1),
+	[DEC_IRQ_TC2]		= KN02_IRQ_NR(KN02_CSR_INR_TC2),
+	[DEC_IRQ_TIMER]		= -1,
+	[DEC_IRQ_VIDEO]		= -1,
+	[DEC_IRQ_ASC_MERR]	= -1,
+	[DEC_IRQ_ASC_ERR]	= -1,
+	[DEC_IRQ_ASC_DMA]	= -1,
+	[DEC_IRQ_FLOPPY_ERR]	= -1,
+	[DEC_IRQ_ISDN_ERR]	= -1,
+	[DEC_IRQ_ISDN_RXDMA]	= -1,
+	[DEC_IRQ_ISDN_TXDMA]	= -1,
+	[DEC_IRQ_LANCE_MERR]	= -1,
+	[DEC_IRQ_SCC0A_RXERR]	= -1,
+	[DEC_IRQ_SCC0A_RXDMA]	= -1,
+	[DEC_IRQ_SCC0A_TXERR]	= -1,
+	[DEC_IRQ_SCC0A_TXDMA]	= -1,
+	[DEC_IRQ_SCC0B_RXERR]	= -1,
+	[DEC_IRQ_SCC0B_RXDMA]	= -1,
+	[DEC_IRQ_SCC0B_TXERR]	= -1,
+	[DEC_IRQ_SCC0B_TXDMA]	= -1,
+	[DEC_IRQ_SCC1A_RXERR]	= -1,
+	[DEC_IRQ_SCC1A_RXDMA]	= -1,
+	[DEC_IRQ_SCC1A_TXERR]	= -1,
+	[DEC_IRQ_SCC1A_TXDMA]	= -1,
+};
+
+static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
+	{ { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_MEMORY) },
+		{ i: DEC_CPU_IRQ_NR(KN02_CPU_INR_MEMORY) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
+		{ i: DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
+		{ p: kn02_io_int } },
+	{ { i: DEC_CPU_IRQ_ALL },
+		{ p: cpu_all_int } },
+};
+
+static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
+	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
+		{ i: KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
+	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
+		{ i: KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
+	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
+		{ i: KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
+	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
+		{ i: KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
+	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
+		{ i: KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
+	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
+		{ i: KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
+	{ { i: KN02_IRQ_ALL },
+		{ p: kn02_all_int } },
+};
+
 void __init dec_init_kn02(void)
 {
-    /*
-     * Setup some memory addresses. FIXME: probably incomplete!
-     */
-    dec_rtc_base = (char *) KN02_RTC_BASE;
-    isr = (void *) KN02_CSR_ADDR;
-    imr = (void *) KN02_CSR_ADDR;
-
-    /*
-     * Setup IOASIC interrupt
-     */
-    cpu_ivec_tbl[1] = kn02_io_int;
-    cpu_mask_tbl[1] = IE_IRQ0;
-    cpu_irq_nr[1] = -1;
-    *imr = *imr & 0xff00ff00;
-
-    /*
-     * Setup interrupt structure
-     */
-    dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
-    dec_interrupt[CLOCK].iemask = 0;
-    cpu_mask_tbl[0] = IE_IRQ1;
-    cpu_irq_nr[0] = CLOCK;
-
-    dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
-    dec_interrupt[SCSI_INT].iemask = KN02_SLOT5;
-    asic_mask_tbl[0] = KN02_SLOT5;
-    asic_irq_nr[0] = SCSI_INT;
-
-    dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
-    dec_interrupt[ETHER].iemask = KN02_SLOT6;
-    asic_mask_tbl[1] = KN02_SLOT6;
-    asic_irq_nr[1] = ETHER;
-
-    dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
-    dec_interrupt[SERIAL].iemask = KN02_SLOT7;
-    asic_mask_tbl[2] = KN02_SLOT7;
-    asic_irq_nr[2] = SERIAL;
-
-    dec_interrupt[TC0].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC0].iemask = KN02_SLOT0;
-    asic_mask_tbl[3] = KN02_SLOT0;
-    asic_irq_nr[3] = TC0;
-
-    dec_interrupt[TC1].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC1].iemask = KN02_SLOT1;
-    asic_mask_tbl[4] = KN02_SLOT1;
-    asic_irq_nr[4] = TC1;
-
-    dec_interrupt[TC2].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC2].iemask = KN02_SLOT2;
-    asic_mask_tbl[5] = KN02_SLOT2;
-    asic_irq_nr[5] = TC2;
-
-    dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
-    dec_interrupt[MEMORY].iemask = 0;
-    cpu_mask_tbl[2] = IE_IRQ3;
-    cpu_irq_nr[2] = MEMORY;
-
-    dec_interrupt[FPU].cpu_mask = IE_IRQ5;
-    dec_interrupt[FPU].iemask = 0;
-    cpu_mask_tbl[3] = IE_IRQ5;
-    cpu_irq_nr[3] = FPU;
+	/* Setup some memory addresses. */
+	dec_rtc_base = (char *) KN02_RTC_BASE;
+
+	/* IRQ routing. */
+	memcpy(&dec_interrupt, &kn02_interrupt,
+		sizeof(kn02_interrupt));
+
+	/* CPU IRQ priorities. */
+	memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
+		sizeof(kn02_cpu_mask_nr_tbl));
+
+	/* KN02 CSR IRQ priorities. */
+	memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
+		sizeof(kn02_asic_mask_nr_tbl));
+
+	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+	init_kn02_irqs(KN02_IRQ_BASE);
 
 }				/* dec_init_kn02 */
 
+
 /*
- * Machine-specific initialisation for kn02ba, aka 3min, aka DS5000/1xx.
+ * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
+ * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
+ * DS5000/150, aka 4min.
  */
+static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
+	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
+	[DEC_IRQ_AB_RECV]	= -1,
+	[DEC_IRQ_AB_XMIT]	= -1,
+	[DEC_IRQ_DZ11]		= -1,
+	[DEC_IRQ_ASC]		= IO_IRQ_NR(KN02BA_IO_INR_ASC),
+	[DEC_IRQ_FLOPPY]	= -1,
+	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
+	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
+	[DEC_IRQ_ISDN]		= -1,
+	[DEC_IRQ_LANCE]		= IO_IRQ_NR(KN02BA_IO_INR_LANCE),
+	[DEC_IRQ_MEMORY]	= IO_IRQ_NR(KN02BA_IO_INR_MEMORY),
+	[DEC_IRQ_PSU]		= IO_IRQ_NR(KN02BA_IO_INR_PSU),
+	[DEC_IRQ_RTC]		= IO_IRQ_NR(KN02BA_IO_INR_RTC),
+	[DEC_IRQ_SCC0]		= IO_IRQ_NR(KN02BA_IO_INR_SCC0),
+	[DEC_IRQ_SCC1]		= IO_IRQ_NR(KN02BA_IO_INR_SCC1),
+	[DEC_IRQ_SII]		= -1,
+	[DEC_IRQ_TC0]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
+	[DEC_IRQ_TC1]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
+	[DEC_IRQ_TC2]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
+	[DEC_IRQ_TIMER]		= -1,
+	[DEC_IRQ_VIDEO]		= -1,
+	[DEC_IRQ_ASC_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
+	[DEC_IRQ_ASC_ERR]	= IO_IRQ_NR(IO_INR_ASC_ERR),
+	[DEC_IRQ_ASC_DMA]	= IO_IRQ_NR(IO_INR_ASC_DMA),
+	[DEC_IRQ_FLOPPY_ERR]	= -1,
+	[DEC_IRQ_ISDN_ERR]	= -1,
+	[DEC_IRQ_ISDN_RXDMA]	= -1,
+	[DEC_IRQ_ISDN_TXDMA]	= -1,
+	[DEC_IRQ_LANCE_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
+	[DEC_IRQ_SCC0A_RXERR]	= IO_IRQ_NR(IO_INR_SCC0A_RXERR),
+	[DEC_IRQ_SCC0A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
+	[DEC_IRQ_SCC0A_TXERR]	= IO_IRQ_NR(IO_INR_SCC0A_TXERR),
+	[DEC_IRQ_SCC0A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
+	[DEC_IRQ_SCC0B_RXERR]	= -1,
+	[DEC_IRQ_SCC0B_RXDMA]	= -1,
+	[DEC_IRQ_SCC0B_TXERR]	= -1,
+	[DEC_IRQ_SCC0B_TXDMA]	= -1,
+	[DEC_IRQ_SCC1A_RXERR]	= IO_IRQ_NR(IO_INR_SCC1A_RXERR),
+	[DEC_IRQ_SCC1A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
+	[DEC_IRQ_SCC1A_TXERR]	= IO_IRQ_NR(IO_INR_SCC1A_TXERR),
+	[DEC_IRQ_SCC1A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
+};
+
+static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
+	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
+		{ p: kn02xa_io_int } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
+		{ i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
+		{ i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
+		{ i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
+	{ { i: DEC_CPU_IRQ_ALL },
+		{ p: cpu_all_int } },
+};
+
+static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
+	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_MEMORY) },
+		{ i: IO_IRQ_NR(KN02BA_IO_INR_MEMORY) } },
+	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
+		{ i: IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
+	{ { i: IO_IRQ_DMA },
+		{ p: asic_dma_int } },
+	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
+		{ i: IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
+	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
+		{ i: IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
+	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
+		{ i: IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
+	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
+		{ i: IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
+	{ { i: IO_IRQ_ALL },
+		{ p: asic_all_int } },
+};
+
 void __init dec_init_kn02ba(void)
 {
-    /*
-     * Setup some memory addresses.
-     */
-    ioasic_base = (void *) KN02XA_IOASIC_BASE;
-    dec_rtc_base = (char *) KN02XA_RTC_BASE;
-    isr = (void *) KN02XA_IOASIC_REG(SIR);
-    imr = (void *) KN02XA_IOASIC_REG(SIMR);
-
-    /*
-     * Setup IOASIC interrupt
-     */
-    cpu_mask_tbl[0] = IE_IRQ3;
-    cpu_irq_nr[0] = -1;
-    cpu_ivec_tbl[0] = kn02xa_io_int;
-    *imr = 0;
-
-    /*
-     * Setup interrupt structure
-     */
-    dec_interrupt[CLOCK].cpu_mask = IE_IRQ3;
-    dec_interrupt[CLOCK].iemask = KMIN_CLOCK;
-    asic_mask_tbl[0] = KMIN_CLOCK;
-    asic_irq_nr[0] = CLOCK;
-
-    dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
-    dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
-    asic_mask_tbl[1] = SCSI_DMA_INTS;
-    asic_irq_nr[1] = SCSI_DMA_INT;
-
-    dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
-    dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
-    asic_mask_tbl[2] = SCSI_CHIP;
-    asic_irq_nr[2] = SCSI_INT;
-
-    dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
-    dec_interrupt[ETHER].iemask = LANCE_INTS;
-    asic_mask_tbl[3] = LANCE_INTS;
-    asic_irq_nr[3] = ETHER;
-
-    dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
-    dec_interrupt[SERIAL].iemask = SERIAL_INTS;
-    asic_mask_tbl[4] = SERIAL_INTS;
-    asic_irq_nr[4] = SERIAL;
-
-    dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
-    dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT;
-    asic_mask_tbl[5] = KMIN_TIMEOUT;
-    asic_irq_nr[5] = MEMORY;
-
-    dec_interrupt[TC0].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC0].iemask = 0;
-    cpu_mask_tbl[1] = IE_IRQ0;
-    cpu_irq_nr[1] = TC0;
-
-    dec_interrupt[TC1].cpu_mask = IE_IRQ1;
-    dec_interrupt[TC1].iemask = 0;
-    cpu_mask_tbl[2] = IE_IRQ1;
-    cpu_irq_nr[2] = TC1;
-
-    dec_interrupt[TC2].cpu_mask = IE_IRQ2;
-    dec_interrupt[TC2].iemask = 0;
-    cpu_mask_tbl[3] = IE_IRQ2;
-    cpu_irq_nr[3] = TC2;
-
-    dec_interrupt[HALT].cpu_mask = IE_IRQ4;
-    dec_interrupt[HALT].iemask = 0;
-    cpu_mask_tbl[4] = IE_IRQ4;
-    cpu_irq_nr[4] = HALT;
-
-    dec_interrupt[FPU].cpu_mask = IE_IRQ5;
-    dec_interrupt[FPU].iemask = 0;
-    cpu_mask_tbl[5] = IE_IRQ5;
-    cpu_irq_nr[5] = FPU;
+	/* Setup some memory addresses. */
+	ioasic_base = (void *) KN02BA_IOASIC_BASE;
+	dec_rtc_base = (char *) KN02BA_RTC_BASE;
+
+	/* IRQ routing. */
+	memcpy(&dec_interrupt, &kn02ba_interrupt,
+		sizeof(kn02ba_interrupt));
+
+	/* CPU IRQ priorities. */
+	memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
+		sizeof(kn02ba_cpu_mask_nr_tbl));
+
+	/* I/O ASIC IRQ priorities. */
+	memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
+		sizeof(kn02ba_asic_mask_nr_tbl));
+
+	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+	init_ioasic_irqs(IO_IRQ_BASE);
 
-    dec_halt_init(&irq10);
 }				/* dec_init_kn02ba */
 
+
 /*
- * Machine-specific initialisation for kn02ca, aka maxine, aka DS5000/2x.
+ * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
+ * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
+ * DS5000/50, aka 4MAXine.
  */
+static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
+	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
+	[DEC_IRQ_AB_RECV]	= IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
+	[DEC_IRQ_AB_XMIT]	= IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
+	[DEC_IRQ_DZ11]		= -1,
+	[DEC_IRQ_ASC]		= IO_IRQ_NR(KN02CA_IO_INR_ASC),
+	[DEC_IRQ_FLOPPY]	= IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
+	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
+	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
+	[DEC_IRQ_ISDN]		= IO_IRQ_NR(KN02CA_IO_INR_ISDN),
+	[DEC_IRQ_LANCE]		= IO_IRQ_NR(KN02CA_IO_INR_LANCE),
+	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_MEMORY),
+	[DEC_IRQ_PSU]		= -1,
+	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
+	[DEC_IRQ_SCC0]		= IO_IRQ_NR(KN02CA_IO_INR_SCC0),
+	[DEC_IRQ_SCC1]		= -1,
+	[DEC_IRQ_SII]		= -1,
+	[DEC_IRQ_TC0]		= IO_IRQ_NR(KN02CA_IO_INR_TC0),
+	[DEC_IRQ_TC1]		= IO_IRQ_NR(KN02CA_IO_INR_TC1),
+	[DEC_IRQ_TC2]		= -1,
+	[DEC_IRQ_TIMER]		= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
+	[DEC_IRQ_VIDEO]		= IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
+	[DEC_IRQ_ASC_MERR]	= IO_IRQ_NR(IO_INR_ASC_MERR),
+	[DEC_IRQ_ASC_ERR]	= IO_IRQ_NR(IO_INR_ASC_ERR),
+	[DEC_IRQ_ASC_DMA]	= IO_IRQ_NR(IO_INR_ASC_DMA),
+	[DEC_IRQ_FLOPPY_ERR]	= IO_IRQ_NR(IO_INR_FLOPPY_ERR),
+	[DEC_IRQ_ISDN_ERR]	= IO_IRQ_NR(IO_INR_ISDN_ERR),
+	[DEC_IRQ_ISDN_RXDMA]	= IO_IRQ_NR(IO_INR_ISDN_RXDMA),
+	[DEC_IRQ_ISDN_TXDMA]	= IO_IRQ_NR(IO_INR_ISDN_TXDMA),
+	[DEC_IRQ_LANCE_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
+	[DEC_IRQ_SCC0A_RXERR]	= IO_IRQ_NR(IO_INR_SCC0A_RXERR),
+	[DEC_IRQ_SCC0A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
+	[DEC_IRQ_SCC0A_TXERR]	= IO_IRQ_NR(IO_INR_SCC0A_TXERR),
+	[DEC_IRQ_SCC0A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
+	[DEC_IRQ_SCC0B_RXERR]	= IO_IRQ_NR(IO_INR_SCC0B_RXERR),
+	[DEC_IRQ_SCC0B_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0B_RXDMA),
+	[DEC_IRQ_SCC0B_TXERR]	= IO_IRQ_NR(IO_INR_SCC0B_TXERR),
+	[DEC_IRQ_SCC0B_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0B_TXDMA),
+	[DEC_IRQ_SCC1A_RXERR]	= -1,
+	[DEC_IRQ_SCC1A_RXDMA]	= -1,
+	[DEC_IRQ_SCC1A_TXERR]	= -1,
+	[DEC_IRQ_SCC1A_TXDMA]	= -1,
+};
+
+static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
+	{ { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_MEMORY) },
+		{ i: DEC_CPU_IRQ_NR(KN02CA_CPU_INR_MEMORY) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
+		{ i: DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
+		{ p: kn02xa_io_int } },
+	{ { i: DEC_CPU_IRQ_ALL },
+		{ p: cpu_all_int } },
+};
+
+static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
+	{ { i: IO_IRQ_DMA },
+		{ p: asic_dma_int } },
+	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
+		{ i: IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
+	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
+		{ i: IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
+	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
+		{ i: IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
+	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
+		{ i: IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
+	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
+		{ i: IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
+	{ { i: IO_IRQ_ALL },
+		{ p: asic_all_int } },
+};
+
 void __init dec_init_kn02ca(void)
 {
-    /*
-     * Setup some memory addresses. FIXME: probably incomplete!
-     */
-    ioasic_base = (void *) KN02XA_IOASIC_BASE;
-    dec_rtc_base = (char *) KN02XA_RTC_BASE;
-    isr = (void *) KN02XA_IOASIC_REG(SIR);
-    imr = (void *) KN02XA_IOASIC_REG(SIMR);
-
-    /*
-     * Setup IOASIC interrupt
-     */
-    cpu_ivec_tbl[1] = kn02xa_io_int;
-    cpu_irq_nr[1] = -1;
-    cpu_mask_tbl[1] = IE_IRQ3;
-    *imr = 0;
-
-    /*
-     * Setup interrupt structure
-     */
-    dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
-    dec_interrupt[CLOCK].iemask = 0;
-    cpu_mask_tbl[0] = IE_IRQ1;
-    cpu_irq_nr[0] = CLOCK;
-
-    dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
-    dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
-    asic_mask_tbl[0] = SCSI_DMA_INTS;
-    asic_irq_nr[0] = SCSI_DMA_INT;
-
-    dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
-    dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
-    asic_mask_tbl[1] = SCSI_CHIP;
-    asic_irq_nr[1] = SCSI_INT;
-
-    dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
-    dec_interrupt[ETHER].iemask = LANCE_INTS;
-    asic_mask_tbl[2] = LANCE_INTS;
-    asic_irq_nr[2] = ETHER;
-
-    dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
-    dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS;
-    asic_mask_tbl[3] = XINE_SERIAL_INTS;
-    asic_irq_nr[3] = SERIAL;
-
-    dec_interrupt[TC0].cpu_mask = IE_IRQ3;
-    dec_interrupt[TC0].iemask = MAXINE_TC0;
-    asic_mask_tbl[4] = MAXINE_TC0;
-    asic_irq_nr[4] = TC0;
-
-    dec_interrupt[TC1].cpu_mask = IE_IRQ3;
-    dec_interrupt[TC1].iemask = MAXINE_TC1;
-    asic_mask_tbl[5] = MAXINE_TC1;
-    asic_irq_nr[5] = TC1;
-
-    dec_interrupt[MEMORY].cpu_mask = IE_IRQ2;
-    dec_interrupt[MEMORY].iemask = 0;
-    cpu_mask_tbl[2] = IE_IRQ2;
-    cpu_irq_nr[2] = MEMORY;
-
-    dec_interrupt[HALT].cpu_mask = IE_IRQ4;
-    dec_interrupt[HALT].iemask = 0;
-    cpu_mask_tbl[3] = IE_IRQ4;
-    cpu_irq_nr[3] = HALT;
-
-    dec_interrupt[FPU].cpu_mask = IE_IRQ5;
-    dec_interrupt[FPU].iemask = 0;
-    cpu_mask_tbl[4] = IE_IRQ5;
-    cpu_irq_nr[4] = FPU;
+	/* Setup some memory addresses. */
+	ioasic_base = (void *) KN02CA_IOASIC_BASE;
+	dec_rtc_base = (char *) KN02CA_RTC_BASE;
+
+	/* IRQ routing. */
+	memcpy(&dec_interrupt, &kn02ca_interrupt,
+		sizeof(kn02ca_interrupt));
+
+	/* CPU IRQ priorities. */
+	memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
+		sizeof(kn02ca_cpu_mask_nr_tbl));
+
+	/* I/O ASIC IRQ priorities. */
+	memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
+		sizeof(kn02ca_asic_mask_nr_tbl));
+
+	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+	init_ioasic_irqs(IO_IRQ_BASE);
 
-    dec_halt_init(&irq10);
 }				/* dec_init_kn02ca */
 
+
 /*
- * Machine-specific initialisation for kn03, aka 3max+, aka DS5000/240.
+ * Machine-specific initialisation for KN03, aka DS5000/240,
+ * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
+ * DS5000/260, aka 4max+ and DS5900-260.
  */
+static int kn03_interrupt[DEC_NR_INTS] __initdata = {
+	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
+	[DEC_IRQ_AB_RECV]	= -1,
+	[DEC_IRQ_AB_XMIT]	= -1,
+	[DEC_IRQ_DZ11]		= -1,
+	[DEC_IRQ_ASC]		= IO_IRQ_NR(KN03_IO_INR_ASC),
+	[DEC_IRQ_FLOPPY]	= -1,
+	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
+	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
+	[DEC_IRQ_ISDN]		= -1,
+	[DEC_IRQ_LANCE]		= IO_IRQ_NR(KN03_IO_INR_LANCE),
+	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN03_CPU_INR_MEMORY),
+	[DEC_IRQ_PSU]		= IO_IRQ_NR(KN03_IO_INR_PSU),
+	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
+	[DEC_IRQ_SCC0]		= IO_IRQ_NR(KN03_IO_INR_SCC0),
+	[DEC_IRQ_SCC1]		= IO_IRQ_NR(KN03_IO_INR_SCC1),
+	[DEC_IRQ_SII]		= -1,
+	[DEC_IRQ_TC0]		= IO_IRQ_NR(KN03_IO_INR_TC0),
+	[DEC_IRQ_TC1]		= IO_IRQ_NR(KN03_IO_INR_TC1),
+	[DEC_IRQ_TC2]		= IO_IRQ_NR(KN03_IO_INR_TC2),
+	[DEC_IRQ_TIMER]		= -1,
+	[DEC_IRQ_VIDEO]		= -1,
+	[DEC_IRQ_ASC_MERR]	= IO_IRQ_NR(IO_INR_ASC_MERR),
+	[DEC_IRQ_ASC_ERR]	= IO_IRQ_NR(IO_INR_ASC_ERR),
+	[DEC_IRQ_ASC_DMA]	= IO_IRQ_NR(IO_INR_ASC_DMA),
+	[DEC_IRQ_FLOPPY_ERR]	= -1,
+	[DEC_IRQ_ISDN_ERR]	= -1,
+	[DEC_IRQ_ISDN_RXDMA]	= -1,
+	[DEC_IRQ_ISDN_TXDMA]	= -1,
+	[DEC_IRQ_LANCE_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
+	[DEC_IRQ_SCC0A_RXERR]	= IO_IRQ_NR(IO_INR_SCC0A_RXERR),
+	[DEC_IRQ_SCC0A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
+	[DEC_IRQ_SCC0A_TXERR]	= IO_IRQ_NR(IO_INR_SCC0A_TXERR),
+	[DEC_IRQ_SCC0A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
+	[DEC_IRQ_SCC0B_RXERR]	= -1,
+	[DEC_IRQ_SCC0B_RXDMA]	= -1,
+	[DEC_IRQ_SCC0B_TXERR]	= -1,
+	[DEC_IRQ_SCC0B_TXDMA]	= -1,
+	[DEC_IRQ_SCC1A_RXERR]	= IO_IRQ_NR(IO_INR_SCC1A_RXERR),
+	[DEC_IRQ_SCC1A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
+	[DEC_IRQ_SCC1A_TXERR]	= IO_IRQ_NR(IO_INR_SCC1A_TXERR),
+	[DEC_IRQ_SCC1A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
+};
+
+static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
+	{ { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_MEMORY) },
+		{ i: DEC_CPU_IRQ_NR(KN03_CPU_INR_MEMORY) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
+		{ i: DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
+	{ { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 
+		{ p: kn03_io_int } },
+	{ { i: DEC_CPU_IRQ_ALL }, 
+		{ p: cpu_all_int } },
+};
+
+static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
+	{ { i: IO_IRQ_DMA },
+		{ p: asic_dma_int } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_SCC0) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_SCC0) } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_SCC1) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_SCC1) } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_ASC) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_ASC) } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_LANCE) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_LANCE) } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_TC2) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_TC2) } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_TC1) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_TC1) } },
+	{ { i: IO_IRQ_MASK(KN03_IO_INR_TC0) },
+		{ i: IO_IRQ_NR(KN03_IO_INR_TC0) } },
+	{ { i: IO_IRQ_ALL },
+		{ p: asic_all_int } },
+};
+
 void __init dec_init_kn03(void)
 {
-    /*
-     * Setup some memory addresses. FIXME: probably incomplete!
-     */
-    ioasic_base = (void *) KN03_IOASIC_BASE;
-    dec_rtc_base = (char *) KN03_RTC_BASE;
-    isr = (void *) KN03_IOASIC_REG(SIR);
-    imr = (void *) KN03_IOASIC_REG(SIMR);
-
-    /*
-     * Setup IOASIC interrupt
-     */
-    cpu_ivec_tbl[1] = kn03_io_int;
-    cpu_mask_tbl[1] = IE_IRQ0;
-    cpu_irq_nr[1] = -1;
-    *imr = 0;
-
-    /*
-     * Setup interrupt structure
-     */
-    dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
-    dec_interrupt[CLOCK].iemask = 0;
-    cpu_mask_tbl[0] = IE_IRQ1;
-    cpu_irq_nr[0] = CLOCK;
-
-    dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0;
-    dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
-    asic_mask_tbl[0] = SCSI_DMA_INTS;
-    asic_irq_nr[0] = SCSI_DMA_INT;
-
-    dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
-    dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
-    asic_mask_tbl[1] = SCSI_CHIP;
-    asic_irq_nr[1] = SCSI_INT;
-
-    dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
-    dec_interrupt[ETHER].iemask = LANCE_INTS;
-    asic_mask_tbl[2] = LANCE_INTS;
-    asic_irq_nr[2] = ETHER;
-
-    dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
-    dec_interrupt[SERIAL].iemask = SERIAL_INTS;
-    asic_mask_tbl[3] = SERIAL_INTS;
-    asic_irq_nr[3] = SERIAL;
-
-    dec_interrupt[TC0].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC0].iemask = KN03_TC0;
-    asic_mask_tbl[4] = KN03_TC0;
-    asic_irq_nr[4] = TC0;
-
-    dec_interrupt[TC1].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC1].iemask = KN03_TC1;
-    asic_mask_tbl[5] = KN03_TC1;
-    asic_irq_nr[5] = TC1;
-
-    dec_interrupt[TC2].cpu_mask = IE_IRQ0;
-    dec_interrupt[TC2].iemask = KN03_TC2;
-    asic_mask_tbl[6] = KN03_TC2;
-    asic_irq_nr[6] = TC2;
-
-    dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
-    dec_interrupt[MEMORY].iemask = 0;
-    cpu_mask_tbl[2] = IE_IRQ3;
-    cpu_irq_nr[2] = MEMORY;
-
-    dec_interrupt[HALT].cpu_mask = IE_IRQ4;
-    dec_interrupt[HALT].iemask = 0;
-    cpu_mask_tbl[3] = IE_IRQ4;
-    cpu_irq_nr[3] = HALT;
-
-    dec_interrupt[FPU].cpu_mask = IE_IRQ5;
-    dec_interrupt[FPU].iemask = 0;
-    cpu_mask_tbl[4] = IE_IRQ5;
-    cpu_irq_nr[4] = FPU;
+	/* Setup some memory addresses.  */
+	ioasic_base = (void *) KN03_IOASIC_BASE;
+	dec_rtc_base = (char *) KN03_RTC_BASE;
+
+	/* IRQ routing. */
+	memcpy(&dec_interrupt, &kn03_interrupt,
+		sizeof(kn03_interrupt));	
+
+	/* CPU IRQ priorities. */
+	memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
+		sizeof(kn03_cpu_mask_nr_tbl));
+
+	/* I/O ASIC IRQ priorities. */
+	memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
+		sizeof(kn03_asic_mask_nr_tbl));
+
+	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+	init_ioasic_irqs(IO_IRQ_BASE);
 
-    dec_halt_init(&irq10);
 }				/* dec_init_kn03 */
+
+
+void __init init_IRQ(void)
+{
+	switch (mips_machtype) {
+	case MACH_DS23100:	/* DS2100/DS3100 Pmin/Pmax */
+		dec_init_kn01();
+		break;
+	case MACH_DS5100:	/* DS5100 MIPSmate */
+		dec_init_kn230();
+		break;
+	case MACH_DS5000_200:	/* DS5000/200 3max */
+		dec_init_kn02();
+		break;
+	case MACH_DS5000_1XX:	/* DS5000/1xx 3min */
+		dec_init_kn02ba();
+		break;
+	case MACH_DS5000_2X0:	/* DS5000/240 3max+ */
+		dec_init_kn03();
+		break;
+	case MACH_DS5000_XX:	/* Personal DS5000/xx */
+		dec_init_kn02ca();
+		break;
+	case MACH_DS5800:	/* DS5800 Isis */
+		panic("Don't know how to set this up!");
+		break;
+	case MACH_DS5400:	/* DS5400 MIPSfair */
+		panic("Don't know how to set this up!");
+		break;
+	case MACH_DS5500:	/* DS5500 MIPSfair-2 */
+		panic("Don't know how to set this up!");
+		break;
+	}
+	set_except_vector(0, decstation_handle_int);
+
+	/* Free the FPU interrupt if the exception is present. */
+	if (!(mips_cpu.options & MIPS_CPU_NOFPUEX)) {
+		cpu_fpu_mask = 0;
+		dec_interrupt[DEC_IRQ_FPU] = -1;
+	}
+
+	/* Register board interrupts: FPU and cascade. */
+	if (dec_interrupt[DEC_IRQ_FPU] >= 0)
+		setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
+	if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
+		setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
+
+	/* Register the HALT interrupt. */
+	if (dec_interrupt[DEC_IRQ_HALT] >= 0)
+		setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
+}
+
+EXPORT_SYMBOL(dec_interrupt);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/dec/time.c linux/arch/mips/dec/time.c
--- linux.orig/arch/mips/dec/time.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/dec/time.c	2002-08-01 06:42:37.000000000 +0000
@@ -8,6 +8,7 @@
  * found in some MIPS systems.
  *
  */
+#include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/sched.h>
@@ -44,7 +45,7 @@
 
 /* This is for machines which generate the exact clock. */
 #define USECS_PER_JIFFY (1000000/HZ)
-#define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff)
+#define USECS_PER_JIFFY_FRAC ((u32)((1000000ULL << 32) / HZ))
 
 /* Cycle counter value at the previous timer interrupt.. */
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig linux/arch/mips/defconfig
--- linux.orig/arch/mips/defconfig	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig	2002-08-01 06:42:33.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,58 +10,64 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 CONFIG_SGI_IP22=y
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
 CONFIG_ARC32=y
 CONFIG_BOARD_SCACHE=y
+CONFIG_IRQ_CPU=y
 CONFIG_PC_KEYB=y
 CONFIG_SGI=y
 CONFIG_NEW_IRQ=y
-CONFIG_OLD_TIME_C=y
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-# CONFIG_PCI is not set
-# CONFIG_I8259 is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 CONFIG_CPU_R5000=y
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -70,6 +76,7 @@
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_MIPS32 is not set
 # CONFIG_CPU_MIPS64 is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -79,20 +86,28 @@
 # General setup
 #
 # CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
 CONFIG_BINFMT_IRIX=y
 CONFIG_FORWARD_KEYBOARD=y
 # CONFIG_ARC_CONSOLE is not set
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -105,6 +120,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
@@ -112,7 +133,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
@@ -127,6 +150,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -134,8 +158,6 @@
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-CONFIG_NETLINK=y
-CONFIG_RTNETLINK=y
 CONFIG_NETLINK_DEV=y
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
@@ -156,12 +178,18 @@
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -179,6 +207,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -219,6 +252,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_DPT_I2O is not set
@@ -238,7 +272,6 @@
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR_D700 is not set
 # CONFIG_SCSI_NCR53C7xx is not set
 # CONFIG_SCSI_PAS16 is not set
 # CONFIG_SCSI_PCI2000 is not set
@@ -273,7 +306,6 @@
 # CONFIG_SUNLANCE is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -294,6 +326,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -334,11 +367,6 @@
 # CONFIG_ISDN is not set
 
 #
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
 # Character devices
 #
 CONFIG_VT=y
@@ -358,7 +386,11 @@
 # Mice
 #
 # CONFIG_BUSMOUSE is not set
-# CONFIG_MOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+# CONFIG_MK712_MOUSE is not set
 
 #
 # Joysticks
@@ -377,14 +409,32 @@
 #
 # Watchdog Cards
 #
-# CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_SC520_WDT is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_WAFER_WDT is not set
+CONFIG_INDYDOG=y
+# CONFIG_I810_TCO is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_SC1200_WDT is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_MACHZ_WDT is not set
+CONFIG_INDYDOG=y
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -401,13 +451,9 @@
 #
 # SGI Character devices
 #
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
 CONFIG_SGI_NEWPORT_CONSOLE=y
 CONFIG_FONT_8x16=y
-# CONFIG_PSMOUSE is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
+CONFIG_DUMMY_CONSOLE=y
 
 #
 # File systems
@@ -423,7 +469,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -436,11 +481,12 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 CONFIG_ISO9660_FS=y
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -481,6 +527,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -533,98 +581,9 @@
 # CONFIG_USB is not set
 
 #
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-
-#
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -639,5 +598,6 @@
 # Kernel hacking
 #
 CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-atlas linux/arch/mips/defconfig-atlas
--- linux.orig/arch/mips/defconfig-atlas	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-atlas	2002-08-01 06:42:40.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,51 +10,59 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 CONFIG_MIPS_ATLAS=y
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 # CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
 CONFIG_PCI=y
 CONFIG_SWAP_IO_SPACE=y
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-# CONFIG_I8259 is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 CONFIG_CPU_R5000=y
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -63,6 +71,7 @@
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_MIPS32 is not set
 # CONFIG_CPU_MIPS64 is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -72,20 +81,27 @@
 # General setup
 #
 # CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
 CONFIG_BINFMT_IRIX=y
 # CONFIG_FORWARD_KEYBOARD is not set
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
 # CONFIG_PCI_NAMES is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_SYSCTL is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -98,6 +114,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
@@ -105,7 +127,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
@@ -121,13 +145,14 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
 # Networking options
 #
 # CONFIG_PACKET is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -140,17 +165,24 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -168,6 +200,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -213,6 +250,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_DPT_I2O is not set
@@ -233,8 +271,8 @@
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR_D700 is not set
 # CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_NCR53C8XX is not set
 # CONFIG_SCSI_SYM53C8XX is not set
 # CONFIG_SCSI_PAS16 is not set
@@ -253,6 +291,16 @@
 # CONFIG_SCSI_DEBUG is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -265,6 +313,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -274,7 +323,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -295,6 +343,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -335,11 +384,6 @@
 # CONFIG_ISDN is not set
 
 #
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
 # Character devices
 #
 # CONFIG_VT is not set
@@ -379,13 +423,11 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 CONFIG_RTC=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -413,7 +455,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -426,11 +467,12 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -471,6 +513,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -491,98 +535,9 @@
 # CONFIG_USB is not set
 
 #
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-
-#
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -599,6 +554,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-cobalt linux/arch/mips/defconfig-cobalt
--- linux.orig/arch/mips/defconfig-cobalt	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-cobalt	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,609 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+CONFIG_MIPS_COBALT=y
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_COBALT_LCD=y
+CONFIG_PCI=y
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+CONFIG_CPU_NEVADA=y
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_LLDSCD=y
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NET=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+# CONFIG_IDEDMA_ONLYDISK is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CMD680 is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+CONFIG_BLK_DEV_VIA82CXXX=y
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+CONFIG_BLK_DEV_IDE_MODES=y
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+CONFIG_TULIP=y
+# CONFIG_TC35815 is not set
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_MMIO is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=16
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ddb5476 linux/arch/mips/defconfig-ddb5476
--- linux.orig/arch/mips/defconfig-ddb5476	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/defconfig-ddb5476	2002-08-01 06:42:42.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -15,23 +15,30 @@
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_NINO is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
 # CONFIG_MOMENCO_OCELOT is not set
 CONFIG_DDB5476=y
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SNI_RM200_PCI is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_MCA is not set
@@ -39,11 +46,15 @@
 CONFIG_ISA=y
 CONFIG_PCI=y
 CONFIG_PC_KEYB=y
-CONFIG_ROTTEN_IRQ=y
+CONFIG_NEW_IRQ=y
+CONFIG_IRQ_CPU=y
+CONFIG_I8259=y
 CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+CONFIG_NEW_PCI=y
+CONFIG_PCI_AUTO=y
 CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
 CONFIG_EISA=y
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
@@ -54,10 +65,12 @@
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 CONFIG_CPU_R5432=y
 # CONFIG_CPU_RM7000 is not set
@@ -84,6 +97,7 @@
 # CONFIG_PCI_NAMES is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
@@ -93,7 +107,6 @@
 #
 # CONFIG_PNP is not set
 # CONFIG_ISAPNP is not set
-# CONFIG_PNPBIOS is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -128,6 +141,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -135,7 +149,7 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -148,11 +162,13 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
@@ -266,6 +282,16 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -278,6 +304,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -287,7 +314,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -304,6 +330,7 @@
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
 CONFIG_TULIP=y
+# CONFIG_TC35815 is not set
 # CONFIG_TULIP_MWI is not set
 # CONFIG_TULIP_MMIO is not set
 # CONFIG_DE4X5 is not set
@@ -316,15 +343,18 @@
 CONFIG_NE2K_PCI=y
 # CONFIG_NE3210 is not set
 # CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_LAN_SAA9730 is not set
 # CONFIG_NET_POCKET is not set
@@ -433,7 +463,6 @@
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -461,7 +490,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -477,8 +505,9 @@
 # CONFIG_RAMFS is not set
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -519,6 +548,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -543,13 +574,14 @@
 # CONFIG_FB_CLGEN is not set
 # CONFIG_FB_PM2 is not set
 # CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_E1355 is not set
 # CONFIG_FB_MATROX is not set
 # CONFIG_FB_ATY is not set
 # CONFIG_FB_RADEON is not set
 # CONFIG_FB_ATY128 is not set
 # CONFIG_FB_SIS is not set
 CONFIG_FB_3DFX=y
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FBCON_ADVANCED is not set
 CONFIG_FBCON_CFB8=y
@@ -582,13 +614,19 @@
 #
 # CONFIG_USB_AUDIO is not set
 # CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 
@@ -616,12 +654,10 @@
 #
 #   Video4Linux support is needed for USB Multimedia device support
 #
-# CONFIG_USB_DABUSB is not set
 
 #
 # USB Network adaptors
 #
-# CONFIG_USB_PLUSB is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_CATC is not set
@@ -644,25 +680,30 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 
 #
-# Miscellaneous USB drivers
+# USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
 
 #
 # Input core support
@@ -679,6 +720,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+CONFIG_DEBUG=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ddb5477 linux/arch/mips/defconfig-ddb5477
--- linux.orig/arch/mips/defconfig-ddb5477	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/defconfig-ddb5477	2002-08-01 06:42:36.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -15,34 +15,44 @@
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_NINO is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
 # CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_DDB5476 is not set
 CONFIG_DDB5477=y
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SNI_RM200_PCI is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_MCA is not set
 # CONFIG_SBUS is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_PCI=y
 CONFIG_NEW_TIME_C=y
 CONFIG_NEW_IRQ=y
+CONFIG_IRQ_CPU=y
+CONFIG_NEW_PCI=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PCI_AUTO=y
+CONFIG_DUMMY_KEYB=y
 # CONFIG_ISA is not set
 # CONFIG_EISA is not set
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
@@ -53,10 +63,12 @@
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 CONFIG_CPU_R5432=y
 # CONFIG_CPU_RM7000 is not set
@@ -83,6 +95,7 @@
 # CONFIG_PCI_NAMES is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
@@ -120,6 +133,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -127,7 +141,7 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -140,11 +154,13 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
@@ -187,6 +203,16 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -199,6 +225,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -208,7 +235,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -222,6 +248,7 @@
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
 CONFIG_TULIP=y
+# CONFIG_TC35815 is not set
 # CONFIG_TULIP_MWI is not set
 # CONFIG_TULIP_MMIO is not set
 # CONFIG_DE4X5 is not set
@@ -234,15 +261,18 @@
 # CONFIG_NE2K_PCI is not set
 # CONFIG_NE3210 is not set
 # CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_LAN_SAA9730 is not set
 # CONFIG_NET_POCKET is not set
@@ -309,7 +339,8 @@
 CONFIG_SERIAL_CONSOLE=y
 # CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_UNIX98_PTYS is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
 
 #
 # I2C support
@@ -346,7 +377,6 @@
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -374,7 +404,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -390,8 +419,9 @@
 # CONFIG_RAMFS is not set
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -399,7 +429,7 @@
 # CONFIG_DEVFS_FS is not set
 # CONFIG_DEVFS_MOUNT is not set
 # CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS is not set
+CONFIG_DEVPTS_FS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_QNX4FS_RW is not set
 # CONFIG_ROMFS_FS is not set
@@ -432,6 +462,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -444,7 +476,30 @@
 #
 # Sound
 #
-# CONFIG_SOUND is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_HAL2 is not set
+CONFIG_SOUND_VRC5477=y
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
 
 #
 # USB support
@@ -463,13 +518,19 @@
 #
 # CONFIG_USB_AUDIO is not set
 # CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 
@@ -497,12 +558,10 @@
 #
 #   Video4Linux support is needed for USB Multimedia device support
 #
-# CONFIG_USB_DABUSB is not set
 
 #
 # USB Network adaptors
 #
-# CONFIG_USB_PLUSB is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_CATC is not set
@@ -525,25 +584,30 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 
 #
-# Miscellaneous USB drivers
+# USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
 
 #
 # Input core support
@@ -560,6 +624,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-CONFIG_LL_DEBUG=y
+CONFIG_DEBUG=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-decstation linux/arch/mips/defconfig-decstation
--- linux.orig/arch/mips/defconfig-decstation	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/defconfig-decstation	2002-08-01 06:42:45.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,52 +10,59 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 CONFIG_DECSTATION=y
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 # CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-# CONFIG_PCI is not set
-# CONFIG_I8259 is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
+CONFIG_IRQ_CPU=y
+CONFIG_NEW_IRQ=y
+CONFIG_NONCOHERENT_IO=y
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 CONFIG_CPU_R3000=y
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -67,24 +74,31 @@
 # CONFIG_CPU_ADVANCED is not set
 # CONFIG_CPU_HAS_LLSC is not set
 # CONFIG_CPU_HAS_LLDSCD is not set
-# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_WB=y
 
 #
 # General setup
 #
 CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+CONFIG_TC=y
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
-CONFIG_TC=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -97,6 +111,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
@@ -104,7 +124,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
@@ -119,6 +141,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -126,7 +149,7 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -139,17 +162,24 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -167,6 +197,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -206,6 +241,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_DPT_I2O is not set
@@ -225,7 +261,6 @@
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR_D700 is not set
 # CONFIG_SCSI_NCR53C7xx is not set
 # CONFIG_SCSI_PAS16 is not set
 # CONFIG_SCSI_PCI2000 is not set
@@ -251,6 +286,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -259,7 +295,6 @@
 # CONFIG_SUNLANCE is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -280,6 +315,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -320,11 +356,6 @@
 # CONFIG_ISDN is not set
 
 #
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
 # Character devices
 #
 # CONFIG_VT is not set
@@ -364,13 +395,11 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -387,13 +416,10 @@
 #
 # DECStation Character devices
 #
-# CONFIG_VT is not set
 CONFIG_SERIAL=y
 # CONFIG_DZ is not set
 CONFIG_ZS=y
 CONFIG_SERIAL_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
 # CONFIG_RTC is not set
 
 #
@@ -410,7 +436,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -423,11 +448,12 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -468,6 +494,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -491,103 +519,19 @@
 # CONFIG_NLS is not set
 
 #
-# USB support
-#
-# CONFIG_USB is not set
-
-#
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
+# Sound
 #
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
+# CONFIG_SOUND is not set
 
 #
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
+# USB support
 #
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB is not set
 
 #
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -604,6 +548,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ev64120 linux/arch/mips/defconfig-ev64120
--- linux.orig/arch/mips/defconfig-ev64120	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-ev64120	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,534 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+CONFIG_MIPS_EV64120=y
+# CONFIG_EVB_PCI1 is not set
+# CONFIG_SYSCLK_75 is not set
+# CONFIG_SYSCLK_83 is not set
+CONFIG_SYSCLK_100=y
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PCI=y
+# CONFIG_ISA is not set
+CONFIG_MIPS_GT64120=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_OLD_TIME_C=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+CONFIG_CPU_R5000=y
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_LLDSCD=y
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_BINFMT_IRIX is not set
+# CONFIG_FORWARD_KEYBOARD is not set
+CONFIG_NET=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_TC35815 is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+CONFIG_NE2K_PCI=y
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ev96100 linux/arch/mips/defconfig-ev96100
--- linux.orig/arch/mips/defconfig-ev96100	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-ev96100	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,529 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_KMOD is not set
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+CONFIG_MIPS_EV96100=y
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PCI=y
+CONFIG_MIPS_GT96100=y
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_PCI=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PCI_AUTO=y
+CONFIG_SWAP_IO_SPACE=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+CONFIG_CPU_RM7000=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_64BIT_PHYS_ADDR is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_LLDSCD=y
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_BINFMT_IRIX is not set
+# CONFIG_FORWARD_KEYBOARD is not set
+CONFIG_NET=y
+CONFIG_PCI_NAMES=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MIPS_GT96100ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+CONFIG_TULIP=y
+# CONFIG_TC35815 is not set
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_MMIO is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-hp-lj linux/arch/mips/defconfig-hp-lj
--- linux.orig/arch/mips/defconfig-hp-lj	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-hp-lj	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,668 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_ATLAS is not set
+CONFIG_MIPS_MALTA=y
+# CONFIG_NINO is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_I8259=y
+CONFIG_PCI=y
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_SWAP_IO_SPACE=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64 is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_64BIT_PHYS_ADDR is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_KCORE_ELF=y
+CONFIG_ELF_KERNEL=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Block devices
+#
+CONFIG_BLK_DEV_FD=y
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+CONFIG_PCNET32=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_TC35815 is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Old CD-ROM drivers (not SCSI, not IDE)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+CONFIG_EFS_FS=y
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ip22 linux/arch/mips/defconfig-ip22
--- linux.orig/arch/mips/defconfig-ip22	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-ip22	2002-08-01 06:42:48.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,58 +10,64 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 CONFIG_SGI_IP22=y
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
 CONFIG_ARC32=y
 CONFIG_BOARD_SCACHE=y
+CONFIG_IRQ_CPU=y
 CONFIG_PC_KEYB=y
 CONFIG_SGI=y
 CONFIG_NEW_IRQ=y
-CONFIG_OLD_TIME_C=y
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-# CONFIG_PCI is not set
-# CONFIG_I8259 is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 CONFIG_CPU_R5000=y
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -70,6 +76,7 @@
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_MIPS32 is not set
 # CONFIG_CPU_MIPS64 is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -79,20 +86,28 @@
 # General setup
 #
 # CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
 CONFIG_BINFMT_IRIX=y
 CONFIG_FORWARD_KEYBOARD=y
 # CONFIG_ARC_CONSOLE is not set
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -105,6 +120,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
@@ -112,7 +133,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
@@ -127,6 +150,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -134,8 +158,6 @@
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-CONFIG_NETLINK=y
-CONFIG_RTNETLINK=y
 CONFIG_NETLINK_DEV=y
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
@@ -156,12 +178,18 @@
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -179,6 +207,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -219,6 +252,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_DPT_I2O is not set
@@ -238,7 +272,6 @@
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR_D700 is not set
 # CONFIG_SCSI_NCR53C7xx is not set
 # CONFIG_SCSI_PAS16 is not set
 # CONFIG_SCSI_PCI2000 is not set
@@ -273,7 +306,6 @@
 # CONFIG_SUNLANCE is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -294,6 +326,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -334,11 +367,6 @@
 # CONFIG_ISDN is not set
 
 #
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
 # Character devices
 #
 CONFIG_VT=y
@@ -358,7 +386,11 @@
 # Mice
 #
 # CONFIG_BUSMOUSE is not set
-# CONFIG_MOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+# CONFIG_MK712_MOUSE is not set
 
 #
 # Joysticks
@@ -377,14 +409,32 @@
 #
 # Watchdog Cards
 #
-# CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_SC520_WDT is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_WAFER_WDT is not set
+CONFIG_INDYDOG=y
+# CONFIG_I810_TCO is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_SC1200_WDT is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_MACHZ_WDT is not set
+CONFIG_INDYDOG=y
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -401,13 +451,9 @@
 #
 # SGI Character devices
 #
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
 CONFIG_SGI_NEWPORT_CONSOLE=y
 CONFIG_FONT_8x16=y
-# CONFIG_PSMOUSE is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
+CONFIG_DUMMY_CONSOLE=y
 
 #
 # File systems
@@ -423,7 +469,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -436,11 +481,12 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 CONFIG_ISO9660_FS=y
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -481,6 +527,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -533,98 +581,9 @@
 # CONFIG_USB is not set
 
 #
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-
-#
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -639,5 +598,6 @@
 # Kernel hacking
 #
 CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-it8172 linux/arch/mips/defconfig-it8172
--- linux.orig/arch/mips/defconfig-it8172	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-it8172	2002-08-01 06:42:40.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -15,28 +15,31 @@
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_NINO is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
 # CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SNI_RM200_PCI is not set
 CONFIG_MIPS_ITE8172=y
 # CONFIG_IT8172_REVC is not set
-CONFIG_QTRONIX_KEYBOARD=y
-CONFIG_IT8172_CIR=y
-# CONFIG_IT8172_SCR0 is not set
-# CONFIG_IT8172_SCR1 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_MCA is not set
@@ -45,26 +48,31 @@
 CONFIG_IT8712=y
 CONFIG_PC_KEYB=y
 CONFIG_NEW_PCI=y
+CONFIG_NONCOHERENT_IO=y
 CONFIG_PCI_AUTO=y
+CONFIG_IT8172_CIR=y
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
 # CONFIG_ISA is not set
 # CONFIG_EISA is not set
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
 #
 CONFIG_MODULES=y
 # CONFIG_MODVERSIONS is not set
-# CONFIG_KMOD is not set
+CONFIG_KMOD=y
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -91,6 +99,7 @@
 CONFIG_PCI_NAMES=y
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_SYSCTL=y
@@ -102,7 +111,6 @@
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_PARTITIONS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_BOOTLDR_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -117,14 +125,17 @@
 # RAM/ROM/Flash chip drivers
 #
 CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_VIRTUAL_ER is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_AMDSTD is not set
-# CONFIG_MTD_SHARP is not set
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
 # CONFIG_MTD_JEDEC is not set
 
 #
@@ -134,16 +145,9 @@
 CONFIG_MTD_PHYSMAP_START=8000000
 CONFIG_MTD_PHYSMAP_LEN=2000000
 CONFIG_MTD_PHYSMAP_BUSWIDTH=4
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_SBC_GXX is not set
-# CONFIG_MTD_ELAN_104NC is not set
-# CONFIG_MTD_DBOX2 is not set
+# CONFIG_MTD_PB1000 is not set
+# CONFIG_MTD_PB1500 is not set
 # CONFIG_MTD_CSTM_MIPS_IXX is not set
-# CONFIG_MTD_CFI_FLAGADM is not set
-# CONFIG_MTD_MIXMEM is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_VMAX is not set
 # CONFIG_MTD_OCELOT is not set
 
 #
@@ -152,6 +156,7 @@
 # CONFIG_MTD_PMC551 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
 
 #
 # Disk-On-Chip Device Drivers
@@ -180,7 +185,7 @@
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_BLK_DEV_INITRD is not set
@@ -194,16 +199,18 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
 # Networking options
 #
-# CONFIG_PACKET is not set
-# CONFIG_NETLINK is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
-# CONFIG_UNIX is not set
+CONFIG_UNIX=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
@@ -213,11 +220,13 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
@@ -347,6 +356,16 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -359,6 +378,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -368,7 +388,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -382,6 +401,7 @@
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
 CONFIG_TULIP=y
+# CONFIG_TC35815 is not set
 # CONFIG_TULIP_MWI is not set
 # CONFIG_TULIP_MMIO is not set
 # CONFIG_DE4X5 is not set
@@ -394,15 +414,18 @@
 # CONFIG_NE2K_PCI is not set
 # CONFIG_NE3210 is not set
 # CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
 CONFIG_8139TOO=y
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_LAN_SAA9730 is not set
 # CONFIG_NET_POCKET is not set
@@ -469,8 +492,8 @@
 CONFIG_SERIAL_CONSOLE=y
 # CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
-CONFIG_QTRONIX_KEYBOARD=y
-CONFIG_IT8172_CIR=y
+# CONFIG_QTRONIX_KEYBOARD is not set
+CONFIG_PC_KEYB=y
 # CONFIG_IT8172_SCR0 is not set
 # CONFIG_IT8172_SCR1 is not set
 CONFIG_UNIX98_PTYS=y
@@ -507,11 +530,10 @@
 # CONFIG_WATCHDOG is not set
 # CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
+CONFIG_RTC=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -540,7 +562,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -556,8 +577,9 @@
 # CONFIG_RAMFS is not set
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -598,6 +620,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -610,7 +634,31 @@
 #
 # Sound
 #
-# CONFIG_SOUND is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+CONFIG_SOUND_IT8172=y
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_HAL2 is not set
+CONFIG_SOUND_IT8172=y
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
 
 #
 # USB support
@@ -629,13 +677,19 @@
 #
 # CONFIG_USB_AUDIO is not set
 # CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 
@@ -663,12 +717,10 @@
 #
 #   Video4Linux support is needed for USB Multimedia device support
 #
-# CONFIG_USB_DABUSB is not set
 
 #
 # USB Network adaptors
 #
-# CONFIG_USB_PLUSB is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_CATC is not set
@@ -691,25 +743,30 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 
 #
-# Miscellaneous USB drivers
+# USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
 
 #
 # Input core support
@@ -726,6 +783,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ivr linux/arch/mips/defconfig-ivr
--- linux.orig/arch/mips/defconfig-ivr	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-ivr	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,763 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+CONFIG_MIPS_IVR=y
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PCI=y
+CONFIG_PC_KEYB=y
+CONFIG_NEW_PCI=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PCI_AUTO=y
+CONFIG_IT8172_CIR=y
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+CONFIG_CPU_NEVADA=y
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_LLDSCD=y
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NET=y
+CONFIG_PCI_NAMES=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CMD680 is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+CONFIG_BLK_DEV_IT8172=y
+CONFIG_IT8172_TUNING=y
+CONFIG_BLK_DEV_IT8172=y
+CONFIG_IT8172_TUNING=y
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+CONFIG_BLK_DEV_IDE_MODES=y
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+CONFIG_TULIP=y
+# CONFIG_TC35815 is not set
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_MMIO is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_QTRONIX_KEYBOARD=y
+CONFIG_IT8172_CIR=y
+# CONFIG_IT8172_SCR0 is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_LONG_TIMEOUT is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+CONFIG_USB_OHCI=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_WACOM is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_BRLVGER is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-jmr3927 linux/arch/mips/defconfig-jmr3927
--- linux.orig/arch/mips/defconfig-jmr3927	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-jmr3927	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,671 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_NINO is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+CONFIG_TOSHIBA_JMR3927=y
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_NONCOHERENT_IO=y
+CONFIG_TOSHIBA_BOARDS=y
+CONFIG_PCI=y
+CONFIG_NEW_PCI=y
+CONFIG_PCI_AUTO=y
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_PC_KEYB=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+CONFIG_CPU_TX39XX=y
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_ADVANCED is not set
+# CONFIG_CPU_HAS_LLSC is not set
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_RTC_DS1742=y
+CONFIG_KCORE_ELF=y
+CONFIG_ELF_KERNEL=y
+# CONFIG_BINFMT_IRIX is not set
+# CONFIG_FORWARD_KEYBOARD is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+# CONFIG_IDE is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+CONFIG_TC35815=y
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Old CD-ROM drivers (not SCSI, not IDE)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_ESPSERIAL is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_SERIAL_TX3912 is not set
+# CONFIG_SERIAL_TX3912_CONSOLE is not set
+# CONFIG_AU1000_UART is not set
+CONFIG_TXX927_SERIAL=y
+CONFIG_TXX927_SERIAL_CONSOLE=y
+# CONFIG_UNIX98_PTYS is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_EXT2_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_CLGEN is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+CONFIG_FBCON_MFB=y
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-malta linux/arch/mips/defconfig-malta
--- linux.orig/arch/mips/defconfig-malta	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-malta	2002-08-01 06:42:37.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,53 +10,62 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
-CONFIG_MIPS_MALTA=y
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+CONFIG_MIPS_MALTA=y
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 # CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
 CONFIG_I8259=y
 CONFIG_PCI=y
 CONFIG_HAVE_STD_PC_SERIAL_PORT=y
 CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
 CONFIG_SWAP_IO_SPACE=y
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
+CONFIG_PC_KEYB=y
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -65,6 +74,9 @@
 # CONFIG_CPU_SB1 is not set
 CONFIG_CPU_MIPS32=y
 # CONFIG_CPU_MIPS64 is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 # CONFIG_CPU_HAS_LLDSCD is not set
@@ -74,18 +86,25 @@
 # General setup
 #
 CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
 # CONFIG_PCI_NAMES is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_SYSCTL is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -98,6 +117,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 CONFIG_BLK_DEV_FD=y
@@ -105,7 +130,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
@@ -121,13 +148,14 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
 # Networking options
 #
 # CONFIG_PACKET is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -140,17 +168,24 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -168,6 +203,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -213,6 +253,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_DPT_I2O is not set
@@ -233,8 +274,8 @@
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR_D700 is not set
 # CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_NCR53C8XX is not set
 # CONFIG_SCSI_SYM53C8XX is not set
 # CONFIG_SCSI_PAS16 is not set
@@ -253,6 +294,16 @@
 # CONFIG_SCSI_DEBUG is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -265,6 +316,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -274,7 +326,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -288,6 +339,7 @@
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
 # CONFIG_TULIP is not set
+# CONFIG_TC35815 is not set
 # CONFIG_DE4X5 is not set
 # CONFIG_DGRS is not set
 # CONFIG_DM9102 is not set
@@ -298,15 +350,18 @@
 # CONFIG_NE2K_PCI is not set
 # CONFIG_NE3210 is not set
 # CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_LAN_SAA9730 is not set
 # CONFIG_NET_POCKET is not set
@@ -321,6 +376,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -361,11 +417,6 @@
 # CONFIG_ISDN is not set
 
 #
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
 # Character devices
 #
 # CONFIG_VT is not set
@@ -405,13 +456,11 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 CONFIG_RTC=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -439,7 +488,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -452,11 +500,12 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -497,6 +546,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -517,98 +568,9 @@
 # CONFIG_USB is not set
 
 #
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-
-#
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -625,6 +587,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-nino linux/arch/mips/defconfig-nino
--- linux.orig/arch/mips/defconfig-nino	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-nino	2002-08-01 06:42:33.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -15,35 +15,43 @@
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 CONFIG_NINO=y
 # CONFIG_NINO_4MB is not set
 CONFIG_NINO_8MB=y
 # CONFIG_NINO_16MB is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
 # CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SNI_RM200_PCI is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_MCA is not set
 # CONFIG_SBUS is not set
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
 CONFIG_PC_KEYB=y
 # CONFIG_ISA is not set
 # CONFIG_EISA is not set
-# CONFIG_PCI is not set
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
@@ -56,10 +64,12 @@
 # CPU selection
 #
 CONFIG_CPU_R3000=y
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -81,10 +91,11 @@
 CONFIG_ELF_KERNEL=y
 # CONFIG_BINFMT_AOUT is not set
 CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=y
-# CONFIG_NET is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_SYSCTL is not set
@@ -111,10 +122,15 @@
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=2048
+CONFIG_BLK_DEV_RAM_SIZE=512
 CONFIG_BLK_DEV_INITRD=y
 
 #
+# MIPS initrd options
+#
+# CONFIG_EMBEDDED_RAMDISK is not set
+
+#
 # Multi-device support (RAID and LVM)
 #
 # CONFIG_MD is not set
@@ -123,9 +139,54 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -145,13 +206,33 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+# CONFIG_NETDEVICES is not set
+
+#
 # Amateur Radio support
 #
 # CONFIG_HAMRADIO is not set
 
 #
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
 # ISDN subsystem
 #
+# CONFIG_ISDN is not set
 
 #
 # Old CD-ROM drivers (not SCSI, not IDE)
@@ -161,7 +242,8 @@
 #
 # Character devices
 #
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
 # CONFIG_SERIAL is not set
 # CONFIG_SERIAL_EXTENDED is not set
 CONFIG_SERIAL_NONSTANDARD=y
@@ -184,8 +266,8 @@
 CONFIG_SERIAL_TX3912=y
 CONFIG_SERIAL_TX3912_CONSOLE=y
 # CONFIG_AU1000_UART is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_TXX927_SERIAL is not set
+# CONFIG_UNIX98_PTYS is not set
 
 #
 # I2C support
@@ -222,7 +304,6 @@
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -250,7 +331,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -266,8 +346,9 @@
 # CONFIG_RAMFS is not set
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -275,7 +356,7 @@
 # CONFIG_DEVFS_FS is not set
 # CONFIG_DEVFS_MOUNT is not set
 # CONFIG_DEVFS_DEBUG is not set
-CONFIG_DEVPTS_FS=y
+# CONFIG_DEVPTS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_QNX4FS_RW is not set
 # CONFIG_ROMFS_FS is not set
@@ -285,8 +366,31 @@
 # CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
-# CONFIG_NCPFS_NLS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -297,6 +401,50 @@
 # CONFIG_NLS is not set
 
 #
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_TRIDENT is not set
+CONFIG_FB_TX3912=y
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+CONFIG_FBCON_MFB=y
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
+# CONFIG_FBCON_CFB16 is not set
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
 # Sound
 #
 # CONFIG_SOUND is not set
@@ -318,13 +466,19 @@
 #
 # CONFIG_USB_AUDIO is not set
 # CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 
@@ -352,15 +506,15 @@
 #
 #   Video4Linux support is needed for USB Multimedia device support
 #
-# CONFIG_USB_DABUSB is not set
 
 #
 # USB Network adaptors
 #
-
-#
-#   Networking support is needed for USB Networking device support
-#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
 
 #
 # USB port drivers
@@ -378,25 +532,30 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 
 #
-# Miscellaneous USB drivers
+# USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
 
 #
 # Input core support
@@ -411,5 +570,6 @@
 # Kernel hacking
 #
 CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-ocelot linux/arch/mips/defconfig-ocelot
--- linux.orig/arch/mips/defconfig-ocelot	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-ocelot	2002-08-01 06:42:42.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -15,23 +15,30 @@
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_NINO is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
 CONFIG_MOMENCO_OCELOT=y
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SNI_RM200_PCI is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_MCA is not set
@@ -40,10 +47,10 @@
 CONFIG_SYSCLK_100=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_NEW_IRQ=y
+CONFIG_NONCOHERENT_IO=y
 CONFIG_OLD_TIME_C=y
 # CONFIG_ISA is not set
 # CONFIG_EISA is not set
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
@@ -54,10 +61,12 @@
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 CONFIG_CPU_RM7000=y
@@ -66,6 +75,8 @@
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_MIPS32 is not set
 # CONFIG_CPU_MIPS64 is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -86,6 +97,7 @@
 CONFIG_PCI_NAMES=y
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
@@ -123,13 +135,14 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
 # Networking options
 #
 # CONFIG_PACKET is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -142,11 +155,13 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
@@ -189,6 +204,16 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -201,6 +226,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -210,7 +236,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -224,6 +249,7 @@
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
 # CONFIG_TULIP is not set
+# CONFIG_TC35815 is not set
 # CONFIG_DE4X5 is not set
 # CONFIG_DGRS is not set
 # CONFIG_DM9102 is not set
@@ -234,15 +260,18 @@
 # CONFIG_NE2K_PCI is not set
 # CONFIG_NE3210 is not set
 # CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_WINBOND_840 is not set
 # CONFIG_LAN_SAA9730 is not set
 # CONFIG_NET_POCKET is not set
@@ -347,7 +376,6 @@
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -375,7 +403,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -391,8 +418,9 @@
 # CONFIG_RAMFS is not set
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -433,6 +461,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -464,13 +494,19 @@
 #
 # CONFIG_USB_AUDIO is not set
 # CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 
@@ -498,12 +534,10 @@
 #
 #   Video4Linux support is needed for USB Multimedia device support
 #
-# CONFIG_USB_DABUSB is not set
 
 #
 # USB Network adaptors
 #
-# CONFIG_USB_PLUSB is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_CATC is not set
@@ -526,25 +560,30 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 
 #
-# Miscellaneous USB drivers
+# USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
 
 #
 # Input core support
@@ -561,6 +600,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-osprey linux/arch/mips/defconfig-osprey
--- linux.orig/arch/mips/defconfig-osprey	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-osprey	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,489 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+CONFIG_NEC_OSPREY=y
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_VR4181=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_MANY_PORTS=y
+CONFIG_NEW_IRQ=y
+CONFIG_IRQ_CPU=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_DUMMY_KEYB=y
+# CONFIG_SCSI is not set
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+CONFIG_CPU_VR41XX=y
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_ADVANCED is not set
+# CONFIG_CPU_HAS_LLSC is not set
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+CONFIG_NE2000=y
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-pb1000 linux/arch/mips/defconfig-pb1000
--- linux.orig/arch/mips/defconfig-pb1000	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-pb1000	2002-08-01 06:42:39.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,52 +10,63 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+CONFIG_MIPS_PB1000=y
+CONFIG_PCI_AUTO=y
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 # CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-CONFIG_MIPS_PB1000=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
 CONFIG_MIPS_AU1000=y
 CONFIG_NEW_IRQ=y
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-# CONFIG_PCI is not set
-# CONFIG_I8259 is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
+CONFIG_PCI=y
+CONFIG_NEW_PCI=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PC_KEYB=y
+MAX_HWIFS=1
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
 # CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
@@ -64,6 +75,9 @@
 # CONFIG_CPU_SB1 is not set
 CONFIG_CPU_MIPS32=y
 # CONFIG_CPU_MIPS64 is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 CONFIG_CPU_ADVANCED=y
 CONFIG_CPU_HAS_LLSC=y
 # CONFIG_CPU_HAS_LLDSCD is not set
@@ -73,22 +87,107 @@
 # General setup
 #
 CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_PCMCIA is not set
+CONFIG_PCI_NAMES=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=m
+# CONFIG_CARDBUS is not set
+# CONFIG_TCIC is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+CONFIG_PCMCIA_AU1000=m
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set
+# CONFIG_HOTPLUG_PCI_ACPI is not set
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
 #
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PB1000=y
+# CONFIG_MTD_PB1500 is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_MS02NV is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
 
 #
 # Parallel port support
@@ -96,6 +195,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
@@ -103,8 +208,10 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_BLK_DEV_INITRD is not set
@@ -118,6 +225,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -125,7 +233,7 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -138,17 +246,24 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -166,6 +281,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -175,9 +295,52 @@
 #
 # ATA/IDE/MFM/RLL support
 #
-# CONFIG_IDE is not set
-# CONFIG_BLK_DEV_IDE_MODES is not set
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
 # CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
 
 #
 # SCSI support
@@ -185,6 +348,16 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -197,6 +370,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -204,14 +378,15 @@
 CONFIG_NET_ETHERNET=y
 CONFIG_MIPS_AU1000_ENET=y
 # CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
 # CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
 # CONFIG_NET_ISA is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_NET_POCKET is not set
@@ -226,6 +401,7 @@
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -251,6 +427,11 @@
 # CONFIG_WAN is not set
 
 #
+# PCMCIA network device support
+#
+# CONFIG_NET_PCMCIA is not set
+
+#
 # Amateur Radio support
 #
 # CONFIG_HAMRADIO is not set
@@ -266,11 +447,6 @@
 # CONFIG_ISDN is not set
 
 #
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
 # Character devices
 #
 # CONFIG_VT is not set
@@ -285,6 +461,7 @@
 # CONFIG_ESPSERIAL is not set
 # CONFIG_MOXA_INTELLIO is not set
 # CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
 # CONFIG_SYNCLINK is not set
 # CONFIG_N_HDLC is not set
 # CONFIG_RISCOM8 is not set
@@ -296,6 +473,7 @@
 # CONFIG_SERIAL_TX3912_CONSOLE is not set
 CONFIG_AU1000_UART=y
 CONFIG_AU1000_SERIAL_CONSOLE=y
+# CONFIG_TXX927_SERIAL is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_UNIX98_PTY_COUNT=256
 
@@ -328,13 +506,11 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -344,6 +520,13 @@
 # CONFIG_DRM is not set
 
 #
+# PCMCIA character devices
+#
+# CONFIG_PCMCIA_SERIAL_CS is not set
+CONFIG_AU1000_GPIO=y
+# CONFIG_TS_AU1000_ADS7846 is not set
+
+#
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
@@ -362,7 +545,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -372,14 +554,16 @@
 # CONFIG_VFAT_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_JFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
-CONFIG_ISO9660_FS=y
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -387,7 +571,7 @@
 # CONFIG_DEVFS_FS is not set
 # CONFIG_DEVFS_MOUNT is not set
 # CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS is not set
+CONFIG_DEVPTS_FS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_QNX4FS_RW is not set
 # CONFIG_ROMFS_FS is not set
@@ -420,32 +604,43 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
 #
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
+# CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
 # CONFIG_SMB_NLS is not set
 # CONFIG_NLS is not set
 
 #
 # Sound
 #
-# CONFIG_SOUND is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+CONFIG_SOUND_AU1000=y
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
 
 #
 # USB support
@@ -453,98 +648,9 @@
 # CONFIG_USB is not set
 
 #
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-
-#
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -561,5 +667,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-pb1500 linux/arch/mips/defconfig-pb1500
--- linux.orig/arch/mips/defconfig-pb1500	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-pb1500	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,1002 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+CONFIG_MIPS_PB1500=y
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_MIPS_AU1000=y
+CONFIG_NEW_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_AUTO=y
+CONFIG_NEW_PCI=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PC_KEYB=y
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64 is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
+CONFIG_CPU_ADVANCED=y
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_LLDSCD is not set
+CONFIG_CPU_HAS_WB=y
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NET=y
+CONFIG_PCI_NAMES=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=m
+# CONFIG_CARDBUS is not set
+# CONFIG_TCIC is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_PCMCIA_AU1000 is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set
+# CONFIG_HOTPLUG_PCI_ACPI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PB1000 is not set
+CONFIG_MTD_PB1500=y
+CONFIG_MTD_PB1500_BOOT=y
+# CONFIG_MTD_PB1500_USER is not set
+# CONFIG_MTD_CSTM_MIPS_IXX is not set
+# CONFIG_MTD_OCELOT is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_MS02NV is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_IDEDISK_MULTI_MODE=y
+# CONFIG_IDEDISK_STROKE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_OFFBOARD=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CMD680 is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+CONFIG_BLK_DEV_HPT366=y
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+CONFIG_BLK_DEV_IDE_MODES=y
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MIPS_AU1000_ENET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_TC35815 is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+CONFIG_8139TOO_PIO=y
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_RHINE_MMIO is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_LAN_SAA9730 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+CONFIG_PPPOE=m
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+CONFIG_PCMCIA_3C589=m
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
+# CONFIG_NET_PCMCIA_RADIO is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_ESPSERIAL is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_SERIAL_TX3912 is not set
+# CONFIG_SERIAL_TX3912_CONSOLE is not set
+CONFIG_AU1000_UART=y
+CONFIG_AU1000_SERIAL_CONSOLE=y
+# CONFIG_TXX927_SERIAL is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_PCMCIA_SERIAL_CS is not set
+# CONFIG_AU1000_GPIO is not set
+# CONFIG_TS_AU1000_ADS7846 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=m
+CONFIG_JFFS_FS_VERBOSE=0
+CONFIG_JFFS_PROC_FS=y
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_CRAMFS=m
+CONFIG_TMPFS=y
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+CONFIG_ZLIB_FS_INFLATE=m
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_SMB_NLS=y
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_CLGEN is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+CONFIG_FBCON_CFB8=y
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+# CONFIG_FBCON_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+CONFIG_SOUND_AU1000=y
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_LONG_TIMEOUT is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+CONFIG_USB_OHCI=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_BLUETOOTH is not set
+
+#
+#   SCSI support is needed for USB Storage
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_WACOM is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_BRLVGER is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_REMOTE_DEBUG is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-rm200 linux/arch/mips/defconfig-rm200
--- linux.orig/arch/mips/defconfig-rm200	2001-09-09 17:43:02.000000000 +0000
+++ linux/arch/mips/defconfig-rm200	2002-08-01 06:42:47.000000000 +0000
@@ -2,7 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
-# CONFIG_SMP is not set
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -10,57 +10,65 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_NINO is not set
 # CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
 # CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
 # CONFIG_DDB5476 is not set
 # CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
 # CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
 CONFIG_SNI_RM200_PCI=y
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
 CONFIG_ARC32=y
 CONFIG_I8259=y
 CONFIG_ISA=y
+CONFIG_NEW_IRQ=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_OLD_TIME_C=y
 CONFIG_PC_KEYB=y
 CONFIG_PCI=y
-CONFIG_ROTTEN_IRQ=y
-CONFIG_OLD_TIME_C=y
-CONFIG_EISA=y
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_VR41XX is not set
 # CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-CONFIG_CPU_R5000=y
+CONFIG_CPU_R4X00=y
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_NEVADA is not set
@@ -68,6 +76,7 @@
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_MIPS32 is not set
 # CONFIG_CPU_MIPS64 is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -77,26 +86,25 @@
 # General setup
 #
 CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
 # CONFIG_ARC_CONSOLE is not set
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
 CONFIG_NET=y
 # CONFIG_PCI_NAMES is not set
+CONFIG_EISA=y
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
 # CONFIG_SYSVIPC is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
-
-#
-# Plug and Play configuration
-#
-# CONFIG_PNP is not set
-# CONFIG_ISAPNP is not set
-# CONFIG_PNPBIOS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -109,6 +117,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 CONFIG_BLK_DEV_FD=y
@@ -116,7 +130,9 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
@@ -131,6 +147,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -138,7 +155,7 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -148,17 +165,24 @@
 # CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
 #
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
 # CONFIG_DECNET is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_X25 is not set
@@ -176,6 +200,11 @@
 # CONFIG_NET_SCHED is not set
 
 #
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
 # Telephony Support
 #
 # CONFIG_PHONE is not set
@@ -195,6 +224,16 @@
 # CONFIG_SCSI is not set
 
 #
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
 # Network device support
 #
 # CONFIG_NETDEVICES is not set
@@ -259,13 +298,11 @@
 # Watchdog Cards
 #
 # CONFIG_WATCHDOG is not set
-# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 CONFIG_RTC=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
 
 #
 # Ftape, the floppy tape device driver
@@ -293,7 +330,6 @@
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-# CONFIG_CMS_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_JBD_DEBUG is not set
@@ -306,11 +342,12 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 # CONFIG_ISO9660_FS is not set
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
-# CONFIG_FREEVXFS_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
@@ -351,6 +388,8 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -395,98 +434,9 @@
 # CONFIG_USB is not set
 
 #
-# USB Controllers
-#
-# CONFIG_USB_UHCI is not set
-# CONFIG_USB_UHCI_ALT is not set
-# CONFIG_USB_OHCI is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_AUDIO is not set
-# CONFIG_USB_BLUETOOTH is not set
-# CONFIG_USB_STORAGE is not set
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# USB Human Interface Devices (HID)
-#
-
-#
-#   Input core support is needed for USB HID
-#
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_DC2XX is not set
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_SCANNER is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
-
-#
-# USB Multimedia devices
-#
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# USB Network adaptors
-#
-# CONFIG_USB_PLUSB is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_CDCETHER is not set
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-
-#
-# Miscellaneous USB drivers
+# Bluetooth support
 #
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_ID75 is not set
+# CONFIG_BLUEZ is not set
 
 #
 # Input core support
@@ -501,5 +451,6 @@
 # Kernel hacking
 #
 CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/defconfig-sb1250-swarm linux/arch/mips/defconfig-sb1250-swarm
--- linux.orig/arch/mips/defconfig-sb1250-swarm	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/defconfig-sb1250-swarm	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,507 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_ALGOR_P4032 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+CONFIG_SIBYTE_SB1250=y
+# CONFIG_PCI is not set
+# CONFIG_SIBYTE_SB1250_PROF is not set
+# CONFIG_BCM1250_TBPROF is not set
+# CONFIG_REMOTE_DEBUG is not set
+CONFIG_SIBYTE_SWARM=y
+# CONFIG_SIMULATION is not set
+# CONFIG_L3DEMO is not set
+CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS=16
+CONFIG_SMP=y
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_NEW_IRQ=y
+CONFIG_NEW_TIME_C=y
+CONFIG_DUMMY_KEYB=y
+CONFIG_SWAP_IO_SPACE=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+CONFIG_CPU_SB1=y
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+CONFIG_SB1_PASS_1_WORKAROUNDS=y
+CONFIG_SB1_CACHE_ERROR=y
+CONFIG_VTAG_ICACHE=y
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_64BIT_PHYS_ADDR is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_LLDSCD=y
+# CONFIG_CPU_HAS_WB is not set
+
+#
+# General setup
+#
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_BINFMT_IRIX is not set
+# CONFIG_FORWARD_KEYBOARD is not set
+CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_SB1250_MAC=y
+CONFIG_NET_SB1250_MAC=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_ESPSERIAL is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_SERIAL_TX3912 is not set
+# CONFIG_SERIAL_TX3912_CONSOLE is not set
+# CONFIG_AU1000_UART is not set
+# CONFIG_TXX927_SERIAL is not set
+CONFIG_SIBYTE_SB1250_DUART=y
+CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
+CONFIG_SERIAL_CONSOLE=y
+CONFIG_SB1250_DUART_OUTPUT_BUF_SIZE=1024
+# CONFIG_SIBYTE_SB1250_DUART_NO_PORT_1 is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_EXT2_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG is not set
+# CONFIG_MAGIC_SYSRQ is not set
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/Makefile linux/arch/mips/galileo-boards/ev64120/Makefile
--- linux.orig/arch/mips/galileo-boards/ev64120/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/Makefile	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,26 @@
+#
+#  Copyright 2000 RidgeRun, Inc.
+#  Author: RidgeRun, Inc.
+#     	glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+#
+# Makefile for the Galileo EV64120 board.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+USE_STANDARD_AS_RULE := true
+
+all:	ev64120.o int-handler.o
+
+O_TARGET := ev64120.o
+
+export-objs		= i2o.o
+
+obj-y	:= serialGT.o int-handler.o promcon.o reset.o setup.o irq.o \
+	   irq-handler.o i2o.o pci_bios.o
+
+int-handler.o: int-handler.S
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/cntmr.c linux/arch/mips/galileo-boards/ev64120/cntmr.c
--- linux.orig/arch/mips/galileo-boards/ev64120/cntmr.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/cntmr.c	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,207 @@
+/* cntmr.c - GT counters/timers functions */
+
+/* Copyright - Galileo technology. 9/3/2000 */
+
+/*
+DESCRIPTION
+This file contains function which serves the user with a complete interface
+to the GT internal counters and timers, please advise: each counter/timer unit
+can function only as a counter or a timer at current time.
+Counter/timer 0 is 32 bit wide.
+Counters/timers 1-3 are 24 bit wide.
+*/
+
+/* includes */
+
+#ifdef __linux__
+#include <asm/galileo/evb64120A/cntmr.h>
+#include <asm/galileo/evb64120A/core.h>
+#else
+#include "cntmr.h"
+#include "core.h"
+#endif
+
+/********************************************************************
+* cntTmrStart - Starts a counter/timer with given an initiate value.
+*
+* INPUTS:  unsigned int countNum - Selects one of the 8 counters/timers.
+*          unsigned int countValue - Initial value for count down. 
+*          CNT_TMR_OP_MODES opMode - Set Mode, Counter or Timer.
+*
+* RETURNS: false if one of the parameters is erroneous, true otherwise.
+*********************************************************************/
+
+bool cntTmrStart(CNTMR_NUM countNum, unsigned int countValue,
+		 CNT_TMR_OP_MODES opMode)
+{
+	unsigned int command = 1;
+	unsigned int value;
+
+	if (countNum > LAST_CNTMR)
+		return false;
+	else {
+		GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
+		cntTmrDisable(countNum);
+		GT_REG_WRITE((TIMER_COUNTER0 + (4 * countNum)),
+			     countValue);
+		command = command << countNum * 2;
+		value = value | command;
+		command = command << 1;
+		switch (opMode) {
+		case TIMER:	/* The Timer/Counter bit set to logic '1' */
+			value = value | command;
+			break;
+		case COUNTER:	/* The Timer/Counter bit set to logic '0' */
+			value = value & ~command;
+			break;
+		default:
+			return false;
+		}
+		GT_REG_WRITE(TIMER_COUNTER_CONTROL, value);
+		return true;
+	}
+}
+
+/********************************************************************
+* cntTmrDisable - Disables the timer/counter operation and return its 
+*                 value.
+*
+* INPUTS:  unsigned int countNum - Selects one of the 8 counters/timers.
+* RETURNS: The counter/timer value (unsigned int), if any of the arguments are 
+*          erroneous return 0.
+*********************************************************************/
+
+unsigned int cntTmrDisable(CNTMR_NUM countNum)
+{
+	unsigned int command = 1;
+	unsigned int regValue;
+	unsigned int value;
+
+	GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
+	if (countNum > LAST_CNTMR)
+		return 0;
+	GT_REG_READ(TIMER_COUNTER0 + 4 * countNum, &regValue);
+	command = command << countNum * 2;	/* Disable the timer/counter */
+	value = value & ~command;
+	GT_REG_WRITE(TIMER_COUNTER_CONTROL, value);
+	return regValue;
+}
+
+/********************************************************************
+* cntTmrRead - Reads a timer or a counter value. (This operation can be
+*              perform while the counter/timer is active).
+*
+* RETURNS: The counter/timer value. If wrong input value, return 0.
+*********************************************************************/
+
+unsigned int cntTmrRead(CNTMR_NUM countNum)
+{
+	unsigned int value;
+	if (countNum > LAST_CNTMR)
+		return 0;
+	else
+		GT_REG_READ(TIMER_COUNTER0 + countNum * 4, &value);
+	return value;
+}
+
+/********************************************************************
+* cntTmrEnable - Set enable-bit of timer/counter.
+*                Be aware: If the counter/timer is active, this function
+*                          will terminate with an false.
+*
+* INPUTS:  unsigned int countNum - Selects one of the 8 counters/timers.
+* RETURNS: false if one of the parameters is erroneous, true otherwise.
+*********************************************************************/
+
+bool cntTmrEnable(CNTMR_NUM countNum)
+{
+	unsigned int command = 1;
+	unsigned int value;
+	GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
+	if (countNum > LAST_CNTMR)
+		return false;
+	else {
+		command = command << countNum * 2;
+		if ((command & value) != 0)	/* ==> The counter/timer is enabled */
+			return false;	/* doesn't make sense to Enable an "enabled" counter */
+		value = value | command;
+		GT_REG_WRITE(TIMER_COUNTER_CONTROL, value);
+		return true;
+	}
+}
+
+/********************************************************************
+* cntTmrLoad - loading value for timer number countNum.
+*              Be aware: If this function try to load value to an enabled
+*                        counter/timer it terminate with false.
+*
+* INPUTS:  unsigned int countNum - Selects one of the 8 counters/timers.
+*          unsigned int countValue - The value for load the register.
+* RETURNS: false if one of the parameters is erroneous, true otherwise.
+*********************************************************************/
+
+bool cntTmrLoad(unsigned int countNum, unsigned int countValue)
+{
+	unsigned int command = 1;
+	unsigned int value;
+	GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
+	if (countNum > LAST_CNTMR)
+		return false;
+	else {
+		command = command << countNum * 2;
+		value = value & command;
+		if (value != 0) {	/* ==> The counter/timer is enabled */
+			return false;	/* can't reload value when counter/timer is enabled */
+		} else {
+			GT_REG_WRITE((TIMER_COUNTER0 + (4 * countNum)),
+				     countValue);
+			return true;
+		}
+
+	}
+}
+
+/********************************************************************
+* cntTmrSetMode - Configurate the Mode of the channel to work as a counter
+*                 or as a timer. (for more details on the different between
+*                 those two modes is written in the Data Sheet).
+*                 NOTE: This function only set the counter/timer mode and
+*                 don't enable it. 
+*                 Be aware: If this function try to load value to an enabled
+*                           counter/timer it terminate with false.
+* 
+* INPUTS:  unsigned int countNum - Selects one of the 8 counters/timers.
+*          CNT_TMR_OP_MODES opMode - TIMER or COUNTER mode.
+* RETURNS: false if one of the parameters is erroneous true otherwise .
+*********************************************************************/
+
+bool cntTmrSetMode(CNTMR_NUM countNum, CNT_TMR_OP_MODES opMode)
+{
+	unsigned int command = 1;
+	unsigned int value;
+
+	GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
+	if (countNum > LAST_CNTMR)
+		return false;
+	else {
+		command = command << countNum * 2;
+		value = value & command;
+		if (value != 0) {	/* ==> The counter/timer is enabled */
+			return false;	/* can't set the Mode when counter/timer is enabled */
+		} else {
+			command = command << 1;
+			switch (opMode) {
+			case TIMER:
+				value = value | command;	/* The Timer/Counter bit set to logic '1' */
+				break;
+			case COUNTER:
+				value = value & ~command;	/*The Timer/Counter bit set to logic '0' */
+				break;
+			default:
+				return false;
+			}
+			GT_REG_WRITE(TIMER_COUNTER_CONTROL, value);
+			return true;
+		}
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/Makefile linux/arch/mips/galileo-boards/ev64120/compressed/Makefile
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/Makefile	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,177 @@
+# =============================================================
+#
+# linux/arch/mips/galileo/compressed/Makefile
+#
+# By RidgeRun Inc.
+#
+# Description:
+#   Create a system containing a copy of the compressed vmlinux kernel.
+#   The system knows how to decompress the contained kernel and then
+#   jump to it resulting in a linux kernel boot.
+#
+#   The system comes in three forms:
+#
+#       1. - ramsys - 
+#          to be loaded into ram then run. When run
+#          it decompresses the kernel housed in its internal
+#          data structures and then jumps to the image which
+#          results in a linux kernel boot.
+#
+#       2. - flashsys - 
+#          to be loaded into ram so that it can be
+#          burned into the onboard flash. Then the board jumpers
+#          can be switched so that the next power cycle caused
+#          the system in flash to run which then proceeds as
+#          described by #1 above.
+#          Note: burner.srec is the utility that will allow
+#          the user to get this image into flash.
+#
+#       3. - flashsys2 - 
+#          to be loaded into ram so that it can be
+#          burned into the onboard flash. Then on each power
+#          cycle when the standard PMON prompt is presented 
+#          the user can type `call 0xbf000000` to invoke
+#          the system in flash which then proceeds as
+#          described by #1 above.
+#          Note: burner.srec is the utility that will allow
+#          the user to get this image into flash.
+#
+#       4. - burner.srec -
+#          related to #2 and #3 above.
+#
+# =============================================================
+
+USE_STANDARD_AS_RULE := true
+
+all: ramsys.srec \
+     flashsys.srec \
+     flashsys2.srec \
+     burner.srec
+
+SYSTEM = $(TOPDIR)/vmlinux
+
+CFLAGS_2 = -DCONSOLE_SERIAL -DDELIMITERLINES -DGALILEO_PORT \
+           -DANSIESC -DELF_IMAGE -DELF_IMAGE -DDOWNLOAD_PROTO_TFTP \
+           -DEVB64120A -D__MIPSEB__ -DINCLUDE_EEPRO100 \
+           -DINCLUDE_GETH0 -DNOPRINTK -DPROM -DCOMPRESSEDVMLINUX
+
+sbdreset_evb64120A.o:
+	$(CC) $(CFLAGS) $(CFLAGS_2) -c sbdreset_evb64120A.S -o $*.o
+memory.o:
+	$(CC) $(CFLAGS) $(CFLAGS_2) -c memory.c -o $*.o
+pci.o:
+	$(CC) $(CFLAGS) $(CFLAGS_2) -c pci.c -o $*.o
+pci_etherboot.o:
+	$(CC) $(CFLAGS) $(CFLAGS_2) -c pci_etherboot.c -o $*.o
+load.o:
+	$(CC) $(CFLAGS) $(CFLAGS_2) -c load.c -o $*.o
+flashdrv.o:
+	$(CC) $(CFLAGS) $(CFLAGS_2) -c flashdrv.c -o $*.o
+
+gz2asm: gz2asm.c
+	g++ -o gz2asm gz2asm.c
+
+doit: doit.c
+	gcc -o doit doit.c
+
+piggy.gz: $(SYSTEM)
+	rm -f piggy piggy.gz 
+	$(OBJCOPY) -S -O binary $(SYSTEM) piggy
+	gzip -f -9 < piggy > piggy.gz
+
+piggy.S: doit fixit piggy.gz
+	./doit < piggy.gz > piggy.S; . ./fixit piggy.S
+
+OBJECTS_ramsys    = head.o misc.o piggy.o ../serialGT.o
+OBJECTS_flashsys  = sbdreset_evb64120A.o evb64120A_Setup.o pci_etherboot.o memory.o pci.o head.o misc.o piggy.o ../serialGT.o
+OBJECTS_flashsys2 = xfer.o head.o misc.o piggy.o ../serialGT.o
+OBJECTS_burner    = burner.o load.o flashdrv.o
+
+ramsys.srec : $(OBJECTS_ramsys) ld.script.gal
+	@# Note: this image is intended to run out of ram. No flash involved.
+	$(LD) -T ld.script.gal -o ramsys $(OBJECTS_ramsys) 
+	$(NM) ramsys | grep -v '\(compiled\)\|\(\.o$$\)\|\( [aU] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | sort > System_ramsys.map
+	$(OBJCOPY) -O srec ramsys ramsys.srec
+	cp ramsys.srec $(TOPDIR)/.
+
+flashsys.srec : $(OBJECTS_flashsys) ld.sys.big.Flash
+	@# Note1: Use the burn utility to get this image into flash.
+	@# Note2: This image is intended to run out of flash as invoked
+	@# directly at powerup when EVB64120A jumpers are configured to 
+	@# bypass the onboard eprom.
+	@# Assumes that 0xBFC00000 is the bootup run address (normal MIPS).
+	@# And assumes that EVB64120A jumber J11 is added to the board and jumber
+	@# J20 is moved from the 2&3 position to the 1&2 position instead. Without
+	@# the jumper settings the system will execute at address 0xBFC00000,
+	@# as normal, yet that address will map to the onboard eeprom instead
+	@# of the onboard flash.
+	@# 
+	$(LD) -T ld.sys.big.Flash -o flashsys $(OBJECTS_flashsys) 
+	$(NM) flashsys | grep -v '\(compiled\)\|\(\.o$$\)\|\( a \)' | sort > System_flashsys.map
+	@#
+	@# Next, Create the image that we want to place in the flash part.
+	$(OBJCOPY)  -S -g --strip-unneeded \
+	      --adjust-section-vma=.text+0x3f820000 \
+	      --adjust-section-vma=.rodata+0x3f820000 \
+	      --adjust-section-vma=.reginfo+0x3f820000 \
+	      --adjust-section-vma=.data+0x3f820000  \
+	      --remove-section=.bss \
+	      --remove-section=.scommon \
+	      --remove-section=.note \
+	      --remove-section=.comment \
+	      flashsys flashsys.temp
+	@#
+	@# Next, change the addresses so that when we download to
+	@# to the board's ram it will land starting at address 0xA0300000
+	@# because this is where we have choosen to have the image temporarily sit
+	@# while we subsequently burn it (using some method not revealed here) into
+	@# the board's flash. After the burn the system can be setup (via jumpers) 
+	@# to boot this image directory from the flash part.
+	$(OBJCOPY) -O srec --adjust-vma=0xe0700000 flashsys.temp flashsys.srec
+	cp flashsys.srec $(TOPDIR)/.
+
+flashsys2.srec : $(OBJECTS_flashsys2) ld.sys.big.Flash2
+	@# Note1: Use the burn utility to get this image into flash.
+	@# Note2: This image is intended to be run out of flash as invoked
+	@# manually from the standard PMON running in eprom. This means that
+	@# the image will be set to run from location 0xBF000000 which is the
+	@# location the flash is mapped to when the board jumpers are set to
+	@# the standard location such that the board boots out of onboard
+	@# eprom. From the PMON prompt the user can type `call 0xbf000000`
+	@# to transfer control to the image we are constructing here.
+	@# 
+	$(LD) -T ld.sys.big.Flash2 -o flashsys2 $(OBJECTS_flashsys2) 
+	$(NM) flashsys2 | grep -v '\(compiled\)\|\(\.o$$\)\|\( a \)' | sort > System_flashsys2.map
+	@#
+	@# Next, Create the image that we want to place in the flash part.
+	$(OBJCOPY)  -S -g --strip-unneeded \
+	      --adjust-section-vma=.text+0x3ec20000 \
+	      --adjust-section-vma=.rodata+0x3ec20000 \
+	      --adjust-section-vma=.reginfo+0x3ec20000 \
+	      --adjust-section-vma=.data+0x3ec20000  \
+	      --remove-section=.bss \
+	      --remove-section=.scommon \
+	      --remove-section=.note \
+	      --remove-section=.comment \
+	      flashsys2 flashsys2.temp
+	@#
+	@# Next, change the addresses so that when we download to
+	@# to the board's ram it will land starting at address 0xA0300000
+	@# because this is where we have choosen to have the image temporarily sit
+	@# while we subsequently burn it (using some method not revealed here) into
+	@# the board's flash. After the burn a user will then be able to type
+	@# `call 0xbf000000` at the PMON prompt (following a power cycle) to invoke
+	@# the linux kernel.
+	$(OBJCOPY) -O srec --adjust-vma=0xe1300000 flashsys2.temp flashsys2.srec
+	cp flashsys2.srec $(TOPDIR)/.
+
+burner.srec : $(OBJECTS_burner) ld.sys.big.burner
+	@# This utility can be used to burn the flashsys.srec or flashsys2.srec
+	@# into the EVB64120A's on board flash part (1Meg minimum).
+	$(LD) -T ld.sys.big.burner -o burner $(OBJECTS_burner) 
+	$(NM) burner | grep -v '\(compiled\)\|\(\.o$$\)\|\( [aU] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | sort > System_burner.map
+	$(OBJCOPY) -O srec burner burner.srec
+	cp burner.srec $(TOPDIR)/.
+
+clean:
+	rm -f doit piggy.S piggy.gz piggy burner *.o ramsys* flashsys* System*.map *.srec
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/README linux/arch/mips/galileo-boards/ev64120/compressed/README
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/README	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/README	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,131 @@
++------------------------------------------------+
+|  $TOPDIR/arch/mips/galileo/compressed/README   |
+|                                                |
+|  By RidgeRun Inc,                              |
+|  Aug, 2000                                     |
++------------------------------------------------+
+
+Description:
+============
+  It is intended that this makefile be wired in to run as
+  part of a top level linux build. For example, at the
+  time of this writing, if the user types "make gboot" at
+  the top level then in addition to building vmlinux the
+  build system's makefiles will descend into this
+  directory and build the "all:" target of this
+  Makefile. This will have the result of compressing the
+  vmlinux system and producing four separate systems. The
+  following snippet is pulled from this directory's
+  Makefile and describes each system.
+
+  Four systems are availalbe for download to the EVB64120A
+  board.
+
+   1. - ramsys - 
+      To be loaded into ram then run. When run
+      it decompresses the "vmlinux" kernel housed in its internal
+      data structures and then jumps to the image which
+      results in a linux kernel boot.
+
+   2. - flashsys - 
+      To be loaded into ram so that it can be
+      burned into the onboard flash. Then the board jumpers
+      can be switched so that the next power cycle caused
+      the system in flash to run which then proceeds as
+      described by #1 above.
+      Note: burner.srec is the utility that will allow
+      the user to get this image into flash.
+
+   3. - flashsys2 - 
+      To be loaded into ram so that it can be
+      burned into the onboard flash. Then on each power
+      cycle when the standard PMON prompt is presented 
+      the user can type `call 0xbf000000` to invoke
+      the system in flash which then proceeds as
+      described by #1 above.
+      Note: burner.srec is the utility that will allow
+      the user to get this image into flash.
+
+   4. - burner.srec -
+      Related to #2 and #3 above.
+
+Example: Running from Ram
+==========================
+
+  In this scenario the compressed system is downloaded
+  into ram and run directly from there. No flash is involved 
+  in this scenario. Naturally, the download must be repeated 
+  on every power cycle.
+
+  1. At the PMON prompt type `load`
+  2. Assuming you have your host connected to /dev/ttyS0
+     type the following command in a host shell window.
+     `cat ramsys.srec > /dev/ttyS0`
+  3. When the download completes type the following
+     at the PMON prompt: `g`
+
+
+Example: Running from flash: Scenario #1
+========================================
+
+  In this scenario vmlinux runs out of flash code
+  automatically on every power up. This means that 
+  standard PMON code (of eprom) never runs.
+
+  1. Place the boot jumpers in the Boot-from-eprom
+     state. This is the normal state and how the jumpers
+     are found when booting PMON.
+
+     Jumper settings. J11 - Removed
+                      J20 - Moved from the 1&2 position to 
+                            the 2&3 position instead
+
+  2. Use PMON to "load" the burner.srec image and then
+     run it. This utility will prompt you to download
+     the image that you want burned into the flash
+     part.
+
+  3. Send the flashsys.srec image to the running burner
+     utility. The utililty will indicate when the burn
+     process has completed.
+
+  4. Now switch off power and change the jumpers to 
+     the boot-from-flash position. The next power cycle
+     will run the flash based system automatically.
+
+     Jumper settings. J11 - Added.
+                      J20 - Moved from the 2&3 position to 
+                            the 1&2 position instead
+
+Example: Running from flash: Scenario #2
+========================================
+
+  In this scenario vmlinux runs out of flash only if the
+  PMON user decides to jump there by issuing a command to
+  PMON. Every power cycle would continue to bring up PMON
+  and a user will have to reissue the jump command to
+  force control transfer to the flash system.
+
+  1. Insure that the boot jumpers are in the Boot-from-eprom
+     state. This is the normal state and how the jumpers
+     are found when booting PMON.
+
+     Jumper settings. J11 - Removed
+                      J20 - Moved from the 1&2 position to 
+                            the 2&3 position instead
+
+  2. Use PMON to "load" the burner.srec image and then
+     run it. This utility will prompt you to download
+     the image that you want burned into the flash
+     part.
+
+  3. Send the flashsys2.srec image to the running burner
+     utility. The utililty will indicate when the burn
+     process has completed.
+
+  4. Now that the image is in flash the user can invoke
+     the following PMON command whenever a vmlinux
+     boot is desired:
+
+     call 0xbf000000
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/burner.c linux/arch/mips/galileo-boards/ev64120/compressed/burner.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/burner.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/burner.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,230 @@
+/*
+ *  arch/mips/galileo/compressed/burner.c
+ *
+ *  By RidgeRun Inc (Leveraged from Galileo's main.c, misc.c, etc).
+ *
+ *  Burn image from ram to flash 
+ *  For use with Galileo EVB64120A MIPS eval board.
+ */
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <asm/galileo-boards/evb64120A/eeprom_param.h>
+#include <asm/galileo-boards/evb64120A/flashdrv.h>
+
+#define IMAGEOFFSET 0x00300000
+
+static void burn_image_from_memory(void);
+static char *sprintf(char *buf, const char *fmt, ...);
+static void printf(const char *fmt, ...);
+
+unsigned int FlashSize;
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+int main(void)
+{
+	printf("\n");
+	printf("\n");
+	printf("\n");
+	printf("\n");
+	printf("       +--------------------+\n");
+	printf("       |                    |\n");
+	printf("       | Flash Burn Utility |\n");
+	printf("       |                    |\n");
+	printf("       +--------------------+\n");
+	printf("\n");
+	printf("Please send your *.srec image to the parallel port\n");
+	printf("\n");
+	printf("Note: The *.srec image should be setup to\n");
+	printf("      load into address 0xa0300000 where\n");
+	printf("      it will then be transferred to flash\n");
+	printf("\n");
+
+	SET_REG_BITS(0x468, BIT20);	// Set Flash to be 16 bit wide
+	FlashSize = flashInit(0xbf000000, 2, X16);
+
+	galileo_dl();		// read in the users *.srec image.
+	burn_image_from_memory();	// put it in flash.
+
+	printf("\n");
+	printf("\n");
+	printf("+---------------+\n");
+	printf("|     Done      |\n");
+	printf("|(please reboot)|\n");
+	printf("+---------------+\n");
+	printf("\n");
+
+	while (1) {
+	}
+	return 0;
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+static void burn_image_from_memory(void)
+{
+	unsigned int count, delta, temp, temp1;
+	unsigned int to_sector, last_sector;
+
+	/* Find how many sectors needed to be erased */
+	to_sector = flashInWhichSector(FlashSize - 4);	// skranz, modified.
+	if (to_sector == 0xffffffff) {
+		printf
+		    ("Flash Burning Error - Flash too small - Cannot burn image\n");	// skranz, modified.
+		return;
+	}
+
+	/* Which is the last sector */
+	last_sector = flashInWhichSector(FlashSize - 4);
+	delta = 0;
+	printf("\nErasing first %d sectors\n", to_sector);
+	for (count = 0; count < to_sector + 1; count++) {
+		printf("Erasing sector %d\n", count);
+		flashEraseSector(count);
+	}
+	printf("flash region size = %d\n", FlashSize);	// skranz, added
+	printf("Sdram IMAGEOFFSET = %d\n", IMAGEOFFSET);	// skranz, added
+
+	printf("Burning from Sdram to %d mark; full burn.\n", FlashSize);
+	for (count = 0; count < (FlashSize - delta); count = count + 4) {
+		flashWriteWord(count,
+			       *(unsigned int *) ((count | NONE_CACHEABLE)
+						  + IMAGEOFFSET));	// skranz, modified.
+		temp = flashReadWord(count);
+		temp1 = *(unsigned int *) ((count | NONE_CACHEABLE) + IMAGEOFFSET);	// skranz, modified.
+		if (((unsigned int) temp) != ((unsigned int) temp1)) {
+			printf
+			    ("Burning error at address %X : flash(%X) sdram(%X)\n",
+			     count, flashReadWord(count),
+			     *(unsigned int *) ((count | NONE_CACHEABLE) + IMAGEOFFSET));	// skranz, modified.
+			printf("Aborting Prematurally.\n");
+			break;
+		}
+	}
+	printf("Finished burning Image\n");
+}
+
+/******************************
+ Routine:
+ Description:
+	Formats:
+		%X	- 4 byte ASCII (8 hex digits)
+		%x	- 2 byte ASCII (4 hex digits)
+		%b	- 1 byte ASCII (2 hex digits)
+		%d	- decimal (also %i)
+		%c	- ASCII char
+		%s	- ASCII string
+		%I	- Internet address in x.x.x.x notation
+ ******************************/
+static char hex[] = "0123456789ABCDEF";
+static char *do_printf(char *buf, const char *fmt, const int *dp)
+{
+	register char *p;
+	char tmp[16];
+	while (*fmt) {
+		if (*fmt == '%') {	/* switch() uses more space */
+			fmt++;
+
+			if (*fmt == 'X') {
+				const long *lp = (const long *) dp;
+				register long h = *lp++;
+				dp = (const int *) lp;
+				*(buf++) = hex[(h >> 28) & 0x0F];
+				*(buf++) = hex[(h >> 24) & 0x0F];
+				*(buf++) = hex[(h >> 20) & 0x0F];
+				*(buf++) = hex[(h >> 16) & 0x0F];
+				*(buf++) = hex[(h >> 12) & 0x0F];
+				*(buf++) = hex[(h >> 8) & 0x0F];
+				*(buf++) = hex[(h >> 4) & 0x0F];
+				*(buf++) = hex[h & 0x0F];
+			}
+			if (*fmt == 'x') {
+				register int h = *(dp++);
+				*(buf++) = hex[(h >> 12) & 0x0F];
+				*(buf++) = hex[(h >> 8) & 0x0F];
+				*(buf++) = hex[(h >> 4) & 0x0F];
+				*(buf++) = hex[h & 0x0F];
+			}
+			if (*fmt == 'b') {
+				register int h = *(dp++);
+				*(buf++) = hex[(h >> 4) & 0x0F];
+				*(buf++) = hex[h & 0x0F];
+			}
+			if ((*fmt == 'd') || (*fmt == 'i')) {
+				register int dec = *(dp++);
+				p = tmp;
+				if (dec < 0) {
+					*(buf++) = '-';
+					dec = -dec;
+				}
+				do {
+					*(p++) = '0' + (dec % 10);
+					dec = dec / 10;
+				} while (dec);
+				while ((--p) >= tmp)
+					*(buf++) = *p;
+			}
+			if (*fmt == 'I') {
+				union {
+					long l;
+					unsigned char c[4];
+				} u;
+				const long *lp = (const long *) dp;
+				u.l = *lp++;
+				dp = (const int *) lp;
+				buf = sprintf(buf, "%d.%d.%d.%d",
+					      u.c[0], u.c[1], u.c[2],
+					      u.c[3]);
+			}
+			if (*fmt == 'c')
+				*(buf++) = *(dp++);
+			if (*fmt == 's') {
+				p = (char *) *dp++;
+				while (*p)
+					*(buf++) = *p++;
+			}
+		} else
+			*(buf++) = *fmt;
+		fmt++;
+	}
+	*buf = 0;
+	return (buf);
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+static char *sprintf(char *buf, const char *fmt, ...)
+{
+	return do_printf(buf, fmt, ((const int *) &fmt) + 1);
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+void putchar(int c)
+{
+	if (c == '\n') {
+		serial_putc('\r');
+	}
+	serial_putc(c);
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+static void printf(const char *fmt, ...)
+{
+	char buf[256], *p;
+	p = buf;
+	do_printf(buf, fmt, ((const int *) &fmt) + 1);
+	while (*p)
+		putchar(*p++);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/doit.c linux/arch/mips/galileo-boards/ev64120/compressed/doit.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/doit.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/doit.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,75 @@
+/*
+ *    By RidgeRun Inc.
+ *
+ *    The input to this program is intended to be
+ *    a compressed linux kernel. The output of this
+ *    program is then a constructed *.S file which
+ *    defines a large data structure -- the contents
+ *    of which represent the compressed kernel which
+ *    can subsequently be used in a program designed
+ *    to access that struture for decompression at
+ *    runtime and then subsequent kernel bootup.
+ *
+ *    Example Usage:
+ *       ./doit < piggy.gz > piggy.S
+ *       
+ */
+
+#include <stdio.h>
+
+void printval(int i)
+{
+	int tth, th, h, t, d;
+
+	if (i > 99999) {
+		printf("Error - printval outofbounds\n");
+		return;
+	}
+
+	tth = 0;
+	th = 0;
+	//tth = (i) / 10000;
+	//th  = (i - (tth * 10000)) / 1000;
+	h = (i - ((tth * 10000) + (th * 1000))) / 100;
+	t = (i - ((tth * 10000) + (th * 1000) + (h * 100))) / 10;
+	d = (i - ((tth * 10000) + (th * 1000) + (h * 100) + (t * 10)));
+	//putchar(tth + '0');
+	//putchar(th + '0');
+	putchar(h + '0');
+	putchar(t + '0');
+	putchar(d + '0');
+}
+
+main(int argc, char **argv)
+{
+	int val;
+	int size = 0;
+	unsigned char c;
+
+	printf("gcc2_compiled.:\n");
+	printf("__gnu_compiled_c:\n");
+	printf("\t.globl linux_compressed_start\n");
+	printf("\t.text\n");
+	printf("\t.align 2\n");
+	printf("\t.type linux_compressed_start,@object\n");
+	printf("linux_compressed_start:\n");
+
+
+	val = getchar();
+	while (val != EOF) {
+		size++;
+		c = (unsigned char) (val & 0x00ff);
+		printf("\t.byte  ");
+		printval((int) c);
+		printf("\n");
+		val = getchar();
+	}
+	printf("\t.size linux_compressed_start,%d\n", size);
+	printf("\t.globl linux_compressed_size\n");
+	printf("\t.text\n");
+	printf("\t.align 2\n");
+	printf("\t.type linux_compressed_size,@object\n");
+	printf("\t.size linux_compressed_size,4\n");
+	printf("linux_compressed_size:\n");
+	printf("\t.word %d\n", size);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/etherboot.h linux/arch/mips/galileo-boards/ev64120/compressed/etherboot.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/etherboot.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/etherboot.h	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,566 @@
+/**************************************************************************
+ETHERBOOT -  BOOTP/TFTP Bootstrap Program
+
+Author: Martin Renters
+  Date: Dec/93
+
+**************************************************************************/
+
+#include "osdep.h"
+
+/* These could be customised for different languages perhaps */
+#define	ASK_PROMPT	"Boot from (N)etwork or from (L)ocal? "
+#define	ANS_NETWORK	'N'
+#define	ANS_LOCAL	'L'
+#ifndef	ANS_DEFAULT		/* in case left out in Makefile */
+#define	ANS_DEFAULT	ANS_NETWORK
+#endif
+
+#define	TAGGED_IMAGE		/* eventually optional */
+#if	!defined(TAGGED_IMAGE) && !defined(AOUT_IMAGE) && !defined(ELF_IMAGE)
+#define	TAGGED_IMAGE		/* choose at least one */
+#endif
+
+#define ESC		0x1B
+
+#ifndef	DEFAULT_BOOTFILE
+#define DEFAULT_BOOTFILE	"/tftpboot/kernel"
+#endif
+
+/* Clean up console settings... mainly CONSOLE_CRT and CONSOLE_SERIAL are used
+ * in the sources (except start.S and serial.S which cannot include
+ * etherboot.h).  At least one of the CONSOLE_xxx has to be set, and
+ * CONSOLE_DUAL sets both CONSOLE_CRT and CONSOLE_SERIAL.  If none is set,
+ * CONSOLE_CRT is assumed.  */
+#ifdef	CONSOLE_DUAL
+#undef CONSOLE_CRT
+#define CONSOLE_CRT
+#undef CONSOLE_SERIAL
+#define CONSOLE_SERIAL
+#endif
+#if	defined(CONSOLE_CRT) && defined(CONSOLE_SERIAL)
+#undef CONSOLE_DUAL
+#define CONSOLE_DUAL
+#endif
+#if	!defined(CONSOLE_CRT) && !defined(CONSOLE_SERIAL)
+#define CONSOLE_CRT
+#endif
+
+#ifndef	DOWNLOAD_PROTO_NFS
+#undef DOWNLOAD_PROTO_TFTP
+#define DOWNLOAD_PROTO_TFTP	/* default booting protocol */
+#endif
+
+#ifdef	DOWNLOAD_PROTO_TFTP
+#define download(fname,loader) tftp((fname),(loader))
+#endif
+#ifdef	DOWNLOAD_PROTO_NFS
+#define download(fname,loader) nfs((fname),(loader))
+#endif
+
+#ifndef	MAX_TFTP_RETRIES
+#define MAX_TFTP_RETRIES	20
+#endif
+
+#ifndef	MAX_BOOTP_RETRIES
+#define MAX_BOOTP_RETRIES	20
+#endif
+
+#ifndef	MAX_BOOTP_EXTLEN
+#if	(RELOC < 0x94000)
+/* Force internal buffer (if external buffer would overlap with our code...) */
+#undef INTERNAL_BOOTP_DATA
+#define INTERNAL_BOOTP_DATA
+#endif
+/* sizeof(struct bootp_t) == 0x240 */
+#if	defined(INTERNAL_BOOTP_DATA) || (RELOC >= 0x94240)
+#define MAX_BOOTP_EXTLEN	1024
+#else
+#define MAX_BOOTP_EXTLEN	(1024-sizeof(struct bootp_t))
+#endif
+#endif
+
+#ifndef	MAX_ARP_RETRIES
+#define MAX_ARP_RETRIES		20
+#endif
+
+#ifndef	MAX_RPC_RETRIES
+#define MAX_RPC_RETRIES		20
+#endif
+
+#define	TICKS_PER_SEC		18
+
+/* Inter-packet retry in ticks */
+#define TIMEOUT			(10*TICKS_PER_SEC)
+
+/* These settings have sense only if compiled with -DCONGESTED */
+/* total retransmission timeout in ticks */
+#define TFTP_TIMEOUT		(30*TICKS_PER_SEC)
+/* packet retransmission timeout in ticks */
+#define TFTP_REXMT		(3*TICKS_PER_SEC)
+
+#ifndef	NULL
+#define NULL	((void *)0)
+#endif
+
+#define TRUE		1
+#define FALSE		0
+
+#define ETHER_ADDR_SIZE		6	/* Size of Ethernet address */
+#define ETHER_HDR_SIZE		14	/* Size of ethernet header */
+#define ETH_MIN_PACKET		64
+#define ETH_MAX_PACKET		1518
+
+#define VENDOR_NONE	0
+#define VENDOR_WD	1
+#define VENDOR_NOVELL	2
+#define VENDOR_3COM	3
+#define VENDOR_3C509	4
+#define VENDOR_CS89x0	5
+
+#define FLAG_PIO	0x01
+#define FLAG_16BIT	0x02
+#define FLAG_790	0x04
+
+#define ARP_CLIENT	0
+#define ARP_SERVER	1
+#define ARP_GATEWAY	2
+#define ARP_ROOTSERVER	3
+#define ARP_SWAPSERVER	4
+#define MAX_ARP		ARP_SWAPSERVER+1
+
+#define	RARP_REQUEST	3
+#define	RARP_REPLY	4
+
+#define IP		0x0800
+#define ARP		0x0806
+#define	RARP		0x8035
+
+#define BOOTP_SERVER	67
+#define BOOTP_CLIENT	68
+#define TFTP_PORT	69
+#define SUNRPC_PORT	111
+
+#define IP_UDP		17
+/* Same after going through htonl */
+#define IP_BROADCAST	0xFFFFFFFF
+
+#define ARP_REQUEST	1
+#define ARP_REPLY	2
+
+#define BOOTP_REQUEST	1
+#define BOOTP_REPLY	2
+
+#define TAG_LEN(p)		(*((p)+1))
+#define RFC1533_COOKIE		99, 130, 83, 99
+#define RFC1533_PAD		0
+#define RFC1533_NETMASK		1
+#define RFC1533_TIMEOFFSET	2
+#define RFC1533_GATEWAY		3
+#define RFC1533_TIMESERVER	4
+#define RFC1533_IEN116NS	5
+#define RFC1533_DNS		6
+#define RFC1533_LOGSERVER	7
+#define RFC1533_COOKIESERVER	8
+#define RFC1533_LPRSERVER	9
+#define RFC1533_IMPRESSSERVER	10
+#define RFC1533_RESOURCESERVER	11
+#define RFC1533_HOSTNAME	12
+#define RFC1533_BOOTFILESIZE	13
+#define RFC1533_MERITDUMPFILE	14
+#define RFC1533_DOMAINNAME	15
+#define RFC1533_SWAPSERVER	16
+#define RFC1533_ROOTPATH	17
+#define RFC1533_EXTENSIONPATH	18
+#define RFC1533_IPFORWARDING	19
+#define RFC1533_IPSOURCEROUTING	20
+#define RFC1533_IPPOLICYFILTER	21
+#define RFC1533_IPMAXREASSEMBLY	22
+#define RFC1533_IPTTL		23
+#define RFC1533_IPMTU		24
+#define RFC1533_IPMTUPLATEAU	25
+#define RFC1533_INTMTU		26
+#define RFC1533_INTLOCALSUBNETS	27
+#define RFC1533_INTBROADCAST	28
+#define RFC1533_INTICMPDISCOVER	29
+#define RFC1533_INTICMPRESPOND	30
+#define RFC1533_INTROUTEDISCOVER 31
+#define RFC1533_INTROUTESOLICIT	32
+#define RFC1533_INTSTATICROUTES	33
+#define RFC1533_LLTRAILERENCAP	34
+#define RFC1533_LLARPCACHETMO	35
+#define RFC1533_LLETHERNETENCAP	36
+#define RFC1533_TCPTTL		37
+#define RFC1533_TCPKEEPALIVETMO	38
+#define RFC1533_TCPKEEPALIVEGB	39
+#define RFC1533_NISDOMAIN	40
+#define RFC1533_NISSERVER	41
+#define RFC1533_NTPSERVER	42
+#define RFC1533_VENDOR		43
+#define RFC1533_NBNS		44
+#define RFC1533_NBDD		45
+#define RFC1533_NBNT		46
+#define RFC1533_NBSCOPE		47
+#define RFC1533_XFS		48
+#define RFC1533_XDM		49
+#ifndef	NO_DHCP_SUPPORT
+#define RFC2132_REQ_ADDR	50
+#define RFC2132_MSG_TYPE	53
+#define RFC2132_SRV_ID		54
+#define RFC2132_PARAM_LIST	55
+#define RFC2132_MAX_SIZE	57
+
+#define DHCPDISCOVER		1
+#define DHCPOFFER		2
+#define DHCPREQUEST		3
+#define DHCPACK			5
+#endif				/* NO_DHCP_SUPPORT */
+
+#define RFC1533_VENDOR_MAJOR	0
+#define RFC1533_VENDOR_MINOR	0
+
+#define RFC1533_VENDOR_MAGIC	128
+#define RFC1533_VENDOR_ADDPARM	129
+#ifdef	IMAGE_FREEBSD
+#define RFC1533_VENDOR_HOWTO    132
+#endif
+#define RFC1533_VENDOR_MNUOPTS	160
+#define RFC1533_VENDOR_SELECTION 176
+#define RFC1533_VENDOR_MOTD	184
+#define RFC1533_VENDOR_NUMOFMOTD 8
+#define RFC1533_VENDOR_IMG	192
+#define RFC1533_VENDOR_NUMOFIMG	16
+
+#define RFC1533_END		255
+#define BOOTP_VENDOR_LEN	64
+#ifndef	NO_DHCP_SUPPORT
+#define DHCP_OPT_LEN		312
+#endif				/* NO_DHCP_SUPPORT */
+
+#define	TFTP_DEFAULTSIZE_PACKET	512
+#define	TFTP_MAX_PACKET		1432	/* 512 */
+
+#define TFTP_RRQ	1
+#define TFTP_WRQ	2
+#define TFTP_DATA	3
+#define TFTP_ACK	4
+#define TFTP_ERROR	5
+#define TFTP_OACK	6
+
+#define TFTP_CODE_EOF	1
+#define TFTP_CODE_MORE	2
+#define TFTP_CODE_ERROR	3
+#define TFTP_CODE_BOOT	4
+#define TFTP_CODE_CFG	5
+
+#define AWAIT_ARP	0
+#define AWAIT_BOOTP	1
+#define AWAIT_TFTP	2
+#define AWAIT_RARP	3
+#define AWAIT_RPC	4
+#define AWAIT_QDRAIN	5	/* drain queue, process ARP requests */
+
+typedef struct {
+	unsigned long s_addr;
+} in_addr;
+
+struct arptable_t {
+	in_addr ipaddr;
+	unsigned char node[6];
+};
+
+/*
+ * A pity sipaddr and tipaddr are not longword aligned or we could use
+ * in_addr. No, I don't want to use #pragma packed.
+ */
+struct arprequest {
+	unsigned short hwtype;
+	unsigned short protocol;
+	char hwlen;
+	char protolen;
+	unsigned short opcode;
+	char shwaddr[6];
+	char sipaddr[4];
+	char thwaddr[6];
+	char tipaddr[4];
+};
+
+struct iphdr {
+	char verhdrlen;
+	char service;
+	unsigned short len;
+	unsigned short ident;
+	unsigned short frags;
+	char ttl;
+	char protocol;
+	unsigned short chksum;
+	in_addr src;
+	in_addr dest;
+};
+
+struct udphdr {
+	unsigned short src;
+	unsigned short dest;
+	unsigned short len;
+	unsigned short chksum;
+};
+
+struct bootp_t {
+	struct iphdr ip;
+	struct udphdr udp;
+	char bp_op;
+	char bp_htype;
+	char bp_hlen;
+	char bp_hops;
+	unsigned long bp_xid;
+	unsigned short bp_secs;
+	unsigned short unused;
+	in_addr bp_ciaddr;
+	in_addr bp_yiaddr;
+	in_addr bp_siaddr;
+	in_addr bp_giaddr;
+	char bp_hwaddr[16];
+	char bp_sname[64];
+	char bp_file[128];
+#ifdef	NO_DHCP_SUPPORT
+	char bp_vend[BOOTP_VENDOR_LEN];
+#else
+	char bp_vend[DHCP_OPT_LEN];
+#endif				/* NO_DHCP_SUPPORT */
+};
+
+struct bootpd_t {
+	struct bootp_t bootp_reply;
+	unsigned char bootp_extension[MAX_BOOTP_EXTLEN];
+};
+
+struct tftp_t {
+	struct iphdr ip;
+	struct udphdr udp;
+	unsigned short opcode;
+	union {
+		char rrq[TFTP_DEFAULTSIZE_PACKET];
+		struct {
+			unsigned short block;
+			char download[TFTP_MAX_PACKET];
+		} data;
+		struct {
+			unsigned short block;
+		} ack;
+		struct {
+			unsigned short errcode;
+			char errmsg[TFTP_DEFAULTSIZE_PACKET];
+		} err;
+		struct {
+			char data[TFTP_DEFAULTSIZE_PACKET + 2];
+		} oack;
+	} u;
+};
+
+#define TFTP_MIN_PACKET	(sizeof(struct iphdr) + sizeof(struct udphdr) + 4)
+
+struct rpc_t {
+	struct iphdr ip;
+	struct udphdr udp;
+	union {
+		char data[300];	/* longest RPC call must fit!!!! */
+		struct {
+			long id;
+			long type;
+			long rpcvers;
+			long prog;
+			long vers;
+			long proc;
+			long data[1];
+		} call;
+		struct {
+			long id;
+			long type;
+			long rstatus;
+			long verifier;
+			long v2;
+			long astatus;
+			long data[1];
+		} reply;
+	} u;
+};
+
+#define PROG_PORTMAP	100000
+#define PROG_NFS	100003
+#define PROG_MOUNT	100005
+
+#define MSG_CALL	0
+#define MSG_REPLY	1
+
+#define PORTMAP_GETPORT	3
+
+#define MOUNT_ADDENTRY	1
+#define MOUNT_UMOUNTALL	4
+
+#define NFS_LOOKUP	4
+#define NFS_READ	6
+
+#define NFS_FHSIZE	32
+
+#define NFSERR_PERM	1
+#define NFSERR_NOENT	2
+#define NFSERR_ACCES	13
+
+/* Block size used for NFS read accesses.  A RPC reply packet (including  all
+ * headers) must fit within a single Ethernet frame to avoid fragmentation.
+ * Chosen to be a power of two, as most NFS servers are optimized for this.  */
+#define NFS_READ_SIZE	1024
+
+#define	FLOPPY_BOOT_LOCATION	0x7c00
+
+#define	ROM_INFO_LOCATION	0x7dfa
+/* at end of floppy boot block */
+
+struct rom_info {
+	unsigned short rom_segment;
+	unsigned short rom_length;
+};
+
+/***************************************************************************
+External prototypes
+***************************************************************************/
+/* main.c */
+extern void print_bytes P((unsigned char *bytes, int len));
+extern void load P((void));
+extern int load_linux P((int root_mount_port, int swap_mount_port,
+			 int root_nfs_port, char *kernel_handle));
+extern int downloadkernel P((unsigned char *, int, int, int));
+extern int tftp
+P((const char *name, int (*)(unsigned char *, int, int, int)));
+extern void rpc_init(void);
+extern int nfs
+P((const char *name, int (*)(unsigned char *, int, int, int)));
+extern void nfs_umountall P((int));
+extern int bootp P((void));
+extern int rarp P((void));
+extern int udp_transmit P((unsigned long destip, unsigned int srcsock,
+			   unsigned int destsock, int len,
+			   const void *buf));
+
+extern int await_reply P((int type, int ival, void *ptr, int timeout));
+extern int decode_rfc1533 P((unsigned char *, int, int, int));
+extern unsigned short ipchksum P((unsigned short *, int len));
+extern void rfc951_sleep P((int));
+extern void cleanup_net P((void));
+extern void cleanup P((void));
+
+/* config.c */
+extern void print_config(void);
+extern void eth_reset(void);
+extern int eth_probe(void);
+extern int eth_poll(void);
+extern void eth_transmit(const char *d, unsigned int t, unsigned int s,
+			 const void *p);
+extern void eth_disable(void);
+
+/* bootmenu.c */
+extern int execute P((char *string));
+extern void bootmenu P((int));
+extern void show_motd P((void));
+extern void parse_menuopts P((char *, int));
+extern int getoptvalue P((char **, int *, int *));
+extern void selectImage P((char **));
+
+/* osloader.c */
+#if	defined(AOUT_IMAGE) || defined(ELF_IMAGE)
+extern int howto;
+#endif
+extern int os_download P((unsigned int, unsigned char *, unsigned int));
+
+/* misc.c */
+extern void twiddle P((void));
+extern void sleep P((int secs));
+extern int strcasecmp P((char *a, char *b));
+extern char *substr P((char *a, char *b));
+extern int getdec P((char **));
+extern void printf P((const char *, ...));
+extern char *sprintf P((char *, const char *, ...));
+extern int inet_aton P((char *p, in_addr * i));
+extern void gateA20_set P((void));
+extern void gateA20_unset P((void));
+extern void putchar P((int));
+extern int getchar P((void));
+extern int iskey P((void));
+
+/* start*.S */
+extern int getc P((void));
+extern void putc P((int));
+extern int ischar P((void));
+extern int getshift P((void));
+extern unsigned int memsize P((void));
+extern unsigned short basememsize P((void));
+extern void disk_init P((void));
+extern unsigned int disk_read P((int drv, int c, int h, int s, char *buf));
+extern void xstart P((unsigned long, unsigned long, char *));
+extern unsigned long currticks P((void));
+extern int setjmp P((void *jmpbuf));
+extern void longjmp P((void *jmpbuf, int where));
+extern void exit P((int status));
+extern void slowdownio P((void));
+
+/* serial.S */
+extern int serial_getc P((void));
+extern void serial_putc P((int));
+extern int serial_ischar P((void));
+extern int serial_init P((void));
+
+/* ansiesc.c */
+extern void ansi_reset P((void));
+extern void enable_cursor P((int));
+extern void handleansi P((unsigned char));
+
+/* md5.c */
+extern void md5_put P((unsigned int ch));
+extern void md5_done P((unsigned char *buf));
+
+/* floppy.c */
+extern int bootdisk P((int dev, int part));
+
+/***************************************************************************
+External variables
+***************************************************************************/
+/* main.c */
+extern const char *kernel;
+extern char kernel_buf[128];
+extern struct rom_info rom;
+extern int hostnamelen;
+extern unsigned long netmask;
+extern int jmp_bootmenu[10];
+extern struct arptable_t arptable[MAX_ARP];
+#ifdef	IMAGE_MENU
+extern char *motd[RFC1533_VENDOR_NUMOFMOTD];
+extern int menutmo, menudefault;
+extern unsigned char *defparams;
+extern int defparams_max;
+#endif
+#if	defined(ETHERBOOT32) && !defined(INTERNAL_BOOTP_DATA)
+#define	BOOTP_DATA_ADDR	((struct bootpd_t *)0x93C00)
+#else
+extern struct bootpd_t bootp_data;
+#define	BOOTP_DATA_ADDR	(&bootp_data)
+#endif
+extern unsigned char *end_of_rfc1533;
+#ifdef	IMAGE_FREEBSD
+extern int freebsd_howto;
+#endif
+
+/* config.c */
+extern struct nic nic;
+
+/* bootmenu.c */
+
+/* osloader.c */
+
+/* created by linker */
+extern char _start[], _edata[], _end[];
+
+/*
+ * Local variables:
+ *  c-basic-offset: 8
+ * End:
+ */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/evb64120A_Setup.c linux/arch/mips/galileo-boards/ev64120/compressed/evb64120A_Setup.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/evb64120A_Setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/evb64120A_Setup.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,197 @@
+/*
+ *  arch/mips/galileo/compressed/evb64120A_memSetup.c
+ *
+ *  By RidgeRun Inc, (Leveraged from Galileo's sbd.c)
+ *
+ *  Xfer an image from flash to ram.
+ *  For use with Galileo EVB64120A MIPS eval board.
+ */
+#include "ns16550.h"
+#include <linux/serial_reg.h>
+#include <asm/galileo-boards/evb64120A/pci.h>
+#include <asm/galileo-boards/evb64120A/core.h>
+
+void XferToRam(void);
+bool mapMemoryBanks0and1(unsigned int bank0Base, unsigned int bank0Length,
+			 unsigned int bank1Base, unsigned int bank1Length);
+bool mapMemoryBanks2and3(unsigned int bank2Base, unsigned int bank2Length,
+			 unsigned int bank3Base, unsigned int bank3Length);
+bool mapDevices0_1and2MemorySpace(unsigned int device0Base,
+				  unsigned int device0Length,
+				  unsigned int device1Base,
+				  unsigned int device1Length,
+				  unsigned int device2Base,
+				  unsigned int device2Length);
+
+#define RUNNINGFROMFLASH
+#include "./xfer.c"
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+unsigned int readWord(unsigned int addr)
+{
+	unsigned int tmp;
+	tmp = *(unsigned int *) (addr | NONE_CACHEABLE);
+	return WORDSWAP(tmp);
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+void writeWord(unsigned int addr, unsigned int data)
+{
+	*((unsigned int *) (addr | NONE_CACHEABLE)) = WORDSWAP(data);
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+unsigned int GetExtendedMemorySize(void)
+{
+	unsigned int address, data = 0x11223344, type;
+	unsigned int bank1_ef = false, bank2_ef = false, bank3_ef = false;
+	unsigned int bank0_size, bank2_size, bank3_size, total_size = 0;
+
+	mapMemoryBanks0and1(0, 0x800000, 0x800000, 0x800000);
+	mapMemoryBanks2and3(0x1000000, 0x800000, 0x1800000, 0x800000);
+	type = readWord(0x14000810);
+	switch (type) {
+	case 16:
+		bank0_size = 0x1000000;
+		break;
+	case 64:
+		bank0_size = 0x4000000;
+		break;
+	case 128:
+		bank0_size = 0x8000000;
+		break;
+	case 256:
+		bank0_size = 0x10000000;
+		break;
+	default:
+		bank0_size = 0x1000000;
+		break;
+	}
+
+	type = readWord(0x14000814);
+	switch (type) {
+	case 16:
+		bank2_size = 0x1000000;
+		bank3_size = 0x1000000;
+		break;
+	case 64:
+		bank2_size = 0x4000000;
+		bank3_size = 0x4000000;
+		break;
+	case 128:
+		bank2_size = 0x8000000;
+		bank3_size = 0x8000000;
+		break;
+	case 256:
+		bank2_size = 0x10000000;
+		bank3_size = 0x10000000;
+		break;
+	default:
+		bank2_size = 0x1000000;
+		bank3_size = 0x1000000;
+		break;
+	}
+
+	/* Check which banks exist */
+	/* Bank 1 */
+	for (address = 0xffff00; address < 0x1000000; address += 4)
+		writeWord(address, data);
+	for (address = 0xffff00; address < 0x1000000; address += 4) {
+		if (readWord(address) != data)
+			break;
+	}
+	if (address == 0x1000000)
+		bank1_ef = true;
+	// Bank 2
+	for (address = 0x17fff00; address < 0x1800000; address += 4)
+		writeWord(address, data);
+	for (address = 0x17fff00; address < 0x1800000; address += 4) {
+		if (readWord(address) != data)
+			break;
+	}
+	if (address == 0x1800000)
+		bank2_ef = true;
+	else
+		bank2_size = 0x0;
+	// Bank 3
+	for (address = 0x1ffff00; address < 0x2000000; address += 4)
+		writeWord(address, data);
+	for (address = 0x1ffff00; address < 0x2000000; address += 4) {
+		if (readWord(address) != data)
+			break;
+	}
+	if (address == 0x2000000)
+		bank3_ef = true;
+
+	// Reconfig the system with the new bank0 (and maybe bank1) size.
+	if (bank0_size == 0x10000000)
+		bank1_ef = false;
+	if (bank1_ef == true) {
+		mapMemoryBanks0and1(0, bank0_size, bank0_size, bank0_size);
+		// Fix the PCI bars
+		pci0MapMemoryBanks0_1(0, bank0_size * 2);
+		pci1MapMemoryBanks0_1(0, bank0_size * 2);
+		total_size += bank0_size * 2;
+	} else {
+		mapMemoryBanks0and1(0, bank0_size, bank0_size, 0);
+		// Fix the PCI bars
+		pci0MapMemoryBanks0_1(0, bank0_size);
+		pci1MapMemoryBanks0_1(0, bank0_size);
+		total_size += bank0_size;
+	}
+	if (total_size == 0x10000000) {
+		bank2_ef = false;
+		bank3_ef = false;
+	} else {
+		if ((total_size + bank2_size) > 0x10000000) {
+			bank2_size = 0x10000000 - total_size;
+			bank3_ef = false;
+		} else {
+			if (bank3_size + total_size + bank2_size >
+			    0x10000000) {
+				bank3_size =
+				    0x10000000 - (total_size + bank2_size);
+			}
+		}
+	}
+	if (bank2_ef == true) {
+		if (bank3_ef == true) {
+			mapMemoryBanks2and3(total_size, bank2_size,
+					    total_size + bank2_size,
+					    bank3_size);
+			// Fix the PCI bars
+			pci0MapMemoryBanks2_3(total_size,
+					      bank2_size + bank3_size);
+			pci1MapMemoryBanks2_3(total_size,
+					      bank2_size + bank3_size);
+			total_size += (bank2_size + bank3_size);
+		} else {
+			mapMemoryBanks2and3(total_size, bank2_size,
+					    total_size + bank2_size, 0);
+			// Fix the PCI bars
+			pci0MapMemoryBanks2_3(total_size, bank2_size);
+			pci1MapMemoryBanks2_3(total_size, bank2_size);
+			total_size += bank2_size;
+		}
+	} else {
+		mapMemoryBanks2and3(total_size, 0, total_size, 0);
+		pci0MapMemoryBanks2_3(total_size, 0);
+		pci1MapMemoryBanks2_3(total_size, 0);
+	}
+	/* Reorganize the devices memory map */
+	mapDevices0_1and2MemorySpace(0x1c000000, 0x800000, 0x1a000000,
+				     0xc00000, 0x1d000000, 0x800000);
+
+	XferToRam();
+	return 0;		// Not that we'll ever get to this line of code, but
+	// it does satisfy a compiler warning.
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/fixit linux/arch/mips/galileo-boards/ev64120/compressed/fixit
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/fixit	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/fixit	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,17 @@
+#!/bin/ksh
+
+# By RidgeRun Inc.
+#
+# The input to this script is
+# intended to be a *.S file which
+# was previously created by the doit
+# program. That program constructs
+# a *.S file which has a defined data
+# table containing values with leading
+# zeroes. To satisfy our assembler those
+# leading zeroes need to be stripped off
+# and that is the purpose of this script.
+
+echo "Removing leading zeros"
+sed -e "s/ 0\(.\)/ \1/g" $1 | sed -e "s/ 0\(.\)/ \1/g" > $1.new
+mv $1.new $1
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/flashdrv.c linux/arch/mips/galileo-boards/ev64120/compressed/flashdrv.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/flashdrv.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/flashdrv.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,1560 @@
+/* flashdrv.c - FLASH memory functions and definitions*/
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This flash driver gives the user a convenient interface to FLASH memory located
+on the user`s board, it supports various layout configurations such as:
+1. One pure 8 bit device (Such as AMD`s AM29LV040B).
+2. 1,2,4 or 8 devices 16 bit wide configured to operate in 8 bit mode.
+3. 1,2 or 4 devices each 16 bit wide.
+Before using the driver you must call the initialization function at least once
+or when ever you are changing the FLASH base address.
+The list bellow contains the supported FLASH memory devices, new devices can be
+added easily in the future.
+*/
+
+/*includes*/
+#ifdef __linux__
+#include <asm/galileo-boards/evb64120A/flashdrv.h>
+#else
+#include "flashdrv.h"
+#endif
+/* locals */
+
+#ifdef __MIPSEB__		// skranz, add
+#define BE			// skranz, add
+#endif				// skranz, add
+
+/******************************************************************************
+* Those two tables contain the supported flash devices information needed by
+* the driver: 
+* The first table "flashParametrs" starts with 10 shared fields 
+*  (currently 6 are reserved):
+*   index 0 => Pointer to an entry in the second table list
+*   index 1 => baseAddress - Flash memory device base address.
+*   index 2 => width - 1, 2, 4 or 8 Bytes. 
+*   index 3 => mode - PURE8, X8 or X16 flash configuration (for X16 devices only)
+* The second table (flashTypes) contains: 
+* Entry`s structure:
+*   Manufacture ID,Device ID,number of sectors,list of sector`s sizes
+*   (in Kbytes starting with sector number 0).
+* The end of the list is pointed with a zero.
+******************************************************************************/
+unsigned int flashParametrs[10];	/* 0  Entry pointer */
+				 /* 0  Base address  */
+				 /* 0  Width         */
+				 /* 0  Mode          */
+				 /* 0,0,0,0,0,0, spare entries. */
+unsigned int flashTypes[] = {
+
+	/* 0 */ AMD_FLASH, AM29F400BB, 11, 16, 8, 8, 32, 64, 64, 64, 64,
+	    64, 64, 64,
+	/* 1 */ AMD_FLASH, AM29F400BT, 11, 64, 64, 64, 64, 64, 64, 64, 32,
+	    8, 8, 16,
+	/* 2 */ ST_FLASH, M29W040, 8, 64, 64, 64, 64, 64, 64, 64, 64,
+	/* 3 */ AMD_FLASH, AM29LV040B, 8, 64, 64, 64, 64, 64, 64, 64, 64,
+	/* 4 */ AMD_FLASH, AM29LV800BT, 19, 64, 64, 64, 64, 64, 64, 64, 64,
+	    64, 64,
+	64, 64, 64, 64, 64, 32, 8, 8, 16,
+	/* 5 */ INTEL_FLASH, I28F320J3A, 32, 128, 128, 128, 128, 128, 128,
+	    128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128,
+	/* 6 */ INTEL_FLASH, I28F640J3A, 64, 128, 128, 128, 128, 128, 128,
+	    128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128,
+	/* 7 */ INTEL_FLASH, I28F128J3A, 128, 128, 128, 128, 128, 128, 128,
+	    128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
+	/* 8 */ AMD_FLASH, AM29LV400BB, 11, 16, 8, 8, 32, 64, 64, 64, 64,
+	    64, 64, 64,
+	/* 9 */ AMD_FLASH, AM29LV400BT, 11, 64, 64, 64, 64, 64, 64, 64, 32,
+	    8, 8, 16,
+	/* 10 */ INTEL_FLASH, I28F320B3_T, 71, 64, 64, 64, 64, 64, 64, 64,
+	    64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 8, 8, 8, 8, 8, 8, 8, 8,
+	/* 11 */ INTEL_FLASH, I28F320B3_B, 71, 8, 8, 8, 8, 8, 8, 8, 8, 64,
+	    64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	/* 12 */ INTEL_FLASH, I28F160B3_B, 39, 8, 8, 8, 8, 8, 8, 8, 8, 64,
+	    64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64,
+	/* 13 */ INTEL_FLASH, I28F160B3_T, 39, 64, 64, 64, 64, 64, 64, 64,
+	    64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+	64, 64, 8, 8, 8, 8, 8, 8, 8, 8,
+
+	0			/* End of list indicator */
+};
+
+/********************************************************************
+* flashInit - Initializes the FLASH memory driver`s parameters, this function 
+*             must be called at least once before using the FLASH memory.
+*             If you are changing the FLASH base address call this function
+*             again.
+*
+* INPUTS:     unsigned int flashBaseAddress - The flash base Address.
+*             unsigned int flashWidth - Flash bus width in Bytes: 1,2,4 or 8.
+*             flashMode - PURE8, X8 or X16. 
+* RETURNS:    Flash Size, zero when operation (flashInit) failed.
+*********************************************************************/
+unsigned int flashInit(unsigned int flashBaseAddress,
+		       unsigned int flashWidth, FLASHmode flashMode)
+{
+	unsigned short mfrId = 0;
+	unsigned short devId = 0xffff;
+	unsigned int FirstAddr, SecondAddr, ThirdAddr;
+	unsigned int pArray = 0;
+	unsigned int counter;
+	unsigned int flashSize = 0;
+
+	/* update the list with relevant parametrs */
+	flashParametrs[0] = 0;	/* Default initialization */
+	flashParametrs[1] = flashBaseAddress;
+	flashParametrs[2] = flashWidth;
+	flashParametrs[3] = flashMode;
+	/* Get the FLASH`s ID */
+	switch (FLASH_WIDTH) {
+	case 1:
+		/* AMD or ST ?? * */
+		if (flashMode == PURE8) {	/* Boot Flash */
+			FirstAddr = 0x5555;
+			SecondAddr = 0x2aaa;
+			ThirdAddr = 0x5555;
+		} else {	/* X16 device configured to 8bit Mode */
+
+			FirstAddr = 0xaaaa;
+			SecondAddr = 0x5555;
+			ThirdAddr = 0xaaaa;
+		}
+		flashReset();
+		WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xAA);
+		WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+		WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0x90);
+		READ_CHAR(FLASH_BASE_ADDRESS + 0x0, &mfrId);
+		if (mfrId == AMD_FLASH || mfrId == ST_FLASH) {
+			flashReset();
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xAA);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0x90);
+			READ_CHAR(FLASH_BASE_ADDRESS + 0x1, &devId);
+			break;
+		}
+		/* Micron or Intel ?? * */
+		WRITE_CHAR(FLASH_BASE_ADDRESS, 0xff);	/* Read Array */
+		/* Flash reset for Intel/Micron */
+		WRITE_CHAR(FLASH_BASE_ADDRESS, 0x90);	/* IDENTIFY Device */
+		READ_CHAR(FLASH_BASE_ADDRESS + 0x0, &mfrId);	/*Address for ManufactureID */
+		if (mfrId == INTEL_FLASH || mfrId == MICRON_FLASH) {
+			WRITE_CHAR(FLASH_BASE_ADDRESS, 0xff);	/* Read Array */
+			/*Flash reset for Intel/Micron */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, 0x90);	/* IDENTIFY Device */
+			READ_CHAR(FLASH_BASE_ADDRESS + 0x1, &devId);	/*Address for DeviceID */
+		}
+		break;
+	case 2:
+	case 4:
+	case 8:
+		/* AMD or ST ??? */
+		flashReset();
+		WRITE_SHORT(FLASH_BASE_ADDRESS + 0x5555 * FLASH_WIDTH,
+			    0xaa);
+		WRITE_SHORT(FLASH_BASE_ADDRESS + 0x2aaa * FLASH_WIDTH,
+			    0x55);
+		WRITE_SHORT(FLASH_BASE_ADDRESS + 0x5555 * FLASH_WIDTH,
+			    0x90);
+		READ_SHORT(FLASH_BASE_ADDRESS, &mfrId);
+		flashReset();
+		/* Read the device ID */
+		if (mfrId == AMD_FLASH || mfrId == ST_FLASH) {
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    0x5555 * FLASH_WIDTH, 0xaa);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    0x2aaa * FLASH_WIDTH, 0x55);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    0x5555 * FLASH_WIDTH, 0x90);
+			READ_SHORT(FLASH_BASE_ADDRESS + 0x1 * FLASH_WIDTH,
+				   &devId);
+			break;
+		}
+		/* Micron or Intel ?? * */
+		WRITE_WORD(FLASH_BASE_ADDRESS, 0x00ff00ff);
+		WRITE_WORD(FLASH_BASE_ADDRESS, 0x00900090);
+		if ((FLASH_WIDTH == 4) || (FLASH_WIDTH == 8)) {	/* 32 or 64 bit */
+			READ_SHORT(FLASH_BASE_ADDRESS, &mfrId);
+		} else {	/* FLASH_WIDTH = 2 */
+
+			READ_SHORT(FLASH_BASE_ADDRESS, &mfrId);
+		}
+		if ((mfrId == INTEL_FLASH) || (mfrId == MICRON_FLASH)) {
+			/* Flash reset for Intel/Micron */
+			flashReset();
+			WRITE_WORD(FLASH_BASE_ADDRESS, 0x00ff00ff);
+			WRITE_WORD(FLASH_BASE_ADDRESS, 0x00900090);
+			READ_SHORT(FLASH_BASE_ADDRESS + 0x1 * FLASH_WIDTH,
+				   &devId);
+		}
+		break;
+
+	}
+	/* Try to locate the device in the supported flashes list (FLASH_TYPE). 
+	   according to the keys: 
+	   1) mfrId - manufactor ID.
+	   2) devId - device ID.  
+	 */
+
+	while (true) {
+		if (flashTypes[pArray] == 0) {
+			flashReset();
+			return 0;	/* Device not in the list */
+		}
+		if ((flashTypes[pArray] == mfrId) &&
+		    (flashTypes[pArray + 1] == devId)) {
+			POINTER_TO_FLASH = pArray;
+			for (counter = 0;
+			     counter < flashTypes[NUMBER_OF_SECTORS];
+			     counter++) {
+				flashSize =
+				    flashSize +
+				    flashTypes[FIRST_SECTOR_SIZE +
+					       counter];
+			}
+			if (FLASH_MODE != PURE8) {
+				flashReset();
+				return (flashSize * _1K *
+					(FLASH_WIDTH / (FLASH_MODE / 8)));
+			} else {
+				flashReset();
+				return (flashSize * _1K * FLASH_WIDTH);
+			}
+		}
+		pArray += (3 + flashTypes[pArray + 2]);	/* Move to next entry */
+	}
+}
+
+/********************************************************************
+* flashReset - Resets the Flash memory (FLASH`s internal protocol reset).
+*                
+* INTPUTS:  N/A    
+* OUTPUT:   N/A  
+*********************************************************************/
+void flashReset()
+{
+	unsigned char ucData;
+	unsigned short usData;
+	unsigned int uiData;
+
+	if ((flashTypes[POINTER_TO_FLASH] == AMD_FLASH) ||
+	    (flashTypes[POINTER_TO_FLASH]) == ST_FLASH) {
+		if (FLASH_MODE == X16) {
+			ucData = 0xf0;
+			usData = 0xf0;
+			uiData = 0x00f000f0;
+		} else {	/* case of PURE8 or X8 */
+
+			ucData = 0xf0;
+			usData = 0xf0f0;
+			uiData = 0xf0f0f0f0;
+		}
+	} else {
+		if (FLASH_MODE == X16) {
+			ucData = 0xff;
+			usData = 0xff;
+			uiData = 0x00ff00ff;
+		} else {	/* case of PURE8 or X8 */
+
+			ucData = 0xff;
+			usData = 0xffff;
+			uiData = 0xffffffff;
+		}
+	}
+	switch (FLASH_WIDTH) {
+	case 1:
+		WRITE_CHAR(FLASH_BASE_ADDRESS, ucData);
+		break;
+	case 2:
+		WRITE_SHORT(FLASH_BASE_ADDRESS, usData);
+		break;
+	case 4:
+		WRITE_WORD(FLASH_BASE_ADDRESS, uiData);
+		break;
+	case 8:
+		WRITE_WORD(FLASH_BASE_ADDRESS, uiData);
+		WRITE_WORD(FLASH_BASE_ADDRESS + 0x4, uiData);
+		break;
+	}
+}
+
+/********************************************************************
+* flashErase - The function erases the WHOLE flash memory.
+*
+*
+* RETURNS: true on success,false on failure
+*********************************************************************/
+bool flashErase()
+{
+	unsigned int totalFlashSize;
+	unsigned int address;
+	unsigned int readData;
+	unsigned int nextSector;
+
+	flashReset();
+	totalFlashSize = flashGetSize();
+	/* scan all flash memory space. */
+	address = 0;
+	while (address < totalFlashSize) {
+		readData = flashReadWord(address);
+		if (readData != 0xffffffff) {	/* offset with dirty data. */
+			flashEraseSector(flashInWhichSector(address));
+			nextSector = flashInWhichSector(address) + 1;
+			if (nextSector < flashTypes[NUMBER_OF_SECTORS])
+				/* jump to next sector. */
+				address = flashGetSectorOffset(nextSector);
+			else
+				/* end of erasing. */
+				address = totalFlashSize;
+		} else
+			address += 4;
+	}
+	return true;
+}
+
+/********************************************************************
+* flashEraseSector - The function erases a specific sector in the flash memory.
+*
+* INPUTS:  Sector number.
+* RETURNS: true on success,false on failure.
+*********************************************************************/
+bool flashEraseSector(unsigned int sectorNumber)
+{
+	volatile unsigned int spin;
+	unsigned int regValue;
+	unsigned int sectorBaseAddress = 0;
+	unsigned int i;
+	unsigned int data20, dataD0, data70;
+	unsigned int dataPoll;
+	unsigned int FirstAddr, SecondAddr, ThirdAddr, FourthAddr,
+	    FifthAddr;
+	unsigned int FirstData, SecondData, ThirdData;
+	unsigned int FourthData, FifthData, SixthData;
+
+	/* calculate the sector base Address according to the following parametrs:
+	   1: FLASH_WIDTH
+	   2: the size of each sector which it detailed in the table */
+
+	/* checking the if the sectorNumber is legal. */
+	if (sectorNumber > flashTypes[NUMBER_OF_SECTORS] - 1)
+		return false;
+	/* now the calculation begining of the sector Address */
+	for (i = 0; i < sectorNumber; i++) {
+		sectorBaseAddress =
+		    sectorBaseAddress + flashTypes[FIRST_SECTOR_SIZE + i];
+	}
+	/* In case of X8 wide the address should be */
+	if (FLASH_MODE == PURE8)
+		sectorBaseAddress = _1K * sectorBaseAddress;
+	if (FLASH_MODE == X8)
+		sectorBaseAddress = _1K * sectorBaseAddress;
+	/* In case of X16 wide the address should be */
+	if (FLASH_MODE == X16)
+		sectorBaseAddress = _1K * sectorBaseAddress / 2;
+	flashReset();
+	if ((flashTypes[POINTER_TO_FLASH] == AMD_FLASH) || \
+	    (flashTypes[POINTER_TO_FLASH] == ST_FLASH)) {
+		switch (FLASH_WIDTH) {
+		case 1:
+			if (FLASH_MODE == PURE8) {	/* Boot Flash PURE8 */
+				FirstAddr = 0x5555;
+				SecondAddr = 0x2aaa;
+				ThirdAddr = 0x5555;
+				FourthAddr = 0x5555;
+				FifthAddr = 0x2aaa;
+			} else {
+				FirstAddr = 0xaaaa;
+				SecondAddr = 0x5555;
+				ThirdAddr = 0xaaaa;
+				FourthAddr = 0xaaaa;
+				FifthAddr = 0x5555;
+			}
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xAA);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0x80);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FourthAddr, 0xAA);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FifthAddr, 0x55);
+			WRITE_CHAR(
+				   (FLASH_BASE_ADDRESS +
+				    (sectorBaseAddress & 0xffffff00)),
+				   0x30);
+			/* Poll on the flash */
+			do {
+				READ_CHAR(FLASH_BASE_ADDRESS +
+					  sectorBaseAddress, &regValue);
+			} while ((regValue & 0x80) != 0x80);
+
+			break;
+		case 2:
+			if (FLASH_MODE == X16) {
+				FirstData = 0xaa;	/* Data for the First  Cycle */
+				SecondData = 0x55;	/* Data for the Second Cycle */
+				ThirdData = 0x80;	/* Data for the Third  Cycle */
+				FourthData = 0xaa;	/* Data for the Fourth Cycle */
+				FifthData = 0x55;	/* Data for the Fifth  Cycle */
+				SixthData = 0x30;	/* Data for the Sixth  Cycle */
+				FirstAddr = 0x5555;	/* Address for the First  Cycle */
+				SecondAddr = 0x2aaa;	/* Address for the Second Cycle */
+				ThirdAddr = 0x5555;	/* Address for the Third  Cycle */
+				FourthAddr = 0x5555;	/* Address for the Fourth Cycle */
+				FifthAddr = 0x2aaa;	/* Address for the Fifth  Cycle */
+			} else {	/* (FLASH_MODE = 8) */
+
+				FirstData = 0xaaaa;	/* Data for the First  Cycle */
+				SecondData = 0x5555;	/* Data for the Second Cycle */
+				ThirdData = 0x8080;	/* Data for the Third  Cycle */
+				FourthData = 0xaaaa;	/* Data for the Fourth Cycle */
+				FifthData = 0x5555;	/* Data for the Fifth  Cycle */
+				SixthData = 0x3030;	/* Data for the Sixth  Cycle */
+				FirstAddr = 0xaaaa;	/* Address for the First  Cycle */
+				SecondAddr = 0x5555;	/* Address for the Second Cycle */
+				ThirdAddr = 0xaaaa;	/* Address for the Third  Cycle */
+				FourthAddr = 0xaaaa;	/* Address for the Fourth Cycle */
+				FifthAddr = 0x5555;	/* Address for the Fifth  Cycle */
+			}
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    FirstAddr * FLASH_WIDTH, FirstData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    SecondAddr * FLASH_WIDTH, SecondData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    ThirdAddr * FLASH_WIDTH, ThirdData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    FourthAddr * FLASH_WIDTH, FourthData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    FifthAddr * FLASH_WIDTH, FifthData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    (sectorBaseAddress & 0xffffff00) *
+				    FLASH_WIDTH, SixthData);
+			/* Poll on the flash */
+			if (FLASH_MODE == X16) {	/* 1 device of 16 bit */
+				dataPoll = 0x0080;
+			} else {	/* (FLASH_MODE = 8) ==> 2 devices , 8 bit each => 16bit */
+
+				dataPoll = 0x8080;
+			}
+			do {
+				READ_SHORT(FLASH_BASE_ADDRESS +
+					   sectorBaseAddress * FLASH_WIDTH,
+					   &regValue);
+				for (spin = 0; spin < 100; spin++) {
+				}	// skranz, added spin loop.
+			} while ((regValue & dataPoll) != dataPoll);
+			break;
+		case 4:
+			if (FLASH_MODE == X16) {
+				FirstData = 0x00aa00aa;	/* Data for the First  Cycle */
+				SecondData = 0x00550055;	/* Data for the Second Cycle */
+				ThirdData = 0x00800080;	/* Data for the Third  Cycle */
+				FourthData = 0x00aa00aa;	/* Data for the Fourth Cycle */
+				FifthData = 0x00550055;	/* Data for the Fifth  Cycle */
+				SixthData = 0x00300030;	/* Data for the Sixth  Cycle */
+				FirstAddr = 0x5555;	/* Address for the First  Cycle */
+				SecondAddr = 0x2aaa;	/* Address for the Second Cycle */
+				ThirdAddr = 0x5555;	/* Address for the Third  Cycle */
+				FourthAddr = 0x5555;	/* Address for the Fourth Cycle */
+				FifthAddr = 0x2aaa;	/* Address for the Fifth  Cycle */
+			} else {	/* if (FLASH_MODE == 8) */
+
+				FirstData = 0xaaaaaaaa;	/* Data for the First  Cycle */
+				SecondData = 0x55555555;	/* Data for the Second Cycle */
+				ThirdData = 0x80808080;	/* Data for the Third  Cycle */
+				FourthData = 0xAAAAAAAA;	/* Data for the Fourth Cycle */
+				FifthData = 0x55555555;	/* Data for the Fifth  Cycle */
+				SixthData = 0x30303030;	/* Data for the Sixth  Cycle */
+				FirstAddr = 0xaaaa;	/* Address for the First  Cycle */
+				SecondAddr = 0x5555;	/* Address for the Second Cycle */
+				ThirdAddr = 0xaaaa;	/* Address for the Third  Cycle */
+				FourthAddr = 0xaaaa;	/* Address for the Fourth Cycle */
+				FifthAddr = 0x5555;	/* Address for the Fifth  Cycle */
+			}
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FirstAddr * FLASH_WIDTH, FirstData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   SecondAddr * FLASH_WIDTH, SecondData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   ThirdAddr * FLASH_WIDTH, ThirdData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FourthAddr * FLASH_WIDTH, FourthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FifthAddr * FLASH_WIDTH, FifthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   (sectorBaseAddress & 0xffffff00) *
+				   FLASH_WIDTH, SixthData);
+			/* Poll on the flash */
+			if (FLASH_MODE == X16) {	/* 4 devices , 16 bit each => 64bit */
+				dataPoll = 0x00800080;
+			} else {	/* (FLASH_MODE = 8) ==> 8 devices , 8 bit each => 64bit */
+
+				dataPoll = 0x80808080;
+			}
+			do {
+				READ_WORD(FLASH_BASE_ADDRESS +
+					  sectorBaseAddress * FLASH_WIDTH,
+					  &regValue);
+			} while ((regValue & dataPoll) != dataPoll);
+			break;
+		case 8:	/* In case of 64bit width the transformation is 1->8 */
+			if (FLASH_MODE == X16) {
+				FirstData = 0x00aa00aa;	/* Data for the First  Cycle */
+				SecondData = 0x00550055;	/* Data for the Second Cycle */
+				ThirdData = 0x00800080;	/* Data for the Third  Cycle */
+				FourthData = 0x00aa00aa;	/* Data for the Fourth Cycle */
+				FifthData = 0x00550055;	/* Data for the Fifth  Cycle */
+				SixthData = 0x00300030;	/* Data for the Sixth  Cycle */
+				FirstAddr = 0x5555;	/* Address for the First  Cycle */
+				SecondAddr = 0x2aaa;	/* Address for the Second Cycle */
+				ThirdAddr = 0x5555;	/* Address for the Third  Cycle */
+				FourthAddr = 0x5555;	/* Address for the Fourth Cycle */
+				FifthAddr = 0x2aaa;	/* Address for the Fifth  Cycle */
+			} else {	/* (FLASH_MODE = 8 */
+
+				FirstData = 0xaaaaaaaa;	/* Data for the First  Cycle */
+				SecondData = 0x55555555;	/* Data for the Second Cycle */
+				ThirdData = 0x80808080;	/* Data for the Third  Cycle */
+				FourthData = 0xAAAAAAAA;	/* Data for the Fourth Cycle */
+				FifthData = 0x55555555;	/* Data for the Fifth  Cycle */
+				SixthData = 0x30303030;	/* Data for the Sixth  Cycle */
+				FirstAddr = 0xaaaa;	/* Address for the First  Cycle */
+				SecondAddr = 0x5555;	/* Address for the Second Cycle */
+				ThirdAddr = 0xaaaa;	/* Address for the Third  Cycle */
+				FourthAddr = 0xaaaa;	/* Address for the Fourth Cycle */
+				FifthAddr = 0x5555;	/* Address for the Fifth  Cycle */
+			}
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FirstAddr * FLASH_WIDTH, FirstData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   SecondAddr * FLASH_WIDTH, SecondData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   ThirdAddr * FLASH_WIDTH, ThirdData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FourthAddr * FLASH_WIDTH, FourthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FifthAddr * FLASH_WIDTH, FifthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   (sectorBaseAddress & 0xffffff00) *
+				   FLASH_WIDTH, SixthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FirstAddr * FLASH_WIDTH + 4, FirstData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   SecondAddr * FLASH_WIDTH + 4,
+				   SecondData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   ThirdAddr * FLASH_WIDTH + 4, ThirdData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FourthAddr * FLASH_WIDTH + 4,
+				   FourthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   FifthAddr * FLASH_WIDTH + 4, FifthData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   (sectorBaseAddress & 0xffffff00)
+				   * FLASH_WIDTH + 4, SixthData);
+			/* Poll on the flash */
+			if (FLASH_MODE == X16) {	/* 4 devices , 16 bit each => 64bit */
+				dataPoll = 0x00800080;
+			} else {	/* (FLASH_MODE = 8) ==> 8 devices , 8 bit each => 64bit */
+
+				dataPoll = 0x80808080;
+			}
+			do {
+				READ_WORD(FLASH_BASE_ADDRESS +
+					  sectorBaseAddress * FLASH_WIDTH,
+					  &regValue);
+			} while ((regValue & dataPoll) != dataPoll);
+			do {
+				READ_WORD(FLASH_BASE_ADDRESS +
+					  sectorBaseAddress * FLASH_WIDTH +
+					  4, &regValue);
+			} while ((regValue & dataPoll) != dataPoll);
+			break;
+		default:
+			return false;
+		}
+	} /* End of 'flash erase sector' for AMD/ST */
+	else {			/* Intel/Micron */
+
+		switch (FLASH_WIDTH) {
+		case 1:
+			WRITE_CHAR(FLASH_BASE_ADDRESS, 0x20);
+			WRITE_CHAR(
+				   (FLASH_BASE_ADDRESS +
+				    (sectorBaseAddress & 0xffffff00)),
+				   0xd0);
+			/* Poll on the flash */
+			while (true) {
+				WRITE_CHAR(FLASH_BASE_ADDRESS, 0x70);
+				READ_CHAR(FLASH_BASE_ADDRESS, &regValue);
+				if ((regValue & 0x80) == 0x80)
+					break;
+			}
+			break;
+		case 2:
+			if (FLASH_MODE == X16) {	/* 1 device 16 bit.  */
+				data20 = 0x0020;;
+				dataD0 = 0x00d0;;
+			} else {	/* (FLASH_MODE = 8) ==> 2 devices , 8 bit each => 16bit */
+
+				data20 = 0x2020;
+				dataD0 = 0xd0d0;
+			}
+			WRITE_SHORT(FLASH_BASE_ADDRESS, data20);
+			WRITE_SHORT(
+				    (FLASH_BASE_ADDRESS +
+				     ((sectorBaseAddress * 2) &
+				      0xffffff00)), dataD0);
+			/* Poll on the flash */
+			if (FLASH_MODE == X16) {
+				dataPoll = 0x0080;
+				data70 = 0x0070;
+			} else {	/* (FLASH_MODE = 8) */
+
+				dataPoll = 0x8080;
+				data70 = 0x7070;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS +
+					    sectorBaseAddress * 2, data70);
+				READ_SHORT(FLASH_BASE_ADDRESS +
+					   sectorBaseAddress * 2,
+					   &regValue);
+				if ((regValue & 0x0080) == 0x0080)
+					break;
+			}
+			break;
+		case 4:
+			if (FLASH_MODE == X16) {	/* 2 devices , 16 bit each => 32bit */
+				data20 = 0x00200020;
+				dataD0 = 0x00d000d0;
+			} else {	/* (FLASH_MODE = 8) ==> 4 devices , 8 bit each => 32bit */
+
+				data20 = 0x20202020;
+				dataD0 = 0xd0d0d0d0;
+			}
+			WRITE_WORD(FLASH_BASE_ADDRESS, data20);
+			WRITE_WORD(
+				   (FLASH_BASE_ADDRESS +
+				    ((sectorBaseAddress * 4) &
+				     0xffffff00)), dataD0);
+			/* Poll on the flash */
+			if (FLASH_MODE == X16) {
+				dataPoll = 0x0080;
+				data70 = 0x0070;
+			} else {	/* (FLASH_MODE = 8) */
+
+				dataPoll = 0x8080;
+				data70 = 0x7070;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS, data70);
+				READ_SHORT(FLASH_BASE_ADDRESS, &regValue);
+				if ((regValue & dataPoll) == dataPoll)
+					break;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS + 2,
+					    data70);
+				READ_SHORT(FLASH_BASE_ADDRESS + 2,
+					   &regValue);
+				if ((regValue & dataPoll) == dataPoll)
+					break;
+			}
+			break;
+		case 8:
+			if (FLASH_MODE == X16) {	/* 4 devices , 16 bit each => 64bit */
+				data20 = 0x00200020;
+				dataD0 = 0x00d000d0;
+			} else {	/* (FLASH_MODE = 8) ==> 8 devices , 8 bit each => 64bit */
+
+				data20 = 0x20202020;
+				dataD0 = 0xd0d0d0d0;
+			}
+			WRITE_WORD(FLASH_BASE_ADDRESS, data20);
+			WRITE_WORD(
+				   (FLASH_BASE_ADDRESS +
+				    ((sectorBaseAddress * 8) &
+				     0xffffff00)), dataD0);
+			WRITE_WORD(FLASH_BASE_ADDRESS + 4, data20);
+			WRITE_WORD(
+				   (FLASH_BASE_ADDRESS +
+				    ((sectorBaseAddress * 8) & 0xffffff00 +
+				     4)), dataD0);
+			/* Poll on the flash */
+			if (FLASH_MODE == X16) {
+				dataPoll = 0x0080;
+				data70 = 0x0070;
+			} else {	/* (FLASH_MODE = 8) */
+
+				dataPoll = 0x8080;
+				data70 = 0x7070;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS +
+					    sectorBaseAddress * 8, data70);
+				READ_SHORT(FLASH_BASE_ADDRESS +
+					   sectorBaseAddress * 8,
+					   &regValue);
+				if ((regValue & dataPoll) == dataPoll)
+					break;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS + 2,
+					    data70);
+				READ_SHORT(FLASH_BASE_ADDRESS + 2,
+					   &regValue);
+				if ((regValue & dataPoll) == dataPoll)
+					break;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS + 4,
+					    data70);
+				READ_SHORT(FLASH_BASE_ADDRESS + 4,
+					   &regValue);
+				if ((regValue & dataPoll) == dataPoll)
+					break;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS + 6,
+					    data70);
+				READ_SHORT(FLASH_BASE_ADDRESS + 6,
+					   &regValue);
+				if ((regValue & dataPoll) == dataPoll)
+					break;
+			}
+			break;
+		default:
+			return false;
+		}
+	}
+	flashReset();
+	return true;
+}
+
+/********************************************************************
+* flashWriteWord - Write 32Bit to the FLASH memory at the given offset from the
+*                  FLASH base address.
+*   			   address 0 = 0x00000000 !!
+*				   Attention!!! data "0" cannot be programed back to 
+*                  "1" (only by first performing an earase operation).
+*                  The function takes care of Big/Little endian conversion
+*
+* INPUTS:  offset - The offset from the flash`s base address.
+*          data   - The data that should be written.
+* RETURNS: true on success,false on failure
+*********************************************************************/
+bool flashWriteWord(unsigned int offset, unsigned int data)
+{
+	unsigned char c, rc;
+	unsigned short s, rs;
+	register unsigned int rw;
+	register unsigned int regValue;
+	register unsigned int FirstAddr, SecondAddr, ThirdAddr;
+	register unsigned int FirstData, SecondData, ThirdData;
+	register unsigned int data10, data20, data70, data80;
+
+	if ((flashTypes[POINTER_TO_FLASH] == AMD_FLASH) || \
+	    (flashTypes[POINTER_TO_FLASH] == ST_FLASH)) {
+		switch (FLASH_WIDTH) {
+		case 1:	/* Split the 32 bit write into four 8bit Writings */
+			if (FLASH_MODE == PURE8) {	/* Boot Flash */
+				FirstAddr = 0x5555;
+				SecondAddr = 0x2aaa;
+				ThirdAddr = 0x5555;
+			} else {
+				FirstAddr = 0xaaaa;
+				SecondAddr = 0x5555;
+				ThirdAddr = 0xaaaa;
+			}
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
+#ifdef BE
+			c = (data >> 24);
+#else
+			c = data;
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset, c);
+			/* Writing first Byte */
+			while (true) {
+				READ_CHAR(FLASH_BASE_ADDRESS + offset,
+					  &rc);
+				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
+					break;	/* DQ7 =  DATA */
+				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
+					READ_CHAR(FLASH_BASE_ADDRESS +
+						  offset, &rc);
+					if ((rc & 0x80) == (c & 0x80))
+						break;	/* DQ7 = DATA  */
+					else
+						return false;	/* DQ7 != DATA */
+				}
+			}
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
+#ifdef BE
+			c = (data >> 16);
+#else
+			c = (data >> 8);
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 1, c);
+			/* Writing second Byte */
+			while (true) {
+				READ_CHAR(FLASH_BASE_ADDRESS + offset + 1,
+					  &rc);
+				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
+					break;	/* DQ7 = DATA  */
+				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
+					READ_CHAR(FLASH_BASE_ADDRESS +
+						  offset + 1, &rc);
+					if ((rc & 0x80) == (c & 0x80))
+						break;	/* DQ7 = DATA  */
+					else
+						return false;	/* DQ7 != DATA */
+				}
+			}
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
+#ifdef BE
+			c = (data >> 8);
+#else
+			c = (data >> 16);
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 2, c);
+			/* Writing third Byte */
+			while (true) {
+				READ_CHAR(FLASH_BASE_ADDRESS + offset + 2,
+					  &rc);
+				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
+					break;	/* DQ7 = DATA  */
+				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
+					READ_CHAR(FLASH_BASE_ADDRESS +
+						  offset + 2, &rc);
+					if ((rc & 0x80) == (c & 0x80))
+						break;	/* DQ7 = DATA  */
+					else
+						return false;	/* DQ7 != DATA */
+				}
+			}
+			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
+			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
+#ifdef BE
+			c = data;
+#else
+			c = (data >> 24);
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 3, c);
+			/* Writing fourth Byte */
+			while (true) {
+				READ_CHAR(FLASH_BASE_ADDRESS + offset + 3,
+					  &rc);
+				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
+					break;	/* DQ7 = DATA  */
+				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
+					READ_CHAR(FLASH_BASE_ADDRESS +
+						  offset + 3, &rc);
+					if ((rc & 0x80) == (c & 0x80))
+						break;	/* DQ7 = DATA  */
+					else
+						return false;	/* DQ7 != DATA */
+				}
+			}
+			break;
+		case 2:	/* Split the 32 bit write into two 8/16 bit Writings 
+				   (16bit width). */
+			if (FLASH_MODE == X16) {
+				FirstData = 0xaa;	/* Data for the First  Cycle    */
+				SecondData = 0x55;	/* Data for the Second Cycle    */
+				ThirdData = 0xa0;	/* Data for the Third  Cycle    */
+				FirstAddr = 0x5555;	/* Address for the First  Cycle */
+				SecondAddr = 0x2aaa;	/* Address for the Second Cycle */
+				ThirdAddr = 0x5555;	/* Address for the Third  Cycle */
+			} else {	/* if (FLASH_MODE == 8) */
+
+				FirstData = 0xaaaa;	/* Data for the First  Cycle    */
+				SecondData = 0x5555;	/* Data for the Second Cycle    */
+				ThirdData = 0xa0a0;	/* Data for the Third  Cycle    */
+				FirstAddr = 0xaaaa;	/* Address for the First  Cycle */
+				SecondAddr = 0x5555;	/* Address for the Second Cycle */
+				ThirdAddr = 0xaaaa;	/* Address for the Third  Cycle */
+			}
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    FirstAddr * FLASH_WIDTH, FirstData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    SecondAddr * FLASH_WIDTH, SecondData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    ThirdAddr * FLASH_WIDTH, ThirdData);
+#ifdef BE
+			s = (data >> 16);
+#else
+			s = data;
+#endif
+			WRITE_SHORT(FLASH_BASE_ADDRESS + offset, s);
+			/* Writing Two Bytes */
+			if (FLASH_MODE == X16) {
+				data80 = 0x80;;
+				data20 = 0x20;;
+			} else {	/* if (FLASH_MODE == 8) */
+
+				data80 = 0x8080;
+				data20 = 0x2020;
+			}
+			while (true) {
+				READ_SHORT(FLASH_BASE_ADDRESS + offset,
+					   &rs);
+				if ((rs & data80) == (s & data80))	/* DQ7 =? DATA */
+					break;	/* DQ7 =  DATA */
+				if ((rs & data20) == data20) {	/* DQ5 =? DATA */
+					READ_SHORT(FLASH_BASE_ADDRESS +
+						   offset, &rs);
+					if ((rs & data80) == (s & data80))
+						break;	/* DQ7 = DATA  */
+					else {
+						flashReset();
+						return false;	/* DQ7 != DATA */
+					}
+				}
+			}
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    FirstAddr * FLASH_WIDTH, FirstData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    SecondAddr * FLASH_WIDTH, SecondData);
+			WRITE_SHORT(FLASH_BASE_ADDRESS +
+				    ThirdAddr * FLASH_WIDTH, ThirdData);
+#ifdef BE
+			s = data;
+#else
+			s = (data >> 16);
+#endif
+			WRITE_SHORT(FLASH_BASE_ADDRESS + offset + 2, s);
+			/* Writing Two Bytes */
+			while (true) {
+				READ_SHORT(FLASH_BASE_ADDRESS + offset + 2,
+					   &rs);
+				if ((rs & data80) == (s & data80))	/* DQ7 =? DATA */
+					break;	/* DQ7 =  DATA */
+				if ((rs & data20) == data20) {	/* DQ5 =? '1'  */
+					READ_SHORT(FLASH_BASE_ADDRESS +
+						   offset + 2, &rs);
+					if ((rs & data80) == (s & data80))
+						break;	/* DQ7 = DATA  */
+					else {
+						flashReset();
+						return false;	/* DQ7 != DATA */
+					}
+				}
+			}
+			return true;
+		case 4:
+		case 8:
+			if (FLASH_MODE == X16) {
+				FirstData = 0x00aa00aa;
+				SecondData = 0x00550055;
+				ThirdData = 0x00a000a0;
+				FirstAddr = 0x5555;
+				SecondAddr = 0x2aaa;
+				ThirdAddr = 0x5555;
+			} else {	/* (FLASH_MODE == 8) */
+
+				FirstData = 0xaaaaaaaa;	/* Data for the First  Cycle    */
+				SecondData = 0x55555555;	/* Data for the Second Cycle    */
+				ThirdData = 0xa0a0a0a0;	/* Data for the Third  Cycle    */
+				FirstAddr = 0xaaaaaaaa;	/* Address for the First  Cycle */
+				SecondAddr = 0x55555555;	/* Address for the Second Cycle */
+				ThirdAddr = 0xaaaaaaaa;	/* Address for the Third  Cycle */
+			}
+			WRITE_WORD(FLASH_BASE_ADDRESS + FirstAddr *
+				   FLASH_WIDTH + offset % FLASH_WIDTH,
+				   FirstData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   SecondAddr * FLASH_WIDTH +
+				   offset % FLASH_WIDTH, SecondData);
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   ThirdAddr * FLASH_WIDTH +
+				   offset % FLASH_WIDTH, ThirdData);
+			/* writting the word. */
+			WRITE_WORD(FLASH_BASE_ADDRESS + offset, data);
+			/* preparing the polling patterns. */
+			if (FLASH_MODE == X16) {
+				data80 = 0x00800080;
+				data20 = 0x00200020;
+			} else {	/* (FLASH_MODE == 8) */
+
+				data80 = 0x80808080;
+				data20 = 0x20202020;
+			}
+			while (true) {	/* polling loop. */
+				rw = READWORD(FLASH_BASE_ADDRESS + offset);
+				/* DQ7 =? DATA */
+				if ((rw & data80) == (data & data80))
+					break;	/* DQ7 =  DATA */
+				if ((rw & data20) == data20) {	/* DQ5 =? '1'  */
+					rw =
+					    READWORD(FLASH_BASE_ADDRESS +
+						     offset);
+					if ((rw & data80) ==
+					    (data & data80)) break;	/* DQ7 = DATA  */
+					else
+						return false;	/* DQ7 != DATA */
+				}
+			}
+			return true;
+		default:
+			return false;	/* case of invalid flash Width. */
+		}
+	} else {		/* Intel/Micron */
+
+		switch (FLASH_WIDTH) {
+		case 1:
+			/* Writing First Byte */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, 0x10);
+#ifdef BE
+			c = (data >> 24);
+#else
+			c = data;
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset, c);
+			while (true) {
+				/* Reading STATUS Register */
+				WRITE_CHAR(FLASH_BASE_ADDRESS, 0x70);
+				regValue = READCHAR(FLASH_BASE_ADDRESS);
+				if ((regValue & 0x80) == 0x80)
+					break;	/* Case of Write-Operation had Ended */
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, 0x70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS);
+			if ((regValue & 0x10) == 0x10)
+				return false;	/* Write failure */
+
+			/* Writing Second Byte */
+			WRITE_CHAR(FLASH_BASE_ADDRESS + 1, 0x10);
+#ifdef BE
+			c = (data >> 16);
+#else
+			c = (data >> 8);
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 1, c);
+			while (true) {
+				/* Reading STATUS Register */
+				WRITE_CHAR(FLASH_BASE_ADDRESS + 1, 0x70);
+				regValue =
+				    READCHAR(FLASH_BASE_ADDRESS + 1);
+				if ((regValue & 0x80) == 0x80)
+					break;	/* Write operation ended */
+			}
+			/* Reading STATUS Register for Writing verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS + 1, 0x70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS + 1);
+			if ((regValue & 0x10) == 0x10)
+				return false;	/* Write failure */
+
+			/* Writing Third Byte */
+			WRITE_CHAR(FLASH_BASE_ADDRESS + 2, 0x10);
+#ifdef BE
+			c = (data >> 8);
+#else
+			c = (data >> 16);
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 2, c);
+			while (true) {
+				/* Reading STATUS Register */
+				WRITE_CHAR(FLASH_BASE_ADDRESS + 2, 0x70);
+				regValue =
+				    READCHAR(FLASH_BASE_ADDRESS + 2);
+				if ((regValue & 0x80) == 0x80)
+					break;	/* Write operation ended */
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS + 2, 0x70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS + 2);
+			if ((regValue & 0x10) == 0x10)
+				return false;	/* Write failure */
+
+			/* Writing Fourth Byte */
+			WRITE_CHAR(FLASH_BASE_ADDRESS + 3, 0x10);
+#ifdef BE
+			c = data;
+#else
+			c = (data >> 24);
+#endif
+			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 3, c);
+			while (true) {
+				/* Reading STATUS Register */
+				WRITE_CHAR(FLASH_BASE_ADDRESS + 3, 0x70);
+				regValue =
+				    READCHAR(FLASH_BASE_ADDRESS + 3);
+				if ((regValue & 0x80) == 0x80)
+					break;	/* Write operation ended */
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS + 3, 0x70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS + 3);
+			if ((regValue & 0x10) == 0x10)
+				return false;	/* Write failure */
+			flashReset();
+			return true;
+		case 2:
+			if (FLASH_MODE == X16) {	/* Case of one X16 bit device */
+				FirstData = 0x0010;	/* Data for the First  Cycle  */
+			} else {	/* if (FLASH_MODE == 8) ==> Case of two X8 bit devices */
+
+				FirstData = 0x1010;	/* Data for the First  Cycle  */
+			}
+			/* Writing First two Bytes */
+			WRITE_SHORT(FLASH_BASE_ADDRESS, FirstData);
+#ifdef BE
+			s = (data >> 16);
+#else
+			s = data;
+#endif
+			WRITE_SHORT(FLASH_BASE_ADDRESS + offset, s);
+			if (FLASH_MODE == X16) {
+				data70 = 0x0070;
+				data80 = 0x0080;
+				data10 = 0x0010;
+			} else {	/* case of (FLASH_MODE == X8) */
+
+				data70 = 0x7070;
+				data80 = 0x8080;
+				data10 = 0x1010;
+			}
+			/* polling on writing action => when done break. */
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS, data70);
+				regValue = READSHORT(FLASH_BASE_ADDRESS);
+				if ((regValue & data80) == data80)
+					break;
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, data70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS);
+			if ((regValue & data10) == data10)
+				return false;	/* Write failure */
+			/* Writing Last two Bytes */
+			WRITE_SHORT(FLASH_BASE_ADDRESS + 2, FirstData);
+#ifdef BE
+			s = data;
+#else
+			s = (data >> 16);
+#endif
+			WRITE_SHORT(FLASH_BASE_ADDRESS + offset + 2, s);
+			/* polling on writing action => when done break. */
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS + 2,
+					    data70);
+				regValue =
+				    READSHORT(FLASH_BASE_ADDRESS + 2);
+				if ((regValue & data80) == data80)
+					break;
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, data70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS);
+			if ((regValue & data10) == data10)
+				return false;	/* Write failure */
+			flashReset();
+			return true;
+		case 4:
+		case 8:
+			if (FLASH_MODE == X16) {	/* Case of one X16 bit device */
+				FirstData = 0x00100010;	/* Data for the First  Cycle  */
+			} else {	/* (FLASH_MODE == 8) ==> Case of two X8 bit devices */
+
+				FirstData = 0x10101010;	/* Data for the First  Cycle  */
+			}
+			/* Writing First two Bytes */
+			WRITE_WORD(FLASH_BASE_ADDRESS +
+				   offset % FLASH_WIDTH, FirstData);
+#ifdef BE
+			s = (data >> 16);
+#else
+			s = data;
+#endif
+			/* writing the 32-bit data to flash. */
+			WRITE_WORD(FLASH_BASE_ADDRESS + offset, data);
+			if (FLASH_MODE == X16) {
+				data70 = 0x0070;
+				data80 = 0x0080;
+				data10 = 0x0010;
+			} else {	/* (FLASH_MODE == 8) */
+
+				data70 = 0x7070;
+				data80 = 0x8080;
+				data10 = 0x1010;
+			}
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS +
+					    offset % FLASH_WIDTH, data70);
+				regValue = READSHORT(FLASH_BASE_ADDRESS);
+				if ((regValue & data80) == data80)
+					break;
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, data70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS);
+			if ((regValue & data10) == data10)
+				return false;	/* Write failure */
+
+			/* Writing Last two Bytes */
+#ifdef BE
+			s = data;
+#else
+			s = (data >> 16);
+#endif
+			while (true) {
+				WRITE_SHORT(FLASH_BASE_ADDRESS +
+					    offset % FLASH_WIDTH + 2,
+					    data70);
+				regValue =
+				    READSHORT(FLASH_BASE_ADDRESS +
+					      offset % FLASH_WIDTH + 2);
+				if ((regValue & data80) == data80)
+					break;
+			}
+			/* Reading STATUS Register for Writing Verification */
+			WRITE_CHAR(FLASH_BASE_ADDRESS, data70);
+			regValue = READCHAR(FLASH_BASE_ADDRESS);
+			if ((regValue & data10) == data10)
+				return false;	/* Write failure */
+
+			flashReset();
+			return true;
+		default:
+			flashReset();
+			return false;
+		}
+	}
+	flashReset();
+	return true;
+}
+
+/********************************************************************
+* flashReadWord - Read 32Bit from the FLASH memory at a given offset 
+*                 from the FLASH base address.
+* 				  address 0 = 0x00000000 !!
+*                 The function takes care of Big/Little endian conversion
+* INPUTS:  offset,the offset from the flash`s base address
+* RETURNS: data
+*********************************************************************/
+unsigned int flashReadWord(unsigned int offset)
+{
+	unsigned int regValue;
+	flashReset();
+	READ_WORD(FLASH_BASE_ADDRESS + offset, &regValue);
+	return regValue;
+}
+
+/********************************************************************
+* flashInWhichSector - Returns the sector`s number at which offset is at.
+*
+* INPUTS:  Offset
+* RETURNS: Sector number,or 0xffffffff in case the address is out of range or 
+*          flash wasn't initialize.
+*********************************************************************/
+unsigned int flashInWhichSector(unsigned int offset)
+{
+	unsigned int sectorNumber, numberOfDevices;
+	unsigned int accMemory = 0;
+
+	if ((FLASH_MODE == PURE8) || (FLASH_MODE == X8)) {
+		numberOfDevices = FLASH_WIDTH;
+	} else {		/* X16 mode */
+
+		numberOfDevices = FLASH_WIDTH / 2;
+	}
+	for (sectorNumber = 0;
+	     sectorNumber < flashTypes[NUMBER_OF_SECTORS]; sectorNumber++) {
+		accMemory =
+		    accMemory + flashTypes[FIRST_SECTOR_SIZE +
+					   sectorNumber];
+		if (offset < accMemory * numberOfDevices * 1024)
+			return sectorNumber;
+	}
+	return 0xffffffff;
+}
+
+/********************************************************************
+* flashGetSectorSize - When given a Valid sector Number returns its Size.
+*
+* INPUTS:  unsigned int sectorNumber.
+* RETURNS: Sector size. (if Sector number isn't valid or flash wasn't 
+*          initialize return 0.)
+*********************************************************************/
+unsigned int flashGetSectorSize(unsigned int sectorNumber)
+{
+	if (sectorNumber >= flashTypes[NUMBER_OF_SECTORS])
+		return 0;
+	else {
+		if (FLASH_MODE != PURE8)
+			return (flashTypes
+				[FIRST_SECTOR_SIZE +
+				 sectorNumber] * _1K * (FLASH_WIDTH * 8 /
+							FLASH_MODE));
+		else		/* in case of PUR8 */
+			return (flashTypes
+				[FIRST_SECTOR_SIZE +
+				 sectorNumber] * _1K * FLASH_WIDTH);
+	}
+}
+
+/********************************************************************
+* getFlashSize - Return Total flash size.
+*
+* INPUTS:  N/A.
+* RETURNS: Flash size. (If flash wasn't initialize return 0)
+*********************************************************************/
+unsigned int flashGetSize()
+{
+	unsigned int sectorNum;
+	unsigned int totalSize = 0;
+
+	if (POINTER_TO_FLASH == 0)
+		return 0;	/* case of flash not initialize */
+	for (sectorNum = 0; sectorNum < flashTypes[NUMBER_OF_SECTORS];
+	     sectorNum++) {
+		totalSize += flashGetSectorSize(sectorNum);
+	}
+	return (totalSize);
+
+}
+
+/********************************************************************
+* flashGetSectorOffset - Returns sector base address.
+*
+* INPUTS:  unsigned int sectorNum.
+* RETURNS: Sector Base Address.
+*********************************************************************/
+unsigned int flashGetSectorOffset(unsigned int sectorNum)
+{
+	unsigned int i;
+	unsigned int sectorBaseAddress = 0;
+	unsigned int numOfDevices;
+
+	if (sectorNum > (flashParametrs[NUMBER_OF_SECTORS] - 1))
+		return 0xffffffff;
+	for (i = 0; i < sectorNum; i++) {
+		sectorBaseAddress =
+		    sectorBaseAddress + flashTypes[FIRST_SECTOR_SIZE + i];
+	}
+	if (FLASH_MODE == X16)
+		numOfDevices = FLASH_WIDTH * 8 / FLASH_MODE;
+	else
+		numOfDevices = FLASH_WIDTH;
+	return (_1K * sectorBaseAddress * numOfDevices);
+
+}
+
+/********************************************************************
+* flashWriteBlock - Write block of chars to flash.
+*
+* INPUTS:  unsigned int offset - flash destination address.
+*          unsigned int numOfByte - block size.
+*          unsigned char * blockAddress - block source address.
+* RETURNS: Number of Bytes written.
+*********************************************************************/
+unsigned int flashWriteBlock(unsigned int offset, unsigned int numOfByte,
+			     unsigned char *blockAddress)
+{
+	register unsigned int flashWrite;
+	register unsigned int align;
+	register unsigned int num;
+	register unsigned int i;
+
+	if ((offset + numOfByte) > flashGetSize())
+		numOfByte = flashGetSize() - offset;	/* getting to flash boundary. */
+	num = numOfByte;
+	align = offset % 4;	/* alignment toward flash.    */
+	/* writes chars until the offset toward flash will be align. */
+	for (i = align; (i < 4) && (numOfByte > 0) && (align != 0); i++) {
+		flashWriteChar(offset, blockAddress[0]);
+		numOfByte--;
+		offset++;
+		blockAddress++;
+	}
+	while (numOfByte > 3) {
+#ifdef LE
+		flashWrite = blockAddress[0] | (blockAddress[1] << 8) |
+		    (blockAddress[2] << 16) | (blockAddress[3] << 24);
+#else
+		flashWrite = blockAddress[3] | (blockAddress[2] << 8) |
+		    (blockAddress[1] << 16) | (blockAddress[0] << 24);
+#endif
+		if (flashWrite != 0xffffffff)	/* for optimization. */
+			flashWriteWord(offset, flashWrite);
+		numOfByte -= 4;
+		blockAddress += 4;
+		offset += 4;
+	}
+	while (numOfByte > 0) {
+		flashWriteChar(offset, blockAddress[0]);
+		numOfByte--;
+		blockAddress++;
+		offset++;
+	}
+	return num;
+}
+
+/********************************************************************
+* flashReadBlock - Read block of chars from flash.
+*
+* INPUTS:  unsigned int offset - flash source address.
+*          unsigned int numOfByte - block size.
+*          unsigned char * blockAddress - block destination address.
+* RETURNS: Number of Bytes written.
+*********************************************************************/
+unsigned int flashReadBlock(unsigned int offset, unsigned int numOfByte,
+			    unsigned char *blockAddress)
+{
+	unsigned int i;
+	for (i = 0; i < numOfByte; i++) {
+		blockAddress[i] = flashReadChar(offset + i);
+	}
+	return numOfByte;
+}
+
+/********************************************************************
+* flashReadChar - read one charecter form given flash offset.
+*
+* INPUTS:  unsigned int offset - required offset to be read from.
+* RETURNS: read charecter.
+*********************************************************************/
+unsigned char flashReadChar(unsigned int offset)
+{
+	unsigned char regValue;
+
+	flashReset();
+	READ_CHAR(FLASH_BASE_ADDRESS + offset, &regValue);
+	return regValue;
+}
+
+/********************************************************************
+* flashReadShort - read 16bit form given flash offset.
+*
+* INPUTS:  unsigned int offset - required offset to be read from.
+* RETURNS: 16bit data.
+*********************************************************************/
+unsigned short flashReadShort(unsigned int offset)
+{
+	unsigned short regValue;
+
+	flashReset();
+	READ_SHORT(FLASH_BASE_ADDRESS + offset, &regValue);
+	return regValue;
+}
+
+/********************************************************************
+* flashWriteShort - write 16bit data to a given flash offset.
+*                  It reads the whole word 32bit wide, modify the  short 
+*                  and write back the word.
+*
+* INPUTS:  unsigned int offset - required offset to be write to.
+*          unsigned short sdata - data to be written.
+* RETURNS: true if writting successesed false otherwise.
+*********************************************************************/
+bool flashWriteShort(unsigned int offset, unsigned short sdata)
+{
+	unsigned int align;
+	unsigned int flashWrite;
+	unsigned int flashRead;
+
+	align = offset % 4;
+	if ((align == 1) || (align == 3))
+		return false;	/* offset misaligned. */
+	flashRead = flashReadWord(offset - align);
+	if (align == 0)
+#ifdef BE
+		flashWrite = (flashRead & 0x0000ffff) | (sdata << 16);
+#else
+		flashWrite = (flashRead & 0xffff0000) | sdata;
+#endif
+	else			/* (align == 2) */
+#ifdef BE
+		flashWrite = (flashRead & 0xffff0000) | sdata;
+#else
+		flashWrite = (flashRead & 0x0000ffff) | (sdata << 16);
+#endif
+	flashWriteWord(offset - align, flashWrite);
+	return true;
+
+}
+
+/********************************************************************
+* flashWriteChar - write one charecter (8 bit) to a given flash offset.
+*                  It reads the whole word 32bit wide, modify the charecter 
+*                  and write back the word.
+*
+* INPUTS:  unsigned int offset - required offset to be write to.
+*          unsigned short sdata - data to be written.
+* RETURNS: true if writting successed.
+*********************************************************************/
+bool flashWriteChar(unsigned int offset, unsigned char cdata)
+{
+	unsigned int align;
+	unsigned int flashWrite;
+	unsigned int flashRead;
+
+	align = offset % 4;
+	flashRead = flashReadWord(offset - align);
+#ifdef BE
+	flashWrite = (flashRead & ~(0xff000000 >> (8 * align))) |
+	    (cdata << (8 * (3 - align)));
+#else
+	flashWrite = (flashRead & ~(0xff000000 << (8 * align))) |
+	    (cdata << (8 * align));
+#endif
+	flashWriteWord(offset - align, flashWrite);
+	return true;
+}
+
+/********************************************************************
+* flashGetNumOfSectors - write one charecter (8 bit) to a given flash offset.
+*                        It reads the whole word 32bit wide, modify the  
+*                        charecter and write back the word.
+*
+* INPUTS:  N/A.
+* RETURNS: Number of sectors.
+*********************************************************************/
+unsigned int flashGetNumOfSectors(void)
+{
+	return (flashTypes[NUMBER_OF_SECTORS]);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/galileo_port.h linux/arch/mips/galileo-boards/ev64120/compressed/galileo_port.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/galileo_port.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/galileo_port.h	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,8 @@
+#define GFP_KERNEL 0
+#define GFP_ATOMIC 1
+#define KERN_ERR ""
+
+void *kmalloc(unsigned int, int);
+void *memset(void *, char, unsigned int);
+int memcmp(char *, char *, unsigned int);
+void *memcpy(void *to, const void *from, unsigned int);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/gt64011.h linux/arch/mips/galileo-boards/ev64120/compressed/gt64011.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/gt64011.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/gt64011.h	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,279 @@
+/*
+ * gt64011.h: Galileo PCI system controller
+ * Copyright (c) 1998 Algorithmics Ltd
+ */
+
+#ifdef __ASSEMBLY__
+
+/* offsets from base register */
+#define GT64011(x)		(x)
+
+/* device is littleendian, so data may need to be swapped */
+#ifdef GALILEO_PORT
+#define htoll(x) ((((x) & 0x00ff) << 24) | \
+		  (((x) & 0xff00) <<  8) | \
+		  (((x) >> 8)  & 0xff00) | \
+		  (((x) >> 24) & 0x00ff))
+/*#define ltohl(x) htoll(x)*/
+#else
+#define htoll(x) (x)
+/* #define ltohl(x) (x) */
+#endif
+
+#else /* !__ASSEMBLY__ */
+
+/* offsets from base pointer, this construct allows optimisation */
+static char *const _gt64011p = (char *) PA_TO_KVA1(GT64011_BASE);
+
+#define GT64011(x)		*(volatile unsigned long *)(_gt64011p + (x))
+
+/* device is littleendian, so data may need to be swapped */
+#ifdef GALILEO_PORT
+#define htoll(x)     ({			\
+  unsigned int v = (unsigned int)(x);	\
+  v = (((v & 0x00ff) << 24) |		\
+       ((v & 0xff00) <<  8) |		\
+       ((v >>  8) & 0xff00) |		\
+       ((v >> 24) & 0x00ff));		\
+    v;					\
+    })
+#define ltohl(x) htoll(x)
+
+#else
+asjdsajd
+#define htoll(x) (x)
+#define ltohl(x) (x)
+#endif
+#endif /* __ASSEMBLY__ */
+/* CPU configuration */
+#define GT_CPU_CFG	GT64011(0x000)
+#define GT_CPU_CFG_WriteMode	(1<<11)
+#define GT_CPU_CFG_Endianess	(1<<12)
+/* Processor Address Space */
+#define GT_PAS_RAS10LO	GT64011(0x008)
+#define GT_PAS_RAS10HI	GT64011(0x010)
+#define GT_PAS_RAS32LO	GT64011(0x018)
+#define GT_PAS_RAS32HI	GT64011(0x020)
+#define GT_PAS_CS20LO	GT64011(0x028)
+#define GT_PAS_CS20HI	GT64011(0x030)
+#define GT_PAS_CS3BOOTLO GT64011(0x038)
+#define GT_PAS_CS3BOOTHI GT64011(0x040)
+#define GT_PAS_PCIIOLO	GT64011(0x048)
+#define GT_PAS_PCIIOHI	GT64011(0x050)
+#define GT_PAS_PCIMEMLO	GT64011(0x058)
+#define GT_PAS_PCIMEMHI	GT64011(0x060)
+#define GT_PAS_INTDEC	GT64011(0x068)
+#define GT_PAS_BUSERRLO	GT64011(0x070)
+#define GT_PAS_PCIMEM1LO GT64011(0x080)
+#define GT_PAS_PCIMEM1HI GT64011(0x088)
+#define GT_PAS_LOMASK_Low	0x7ff
+#define GT_PAS_LOSHIFT_Low	0
+#define GT_PAS_HIMASK_High	0x07f
+#define GT_PAS_HISHIFT_High	0
+/* DRAM and  Device Address Space */
+#define GT_DDAS_RAS0LO	GT64011(0x400)
+#define GT_DDAS_RAS0HI	GT64011(0x404)
+#define GT_DDAS_RAS1LO	GT64011(0x408)
+#define GT_DDAS_RAS1HI	GT64011(0x40c)
+#define GT_DDAS_RAS2LO	GT64011(0x410)
+#define GT_DDAS_RAS2HI	GT64011(0x414)
+#define GT_DDAS_RAS3LO	GT64011(0x418)
+#define GT_DDAS_RAS3HI	GT64011(0x41c)
+#define GT_DDAS_CS0LO	GT64011(0x420)
+#define GT_DDAS_CS0HI	GT64011(0x424)
+#define GT_DDAS_CS1LO	GT64011(0x428)
+#define GT_DDAS_CS1HI	GT64011(0x42c)
+#define GT_DDAS_CS2LO	GT64011(0x430)
+#define GT_DDAS_CS2HI	GT64011(0x434)
+#define GT_DDAS_CS3LO	GT64011(0x438)
+#define GT_DDAS_CS3HI	GT64011(0x43c)
+#define GT_DDAS_BOOTCSLO	GT64011(0x440)
+#define GT_DDAS_BOOTCSHI	GT64011(0x444)
+#define GT_DDAS_ERROR	GT64011(0x470)
+#define GT_DDAS_LOMASK_Low	0xff
+#define GT_DDAS_LOSHIFT_Low	0
+#define GT_DDAS_HIMASK_High	0xff
+#define GT_DDAS_HISHIFT_High	0
+/* DRAM Configuration */
+#define GT_DRAM_CFG	GT64011(0x448)
+#define GT_DRAM_CFG_RefIntCntMASK	0x00003fff
+#define GT_DRAM_CFG_RefIntCntSHIFT	0
+#define GT_DRAM_CFG_RefIntCnt(x)	(((x)<<GT_DRAM_CFG_RefIntCntSHIFT)&\
+					 GT_DRAM_CFG_RefIntCntMASK)
+#define GT_DRAM_CFG_StagRef		(1<<16)
+#define GT_DRAM_CFG_StagRefOn		0
+#define GT_DRAM_CFG_StagRefAll		GT_DRAM_CFG_StagRef
+#define GT_DRAM_CFG_ADSFunct		(1<<17)
+#define GT_DRAM_CFG_ADSFunctDRAM	0
+#define GT_DRAM_CFG_ADSFunctOnly	GT_DRAM_CFG_ADSFunct
+#define GT_DRAM_CFG_DRAMLatch		(1<<18)
+#define GT_DRAM_CFG_DRAMLatchActive	0
+#define GT_DRAM_CFG_DRAMLatchTransparent GT_DRAM_CFG_DRAMLatch
+/* DRAM Parameters */
+#define GT_DRAMPAR_BANK0 GT64011(0x44c)
+#define GT_DRAMPAR_BANK1 GT64011(0x450)
+#define GT_DRAMPAR_BANK2 GT64011(0x454)
+#define GT_DRAMPAR_BANK3 GT64011(0x458)
+#define GT_DRAMPAR_CASWr		(1<<0)
+#define GT_DRAMPAR_CASWr1		0
+#define GT_DRAMPAR_CASWr2		GT_DRAMPAR_CASWr
+#define GT_DRAMPAR_RAStoCASWr		(1<<1)
+#define GT_DRAMPAR_RAStoCASWr2		0
+#define GT_DRAMPAR_RAStoCASWr3		GT_DRAMPAR_RAStoCASWr
+#define GT_DRAMPAR_CASRd		(1<<2)
+#define GT_DRAMPAR_CASRd1		0
+#define GT_DRAMPAR_CASRd2		GT_DRAMPAR_CASRd
+#define GT_DRAMPAR_RAStoCASRd		(1<<3)
+#define GT_DRAMPAR_RAStoCASRd2		0
+#define GT_DRAMPAR_RAStoCASRd3		GT_DRAMPAR_RAStoCASRd
+#define GT_DRAMPAR_RefreshSHIFT		4
+#define GT_DRAMPAR_RefreshMASK		(3<<4)
+#define GT_DRAMPAR_Refresh512		(0<<4)
+#define GT_DRAMPAR_Refresh1024		(1<<4)
+#define GT_DRAMPAR_Refresh2048		(2<<4)
+#define GT_DRAMPAR_Refresh4096		(3<<4)
+#define GT_DRAMPAR_BankWidth		(1<<6)
+#define GT_DRAMPAR_BankWidth32		0
+#define GT_DRAMPAR_BankWidth64		GT_DRAMPAR_BankWidth
+#define GT_DRAMPAR_BankLoc		(1<<7)
+#define GT_DRAMPAR_BankLocEven		0
+#define GT_DRAMPAR_BankLocOdd		GT_DRAMPAR_BankLoc
+#define GT_DRAMPAR_Parity		(1<<8)
+#define GT_DRAMPAR_ParityDisable	0
+#define GT_DRAMPAR_ParityEnable		GT_DRAMPAR_Parity
+#define GT_DRAMPAR_MBZ			(1<<9)
+/* Device Parameters */
+#define GT_DEVPAR_BANK0	GT64011(0x45c)
+#define GT_DEVPAR_BANK1	GT64011(0x460)
+#define GT_DEVPAR_BANK2	GT64011(0x464)
+#define GT_DEVPAR_BANK3	GT64011(0x468)
+#define GT_DEVPAR_BOOT	GT64011(0x46c)
+#define GT_DEVPAR_TurnOffMASK		(7<<0)
+#define GT_DEVPAR_TurnOffSHIFT		0
+#define GT_DEVPAR_TurnOff(x)		((x)<<0)
+#define GT_DEVPAR_AccToFirstMASK	(15<<3)
+#define GT_DEVPAR_AccToFirstSHIFT	3
+#define GT_DEVPAR_AccToFirst(x)		((x)<<3)
+#define GT_DEVPAR_AccToNextMASK		(15<<7)
+#define GT_DEVPAR_AccToNextSHIFT	7
+#define GT_DEVPAR_AccToNext(x)		((x)<<7)
+#define GT_DEVPAR_ADStoWrMASK		(7<<11)
+#define GT_DEVPAR_ADStoWrSHIFT		11
+#define GT_DEVPAR_ADStoWr(x)		((x)<<11)
+#define GT_DEVPAR_WrActiveMASK		(7<<14)
+#define GT_DEVPAR_WrActiveSHIFT		14
+#define GT_DEVPAR_WrActive(x)		((x)<<14)
+#define GT_DEVPAR_WrHighMASK		(7<<17)
+#define GT_DEVPAR_WrHighSHIFT		17
+#define GT_DEVPAR_WrHigh(x)		((x)<<17)
+#define GT_DEVPAR_DevWidthMASK		(3<<20)
+#define GT_DEVPAR_DevWidthSHIFT		20
+#define GT_DEVPAR_DevWidth8		(0<<20)
+#define GT_DEVPAR_DevWidth16		(1<<20)
+#define GT_DEVPAR_DevWidth32		(2<<20)
+#define GT_DEVPAR_DevWidth64		(3<<20)
+#define GT_DEVPAR_DevLoc		(1<<23)
+#define GT_DEVPAR_DevLocEven		0
+#define GT_DEVPAR_DevLocOdd		GT_DEVPAR_DevLoc
+#define GT_DEVPAR_LatchFunct		(1<<25)
+#define GT_DEVPAR_LatchFunctTransparent 0
+#define GT_DEVPAR_LatchFunctEnable	GT_DEVPAR_LatchFunct
+#define GT_DEVPAR_Parity		(1<<30)
+#define GT_DEVPAR_ParityDisable		0
+#define GT_DEVPAR_ParityEnable		GT_DEVPAR_Parity
+#define GT_DEVPAR_ReservedMASK		0x3d400000
+#define GT_DEVPAR_Reserved		0x14400000
+/* PCI Internal */
+#define GT_IPCI_CMD GT64011(0xc00)
+#define GT_IPCI_CMD_ByteSwap		(1<<0)
+#define GT_IPCI_CMD_ByteSwapOn		0
+#define GT_IPCI_CMD_ByteSwapOff		GT_INTPCI_CMD_ByteSwap
+#define GT_IPCI_CMD_SyncModeMASK	(3<<1)
+#define GT_IPCI_CMD_SyncModeSHIFT	1
+#define GT_IPCI_CMD_SyncModeStd		(0<<1)
+#define GT_IPCI_CMD_SyncMode1		(1<<1)
+#define GT_IPCI_CMD_SyncMode2		(2<<1)
+#define GT_IPCI_TOR	GT64011(0xc04)
+#define GT_IPCI_TOR_Timeout0MASK	(255<<0)
+#define GT_IPCI_TOR_Timeout0SHIFT	0
+#define GT_IPCI_TOR_Timeout0(x)	((x)<<0)
+#define GT_IPCI_TOR_Timeout1MASK	(255<<8)
+#define GT_IPCI_TOR_Timeout1SHIFT	8
+#define GT_IPCI_TOR_Timeout1(x)	((x)<<8)
+#define GT_IPCI_TOR_RetryCtrMASK	(255<<16)
+#define GT_IPCI_TOR_RetryCtrSHIFT	16
+#define GT_IPCI_TOR_RetryCtr(x)		((x)<<16)
+#define GT_IPCI_RAS10SIZE	GT64011(0xc08)
+#define GT_IPCI_RAS32SIZE	GT64011(0xc0c)
+#define GT_IPCI_CS20SIZE	GT64011(0xc10)
+#define GT_IPCI_CS3BOOTSIZE	GT64011(0xc14)
+#define GT_IPCI_SIZE_BankSizeMASK	(0xfffff<<12)
+#define GT_IPCI_SIZE_BankSizeSHIFT	12
+#define GT_IPCI_INTRCAUSE	GT64011(0xc18)
+#define GT_IPCI_INTRMASK	GT64011(0xc1c)
+#define  GT_INTR_INTSUM			0x0000001
+#define  GT_INTR_MEMOUT			0x0000002
+#define  GT_INTR_DMAOUT			0x0000004
+#define  GT_INTR_CPUOUT			0x0000008
+#define  GT_INTR_DMA0COMP		0x0000010
+#define  GT_INTR_DMA1COMP		0x0000020
+#define  GT_INTR_DMA2COMP		0x0000040
+#define  GT_INTR_DMA3COMP		0x0000080
+#define  GT_INTR_T0EXP			0x0000100
+#define  GT_INTR_T1EXP			0x0000200
+#define  GT_INTR_T2EXP			0x0000400
+#define  GT_INTR_T3EXP			0x0000800
+#define  GT_INTR_MASRDERR		0x0001000
+#define  GT_INTR_SLVWRERR		0x0002000
+#define  GT_INTR_MASWRERR		0x0004000
+#define  GT_INTR_SLVRDERR		0x0008000
+#define  GT_INTR_ADDRERR		0x0010000
+#define  GT_INTR_MEMERR			0x0020000
+#define  GT_INTR_MASABORT		0x0040000
+#define  GT_INTR_TARABORT		0x0080000
+#define  GT_INTR_RETRYCTR		0x0010000
+#define  GT_INTR_CPU2PCIA		0x0020000
+#define  GT_INTR_CPU2PCIB		0x0040000
+#define  GT_INTR_CPU2PCIC		0x0080000
+#define  GT_INTR_CPU2PCID		0x0100000
+#define  GT_INTR_CPU2PCIE		0x0200000
+#define  GT_INTR_PCI2CPUA		0x0400000
+#define  GT_INTR_PCI2CPUB		0x0800000
+#define  GT_INTR_PCI2CPUC		0x1000000
+#define  GT_INTR_PCI2CPUD		0x2000000
+#define  GT_INTR_CPUINTSUM		0x4000000
+#define  GT_INTR_PCIINTSUM		0x8000000
+#define GT_IPCI_PCIINTMASK	GT64011(0xc24)
+#define GT_IPCI_SERMASK		GT64011(0xc28)
+#define GT_IPCI_SERMASK_AddrErr		(1<<0)
+#define GT_IPCI_SERMASK_MasWrErr	(1<<1)
+#define GT_IPCI_SERMASK_MasRdErr	(1<<2)
+#define GT_IPCI_SERMASK_MemErr		(1<<3)
+#define GT_IPCI_SERMASK_MasAbort	(1<<4)
+#define GT_IPCI_SERMASK_TarAbort	(1<<5)
+#define GT_IPCI_INTACK		GT64011(0xc34)
+#define GT_IPCI_BAREN		GT64011(0xc3c)
+#define GT_IPCI_BAREN_SwCs3BootDis	(1<<0)
+#define GT_IPCI_BAREN_SwRas32Dis	(1<<1)
+#define GT_IPCI_BAREN_SwRas10Dis	(1<<2)
+#define GT_IPCI_BAREN_IntIODis		(1<<3)
+#define GT_IPCI_BAREN_IntMemDis		(1<<4)
+#define GT_IPCI_BAREN_Cs3BootDis	(1<<5)
+#define GT_IPCI_BAREN_Cs20Dis		(1<<6)
+#define GT_IPCI_BAREN_Ras32Dis		(1<<7)
+#define GT_IPCI_BAREN_Ras10Dis		(1<<8)
+#define GT_IPCI_CFGADDR		GT64011(0xcf8)
+#define GT_IPCI_CFGDATA		GT64011(0xcfc)
+#define GT_IPCI_CFGADDR_RegNumMASK	(0x3f<<2)
+#define GT_IPCI_CFGADDR_RegNumSHIFT	2
+#define GT_IPCI_CFGADDR_RegNum(x)	((x)<<2)
+#define GT_IPCI_CFGADDR_FunctNumMASK	(0x7<<8)
+#define GT_IPCI_CFGADDR_FunctNumSHIFT	8
+#define GT_IPCI_CFGADDR_FunctNum(x)	((x)<<8)
+#define GT_IPCI_CFGADDR_DevNumMASK	(0x1f<<11)
+#define GT_IPCI_CFGADDR_DevNumSHIFT	11
+#define GT_IPCI_CFGADDR_DevNum(x)	((x)<<11)
+#define GT_IPCI_CFGADDR_BusNumMASK	(0xff<<16)
+#define GT_IPCI_CFGADDR_BusNumSHIFT	16
+#define GT_IPCI_CFGADDR_BusNum(x)	((x)<<16)
+#define GT_IPCI_CFGADDR_ConfigEn	(1<<31)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/head.S linux/arch/mips/galileo-boards/ev64120/compressed/head.S
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/head.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/head.S	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,19 @@
+/*
+ *  arch/mips/galileo/compressed/head.S
+ *
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+	.text
+NESTED(startup, 16, sp)
+	.set	noreorder
+        
+	jal decompress_kernel
+	nop
+        
+        jal kernel_location_start+0x584
+        nop
+        
+	END(startup)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.script.gal linux/arch/mips/galileo-boards/ev64120/compressed/ld.script.gal
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.script.gal	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/ld.script.gal	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,19 @@
+OUTPUT_FORMAT("elf32-bigmips")
+OUTPUT_ARCH(mips)
+ENTRY(startup)
+SECTIONS 
+{ 
+  kernel_location_start = 0x80100000;
+  . = 0x80400000;
+  .text : {
+  *(.text)
+  }
+  .bss : {
+  *(.bss)
+  }
+  .data :{
+  *(.data)
+  }
+  malloc_start = .;
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash linux/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,29 @@
+OUTPUT_FORMAT("elf32-bigmips")
+OUTPUT_ARCH(mips)
+ENTRY(sbdreset)
+
+SECTIONS
+{
+  . = 0xBFC00000;
+  .got : {*(.got)}
+  .reset : { 
+    sbdreset = ABSOLUTE(.);
+    sbdreset_evb64120A.o
+    evb64120A_Setup.o /* <-- Note: contains xfer.c contents as well.. */
+    pci_etherboot.o
+    memory.o
+    pci.o
+  }
+  kernel_location_start = 0x80100000;
+  . = 0x80400000;
+  .text : {
+  *(.text)
+  }
+  .bss : {
+  *(.bss)
+  }
+  .data :{
+  *(.data)
+  }
+  malloc_start = .;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash2 linux/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash2
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash2	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.Flash2	2002-08-01 06:42:34.000000000 +0000
@@ -0,0 +1,24 @@
+OUTPUT_FORMAT("elf32-bigmips")
+OUTPUT_ARCH(mips)
+ENTRY(XferToRam)
+
+SECTIONS
+{
+  . = 0xBF000000;
+  .got : {*(.got)}
+  .reset : { 
+    xfer.o
+  }
+  kernel_location_start = 0x80100000;
+  . = 0x80400000;
+  .text : {
+  *(.text)
+  }
+  .bss : {
+  *(.bss)
+  }
+  .data :{
+  *(.data)
+  }
+  malloc_start = .;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.burner linux/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.burner
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.burner	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/ld.sys.big.burner	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,11 @@
+OUTPUT_FORMAT("elf32-bigmips")
+OUTPUT_ARCH(mips)
+ENTRY(main)
+
+SECTIONS
+{
+ . = 0xA0400000;
+ .text : {*(.text)}
+ .data : {*(.data)}
+ .bss  : {*(.bss)}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/load.c linux/arch/mips/galileo-boards/ev64120/compressed/load.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/load.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/load.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,244 @@
+
+/* control character used for download */
+#define ETX	CNTRL('c')
+#define ACK	CNTRL('f')
+#define NAK	CNTRL('u')
+#define XON	CNTRL('q')
+#define XOFF	CNTRL('s')
+
+unsigned int csum;
+unsigned int dl_entry;
+
+static const unsigned char hextab[256] = {
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 255, 255, 255, 255, 255, 255,
+	255, 10, 11, 12, 13, 14, 15, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 10, 11, 12, 13, 14, 15, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+	    255, 255, 255,
+};
+
+
+unsigned char ascii_to_bin(unsigned char c)
+{
+	return hextab[c];
+}
+
+unsigned char read_char_direct(void)
+{
+	unsigned char c, *cp;
+	cp = (unsigned char *) 0xbd000020;
+	while (1) {
+		if (*(cp + 0x14) & 0x01) {
+			c = (volatile unsigned char) *cp;
+			return c;
+		}
+		cp++;
+		cp--;
+	}
+}
+
+unsigned char get_pair(void)
+{
+	unsigned char byte;
+
+	byte = ascii_to_bin(read_char_direct()) << 4;
+	byte |= ascii_to_bin(read_char_direct());
+	csum += byte;
+	return (byte);
+}
+
+
+void serial_putc(int ch)
+{
+	unsigned long temp;
+	for (temp = 0; temp < 1000; temp++) {
+	}
+	*(char *) 0xbd000020 = (char) ch;
+}
+
+
+int inline serial_getc(void)
+{
+	return read_char_direct();
+}
+
+int serial_ischar(void)
+{
+
+	unsigned char c, *cp;
+	unsigned count;
+	cp = (unsigned char *) 0xbd000020;
+	count = 0;
+	while (count != 100) {
+		if (*(cp + 0x14) & 0x01) {
+			c = (volatile unsigned char) *cp;
+			return c;
+		}
+		cp++;
+		cp--;
+		count++;
+	}
+	return 0;
+}
+
+int serial_init(void)
+{
+	return 0;
+}
+
+
+int galileo_dl(void)
+{
+#define display_char '.'
+#define display_error 'E'
+#define display_error_bad_7 '7'
+#define display_error_unknown 'U'
+#define display_error_length 'L'
+
+	register int length, address, save_csum;
+	int i, first, done, eof, reccount, type, client_pc;
+	int src, dbl_length;
+	unsigned char *buffptr, databuff[258], tempo;
+	register int display_counter, chunks, leftovers, putter,
+	    bytes_per_chunk;
+	display_counter = 0;
+	bytes_per_chunk = 16;
+	csum = 0;
+
+	reccount = 1;
+	for (first = 1, done = 0; !done; first = 0, reccount++) {
+		while (read_char_direct() != 'S')
+			continue;
+		csum = 0;
+		type = read_char_direct();
+		length = get_pair();
+		if (length < 0 || length >= 256) {
+			*(char *) 0xbd000020 = display_error_length;
+			//      *(char*)0xbd00000c = display_error_length;
+			return 0;
+		}
+		length--;
+		switch (type) {
+		case '0':
+			while (length-- > 0)
+				get_pair();
+			break;
+		case '3':
+			address = 0;
+			for (i = 0; i < 4; i++) {
+				address <<= 8;
+				address |= get_pair();
+				length--;
+			}
+			if (address == -1) {
+				eof = 1;
+				continue;
+			}
+			buffptr = &databuff[0];
+			dbl_length = length << 1;
+			chunks = dbl_length / bytes_per_chunk;
+			leftovers = dbl_length % bytes_per_chunk;
+			putter = bytes_per_chunk >> 1;
+			while (chunks--) {
+				for (i = 0; i < bytes_per_chunk; i++)
+					databuff[i] = read_char_direct();
+				src = i = 0;
+				while (i++ < putter) {
+					tempo =
+					    (ascii_to_bin(databuff[src++])
+					     << 4) |
+					    ascii_to_bin(databuff[src++]);
+					csum += tempo;
+					*(char *) address++ = tempo;
+				}
+			}
+			if (leftovers) {
+				putter = leftovers / 2;
+				for (i = 0; i < leftovers; i++)
+					databuff[i] = read_char_direct();
+				src = i = 0;
+				while (i++ < putter) {
+					tempo =
+					    (ascii_to_bin(databuff[src++])
+					     << 4) |
+					    ascii_to_bin(databuff[src++]);
+					csum += tempo;
+					*(char *) address++ = tempo;
+				}
+			}
+			break;
+
+		case '7':
+			address = 0;
+			for (i = 0; i < 4; i++) {
+				address <<= 8;
+				address |= get_pair();
+				length--;
+			}
+			if (address == -1) {
+				eof = 1;
+				continue;
+			}
+			client_pc = address;
+			if (length) {
+				*(char *) 0xbd000020 = display_error_bad_7;
+				//                      *(char*)0xbd00000c = display_error_bad_7;
+			}
+
+			done = 1;
+			break;
+
+		default:
+			*(char *) 0xbd000020 = display_error_unknown;
+			//              *(char*)0xbd00000c = display_error_unknown;
+
+			break;
+		}
+		save_csum = (~csum) & 0xff;
+		if ((csum = get_pair()) < 0) {
+			eof = 1;
+			continue;
+		}
+		if (csum != save_csum) {
+			*(char *) 0xbd000020 = display_error;
+			//                *(char*)0xbd00000c = display_error;
+		} else {
+
+			if (display_counter % 50 == 0) {
+				*(char *) 0xbd000020 = display_char;
+				display_counter = 0;
+			}
+			display_counter++;
+
+		}
+	}
+	--reccount;
+	dl_entry = client_pc;
+	return dl_entry;	/* Success */
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/meminit.S linux/arch/mips/galileo-boards/ev64120/compressed/meminit.S
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/meminit.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/meminit.S	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,187 @@
+/* 
+ * Define BUSWIDTH to usually be real buswidth X 2 (i.e assuming 
+ * 2-way interleaving).  This is so that the test pattern and
+ * inverted pattern are written to the same bank of memory, which
+ * prevents us reading back data sitting in the dram buffers and 
+ * getting a false match.
+ */
+
+#ifndef BUSWIDTH
+# if #cpu(r3000) || #cpu(r4300) || #cpu(r4650)
+#  define BUSWIDTH	8		/* 32 bit memory, bank interleaved */
+# elif #cpu(r4000)
+#  define BUSWIDTH	16		/* 64 bit memory, bank interleaved */
+# endif
+#endif
+
+#ifndef RAM_BASE
+#define RAM_BASE	KSEG1_BASE
+#endif
+			
+#ifndef MEMSTART
+#define MEMSTART	0x0		/* start of physical memory */
+#endif
+		
+#ifndef MEMINCR
+# define MEMINCR	0x10000		/* work up in 64Kb increments */
+#endif
+
+SLEAF(size_mem)
+	mfc0	t8,C0_STATUS
+#if #cpu(r4000)
+	/* disable cache and memory parity checking */
+	or	t0,t8,SR_DE
+	mtc0	t0,C0_STATUS
+#endif
+
+	li	t0,RAM_BASE+MEMSTART	# start at bottom of phys mem
+	move	t1,t0			# remember start address
+	li	t2,0xaa55aa55		# pattern 
+	not	t3,t2			# ~pattern
+
+	move	t7,k0
+	la	t4,.fail		# bus error exception catcher
+	addu	k0,t4,s8		# RELOC 
+	
+	/* fill first 64Kb with zero (for cache init) */
+	move	t4,t0
+	li	t5,0x10000
+1:	sw	zero,0(t4)
+	sw	zero,4(t4)
+	sw	zero,8(t4)
+	sw	zero,12(t4)
+	subu	t5,16
+	addu	t4,16
+	bnez	t5,1b
+
+.loop:
+        addu    t0,MEMINCR		
+	move	t4,t0
+
+	/* store pattern in bank 0, line 0 */
+	sw	t2,0(t4)
+	addu	t4,4
+
+#if BUSWIDTH > 4
+	/* fill remainder of line with zeros */
+	li	t5,BUSWIDTH-4
+1:	sw	zero,0(t4)
+	subu	t5,4
+	addu	t4,4
+	bnez	t5,1b
+#endif
+
+	/* store inverse pattern in bank 0, line 1 */
+	sw	t3,0(t4)
+	addu	t4,4
+
+#if BUSWIDTH > 4
+	/* fill remainder of line with zeros */
+	li	t5,BUSWIDTH-4
+1:	sw	zero,0(t4)
+	subu	t5,4
+	addu	t4,4
+	bnez	t5,1b
+#endif
+
+	/* defeat write buffering */
+#if #cpu(r4000)
+	sync
+#else
+	lw	zero,-4(t4)
+#endif
+
+	lw	t4,0(t0)		# read first word of line
+	lw	t5,0(t1)		# read start of memory (should be zero)
+	bne	t4,t2,.fail		# this line wrong?
+        beq     t5,zero,.loop		# start of mem overwritten?
+
+.fail:
+	move	k0,t7			# clear exception catcher
+
+	/* restore Status register */
+	mtc0	t8,C0_STATUS
+
+	/* return top of memory offset (normally == size) */
+	subu 	v0,t0,RAM_BASE
+	j	ra
+END(size_mem)
+
+
+/*
+ * We must often initialise memory so that it has good parity/ecc, 
+ * and this must be done before the caches are used.
+ */
+
+/*
+	clear_mem (size)
+	  - clear memory from RAM_BASE+MEMSTART to RAM_BASE+MEMSTART+size
+	clear_mem_range (size, start)  
+	  - clear memory from start to start+size
+*/
+
+SLEAF(clear_mem)
+	li	a1,RAM_BASE+MEMSTART	# start at bottom of phys mem
+clear_mem_range:	
+	beqz	a0,9f
+	addu	a0,a1			# end of memory 
+	
+	/* XXX should run cached, but caches may not be initialised yet */
+	.set noreorder	
+#if __mips >= 3
+1:	sd	zero,0(a1)
+	sd	zero,8(a1)
+	sd	zero,16(a1)
+	sd	zero,24(a1)
+	sd	zero,32(a1)
+	sd	zero,40(a1)
+	sd	zero,48(a1)
+	addu	a1,64
+	bne	a1,a0,1b
+	sd	zero,-8(a1)		# BDSLOT
+#else	
+1:	sw	zero,0(a1)
+	sw	zero,4(a1)
+	sw	zero,8(a1)
+	sw	zero,12(a1)
+	sw	zero,16(a1)
+	sw	zero,20(a1)
+	sw	zero,24(a1)
+	sw	zero,28(a1)
+	sw	zero,32(a1)
+	sw	zero,36(a1)
+	sw	zero,40(a1)
+	sw	zero,44(a1)
+	sw	zero,48(a1)
+	sw	zero,52(a1)
+	sw	zero,56(a1)
+	addu	a1,64
+	bne	a1,a0,1b
+	sw	zero,-4(a1)		# BDSLOT
+#endif	
+	.set	reorder
+
+9:	j	ra
+END(clear_mem)
+
+
+SLEAF(init_tlb)
+	/* initialise tlb */
+	mtc0	zero,C0_TLBLO0		/* tlblo0 = invalid */
+	mtc0	zero,C0_TLBLO1		/* tlblo1 = invalid */
+        mtc0	zero,C0_PGMASK
+	li	t8,K1BASE		/* tlbhi  = impossible vpn */
+	li	t9,(NTLBENTRIES-1)	/* index */
+	
+	.set noreorder
+	nop
+1:	mtc0	t8,C0_TLBHI
+	mtc0	t9,C0_INX
+	addu	t8,0x2000		/* inc vpn */
+	tlbwi
+	bnez	t9,1b
+	subu	t9,1			# BDSLOT
+	.set reorder
+
+	j	ra
+END(init_tlb)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/memory.c linux/arch/mips/galileo-boards/ev64120/compressed/memory.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/memory.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/memory.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,593 @@
+/* Memory.c - Memory mappings and remapping functions */
+
+/* Copyright - Galileo technology. */
+
+/*
+DESCRIPTION
+This file contains function which gives the user the ability to remap the
+SDRAM memory and devices windows, please pay attention to overlapping windows
+since the function do not take care of that for you.
+When remapping the SDRAM or devices memory space pay attention to the PCI
+mappings and make sure to coordinate between the two interfaces!!!           
+*/
+
+/* includes */
+
+#ifdef __linux__
+#include <asm/galileo-boards/evb64120A/core.h>
+#include <asm/galileo-boards/evb64120A/memory.h>
+#else
+#include "Core.h"
+#include "Memory.h"
+#endif
+
+/********************************************************************
+* getMemoryBankBaseAddress - Extract the base address of a memory bank
+*      - If the memory bank size is 0 then this base address has no meaning !!!
+*
+* INPUTS:  MEMORY_BANK bank - SDRAM Bank number.
+* OUTPUT:  N/A  
+* RETURNS: Memory bank base address.
+*********************************************************************/
+unsigned int getMemoryBankBaseAddress(MEMORY_BANK bank)
+{
+	unsigned int base, regBase;
+	GT_REG_READ((SCS_1_0_LOW_DECODE_ADDRESS + (bank / 2) * 0x10),
+		    &base);
+	base = base << 21;
+	GT_REG_READ((SCS_0_LOW_DECODE_ADDRESS + bank * 8), &regBase);
+	base = base | (regBase << 20);
+	return base;
+}
+
+/********************************************************************
+* getDeviceBaseAddress - Extract the base address of a device.
+*           - If the device size is 0 then this base address has no meaning!!!
+*
+* INPUT:   DEVICE device - Bank number.
+* OUTPUT:  N/A  
+* RETURNS: Device base address.
+*********************************************************************/
+unsigned int getDeviceBaseAddress(DEVICE device)
+{
+	unsigned int base, regBase;
+	GT_REG_READ((CS_2_0_LOW_DECODE_ADDRESS + (device / 3) * 0x10),
+		    &base);
+	base = base << 21;
+	GT_REG_READ((CS_0_LOW_DECODE_ADDRESS + device * 0x8), &regBase);
+	base = base | (regBase << 20);
+	return base;
+}
+
+/********************************************************************
+* getMemoryBankSize - Extract the size of a memory bank.
+*
+* INPUT:   MEMORY_BANK bank - Bank number
+* OUTPUT:  N/A
+* RETURNS: Memory bank size.
+*********************************************************************/
+unsigned int getMemoryBankSize(MEMORY_BANK bank)
+{
+	unsigned int size, base, value;
+	base = getMemoryBankBaseAddress(bank);
+	GT_REG_READ((SCS_0_HIGH_DECODE_ADDRESS + bank * 8), &size);
+	size = ((size + 1) << 20) - (base & 0x0fffffff);
+	GT_REG_READ((SCS_0_HIGH_DECODE_ADDRESS + bank * 8), &value);
+	if (value == 0)
+		return 0;
+	else
+		return size;
+}
+
+/********************************************************************
+* getDeviceSize - Extract the size of a device memory space
+*
+* INPUT:    DEVICE device - Device number
+* OUTPUT:   N/A  
+* RETURNS:  Size of a device memory space.
+*********************************************************************/
+unsigned int getDeviceSize(DEVICE device)
+{
+	unsigned int size, base, value;
+	base = getDeviceBaseAddress(device);
+	GT_REG_READ((CS_0_HIGH_DECODE_ADDRESS + device * 8), &size);
+	size = ((size + 1) << 20) - (base & 0x0fffffff);
+	GT_REG_READ((CS_0_HIGH_DECODE_ADDRESS + device * 8), &value);
+	if ((value + 1) == 0)
+		return 0;
+	else
+		return size;
+}
+
+/********************************************************************
+* getDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width.
+*                  The width is determine in registers: 'Device Parameters'
+*                  registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device.
+*                  at bits: [21:20].                  
+*
+* INPUT:    DEVICE device - Device number
+* OUTPUT:   N/A  
+* RETURNS:  Device width in Bytes (1,2,4, or 8), 0 if error had occurred.
+*********************************************************************/
+unsigned int getDeviceWidth(DEVICE device)
+{
+	unsigned int width;
+	unsigned int regValue;
+
+	GT_REG_READ(DEVICE_BANK0PARAMETERS + device * 4, &regValue);
+	width = (regValue & 0x00300000) >> 20;
+	switch (width) {
+	case 0:
+		return 1;
+	case 1:
+		return 2;
+	case 2:
+		return 4;
+	case 3:
+		return 8;
+	default:
+		return 0;
+	}
+}
+
+/********************************************************************
+* mapMemoryBanks0and1 - Sets new bases and boundaries for memory banks 0 and 1
+*                     - Pay attention to the PCI mappings and make sure to 
+*                       coordinate between the two interfaces!!!
+*                     - It is the programmer`s responsibility to make sure 
+*                       there are no conflicts with other memory spaces!!!
+*                     - If a bank needs to be closed , give it a 0 length
+*
+*
+* INPUTS: unsigned int bank0Base - required bank 0 base address.
+*         unsigned int bank0Length - required bank 0 size.
+*         unsigned int bank1Base - required bank 1 base address.
+*         unsigned int bank1Length - required bank 1 size.
+* RETURNS: true on success, false on failure or if one of the parameters is 
+*          erroneous.
+*********************************************************************/
+bool mapMemoryBanks0and1(unsigned int bank0Base, unsigned int bank0Length,
+			 unsigned int bank1Base, unsigned int bank1Length)
+{
+	unsigned int mainBank0Top = bank0Base + bank0Length;
+	unsigned int mainBank1Top = bank1Base + bank1Length;
+	unsigned int memBank0Base, bank0Top;
+	unsigned int memBank1Base, bank1Top;
+
+	if (bank0Base <= bank1Base) {
+		if ((bank0Base + bank0Length) > bank1Base)
+			return false;
+	} else {
+		if ((bank1Base + bank1Length) > bank0Base)
+			return false;
+	}
+
+	if (bank0Length == 0)
+		mainBank0Top++;
+	if (bank1Length == 0)
+		mainBank1Top++;
+
+	memBank0Base = ((unsigned int) (bank0Base & 0x0fffffff)) >> 20;
+	bank0Top = ((unsigned int) (mainBank0Top & 0x0fffffff)) >> 20;
+	memBank1Base = ((unsigned int) (bank1Base & 0x0fffffff)) >> 20;
+	bank1Top = ((unsigned int) (mainBank1Top & 0x0fffffff)) >> 20;
+
+	if (mainBank1Top > mainBank0Top) {
+		bank0Base >>= 21;
+		mainBank0Top =
+		    ((unsigned int) (mainBank1Top & 0x0fffffff)) >> 21;
+	} else {
+		bank0Base = bank1Base >> 21;
+		mainBank0Top =
+		    ((unsigned int) (mainBank0Top & 0x0fffffff)) >> 21;
+	}
+	GT_REG_WRITE(SCS_1_0_LOW_DECODE_ADDRESS, bank0Base);
+	if ((bank0Length + bank1Length) != 0) {
+		GT_REG_WRITE(SCS_1_0_HIGH_DECODE_ADDRESS,
+			     mainBank0Top - 1);
+	} else {
+		GT_REG_WRITE(SCS_1_0_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	if (bank1Length != 0) {
+		GT_REG_WRITE(SCS_1_HIGH_DECODE_ADDRESS, bank1Top - 1);
+	} else {
+		GT_REG_WRITE(SCS_1_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(SCS_1_LOW_DECODE_ADDRESS, memBank1Base);
+	if (bank0Length != 0) {
+		GT_REG_WRITE(SCS_0_HIGH_DECODE_ADDRESS, bank0Top - 1);
+	} else {
+		GT_REG_WRITE(SCS_0_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(SCS_0_LOW_DECODE_ADDRESS, memBank0Base);
+	return true;
+}
+
+/********************************************************************
+* mapMemoryBanks2and3 - Sets new bases and boundaries for memory banks 2 and 3
+*                     - Pay attention to the PCI mappings and make sure to  
+*                       coordinate between the two interfaces!!!
+*                     - It`s the programmer`s responsibility to make sure there
+*                       are no conflicts with other memory spaces!!!
+*                     - If a bank needs to be closed , give it a 0 length.
+*
+*
+* INPUTS: unsigned int bank2Base - required bank 2 base address.
+*         unsigned int bank2Length - required bank 2 size.
+*         unsigned int bank3Base - required bank 3 base address.
+*         unsigned int bank3Length - required bank 3 size.
+* RETURNS: true on success, false on failure or if one of the parameters is 
+*          erroneous.
+*********************************************************************/
+bool mapMemoryBanks2and3(unsigned int bank2Base, unsigned int bank2Length,
+			 unsigned int bank3Base, unsigned int bank3Length)
+{
+	unsigned int mainBank2Top =
+	    (unsigned int) (bank2Base + bank2Length);
+	unsigned int mainBank3Top =
+	    (unsigned int) (bank3Base + bank3Length);
+	unsigned int memBank2Base, bank2Top;
+	unsigned int memBank3Base, bank3Top;
+
+	if (bank2Base <= bank3Base) {
+		if ((bank2Base + bank2Length) > bank3Base)
+			return false;
+	} else {
+		if ((bank3Base + bank3Length) > bank2Base)
+			return false;
+	}
+	if (bank2Length == 0)
+		mainBank2Top++;
+	if (bank3Length == 0)
+		mainBank3Top++;
+
+	memBank2Base = ((unsigned int) (bank2Base & 0x0fffffff)) >> 20;
+	bank2Top = ((unsigned int) (mainBank2Top & 0x0fffffff)) >> 20;
+	memBank3Base = ((unsigned int) (bank3Base & 0x0fffffff)) >> 20;
+	bank3Top = ((unsigned int) (mainBank3Top & 0x0fffffff)) >> 20;
+
+	if (mainBank3Top > mainBank2Top) {
+		bank2Base >>= 21;
+		mainBank2Top =
+		    ((unsigned int) (mainBank3Top & 0x0fffffff)) >> 21;
+	} else {
+		bank2Base = bank3Base >> 21;
+		mainBank2Top =
+		    ((unsigned int) (mainBank2Top & 0x0fffffff)) >> 21;
+	}
+	GT_REG_WRITE(SCS_3_2_LOW_DECODE_ADDRESS, bank2Base);
+	if ((bank2Length + bank3Length) != 0) {
+		GT_REG_WRITE(SCS_3_2_HIGH_DECODE_ADDRESS,
+			     mainBank2Top - 1);
+	} else {
+		GT_REG_WRITE(SCS_3_2_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	if (bank3Length != 0) {
+		GT_REG_WRITE(SCS_3_HIGH_DECODE_ADDRESS, bank3Top - 1);
+	} else {
+		GT_REG_WRITE(SCS_3_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(SCS_3_LOW_DECODE_ADDRESS, memBank3Base);
+	if (bank2Length != 0) {
+		GT_REG_WRITE(SCS_2_HIGH_DECODE_ADDRESS, bank2Top - 1);
+	} else {
+		GT_REG_WRITE(SCS_2_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(SCS_2_LOW_DECODE_ADDRESS, memBank2Base);
+	return true;
+}
+
+/********************************************************************
+* mapDevices0_1and2MemorySpace - Sets new bases and boundaries for devices 0,1 
+*                                and 2
+*                     - Pay attention to the PCI mappings and make sure to 
+*                        coordinate between the two interfaces!!!
+*                     - It`s the programmer`s responsibility to make sure there
+*                       are no conflicts with other memory spaces!!!
+*                     - If a device needs to be closed , give it a 0 length
+*
+*
+* INPUTS: unsigned int device0Base - required cs_0 base address.
+*         unsigned int device0Length - required cs_0 size.
+*         unsigned int device1Base - required cs_1 base address. 
+*         unsigned int device1Length - required cs_0 size.       
+*         unsigned int device2Base - required cs_2 base address. 
+*         unsigned int device2Length - required cs_2 size.       
+* RETURNS: true on success, false on failure or if one of the parameters is 
+*          erroneous.
+*********************************************************************/
+bool mapDevices0_1and2MemorySpace(unsigned int device0Base,
+				  unsigned int device0Length,
+				  unsigned int device1Base,
+				  unsigned int device1Length,
+				  unsigned int device2Base,
+				  unsigned int device2Length)
+{
+	unsigned int deviceBank0Top =
+	    (unsigned int) (device0Base + device0Length);
+	unsigned int deviceBank1Top =
+	    (unsigned int) (device1Base + device1Length);
+	unsigned int deviceBank2Top =
+	    (unsigned int) (device2Base + device2Length);
+	unsigned int device0BaseTemp = 0, device0TopTemp = 0;
+	unsigned int bank0Base, bank0Top;
+	unsigned int bank1Base, bank1Top;
+	unsigned int bank2Base, bank2Top;
+	bank0Base = ((unsigned int) (device0Base & 0x0fffffff)) >> 20;
+	bank0Top = ((unsigned int) (deviceBank0Top & 0x0fffffff)) >> 20;
+	bank1Base = ((unsigned int) (device1Base & 0x0fffffff)) >> 20;
+	bank1Top = ((unsigned int) (deviceBank1Top & 0x0fffffff)) >> 20;
+	bank2Base = ((unsigned int) (device2Base & 0x0fffffff)) >> 20;
+	bank2Top = ((unsigned int) (deviceBank2Top & 0x0fffffff)) >> 20;
+
+	if (device0Length == 0)
+		deviceBank0Top++;
+	if (device1Length == 0)
+		deviceBank1Top++;
+	if (device2Length == 0)
+		deviceBank2Top++;
+
+	if (device0Base <= device1Base && device0Base <= device2Base) {
+		if ((device0Base + device0Length) > device1Base || \
+		    (device0Base + device0Length) > device2Base)
+			return false;
+		if (device1Base <= device2Base) {
+			if ((device1Base + device1Length) > device2Base)
+				return false;
+		} else {
+			if ((device2Base + device2Length) > device1Base)
+				return false;
+		}
+	}
+
+	if (device1Base <= device0Base && device1Base <= device2Base) {
+		if ((device1Base + device1Length) > device0Base ||
+		    (device1Base + device1Length) > device2Base)
+			return false;
+		if (device0Base <= device2Base) {
+			if ((device0Base + device0Length) > device2Base)
+				return false;
+		} else {
+			if ((device2Base + device2Length) > device0Base)
+				return false;
+		}
+	}
+
+	if (device2Base <= device1Base && device2Base <= device0Base) {
+		if ((device2Base + device2Length) > device1Base ||
+		    (device2Base + device2Length) > device0Base)
+			return false;
+		if (device0Base <= device1Base) {
+			if ((device0Base + device0Length) > device1Base)
+				return false;
+		} else {
+			if ((device1Base + device1Length) > device0Base)
+				return false;
+		}
+	}
+
+	if ((deviceBank2Top > deviceBank1Top) && (deviceBank1Top >
+						  deviceBank0Top)) {
+		device0BaseTemp = device0Base >> 21;
+		device0TopTemp =
+		    ((unsigned int) (deviceBank2Top & 0x0fffffff)) >> 21;
+	}
+	if ((deviceBank2Top > deviceBank0Top)
+	    && (deviceBank0Top > deviceBank1Top)) {
+		device0BaseTemp = device1Base >> 21;
+		device0TopTemp =
+		    ((unsigned int) (deviceBank2Top & 0x0fffffff)) >> 21;
+	}
+	if ((deviceBank1Top > deviceBank2Top)
+	    && (deviceBank2Top > deviceBank0Top)) {
+		device0BaseTemp = device0Base >> 21;
+		device0TopTemp =
+		    ((unsigned int) (deviceBank1Top & 0x0fffffff)) >> 21;
+	}
+	if ((deviceBank1Top > deviceBank0Top)
+	    && (deviceBank0Top > deviceBank2Top)) {
+		device0BaseTemp = device2Base >> 21;
+		device0TopTemp =
+		    ((unsigned int) (deviceBank1Top & 0x0fffffff)) >> 21;
+	}
+	if ((deviceBank0Top > deviceBank2Top)
+	    && (deviceBank2Top > deviceBank1Top)) {
+		device0BaseTemp = device1Base >> 21;
+		device0TopTemp =
+		    ((unsigned int) (deviceBank0Top & 0x0fffffff)) >> 21;
+	}
+	if ((deviceBank0Top > deviceBank1Top)
+	    && (deviceBank1Top > deviceBank2Top)) {
+		device0BaseTemp = device2Base >> 21;
+		device0TopTemp =
+		    ((unsigned int) (deviceBank0Top & 0x0fffffff)) >> 21;
+	}
+	GT_REG_WRITE(CS_2_0_LOW_DECODE_ADDRESS, device0BaseTemp);
+	if ((device0Length + device1Length + device2Length) != 0) {
+		GT_REG_WRITE(CS_2_0_HIGH_DECODE_ADDRESS,
+			     device0TopTemp - 1);
+	} else {
+		GT_REG_WRITE(CS_2_0_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(CS_0_LOW_DECODE_ADDRESS, bank0Base);
+	if (device0Length != 0) {
+		GT_REG_WRITE(CS_0_HIGH_DECODE_ADDRESS, bank0Top - 1);
+	} else {
+		GT_REG_WRITE(CS_0_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(CS_1_LOW_DECODE_ADDRESS, bank1Base);
+	if (device1Length != 0) {
+		GT_REG_WRITE(CS_1_HIGH_DECODE_ADDRESS, bank1Top - 1);
+	} else {
+		GT_REG_WRITE(CS_1_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(CS_2_LOW_DECODE_ADDRESS, bank2Base);
+	if (device2Length != 0) {
+		GT_REG_WRITE(CS_2_HIGH_DECODE_ADDRESS, bank2Top - 1);
+	} else {
+		GT_REG_WRITE(CS_2_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	return true;
+}
+
+/********************************************************************
+* mapDevices3andBootMemorySpace - Sets new bases and boundaries for devices: 
+*                                 3 and boot
+*                     - Pay attention to the PCI mappings and make sure to 
+*                       coordinate between the two interfaces!!!
+*                     - It is the programmer`s responsibility to make sure 
+*                       there are no conflicts with other memory spaces!!!
+*                     - If a device needs to be closed , give it a 0 length.
+*
+* INPUTS: base and length of device 3and boot
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool mapDevices3andBootMemorySpace(unsigned int device3Base,
+				   unsigned int device3Length,
+				   unsigned int bootDeviceBase,
+				   unsigned int bootDeviceLength)
+{
+	unsigned int deviceBank3Top =
+	    (unsigned int) (device3Base + device3Length);
+	unsigned int deviceBankBootTop =
+	    (unsigned int) (bootDeviceBase + bootDeviceLength);
+	unsigned int bank3Base, bank3Top;
+	unsigned int bank4Base, bank4Top;
+	unsigned int Device1Base, Device1Top;
+
+	bank3Top = ((unsigned int) (deviceBank3Top & 0x0fffffff)) >> 20;
+	bank4Top = ((unsigned int) (deviceBankBootTop & 0x0fffffff)) >> 20;
+	bank3Base = ((unsigned int) (device3Base & 0x0fffffff)) >> 20;
+	bank4Base = ((unsigned int) (bootDeviceBase & 0x0fffffff)) >> 20;
+
+	if (device3Base <= bootDeviceBase) {
+		if (deviceBank3Top > bootDeviceBase)
+			return false;
+	} else {
+		if (deviceBankBootTop > device3Base)
+			return false;
+	}
+
+	if (deviceBankBootTop > deviceBank3Top) {
+		Device1Base = device3Base >> 21;
+		Device1Top =
+		    ((unsigned int) (deviceBankBootTop & 0x0fffffff)) >>
+		    21;
+	} else {
+		Device1Base = bootDeviceBase >> 21;
+		Device1Top =
+		    ((unsigned int) (deviceBank3Top & 0x0fffffff)) >> 21;
+	}
+	GT_REG_WRITE(CS_3_BOOTCS_LOW_DECODE_ADDRESS, Device1Base);
+	if ((device3Length + bootDeviceLength) != 0) {
+		GT_REG_WRITE(CS_3_BOOTCS_HIGH_DECODE_ADDRESS,
+			     Device1Top - 1);
+	} else {
+		GT_REG_WRITE(CS_3_BOOTCS_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(CS_3_LOW_DECODE_ADDRESS, bank3Base);
+	if (device3Length != 0) {
+		GT_REG_WRITE(CS_3_HIGH_DECODE_ADDRESS, bank3Top - 1);
+	} else {
+		GT_REG_WRITE(CS_3_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	GT_REG_WRITE(BOOTCS_LOW_DECODE_ADDRESS, bank4Base);
+	if (bootDeviceLength != 0) {
+		GT_REG_WRITE(BOOTCS_HIGH_DECODE_ADDRESS, bank4Top - 1);
+	} else {
+		GT_REG_WRITE(BOOTCS_HIGH_DECODE_ADDRESS, 0x0);
+	}
+	return true;
+}
+
+/********************************************************************
+* modifyDeviceParameters - This function can be used to modify a device`s 
+*                          parameters.
+*                        - Be advised to check the spec before modifying them.
+* Inputs:
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool modifyDeviceParameters(DEVICE device, unsigned int turnOff,
+			    unsigned int accToFirst,
+			    unsigned int accToNext, unsigned int aleToWr,
+			    unsigned int wrActive, unsigned int wrHigh,
+			    unsigned int width, bool paritySupport)
+{
+	unsigned int data, oldValue;
+
+	if ((turnOff > 0x7 && turnOff != DONT_MODIFY)
+	    || (accToFirst > 0xf && accToFirst != DONT_MODIFY)
+	    || (accToNext > 0xf && accToNext != DONT_MODIFY)
+	    || (aleToWr > 0x7 && aleToWr != DONT_MODIFY)
+	    || (wrActive > 0x7 && wrActive != DONT_MODIFY)
+	    || (wrHigh > 0x7 && wrHigh != DONT_MODIFY)) {
+		return false;
+	}
+
+	GT_REG_READ((DEVICE_BANK0PARAMETERS + device * 4), &oldValue);
+	if (turnOff == DONT_MODIFY)
+		turnOff = oldValue & 0x00000007;
+	else
+		turnOff = turnOff;
+
+	if (accToFirst == DONT_MODIFY)
+		accToFirst = oldValue & 0x00000078;
+	else
+		accToFirst = accToFirst << 3;
+
+	if (accToNext == DONT_MODIFY)
+		accToNext = oldValue & 0x00000780;
+	else
+		accToNext = accToNext << 7;
+
+	if (aleToWr == DONT_MODIFY)
+		aleToWr = oldValue & 0x00003800;
+	else
+		aleToWr = aleToWr << 11;
+
+	if (wrActive == DONT_MODIFY)
+		wrActive = oldValue & 0x0001c000;
+	else
+		wrActive = wrActive << 14;
+
+	if (wrHigh == DONT_MODIFY)
+		wrHigh = oldValue & 0x000e0000;
+	else
+		wrHigh = wrHigh << 17;
+
+	data =
+	    turnOff | accToFirst | accToNext | aleToWr | wrActive | wrHigh;
+	switch (width) {
+	case _8BIT:
+		break;
+	case _16BIT:
+		data = data | _16BIT;
+		break;
+	case _32BIT:
+		data = data | _32BIT;
+		break;
+	case _64BIT:
+		data = data | _64BIT;
+		break;
+	default:
+		return false;
+	}
+	if (paritySupport == true)
+		data = data | PARITY_SUPPORT;
+	GT_REG_WRITE(DEVICE_BANK0PARAMETERS + device * 4, data);
+	return true;
+}
+
+/********************************************************************
+* remapAddress - This fubction used for address remapping 
+* Inputs:      - regOffset: remap register 
+*                remapHeader : remapped address
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool remapAddress(unsigned int remapReg, unsigned int remapValue)
+{
+	unsigned int valueForReg;
+	valueForReg = (remapValue & 0xffe00000) >> 21;
+	GT_REG_WRITE(remapReg, valueForReg);
+	return true;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/misc.c linux/arch/mips/galileo-boards/ev64120/compressed/misc.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/misc.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/misc.c	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,313 @@
+/*
+ * arch/mips/galileo/misc.c
+ * 
+ * This is a collection of several routines from gzip-1.0.3 
+ * adapted for Linux.
+ *
+ * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
+ * puts by Nick Holloway 1993, better puts by Martin Mares 1995
+ * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
+ *
+ * Modified by RidgeRun Inc.
+ */
+
+#include <linux/vmalloc.h>
+#include <asm/io.h>
+/*
+ * gzip declarations
+ */
+
+#define OF(args)  args
+#define STATIC static
+
+#define channel 1
+
+#undef memset
+#undef memcpy
+#define memzero(s, n)     memset ((s), 0, (n))
+
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+			     /* and a power of two */
+
+static uch *inbuf;		/* input buffer */
+static uch window[WSIZE];	/* Sliding window buffer */
+
+static unsigned insize = 0;	/* valid bytes in inbuf */
+static unsigned inptr = 0;	/* index of next byte to be processed in inbuf */
+static unsigned outcnt = 0;	/* bytes in output buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01	/* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02	/* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04	/* bit 2 set: extra field present */
+#define ORIG_NAME    0x08	/* bit 3 set: original file name present */
+#define COMMENT      0x10	/* bit 4 set: file comment present */
+#define ENCRYPTED    0x20	/* bit 5 set: file is encrypted */
+#define RESERVED     0xC0	/* bit 6,7:   reserved */
+
+void variable_init();
+static void puts(const char *);
+
+void int2hex(int i)
+{
+	int tth, th, h, t, d;
+
+	if (i > 99999) {
+		serial_putc(channel, "Error - int2hex outofbounds");
+		return;
+	}
+
+	tth = (i) / 10000;
+	th = (i - (tth * 10000)) / 1000;
+	h = (i - ((tth * 10000) + (th * 1000))) / 100;
+	t = (i - ((tth * 10000) + (th * 1000) + (h * 100))) / 10;
+	d = (i - ((tth * 10000) + (th * 1000) + (h * 100) + (t * 10)));
+	serial_putc(channel, tth + '0');
+	serial_putc(channel, th + '0');
+	serial_putc(channel, h + '0');
+	serial_putc(channel, t + '0');
+	serial_putc(channel, d + '0');
+}
+
+int checksum;
+int byte_count;
+static unsigned char *input_data;
+
+static int printCnt = 0;
+
+int get_byte()
+{
+	unsigned char c = (inptr < insize ? inbuf[inptr++] : fill_inbuf());
+	byte_count++;
+	checksum += c;
+
+	// if (printCnt++ < 150)
+	// {
+	//   puts("\n");
+	//   puts("byte count = ");
+	//   int2hex(byte_count & 0xff);
+	//   puts(" byte val = ");
+	//   int2hex(c);
+	//   puts(" checksum = ");
+	//   int2hex(checksum & 0xff);
+	//   puts("\n");
+	// }
+	return c;
+}
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+
+
+#define STACK_SIZE (4096)
+long user_stack[STACK_SIZE];
+long *stack_start = &user_stack[STACK_SIZE];
+
+extern int linux_compressed_start;
+extern int linux_compressed_size;
+extern int malloc_start;
+
+static int input_len;
+
+static long bytes_out = 0;
+extern int kernel_location_start;
+static uch *output_data;
+static unsigned long output_ptr = 0;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#include "../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size < 0)
+		error("Malloc error\n");
+	//      if (free_mem_ptr <= 0) error("Memory error\n");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *) free_mem_ptr;
+	free_mem_ptr += size;
+
+	if (free_mem_ptr >= free_mem_end_ptr)
+		error("\nOut of memory\n");
+
+	return p;
+}
+
+static void free(void *where)
+{				/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+
+static void puts(const char *s)
+{
+	while (*s) {
+		if (*s == 10)
+			serial_putc(channel, 13);
+		serial_putc(channel, *s++);
+	}
+}
+
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+	return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+	return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+	if (insize != 0) {
+		error("ran out of input data\n");
+	}
+
+	inbuf = input_data;
+	insize = input_len;
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+	ulg c = crc;		/* temporary variable */
+	unsigned n;
+	uch *in, *out, ch;
+
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg) outcnt;
+	output_ptr += (ulg) outcnt;
+	outcnt = 0;
+}
+
+check_mem()
+{
+	int i;
+
+	puts("\ncplens = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplens[i]);
+		puts(" ");
+	}
+	puts("\ncplext = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(cplext[i]);
+		puts(" ");
+	}
+	puts("\nborder = ");
+	for (i = 0; i < 10; i++) {
+		int2hex(border[i]);
+		puts(" ");
+	}
+	puts("\n");
+}
+
+static void error(char *x)
+{
+	check_mem();
+	puts("\n\n");
+	puts(x);
+	puts("byte_count = ");
+	int2hex(byte_count);
+	puts("\n");
+	puts("\n\n -- System halted");
+	while (1);		/* Halt */
+}
+
+void variable_init()
+{
+	byte_count = 0;
+	checksum = 0;
+	input_data = (unsigned char *) &linux_compressed_start;
+	input_len = linux_compressed_size;
+	output_data = &kernel_location_start;
+	free_mem_ptr = (long) &malloc_start;
+	free_mem_end_ptr = (long) ((char *) &malloc_start + 0x400000);
+}
+
+int decompress_kernel()
+{
+	//check_mem();
+
+	variable_init();
+
+	makecrc();
+	puts("Uncompressing Linux... \n");
+	gunzip();		// ...see inflate.c
+	puts("Ok, booting the kernel.\n");
+	return 0;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/ns16550.h linux/arch/mips/galileo-boards/ev64120/compressed/ns16550.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/ns16550.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/ns16550.h	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,126 @@
+/*  NS16550 UART registers  */
+
+#ifndef NS16550H
+#define NS16550H
+
+#define UART_BASE		0xbd000000
+#define NS16550_CHANA   PHYS_TO_K1(UART_BASE + 0x20)
+#define NS16550_CHANB   PHYS_TO_K1(UART_BASE)
+
+#ifndef NS16550_HZ
+#define NS16550_HZ      3686400
+#endif
+
+#ifdef __ASSEMBLY__
+
+#ifndef NSREG
+#define NSREG(x) ((x)*4)
+#endif
+
+#define DATA	NSREG(0)	/* data register (R/W) */
+#define IER	    NSREG(1)	/* interrupt enable (W) */
+#define IIR	    NSREG(2)	/* interrupt identification (R) */
+#define	FIFO	IIR		/* 16550 fifo control (W) */
+#define CFCR	NSREG(3)	/* line control register (R/W) */
+#define MCR	    NSREG(4)	/* modem control register (R/W) */
+#define LSR	    NSREG(5)	/* line status register (R/W) */
+#define MSR	    NSREG(6)	/* modem status register (R/W) */
+#define SCR	    NSREG(7)	/* scratch register (R/W) */
+
+#else
+
+#ifndef nsreg
+#if #endian(little)
+#define nsreg(x)	unsigned :24; unsigned char x;
+#else
+/*#define nsreg(x)	unsigned char x; unsigned :24;*/
+#define nsreg(x) unsigned int x:8;unsigned int :24;
+#endif
+#endif
+
+typedef struct {
+	nsreg(data);		/* data register (R/W) */
+	nsreg(ier);		/* interrupt enable (W) */
+	nsreg(iir);		/* interrupt identification (R) */
+#define	fifo	iir		/* 16550 fifo control (W) */
+	nsreg(cfcr);		/* line control register (R/W) */
+	nsreg(mcr);		/* modem control register (R/W) */
+	nsreg(lsr);		/* line status register (R/W) */
+	nsreg(msr);		/* modem status register (R/W) */
+	nsreg(scr);		/* scratch register (R/W) */
+} ns16550dev;
+#endif
+
+
+/* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */
+#define BRTC(x)         (NS16550_HZ / (16*(x)))
+
+/* interrupt enable register */
+#define IER_ERXRDY      0x1	/* int on rx ready */
+#define IER_ETXRDY      0x2	/* int on tx ready */
+#define IER_ERLS        0x4	/* int on line status change */
+#define IER_EMSC        0x8	/* int on modem status change */
+
+/* interrupt identification register */
+#define IIR_IMASK       0xf	/* mask */
+#define IIR_RXTOUT      0xc	/* receive timeout */
+#define IIR_RLS         0x6	/* receive line status */
+#define IIR_RXRDY       0x4	/* receive ready */
+#define IIR_TXRDY       0x2	/* transmit ready */
+#define IIR_NOPEND      0x1	/* nothing */
+#define IIR_MLSC        0x0	/* modem status */
+#define IIR_FIFO_MASK   0xc0	/* set if FIFOs are enabled */
+
+/* fifo control register */
+#define FIFO_ENABLE     0x01	/* enable fifo */
+#define FIFO_RCV_RST    0x02	/* reset receive fifo */
+#define FIFO_XMT_RST    0x04	/* reset transmit fifo */
+#define FIFO_DMA_MODE   0x08	/* enable dma mode */
+#define FIFO_TRIGGER_1  0x00	/* trigger at 1 char */
+#define FIFO_TRIGGER_4  0x40	/* trigger at 4 chars */
+#define FIFO_TRIGGER_8  0x80	/* trigger at 8 chars */
+#define FIFO_TRIGGER_14 0xc0	/* trigger at 14 chars */
+
+/* character format control register */
+#define CFCR_DLAB       0x80	/* divisor latch */
+#define CFCR_SBREAK     0x40	/* send break */
+#define CFCR_PZERO      0x30	/* zero parity */
+#define CFCR_PONE       0x20	/* one parity */
+#define CFCR_PEVEN      0x10	/* even parity */
+#define CFCR_PODD       0x00	/* odd parity */
+#define CFCR_PENAB      0x08	/* parity enable */
+#define CFCR_STOPB      0x04	/* 2 stop bits */
+#define CFCR_8BITS      0x03	/* 8 data bits */
+#define CFCR_7BITS      0x02	/* 7 data bits */
+#define CFCR_6BITS      0x01	/* 6 data bits */
+#define CFCR_5BITS      0x00	/* 5 data bits */
+
+/* modem control register */
+#define MCR_LOOPBACK    0x10	/* loopback */
+#define MCR_IENABLE     0x08	/* output 2 = int enable */
+#define MCR_DRS         0x04	/* output 1 = xxx */
+#define MCR_RTS         0x02	/* enable RTS */
+#define MCR_DTR         0x01	/* enable DTR */
+
+/* line status register */
+#define LSR_RCV_FIFO    0x80	/* error in receive fifo */
+#define LSR_TSRE        0x40	/* transmitter empty */
+#define LSR_TXRDY       0x20	/* transmitter ready */
+#define LSR_BI          0x10	/* break detected */
+#define LSR_FE          0x08	/* framing error */
+#define LSR_PE          0x04	/* parity error */
+#define LSR_OE          0x02	/* overrun error */
+#define LSR_RXRDY       0x01	/* receiver ready */
+#define LSR_RCV_MASK    0x1f
+
+/* modem status register */
+#define MSR_DCD         0x80	/* DCD active */
+#define MSR_RI          0x40	/* RI  active */
+#define MSR_DSR         0x20	/* DSR active */
+#define MSR_CTS         0x10	/* CTS active */
+#define MSR_DDCD        0x08	/* DCD changed */
+#define MSR_TERI        0x04	/* RI  changed */
+#define MSR_DDSR        0x02	/* DSR changed */
+#define MSR_DCTS        0x01	/* CTS changed */
+
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/osdep.h linux/arch/mips/galileo-boards/ev64120/compressed/osdep.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/osdep.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/osdep.h	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,36 @@
+#ifndef	__OSDEP_H__
+#define __OSDEP_H__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#if	defined(__linux__) || defined(__FreeBSD__) || defined (__MIPSEB__)
+#define	ETHERBOOT32
+#define ntohl(x) (x)
+#define htonl(x) (x)
+#define ntohs(x) (x)
+#define htons(x) (x)
+
+#endif
+
+
+
+
+/* ANSI prototyping macro */
+#ifdef	__STDC__
+#define	P(x)	x
+#else
+#define	P(x)	()
+#endif
+
+#endif
+
+/*
+ * Local variables:
+ *  c-basic-offset: 8
+ * End:
+ */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/pci.c linux/arch/mips/galileo-boards/ev64120/compressed/pci.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/pci.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/pci.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,1336 @@
+/* PCI.c - PCI functions */
+
+/* Copyright - Galileo technology. */
+
+#ifdef __linux__
+#include <asm/galileo-boards/evb64120A/core.h>
+#include <asm/galileo-boards/evb64120A/pci.h>
+#ifndef PROM
+#include <linux/kernel.h>
+#endif
+
+#undef PCI_DEBUG
+
+#ifdef PCI_DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#else
+#include "core.h"
+#include "pci.h"
+#include <string.h>
+#endif
+
+/********************************************************************
+* pci0ScanDevices   - This function scan PCI0 bus, if found any device on
+*                     this bus it interrogate the Device for the information 
+*                     it can discover.
+*                     The fields with all information are the following: 
+*    char            type[20];
+*    unsigned int    deviceNum;
+*    unsigned int    venID;                                            
+*    unsigned int    deviceID;
+*    unsigned int    bar0Base;
+*    unsigned int    bar0Size;
+*    unsigned int    bar1Base;
+*    unsigned int    bar1Size;
+*    unsigned int    bar2Base;
+*    unsigned int    bar2Size;
+*    unsigned int    bar3Base;
+*    unsigned int    bar3Size;
+*    unsigned int    bar4Base;
+*    unsigned int    bar4Size;
+*    unsigned int    bar5Base;
+*    unsigned int    bar5Size;
+* 
+* Inputs:   PCI0_DEVICE* pci0Detect - Pointer to an array of STRUCT PCI0_DEVICE.
+*           unsigned int numberOfElment - The PCI0_DEVICE Array length.
+* Output:   None.
+*********************************************************************/
+
+void pci0ScanDevices(PCI_DEVICE * pci0Detect, unsigned int numberOfElment)
+{
+	PCI_DEVICE *pci0ArrayPointer = pci0Detect;
+	unsigned int id;	/* PCI Configuration register 0x0. */
+	unsigned int device;	/* device`s Counter. */
+	unsigned int classCode;	/* PCI Configuration register 0x8 */
+	unsigned int arrayCounter = 0;
+	unsigned int memBaseAddress;
+	unsigned int memSize;
+	unsigned int c18RegValue;
+
+	PCI0_MASTER_ENABLE(SELF);
+	/* According to PCI REV 2.1 MAX agents on the bus are -21- */
+	for (device = 6; device < 8; device++) {
+		id = pci0ReadConfigReg(PCI_0DEVICE_AND_VENDOR_ID, device);
+		GT_REG_READ(INTERRUPT_CAUSE_REGISTER, &c18RegValue);
+		/* Clearing bit 18 of in the Cause Register 0xc18 by writting 0. */
+		GT_REG_WRITE(INTERRUPT_CAUSE_REGISTER,
+			     c18RegValue & 0xfffbffff);
+		if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) {
+			classCode =
+			    pci0ReadConfigReg
+			    (PCI_0CLASS_CODE_AND_REVISION_ID, device);
+			pci0ArrayPointer->deviceNum = device;
+			pci0ArrayPointer->venID = (id & 0xffff);
+			pci0ArrayPointer->deviceID =
+			    ((id & 0xffff0000) >> 16);
+			DBG("\nrr: venID %x devID %x\n",
+			    pci0ArrayPointer->venID,
+			    pci0ArrayPointer->deviceID);
+			DBG("rr: device found %x\n",
+			    pci0ArrayPointer->deviceNum);
+			/* BAR0 parameters */
+			memBaseAddress = pci0ReadConfigReg(BAR0, device);
+			pci0ArrayPointer->bar0Type = memBaseAddress & 1;
+			pci0ArrayPointer->bar0Base =
+			    memBaseAddress & 0xfffff000;
+			pci0WriteConfigReg(BAR0, device, 0xffffffff);
+			memSize = pci0ReadConfigReg(BAR0, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci0ArrayPointer->bar0Size = 0;
+			} else {
+				if (pci0ArrayPointer->bar0Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci0ArrayPointer->bar0Size = memSize;
+			}
+			DBG("rr: device BAR0 size %x\n", memSize);
+			DBG("rr: device BAR0 address %x\n",
+			    memBaseAddress);
+			pci0WriteConfigReg(BAR0, device, memBaseAddress);
+			/* BAR1 parameters */
+			memBaseAddress = pci0ReadConfigReg(BAR1, device);
+			pci0ArrayPointer->bar1Type = memBaseAddress & 1;
+			pci0ArrayPointer->bar1Base =
+			    memBaseAddress & 0xfffff000;
+			pci0WriteConfigReg(BAR1, device, 0xffffffff);
+			memSize = pci0ReadConfigReg(BAR1, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci0ArrayPointer->bar1Size = 0;
+			} else {
+				if (pci0ArrayPointer->bar1Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci0ArrayPointer->bar1Size = memSize;
+			}
+			DBG("rr: device BAR1 size %x\n", memSize);
+			DBG("rr: device BAR1 address %x\n",
+			    memBaseAddress);
+			pci0WriteConfigReg(BAR1, device, memBaseAddress);
+			/* BAR2 parameters */
+			memBaseAddress = pci0ReadConfigReg(BAR2, device);
+			pci0ArrayPointer->bar2Type = memBaseAddress & 1;
+			pci0ArrayPointer->bar2Base =
+			    memBaseAddress & 0xfffff000;
+			pci0WriteConfigReg(BAR2, device, 0xffffffff);
+			memSize = pci0ReadConfigReg(BAR2, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci0ArrayPointer->bar2Size = 0;
+			} else {
+				if (pci0ArrayPointer->bar2Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci0ArrayPointer->bar2Size = memSize;
+			}
+			DBG("rr: device BAR2 size %x\n", memSize);
+			DBG("rr: device BAR2 address %x\n",
+			    memBaseAddress);
+			pci0WriteConfigReg(BAR2, device, memBaseAddress);
+			/* BAR3 parameters */
+			memBaseAddress = pci0ReadConfigReg(BAR3, device);
+			pci0ArrayPointer->bar3Type = memBaseAddress & 1;
+			pci0ArrayPointer->bar3Base =
+			    memBaseAddress & 0xfffff000;
+			pci0WriteConfigReg(BAR3, device, 0xffffffff);
+			memSize = pci0ReadConfigReg(BAR3, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci0ArrayPointer->bar3Size = 0;
+			} else {
+				if (pci0ArrayPointer->bar3Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci0ArrayPointer->bar3Size = memSize;
+			}
+			DBG("rr: device BAR3 size %x\n", memSize);
+			DBG("rr: device BAR3 address %x\n",
+			    memBaseAddress);
+			pci0WriteConfigReg(BAR3, device, memBaseAddress);
+			/* BAR4 parameters */
+			memBaseAddress = pci0ReadConfigReg(BAR4, device);
+			pci0ArrayPointer->bar4Type = memBaseAddress & 1;
+			pci0ArrayPointer->bar4Base =
+			    memBaseAddress & 0xfffff000;
+			pci0WriteConfigReg(BAR4, device, 0xffffffff);
+			memSize = pci0ReadConfigReg(BAR4, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci0ArrayPointer->bar4Size = 0;
+			} else {
+				if (pci0ArrayPointer->bar4Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci0ArrayPointer->bar4Size = memSize;
+			}
+			DBG("rr: device BAR4 size %x\n", memSize);
+			DBG("rr: device BAR4 address %x\n",
+			    memBaseAddress);
+			pci0WriteConfigReg(BAR4, device, memBaseAddress);
+			/* BAR5 parameters */
+			memBaseAddress = pci0ReadConfigReg(BAR5, device);
+			pci0ArrayPointer->bar5Type = memBaseAddress & 1;
+			pci0ArrayPointer->bar5Base =
+			    memBaseAddress & 0xfffff000;
+			pci0WriteConfigReg(BAR5, device, 0xffffffff);
+			memSize = pci0ReadConfigReg(BAR5, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci0ArrayPointer->bar5Size = 0;
+			} else {
+				if (pci0ArrayPointer->bar5Type == 1)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci0ArrayPointer->bar5Size = memSize;
+			}
+			DBG("rr: device BAR5 size %x\n", memSize);
+			DBG("rr: device BAR5 address %x\n",
+			    memBaseAddress);
+			pci0WriteConfigReg(BAR5, device, memBaseAddress);
+			/* End of BARs Detection. */
+
+			classCode = ((classCode & 0xff000000) >> 24);
+			switch (classCode) {
+			case 0x0:
+				strcpy(pci0ArrayPointer->type,
+				       "Old generation device");
+				break;
+			case 0x1:
+				strcpy(pci0ArrayPointer->type,
+				       "Mass storage controller");
+				break;
+			case 0x2:
+				strcpy(pci0ArrayPointer->type,
+				       "Network controller");
+				break;
+			case 0x3:
+				strcpy(pci0ArrayPointer->type,
+				       "Display controller");
+				break;
+			case 0x4:
+				strcpy(pci0ArrayPointer->type,
+				       "Multimedia device");
+				break;
+			case 0x5:
+				strcpy(pci0ArrayPointer->type,
+				       "Memory controller");
+				break;
+			case 0x6:
+				strcpy(pci0ArrayPointer->type,
+				       "Bridge Device");
+				break;
+			case 0x7:
+				strcpy(pci0ArrayPointer->type,
+				       "Simple Communication controllers");
+				break;
+			case 0x8:
+				strcpy(pci0ArrayPointer->type,
+				       "Base system peripherals");
+				break;
+			case 0x9:
+				strcpy(pci0ArrayPointer->type,
+				       "Input Devices");
+				break;
+			case 0xa:
+				strcpy(pci0ArrayPointer->type,
+				       "Docking stations");
+				break;
+			case 0xb:
+				strcpy(pci0ArrayPointer->type,
+				       "Processors");
+				break;
+			case 0xc:
+				strcpy(pci0ArrayPointer->type,
+				       "Serial bus controllers");
+				break;
+			case 0xd:
+				strcpy(pci0ArrayPointer->type,
+				       "Wireless controllers");
+				break;
+			case 0xe:
+				strcpy(pci0ArrayPointer->type,
+				       "Intelligent I/O controllers");
+				break;
+			case 0xf:
+				strcpy(pci0ArrayPointer->type,
+				       "Satellite communication controllers");
+				break;
+			case 0x10:
+				strcpy(pci0ArrayPointer->type,
+				       "Encryption/Decryption controllers");
+				break;
+			case 0x11:
+				strcpy(pci0ArrayPointer->type,
+				       "Data acquisition and signal processing controllers");
+				break;
+			default:
+				break;
+
+			}
+			arrayCounter++;	/* point to the next element in the Array. */
+			if (arrayCounter == numberOfElment)
+				return;	/* When the Array is fully used, return. */
+			/* Else, points to next free Element. */
+			pci0ArrayPointer = &pci0Detect[arrayCounter];
+		}
+	}
+	pci0ArrayPointer->deviceNum = 0;	/* 0 => End of List */
+}
+
+
+/********************************************************************
+* pci1ScanDevices   - This function scan PCI1 bus, if found any device on
+*                     this bus it interrogate the Device for the information 
+*                     it can discover.
+*                     The fields with all information are the following: 
+*    char            type[20];
+*    unsigned int    deviceNum;
+*    unsigned int    venID;                                            
+*    unsigned int    deviceID;
+*    unsigned int    bar0Base;
+*    unsigned int    bar0Size;
+*    unsigned int    bar1Base;
+*    unsigned int    bar1Size;
+*    unsigned int    bar2Base;
+*    unsigned int    bar2Size;
+*    unsigned int    bar3Base;
+*    unsigned int    bar3Size;
+*    unsigned int    bar4Base;
+*    unsigned int    bar4Size;
+*    unsigned int    bar5Base;
+*    unsigned int    bar5Size;
+* 
+* Inputs:   Pointer to an array of STRUCT PCI1_DEVICE. 
+* Output:   None.
+*********************************************************************/
+
+void pci1ScanDevices(PCI_DEVICE * pci1Detect, unsigned int numberOfElment)
+{
+	PCI_DEVICE *pci1ArrayPointer = pci1Detect;
+	unsigned int id;	/* PCI Configuration register 0x0. */
+	unsigned int device;	/* device`s Counter. */
+	unsigned int classCode;	/* PCI Configuration register 0x8 */
+	unsigned int arrayCounter = 0;
+	unsigned int memBaseAddress;
+	unsigned int memSize;
+	unsigned int c98RegValue;
+
+	PCI1_MASTER_ENABLE(SELF);
+	/* According to PCI REV 2.1 MAX agents on the bus are -21- */
+	for (device = 1; device < 22; device++) {
+		id = pci1ReadConfigReg(PCI_0DEVICE_AND_VENDOR_ID, device);
+		GT_REG_READ(HIGH_INTERRUPT_CAUSE_REGISTER, &c98RegValue);
+		/* Clearing bit 18 of in the High Cause Register 0xc98 */
+		GT_REG_WRITE(HIGH_INTERRUPT_CAUSE_REGISTER,
+			     c98RegValue & 0xfffbffff);
+		if ((id != 0xffffffff) && !(c98RegValue & 0x40000)) {
+			classCode =
+			    pci1ReadConfigReg
+			    (PCI_0CLASS_CODE_AND_REVISION_ID, device);
+			pci1ArrayPointer->deviceNum = device;
+			pci1ArrayPointer->venID = (id & 0xffff);
+			pci1ArrayPointer->deviceID =
+			    ((id & 0xffff0000) >> 16);
+
+			/* BAR0 parameters */
+			memBaseAddress = pci1ReadConfigReg(BAR0, device);
+			pci1ArrayPointer->bar0Type = memBaseAddress & 1;
+			pci1ArrayPointer->bar0Base =
+			    memBaseAddress & 0xfffff000;
+			pci1WriteConfigReg(BAR0, device, 0xffffffff);
+			memSize = pci1ReadConfigReg(BAR0, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci1ArrayPointer->bar0Size = 0;
+			} else {
+				if (pci1ArrayPointer->bar0Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci1ArrayPointer->bar0Size = memSize;
+			}
+			pci1WriteConfigReg(BAR0, device, memBaseAddress);
+			/* BAR1 parameters */
+			memBaseAddress = pci1ReadConfigReg(BAR1, device);
+			pci1ArrayPointer->bar1Type = memBaseAddress & 1;
+			pci1ArrayPointer->bar1Base =
+			    memBaseAddress & 0xfffff000;
+			pci1WriteConfigReg(BAR1, device, 0xffffffff);
+			memSize = pci1ReadConfigReg(BAR1, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci1ArrayPointer->bar1Size = 0;
+			} else {
+				if (pci1ArrayPointer->bar1Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci1ArrayPointer->bar1Size = memSize;
+			}
+			pci1WriteConfigReg(BAR1, device, memBaseAddress);
+			/* BAR2 parameters */
+			memBaseAddress = pci1ReadConfigReg(BAR2, device);
+			pci1ArrayPointer->bar2Type = memBaseAddress & 1;
+			pci1ArrayPointer->bar2Base =
+			    memBaseAddress & 0xfffff000;
+			pci1WriteConfigReg(BAR2, device, 0xffffffff);
+			memSize = pci1ReadConfigReg(BAR2, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci1ArrayPointer->bar2Size = 0;
+			} else {
+				if (pci1ArrayPointer->bar2Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci1ArrayPointer->bar2Size = memSize;
+			}
+			pci1WriteConfigReg(BAR2, device, memBaseAddress);
+			/* BAR3 parameters */
+			memBaseAddress = pci1ReadConfigReg(BAR3, device);
+			pci1ArrayPointer->bar3Type = memBaseAddress & 1;
+			pci1ArrayPointer->bar3Base =
+			    memBaseAddress & 0xfffff000;
+			pci1WriteConfigReg(BAR3, device, 0xffffffff);
+			memSize = pci1ReadConfigReg(BAR3, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci1ArrayPointer->bar3Size = 0;
+			} else {
+				if (pci1ArrayPointer->bar3Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci1ArrayPointer->bar3Size = memSize;
+			}
+			pci1WriteConfigReg(BAR3, device, memBaseAddress);
+			/* BAR4 parameters */
+			memBaseAddress = pci1ReadConfigReg(BAR4, device);
+			pci1ArrayPointer->bar4Type = memBaseAddress & 1;
+			pci1ArrayPointer->bar4Base =
+			    memBaseAddress & 0xfffff000;
+			pci1WriteConfigReg(BAR4, device, 0xffffffff);
+			memSize = pci1ReadConfigReg(BAR4, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci1ArrayPointer->bar4Size = 0;
+			} else {
+				if (pci1ArrayPointer->bar4Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci1ArrayPointer->bar4Size = memSize;
+			}
+			pci1WriteConfigReg(BAR4, device, memBaseAddress);
+			/* BAR5 parameters */
+			memBaseAddress = pci1ReadConfigReg(BAR5, device);
+			pci1ArrayPointer->bar5Type = memBaseAddress & 1;
+			pci1ArrayPointer->bar5Base =
+			    memBaseAddress & 0xfffff000;
+			pci1WriteConfigReg(BAR5, device, 0xffffffff);
+			memSize = pci1ReadConfigReg(BAR5, device);
+			if (memSize == 0) {	/* case of an empty BAR */
+				pci1ArrayPointer->bar5Size = 0;
+			} else {
+				if (pci1ArrayPointer->bar5Type == 0)	/* memory space */
+					memSize =
+					    ~(memSize & 0xfffffff0) + 1;
+				else	/* IO space */
+					memSize =
+					    ~(memSize & 0xfffffffc) + 1;
+				pci1ArrayPointer->bar5Size = memSize;
+			}
+			pci1WriteConfigReg(BAR5, device, memBaseAddress);
+			/* End of BARs Detection. */
+
+			classCode = ((classCode & 0xff000000) >> 24);
+			switch (classCode) {
+			case 0x0:
+				strcpy(pci1ArrayPointer->type,
+				       "Old generation device");
+				break;
+			case 0x1:
+				strcpy(pci1ArrayPointer->type,
+				       "Mass storage controller");
+				break;
+			case 0x2:
+				strcpy(pci1ArrayPointer->type,
+				       "Network controller");
+				break;
+			case 0x3:
+				strcpy(pci1ArrayPointer->type,
+				       "Display controller");
+				break;
+			case 0x4:
+				strcpy(pci1ArrayPointer->type,
+				       "Multimedia device");
+				break;
+			case 0x5:
+				strcpy(pci1ArrayPointer->type,
+				       "Memory controller");
+				break;
+			case 0x6:
+				strcpy(pci1ArrayPointer->type,
+				       "Bridge Device");
+				break;
+			case 0x7:
+				strcpy(pci1ArrayPointer->type,
+				       "Simple Communication controllers");
+				break;
+			case 0x8:
+				strcpy(pci1ArrayPointer->type,
+				       "Base system peripherals");
+				break;
+			case 0x9:
+				strcpy(pci1ArrayPointer->type,
+				       "Input Devices");
+				break;
+			case 0xa:
+				strcpy(pci1ArrayPointer->type,
+				       "Docking stations");
+				break;
+			case 0xb:
+				strcpy(pci1ArrayPointer->type,
+				       "Processors");
+				break;
+			case 0xc:
+				strcpy(pci1ArrayPointer->type,
+				       "Serial bus controllers");
+				break;
+			case 0xd:
+				strcpy(pci1ArrayPointer->type,
+				       "Wireless controllers");
+				break;
+			case 0xe:
+				strcpy(pci1ArrayPointer->type,
+				       "Intelligent I/O controllers");
+				break;
+			case 0xf:
+				strcpy(pci1ArrayPointer->type,
+				       "Satellite communication controllers");
+				break;
+			case 0x10:
+				strcpy(pci1ArrayPointer->type,
+				       "Encryption/Decryption controllers");
+				break;
+			case 0x11:
+				strcpy(pci1ArrayPointer->type,
+				       "Data acquisition and signal processing controllers");
+				break;
+			}
+			arrayCounter++;	/* point to the next element in the Array. */
+			if (arrayCounter == numberOfElment)
+				return;	/* When the Array is fully used, return. */
+			/* Else, points to next free Element. */
+			pci1ArrayPointer = &pci1Detect[arrayCounter];
+		}
+	}
+	pci1ArrayPointer->deviceNum = 0;	/* 0 => End of List */
+}
+
+/********************************************************************
+* pci0WriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before 
+*                      writingto another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec 
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.                
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+
+void pci0WriteConfigReg(unsigned int regOffset, unsigned int pciDevNum,
+			unsigned int data)
+{
+	unsigned int DataForRegCf8;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0x0fffffff;
+	DataForRegCf8 = (regOffset | pciDevNum | functionNum) | BIT31;
+	GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			     data);
+	} else {		/* configuration Transaction over the pci. */
+
+		/* The PCI is working in LE Mode So it swap the Data. */
+		GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			     WORDSWAP(data));
+	}
+}
+
+/********************************************************************
+* pci1WriteConfigReg - Write to a PCI configuration register
+*                   - Make sure the GT is configured as a master before writing
+*                     to another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* Inputs:   unsigned int regOffset: The register offset as it apears in the  
+*           GT spec (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.                
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+
+void pci1WriteConfigReg(unsigned int regOffset, unsigned int pciDevNum,
+			unsigned int data)
+{
+	unsigned int DataForRegCf8;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0x0fffffff;
+	if (pciDevNum == SELF) {	/* This board */
+		/* when configurating our own PCI 1 L-unit the access is through  
+		   the PCI 0 interface with reg number = reg number + 0x80 */
+		DataForRegCf8 =
+		    (regOffset | pciDevNum | functionNum | 0x80) | BIT31;
+		GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
+	} else {
+		DataForRegCf8 =
+		    (regOffset | pciDevNum | functionNum) | BIT31;
+		GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS, DataForRegCf8);
+	}
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			     data);
+	} else {
+		GT_REG_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			     WORDSWAP(data));
+	}
+}
+
+/********************************************************************
+* pci0ReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before 
+*                      reading from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.                
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the 
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+
+unsigned int pci0ReadConfigReg(unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	unsigned int DataForRegCf8;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0x0fffffff;
+	DataForRegCf8 = (regOffset | pciDevNum | functionNum) | BIT31;
+	GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			    &data);
+		return data;
+	} else {		/* The PCI is working in LE Mode So it swap the Data. */
+
+		GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			    &data);
+		return WORDSWAP(data);
+	}
+}
+
+/********************************************************************
+* pci1ReadConfigReg  - Read from a PCI1 configuration register
+*                    - Make sure the GT is configured as a master before 
+*                      reading from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.                
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the 
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+
+unsigned int pci1ReadConfigReg(unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	unsigned int DataForRegCf8;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0x0fffffff;
+	if (pciDevNum == SELF) {	/* This board */
+		/* when configurating our own PCI 1 L-unit the access is through  
+		   the PCI 0 interface with reg number = reg number + 0x80 */
+		DataForRegCf8 =
+		    (regOffset | pciDevNum | functionNum | 0x80) | BIT31;
+		GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
+	} else {
+		DataForRegCf8 =
+		    (regOffset | pciDevNum | functionNum) | BIT31;
+		GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS, DataForRegCf8);
+	}
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			    &data);
+		return data;
+	} else {
+		GT_REG_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
+			    &data);
+		return WORDSWAP(data);
+	}
+}
+
+/********************************************************************
+* pci0MapIOspace - Maps PCI0 IO space for the master.
+* Inputs: base and length of pci0Io
+*********************************************************************/
+
+void pci0MapIOspace(unsigned int pci0IoBase, unsigned int pci0IoLength)
+{
+	unsigned int pci0IoTop =
+	    (unsigned int) (pci0IoBase + pci0IoLength);
+
+	if (pci0IoLength == 0)
+		pci0IoTop++;
+
+	pci0IoBase = (unsigned int) (pci0IoBase >> 21);
+	pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21);
+	GT_REG_WRITE(PCI_0I_O_LOW_DECODE_ADDRESS, pci0IoBase);
+	GT_REG_WRITE(PCI_0I_O_HIGH_DECODE_ADDRESS, pci0IoTop);
+}
+
+/********************************************************************
+* pci1MapIOspace - Maps PCI1 IO space for the master.
+* Inputs: base and length of pci1Io
+*********************************************************************/
+
+void pci1MapIOspace(unsigned int pci1IoBase, unsigned int pci1IoLength)
+{
+	unsigned int pci1IoTop =
+	    (unsigned int) (pci1IoBase + pci1IoLength);
+
+	if (pci1IoLength == 0)
+		pci1IoTop++;
+
+	pci1IoBase = (unsigned int) (pci1IoBase >> 21);
+	pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21);
+	GT_REG_WRITE(PCI_1I_O_LOW_DECODE_ADDRESS, pci1IoBase);
+	GT_REG_WRITE(PCI_1I_O_HIGH_DECODE_ADDRESS, pci1IoTop);
+}
+
+/********************************************************************
+* pci0MapMemory0space - Maps PCI0 memory0 space for the master.
+* Inputs: base and length of pci0Mem0
+*********************************************************************/
+
+
+void pci0MapMemory0space(unsigned int pci0Mem0Base,
+			 unsigned int pci0Mem0Length)
+{
+	unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length;
+
+	if (pci0Mem0Length == 0)
+		pci0Mem0Top++;
+
+	pci0Mem0Base = pci0Mem0Base >> 21;
+	pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21;
+	GT_REG_WRITE(PCI_0MEMORY0_LOW_DECODE_ADDRESS, pci0Mem0Base);
+	GT_REG_WRITE(PCI_0MEMORY0_HIGH_DECODE_ADDRESS, pci0Mem0Top);
+}
+
+/********************************************************************
+* pci1MapMemory0space - Maps PCI1 memory0 space for the master.
+* Inputs: base and length of pci1Mem0
+*********************************************************************/
+
+void pci1MapMemory0space(unsigned int pci1Mem0Base,
+			 unsigned int pci1Mem0Length)
+{
+	unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length;
+
+	if (pci1Mem0Length == 0)
+		pci1Mem0Top++;
+
+	pci1Mem0Base = pci1Mem0Base >> 21;
+	pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21;
+	GT_REG_WRITE(PCI_1MEMORY0_LOW_DECODE_ADDRESS, pci1Mem0Base);
+	GT_REG_WRITE(PCI_1MEMORY0_HIGH_DECODE_ADDRESS, pci1Mem0Top);
+}
+
+/********************************************************************
+* pci0MapMemory1space - Maps PCI0 memory1 space for the master.
+* Inputs: base and length of pci0Mem1
+*********************************************************************/
+
+void pci0MapMemory1space(unsigned int pci0Mem1Base,
+			 unsigned int pci0Mem1Length)
+{
+	unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length;
+
+	if (pci0Mem1Length == 0)
+		pci0Mem1Top++;
+
+	pci0Mem1Base = pci0Mem1Base >> 21;
+	pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21;
+	GT_REG_WRITE(PCI_0MEMORY1_LOW_DECODE_ADDRESS, pci0Mem1Base);
+	GT_REG_WRITE(PCI_0MEMORY1_HIGH_DECODE_ADDRESS, pci0Mem1Top);
+#ifndef PROM
+	DBG(KERN_INFO "pci0Mem1Base %x\n", pci0Mem1Base);
+	DBG(KERN_INFO "pci0Mem1Top %x\n", pci0Mem1Top);
+	GT_REG_READ(PCI_0MEMORY0_ADDRESS_REMAP, &pci0Mem1Base);
+	DBG(KERN_INFO "Mem 0/0 remap %x\n", pci0Mem1Base);
+	GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base);
+	DBG(KERN_INFO "Mem 0/1 remap %x\n", pci0Mem1Base);
+	GT_REG_WRITE(PCI_0MEMORY1_ADDRESS_REMAP, 0x500);
+	GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base);
+	DBG(KERN_INFO "Mem 0/1 remapped %x\n", pci0Mem1Base);
+#endif
+}
+
+/********************************************************************
+* pci1MapMemory1space - Maps PCI1 memory1 space for the master.
+* Inputs: base and length of pci1Mem1
+*********************************************************************/
+
+void pci1MapMemory1space(unsigned int pci1Mem1Base,
+			 unsigned int pci1Mem1Length)
+{
+	unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length;
+
+	if (pci1Mem1Length == 0)
+		pci1Mem1Top++;
+
+	pci1Mem1Base = pci1Mem1Base >> 21;
+	pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21;
+	GT_REG_WRITE(PCI_1MEMORY1_LOW_DECODE_ADDRESS, pci1Mem1Base);
+	GT_REG_WRITE(PCI_1MEMORY1_HIGH_DECODE_ADDRESS, pci1Mem1Top);
+}
+
+/********************************************************************
+* pci0GetIOspaceBase - Return PCI0 IO Base Address.
+* Inputs: N/A
+* Returns: PCI0 IO Base Address.
+*********************************************************************/
+
+unsigned int pci0GetIOspaceBase()
+{
+	unsigned int base;
+	GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	return base;
+}
+
+/********************************************************************
+* pci0GetIOspaceSize - Return PCI0 IO Bar Size.
+* Inputs: N/A
+* Returns: PCI0 IO Bar Size.
+*********************************************************************/
+
+unsigned int pci0GetIOspaceSize()
+{
+	unsigned int top, base, size;
+	GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	GT_REG_READ(PCI_0I_O_HIGH_DECODE_ADDRESS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/********************************************************************
+* pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
+* Inputs: N/A
+* Returns: PCI0 Memory 0 Base Address.
+*********************************************************************/
+
+unsigned int pci0GetMemory0Base()
+{
+	unsigned int base;
+	GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	return base;
+}
+
+/********************************************************************
+* pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
+* Inputs: N/A
+* Returns: PCI0 Memory 0 Bar Size.
+*********************************************************************/
+
+unsigned int pci0GetMemory0Size()
+{
+	unsigned int top, base, size;
+	GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	GT_REG_READ(PCI_0MEMORY0_HIGH_DECODE_ADDRESS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/********************************************************************
+* pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
+* Inputs: N/A
+* Returns: PCI0 Memory 1 Base Address.
+*********************************************************************/
+
+unsigned int pci0GetMemory1Base()
+{
+	unsigned int base;
+	GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	return base;
+}
+
+/********************************************************************
+* pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
+* Inputs: N/A
+* Returns: PCI0 Memory 1 Bar Size.
+*********************************************************************/
+
+unsigned int pci0GetMemory1Size()
+{
+	unsigned int top, base, size;
+	GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	GT_REG_READ(PCI_0MEMORY1_HIGH_DECODE_ADDRESS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/********************************************************************
+* pci1GetIOspaceBase - Return PCI1 IO Base Address.
+* Inputs: N/A
+* Returns: PCI1 IO Base Address.
+*********************************************************************/
+
+unsigned int pci1GetIOspaceBase()
+{
+	unsigned int base;
+	GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	return base;
+}
+
+/********************************************************************
+* pci1GetIOspaceSize - Return PCI1 IO Bar Size.
+* Inputs: N/A
+* Returns: PCI1 IO Bar Size.
+*********************************************************************/
+
+unsigned int pci1GetIOspaceSize()
+{
+	unsigned int top, base, size;
+	GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	GT_REG_READ(PCI_1I_O_HIGH_DECODE_ADDRESS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/********************************************************************
+* pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
+* Inputs: N/A
+* Returns: PCI1 Memory 0 Base Address.
+*********************************************************************/
+
+unsigned int pci1GetMemory0Base()
+{
+	unsigned int base;
+	GT_REG_READ(PCI_1MEMORY0_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	return base;
+}
+
+/********************************************************************
+* pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
+* Inputs: N/A
+* Returns: PCI1 Memory 0 Bar Size.
+*********************************************************************/
+
+unsigned int pci1GetMemory0Size()
+{
+	unsigned int top, base, size;
+	GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	GT_REG_READ(PCI_1MEMORY1_HIGH_DECODE_ADDRESS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/********************************************************************
+* pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
+* Inputs: N/A
+* Returns: PCI1 Memory 1 Base Address.
+*********************************************************************/
+
+unsigned int pci1GetMemory1Base()
+{
+	unsigned int base;
+	GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	return base;
+}
+
+/********************************************************************
+* pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
+* Inputs: N/A
+* Returns: PCI1 Memory 1 Bar Size.
+*********************************************************************/
+
+unsigned int pci1GetMemory1Size()
+{
+	unsigned int top, base, size;
+	GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS, &base);
+	base = base << 21;
+	GT_REG_READ(PCI_1MEMORY1_HIGH_DECODE_ADDRESS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/********************************************************************
+* pci0MapInternalRegSpace - Maps the internal registers memory space for the 
+*                           slave.
+*                           Stays the same for all GT devices Disco include
+* Inputs: base of pci0 internal register
+*********************************************************************/
+
+void pci0MapInternalRegSpace(unsigned int pci0InternalBase)
+{
+	pci0InternalBase = pci0InternalBase & 0xfffff000;
+	pci0InternalBase =
+	    pci0InternalBase |
+	    (pci0ReadConfigReg
+	     (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+	      SELF) & 0x00000fff);
+	pci0WriteConfigReg
+	    (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF,
+	     pci0InternalBase);
+}
+
+/********************************************************************
+* pci1MapInternalRegSpace - Maps the internal registers memory space for the 
+*                           slave.
+*                           Stays the same for all GT devices Disco include
+* Inputs: base of pci1 internal register
+*********************************************************************/
+
+void pci1MapInternalRegSpace(unsigned int pci1InternalBase)
+{
+	pci1InternalBase = pci1InternalBase & 0xfffff000;
+	pci1InternalBase =
+	    pci1InternalBase |
+	    (pci1ReadConfigReg
+	     (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+	      SELF) & 0x00000fff);
+	pci1WriteConfigReg
+	    (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF,
+	     pci1InternalBase);
+}
+
+/********************************************************************
+* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the 
+*                             slave.
+*                             Stays the same for all GT devices Disco include
+* Inputs: base of pci0 internal io register
+*********************************************************************/
+
+void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase)
+{
+	pci0InternalBase = pci0InternalBase & 0xfffff000;
+	pci0InternalBase =
+	    pci0InternalBase |
+	    (pci0ReadConfigReg
+	     (PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
+	      0) & 0x00000fff);
+	pci0WriteConfigReg(PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
+			   SELF, pci0InternalBase);
+}
+
+/********************************************************************
+* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the 
+*                             slave.
+*                             Stays the same for all GT devices Disco include
+* Inputs: base of pci1 internal io register
+*********************************************************************/
+
+void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase)
+{
+	pci1InternalBase = pci1InternalBase & 0xfffff000;
+	pci1InternalBase =
+	    pci1InternalBase |
+	    (pci1ReadConfigReg
+	     (PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
+	      SELF) & 0x00000fff);
+	pci1WriteConfigReg(PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
+			   SELF, pci1InternalBase);
+}
+
+/********************************************************************
+* pci0MapMemoryBanks0_1 - Maps PCI0 memory banks 0 and 1 for the slave.
+*                         for Discovery we need two function: SCS0 & SCS1 
+*                         (instead of SCS[1:0])
+* Inputs: base and size of pci0 dram
+*********************************************************************/
+
+
+void pci0MapMemoryBanks0_1(unsigned int pci0Dram0_1Base,
+			   unsigned int pci0Dram0_1Size)
+{
+	pci0Dram0_1Base = pci0Dram0_1Base & 0xfffff000;
+	pci0Dram0_1Base =
+	    pci0Dram0_1Base |
+	    (pci0ReadConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci0WriteConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF,
+			   pci0Dram0_1Base);
+	/* swapped Bar */
+	pci0WriteConfigReg(PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS, SELF,
+			   pci0Dram0_1Base);
+	if (pci0Dram0_1Size == 0)
+		pci0Dram0_1Size++;
+	GT_REG_WRITE(PCI_0SCS_1_0_BANK_SIZE, pci0Dram0_1Size - 1);
+}
+
+/********************************************************************
+* pci1MapMemoryBanks0_1 - Maps PCI1 memory banks 0 and 1 for the slave.
+*                         for Discovery we need two function: SCS0 & SCS1 
+*                         (instead of SCS[1:0])
+* Inputs: base and size of pci1 dram
+*********************************************************************/
+
+void pci1MapMemoryBanks0_1(unsigned int pci1Dram0_1Base,
+			   unsigned int pci1Dram0_1Size)
+{
+	pci1Dram0_1Base = pci1Dram0_1Base & 0xfffff000;
+	pci1Dram0_1Base =
+	    pci1Dram0_1Base |
+	    (pci1ReadConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci1WriteConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF,
+			   pci1Dram0_1Base);
+	/* swapped Bar */
+	pci1WriteConfigReg(PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS, SELF,
+			   pci1Dram0_1Base);
+	if (pci1Dram0_1Size == 0)
+		pci1Dram0_1Size++;
+	GT_REG_WRITE(PCI_1SCS_1_0_BANK_SIZE, pci1Dram0_1Size - 1);
+}
+
+/********************************************************************
+* pci0MapMemoryBanks2_3 - Maps PCI0 memory banks 2 and 3 for the slave.
+*                         for Discovery we need two function: SCS2 & SCS3 
+*                         (instead of SCS[3:2])
+* Inputs: base and size of pci0 dram
+*********************************************************************/
+
+void pci0MapMemoryBanks2_3(unsigned int pci0Dram2_3Base,
+			   unsigned int pci0Dram2_3Size)
+{
+	pci0Dram2_3Base = pci0Dram2_3Base & 0xfffff000;
+	pci0Dram2_3Base =
+	    pci0Dram2_3Base |
+	    (pci0ReadConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci0WriteConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF,
+			   pci0Dram2_3Base);
+	/* swapped Bar */
+	pci0WriteConfigReg(PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS, SELF,
+			   pci0Dram2_3Base);
+	if (pci0Dram2_3Size == 0)
+		pci0Dram2_3Size++;
+	GT_REG_WRITE(PCI_0SCS_3_2_BANK_SIZE, pci0Dram2_3Size - 1);
+}
+
+/********************************************************************
+* pci1MapMemoryBanks2_3 - Maps PCI1 memory banks 2 and 3 for the slave.
+*                         for Discovery we need two function: SCS2 & SCS3 
+*                         (instead of SCS[3:2])
+* Inputs: base and size of pci1 dram
+*********************************************************************/
+
+void pci1MapMemoryBanks2_3(unsigned int pci1Dram2_3Base,
+			   unsigned int pci1Dram2_3Size)
+{
+	pci1Dram2_3Base = pci1Dram2_3Base & 0xfffff000;
+	pci1Dram2_3Base =
+	    pci1Dram2_3Base |
+	    (pci1ReadConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci1WriteConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF,
+			   pci1Dram2_3Base);
+	/* swapped Bar */
+	pci1WriteConfigReg(PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS, SELF,
+			   pci1Dram2_3Base);
+	if (pci1Dram2_3Size == 0)
+		pci1Dram2_3Size++;
+	GT_REG_WRITE(PCI_1SCS_3_2_BANK_SIZE, pci1Dram2_3Size - 1);
+}
+
+/********************************************************************
+* pci0MapDevices0_1and2MemorySpace - Maps PCI0 devices 0,1 and 2 memory spaces 
+*                                    for the slave.
+*                                    For the Discovery there are 3 separate
+*                                    fucnction's
+* Inputs: base and lengthof pci0 devises012
+*********************************************************************/
+
+
+void pci0MapDevices0_1and2MemorySpace(unsigned int pci0Dev012Base,
+				      unsigned int pci0Dev012Length)
+{
+	pci0Dev012Base = pci0Dev012Base & 0xfffff000;
+	pci0Dev012Base =
+	    pci0Dev012Base |
+	    (pci0ReadConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci0WriteConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF, pci0Dev012Base);
+	if (pci0Dev012Length == 0)
+		pci0Dev012Length++;
+	GT_REG_WRITE(PCI_0CS_2_0_BANK_SIZE, pci0Dev012Length - 1);
+}
+
+/********************************************************************
+* pci1MapDevices0_1and2MemorySpace - Maps PCI1 devices 0,1 and 2 memory spaces 
+*                                    for the slave.
+*                                    For the Discovery there are 3 separate
+*                                    fucnction's
+* Inputs: base and lengthof pci1 devises012
+*********************************************************************/
+
+void pci1MapDevices0_1and2MemorySpace(unsigned int pci1Dev012Base,
+				      unsigned int pci1Dev012Length)
+{
+	pci1Dev012Base = pci1Dev012Base & 0xfffff000;
+	pci1Dev012Base =
+	    pci1Dev012Base |
+	    (pci1ReadConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci1WriteConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF, pci1Dev012Base);
+	if (pci1Dev012Length == 0)
+		pci1Dev012Length++;
+	GT_REG_WRITE(PCI_1CS_2_0_BANK_SIZE, pci1Dev012Length - 1);
+}
+
+/********************************************************************
+* pci0MapDevices3andBootMemorySpace - Maps PCI0 devices 3 and boot memory 
+*                                     spaces for the slave.
+*                                     For the Discovery there are 2 separate 
+*                                     fucnction's
+* Inputs: base and length of pci0 device3/ boot
+*********************************************************************/
+
+void pci0MapDevices3andBootMemorySpace(unsigned int pci0Dev3andBootBase,
+				       unsigned int pci0Dev3andBootLength)
+{
+	pci0Dev3andBootBase = pci0Dev3andBootBase & 0xfffff000;
+	pci0Dev3andBootBase =
+	    pci0Dev3andBootBase |
+	    (pci0ReadConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci0WriteConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF,
+			   pci0Dev3andBootBase);
+	/* swapped Bar */
+	pci0WriteConfigReg(PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS, SELF,
+			   pci0Dev3andBootBase);
+	if (pci0Dev3andBootLength == 0)
+		pci0Dev3andBootLength++;
+	GT_REG_WRITE(PCI_0CS_3_BOOTCS_BANK_SIZE,
+		     pci0Dev3andBootLength - 1);
+}
+
+/********************************************************************
+* pci1MapDevices3andBootMemorySpace - Maps PCI1 devices 3 and boot memory 
+*                                     spaces for the slave.
+*                                     For the Discovery there are 2 separate 
+*                                     fucnction's
+* Inputs: base and length of pci1 device3/ boot
+*********************************************************************/
+
+void pci1MapDevices3andBootMemorySpace(unsigned int pci1Dev3andBootBase,
+				       unsigned int pci1Dev3andBootLength)
+{
+	pci1Dev3andBootBase = pci1Dev3andBootBase & 0xfffff000;
+	pci1Dev3andBootBase =
+	    pci1Dev3andBootBase |
+	    (pci1ReadConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF) &
+	     0x00000fff);
+	pci1WriteConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF,
+			   pci1Dev3andBootBase);
+	/* swapped Bar */
+	pci1WriteConfigReg(PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS, SELF,
+			   pci1Dev3andBootBase);
+	if (pci1Dev3andBootLength == 0)
+		pci1Dev3andBootLength++;
+	GT_REG_WRITE(PCI_1CS_3_BOOTCS_BANK_SIZE,
+		     pci1Dev3andBootLength - 1);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.c linux/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.c	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,318 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+#include <linux/config.h>
+#include <asm/galileo-boards/evb64120A/pci.h>
+#include <asm/byteorder.h>
+
+#include "etherboot.h"
+#include "pci_etherboot.h"
+#include "galileo_port.h"
+
+#define MAX_PCI_DEVS 10
+PCI_DEVICE pci0_devices[MAX_PCI_DEVS];
+PCI_DEVICE pci1_devices[MAX_PCI_DEVS];
+
+static int pci_range_ck(unsigned char bus, unsigned char dev)
+{
+	if ((bus == 0) && (dev >= 0) && (dev < 30))
+		return 0;	// Bus/Device Number OK
+
+	return -1;		// Bus/Device Number not OK  
+}
+
+/********************************************************************
+ * pcibios_(read/write)_config_(byte/word/dword)
+ *
+ *Inputs :
+ *bus - bus number
+ *dev - device number
+ *offset - register offset in the configuration space
+ *val - value to be written / read
+ *
+ *Outputs :
+ *Sucees/Failure
+ *********************************************************************/
+#define PCI_CFG_DATA    ((volatile unsigned long *)0xb4000cfc)
+#define PCI_CFG_CTRL    ((volatile unsigned long *)0xb4000cf8)
+
+#define PCI_CFG_SET(dev,fun,off) \
+        ((*PCI_CFG_CTRL) = cpu_to_le32((0x80000000 | ((dev)<<11) | ((fun)<<8) | (off))))
+
+int pcibios_read_config_dword(unsigned char bus, unsigned char dev,
+			      unsigned char offset, unsigned int *val)
+{
+
+	if (offset & 0x3) {
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+	if (pci_range_ck(bus, dev)) {
+		*val = 0xFFFFFFFF;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	PCI_CFG_SET(dev, 0, offset);
+	if (dev != 0) {
+		*val = *PCI_CFG_DATA;
+	} else {
+		*val = cpu_to_le32(*PCI_CFG_DATA);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_read_config_word(unsigned char bus, unsigned char dev,
+			     unsigned char offset, unsigned short *val)
+{
+	if (offset & 0x1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck(bus, dev)) {
+		*val = 0xffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	PCI_CFG_SET(dev, 0, (offset & ~0x3));
+	if (dev != 0) {
+		*val = *PCI_CFG_DATA >> ((offset & 3) * 8);
+	} else {
+		*val = cpu_to_le32(*PCI_CFG_DATA) >> ((offset & 3) * 8);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_read_config_byte(unsigned char bus, unsigned char dev,
+			     unsigned char offset, unsigned char *val)
+{
+	if (pci_range_ck(bus, dev)) {
+		*val = 0xff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	PCI_CFG_SET(dev, 0, (offset & ~0x3));
+	if (dev != 0) {
+		*val = *PCI_CFG_DATA >> ((offset & 3) * 8);
+	} else {
+		*val = cpu_to_le32(*PCI_CFG_DATA >> ((offset & 3) * 8));
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_write_config_dword(unsigned char bus, unsigned char dev,
+			       unsigned char offset, unsigned int val)
+{
+	if (offset & 0x3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck(bus, dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	PCI_CFG_SET(dev, 0, offset);
+	if (dev != 0) {
+		*PCI_CFG_DATA = val;
+	} else {
+		*PCI_CFG_DATA = cpu_to_le32(val);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_write_config_word(unsigned char bus, unsigned char dev,
+			      unsigned char offset, unsigned short val)
+{
+	unsigned long tmp;
+
+	if (offset & 0x1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (pci_range_ck(bus, dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	PCI_CFG_SET(dev, 0, (offset & ~0x3));
+	if (dev != 0) {
+		tmp = *PCI_CFG_DATA;
+	} else {
+		tmp = cpu_to_le32(*PCI_CFG_DATA);
+	}
+	tmp &= ~(0xffff << ((offset & 0x3) * 8));
+	tmp |= (val << ((offset & 0x3) * 8));
+	if (dev != 0) {
+		*PCI_CFG_DATA = tmp;
+	} else {
+		*PCI_CFG_DATA = cpu_to_le32(tmp);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_write_config_byte(unsigned char bus, unsigned char dev,
+			      unsigned char offset, unsigned char val)
+{
+	unsigned long tmp;
+
+	if (pci_range_ck(bus, dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	PCI_CFG_SET(dev, 0, (offset & ~0x3));
+	if (dev != 0) {
+		tmp = *PCI_CFG_DATA;
+	} else {
+		tmp = cpu_to_le32(*PCI_CFG_DATA);
+	}
+	tmp &= ~(0xff << ((offset & 0x3) * 8));
+	tmp |= (val << ((offset & 0x3) * 8));
+	*PCI_CFG_DATA = cpu_to_le32(tmp);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+/********************************************************************
+ * eth_pci_init - Fill pci_devi
+ *
+ *Inputs :
+ *bus - bus number
+ *dev - device number
+ *offset - register offset in the configuration space
+ *val - value to be written / read
+ *
+ *Outputs :
+ *Sucees/Failure
+ *********************************************************************/
+void eth_pci_init(struct pci_device *pcidev)
+{
+	int i, count;
+	pcibios_write_config_word(0, 0, 4, 0x7);
+	pcibios_write_config_dword(0, 8, BAR0, 0x12000000);
+	pcibios_write_config_dword(0, 8, BAR1, 0x10000001);
+	pcibios_write_config_dword(0, 8, BAR2, 0x12100000);
+	strcpy(pci0_devices[0].type, "Network Controller");
+	pci0_devices[0].deviceNum = 8;
+	pci0_devices[0].venID = 0x8086;
+	pci0_devices[0].deviceID = 0x1229;
+
+	pci0_devices[0].bar0Base = 0x12000000;
+	pci0_devices[0].bar0Size = 0x00001000;
+	pci0_devices[0].bar0Type = 0;
+	pci0_devices[0].bar1Base = 0x10000000;
+	pci0_devices[0].bar1Size = 0x40;
+	pci0_devices[0].bar1Type = 1;
+	pci0_devices[0].bar2Base = 0x12100000;
+	pci0_devices[0].bar2Size = 0x00100000;
+	pci0_devices[0].bar2Type = 0;
+	for (i = 0; pcidev[i].vendor != 0; i++) {
+		/* Look for device in PCI0 first */
+		for (count = 0; count < MAX_PCI_DEVS; count++) {
+			if ((pci0_devices[count].type[0] != 0)
+			    && ((unsigned short) pci0_devices[count].
+				venID == (unsigned short) pcidev[i].vendor)
+			    && ((unsigned short) pci0_devices[count].
+				deviceID ==
+				(unsigned short) pcidev[i].dev_id)) {
+				if ((pci0_devices[count].bar0Type == 1)
+				    && (pci0_devices[count].bar0Size != 0))
+					pcidev[i].ioaddr =
+					    pci0_devices[count].bar0Base;
+				if ((pci0_devices[count].bar1Type == 1)
+				    && (pci0_devices[count].bar1Size != 0))
+					pcidev[i].ioaddr =
+					    pci0_devices[count].bar1Base;
+				if ((pci0_devices[count].bar2Type == 1)
+				    && (pci0_devices[count].bar2Size != 0))
+					pcidev[i].ioaddr =
+					    pci0_devices[count].bar2Base;
+				if ((pci0_devices[count].bar3Type == 1)
+				    && (pci0_devices[count].bar3Size != 0))
+					pcidev[i].ioaddr =
+					    pci0_devices[count].bar3Base;
+				if ((pci0_devices[count].bar4Type == 1)
+				    && (pci0_devices[count].bar4Size != 0))
+					pcidev[i].ioaddr =
+					    pci0_devices[count].bar4Base;
+				if ((pci0_devices[count].bar5Type == 1)
+				    && (pci0_devices[count].bar5Size != 0))
+					pcidev[i].ioaddr =
+					    pci0_devices[count].bar5Base;
+
+				if ((pci0_devices[count].bar0Type == 0)
+				    && (pci0_devices[count].bar0Size != 0))
+					pcidev[i].membase =
+					    pci0_devices[count].bar0Base;
+				if ((pci0_devices[count].bar1Type == 0)
+				    && (pci0_devices[count].bar1Size != 0))
+					pcidev[i].membase =
+					    pci0_devices[count].bar1Base;
+				if ((pci0_devices[count].bar2Type == 0)
+				    && (pci0_devices[count].bar2Size != 0))
+					pcidev[i].membase =
+					    pci0_devices[count].bar2Base;
+				if ((pci0_devices[count].bar3Type == 0)
+				    && (pci0_devices[count].bar3Size != 0))
+					pcidev[i].membase =
+					    pci0_devices[count].bar3Base;
+				if ((pci0_devices[count].bar4Type == 0)
+				    && (pci0_devices[count].bar4Size != 0))
+					pcidev[i].membase =
+					    pci0_devices[count].bar4Base;
+				if ((pci0_devices[count].bar5Type == 0)
+				    && (pci0_devices[count].bar5Size != 0))
+					pcidev[i].membase =
+					    pci0_devices[count].bar5Base;
+				pcidev[i].bus = 0;
+				pcidev[i].devfn =
+				    pci0_devices[count].deviceNum;
+			}
+#ifdef CONFIG_EVB_PCI1
+			if ((pci1_devices[count].type[0] != 0)
+			    && (pci1_devices[count].venID ==
+				pcidev[i].vendor)
+			    && (pci1_devices[count].deviceID ==
+				pcidev[i].dev_id)) {
+				if ((pci1_devices[count].bar0Type == 1)
+				    && (pci1_devices[count].bar0Size != 0))
+					pcidev[i].ioaddr =
+					    pci1_devices[count].bar0Base;
+				if ((pci1_devices[count].bar1Type == 1)
+				    && (pci1_devices[count].bar1Size != 0))
+					pcidev[i].ioaddr =
+					    pci1_devices[count].bar1Base;
+				if ((pci1_devices[count].bar2Type == 1)
+				    && (pci1_devices[count].bar2Size != 0))
+					pcidev[i].ioaddr =
+					    pci1_devices[count].bar2Base;
+				if ((pci1_devices[count].bar3Type == 1)
+				    && (pci1_devices[count].bar3Size != 0))
+					pcidev[i].ioaddr =
+					    pci1_devices[count].bar3Base;
+				if ((pci1_devices[count].bar4Type == 1)
+				    && (pci1_devices[count].bar4Size != 0))
+					pcidev[i].ioaddr =
+					    pci1_devices[count].bar4Base;
+				if ((pci1_devices[count].bar5Type == 1)
+				    && (pci1_devices[count].bar5Size != 0))
+					pcidev[i].ioaddr =
+					    pci1_devices[count].bar5Base;
+
+				if ((pci1_devices[count].bar0Type == 0)
+				    && (pci1_devices[count].bar0Size != 0))
+					pcidev[i].membase =
+					    pci1_devices[count].bar0Base;
+				if ((pci1_devices[count].bar1Type == 0)
+				    && (pci1_devices[count].bar1Size != 0))
+					pcidev[i].membase =
+					    pci1_devices[count].bar1Base;
+				if ((pci1_devices[count].bar2Type == 0)
+				    && (pci1_devices[count].bar2Size != 0))
+					pcidev[i].membase =
+					    pci1_devices[count].bar2Base;
+				if ((pci1_devices[count].bar3Type == 0)
+				    && (pci1_devices[count].bar3Size != 0))
+					pcidev[i].membase =
+					    pci1_devices[count].bar3Base;
+				if ((pci1_devices[count].bar4Type == 0)
+				    && (pci1_devices[count].bar4Size != 0))
+					pcidev[i].membase =
+					    pci1_devices[count].bar4Base;
+				if ((pci1_devices[count].bar5Type == 0)
+				    && (pci1_devices[count].bar5Size != 0))
+					pcidev[i].membase =
+					    pci1_devices[count].bar5Base;
+
+				pcidev[i].bus = 1;
+				pcidev[i].devfn =
+				    pci1_devices[count].deviceNum;
+			}
+#endif
+		}
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.h linux/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/pci_etherboot.h	2002-08-01 06:42:32.000000000 +0000
@@ -0,0 +1,144 @@
+#ifndef	PCI_H
+#define PCI_H
+
+/*
+** Support for NE2000 PCI clones added David Monro June 1997
+** Generalised for other PCI NICs by Ken Yap July 1997
+**
+** Most of this is taken from:
+**
+** /usr/src/linux/drivers/pci/pci.c
+** /usr/src/linux/include/linux/pci.h
+** /usr/src/linux/arch/i386/bios32.c
+** /usr/src/linux/include/linux/bios32.h
+** /usr/src/linux/drivers/net/ne.c
+*/
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#define PCI_COMMAND_IO			0x1	/* Enable response in I/O space */
+#define PCI_COMMAND_MASTER		0x4	/* Enable bus mastering */
+#define PCI_LATENCY_TIMER		0x0d	/* 8 bits */
+
+
+#define PCI_VENDOR_ID           0x00	/* 16 bits */
+#define PCI_DEVICE_ID           0x02	/* 16 bits */
+#define PCI_COMMAND             0x04	/* 16 bits */
+
+#define PCI_CLASS_CODE          0x0b	/* 8 bits */
+#define PCI_SUBCLASS_CODE       0x0a	/* 8 bits */
+#define PCI_HEADER_TYPE         0x0e	/* 8 bits */
+
+#define PCI_BASE_ADDRESS_0      0x10	/* 32 bits */
+#define PCI_BASE_ADDRESS_1      0x14	/* 32 bits */
+#define PCI_BASE_ADDRESS_2      0x18	/* 32 bits */
+#define PCI_BASE_ADDRESS_3      0x1c	/* 32 bits */
+#define PCI_BASE_ADDRESS_4      0x20	/* 32 bits */
+#define PCI_BASE_ADDRESS_5      0x24	/* 32 bits */
+
+#ifndef	PCI_BASE_ADDRESS_IO_MASK
+#define	PCI_BASE_ADDRESS_IO_MASK       (~0x03)
+#endif
+#define	PCI_BASE_ADDRESS_SPACE_IO	0x01
+#define	PCI_ROM_ADDRESS		0x30	/* 32 bits */
+#define	PCI_ROM_ADDRESS_ENABLE	0x01	/* Write 1 to enable ROM,
+					   bits 31..11 are address,
+					   10..2 are reserved */
+
+#define PCI_FUNC(devfn)           ((devfn) & 0x07)
+
+#define BIOS32_SIGNATURE        (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
+
+/* PCI signature: "PCI " */
+#define PCI_SIGNATURE           (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
+
+/* PCI service signature: "$PCI" */
+#define PCI_SERVICE             (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
+
+#define KERN_CODE_SEG	0x8	/* This _MUST_ match start.S */
+
+#define PCI_VENDOR_ID_REALTEK           0x10ec
+#define PCI_DEVICE_ID_REALTEK_8029      0x8029
+#define PCI_DEVICE_ID_REALTEK_8139      0x8139
+#define PCI_VENDOR_ID_WINBOND2          0x1050
+#define PCI_DEVICE_ID_WINBOND2_89C940   0x0940
+#define PCI_VENDOR_ID_COMPEX            0x11f6
+#define PCI_DEVICE_ID_COMPEX_RL2000     0x1401
+#define PCI_VENDOR_ID_KTI               0x8e2e
+#define PCI_DEVICE_ID_KTI_ET32P2        0x3000
+#define PCI_VENDOR_ID_NETVIN            0x4a14
+#define PCI_DEVICE_ID_NETVIN_NV5000SC   0x5000
+#define PCI_VENDOR_ID_3COM		0x10b7
+#define PCI_DEVICE_ID_3COM_3C900TPO	0x9000
+#define PCI_DEVICE_ID_3COM_3C900COMBO	0x9001
+#define PCI_DEVICE_ID_3COM_3C905TX	0x9050
+#define PCI_DEVICE_ID_3COM_3C905T4	0x9051
+#define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
+#define PCI_DEVICE_ID_3COM_3C905C_TXM	0x9200
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_DEVICE_ID_INTEL_82557	0x1229
+#define PCI_VENDOR_ID_AMD		0x1022
+#define PCI_DEVICE_ID_AMD_LANCE		0x2000
+#define PCI_VENDOR_ID_SMC_1211          0x1113
+#define PCI_DEVICE_ID_SMC_1211          0x1211
+#define PCI_VENDOR_ID_DEC		0x1011
+#define PCI_DEVICE_ID_DEC_TULIP		0x0002
+#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
+#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
+#define PCI_DEVICE_ID_DEC_21142		0x0019
+#define PCI_VENDOR_ID_SMC		0x10B8
+#ifndef	PCI_DEVICE_ID_SMC_EPIC100
+# define PCI_DEVICE_ID_SMC_EPIC100	0x0005
+#endif
+#define PCI_VENDOR_ID_MACRONIX		0x10d9
+#define PCI_DEVICE_ID_MX987x5		0x0531
+#define PCI_VENDOR_ID_LINKSYS		0x11AD
+#define PCI_DEVICE_ID_LC82C115		0xC115
+#define PCI_VENDOR_ID_VIATEC		0x1106
+#define PCI_DEVICE_ID_VIA_RHINE_I	0x3043
+#define PCI_DEVICE_ID_VIA_86C100A	0x6100
+#define PCI_VENDOR_ID_DAVICOM		0x1282
+#define PCI_DEVICE_ID_DM9102		0x9102
+
+struct pci_device {
+	unsigned short vendor, dev_id;
+	const char *name;
+	unsigned int membase;
+	unsigned int ioaddr;
+	unsigned short devfn;
+	unsigned short bus;
+};
+
+extern void eth_pci_init(struct pci_device *);
+int pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
+			     unsigned char where, unsigned char *val);
+int pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
+			     unsigned char where, unsigned short *val);
+int pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
+			      unsigned char where, unsigned int *val);
+int pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
+			      unsigned char where, unsigned char val);
+int pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
+			      unsigned char where, unsigned short val);
+int pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
+			       unsigned char where, unsigned int val);
+
+/*
+ * Error values that may be returned by the PCI bios.
+ */
+#define PCIBIOS_SUCCESSFUL              0x00
+#define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
+#define PCIBIOS_BAD_VENDOR_ID           0x83
+#define PCIBIOS_DEVICE_NOT_FOUND        0x86
+#define PCIBIOS_BAD_REGISTER_NUMBER     0x87
+#define PCIBIOS_SET_FAILED              0x88
+#define PCIBIOS_BUFFER_TOO_SMALL        0x89
+
+
+
+#endif				/* PCI_H */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/sbd.h linux/arch/mips/galileo-boards/ev64120/compressed/sbd.h
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/sbd.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/sbd.h	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * sbd.h: cpu board definitions for Galileo-9
+ * Copyright (c) 1997	Algorithmics Ltd
+ */
+
+#ifndef MHZ
+/* fastest possible pipeline clock */
+#define MHZ		150
+#endif
+
+/* FIXME These timings are completely fictional */
+#define RAMCYCLE	60	/* 60ns dram cycle */
+#define ROMCYCLE	750	/* ~750ns rom cycle */
+#define CACHECYCLE	(1000/MHZ)	/* internal clock */
+#define CYCLETIME	CACHECYCLE
+#define CACHEMISS	(CYCLETIME * 6)
+
+/*
+ * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
+ */
+#define ASMDELAY(ns,icycle)	\
+	(((ns) + (icycle)) / ((icycle) * 2))
+
+#define CACHEUS		ASMDELAY(1000, CACHECYCLE)
+#define RAMUS		ASMDELAY(1000, CACHEMISS+RAMCYCLE)
+#define ROMUS		ASMDELAY(1000, CACHEMISS+ROMCYCLE)
+#define CACHEMS		ASMDELAY(1000000, CACHECYCLE)
+#define RAMMS		ASMDELAY(1000000, CACHEMISS+RAMCYCLE)
+#define ROMMS		ASMDELAY(1000000, CACHEMISS+ROMCYCLE)
+
+#ifndef __ASSEMBLY__
+#define nsdelay(ns)	mips_cycle (ASMDELAY (ns, CACHECYCLE))
+#define usdelay(us)	mips_cycle (ASMDELAY ((us)*1000, CACHECYCLE))
+#endif
+
+#define DRAM_BASE		0x00000000
+#define PCI_IO_BASE		0x10000000
+#define PCI_IO_SIZE		0x02000000
+#define PCI_MEM_BASE		0x12000000
+#define PCI_MEM_SIZE		0x02000000
+#define GT64011_BASE		0x14000000
+#define DUART_BASE		0x1d000000
+#define FLASH_BASE		0x1f000000
+#define PROM_BASE		0x1fc00000
+
+
+#define LOCAL_MEM		DRAM_BASE
+#define LOCAL_MEM_SIZE		(128*1024*1024)	/* SDRAM size (16MB) */
+
+#define BOOTPROM_BASE		PROM_BASE
+
+#define DUART_CLOCK		3686400
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S linux/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,1049 @@
+/*
+ * Copyright 1997 Algorithmics Ltd
+ *	All Rights Reserved
+ *	
+ * gal9/sbdreset.sx -- low level board dependent routines
+ */
+
+#ifdef EVB64120A
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/cacheops.h>
+#include <asm/current.h>
+#include <asm/offset.h>
+#include <asm/processor.h>
+#include <asm/regdef.h>
+#include <asm/cachectl.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/cpu.h>
+#include "sbd.h"
+
+
+#include "gt64011.h"
+#include "ns16550.h"
+			
+#ifdef GALILEO_PORT // miniBios crack
+#define C0_CONFIG CP0_CONFIG
+#define C0_STATUS CP0_STATUS
+#define C0_TLBLO0 CP0_ENTRYLO0
+#define C0_TLBLO1 CP0_ENTRYLO1
+#define C0_PGMASK CP0_PAGEMASK
+#define C0_TLBHI CP0_ENTRYHI 
+#define C0_INX CP0_INDEX
+#define NTLBENTRIES     48
+        
+        
+#define CFG_IB CONF_IB
+#define CFG_DB CONF_DB
+#define CFG_C_NONCOHERENT CONF_CM_CACHABLE_NONCOHERENT
+#define C0_SR CP0_STATUS        
+#define SR_DE ST0_DE
+
+        
+        #define SLEAF(x) LEAF(x)
+        #define SEND(x) END(x)
+        #define XLEAF(x) LEAF(x)
+        #define SBD_DISPLAY(a,b,c,d,e) ; 
+
+#define K0BASE          0x80000000
+#define K0SIZE          0x20000000
+#define K1BASE          0xa0000000
+#define K1SIZE          0x20000000
+#define K2BASE          0xc0000000
+
+#define PHYS_TO_K0(pa)  ((pa)|K0BASE)
+#define PHYS_TO_K1(pa)  ((pa)|K1BASE)
+#define K0_TO_PHYS(va)  ((va)&(K0SIZE-1))
+#define K1_TO_PHYS(va)  ((va)&(K1SIZE-1))
+#define K0_TO_K1(va)    ((va)|K1SIZE)
+#define K1_TO_K0(va)    ((va)&~K1SIZE)
+
+#define PA_TO_KVA0(pa)  PHYS_TO_K0(pa)
+#define PA_TO_KVA1(pa)  PHYS_TO_K1(pa)
+#define KVA_TO_PA(pa)   K1_TO_PHYS(pa)
+#define KSEG0_BASE      K0BASE
+#define KSEG1_BASE      K1BASE
+
+
+#endif
+
+#define MB	0x100000
+				
+#define MemTypeNone		0x8000
+#define MemRasMask		0x0f00
+#define MemRasShift		8
+#define MemCasMask		0x000f
+#define MemCasShift 		0
+
+#define rasave	s0
+#define p64011	s1
+#define bank0	s2
+#define bank1	s3
+#define bank2	s4
+#define bank3	s5
+#define memtop	s6
+#define membase	s7
+	
+/*#if #endian(big)	*/
+#ifdef __MIPSEB__
+
+#define HTOLL(sr,tr) \
+	.set noat ; \
+	srl	AT,sr,24 ; \
+	srl	tr,sr,8 ; \
+	and	tr,0xff00 ; \
+	or	AT,tr ; \
+	and	tr,sr,0xff00 ; \
+	sll	tr,8 ; \
+	or	AT,tr ; \
+	sll	tr,sr,24 ; \
+	or	sr,AT,tr ; \
+	.set at
+#else
+#define HTOLL(sr,tr)
+#endif
+				
+#undef DBGSBD
+	
+#ifdef DBGSBD
+#define DBG(s) \
+	.rdata ; \
+88:	.asciiz	s ; \
+	.text ; \
+	la	a0, 88b ; \
+	jal	_dbgmsg
+	
+LEAF(_dbgmsg)
+	.set noat
+	li	AT,PHYS_TO_K1(NS16550_CHANB)
+waitrdy:
+	lbu	v1,LSR(AT)
+	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
+	and	v1,LSR_TXRDY
+	beqz	v1,waitrdy
+	
+	lbu	v1,(a0)
+	addu	a0,1
+	beqz	v1,9f
+	sb	v1,DATA(AT)
+	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
+	b	waitrdy	
+9:	j	ra
+	.set at
+END(_dbgmsg)
+
+LEAF(_dbghex)
+	li	a1,PHYS_TO_K1(NS16550_CHANB)
+	li	t0,8
+1:
+	lbu	t1,LSR(a1)
+	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
+	and	t1,LSR_TXRDY
+	beqz	t1,1b
+	
+	srl	t1,a0,28
+	addu	t1,'0'
+	ble	t1,'9',2f
+	addu	t1,'a'-'0'-10
+2:	sb	t1,DATA(a1)
+	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
+
+	sll	a0,4
+	sub	t0,1
+	bnez	t0,1b
+		
+	j	ra
+	.set at
+END(_dbghex)
+	
+	.rdata
+initb_str:
+	.byte	9,0x40	/* Reset CH B */
+	.byte	1,0x00	/* Interrupt disabled */
+	.byte	3,0xc1	/* 8 bits/char rx enable */
+	.byte	4,0x44	/* x16 clk mode 1 stop bit */
+	.byte	5,0x6a	/* tx 8/bit RTS & tx enable */
+	.byte	9,0x0a	/* MIE Master int enab. and NV No Vector */
+	.byte	11,0x50	/* Select BR gen. out for both rx and ts */
+	.byte	0,0x10
+	.byte	0,0x10
+	.byte	14,0x01	/* enable baud rate gen. */
+	.byte	15,0x00	/* known state for reg 15 */
+	
+	.byte	14,0x00	/* disable baud rate gen. */
+	.byte	12,0x0a /* 0x0a	= 9600 baud time const. - lower 8 bits */
+	.byte	13,0x00	/* 9600 buad time const. - upper 8 bits */
+	.byte	14,0x01	/* enable baud rate gen. */
+	.byte	0xff
+
+	.text
+	
+SLEAF(_dbginit)
+        /*
+        li	v0,PHYS_TO_K1(NS16550_CHANB)
+	la	a0,initb_str
+	or	a0,K1BASE
+1:	lbu	t0,0(a0)
+	beq	t0,0xff,1f
+	sb	t0,LSR(v0)
+	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
+	addu	a0,1
+	b	1b
+        */
+        jal     init_ns16550_chan_b # Debug channel
+	j	ra
+SEND(_dbginit)		
+#else
+#define DBG(s)		
+#endif
+		
+LEAF(sbdreset)
+	move	rasave,ra
+
+	/* if launched by ITROM, leave Config alone */
+#ifndef ITBASE	
+	/* set config register for 32b/32b cachelines, kseg0 cacheable */
+	mfc0	t1,C0_CONFIG
+	and	t1,~0x3f		# set bits 5..0 only
+	or	t1,CFG_IB | CFG_DB | CFG_C_NONCOHERENT
+	mtc0	t1,C0_CONFIG
+#endif	
+
+       /* Initialize stack pointer to 6MB address */        
+         li sp,0xa0600000 
+
+        
+        /*
+	 * slight amount of kludgery here to stop RAM resident
+	 * program from overwriting itself...
+	 */
+//	li	v1,0x1fc00000		/* check return address is in ROM */
+//	and	v0,ra,v1
+//	bne	v0,v1,.noinit
+
+        /* table driven hardware register initialization */
+        la      a0, reginittab
+        or      a0, K1BASE              /* force to kseg1 */
+
+1:      lw      v0,0(a0)
+        lw      v1,4(a0)
+        addu    a0,8
+        beqz    v0,8f
+
+        sw      v1,0(v0)
+        b       1b
+8:
+
+#ifdef DBGSBD
+	jal     init_ns16550_chan_b   # was - _dbginit
+	DBG("sbdreset\r\n")
+#endif
+#define DEVICE_BANK0PARAMETERS                                                          0x45C
+#define DEVICE_BANK1PARAMETERS                                                          0x460
+#define DEVICE_BANK2PARAMETERS                                                          0x464
+#define DEVICE_BANK3PARAMETERS                                                          0x468
+#define DEVICE_BOOT_BANK_PARAMETERS                                                     0x46C
+#define GT_INTERNAL_REG_BASE 0xb4000000
+
+        li      p64011, PA_TO_KVA1(GT64011_BASE)
+         
+        li  v0,0xb400046c       /* Boot Device */
+        lw  t0,0(v0)
+        and t0,0x00003000       /* Keep the correct boot size */
+	or  t0,htoll(0x3847de70)
+	sw  t0,0(v0)
+        
+        li  v0,0xb4000468       /* CS3 Device - 16 bit FLASH memory */
+        li  t0,htoll(0x3859e6e8)
+	sw  t0,0(v0)
+        
+                
+        li  v0,0xb4000c84       /* PCI 1 timeout register */
+        li  t0,htoll(0xffff)
+	sw  t0,0(v0)
+        
+                
+        li  v0,0xb4000c3c       /* Enable I/O response on PCI0 */
+        li  t0,htoll(0x7)
+	sw  t0,0(v0)
+
+        li  v0,0xb4000cbc       /* Enable I/O response on PCI1 */
+        li  t0,htoll(0x7)
+	sw  t0,0(v0)
+
+        /* GT-64120 Initialization */
+        
+        li      p64011, PA_TO_KVA1(GT64011_BASE)	
+
+        /*********************************************************************/
+        /************************* SDRAM initializing ************************/
+        /******************************* START *******************************/
+        
+        
+                                        /* SDRAM banks 0,1,2,3 parameters               */
+        li      t0,htoll(0x01908200)    /* - Standard Monitor: Interleave enabled       */
+        li      v0,0xb4000448           /* - Registered SDRAM (Bit 23)                  */
+        sw      t0,0(v0)                /* - Duplicate Dadr11,BankSel1 and Dadr12       */
+                                        /* - Cas latency: 2 Cycles                      */
+                                        /* - Flow Through enable: One sample            */
+                                        /* - SRAS - precharge time: 3 Cycles            */
+                                        /* - No ECC                                     */
+                                        /* - No ByPass                                  */
+                                        /* - Burst length: 8                            */
+        
+        /* Detect whether we have a 16,64,128 or 256 Mbit SDRAM on DIMM0 */
+        /* Set bank0`s range to: 0 - 0x10000000 (256 MByte)     */
+_DIMM0:
+        li  v0,0xb4000008      
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        
+        li  v0,0xb4000010      
+	li  t0,htoll(0x7f)
+	sw  t0,0(v0)
+        
+        /* Close banks 2 and 3 */
+        li  v0,0xb4000018      
+	li  t0,htoll(0x7ff)
+	sw  t0,0(v0)
+        li  v0,0xb4000020      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)
+        
+        /* Extend bank0 to 0x10000000 and Close bank1,2 and 3 */
+        DBG("Extend bank0 to 0x10000000 and Close bank1,2 and 3...\r\n")
+        li  v0,0xb4000400      
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        li  v0,0xb4000404      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)
+        li  v0,0xb4000408      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)   
+        li  v0,0xb400040c      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)
+        li  v0,0xb4000410      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)   
+        li  v0,0xb4000414      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)
+        li  v0,0xb4000418      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)   
+        li  v0,0xb400041c      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)        
+
+        /* Configure bank0 to 256 Mbit */
+        DBG("Configure bank0 to 256 Mbit...\r\n")
+        li  v0,0xb400044c      
+	li  t0,htoll(0x00004c69)
+        sw  t0,0(v0)
+        
+        /* Config the SDRAM banks decode system */
+	li  v0,0xb400047c      
+	li  t0,htoll(2)
+	sw  t0,0(v0)
+ 
+        li  v0,0xb4000474        
+	li  t0,htoll(0x3)
+	sw  t0,0(v0)
+        
+        li  v0,0xa0000000
+        li  t0,0
+        sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)      
+        
+        /* Write to address 0x2000000 and check if 0x00000000 is being written too */
+        DBG("Write to address 0x2000000 and check if 0x00000000 is being written too...\r\n")
+        li  v0,0xa0000000
+        li  t1,0xa0000010
+        li  t0,htoll(0x0)
+1:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,1b
+
+        /* The address should activate Dadr12 */
+        li  v0,0xa2000000      
+	li  t0,0x11111111
+        sw  t0,0(v0)
+        li  v0,0xa0000010
+        li  t1,0xa0000100
+        li  t0,0x22222222
+2:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,2b
+
+        DBG("Check address 0x00000000 for duplications...\r\n")
+        li    t0,0xa0000000
+        li    v0,0x11111111
+        lw    t0,(t0)
+        bne   t0,v0,_256MBIT
+        
+        /* Write to address 0x1000 and check if 0x00000000 is being written too */
+        DBG("Write to address 0x1000 and check if 0x00000000 is being written too...\r\n")
+        li  v0,0xa0000000
+        li  t1,0xa0000010
+        li  t0,htoll(0x0)
+1:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,1b
+
+        /* The address should activate bank select1*/
+        li  v0,0xa0001000      
+	li  t0,0x11111111
+        sw  t0,0(v0)
+        li  v0,0xa0000010
+        li  t1,0xa0000100
+        li  t0,0x22222222
+2:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,2b
+
+        DBG("Check address 0x00000000 for duplications...\r\n")
+        li    t0,0xa0000000
+        li    v0,0x11111111
+        lw    t0,(t0)
+        beq   t0,v0,_16MBIT
+
+        /* Write to address 0x8000000 and check if 0x00000000 is being written too */
+        DBG("Write to address 0x8000000 and check if 0x00000000 is being written too...\r\n")
+        li  v0,0xa0000000
+        li  t1,0xa0000010
+        li  t0,htoll(0x0)
+1:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,1b
+
+        /* The address should activate Dadr9 which on the column cycle is in active with 64 Mbit
+           device */
+        li  v0,0xa8000000      
+	li  t0,0x11111111
+        sw  t0,0(v0)
+        li  v0,0xa0000010
+        li  t1,0xa0000100
+        li  t0,0x22222222
+2:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,2b
+
+        DBG("Check address 0x00000000 for duplications...\r\n")
+        li    t0,0xa0000000
+        li    v0,0x11111111
+        lw    t0,(t0)
+        beq   t0,v0,_64MBIT
+        b     _128MBIT
+        
+_16MBIT:
+        DBG("16 Mbit SDRAM detected...\r\n")
+        /* In 16 Mbit SDRAM we must use 2 way bank interleaving!!! */
+        li  v0,0xb4000810      
+	li  t0,htoll(16)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00000449)
+        b   _DIMM1
+
+_64MBIT:
+        DBG("64 Mbit SDRAM detected...\r\n")
+        /* In 64 Mbit SDRAM we must use 4 way bank interleaving!!! */
+        li  v0,0xb4000810      
+	li  t0,htoll(64)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00000c69)
+        b   _DIMM1
+
+_128MBIT:
+        DBG("128 Mbit SDRAM detected...\r\n")
+        /* In 128 Mbit SDRAM we must use 4 way bank interleaving!!! */
+        li  v0,0xb4000810      
+	li  t0,htoll(128)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00000c69)
+        b   _DIMM1
+
+_256MBIT:
+        DBG("256 Mbit SDRAM detected...\r\n")
+        /* In 256 Mbit SDRAM we must use 4 way bank interleaving!!! */
+        li  v0,0xb4000810      
+	li  t0,htoll(256)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00004c69)
+        b   _DIMM1
+        
+_DIMM1:        
+        li  v0,0xb400044c
+        sw  t1,0(v0)  # Bank0
+        sw  t1,4(v0)  # Bank1           
+        
+        /* Detect whether we have a 16,64,128 or 256 Mbit SDRAM on DIMM1 */
+        /* Close banks 0 and 1 */
+        li  v0,0xb4000008      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)
+        
+        li  v0,0xb4000010      
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        
+        /* Set bank2`s range to: 0 - 0x10000000 (256 MByte)     */
+        li  v0,0xb4000018      
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        li  v0,0xb4000020      
+	li  t0,htoll(0x7f)
+	sw  t0,0(v0)
+        
+        /* Extend bank2 to 0x10000000 and Close bank0,1 and 3 */
+        DBG("Extend bank2 to 0x10000000 and Close banks 0,1 and 3...\r\n")
+        li  v0,0xb4000400      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)
+        li  v0,0xb4000404      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)
+        li  v0,0xb4000408      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)   
+        li  v0,0xb400040c      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)
+        li  v0,0xb4000410      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)   
+        li  v0,0xb4000414      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)
+        li  v0,0xb4000418      
+	li  t0,htoll(0xff)
+	sw  t0,0(v0)   
+        li  v0,0xb400041c      
+	li  t0,htoll(0x00)
+	sw  t0,0(v0)        
+
+        /* Configure bank2 to 256 Mbit */
+        DBG("Configure bank2 to 256 Mbit...\r\n")
+        li  v0,0xb4000454      
+	li  t0,htoll(0x00004c69)
+        sw  t0,0(v0)
+        
+        /* Config the SDRAM banks decode system */
+	li  v0,0xb400047c      
+	li  t0,htoll(2)
+	sw  t0,0(v0)
+ 
+        li  v0,0xb4000474        
+	li  t0,htoll(0x3)
+	sw  t0,0(v0)
+        
+        li  v0,0xa0000000
+        li  t0,0
+        sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)      
+        
+        /* Write to address 0x2000000 and check if 0x00000000 is being written too */
+        DBG("Write to address 0x2000000 and check if 0x00000000 is being written too...\r\n")
+        li  v0,0xa0000000
+        li  t1,0xa0000010
+        li  t0,htoll(0x0)
+1:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,1b
+
+        /* The address should activate Dadr12 */
+        li  v0,0xa2000000      
+	li  t0,0x11111111
+        sw  t0,0(v0)
+        li  v0,0xa0000010
+        li  t1,0xa0000100
+        li  t0,0x22222222
+2:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,2b
+
+        DBG("Check address 0x00000000 for duplications...\r\n")
+        li    t0,0xa0000000
+        li    v0,0x11111111
+        lw    t0,(t0)
+        bne   t0,v0,_256MBIT2
+        
+        /* Write to address 0x1000 and check if 0x00000000 is being written too */
+        DBG("Write to address 0x1000 and check if 0x00000000 is being written too...\r\n")
+        li  v0,0xa0000000
+        li  t1,0xa0000010
+        li  t0,htoll(0x0)
+1:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,1b
+
+        /* The address should activate bank select1*/
+        li  v0,0xa0001000      
+	li  t0,0x11111111
+        sw  t0,0(v0)
+        li  v0,0xa0000010
+        li  t1,0xa0000100
+        li  t0,0x22222222
+2:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,2b
+
+        DBG("Check address 0x00000000 for duplications...\r\n")
+        li    t0,0xa0000000
+        li    v0,0x11111111
+        lw    t0,(t0)
+        beq   t0,v0,_16MBIT2
+
+        /* Write to address 0x8000000 and check if 0x00000000 is being written too */
+        DBG("Write to address 0x8000000 and check if 0x00000000 is being written too...\r\n")
+        li  v0,0xa0000000
+        li  t1,0xa0000010
+        li  t0,htoll(0x0)
+1:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,1b
+
+        /* The address should activate Dadr9 which on the column cycle is in active with 64 Mbit
+           device */
+        li  v0,0xa8000000      
+	li  t0,0x11111111
+        sw  t0,0(v0)
+        li  v0,0xa0000010
+        li  t1,0xa0000100
+        li  t0,0x22222222
+2:      sw  t0,0(v0)
+        addu v0,4
+        bne t1,v0,2b
+
+        DBG("Check address 0x00000000 for duplications...\r\n")
+        li    t0,0xa0000000
+        li    v0,0x11111111
+        lw    t0,(t0)
+        beq   t0,v0,_64MBIT2
+        b     _128MBIT2
+        
+_16MBIT2:
+        DBG("16 Mbit SDRAM detected...\r\n")
+        /* In 16 Mbit SDRAM we must use 2 way bank interleaving!!! */
+        li  v0,0xb4000814      
+	li  t0,htoll(16)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00000449)
+        b   _INIT_SDRAM
+
+_64MBIT2:
+        DBG("64 Mbit SDRAM detected...\r\n")
+        /* In 64 Mbit SDRAM we must use 4 way bank interleaving!!! */
+        li  v0,0xb4000814      
+	li  t0,htoll(64)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00000c69)
+        b   _INIT_SDRAM
+
+_128MBIT2:
+        DBG("128 Mbit SDRAM detected...\r\n")
+        /* In 128 Mbit SDRAM we must use 4 way bank interleaving!!! */
+        li  v0,0xb4000814      
+	li  t0,htoll(128)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00000c69)
+        b   _INIT_SDRAM
+
+_256MBIT2:
+        DBG("256 Mbit SDRAM detected...\r\n")
+        /* In 256 Mbit SDRAM we must use 4 way bank interleaving!!! */
+        li  v0,0xb4000814      
+	li  t0,htoll(256)
+	sw  t0,0(v0)
+        li  t1,htoll(0x00004c69)
+        b   _INIT_SDRAM
+
+_INIT_SDRAM:        
+        /* Restore defaults */
+        DBG("Restoring defaults...\r\n")
+        li  v0,0xb4000404      
+	li  t0,htoll(0x07)
+	sw  t0,0(v0)
+        li  v0,0xb4000408      
+	li  t0,htoll(0x08)
+	sw  t0,0(v0)
+        li  v0,0xb400040c      
+	li  t0,htoll(0x0f)
+	sw  t0,0(v0)
+        li  v0,0xb4000410      
+	li  t0,htoll(0x10)
+	sw  t0,0(v0)   
+        li  v0,0xb4000414      
+	li  t0,htoll(0x17)
+	sw  t0,0(v0)
+        li  v0,0xb4000418      
+	li  t0,htoll(0x18)
+	sw  t0,0(v0)   
+        li  v0,0xb400041c      
+	li  t0,htoll(0x1f)
+	sw  t0,0(v0)
+        li  v0,0xb4000010      
+	li  t0,htoll(0x07)
+	sw  t0,0(v0)
+        li  v0,0xb4000018      
+	li  t0,htoll(0x008)
+	sw  t0,0(v0)
+        li  v0,0xb4000020      
+	li  t0,htoll(0x0f)
+	sw  t0,0(v0)        
+        
+        li  v0,0xb400044c
+        sw  t1,8(v0)  # Bank2
+        sw  t1,12(v0) # Bank3
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x3)
+	sw  t0,0(v0)
+        
+        li  v0,0xa0000000
+        li  t0,0
+        sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x3)
+	sw  t0,0(v0)
+        
+        li  v0,0xa0800000
+        li  t0,0
+        sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x3)
+	sw  t0,0(v0)
+        
+        li  v0,0xa1000000
+        li  t0,0
+        sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x3)
+	sw  t0,0(v0)
+        
+        li  v0,0xa1800000
+        li  t0,0
+        sw  t0,0(v0)
+        
+        li  v0,0xb4000474        
+	li  t0,htoll(0x0)
+	sw  t0,0(v0)
+        
+        /*********************************************************************/
+        /************************* SDRAM initializing ************************/
+        /******************************* END *********************************/
+        
+        li      p64011, PA_TO_KVA1(GT64011_BASE)
+        
+        li      t0,htoll(0x00000000)    /* RAS[1:0] low decode address */
+        sw      t0,0x008(p64011)
+
+        li      t0,htoll(0x00000007)    /* RAS[1:0] high decode address */
+        sw      t0,0x010(p64011)
+
+        li      t0,htoll(0x00000000)    /* RAS[0] Low decode address */
+        sw      t0,0x400(p64011)
+
+        li      t0,htoll(0x0000000f)    /* RAS[0] High decode address */
+        sw      t0,0x404(p64011)
+
+        li      t0,htoll(0x00000008)    /* RAS[3:2] low decode address */
+        sw      t0,0x018(p64011)
+
+        li      t0,htoll(0x0000000f)    /* RAS[3:2] high decode address */
+        sw      t0,0x020(p64011)
+
+        li      t0,htoll(0x0000000f)    /* RAS[1] Low Decode Address */
+        sw      t0,0x408(p64011)
+
+        li      t0,htoll(0x00000008)    /* RAS[1] High Decode Address */
+        sw      t0,0x40c(p64011)
+
+        li      t0,htoll(0x00000010)    /* RAS[2] Low Decode Address */
+        sw      t0,0x410(p64011)
+
+        li      t0,htoll(0x00000017)    /* RAS[2] High Decode Address */
+        sw      t0,0x414(p64011)
+
+        li      t0,htoll(0x00000018)    /* RAS[3] Low Decode Address */
+        sw      t0,0x418(p64011)
+
+        li      t0,htoll(0x0000001f)    /* RAS[3] High Decode Address <<<<<< 1*/
+        sw      t0,0x41c(p64011)
+	
+#ifdef DBGSBD	
+#define DREG(str,rname) \
+	DBG(str); \
+	DBG(":\t") ;			\
+	lw	a0,rname(p64011) ;	\
+	HTOLL(a0,t0) ;			\
+	jal	_dbghex ;		\
+	DBG("\r\n")
+	
+	DBG("GT-64120 settings:\r\n")
+        DREG("DRAMPAR_BANK0   (44c)",GT_DRAMPAR_BANK0)
+        DREG("DRAMPAR_BANK1   (450)",GT_DRAMPAR_BANK1)
+        DREG("DRAMPAR_BANK2   (454)",GT_DRAMPAR_BANK2)
+        DREG("DRAMPAR_BANK3   (458)",GT_DRAMPAR_BANK3)
+        DREG("PAS_RAS10LO     (008)",GT_PAS_RAS10LO)
+        DREG("PAS_RAS10HI     (010)",GT_PAS_RAS10HI)
+        DREG("PAS_RAS32LO     (018)",GT_PAS_RAS32LO)
+        DREG("PAS_RAS32HI     (020)",GT_PAS_RAS32HI)
+        DREG("DDAS_RAS0LO     (400)",GT_DDAS_RAS0LO)
+        DREG("DDAS_RAS0HI     (404)",GT_DDAS_RAS0HI)
+        DREG("DDAS_RAS1LO     (408)",GT_DDAS_RAS1LO)
+        DREG("DDAS_RAS1HI     (40c)",GT_DDAS_RAS1HI)
+        DREG("DDAS_RAS2LO     (410)",GT_DDAS_RAS2LO)
+        DREG("DDAS_RAS2HI     (414)",GT_DDAS_RAS2HI)
+        DREG("DDAS_RAS3LO     (418)",GT_DDAS_RAS3LO)
+        DREG("DDAS_RAS3HI     (41c)",GT_DDAS_RAS3HI)
+        DREG("GT_DRAM_CFG     (448)",GT_DRAM_CFG)
+        DREG("GT_DEVPAR_BANK0 (45c)",GT_DEVPAR_BANK0)
+        DREG("GT_DEVPAR_BANK1 (460)",GT_DEVPAR_BANK1)
+        DREG("GT_DEVPAR_BANK2 (464)",GT_DEVPAR_BANK2)
+        DREG("GT_DEVPAR_BANK3 (468)",GT_DEVPAR_BANK3)
+        DREG("GT_IPCI_TOR     (c04)",GT_IPCI_TOR)
+#endif
+		
+	/* we can now initialise the caches for a fast clear_mem */
+	SBD_DISPLAY ('C','A','C','H',CHKPNT_CACH)
+	DBG("init_cache\r\n")
+//	jal	mips_init_cache
+
+.noinit:
+
+	/* initialise tlb */
+	SBD_DISPLAY ('I','T','L','B', CHKPNT_ITLB)
+	DBG("init_tlb\r\n")
+//	bal	init_tlb 
+
+//	DBG("sbdreset completed\r\n")
+//	move	ra,rasave
+        j       GetExtendedMemorySize
+        nop
+
+END(sbdreset)
+
+LEAF(_sbd_memfail)
+	SBD_DISPLAY ('!','M','E','M',CHKPNT_0MEM)
+1:	b	1b
+	j	ra
+END(_sbd_memfail)
+
+	.rdata
+RefreshBits:
+	.word	htoll(GT_DRAMPAR_Refresh512)
+	.word	htoll(GT_DRAMPAR_Refresh1024)
+	.word	htoll(GT_DRAMPAR_Refresh2048)
+	.word	htoll(GT_DRAMPAR_Refresh4096)
+	.text
+
+/* DRAM: */
+#define GT_DRAM_CFG_INIT \
+        GT_DRAM_CFG_RefIntCnt(160) | \
+        GT_DRAM_CFG_StagRefOn | \
+        GT_DRAM_CFG_ADSFunctDRAM | \
+        GT_DRAM_CFG_DRAMLatchActive
+
+/* serial port:  widest timings even 8 bit bus, latch enabled no parity */
+#define GT_DEVPAR_SERIALINIT \
+        GT_DEVPAR_TurnOff(7) | \
+        GT_DEVPAR_AccToFirst(15) | \
+        GT_DEVPAR_AccToNext(15) | \
+        GT_DEVPAR_ADStoWr(7) | \
+        GT_DEVPAR_WrActive(7) | \
+        GT_DEVPAR_WrHigh(7) | \
+        GT_DEVPAR_DevWidth8 | \
+        GT_DEVPAR_DevLocEven | \
+        GT_DEVPAR_LatchFunctTransparent | \
+        GT_DEVPAR_ParityDisable | \
+        GT_DEVPAR_Reserved
+
+/* PCI: */
+#define GT_IPCI_TOR_INIT \
+        GT_IPCI_TOR_Timeout0(255) | \
+        GT_IPCI_TOR_Timeout1(255) | \
+        GT_IPCI_TOR_RetryCtr(0)
+
+#define INIT(addr,val) \
+        .word   addr, val
+#define GTINIT(addr,val) \
+        INIT(PHYS_TO_K1(GT64011_BASE+(addr)), htoll(val))
+
+        .rdata
+reginittab:
+
+        /* disable ras1:0 and ras3:2 decodes */
+        GTINIT(GT_PAS_RAS10LO,  GT_PAS_LOMASK_Low);
+        GTINIT(GT_PAS_RAS10HI,  0);
+        GTINIT(GT_PAS_RAS32LO,  GT_PAS_LOMASK_Low);
+        GTINIT(GT_PAS_RAS32HI,  0);
+
+        /* disable RAS[0123] */
+        GTINIT(GT_DDAS_RAS0LO,  GT_DDAS_LOMASK_Low)
+        GTINIT(GT_DDAS_RAS0HI,  0);
+        GTINIT(GT_DDAS_RAS1LO,  GT_DDAS_LOMASK_Low)
+        GTINIT(GT_DDAS_RAS1HI,  0);
+        GTINIT(GT_DDAS_RAS2LO,  GT_DDAS_LOMASK_Low)
+        GTINIT(GT_DDAS_RAS2HI,  0);
+        GTINIT(GT_DDAS_RAS3LO,  GT_DDAS_LOMASK_Low)
+        GTINIT(GT_DDAS_RAS3HI,  0);
+
+        /* 0x45c, 0x460, 0x464, 0x468 */
+	/*GTINIT(GT_DEVPAR_BANK0, GT_DEVPAR_SERIALINIT)*/
+        GTINIT(GT_DEVPAR_BANK0, 0x3847de60)
+        GTINIT(GT_DEVPAR_BANK1, 0x146fffff)
+        GTINIT(GT_DEVPAR_BANK2, 0x144fffff)
+        GTINIT(GT_DEVPAR_BANK3, 0x167fffff)
+
+        GTINIT(GT_IPCI_TOR,     GT_IPCI_TOR_INIT)
+        INIT(0,0)
+        .text
+
+        .globl sbddelay
+
+LEAF(sbdberrenb)
+	mfc0	v0,C0_SR
+	li	t0,SR_DE	
+	bnez	a0,1f
+	or	t1,v0,t0	# disable cache/parity errors (SR_DE = 1)
+	b	2f
+1:	not	t1,t0		# enable cache/parity errors (SR_DE = 0)
+	and	t1,v0
+2:	mtc0	t1,C0_SR
+	and	v0,t0		# get old SR_DE bit
+	xor	v0,t0		# and invert to make it an enable bit
+	j	ra
+END(sbdberrenb)
+
+
+LEAF(sbdberrcnt)
+	move	v0,zero
+	j	ra
+END(sbdberrcnt)
+
+	.lcomm	wbfltmp,4
+
+LEAF(wbflush)
+//XLEAF(mips_wbflush)
+	sync
+	la	t0,wbfltmp
+	or	t0,K1BASE
+	lw	zero,0(t0)
+	j	ra
+END(wbflush)
+
+
+LEAF(sbddelay)
+	li	t1,CACHEUS
+	and	t0,ra,0x20000000
+	beqz	t0,1f
+	li	t1,ROMUS
+1:	mul	a0,t1
+	subu	a0,15		# approx number of loops so far
+
+	.set	noreorder	
+	.set	nomacro
+	nop
+2:	bgtz	a0,2b
+	subu	a0,1
+	.set	macro
+	.set	reorder
+
+	j	ra
+END(sbddelay)
+
+#include "meminit.S"
+
+
+LEAF(mips_cycle)
+	.set	noreorder	
+	.set	nomacro
+1:	bgtz	a0,1b
+	subu	a0,1
+	.set	macro
+	.set	reorder
+	j	ra
+END(mips_cycle)
+
+LEAF(init_ns16550_chan_b)
+	# enable 16550 fifo if it is there
+        li      a0,NS16550_CHANB 
+        li	t0,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
+	sb	t0,FIFO(a0)
+
+	/* convert baud rate in a1 into register value */
+        li	t2,NS16550_HZ/(16*115200)	# brtc = CLK/16/speed
+
+	li	t0,CFCR_DLAB			# select brtc divisor
+	sb	t0,CFCR(a0)
+	sb	t2,DATA(a0)			# store divisor lsb
+	srl	t2,8	
+	sb	t2,IER(a0)			# store divisor msb
+
+	li	t0,CFCR_8BITS			# set 8N1 mode
+	sb	t0,CFCR(a0)
+
+	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS 
+  	sb	t0,MCR(a0)
+ 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!) 
+	sb	t0,IER(a0)
+
+	move	v0,zero				# indicate success
+	j	ra
+	
+END(init_ns16550_chan_b)
+
+LEAF(init_ns16550_chan_a)
+	# enable 16550 fifo if it is there
+        li      a0,NS16550_CHANA 
+        li	t0,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
+	sb	t0,FIFO(a0)
+
+	/* convert baud rate in a1 into register value */
+        li	t2,NS16550_HZ/(16*9600)		# brtc = CLK/16/speed
+
+	li	t0,CFCR_DLAB			# select brtc divisor
+	sb	t0,CFCR(a0)
+	sb	t2,DATA(a0)			# store divisor lsb
+	srl	t2,8	
+	sb	t2,IER(a0)			# store divisor msb
+
+	li	t0,CFCR_8BITS			# set 8N1 mode
+	sb	t0,CFCR(a0)
+
+	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS 
+  	sb	t0,MCR(a0)
+ 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!) 
+	sb	t0,IER(a0)
+
+	move	v0,zero				# indicate success
+	j	ra
+	
+END(init_ns16550_chan_a)
+
+#endif /* EVB64120A */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/compressed/xfer.c linux/arch/mips/galileo-boards/ev64120/compressed/xfer.c
--- linux.orig/arch/mips/galileo-boards/ev64120/compressed/xfer.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/compressed/xfer.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,114 @@
+/*
+ *  arch/mips/galileo/compressed/xfer.c
+ *
+ *  By RidgeRun Inc,
+ *
+ *  Xfer an image from flash to ram.
+ *  For use with Galileo EVB64120A MIPS eval board.
+ */
+
+#include "linux/serial_reg.h"
+
+#define port 0xbd000000
+#define inb(addr) (*(volatile unsigned char *) ((unsigned long)(addr)))
+#define outb(b,addr) (*(volatile unsigned char *) ((unsigned long)(addr)) = (b))
+
+#ifdef RUNNINGFROMFLASH
+// This is where our image of interest is mapped to
+// when the jumbers are set for booting out of flash.
+// (flash part starts at address 0xbfC00000)
+#define srcAddr 0xbfC20000
+#else
+// This is where our image of interest is mapped to
+// when the jumbers are set for booting out of eprom.
+// (flash part starts at address 0xbf000000)
+#define srcAddr 0xbf020000
+#endif
+
+static int PortAddress(unsigned int channel, unsigned char reg);
+static void inline cons_hook(void);
+static void print_message(const char *string);
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+void XferToRam(void)
+{
+	unsigned int temp;
+	void (*entry_point) (void);
+
+	cons_hook();
+
+	print_message("Copying image from Flash to Ram.\n");
+	for (temp = 0; temp < (0x100000 - 0x20000); temp = temp + 4) {
+		*(volatile unsigned int *) (temp + 0xa0400000) =
+		    *(volatile unsigned int *) (temp + srcAddr);
+		if (*(volatile unsigned int *) (temp + 0xa0400000) !=
+		    *(volatile unsigned int *) (temp + srcAddr)) {
+			print_message
+			    ("Error!: copy verification failed.\n");
+			break;
+		}
+	}
+
+	print_message("Now jumping to the code just xferred to ram.\n");
+	entry_point = (void *) 0x80400000;
+	entry_point();
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+static int PortAddress(unsigned int channel, unsigned char reg)
+{
+	unsigned int channelOffset = 0x20;
+	unsigned int regDelta = 4;
+	return (port + (channel * channelOffset) + (reg * regDelta));
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+static void cons_hook(void)
+{
+	register int comstat;
+	unsigned temp;
+	unsigned int channel = 1;	// Channel 1 is the main serial
+	// connector of the EVB64120A. Channel 0
+	// is the secondary serial port (typically
+	// the unsoldered connector of the board).
+
+	temp = *(unsigned int *) 0xb4000464;
+	*(unsigned int *) 0xb4000464 = 0xffff4f14;
+
+	// Set Baud Rate, baud=115K
+	outb(0x83, PortAddress(channel, UART_LCR));
+	outb(0x00, PortAddress(channel, UART_DLM));
+	outb(0x02, PortAddress(channel, UART_DLL));
+	outb(0x03, PortAddress(channel, UART_LCR));
+
+	comstat = inb(PortAddress(channel, UART_LSR));
+	comstat = inb(PortAddress(channel, UART_RX));
+	outb(0x00, PortAddress(channel, UART_IER));
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+static void print_message(const char *string)
+{
+	register int count, loop;
+	/* Display Opening Message */
+	for (count = 0; string[count]; count++) {
+		if (string[count] == '\n') {
+			*(char *) 0xbd000020 = '\r';
+		}
+		*(char *) 0xbd000020 = string[count];
+		for (loop = 0; loop < 2000; loop++) {
+		}
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/dma.c linux/arch/mips/galileo-boards/ev64120/dma.c
--- linux.orig/arch/mips/galileo-boards/ev64120/dma.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/dma.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,168 @@
+/* DMA.C - DMA functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This file gives the user a complete interface to the powerful DMA engines,
+including functions for controling the priority mechanism.
+To fully understand the capabilities of the DMA engines please spare some 
+time to go trough the spec.
+*/
+
+/* includes */
+
+#ifdef __linux__
+#include <asm/galileo/evb64120A/core.h>
+#include <asm/galileo/evb64120A/dma.h>
+#else
+#include "Core.h"
+#include "DMA.h"
+#endif
+/********************************************************************
+* dmaCommand - Write a command to a DMA channel 
+*
+* Inputs: DMA_ENGINE channel - choosing one of the four engine.
+*         unsigned int command - The command to be written to the control register.
+* Returns: false if one of the parameters is erroneous else returns true. 
+*********************************************************************/
+
+bool dmaCommand(DMA_ENGINE channel, unsigned int command)
+{
+	if (channel > LAST_DMA_ENGINE)
+		return false;
+	GT_REG_WRITE(CHANNEL0CONTROL + channel * 4, command);
+	return true;
+}
+
+/********************************************************************
+* dmaTransfer - transfer data from sourceAddr to destAddr on DMA channel
+* Inputs:
+*   DMA_RECORED *nextRecoredPointer: If we are using chain mode DMA transfer,
+*   then this pointer should point to the next recored,otherwise it should be 
+*   NULL.
+*   VERY IMPORTANT !!! When using chain mode, the records must be 16 Bytes 
+*   aligned, the function will take care of that for you, but you need to 
+*   allocate one more record for that, meaning: if you are having 3 records ,
+*   declare 4 (see the example bellow) and start using the second one.
+*   Example:
+*   Performing a chain mode DMA transfer(Copy a 1/4 mega of data using 
+*   chain mode DMA):
+*    DMA_RECORED dmaRecoredArray[4];
+*    dmaRecoredArray[1].ByteCnt = _64KB;
+*    dmaRecoredArray[1].DestAdd = destAddress + _64KB;
+*    dmaRecoredArray[1].SrcAdd  = sourceAddress + _64KB;
+*    dmaRecoredArray[1].NextRecPtr = &dmaRecoredArray[2];
+*    dmaRecoredArray[2].ByteCnt = _64KB;
+*    dmaRecoredArray[2].DestAdd = destAddress + 2*_64KB;
+*    dmaRecoredArray[2].SrcAdd  = sourceAddress + 2*_64KB;
+*    dmaRecoredArray[2].NextRecPtr = &dmaRecoredArray[3];
+*    dmaRecoredArray[3].ByteCnt = _64KB;
+*    dmaRecoredArray[3].DestAdd = destAddress + 3*_64KB;
+*    dmaRecoredArray[3].SrcAdd  = sourceAddress + 3*_64KB;
+*    dmaRecoredArray[3].NextRecPtr = NULL;
+*    performCmDma(0,sourceAddress,destAddress,_64KB,PLAIN,WAIT_TO_END,
+*                            &dmaRecoredArray[1]);
+* Returns: NO_SUCH_CHANNEL if channel does not exist, CHANNEL_BUSY if channel
+*          is active and true if the transfer ended successfully
+*********************************************************************/
+
+DMA_STATUS dmaTransfer(DMA_ENGINE channel, unsigned int sourceAddr,
+		       unsigned int destAddr, unsigned int numOfBytes,
+		       unsigned int command,
+		       DMA_RECORED * nextRecoredPointer)
+{
+	unsigned int tempData, checkBits, alignmentOffset = 0;
+	DMA_RECORED *next = nextRecoredPointer;
+
+	if (channel > LAST_DMA_ENGINE)
+		return NO_SUCH_CHANNEL;
+	if (numOfBytes > 0xffff)
+		return GENERAL_ERROR;
+	if (isDmaChannelActive(channel))
+		return CHANNEL_BUSY;
+	if (next != NULL) {	/* case of chain Mode */
+		alignmentOffset = ((unsigned int) next % 16);
+	}
+	checkBits = command & 0x6000000;
+	if (checkBits == 0) {
+		while (next != NULL) {
+			WRITE_WORD((unsigned int) next - alignmentOffset,
+				   next->ByteCnt);
+			tempData = (unsigned int) next->SrcAdd;
+			WRITE_WORD((unsigned int) next + 4 -
+				   alignmentOffset, tempData & 0x5fffffff);
+			tempData = (unsigned int) next->DestAdd;
+			WRITE_WORD((unsigned int) next + 8 -
+				   alignmentOffset, tempData & 0x5fffffff);
+			tempData = (unsigned int) next->NextRecPtr;
+			WRITE_WORD((unsigned int) next + 12 -
+				   alignmentOffset,
+				   tempData & 0x5fffffff -
+				   alignmentOffset);
+			next = (DMA_RECORED *) tempData;
+			if (next == nextRecoredPointer)
+				next = NULL;
+		}
+	}
+	GT_REG_WRITE(CHANNEL0_DMA_BYTE_COUNT + channel * 4, numOfBytes);
+	tempData = sourceAddr;
+	GT_REG_WRITE(CHANNEL0_DMA_SOURCE_ADDRESS + channel * 4,
+		     tempData & 0x5fffffff);
+	tempData = destAddr;
+	GT_REG_WRITE(CHANNEL0_DMA_DESTINATION_ADDRESS + channel * 4,
+		     tempData & 0x5fffffff);
+	if (nextRecoredPointer != NULL) {
+		tempData =
+		    (unsigned int) nextRecoredPointer - alignmentOffset;
+		GT_REG_WRITE(CHANNEL0NEXT_RECORD_POINTER + 4 * channel,
+			     tempData & 0x5fffffff);
+		command = command | CHANNEL_ENABLE;
+	} else {
+		command = command | CHANNEL_ENABLE | NON_CHAIN_MOD;
+	}
+	/* Activate DMA engine By writting to dmaControlRegister */
+	GT_REG_WRITE(CHANNEL0CONTROL + channel * 4, command);
+
+	return DMA_OK;
+}
+
+/********************************************************************
+* isDmaChannelActive - check if channel is busy
+*
+* Inputs: channel number
+* RETURNS: True if the channel is busy, false otherwise.
+*********************************************************************/
+
+bool isDmaChannelActive(DMA_ENGINE channel)
+{
+	unsigned int data;
+
+	if (channel > LAST_DMA_ENGINE)
+		return false;
+	GT_REG_READ(CHANNEL0CONTROL + 4 * channel, &data);
+	if (data & DMA_ACTIVITY_STATUS)
+		return true;
+	else
+		return false;
+}
+
+
+/********************************************************************
+* changeDmaPriority - update the arbiter`s priority for channels 0-3 
+*
+* Inputs: priority  for channels 0-1, priority  for channels 2-3, 
+          priority for groups and other priority options   
+* RETURNS: false if one of the parameters is erroneous and true else
+*********************************************************************/
+
+bool changeDmaPriority(PRIO_CHAN_0_1 prio_01, PRIO_CHAN_2_3 prio_23,
+		       PRIO_GROUP prioGrp, PRIO_OPT prioOpt)
+{
+	unsigned int prioReg = 0;
+
+	prioReg = (prio_01 & 0x3) + ((prio_23 & 0x3) << 2) +
+	    ((prioGrp & 0x3) << 4) + (prioOpt << 6);
+	GT_REG_WRITE(ARBITER_CONTROL, prioReg);
+	return true;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/i2o.c linux/arch/mips/galileo-boards/ev64120/i2o.c
--- linux.orig/arch/mips/galileo-boards/ev64120/i2o.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/i2o.c	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,689 @@
+/* i2o.c - Drivers for the I2O */
+
+/* Copyright - Galileo technology. */
+
+/*includes*/
+
+#include <linux/module.h>
+
+#ifdef __linux__
+#include <asm/galileo-boards/evb64120A/core.h>
+#include <asm/galileo-boards/evb64120A/i2o.h>
+#else
+#include "Core.h"
+#include "i2o.h"
+#endif
+
+/********************************************************************
+* getInBoundMessage - When the GT is configured for I2O support
+*                     it can receive a message from an agent on the pci bus.
+*                     This message is a 32 bit wide and can be read by
+*                     the CPU.
+*                     The messaging unit contains two sets of registers
+*                     so, actually it can receive a 64 bit message.
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: Data received from the remote agent.
+*********************************************************************/
+unsigned int getInBoundMessage(I2O_MESSAGE_REG messageRegNum)
+{
+	unsigned int regValue;
+
+	GT_REG_READ(INBOUND_MESSAGE_REGISTER0_CPU_SIDE + 4 * messageRegNum,
+		    &regValue);
+	return (regValue);
+}
+
+
+/********************************************************************
+* checkInboundIntAndClear - When a message is received an interrupt is 
+*                           generated, to enable polling instead the use of
+*                           an interrupt handler the user can use this fuction.
+*                           You will need to mask the incomming interrupt for
+*                           proper use.
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: true if the corresponding bit in the cause register is set otherwise
+*          false.
+*********************************************************************/
+bool checkInBoundIntAndClear(I2O_MESSAGE_REG messageRegNum)
+{
+	unsigned int regValue;
+
+	GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regValue);
+	/* clears bit 0 for message register 0 or bit 1 for message register 1 */
+	GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE,
+		     BIT1 * messageRegNum);
+	switch (messageRegNum) {
+	case MESSAGE_REG_0:
+		if (regValue & BIT0)
+			return true;
+		break;
+	case MESSAGE_REG_1:
+		if (regValue & BIT1)
+			return true;
+		break;
+	}
+	return false;
+}
+
+/********************************************************************
+* sendOutBoundMessage - When the GT is configured for I2O support
+*                     it can send a message to an agent on the pci bus.
+*                     This message is a 32 bit wide and can be read by
+*                     the PCI agent.
+*                     The messaging unit contains two sets of registers
+*                     so, actually it can send a 64 bit message.
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+*         unsigned int message - Message to be sent.   
+* OUTPUT: N/A.
+* RETURNS: true.
+*********************************************************************/
+bool sendOutBoundMessage(I2O_MESSAGE_REG messageRegNum,
+			 unsigned int message)
+{
+	GT_REG_WRITE(OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE +
+		     4 * messageRegNum, message);
+	return true;
+}
+
+/********************************************************************
+* checkOutboundInt - When the CPU sends a message to the Outbound
+*                    register it generates an interrupt which is refelcted on
+*                    the Outbound Interrupt cause register, the interrupt can
+*                    be cleard only by the PCI agent which read the message. 
+*                    After sending the message you can acknowledge it by
+*                    monitoring the corresponding bit in the cause register.
+*
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: true if the corresponding bit in the cause register is set otherwise
+*          false.
+*********************************************************************/
+bool outBoundMessageAcknowledge(I2O_MESSAGE_REG messageRegNum)
+{
+	unsigned int regValue;
+
+	GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regValue);
+	switch (messageRegNum) {
+	case MESSAGE_REG_0:
+		if (regValue & BIT0)
+			return true;
+		break;
+	case MESSAGE_REG_1:
+		if (regValue & BIT1)
+			return true;
+		break;
+	}
+	return false;
+}
+
+/********************************************************************
+* maskInBoundMessageInterrupt - Mask the inbound interrupt, when masking
+*                               the interrupt you can work in polling mode
+*                               using the checkInboundIntAndClear function. 
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: true.
+*********************************************************************/
+bool maskInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum)
+{
+	switch (messageRegNum) {
+	case MESSAGE_REG_0:
+		SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			     BIT0);
+		break;
+	case MESSAGE_REG_1:
+		SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			     BIT1);
+		break;
+	}
+	return true;
+}
+
+/********************************************************************
+* enableInBoundMessageInterrupt - unMask the inbound interrupt. 
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: true.
+*********************************************************************/
+bool enableInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum)
+{
+	switch (messageRegNum) {
+	case MESSAGE_REG_0:
+		RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			       BIT0);
+		break;
+	case MESSAGE_REG_1:
+		RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			       BIT1);
+		break;
+	}
+	return true;
+}
+
+/********************************************************************
+* maskOutboundMessageInterrupt - Mask the out bound interrupt, when doing so
+*                           the PCI agent needs to poll on the interrupt
+*                           cause register to monitor an incoming message. 
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: true.
+*********************************************************************/
+bool maskOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum)
+{
+	switch (messageRegNum) {
+	case MESSAGE_REG_0:
+		SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			     BIT0);
+		break;
+	case MESSAGE_REG_1:
+		SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			     BIT1);
+		break;
+	}
+	return true;
+}
+
+/********************************************************************
+* enableOutboundMessageInterrupt - Mask the out bound interrupt, when doing so
+*                           the PCI agent needs to poll on the interrupt
+*                           cause register to monitor an incoming message. 
+* 
+* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register.
+* OUTPUT: N/A.
+* RETURNS: true.
+*********************************************************************/
+bool enableOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum)
+{
+	switch (messageRegNum) {
+	case MESSAGE_REG_0:
+		RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			       BIT0);
+		break;
+	case MESSAGE_REG_1:
+		RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+			       BIT1);
+		break;
+	}
+	return true;
+}
+
+/********************************************************************
+* initiateOutBoundDoorBellInt - Setting a bit in this register to '1' by the 
+*                       CPU generates a PCI interrupt (if it is not masked by
+*                       the Outbound interrupt Mask register)
+*                       Only the PCI agent which recieved the interrupt can
+*                       clear it, only after clearing all the bits the
+*                       interrupt will be de-asserted.
+* 
+* INPUTS: unsigned int data - Requested interrupt bits.
+* OUTPUT: N/A.
+* RETURNS: true.
+*********************************************************************/
+bool initiateOutBoundDoorBellInt(unsigned int data)
+{
+	GT_REG_WRITE(OUTBOUND_DOORBELL_REGISTER_CPU_SIDE, data);
+	return true;
+}
+
+/********************************************************************
+* readInBoundDoorBellInt - Read the in bound door bell interrupt cause
+*                          register.
+* 
+* OUTPUT:  N/A.
+* RETURNS: The 32 bit interrupt cause register.
+*********************************************************************/
+unsigned int readInBoundDoorBellInt()
+{
+	unsigned int regData;
+	GT_REG_READ(INBOUND_DOORBELL_REGISTER_CPU_SIDE, &regData);
+	return regData;
+}
+
+/********************************************************************
+* clearInBoundDoorBellInt - An interrupt generated by a PCI agent through
+*                           the in bound door bell mechanisem can be cleared
+*                           only by the CPU. The interrupt will be de-asserted
+*                           only if all the bits which where set by the PCI
+*                           agent are cleared.
+* 
+* INPUTS:  unsigned int data - Bits to be cleared.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool clearInBoundDoorBellInt(unsigned int data)
+{
+	GT_REG_WRITE(INBOUND_DOORBELL_REGISTER_CPU_SIDE, data);
+	return true;
+}
+
+/********************************************************************
+* isInBoundDoorBellInterruptSet - Check if Inbound Doorbell Interrupt is set,
+*                                 can be used for polling mode.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true if the corresponding bit in the cause register is set otherwise
+*          false.
+*********************************************************************/
+bool isInBoundDoorBellInterruptSet()
+{
+	unsigned int regData;
+
+	GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regData);
+	return (regData & BIT2);
+}
+
+/********************************************************************
+* isOutBoundDoorBellInterruptSet - Check if out bound Doorbell Interrupt is 
+*                                  set, can be used for acknowledging interrupt
+*                                  handling by the agent who recieived the
+*                                  interrupt. 
+* 
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true if the corresponding bit in the cause register is set otherwise
+*          false.
+*********************************************************************/
+bool isOutBoundDoorBellInterruptSet()
+{
+	unsigned int regData;
+
+	GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regData);
+	return (regData & BIT2);
+}
+
+/********************************************************************
+* maskInboundDoorBellInterrupt - Mask the Inbound Doorbell Interrupt.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool maskInBoundDoorBellInterrupt()
+{
+	SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
+	return true;
+}
+
+/********************************************************************
+* enableInboundDoorBellInterrupt - unMask the Inbound Doorbell Interrupt.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool enableInBoundDoorBellInterrupt()
+{
+	RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
+	return true;
+}
+
+/********************************************************************
+* maskOutboundDoorBellInterrupt - Mask the Outbound Doorbell Interrupt.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool maskOutBoundDoorBellInterrupt()
+{
+	SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
+	return true;
+}
+
+/********************************************************************
+* enableOutboundDoorBellInterrupt - unMask the Outbound Doorbell Interrupt.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool enableOutBoundDoorBellInterrupt()
+{
+	RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
+	return true;
+}
+
+/********************************************************************
+* circularQueueEnable - Initialize the I2O messaging mechanism.
+* 
+* INPUTS:   CIRCULE_QUEUE_SIZE cirQueSize - Bits 5:1 in the:
+*           Queue Control Register, Offset 0x50 (0x1c50).
+*           Defines the queues size (refer to the data sheet
+*           for more information)
+*          unsigned int queueBaseAddr - The base address for the first queue.
+*           The other queues base Address will be determined as follows:
+*           Inbound Free = queueBaseAddr
+*           Inbound Post = queueBaseAddr + cirQueSize
+*           Outbound Post = queueBaseAddr + cirQueSize
+*           
+* OUTPUT:  N/A.
+* RETURNS: true.
+*
+*  The Circular Queue Starting Addresses as written in the spec:
+*  ----------------------------------------
+*  |    Queue       |  Starting Address   |
+*  |----------------|---------------------|
+*  | Inbound Free   |       QBAR          |
+*  | Inbound Post   | QBAR + Queue Size   |
+*  | Outbound Post  | QBAR + 2*Queue Size |
+*  | Outbound Free  | QBAR + 3*Queue Size |
+*  ----------------------------------------
+*********************************************************************/
+bool circularQueueEnable(CIRCULAR_QUEUE_SIZE cirQueSize,
+			 unsigned int queueBaseAddr)
+{
+	unsigned int regData;
+
+	regData = BIT0 | (cirQueSize << 1);
+	/* Enable Queue Operation */
+	GT_REG_WRITE(QUEUE_CONTROL_REGISTER_CPU_SIDE, regData);
+	/* Writing The base Address for the 4 Queues */
+	GT_REG_WRITE(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, queueBaseAddr);
+	/* Update The Inbound Free Queue Base Address, offset=0 */
+	GT_REG_WRITE(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, 0);
+	GT_REG_WRITE(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, 0);
+	/* Update The Inbound Post Queue Base Address, offset=_16K*cirQueSize */
+	GT_REG_WRITE(INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE,
+		     _16K * cirQueSize);
+	GT_REG_WRITE(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE,
+		     _16K * cirQueSize);
+	/* Update The Outbound Post Queue Base Address, offset=2*_16K*cirQueSize */
+	GT_REG_WRITE(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE,
+		     2 * _16K * cirQueSize);
+	GT_REG_WRITE(OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE,
+		     2 * _16K * cirQueSize);
+	/* Update The Outbound Free Queue Base Address, offset=3*_16K*cirQueSize */
+	GT_REG_WRITE(OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE,
+		     3 * _16K * cirQueSize);
+	GT_REG_WRITE(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE,
+		     3 * _16K * cirQueSize);
+	return true;
+}
+
+/********************************************************************
+* inBoundPostQueuePop - Two actions are being taken upon pop: 
+*           1) Getting out the data from the Queue`s head.
+*           2) Increment the tail pointer in a cyclic way (The HEAD is
+*              incremented automaticaly by the GT) 
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: Data pointed by tail.
+*********************************************************************/
+unsigned int inBoundPostQueuePop()
+{
+	unsigned int tailAddrPointer;
+	unsigned int data;
+	unsigned int cirQueSize;
+	unsigned int qBar;
+	unsigned int inBoundPostQbase;
+
+	/* Gets the Inbound Post TAIL pointer */
+	GT_REG_READ(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE,
+		    &tailAddrPointer);
+	/* Gets the Data From the pointer Address */
+	READ_WORD(tailAddrPointer, &data);
+	/* incrementing head process: */
+	/* Gets the fifo's base Address */
+	GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar);
+	qBar = qBar & 0xfff00000;
+	/* Gets the fifo's size */
+	GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize);
+	cirQueSize = 0x1f && (cirQueSize >> 1);
+	/* calculating The Inbound Post Queue Base Address */
+	inBoundPostQbase = qBar + 1 * cirQueSize * _16K;
+	/* incrementing Inbound Post queue TAIL in a cyclic loop */
+	tailAddrPointer = inBoundPostQbase + ((tailAddrPointer + 4) %
+					      (_16K * cirQueSize));
+	/* updating the pointer back to INBOUND_POST_TAIL_POINTER_REGISTER */
+	GT_REG_WRITE(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE,
+		     tailAddrPointer);
+	return data;
+}
+
+/********************************************************************
+* isInBoundPostQueueInterruptSet - Check if in bound interrupt is set.
+*                                  can be used for polling mode.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true if the corresponding bit in the cause register is set otherwise
+*          false.
+*********************************************************************/
+bool isInBoundPostQueueInterruptSet()
+{
+	unsigned int regData;
+
+	GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regData);
+	return (regData & BIT4);	/* if set return '1' (true), else '0' (false) */
+}
+
+/********************************************************************
+* clearInBoundPostQueueInterrupt - Clears the Post queue interrupt.
+* 
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool clearInBoundPostQueueInterrupt()
+{
+	GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, BIT4);
+	return true;
+}
+
+/********************************************************************
+* maskInBoundPostQueueInterrupt - Mask the inbound interrupt, when masking
+*                                 the interrupt you can work in polling mode.
+*
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: 
+*********************************************************************/
+void maskInBoundPostQueueInterrupt()
+{
+	unsigned int regData;
+
+	GT_REG_READ(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, &regData);
+	GT_REG_WRITE(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+		     regData | BIT4);
+
+}
+
+/********************************************************************
+* enableInBoundPostQueueInterrupt - Enable interrupt when ever there is a new
+*                                   message from the PCI agent.
+* 
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS:
+*********************************************************************/
+void enableInBoundPostQueueInterrupt()
+{
+	unsigned int regData;
+
+	GT_REG_READ(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, &regData);
+	GT_REG_WRITE(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE,
+		     regData & 0xfffffffb);
+}
+
+/********************************************************************
+* inBoundFreeQueuePush - Two actions are being taken upon push: 
+*           1) Place the user`s data on the Queue`s head.
+*           2) Increment the haed pointer in a cyclic way (The tail is
+*              decremented automaticaly by the GT)
+* 
+* INPUTS:  unsigned int data - Data to be placed in the queue.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool inBoundFreeQueuePush(unsigned int data)
+{
+	unsigned int headPointer;
+	unsigned int cirQueSize;
+	unsigned int qBar;
+	unsigned int inBoundFreeQbase;
+
+	GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE,
+		    &headPointer);
+	/* placing the data in the queue */
+	WRITE_WORD(headPointer, data);
+	/* incrementing head process: */
+	/* Gets the fifo's base Address */
+	GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar);
+	qBar = qBar & 0xfff00000;
+	/* Gets the fifo's size */
+	GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize);
+	cirQueSize = 0x1f && (cirQueSize >> 1);
+	/* calculating The Inbound Free Queue Base Address */
+	inBoundFreeQbase = qBar;
+	/* incrementing Inbound Free queue HEAD in a cyclic loop */
+	headPointer =
+	    inBoundFreeQbase + ((headPointer + 4) % (_16K * cirQueSize));
+	/* updating the pointer back to OUTBOUND_POST_HEAD_POINTER_REGISTER */
+	GT_REG_WRITE(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE,
+		     headPointer);
+	return true;
+}
+
+/********************************************************************
+* isInBoundFreeQueueEmpty - Check if Inbound Free Queue Empty.
+*                           Can be used for acknowledging the messages
+*                           being sent by us to the PCI agent.
+* 
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true if the queue is empty , otherwise false.
+*********************************************************************/
+bool isInBoundFreeQueueEmpty()
+{
+	unsigned int inBoundFreeQueHead;
+	unsigned int inBoundFreeQueTail;
+
+	GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE,
+		    &inBoundFreeQueHead);
+	GT_REG_READ(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE,
+		    &inBoundFreeQueTail);
+	if (inBoundFreeQueHead == inBoundFreeQueTail) {
+		return true;
+	} else
+		return false;
+}
+
+/********************************************************************
+* outBoundPostQueuePush  - Two actions are being taken upon push: 
+*           1) Place the user`s data on the Queue`s head.
+*           2) Increment the haed pointer in a cyclic way (The tail is
+*              decremented automaticaly by the GT when the Agent on the
+*              PCI have read data from the Outbound Port).
+* 
+* INPUTS:  unsigned int data - Data to be placed in the queue`s head.
+* OUTPUT:  N/A.
+* RETURNS: true.
+*********************************************************************/
+bool outBoundPostQueuePush(unsigned int data)
+{
+	unsigned int headPointer;
+	unsigned int cirQueSize;
+	unsigned int qBar;
+	unsigned int outBoundPostQbase;
+
+	GT_REG_READ(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE,
+		    &headPointer);
+	/* placing the data in the queue (where the head point to..) */
+	WRITE_WORD(headPointer, data);
+	/* incrementing head process: */
+	/* Gets the fifo's base Address */
+	GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar);
+	qBar = qBar & 0xfff00000;
+	/* Gets the fifo's size */
+	GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize);
+	cirQueSize = 0x1f && (cirQueSize >> 1);
+	/* calculating The Outbound Post Queue Base Address */
+	outBoundPostQbase = qBar + 2 * cirQueSize * _16K;
+	/* incrementing Outbound Post queue in a cyclic loop */
+	headPointer =
+	    outBoundPostQbase + ((headPointer + 4) % (_16K * cirQueSize));
+	/* updating the pointer back to OUTBOUND_POST_HEAD_POINTER_REGISTER */
+	GT_REG_WRITE(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE,
+		     headPointer);
+	return true;
+}
+
+/********************************************************************
+* isOutBoundPostQueueEmpty - Check if Outbound Post Queue Empty.
+*                            Can be used for acknowledging the messages
+*                            being sent by us to the PCI agent.
+* 
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: true if the queue is empty , otherwise false.
+*********************************************************************/
+bool isOutBoundPostQueueEmpty()
+{
+	unsigned int outBoundPostQueHead;
+	unsigned int outBoundPostQueTail;
+
+	GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE,
+		    &outBoundPostQueHead);
+	GT_REG_READ(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE,
+		    &outBoundPostQueTail);
+	if (outBoundPostQueHead == outBoundPostQueTail) {
+		return true;
+	} else
+		return false;
+}
+
+/********************************************************************
+* outBoundFreeQueuePop - Two actions are being taken upon pop: 
+*           1) Getting out the data from the Queue`s head.
+*           2) Increment the tail pointer in a cyclic way (The HEAD is
+*              incremented automaticaly by the GT)
+* 
+* INPUTS:  N/A.
+* OUTPUT:  N/A.
+* RETURNS: Data pointed by tail.
+*********************************************************************/
+unsigned int outBoundFreeQueuePop()
+{
+	unsigned int tailAddrPointer;
+	unsigned int data;
+	unsigned int cirQueSize;
+	unsigned int qBar;
+	unsigned int outBoundFreeQbase;
+
+	/* Gets the Inbound Post TAIL pointer */
+	GT_REG_READ(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE,
+		    &tailAddrPointer);
+	/* Gets the Data From the pointer Address */
+	READ_WORD(tailAddrPointer, &data);
+	/* incrementing head process: */
+	/* Gets the fifo's base Address */
+	GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar);
+	qBar = qBar & 0xfff00000;
+	/* Gets the fifo's size */
+	GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize);
+	cirQueSize = 0x1f && (cirQueSize >> 1);
+	/* calculating The Inbound Post Queue Base Address */
+	outBoundFreeQbase = qBar + 3 * cirQueSize * _16K;
+	/* incrementing Outbound Free queue TAlL in a cyclic loop */
+	tailAddrPointer = outBoundFreeQbase + ((tailAddrPointer + 4) %
+					       (_16K * cirQueSize));
+	/* updating the pointer back to OUTBOUND_FREE_TAIL_POINTER_REGISTER */
+	GT_REG_WRITE(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE,
+		     tailAddrPointer);
+	return data;
+}
+
+
+EXPORT_SYMBOL(isInBoundDoorBellInterruptSet);
+EXPORT_SYMBOL(initiateOutBoundDoorBellInt);
+EXPORT_SYMBOL(clearInBoundDoorBellInt);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/int-handler.S linux/arch/mips/galileo-boards/ev64120/int-handler.S
--- linux.orig/arch/mips/galileo-boards/ev64120/int-handler.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/int-handler.S	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,113 @@
+/*
+ * int-handler.S
+ *
+ * Based on the cobalt handler.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+/*
+ * galileo_handle_int -
+ *      We check for the timer first, then check PCI ints A and D.
+ *      Then check for serial IRQ and fall through.
+ */
+		.align	5
+		.set	reorder
+		.set	noat
+		NESTED(galileo_handle_int, PT_SIZE, sp)
+		SAVE_ALL
+		CLI
+		.set	at
+		mfc0	t0,CP0_CAUSE  
+		mfc0	t2,CP0_STATUS
+
+		and	t0,t2
+        
+		andi	t1,t0,STATUSF_IP4 /* int2 hardware line (timer) */
+		bnez	t1,ll_galileo_irq
+		andi	t1,t0,STATUSF_IP2 /* int0 hardware line */
+		bnez	t1,ll_pci_intA
+		andi	t1,t0,STATUSF_IP5 /* int3 hardware line */
+		bnez	t1,ll_pci_intD
+		andi	t1,t0,STATUSF_IP6 /* int4 hardware line */
+		bnez	t1,ll_serial_irq
+		andi	t1,t0,STATUSF_IP7 /* compare int */
+		bnez	t1,ll_compare_irq
+		nop
+
+    /* wrong alarm or masked ... */
+		j	spurious_interrupt
+		nop
+		END(galileo_handle_int)
+	
+
+		.align	5
+		.set	reorder
+ll_galileo_irq:
+		li	a0,4
+		move	a1,sp
+		jal	do_IRQ
+		nop
+		j	ret_from_irq
+		nop
+
+		.align	5
+		.set	reorder
+ll_compare_irq:
+		li 	a0,7	
+		move	a1,sp
+		jal	do_IRQ
+		nop
+		j	ret_from_irq
+		nop
+
+		.align	5
+		.set	reorder
+ll_pci_intA:
+		move	a0,sp
+		jal	pci_intA
+		nop
+		j	ret_from_irq
+		nop
+
+#if 0
+		.align	5
+		.set	reorder
+ll_pci_intB:	
+		move 	a0,sp
+		jal	pci_intB
+		nop
+		j	ret_from_irq
+		nop
+
+		.align	5
+		.set	reorder
+ll_pci_intC:	
+		move 	a0,sp
+		jal	pci_intC
+		nop
+		j	ret_from_irq
+		nop
+#endif
+        
+		.align	5
+		.set	reorder
+ll_pci_intD:
+		move 	a0,sp
+		jal	pci_intD
+		nop
+		j	ret_from_irq
+		nop
+	
+		.align	5
+		.set	reorder
+ll_serial_irq:	
+		li	a0,6
+		move	a1,sp
+		jal	do_IRQ
+		nop
+		j	ret_from_irq
+		nop
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/irq-handler.c linux/arch/mips/galileo-boards/ev64120/irq-handler.c
--- linux.orig/arch/mips/galileo-boards/ev64120/irq-handler.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/irq-handler.c	2002-08-01 06:42:35.000000000 +0000
@@ -0,0 +1,270 @@
+/*
+ * Galileo Technology chip interrupt handler
+ *
+ *  Modified by RidgeRun, Inc.
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <asm/ptrace.h>
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/kernel_stat.h>
+#include <asm/io.h>
+#include <asm/gt64120.h>
+#include <asm/galileo-boards/ev64120.h>
+#include <asm/galileo-boards/ev64120int.h>
+
+/*
+ * These are interrupt handlers for the GT on-chip interrupts.  They all come
+ * in to the MIPS on a single interrupt line, and have to be handled and ack'ed
+ * differently than other MIPS interrupts.
+ */
+
+#if CURRENTLY_UNUSED
+
+struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
+void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
+
+/*
+ * hook_irq_handler
+ *
+ * Hooks IRQ handler to the system. When the system is interrupted
+ * the interrupt service routine is called.
+ *
+ * Inputs :
+ * int_cause - The interrupt cause number. In EVB64120 two parameters 
+ *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. 
+ * bit_num   - Indicates which bit number in the cause register
+ * isr_ptr   - Pointer to the interrupt service routine
+ *
+ * Outputs :
+ */
+void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
+{
+	irq_handlers[int_cause][bit_num].routine = isr_ptr;
+}
+
+
+/*
+ * enable_galileo_irq
+ *
+ * Enables the IRQ on Galileo Chip
+ *
+ * Inputs :
+ * int_cause -  The interrupt cause number. In EVB64120 two parameters 
+ *            are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
+ * bit_num   - Indicates which bit number in the cause register
+ *
+ * Outputs :
+ * 1 if succesful, 0 if failure
+ */
+int enable_galileo_irq(int int_cause, int bit_num)
+{
+	if (int_cause == INT_CAUSE_MAIN)
+		SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
+	else if (int_cause == INT_CAUSE_HIGH)
+		SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
+			     (1 << bit_num));
+	else
+		return 0;
+	return 1;
+}
+
+/*
+ * disable_galileo_irq
+ *
+ * Disables the IRQ on Galileo Chip
+ *
+ * Inputs :
+ * int_cause -  The interrupt cause number. In EVB64120 two parameters 
+ *            are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
+ * bit_num   - Indicates which bit number in the cause register
+ *
+ * Outputs :
+ * 1 if succesful, 0 if failure
+ */
+int disable_galileo_irq(int int_cause, int bit_num)
+{
+	if (int_cause == INT_CAUSE_MAIN)
+		RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
+			       (1 << bit_num));
+	else if (int_cause == INT_CAUSE_HIGH)
+		RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
+			       (1 << bit_num));
+	else
+		return 0;
+	return 1;
+}
+
+#endif				/*  UNUSED  */
+
+/*
+ * galileo_irq -
+ *
+ * Interrupt handler for interrupts coming from the Galileo chip.
+ * It could be timer interrupt, built in ethernet ports etc...
+ *
+ * Inputs :
+ *
+ * Outputs :
+ *
+ */
+static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+	unsigned int irq_src, int_high_src, irq_src_mask,
+	    int_high_src_mask;
+	int handled;
+	unsigned int count;
+	static int counter = 0;
+
+	GT_READ(GT_INTRCAUSE_OFS, &irq_src);
+	GT_READ(GT_INTRMASK_OFS, &irq_src_mask);
+	GT_READ(GT_HINTRCAUSE_OFS, &int_high_src);
+	GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask);
+	irq_src = irq_src & irq_src_mask;
+	int_high_src = int_high_src & int_high_src_mask;
+
+	handled = 0;
+
+	/* Execute all interrupt handlers */
+	/* Check for timer interrupt */
+	if (irq_src & 0x00000800) {
+		handled = 1;
+		irq_src &= ~0x00000800;
+		//    RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8);
+		do_timer(regs);
+	}
+
+	if (irq_src) {
+		printk(KERN_INFO
+		       "Other Galileo interrupt received irq_src %x\n",
+		       irq_src);
+#if CURRENTLY_UNUSED
+		for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) {
+			if (irq_src & (1 << count)) {
+				if (irq_handlers[INT_CAUSE_MAIN][count].
+				    routine) {
+					queue_task(&irq_handlers
+						   [INT_CAUSE_MAIN][count],
+						   &tq_immediate);
+					mark_bh(IMMEDIATE_BH);
+					handled = 1;
+				}
+			}
+		}
+#endif				/*  UNUSED  */
+	}
+	GT_WRITE(GT_INTRCAUSE_OFS, 0);
+	GT_WRITE(GT_HINTRCAUSE_OFS, 0);
+
+#undef GALILEO_I2O
+#ifdef GALILEO_I2O
+	/*
+	   Future I2O support.  We currently attach I2O interrupt handlers to the
+	   Galileo interrupt (int 4) and handle them in do_IRQ.
+	 */
+	if (isInBoundDoorBellInterruptSet()) {
+		printk(KERN_INFO "I2O doorbell interrupt received.\n");
+		handled = 1;
+	}
+
+	if (isInBoundPostQueueInterruptSet()) {
+		printk(KERN_INFO "I2O Queue interrupt received.\n");
+		handled = 1;
+	}
+
+	/*
+	   This normally would be outside of the ifdef, but since
+	   we're handling I2O outside of this handler, this
+	   printk shows up every time we get a valid I2O
+	   interrupt.  So turn this off for now.
+	 */
+	if (handled == 0) {
+		if (counter < 50) {
+			printk("Spurious Galileo interrupt...\n");
+			counter++;
+		}
+	}
+#endif
+}
+
+/*
+ * galileo_time_init -
+ *
+ * Initializes timer using galileo's built in timer.
+ *
+ *
+ * Inputs :
+ * irq - number of irq to be used by the timer
+ *
+ * Outpus :
+ *
+ */
+#ifdef CONFIG_SYSCLK_100
+#define Sys_clock (100 * 1000000)	// 100 MHz
+#endif
+#ifdef CONFIG_SYSCLK_83
+#define Sys_clock (83.333 * 1000000)	// 83.333 MHz
+#endif
+#ifdef CONFIG_SYSCLK_75
+#define Sys_clock (75 * 1000000)	// 75 MHz
+#endif
+
+/*
+ * This will ignore the standard MIPS timer interrupt handler that is passed
+ * in as *irq (=irq0 in ../kernel/time.c).  We will do our own timer interrupt
+ * handling.
+ */
+void galileo_time_init(struct irqaction *irq)
+{
+	extern irq_desc_t irq_desc[NR_IRQS];
+	static struct irqaction timer;
+
+	/* Disable timer first */
+	GT_WRITE(GT_TC_CONTROL_OFS, 0);
+	/* Load timer value for 100 Hz */
+	GT_WRITE(GT_TC3_OFS, Sys_clock / 100);
+
+	/*
+	 * Create the IRQ structure entry for the timer.  Since we're too early
+	 * in the boot process to use the "request_irq()" call, we'll hard-code
+	 * the values to the correct interrupt line.
+	 */
+	timer.handler = &galileo_irq;
+	timer.flags = SA_SHIRQ;
+	timer.name = "timer";
+	timer.dev_id = NULL;
+	timer.next = NULL;
+	timer.mask = 0;
+	irq_desc[TIMER].action = &timer;
+
+	/* Enable timer ints */
+	GT_WRITE(GT_TC_CONTROL_OFS, 0xc0);
+	/* clear Cause register first */
+	GT_WRITE(GT_INTRCAUSE_OFS, 0x0);
+	/* Unmask timer int */
+	GT_WRITE(GT_INTRMASK_OFS, 0x800);
+	/* Clear High int register */
+	GT_WRITE(GT_HINTRCAUSE_OFS, 0x0);
+	/* Mask All interrupts at High cause interrupt */
+	GT_WRITE(GT_HINTRMASK_OFS, 0x0);
+
+}
+
+void galileo_irq_init(void)
+{
+	int i, j;
+
+#if CURRENTLY_UNUSED
+	/* Reset irq handlers pointers to NULL */
+	for (i = 0; i < MAX_CAUSE_REGS; i++) {
+		for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
+			irq_handlers[i][j].next = NULL;
+			irq_handlers[i][j].sync = 0;
+			irq_handlers[i][j].routine = NULL;
+			irq_handlers[i][j].data = NULL;
+		}
+	}
+#endif
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/irq.c linux/arch/mips/galileo-boards/ev64120/irq.c
--- linux.orig/arch/mips/galileo-boards/ev64120/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/irq.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,456 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Code to handle irqs on GT64120A boards
+ *  Derived from mips/orion and Cort <cort@fsmlabs.com>
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/galileo-boards/ev64120int.h>
+
+#undef IRQ_DEBUG
+
+#ifdef IRQ_DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+
+asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
+
+#define MAX_AGENTS_PER_INT 21	/*  Random number  */
+unsigned char pci_int_irq[MAX_AGENTS_PER_INT];
+static int max_interrupts = 0;
+
+/*  Duplicate interrupt handlers.  */
+/********************************************************************
+ *pci_int(A/B/C/D) -
+ *	
+ *Calls all the handlers connected to PCI interrupt A/B/C/D
+ *
+ *Inputs :
+ *
+ *Outpus :
+ *
+ *********************************************************************/
+asmlinkage __inline__ void pci_intA(struct pt_regs *regs)
+{
+	unsigned int count = 0;
+	DBG(KERN_INFO "pci_intA, max_interrupts %d\n", max_interrupts);
+	for (count = 0; count < max_interrupts; count++) {
+		do_IRQ(pci_int_irq[count], regs);
+	}
+}
+
+asmlinkage __inline__ void pci_intD(struct pt_regs *regs)
+{
+	unsigned int count = 0;
+	DBG(KERN_INFO "pci_intD, max_interrupts %d\n", max_interrupts);
+	for (count = 0; count < max_interrupts; count++) {
+		do_IRQ(pci_int_irq[count], regs);
+	}
+}
+
+
+/* Function for careful CP0 interrupt mask access */
+static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
+{
+	unsigned long status = read_32bit_cp0_register(CP0_STATUS);
+	DBG(KERN_INFO "modify_cp0_intmask clr %x, set %x\n", clr_mask,
+	    set_mask);
+	DBG(KERN_INFO "modify_cp0_intmask status %x\n", status);
+	status &= ~((clr_mask & 0xFF) << 8);
+	status |= (set_mask & 0xFF) << 8;
+	DBG(KERN_INFO "modify_cp0_intmask status %x\n", status);
+	write_32bit_cp0_register(CP0_STATUS, status);
+}
+
+static inline void mask_irq(unsigned int irq_nr)
+{
+	modify_cp0_intmask(irq_nr, 0);
+}
+
+static inline void unmask_irq(unsigned int irq_nr)
+{
+	modify_cp0_intmask(0, irq_nr);
+}
+
+void disable_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	DBG(KERN_INFO "disable_irq, irq %d\n", irq_nr);
+	save_and_cli(flags);
+	if (irq_nr >= 8) {	// All PCI interrupts are on line 5 or 2
+		mask_irq(9 << 2);
+	} else {
+		mask_irq(1 << irq_nr);
+	}
+	restore_flags(flags);
+}
+
+void enable_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	DBG(KERN_INFO "enable_irq, irq %d\n", irq_nr);
+	save_and_cli(flags);
+	if (irq_nr >= 8) {	// All PCI interrupts are on line 5 or 2
+		DBG(KERN_INFO __FUNCTION__ " pci interrupt %d\n", irq_nr);
+		unmask_irq(9 << 2);
+	} else {
+		DBG(KERN_INFO __FUNCTION__ " interrupt set mask %d\n",
+		    1 << irq_nr);
+		unmask_irq(1 << irq_nr);
+	}
+	restore_flags(flags);
+}
+
+/*
+ * Generic no controller code
+ */
+
+static void no_irq_enable_disable(unsigned int irq)
+{
+}
+static unsigned int no_irq_startup(unsigned int irq)
+{
+	return 0;
+}
+
+#if 0
+static void no_irq_ack(unsigned int irq)
+{
+	printk(KERN_CRIT "Unexpected IRQ trap at vector %u\n", irq);
+}
+#endif
+
+struct hw_interrupt_type no_irq_type = {
+	typename:"none",
+	startup:no_irq_startup,
+	shutdown:no_irq_enable_disable,
+	enable:no_irq_enable_disable,
+	disable:no_irq_enable_disable,
+	ack:NULL,
+	end:no_irq_enable_disable,
+};
+
+//      ack:            no_irq_ack,                re-enable later -- SKJ  
+
+
+/*
+ * Controller mappings for all interrupt sources:
+ */
+irq_desc_t irq_desc[NR_IRQS];
+
+atomic_t irq_err_count;
+
+int get_irq_list(char *buf)
+{
+	int i, len = 0, j;
+	struct irqaction *action;
+
+	len += sprintf(buf + len, "           ");
+	for (j = 0; j < smp_num_cpus; j++)
+		len += sprintf(buf + len, "CPU%d       ", j);
+	*(char *) (buf + len++) = '\n';
+
+	for (i = 0; i < NR_IRQS; i++) {
+		action = irq_desc[i].action;
+		if (!action || !action->handler)
+			continue;
+		len += sprintf(buf + len, "%3d: ", i);
+		len += sprintf(buf + len, "%10u ", kstat_irqs(i));
+		if (irq_desc[i].handler)
+			len +=
+			    sprintf(buf + len, " %s ",
+				    irq_desc[i].handler->typename);
+		else
+			len += sprintf(buf + len, "  None      ");
+		len += sprintf(buf + len, "    %s", action->name);
+		for (action = action->next; action; action = action->next) {
+			len += sprintf(buf + len, ", %s", action->name);
+		}
+		len += sprintf(buf + len, "\n");
+	}
+	len += sprintf(buf + len, "BAD: %10lu\n", atomic_read(&irq_err_count));
+	return len;
+}
+
+asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+{
+	struct irqaction *action;
+	int cpu;
+
+#ifdef IRQ_DEBUG
+	if (irq != TIMER)
+		DBG(KERN_INFO __FUNCTION__ " irq = %d\n", irq);
+	if (irq != TIMER)
+		DBG(KERN_INFO "cause register = %x\n",
+		    read_32bit_cp0_register(CP0_CAUSE));
+	if (irq != TIMER)
+		DBG(KERN_INFO "status register = %x\n",
+		    read_32bit_cp0_register(CP0_STATUS));
+#endif
+
+	cpu = smp_processor_id();
+	irq_enter(cpu, irq);
+	kstat.irqs[cpu][irq]++;
+
+	if (irq_desc[irq].handler->ack) {
+		irq_desc[irq].handler->ack(irq);
+	}
+
+	disable_irq(irq);
+
+	action = irq_desc[irq].action;
+	if (action && action->handler) {
+#ifdef IRQ_DEBUG
+		if (irq != TIMER)
+			DBG(KERN_INFO
+			    "rr: irq %d action %p and handler %p\n", irq,
+			    action, action->handler);
+#endif
+		if (!(action->flags & SA_INTERRUPT))
+			__sti();
+		do {
+			action->handler(irq, action->dev_id, regs);
+			action = action->next;
+		} while (action);
+		__cli();
+		if (irq_desc[irq].handler) {
+			if (irq_desc[irq].handler->end)
+				irq_desc[irq].handler->end(irq);
+			else if (irq_desc[irq].handler->enable)
+				irq_desc[irq].handler->enable(irq);
+		}
+	}
+
+	enable_irq(irq);
+	irq_exit(cpu, irq);
+
+	if (softirq_pending(cpu))
+		do_softirq();
+
+	/* unmasking and bottom half handling is done magically for us. */
+}
+
+int request_irq(unsigned int irq,
+		void (*handler) (int, void *, struct pt_regs *),
+		unsigned long irqflags, const char *devname, void *dev_id)
+{
+	struct irqaction *old, **p, *action;
+	unsigned long flags;
+
+	DBG(KERN_INFO "rr:dev %s irq %d handler %x\n", devname, irq,
+	    handler);
+	if (irq >= NR_IRQS)
+		return -EINVAL;
+
+	action = (struct irqaction *)
+	    kmalloc(sizeof(struct irqaction), GFP_KERNEL);
+	if (!action)
+		return -ENOMEM;
+
+	action->handler = handler;
+	action->flags = irqflags;
+	action->mask = 0;
+	action->name = devname;
+	action->dev_id = dev_id;
+	action->next = NULL;
+
+	save_flags(flags);
+	cli();
+
+	p = &irq_desc[irq].action;
+
+	if ((old = *p) != NULL) {
+		/* Can't share interrupts unless both agree to */
+		if (!(old->flags & action->flags & SA_SHIRQ))
+			return -EBUSY;
+		/* add new interrupt at end of irq queue */
+		do {
+			p = &old->next;
+			old = *p;
+		} while (old);
+	}
+	*p = action;
+
+	restore_flags(flags);
+	if (irq >= 8) {
+		DBG(KERN_INFO "request_irq, max_interrupts %d\n",
+		    max_interrupts);
+		pci_int_irq[max_interrupts++] = irq;	// NOTE:  Add error-handling if > max
+	}
+	enable_irq(irq);
+	return 0;
+}
+
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+	struct irqaction *p, *old = NULL;
+	unsigned long flags;
+	int count, tmp, removed = 0;
+
+	for (p = irq_desc[irq].action; p != NULL; old = p, p = p->next) {
+		/* Found the IRQ, is it the correct dev_id?  */
+		if (dev_id == p->dev_id) {
+			save_flags(flags);
+			cli();
+
+			// remove link from list
+			if (old)
+				old->next = p->next;
+			else
+				irq_desc[irq].action = p->next;
+
+			restore_flags(flags);
+			kfree(p);
+			removed = 1;
+			break;
+		}
+	}
+
+	/*
+	   Remove PCI interrupts from the pci_int_irq list.  Make sure
+	   that some handler was removed before decrementing max_interrupts.
+	 */
+	if ((irq >= 8) && (removed)) {
+		for (count = 0; count < max_interrupts; count++) {
+			if (pci_int_irq[count] == irq) {
+				for (tmp = count; tmp < max_interrupts;
+				     tmp++) {
+					pci_int_irq[tmp] =
+					    pci_int_irq[tmp + 1];
+				}
+			}
+		}
+		max_interrupts--;
+		DBG(KERN_INFO "free_irq, max_interrupts %d\n",
+		    max_interrupts);
+	}
+}
+
+unsigned long probe_irq_on(void)
+{
+	printk(KERN_INFO "probe_irq_on\n");
+	return 0;
+}
+
+int probe_irq_off(unsigned long irqs)
+{
+	printk(KERN_INFO "probe_irq_off\n");
+	return 0;
+}
+
+/********************************************************************
+ *galileo_irq_setup -
+ *
+ *Initializes CPU interrupts
+ *
+ *
+ *Inputs :
+ *
+ *Outpus :
+ *
+ *********************************************************************/
+void galileo_irq_setup(void)
+{
+	extern asmlinkage void galileo_handle_int(void);
+	extern void galileo_irq_init(void);
+
+	DBG(KERN_INFO "rr: galileo_irq_setup entry\n");
+
+	galileo_irq_init();
+
+	/*
+	 * Clear all of the interrupts while we change the able around a bit.
+	 */
+	clear_cp0_status(ST0_IM);
+
+	/* Sets the exception_handler array. */
+	set_except_vector(0, galileo_handle_int);
+
+	cli();
+
+	/*
+	 * Enable timer.  Other interrupts will be enabled as they are
+	 * registered.
+	 */
+	set_cp0_status(IE_IRQ2);
+
+
+#ifdef CONFIG_REMOTE_DEBUG
+	{
+		extern int DEBUG_CHANNEL;
+		serial_init(DEBUG_CHANNEL);
+		serial_set(DEBUG_CHANNEL, 115200);
+		set_debug_traps();
+		breakpoint();	/* you may move this line to whereever you want :-) */
+	}
+#endif
+}
+
+void init_irq_proc(void)
+{
+	/* Nothing, for now.  */
+}
+
+void __init init_IRQ(void)
+{
+	int i;
+
+	DBG(KERN_INFO "rr:init_IRQ\n");
+
+	/*  Let's initialize our IRQ descriptors  */
+	for (i = 0; i < NR_IRQS; i++) {
+		irq_desc[i].status = 0;
+		irq_desc[i].handler = &no_irq_type;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 0;
+		irq_desc[i].lock = SPIN_LOCK_UNLOCKED;
+	}
+
+	galileo_irq_setup();
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/pci_bios.c linux/arch/mips/galileo-boards/ev64120/pci_bios.c
--- linux.orig/arch/mips/galileo-boards/ev64120/pci_bios.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/pci_bios.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,1236 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Galileo Evaluation Boards PCI support.
+ *
+ * The general-purpose functions to read/write and configure the GT64120A's
+ * PCI registers (function names start with pci0 or pci1) are either direct
+ * copies of functions written by Galileo Technology, or are modifications
+ * of their functions to work with Linux 2.4 vs Linux 2.2.  These functions
+ * are Copyright - Galileo Technology.
+ *
+ * Other functions are derived from other MIPS PCI implementations, or were
+ * written by RidgeRun, Inc,  Copyright (C) 2000 RidgeRun, Inc.
+ *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <asm/pci.h>
+#include <asm/io.h>
+#include <asm/galileo-boards/ev64120.h>
+#include <asm/gt64120.h>
+
+#include <linux/init.h>
+
+#undef PCI_DEBUG
+
+#ifdef PCI_DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#ifdef CONFIG_PCI
+
+#define SELF 0
+
+/*
+ * These functions and structures provide the BIOS scan and mapping of the PCI
+ * devices.
+ */
+
+#define MAX_PCI_DEVS 10
+
+struct pci_device {
+	u32 slot;
+	u32 BARtype[6];
+	u32 BARsize[6];
+};
+
+static void __init scan_and_initialize_pci(void);
+static u32 __init scan_pci_bus(struct pci_device *pci_devices);
+static void __init allocate_pci_space(struct pci_device *pci_devices);
+
+static void __init galileo_pcibios_fixup_bus(struct pci_bus *bus);
+
+/*
+ * The functions that actually read and write to the controller.
+ * Copied from or modified from Galileo Technology code.
+ */
+static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device);
+static void pci0WriteConfigReg(unsigned int offset,
+			       struct pci_dev *device, unsigned int data);
+static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device);
+static void pci1WriteConfigReg(unsigned int offset,
+			       struct pci_dev *device, unsigned int data);
+
+static void pci0MapIOspace(unsigned int pci0IoBase,
+			   unsigned int pci0IoLength);
+static void pci1MapIOspace(unsigned int pci1IoBase,
+			   unsigned int pci1IoLength);
+static void pci0MapMemory0space(unsigned int pci0Mem0Base,
+				unsigned int pci0Mem0Length);
+static void pci1MapMemory0space(unsigned int pci1Mem0Base,
+				unsigned int pci1Mem0Length);
+static void pci0MapMemory1space(unsigned int pci0Mem1Base,
+				unsigned int pci0Mem1Length);
+static void pci1MapMemory1space(unsigned int pci1Mem1Base,
+				unsigned int pci1Mem1Length);
+static unsigned int pci0GetIOspaceBase(void);
+static unsigned int pci0GetIOspaceSize(void);
+static unsigned int pci0GetMemory0Base(void);
+static unsigned int pci0GetMemory0Size(void);
+static unsigned int pci0GetMemory1Base(void);
+static unsigned int pci0GetMemory1Size(void);
+static unsigned int pci1GetIOspaceBase(void);
+static unsigned int pci1GetIOspaceSize(void);
+static unsigned int pci1GetMemory0Base(void);
+static unsigned int pci1GetMemory0Size(void);
+static unsigned int pci1GetMemory1Base(void);
+static unsigned int pci1GetMemory1Size(void);
+
+
+/*  Functions to implement "pci ops"  */
+static int galileo_pcibios_read_config_word(struct pci_dev *dev,
+					    int offset, u16 * val);
+static int galileo_pcibios_read_config_byte(struct pci_dev *dev,
+					    int offset, u8 * val);
+static int galileo_pcibios_read_config_dword(struct pci_dev *dev,
+					     int offset, u32 * val);
+static int galileo_pcibios_write_config_byte(struct pci_dev *dev,
+					     int offset, u8 val);
+static int galileo_pcibios_write_config_word(struct pci_dev *dev,
+					     int offset, u16 val);
+static int galileo_pcibios_write_config_dword(struct pci_dev *dev,
+					      int offset, u32 val);
+static void galileo_pcibios_set_master(struct pci_dev *dev);
+
+/*
+ * General-purpose PCI functions.
+ */
+
+/*
+ * pci0MapIOspace - Maps PCI0 IO space for the master.
+ * Inputs: base and length of pci0Io
+ */
+static void pci0MapIOspace(unsigned int pci0IoBase, unsigned int pci0IoLength)
+{
+	unsigned int pci0IoTop =
+	    (unsigned int) (pci0IoBase + pci0IoLength);
+
+	if (pci0IoLength == 0)
+		pci0IoTop++;
+
+	pci0IoBase = (unsigned int) (pci0IoBase >> 21);
+	pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21);
+	GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase);
+	GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop);
+}
+
+/*
+ * pci1MapIOspace - Maps PCI1 IO space for the master.
+ * Inputs: base and length of pci1Io
+ */
+
+static void pci1MapIOspace(unsigned int pci1IoBase,
+			   unsigned int pci1IoLength)
+{
+	unsigned int pci1IoTop =
+	    (unsigned int) (pci1IoBase + pci1IoLength);
+
+	if (pci1IoLength == 0)
+		pci1IoTop++;
+
+	pci1IoBase = (unsigned int) (pci1IoBase >> 21);
+	pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21);
+	GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase);
+	GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop);
+}
+
+/*
+ * pci0MapMemory0space - Maps PCI0 memory0 space for the master.
+ * Inputs: base and length of pci0Mem0
+ */
+
+static void pci0MapMemory0space(unsigned int pci0Mem0Base,
+				unsigned int pci0Mem0Length)
+{
+	unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length;
+
+	if (pci0Mem0Length == 0)
+		pci0Mem0Top++;
+
+	pci0Mem0Base = pci0Mem0Base >> 21;
+	pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21;
+	GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base);
+	GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top);
+}
+
+/*
+ * pci1MapMemory0space - Maps PCI1 memory0 space for the master.
+ * Inputs: base and length of pci1Mem0
+ */
+
+static void pci1MapMemory0space(unsigned int pci1Mem0Base,
+				unsigned int pci1Mem0Length)
+{
+	unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length;
+
+	if (pci1Mem0Length == 0)
+		pci1Mem0Top++;
+
+	pci1Mem0Base = pci1Mem0Base >> 21;
+	pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21;
+	GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base);
+	GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top);
+}
+
+/*
+ * pci0MapMemory1space - Maps PCI0 memory1 space for the master.
+ * Inputs: base and length of pci0Mem1
+ */
+
+static void pci0MapMemory1space(unsigned int pci0Mem1Base,
+				unsigned int pci0Mem1Length)
+{
+	unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length;
+
+	if (pci0Mem1Length == 0)
+		pci0Mem1Top++;
+
+	pci0Mem1Base = pci0Mem1Base >> 21;
+	pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21;
+	GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base);
+	GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top);
+
+}
+
+/*
+ * pci1MapMemory1space - Maps PCI1 memory1 space for the master.
+ * Inputs: base and length of pci1Mem1
+ */
+
+static void pci1MapMemory1space(unsigned int pci1Mem1Base,
+				unsigned int pci1Mem1Length)
+{
+	unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length;
+
+	if (pci1Mem1Length == 0)
+		pci1Mem1Top++;
+
+	pci1Mem1Base = pci1Mem1Base >> 21;
+	pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21;
+	GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base);
+	GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top);
+}
+
+/*
+ * pci0GetIOspaceBase - Return PCI0 IO Base Address.
+ * Inputs: N/A
+ * Returns: PCI0 IO Base Address.
+ */
+
+static unsigned int pci0GetIOspaceBase(void)
+{
+	unsigned int base;
+	GT_READ(GT_PCI0IOLD_OFS, &base);
+	base = base << 21;
+	return base;
+}
+
+/*
+ * pci0GetIOspaceSize - Return PCI0 IO Bar Size.
+ * Inputs: N/A
+ * Returns: PCI0 IO Bar Size.
+ */
+static unsigned int pci0GetIOspaceSize(void)
+{
+	unsigned int top, base, size;
+	GT_READ(GT_PCI0IOLD_OFS, &base);
+	base = base << 21;
+	GT_READ(GT_PCI0IOHD_OFS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/*
+ * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 0 Base Address.
+ */
+static unsigned int pci0GetMemory0Base(void)
+{
+	unsigned int base;
+	GT_READ(GT_PCI0M0LD_OFS, &base);
+	base = base << 21;
+	return base;
+}
+
+/*
+ * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 0 Bar Size.
+ */
+static unsigned int pci0GetMemory0Size(void)
+{
+	unsigned int top, base, size;
+	GT_READ(GT_PCI0M0LD_OFS, &base);
+	base = base << 21;
+	GT_READ(GT_PCI0M0HD_OFS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/*
+ * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 1 Base Address.
+ */
+static unsigned int pci0GetMemory1Base(void)
+{
+	unsigned int base;
+	GT_READ(GT_PCI0M1LD_OFS, &base);
+	base = base << 21;
+	return base;
+}
+
+/*
+ * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 1 Bar Size.
+ */
+
+static unsigned int pci0GetMemory1Size(void)
+{
+	unsigned int top, base, size;
+	GT_READ(GT_PCI0M1LD_OFS, &base);
+	base = base << 21;
+	GT_READ(GT_PCI0M1HD_OFS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/*
+ * pci1GetIOspaceBase - Return PCI1 IO Base Address.
+ * Inputs: N/A
+ * Returns: PCI1 IO Base Address.
+ */
+
+static unsigned int pci1GetIOspaceBase(void)
+{
+	unsigned int base;
+	GT_READ(GT_PCI1IOLD_OFS, &base);
+	base = base << 21;
+	return base;
+}
+
+/*
+ * pci1GetIOspaceSize - Return PCI1 IO Bar Size.
+ * Inputs: N/A
+ * Returns: PCI1 IO Bar Size.
+ */
+
+static unsigned int pci1GetIOspaceSize(void)
+{
+	unsigned int top, base, size;
+	GT_READ(GT_PCI1IOLD_OFS, &base);
+	base = base << 21;
+	GT_READ(GT_PCI1IOHD_OFS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/*
+ * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 0 Base Address.
+ */
+
+static unsigned int pci1GetMemory0Base(void)
+{
+	unsigned int base;
+	GT_READ(GT_PCI1M0LD_OFS, &base);
+	base = base << 21;
+	return base;
+}
+
+/*
+ * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 0 Bar Size.
+ */
+
+static unsigned int pci1GetMemory0Size(void)
+{
+	unsigned int top, base, size;
+	GT_READ(GT_PCI1M1LD_OFS, &base);
+	base = base << 21;
+	GT_READ(GT_PCI1M1HD_OFS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+/*
+ * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 1 Base Address.
+ */
+
+static unsigned int pci1GetMemory1Base(void)
+{
+	unsigned int base;
+	GT_READ(GT_PCI1M1LD_OFS, &base);
+	base = base << 21;
+	return base;
+}
+
+/*
+ * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 1 Bar Size.
+ */
+
+static unsigned int pci1GetMemory1Size(void)
+{
+	unsigned int top, base, size;
+	GT_READ(GT_PCI1M1LD_OFS, &base);
+	base = base << 21;
+	GT_READ(GT_PCI1M1HD_OFS, &top);
+	top = (top << 21);
+	size = ((top - base) & 0xfffffff);
+	size = size | 0x1fffff;
+	return (size + 1);
+}
+
+
+
+/*
+ * pci_range_ck -
+ *
+ * Check if the pci device that are trying to access does really exists
+ * on the evaluation board.  
+ *
+ * Inputs :
+ * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
+ * dev - number of device on the specific pci bus
+ *
+ * Outpus :
+ * 0 - if OK , 1 - if failure
+ */
+static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
+{
+	//DBG(KERN_INFO "p_r_c %d %d\n",bus,dev);
+	if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8))
+		return 0;	// Bus/Device Number OK
+	return -1;		// Bus/Device Number not OK  
+}
+
+/*
+ * pciXReadConfigReg  - Read from a PCI configuration register
+ *                    - Make sure the GT is configured as a master before 
+ *                      reading from another device on the PCI.
+ *                   - The function takes care of Big/Little endian conversion.
+ * INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+ *                        spec)
+ *           pciDevNum: The device number needs to be addressed.                
+ * RETURNS: data , if the data == 0xffffffff check the master abort bit in the 
+ *                 cause register to make sure the data is valid
+ *
+ *  Configuration Address 0xCF8:
+ *
+ *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+ *  |congif|Reserved|  Bus |Device|Function|Register|00|
+ *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+ *
+ */
+static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
+{
+	unsigned int DataForRegCf8;
+	unsigned int data;
+
+	DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
+			 (PCI_FUNC(device->devfn) << 8) |
+			 (offset & ~0x3)) | 0x80000000;
+	GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
+
+	/*  The casual observer might wonder why the READ is duplicated here,
+	   rather than immediately following the WRITE, and just have the
+	   swap in the "if".  That's because there is a latency problem
+	   with trying to read immediately after setting up the address
+	   register.  The "if" check gives enough time for the address
+	   to stabilize, so the READ can work.
+	 */
+	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
+		GT_READ(GT_PCI0_CFGDATA_OFS, &data);
+		return data;
+	} else {	/* The PCI is working in LE Mode so swap the Data. */
+		GT_READ(GT_PCI0_CFGDATA_OFS, &data);
+		return cpu_to_le32(data);
+	}
+}
+
+static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device)
+{
+	unsigned int DataForRegCf8;
+	unsigned int data;
+
+	DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
+			 (PCI_FUNC(device->devfn) << 8) |
+			 (offset & ~0x3)) | 0x80000000;
+	/*  The casual observer might wonder why the READ is duplicated here,
+	   rather than immediately following the WRITE, and just have the
+	   swap in the "if".  That's because there is a latency problem
+	   with trying to read immediately after setting up the address
+	   register.  The "if" check gives enough time for the address
+	   to stabilize, so the READ can work.
+	 */
+	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
+		/* when configurating our own PCI 1 L-unit the access is through  
+		   the PCI 0 interface with reg number = reg number + 0x80 */
+		DataForRegCf8 |= 0x80;
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
+	} else {		/* The PCI is working in LE Mode so swap the Data. */
+		GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8);
+	}
+	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
+		GT_READ(GT_PCI0_CFGDATA_OFS, &data);
+		return data;
+	} else {
+		GT_READ(GT_PCI1_CFGDATA_OFS, &data);
+		return cpu_to_le32(data);
+	}
+}
+
+
+
+/*
+ * pciXWriteConfigReg - Write to a PCI configuration register
+ *                    - Make sure the GT is configured as a master before 
+ *                      writingto another device on the PCI.
+ *                    - The function takes care of Big/Little endian conversion.
+ * Inputs:   unsigned int regOffset: The register offset as it apears in the
+ *           GT spec 
+ *                   (or any other PCI device spec)
+ *           pciDevNum: The device number needs to be addressed.                
+ *
+ *  Configuration Address 0xCF8:
+ *
+ *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+ *  |congif|Reserved|  Bus |Device|Function|Register|00|
+ *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+ *
+ */
+static void pci0WriteConfigReg(unsigned int offset,
+			       struct pci_dev *device, unsigned int data)
+{
+	unsigned int DataForRegCf8;
+
+	DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
+			 (PCI_FUNC(device->devfn) << 8) |
+			 (offset & ~0x3)) | 0x80000000;
+	GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
+	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
+	} else {		/* configuration Transaction over the pci. */
+		/* The PCI is working in LE Mode so swap the Data. */
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, le32_to_cpu(data));
+	}
+}
+
+static void pci1WriteConfigReg(unsigned int offset,
+			       struct pci_dev *device, unsigned int data)
+{
+	unsigned int DataForRegCf8;
+
+	DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
+			 (PCI_FUNC(device->devfn) << 8) |
+			 (offset & ~0x3)) | 0x80000000;
+	/*  There is a latency problem
+	   with trying to read immediately after setting up the address
+	   register.  The "if" check gives enough time for the address
+	   to stabilize, so the WRITE can work.
+	 */
+	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
+		/* when configurating our own PCI 1 L-unit the access is through  
+		   the PCI 0 interface with reg number = reg number + 0x80 */
+		DataForRegCf8 |= 0x80;
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
+	} else {		/* configuration Transaction over the pci. */
+		/* The PCI is working in LE Mode so swap the Data. */
+		GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8);
+	}
+	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
+	} else {		/* configuration Transaction over the pci. */
+		GT_WRITE(GT_PCI1_CFGADDR_OFS, le32_to_cpu(data));
+	}
+}
+
+
+/*
+ * galileo_pcibios_(read/write)_config_(dword/word/byte) -
+ *
+ * reads/write a dword/word/byte register from the configuration space
+ * of a device.
+ *
+ * Inputs :
+ * bus - bus number
+ * dev - device number
+ * offset - register offset in the configuration space
+ * val - value to be written / read
+ *
+ * Outputs :
+ * PCIBIOS_SUCCESSFUL when operation was succesfull
+ * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
+ * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
+ */
+
+static int galileo_pcibios_read_config_dword(struct pci_dev *device,
+					     int offset, u32 * val)
+{
+	int dev, bus;
+	//DBG(KERN_INFO "rcd entry \n",offset,val);
+	bus = device->bus->number;
+	dev = PCI_SLOT(device->devfn);
+
+	if (pci_range_ck(bus, dev)) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	if (offset & 0x3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (bus == 0)
+		*val = pci0ReadConfigReg(offset, device);
+//  if (bus == 1) *val = pci1ReadConfigReg (offset,device);
+	DBG(KERN_INFO "rr: rcd dev %d offset %x %x\n", dev, offset, *val);
+
+	/*
+	 * This is so that the upper PCI layer will get the correct return
+	 * value if we're not attached to anything.
+	 */
+	if ((offset == 0) && (*val == 0xffffffff)) {
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int galileo_pcibios_read_config_word(struct pci_dev *device,
+					    int offset, u16 * val)
+{
+	int dev, bus;
+
+	bus = device->bus->number;
+	dev = PCI_SLOT(device->devfn);
+
+	if (pci_range_ck(bus, dev)) {
+		*val = 0xffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	if (offset & 0x1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	if (bus == 0)
+		*val = (unsigned short) (pci0ReadConfigReg(offset, device) >>
+				         ((offset & ~0x3) * 8));
+//  if (bus == 1) *val = (unsigned short) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8));
+
+	DBG(KERN_INFO "rr: rcw dev %d offset %x %x\n", dev, offset, *val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int galileo_pcibios_read_config_byte(struct pci_dev *device,
+					    int offset, u8 * val)
+{
+	int dev, bus;
+
+	bus = device->bus->number;
+	dev = PCI_SLOT(device->devfn);
+
+	if (pci_range_ck(bus, dev)) {
+		*val = 0xff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	if (bus == 0)
+		*val =
+		    (unsigned char) (pci0ReadConfigReg(offset, device) >>
+				     ((offset & ~0x3) * 8));
+//  if (bus == 1) *val = (unsigned char) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8));
+
+	DBG(KERN_INFO "rr: rcb dev %d offset %x %x\n", dev, offset, *val);
+
+	/*  This is so that the upper PCI layer will get the correct return value if
+	   we're not attached to anything.  */
+	if ((offset == 0xe) && (*val == 0xff)) {
+		u32 MasterAbort;
+		GT_READ(GT_INTRCAUSE_OFS, &MasterAbort);
+		if (MasterAbort & 0x40000) {
+			DBG(KERN_INFO "PCI Master Abort, ICR %x\n",
+			    MasterAbort);
+			GT_WRITE(GT_INTRCAUSE_OFS,
+				 (MasterAbort & 0xfffbffff));
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int galileo_pcibios_write_config_dword(struct pci_dev *device,
+					      int offset, u32 val)
+{
+	int dev, bus;
+
+	bus = device->bus->number;
+	dev = PCI_SLOT(device->devfn);
+
+	if (pci_range_ck(bus, dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	if (offset & 0x3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (bus == 0)
+		pci0WriteConfigReg(offset, device, val);
+//  if (bus == 1) pci1WriteConfigReg (offset,device,val);
+
+	DBG(KERN_INFO "rr: wcd dev %d, offset %x, val %x\n", dev, offset,
+	    val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int galileo_pcibios_write_config_word(struct pci_dev *device,
+					     int offset, u16 val)
+{
+	int dev, bus;
+	unsigned long tmp;
+
+	bus = device->bus->number;
+	dev = PCI_SLOT(device->devfn);
+
+	if (pci_range_ck(bus, dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	if (offset & 0x1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (bus == 0)
+		tmp = pci0ReadConfigReg(offset, device);
+//  if (bus == 1) tmp = pci1ReadConfigReg (offset,device);
+
+	if ((offset % 4) == 0)
+		tmp = (tmp & 0xffff0000) | (val & 0xffff);
+	if ((offset % 4) == 2)
+		tmp = (tmp & 0x0000ffff) | ((val & 0xffff) << 16);
+
+	if (bus == 0)
+		pci0WriteConfigReg(offset, device, tmp);
+//  if (bus == 1) pci1WriteConfigReg (offset,device,tmp);
+	DBG(KERN_INFO "rr: wcw dev %d, offset %x, val %x\n", dev, offset,
+	    val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int galileo_pcibios_write_config_byte(struct pci_dev *device,
+					     int offset, u8 val)
+{
+	int dev, bus;
+	unsigned long tmp;
+
+	bus = device->bus->number;
+	dev = PCI_SLOT(device->devfn);
+
+	if (pci_range_ck(bus, dev))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	if (bus == 0)
+		tmp = pci0ReadConfigReg(offset, device);
+//  if (bus == 1) tmp = pci1ReadConfigReg (offset,device);
+
+	if ((offset % 4) == 0)
+		tmp = (tmp & 0xffffff00) | (val & 0xff);
+	if ((offset % 4) == 1)
+		tmp = (tmp & 0xffff00ff) | ((val & 0xff) << 8);
+	if ((offset % 4) == 2)
+		tmp = (tmp & 0xff00ffff) | ((val & 0xff) << 16);
+	if ((offset % 4) == 3)
+		tmp = (tmp & 0x00ffffff) | ((val & 0xff) << 24);
+
+	if (bus == 0)
+		pci0WriteConfigReg(offset, device, tmp);
+//  if (bus == 1) pci1WriteConfigReg (offset,device,tmp);
+	DBG(KERN_INFO "rr: wcb dev %d, offset %x, val %x\n", dev, offset,
+	    val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static void galileo_pcibios_set_master(struct pci_dev *dev)
+{
+	u16 cmd;
+
+	DBG(KERN_INFO "rr: galileo_pcibios_set_master\n");
+
+	galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER;
+	galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
+	DBG("PCI: Enabling device %s (%04x)\n", dev->slot_name, cmd);
+}
+
+/*  Externally-expected functions.  Do not change function names  */
+
+int pcibios_enable_resources(struct pci_dev *dev)
+{
+	u16 cmd, old_cmd;
+	u16 tmp;
+	u8 tmp1;
+	int idx;
+	struct resource *r;
+
+	DBG(KERN_INFO "rr: pcibios_enable_resources\n");
+
+	galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd);
+	old_cmd = cmd;
+	for (idx = 0; idx < 6; idx++) {
+		r = &dev->resource[idx];
+		DBG(KERN_INFO
+		    "rr: BAR %d, start %lx, end %lx, flags %lx\n", idx,
+		    r->start, r->end, r->flags);
+		if (!r->start && r->end) {
+			printk(KERN_ERR
+			       "PCI: Device %s not available because of resource collisions\n",
+			       dev->slot_name);
+			return -EINVAL;
+		}
+		if (r->flags & IORESOURCE_IO)
+			cmd |= PCI_COMMAND_IO;
+		if (r->flags & IORESOURCE_MEM)
+			cmd |= PCI_COMMAND_MEMORY;
+	}
+	if (cmd != old_cmd) {
+		DBG(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
+		    dev->slot_name, old_cmd, cmd);
+		galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd);
+	}
+
+	/*
+	   Let's fix up the latency timer and cache line size here.  Cache line size =
+	   32 bytes / sizeof dword (4) = 8.
+	   Latency timer must be > 8.  32 is random but appears to work.
+	 */
+	galileo_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
+	if (tmp1 != 8) {
+		DBG(KERN_INFO
+		    "rr: PCI setting cache line size to 8 from %d\n",
+		    tmp1);
+		galileo_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
+						  8);
+	}
+	galileo_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1);
+	if (tmp1 < 32) {
+		DBG(KERN_INFO
+		    "rr: PCI setting latency timer to 32 from %d\n", tmp1);
+		galileo_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER,
+						  32);
+	}
+
+	return 0;
+}
+
+int pcibios_enable_device(struct pci_dev *dev)
+{
+	DBG(KERN_INFO "rr: pcibios_enable_device\n");
+	return pcibios_enable_resources(dev);
+}
+
+void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
+			     struct resource *res, int resource)
+{
+	u32 new, check;
+	int reg;
+
+	DBG(KERN_INFO "rr: pcibios_update_resource\n");
+	return;
+
+	new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
+	if (resource < 6) {
+		reg = PCI_BASE_ADDRESS_0 + 4 * resource;
+	} else if (resource == PCI_ROM_RESOURCE) {
+		res->flags |= PCI_ROM_ADDRESS_ENABLE;
+		reg = dev->rom_base_reg;
+	} else {
+		/* Somebody might have asked allocation of a non-standard resource */
+		return;
+	}
+
+	pci_write_config_dword(dev, reg, new);
+	pci_read_config_dword(dev, reg, &check);
+	if ((new ^ check) &
+	    ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
+	     PCI_BASE_ADDRESS_MEM_MASK)) {
+		DBG(KERN_ERR "PCI: Error while updating region "
+		    "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
+		    new, check);
+	}
+}
+
+void pcibios_align_resource(void *data, struct resource *res,
+			    unsigned long size)
+{
+	struct pci_dev *dev = data;
+
+	DBG(KERN_INFO "pcibios_align_resource\n");
+
+	if (res->flags & IORESOURCE_IO) {
+		unsigned long start = res->start;
+
+		/* We need to avoid collisions with `mirrored' VGA ports
+		   and other strange ISA hardware, so we always want the
+		   addresses kilobyte aligned.  */
+		if (size > 0x100) {
+			DBG(KERN_ERR "PCI: I/O Region %s/%d too large"
+			    " (%ld bytes)\n", dev->slot_name,
+			    dev->resource - res, size);
+		}
+
+		start = (start + 1024 - 1) & ~(1024 - 1);
+		res->start = start;
+	}
+}
+
+/*
+ * structure galileo_pci_ops
+ *
+ * This structure holds the pointers for the PCI configuration space
+ * access, and the fixup for the interrupts.
+ * This structure is registered to the operating system in boot time
+ */
+struct pci_ops galileo_pci_ops = {
+	galileo_pcibios_read_config_byte,
+	galileo_pcibios_read_config_word,
+	galileo_pcibios_read_config_dword,
+	galileo_pcibios_write_config_byte,
+	galileo_pcibios_write_config_word,
+	galileo_pcibios_write_config_dword
+};
+
+/*
+ * galileo_pcibios_fixup_bus -
+ *
+ * After detecting all agents over the PCI , this function is called
+ * in order to give an interrupt number for each PCI device starting
+ * from IRQ 20. It does also enables master for each device.
+ *
+ * Inputs :
+ * mem_start , mem_end are not relevant in MIPS architecture.
+ *
+ * Outpus :
+ * return always mem_start
+ */
+static void __init galileo_pcibios_fixup_bus(struct pci_bus *bus)
+{
+	unsigned int Current_IRQ = 20;
+	struct pci_bus *current_bus = bus;
+	struct pci_dev *devices;
+	struct list_head *devices_link;
+
+	list_for_each(devices_link, &(current_bus->devices)) {
+		devices = pci_dev_b(devices_link);
+		if (devices != NULL) {
+			devices->irq = Current_IRQ++;
+
+			/* Assign an interrupt number for the device */
+			galileo_pcibios_write_config_byte(devices,
+							  PCI_INTERRUPT_LINE,
+							  Current_IRQ);
+			galileo_pcibios_set_master(devices);
+
+		}
+	}
+
+}
+
+struct pci_fixup pcibios_fixups[] = {
+//    { PCI_FIXUP_HEADER, 0x4620, 0x11ab, galileo_pcibios_fixup },
+	{0}
+};
+
+void __init pcibios_fixup_bus(struct pci_bus *c)
+{
+	DBG(KERN_INFO "rr: pcibios_fixup_bus\n");
+	galileo_pcibios_fixup_bus(c);
+}
+
+/*
+ * This code was derived from Galileo Technology's example
+ * and significantly reworked.
+ *
+ * This is very simple.  It does not scan multiple function devices.  It does
+ * not scan behind bridges.  Those would be simple to implement, but we don't
+ * currently need this.
+ */
+static void __init scan_and_initialize_pci(void)
+{
+	struct pci_device pci_devices[MAX_PCI_DEVS];
+
+	if (scan_pci_bus(pci_devices)) {
+		allocate_pci_space(pci_devices);
+	}
+}
+
+/*
+ * This is your basic PCI scan.  It goes through each slot and checks to
+ * see if there's something that responds.  If so, then get the size and
+ * type of each of the responding BARs.  Save them for later.
+ */
+
+static u32 __init scan_pci_bus(struct pci_device *pci_devices)
+{
+	u32 arrayCounter = 0;
+	u32 memType;
+	u32 memSize;
+	u32 pci_slot, bar;
+	u32 id;
+	u32 c18RegValue;
+	struct pci_dev device;
+
+	DBG(KERN_INFO "rr: scan_pci_bus\n");
+
+	/*
+	   According to PCI REV 2.1 MAX agents on the bus are 21.
+	   We don't bother scanning ourselves (slot 0).
+	 */
+	for (pci_slot = 1; pci_slot < 22; pci_slot++) {
+
+		device.devfn = PCI_DEVFN(pci_slot, 0);
+		id = pci0ReadConfigReg(PCI_VENDOR_ID, &device);
+
+		/*  Check for a PCI Master Abort (nothing responds in the slot) */
+		GT_READ(GT_INTRCAUSE_OFS, &c18RegValue);
+		/* Clearing bit 18 of in the Cause Register 0xc18 by writting 0. */
+		GT_WRITE(GT_INTRCAUSE_OFS, (c18RegValue & 0xfffbffff));
+		if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) {
+			DBG(KERN_INFO "rr: found device %x, slot %d\n", id,
+			    pci_slot);
+			pci_devices[arrayCounter].slot = pci_slot;
+			for (bar = 0; bar < 6; bar++) {
+				memType =
+				    pci0ReadConfigReg(PCI_BASE_ADDRESS_0 +
+						      (bar * 4), &device);
+				pci_devices[arrayCounter].BARtype[bar] =
+				    memType & 1;
+				pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
+						   (bar * 4), &device,
+						   0xffffffff);
+				memSize =
+				    pci0ReadConfigReg(PCI_BASE_ADDRESS_0 +
+						      (bar * 4), &device);
+				if (memType & 1) {	/*  IO space  */
+					pci_devices[arrayCounter].
+					    BARsize[bar] =
+					    ~(memSize & 0xfffffffc) + 1;
+				} else {	/*  memory space */
+					pci_devices[arrayCounter].
+					    BARsize[bar] =
+					    ~(memSize & 0xfffffff0) + 1;
+				}
+				DBG(KERN_INFO
+				    "rr: BAR %d, type %d, size %x\n", bar,
+				    (memType & 1),
+				    pci_devices[arrayCounter].
+				    BARsize[bar]);
+			}	/*  BAR counter  */
+
+			arrayCounter++;
+		}
+		/*  found a device  */
+	}			/*  slot counter  */
+
+	DBG(KERN_INFO "rr: found %d devices\n", arrayCounter);
+	if (arrayCounter < MAX_PCI_DEVS) {
+		pci_devices[arrayCounter].slot = -1;
+	}
+	return (arrayCounter);
+}
+
+#define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
+#define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
+
+/*
+ * This function goes through the list of devices and allocates the BARs in
+ * either IO or MEM space.  It does it in order of size, which will limit the
+ * amount of fragmentation we have in the IO and MEM spaces.
+ */
+
+static void __init allocate_pci_space(struct pci_device *pci_devices)
+{
+	u32 count, maxcount, bar;
+	u32 maxSize, maxDevice, maxBAR;
+	u32 alignto;
+	u32 base;
+	u32 pci0_mem_base = pci0GetMemory0Base();
+	u32 pci0_io_base = pci0GetIOspaceBase();
+	struct pci_dev device;
+
+	DBG(KERN_INFO "rr: allocate_pci_space\n");
+
+	DBG(KERN_INFO "pci0_io_base %x\n", pci0_io_base);
+	DBG(KERN_INFO "pci0_mem_base %x\n", pci0_mem_base);
+
+	/*  How many PCI devices do we have?  */
+	maxcount = MAX_PCI_DEVS;
+	for (count = 0; count < MAX_PCI_DEVS; count++) {
+		if (pci_devices[count].slot == -1) {
+			maxcount = count;
+			break;
+		}
+	}
+
+//    DBG(KERN_INFO "Found %d devices\n", maxcount);
+
+	do {
+		/*  Find the largest size BAR we need to allocate  */
+		maxSize = 0;
+		for (count = 0; count < maxcount; count++) {
+			for (bar = 0; bar < 6; bar++) {
+				if (pci_devices[count].BARsize[bar] >
+				    maxSize) {
+					maxSize =
+					    pci_devices[count].
+					    BARsize[bar];
+					maxDevice = count;
+					maxBAR = bar;
+				}
+			}
+		}
+
+		/*
+		   We've found the largest BAR.  Allocate it into IO or
+		   mem space.  We don't idiot check the bases to make
+		   sure they haven't overflowed the current size for that aperture.
+
+		   Don't bother to enable the device's IO or MEM space here.  That will
+		   be done in pci_enable_resources if the device is activated by a driver.
+		 */
+		if (maxSize) {
+			device.devfn =
+			    PCI_DEVFN(pci_devices[maxDevice].slot, 0);
+			if (pci_devices[maxDevice].BARtype[maxBAR] == 1) {
+				alignto = MAX(0x1000, maxSize);
+				base = ALIGN(pci0_io_base, alignto);
+				pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
+						   (maxBAR * 4), &device,
+						   base | 0x1);
+				pci0_io_base = base + alignto;
+				DBG(KERN_INFO
+				    "Device %d BAR %d address %x\n",
+				    pci_devices[maxDevice].slot, maxBAR,
+				    base);
+				DBG(KERN_INFO "New IO base %x\n",
+				    pci0_io_base);
+			} else {
+				alignto = MAX(0x1000, maxSize);
+				base = ALIGN(pci0_mem_base, alignto);
+				pci0WriteConfigReg(PCI_BASE_ADDRESS_0 +
+						   (maxBAR * 4), &device,
+						   base);
+				pci0_mem_base = base + alignto;
+				DBG(KERN_INFO
+				    "Device %d BAR %d address %x\n",
+				    pci_devices[maxDevice].slot, maxBAR,
+				    base);
+				DBG(KERN_INFO "New mem base %x\n",
+				    pci0_mem_base);
+			}
+			/*
+			   This entry is finished.  Remove it from the list we'll scan.
+			 */
+			pci_devices[maxDevice].BARsize[maxBAR] = 0;
+		}
+	} while (maxSize);
+}
+
+unsigned __init int pcibios_assign_all_busses(void)
+{
+	return 1;
+}
+
+void __init pcibios_init(void)
+{
+
+	u32 tmp;
+	struct pci_dev controller;
+
+	controller.devfn = SELF;
+
+	DBG(KERN_INFO "rr: pcibios_init\n");
+	GT_READ(GT_PCI0_CMD_OFS, &tmp);
+	DBG(KERN_INFO "rr: PCI0 command - %x\n", tmp);
+	GT_READ(GT_PCI0_BARE_OFS, &tmp);
+	DBG(KERN_INFO "rr: BAR0 - %x\n", tmp);
+
+	/*
+	 * You have to enable bus mastering to configure any other
+	 * card on the bus.
+	 */
+	tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
+	DBG(KERN_INFO "rr: command/status - %x\n", tmp);
+	tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
+	DBG(KERN_INFO "rr: new command/status - %x\n", tmp);
+	pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
+
+	/*  This scans the PCI bus and sets up initial values.  */
+	scan_and_initialize_pci();
+
+	/*
+	 * Reset PCI I/O and PCI MEM values to ones supported by EVM.
+	 */
+	ioport_resource.start = 0x10000000;
+	ioport_resource.end = 0x11ffffff;	/*  32 MB */
+	iomem_resource.start = 0x12000000;
+	iomem_resource.end = 0x13ffffff;	/* 32 MB */
+
+	pci_scan_bus(0, &galileo_pci_ops, NULL);
+
+}
+
+char *pcibios_setup(char *str)
+{
+	printk(KERN_INFO "rr: pcibios_setup\n");
+	/* Nothing to do for now.  */
+
+	return str;
+}
+
+#endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/promcon.c linux/arch/mips/galileo-boards/ev64120/promcon.c
--- linux.orig/arch/mips/galileo-boards/ev64120/promcon.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/promcon.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,58 @@
+/*
+ * Wrap-around code for a console using the
+ * SGI PROM io-routines.
+ *
+ * Copyright (c) 1999 Ulf Carlsson
+ *
+ * Derived from DECstation promcon.c
+ * Copyright (c) 1998 Harald Koerfgen 
+ */
+#include <linux/tty.h>
+#include <linux/major.h>
+#include <linux/ptrace.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/fs.h>
+
+static void prom_console_write(struct console *co, const char *s,
+			       unsigned count)
+{
+	extern int CONSOLE_CHANNEL;	// The default serial port
+	unsigned i;
+
+	for (i = 0; i < count; i++) {
+		if (*s == 10)
+			serial_putc(CONSOLE_CHANNEL, 13);
+		serial_putc(CONSOLE_CHANNEL, *s++);
+	}
+}
+
+int prom_getchar(void)
+{
+	return 0;
+}
+
+static kdev_t prom_console_device(struct console *c)
+{
+	return MKDEV(TTY_MAJOR, 64 + c->index);
+}
+
+static struct console sercons = {
+    name:	"ttyS",
+    write:	prom_console_write,
+    device:	prom_console_device,
+    flags:	CON_PRINTBUFFER,
+    index:	-1,
+};
+
+/*
+ *    Register console.
+ */
+
+void gal_serial_console_init(void)
+{
+	//  serial_init(); 
+	//serial_set(115200); 
+
+	register_console(&sercons);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/reset.c linux/arch/mips/galileo-boards/ev64120/reset.c
--- linux.orig/arch/mips/galileo-boards/ev64120/reset.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/reset.c	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Ralf Baechle
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+
+void galileo_machine_restart(char *command)
+{
+	*(volatile char *) 0xbc000000 = 0x0f;
+	/*
+	 * Ouch, we're still alive ... This time we take the silver bullet ...
+	 * ... and find that we leave the hardware in a state in which the
+	 * kernel in the flush locks up somewhen during of after the PCI
+	 * detection stuff.
+	 */
+	set_cp0_status(ST0_BEV | ST0_ERL);
+	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_32bit_cp0_register(CP0_WIRED, 0);
+	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+
+void galileo_machine_halt(void)
+{
+	printk(KERN_NOTICE "You can safely turn off the power\n");
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+
+}
+
+void galileo_machine_power_off(void)
+{
+	galileo_machine_halt();
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/serialGT.c linux/arch/mips/galileo-boards/ev64120/serialGT.c
--- linux.orig/arch/mips/galileo-boards/ev64120/serialGT.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/serialGT.c	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,212 @@
+/*
+ * serialGT.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ *  Low Level Serial Port control for use
+ *  with the Galileo EVB64120A MIPS eval board and 
+ *  its on board two channel 16552 Uart.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+// Note:
+//   Serial CHANNELS - 0 is the bottom connector of evb64120A.
+//                       (The one that maps to the "B" channel of the
+//                       board's uart)
+//                     1 is the top connector of evb64120A.
+//                       (The one that maps to the "A" channel of the
+//                       board's uart)
+int DEBUG_CHANNEL = 0;		// See Note Above
+int CONSOLE_CHANNEL = 1;	// See Note Above
+
+#define DUART 0xBD000000	/* Base address of Uart. */
+#define CHANNELOFFSET 0x20	/* DUART+CHANNELOFFSET gets you to the ChanA
+				   register set of the 16552 Uart device.
+				   DUART+0 gets you to the ChanB register set.
+				 */
+#define DUART_DELTA 0x4
+#define FIFO_ENABLE 0x07
+#define INT_ENABLE  0x04	/* default interrupt mask */
+
+#define RBR 0x00
+#define THR 0x00
+#define DLL 0x00
+#define IER 0x01
+#define DLM 0x01
+#define IIR 0x02
+#define FCR 0x02
+#define LCR 0x03
+#define MCR 0x04
+#define LSR 0x05
+#define MSR 0x06
+#define SCR 0x07
+
+#define LCR_DLAB 0x80
+#define XTAL 1843200
+#define LSR_THRE 0x20
+#define LSR_BI   0x10
+#define LSR_DR   0x01
+#define MCR_LOOP 0x10
+#define ACCESS_DELAY 0x10000
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+int inreg(int channel, int reg)
+{
+	int val;
+	val =
+	    *((volatile unsigned char *) DUART +
+	      (channel * CHANNELOFFSET) + (reg * DUART_DELTA));
+	return val;
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+void outreg(int channel, int reg, unsigned char val)
+{
+	*((volatile unsigned char *) DUART + (channel * CHANNELOFFSET)
+	  + (reg * DUART_DELTA)) = val;
+}
+
+/******************************
+ Routine:
+ Description:
+   Initialize the device driver.
+ ******************************/
+void serial_init(int channel)
+{
+	/*
+	 * Configure active port, (CHANNELOFFSET already set.)
+	 *
+	 * Set 8 bits, 1 stop bit, no parity.
+	 *
+	 * LCR<7>       0       divisor latch access bit
+	 * LCR<6>       0       break control (1=send break)
+	 * LCR<5>       0       stick parity (0=space, 1=mark)
+	 * LCR<4>       0       parity even (0=odd, 1=even)
+	 * LCR<3>       0       parity enable (1=enabled)
+	 * LCR<2>       0       # stop bits (0=1, 1=1.5)
+	 * LCR<1:0>     11      bits per character(00=5, 01=6, 10=7, 11=8)
+	 */
+	outreg(channel, LCR, 0x3);
+
+	outreg(channel, FCR, FIFO_ENABLE);	/* Enable the FIFO */
+
+	outreg(channel, IER, INT_ENABLE);	/* Enable appropriate interrupts */
+}
+
+/******************************
+ Routine:
+ Description:
+   Set the baud rate.
+ ******************************/
+void serial_set(int channel, unsigned long baud)
+{
+	unsigned char sav_lcr;
+
+	/*
+	 * Enable access to the divisor latches by setting DLAB in LCR.
+	 *
+	 */
+	sav_lcr = inreg(channel, LCR);
+
+#if 0
+	/*
+	 * Set baud rate 
+	 */
+	outreg(channel, LCR, LCR_DLAB | sav_lcr);
+	//  outreg(DLL,(XTAL/(16*2*(baud))-2));
+	outreg(channel, DLL, XTAL / (16 * baud));
+	//  outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
+	outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
+#else
+	/*
+	 * Note: Set baud rate, hardcoded here for rate of 115200
+	 * since became unsure of above "buad rate" algorithm (??). 
+	 */
+	outreg(channel, LCR, 0x83);
+	outreg(channel, DLM, 0x00);	// See note above
+	outreg(channel, DLL, 0x02);	// See note above.
+	outreg(channel, LCR, 0x03);
+#endif
+
+	/*
+	 * Restore line control register
+	 */
+	outreg(channel, LCR, sav_lcr);
+}
+
+
+/******************************
+ Routine:
+ Description:
+   Transmit a character.
+ ******************************/
+void serial_putc(int channel, int c)
+{
+	while ((inreg(channel, LSR) & LSR_THRE) == 0);
+	outreg(channel, THR, c);
+}
+
+/******************************
+ Routine:
+ Description:
+    Read a received character if one is
+    available.  Return -1 otherwise.
+ ******************************/
+int serial_getc(int channel)
+{
+	if (inreg(channel, LSR) & LSR_DR) {
+		return inreg(channel, RBR);
+	}
+	return -1;
+}
+
+/******************************
+ Routine:
+ Description:
+   Used by embedded gdb client. (example; gdb-stub.c)
+ ******************************/
+char getDebugChar()
+{
+	int val;
+	while ((val = serial_getc(DEBUG_CHANNEL)) == -1);	// loop until we get a character in.
+	return (char) val;
+}
+
+/******************************
+ Routine:
+ Description:
+   Used by embedded gdb target. (example; gdb-stub.c)
+ ******************************/
+void putDebugChar(char c)
+{
+	serial_putc(DEBUG_CHANNEL, (int) c);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev64120/setup.c linux/arch/mips/galileo-boards/ev64120/setup.c
--- linux.orig/arch/mips/galileo-boards/ev64120/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev64120/setup.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,188 @@
+/*
+ * setup.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Galileo Evaluation Boards - board dependent boot routines
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/timex.h>
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/reboot.h>
+#include <asm/mc146818rtc.h>
+#include <asm/traps.h>
+#include <linux/version.h>
+#include <linux/bootmem.h>
+
+extern struct rtc_ops no_rtc_ops;
+
+/* These functions are used for rebooting or halting the machine*/
+extern void galileo_machine_restart(char *command);
+extern void galileo_machine_halt(void);
+extern void galileo_machine_power_off(void);
+/* 
+ *This structure holds pointers to the pci configuration space accesses
+ *and interrupts allocating routine for device over the PCI
+ */
+extern struct pci_ops galileo_pci_ops;
+
+extern unsigned long mips_machgroup;
+
+char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 "
+	    "root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal "
+	    "ip=192.168.1.211:192.168.1.1:::gt::"
+};
+
+//struct eeprom_parameters eeprom_param;
+
+/*
+ * This function is added because arch/mips/mm/init.c needs it
+ * basically it does nothing
+ */
+void prom_free_prom_memory(void)
+{
+}
+
+extern void (*board_time_init) (struct irqaction * irq);
+
+static unsigned char galileo_rtc_read_data(unsigned long addr)
+{
+	return 0;
+}
+
+static void galileo_rtc_write_data(unsigned char data, unsigned long addr)
+{
+}
+
+static int galileo_rtc_bcd_mode(void)
+{
+	return 0;
+}
+
+struct rtc_ops galileo_rtc_ops = {
+	&galileo_rtc_read_data,
+	&galileo_rtc_write_data,
+	&galileo_rtc_bcd_mode
+};
+
+
+void __init bus_error_init(void) { /* nothing */ }
+
+
+/********************************************************************
+ *ev64120_setup -
+ *
+ *Initializes basic routines and structures pointers, memory size (as
+ *given by the bios and saves the command line.
+ *
+ *
+ *Inputs :
+ *
+ *Outpus :
+ *
+ *********************************************************************/
+extern void galileo_time_init();
+void ev64120_setup(void)
+{
+	unsigned int i, j;
+
+	//printk(KERN_INFO "ev64120_setup\n");
+
+	_machine_restart = galileo_machine_restart;
+	_machine_halt = galileo_machine_halt;
+	_machine_power_off = galileo_machine_power_off;
+
+	rtc_ops = &galileo_rtc_ops;
+
+	board_time_init = galileo_time_init;
+	set_io_port_base(KSEG1);
+
+#ifdef CONFIG_L2_L3_CACHE
+#error "external cache not implemented yet"
+	config_register = read_32bit_cp0_register(CP0_CONFIG);
+	printk("\n\n\nchecking second level cache cp0_config = %08lx\n",
+	       config_register);
+	if (config_register & CONF_SC) {	// second/third level cache available
+		config_register = config_register & (1 << 12);
+		write_32bit_cp0_register(CP0_CONFIG, config_register);
+		printk
+		    ("\n\n\nchecking second level cache cp0_config = %08lx\n",
+		     config_register);
+	}
+#endif
+
+}
+
+const char *get_system_type(void)
+{
+	return "Galileo EV64120A";
+}
+
+/*
+ * SetUpBootInfo -
+ *
+ * This function is called at very first stages of kernel startup.
+ * It specifies for the kernel the evaluation board that the linux
+ * is running on. Then it saves the eprom parameters that holds the
+ * command line, memory size etc...
+ *
+ * Inputs :
+ * argc - nothing
+ * argv - holds a pointer to the eprom parameters
+ * envp - nothing
+ */
+
+void SetUpBootInfo(int argc, char **argv, char **envp)
+{
+	mips_machgroup = MACH_GROUP_GALILEO;
+	mips_machtype = MACH_EV64120A;
+}
+
+void __init prom_init(int a, char **b, char **c, int *d)
+{
+	unsigned long free_start, free_end, start_pfn, bootmap_size;
+
+	mips_machgroup = MACH_GROUP_GALILEO;
+	add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/Makefile linux/arch/mips/galileo-boards/ev96100/Makefile
--- linux.orig/arch/mips/galileo-boards/ev96100/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/Makefile	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,20 @@
+#
+#  Copyright 2000 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc.
+#     	ppopov@mvista.com or source@mvista.com
+#
+# Makefile for the Galileo EV96100 board.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET:= ev96100.o
+
+obj-y	:= init.o pci_ops.o pci_fixups.o time.o irq.o int-handler.o setup.o \
+	    puts.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/init.c linux/arch/mips/galileo-boards/ev96100/init.c
--- linux.orig/arch/mips/galileo-boards/ev96100/init.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/init.c	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/generic/generic.c
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <asm/galileo-boards/ev96100.h>
+
+
+/* Environment variable */
+
+typedef struct {
+	char *name;
+	char *val;
+} t_env_var;
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+char arcs_cmdline[CL_SIZE];
+
+int init_debug = 0;
+
+char * __init prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void prom_free_prom_memory (void)
+{
+}
+
+void  __init prom_init_cmdline(void)
+{
+	char *cp;
+	int actr;
+
+	actr = 1; /* Always ignore argv[0] */
+
+	cp = &(arcs_cmdline[0]);
+	while(actr < prom_argc) {
+	        strcpy(cp, prom_argv[actr]);
+		cp += strlen(prom_argv[actr]);
+		*cp++ = ' ';
+		actr++;
+	}
+	if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+		--cp;
+	*cp = '\0';
+}
+
+char *prom_getenv(char *envname)
+{
+	/*
+	 * Return a pointer to the given environment variable.
+	 */
+
+	t_env_var *env = (t_env_var *) prom_envp;
+	int i;
+
+	i = strlen(envname);
+
+	while (env->name) {
+		if (strncmp(envname, env->name, i) == 0) {
+			return (env->val);
+		}
+		env++;
+	}
+	return (NULL);
+}
+
+static inline unsigned char str2hexnum(unsigned char c)
+{
+	if (c >= '0' && c <= '9')
+		return c - '0';
+	if (c >= 'a' && c <= 'f')
+		return c - 'a' + 10;
+	return 0;		/* foo */
+}
+
+static inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		unsigned char num;
+
+		if ((*str == '.') || (*str == ':'))
+			str++;
+		num = str2hexnum(*str++) << 4;
+		num |= (str2hexnum(*str++));
+		ea[i] = num;
+	}
+}
+
+int get_ethernet_addr(char *ethernet_addr)
+{
+	char *ethaddr_str;
+
+	ethaddr_str = prom_getenv("ethaddr");
+	if (!ethaddr_str) {
+		printk("ethaddr not set in boot prom\n");
+		return -1;
+	}
+	str2eaddr(ethernet_addr, ethaddr_str);
+
+	if (init_debug > 1) {
+		int i;
+		printk("get_ethernet_addr: ");
+		for (i = 0; i < 5; i++)
+			printk("%02x:",
+			       (unsigned char) *(ethernet_addr + i));
+		printk("%02x\n", *(ethernet_addr + i));
+	}
+
+	return 0;
+}
+
+const char *get_system_type(void)
+{
+	return "Galileo EV96100";
+}
+
+void __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
+{
+	volatile unsigned char *uart;
+	char ppbuf[8];
+
+	prom_argc = argc;
+	prom_argv = argv;
+	prom_envp = envp;
+
+	mips_machgroup = MACH_GROUP_GALILEO;
+	mips_machtype = MACH_EV96100;
+
+	prom_init_cmdline();
+
+	/* 32 MB upgradable */
+	add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/int-handler.S linux/arch/mips/galileo-boards/ev96100/int-handler.S
--- linux.orig/arch/mips/galileo-boards/ev96100/int-handler.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/int-handler.S	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,32 @@
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.set	noat
+	.align	5
+
+NESTED(ev96100IRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI				# Important: mark KERNEL mode !
+
+	mfc0	t0, CP0_CAUSE		# get pending interrupts
+	mfc0	t1, CP0_STATUS		# get enabled interrupts
+	and	t0, t1			# isolate allowed ones
+
+	# FIX ME add R7000 extensions
+	andi	t0,0xff00		# isolate pending bits
+	andi	a0, t0, CAUSEF_IP7
+	beq	a0, zero, 1f
+	move	a0, sp
+	jal	mips_timer_interrupt
+	j	ret_from_irq
+
+1:	beqz	t0, 3f			# spurious interrupt
+	move	a0, t0
+	move	a1, sp			# delay slot
+	jal	ev96100_cpu_irq
+	j	ret_from_irq
+
+3:	j	spurious_interrupt
+	END(ev96100IRQ)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/irq.c linux/arch/mips/galileo-boards/ev96100/irq.c
--- linux.orig/arch/mips/galileo-boards/ev96100/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/irq.c	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/atlas/atlas_int.c.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/galileo-boards/ev96100int.h>
+
+extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
+
+extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
+extern asmlinkage void ev96100IRQ(void);
+
+static void disable_ev96100_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	save_and_cli(flags);
+	clear_cp0_status(0x100 << irq_nr);
+	restore_flags(flags);
+}
+
+static inline void enable_ev96100_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	save_and_cli(flags);
+	set_cp0_status(0x100 << irq_nr);
+	restore_flags(flags);
+}
+
+static unsigned int startup_ev96100_irq(unsigned int irq)
+{
+	enable_ev96100_irq(irq);
+
+	return 0;	/* never anything pending */
+}
+
+#define shutdown_ev96100_irq		disable_ev96100_irq
+#define mask_and_ack_ev96100_irq	disable_ev96100_irq
+
+static void end_ev96100_irq (unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		enable_ev96100_irq(irq);
+}
+
+static inline unsigned int ffz8(unsigned int word)
+{
+	unsigned long k;
+
+	k = 7;
+	if (word & 0x0fUL) { k -= 4;  word <<= 4;  }
+	if (word & 0x30UL) { k -= 2;  word <<= 2;  }
+	if (word & 0x40UL) { k -= 1; }
+
+	return k;
+}
+
+asmlinkage void ev96100_cpu_irq(unsigned long cause, struct pt_regs * regs)
+{
+	if (!(cause & 0xff00))
+		return;
+
+	do_IRQ(ffz8((cause >> 8) & 0xff), regs);
+}
+
+static struct hw_interrupt_type ev96100_irq_type = {
+	"EV96100",
+	startup_ev96100_irq,
+	shutdown_ev96100_irq,
+	enable_ev96100_irq,
+	disable_ev96100_irq,
+	mask_and_ack_ev96100_irq,
+	end_ev96100_irq
+};
+
+void __init init_IRQ(void)
+{
+	int i;
+
+	set_except_vector(0, ev96100IRQ);
+	init_generic_irq();
+
+	for (i = 0; i < 8; i++) {
+		irq_desc[i].status	= IRQ_DISABLED;
+		irq_desc[i].action	= 0;
+		irq_desc[i].depth	= 1;
+		irq_desc[i].handler	= &ev96100_irq_type;
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/pci_fixups.c linux/arch/mips/galileo-boards/ev96100/pci_fixups.c
--- linux.orig/arch/mips/galileo-boards/ev96100/pci_fixups.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/pci_fixups.c	2002-08-01 06:42:38.000000000 +0000
@@ -0,0 +1,96 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	EV96100 Board specific pci fixups.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci_ids.h>
+
+#include <asm/gt64120.h>
+#include <asm/galileo-boards/ev96100.h>
+
+extern unsigned short get_gt_devid(void);
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
+void __init pcibios_fixup_irqs(void)
+{
+	struct pci_dev *dev;
+	unsigned int slot;
+	u32 vendor;
+	unsigned short gt_devid = get_gt_devid();
+
+	/*
+	** EV96100/A interrupt routing for pci bus 0
+	**
+	** Note: EV96100A board with irq jumper set on 'VxWorks'
+	** for EV96100 compatibility.
+	*/
+
+	pci_for_each_dev(dev) {
+		if (dev->bus->number != 0)
+			return;
+
+		slot = PCI_SLOT(dev->devfn);
+		pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
+
+#ifdef DEBUG
+		printk("devfn %x, slot %d devid %x\n", 
+				dev->devfn, slot, gt_devid);
+#endif
+
+		/* fixup irq line based on slot # */
+		if (slot == 8) {
+			dev->irq = 5;
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 
+					dev->irq);
+		}
+		else if (slot == 9) {
+			dev->irq = 2;
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 
+					dev->irq);
+		}
+	}
+}
+unsigned int pcibios_assign_all_busses(void)
+{
+	return 0;
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/pci_ops.c linux/arch/mips/galileo-boards/ev96100/pci_ops.c
--- linux.orig/arch/mips/galileo-boards/ev96100/pci_ops.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/pci_ops.c	2002-08-01 06:42:28.000000000 +0000
@@ -0,0 +1,274 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Galileo EV96100 board specific pci support.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/generic/pci.c
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/delay.h>
+#include <asm//gt64120.h>
+#include <asm/galileo-boards/ev96100.h>
+#include <asm/pci_channel.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#define GT_PCI_MEM_BASE    0x12000000
+#define GT_PCI_MEM_SIZE    0x02000000
+#define GT_PCI_IO_BASE     0x10000000
+#define GT_PCI_IO_SIZE     0x02000000
+static struct resource pci_io_resource = {
+	"io pci IO space", 
+	0x10000000,
+	0x10000000 + 0x02000000,
+	IORESOURCE_IO};
+
+static struct resource pci_mem_resource = {
+	"ext pci memory space", 
+	0x12000000,
+	0x12000000 + 0x02000000,
+	IORESOURCE_MEM};
+
+extern struct pci_ops gt96100_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+	{ &gt96100_pci_ops, &pci_io_resource, &pci_mem_resource, 1, 0xff },
+	{ NULL, NULL, NULL, NULL, NULL}
+};
+
+int
+static gt96100_config_access(unsigned char access_type, struct pci_dev *dev,
+                           unsigned char where, u32 *data)
+{
+	unsigned char bus = dev->bus->number;
+	unsigned char dev_fn = dev->devfn;
+        u32 intr;
+
+
+	if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0))) {
+            return -1; /* Because of a bug in the galileo (for slot 31). */
+        }
+
+	/* Clear cause register bits */
+	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 
+	                             GT_INTRCAUSE_TARABORT0_BIT));
+
+	/* Setup address */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (bus         << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (dev_fn      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+	udelay(2);
+
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		if (dev_fn != 0) {
+		*data = le32_to_cpu(*data);
+		}
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
+	} 
+        else {
+		GT_READ(GT_PCI0_CFGDATA_OFS, *data);
+		if (dev_fn != 0) {
+		*data = le32_to_cpu(*data);
+		}
+	}
+
+	udelay(2);
+
+	/* Check for master or target abort */
+	GT_READ(GT_INTRCAUSE_OFS, intr);
+
+	if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT))
+	{
+		//printk("config access error:  %x:%x\n", dev_fn,where);
+	        /* Error occured */
+
+	        /* Clear bits */
+	        GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 
+					      GT_INTRCAUSE_TARABORT0_BIT) );
+
+		if (access_type == PCI_ACCESS_READ) {
+			*data = 0xffffffff;
+		}
+		return -1;
+	}
+	return 0;
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int
+read_config_byte (struct pci_dev *dev, int where, u8 *val)
+{
+	u32 data = 0;
+
+	if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) {
+		*val = 0xff;
+		return -1;
+	}
+
+	*val = (data >> ((where & 3) << 3)) & 0xff;
+        DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n", 
+                dev->bus->number, dev->devfn, where, *val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+read_config_word (struct pci_dev *dev, int where, u16 *val)
+{
+	u32 data = 0;
+
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) {
+		*val = 0xffff;
+		return -1;
+	}
+
+	*val = (data >> ((where & 3) << 3)) & 0xffff;
+        DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", 
+                dev->bus->number, dev->devfn, where, *val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+read_config_dword (struct pci_dev *dev, int where, u32 *val)
+{
+	u32 data = 0;
+
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	
+	if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) {
+		*val = 0xffffffff;
+		return -1;
+	}
+
+	*val = data;
+        DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n", 
+                dev->bus->number, dev->devfn, where, *val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_byte (struct pci_dev *dev, int where, u8 val)
+{
+	u32 data = 0;
+       
+	if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((where & 3) << 3))) |
+	       (val << ((where & 3) << 3));
+        DBG("cfg write byte: bus %d dev_fn %x where %x: val %x\n", 
+                dev->bus->number, dev->devfn, where, val);
+
+	if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
+		return -1;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+write_config_word (struct pci_dev *dev, int where, u16 val)
+{
+        u32 data = 0;
+
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+       
+        if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data))
+	       return -1;
+
+	data = (data & ~(0xffff << ((where & 3) << 3))) | 
+	       (val << ((where & 3) << 3));
+        DBG("cfg write word: bus %d dev_fn %x where %x: val %x\n", 
+                dev->bus->number, dev->devfn, where, val);
+
+	if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
+	       return -1;
+
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+write_config_dword(struct pci_dev *dev, int where, u32 val)
+{
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val))
+	       return -1;
+        DBG("cfg write dword: bus %d dev_fn %x where %x: val %x\n", 
+                dev->bus->number, dev->devfn, where, val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops gt96100_pci_ops = {
+	read_config_byte,
+        read_config_word,
+	read_config_dword,
+	write_config_byte,
+	write_config_word,
+	write_config_dword
+};
+
+#endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/puts.c linux/arch/mips/galileo-boards/ev96100/puts.c
--- linux.orig/arch/mips/galileo-boards/ev96100/puts.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/puts.c	2002-08-01 06:42:46.000000000 +0000
@@ -0,0 +1,144 @@
+
+/*
+ * Debug routines which directly access the uart.
+ */
+
+#include <linux/types.h>
+#include <asm/galileo-boards/ev96100.h>
+
+
+//#define SERIAL_BASE    EV96100_UART0_REGS_BASE
+#define SERIAL_BASE    0xBD000020
+#define NS16550_BASE   SERIAL_BASE
+
+#define SERA_CMD       0x0D
+#define SERA_DATA      0x08
+//#define SERB_CMD       0x05
+#define SERB_CMD       20
+#define SERB_DATA      0x00
+#define TX_BUSY        0x20
+
+#define TIMEOUT    0xffff
+#undef SLOW_DOWN
+
+static const char digits[16] = "0123456789abcdef";
+static volatile unsigned char * const com1 = (unsigned char *)SERIAL_BASE;
+
+
+#ifdef SLOW_DOWN
+static inline void slow_down()
+{
+    int k;
+    for (k=0; k<10000; k++);
+}
+#else
+#define slow_down()
+#endif
+
+void
+putch(const unsigned char c)
+{
+    unsigned char ch;
+    int i = 0;
+
+    do {
+        ch = com1[SERB_CMD];
+        slow_down();
+        i++;
+        if (i>TIMEOUT) {
+            break;
+        }
+    } while (0 == (ch & TX_BUSY));
+    com1[SERB_DATA] = c;
+}
+
+void
+putchar(const unsigned char c)
+{
+    unsigned char ch;
+    int i = 0;
+
+    do {
+        ch = com1[SERB_CMD];
+        slow_down();
+        i++;
+        if (i>TIMEOUT) {
+            break;
+        }
+    } while (0 == (ch & TX_BUSY));
+    com1[SERB_DATA] = c;
+}
+
+void
+puts(unsigned char *cp)
+{
+    unsigned char ch;
+    int i = 0;
+
+    while (*cp) {
+        do {
+             ch = com1[SERB_CMD];
+            slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (0 == (ch & TX_BUSY));
+        com1[SERB_DATA] = *cp++;
+    }
+    putch('\r');
+    putch('\n');
+}
+
+void
+fputs(unsigned char *cp)
+{
+    unsigned char ch;
+    int i = 0;
+
+    while (*cp) {
+
+        do {
+             ch = com1[SERB_CMD];
+             slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (0 == (ch & TX_BUSY));
+        com1[SERB_DATA] = *cp++;
+    }
+}
+
+
+void
+put64(uint64_t ul)
+{
+    int cnt;
+    unsigned ch;
+
+    cnt = 16;            /* 16 nibbles in a 64 bit long */
+    putch('0');
+    putch('x');
+    do {
+        cnt--;
+        ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
+                putch(digits[ch]);
+    } while (cnt > 0);
+}
+
+void
+put32(unsigned u)
+{
+    int cnt;
+    unsigned ch;
+
+    cnt = 8;            /* 8 nibbles in a 32 bit long */
+    putch('0');
+    putch('x');
+    do {
+        cnt--;
+        ch = (unsigned char)(u >> cnt * 4) & 0x0F;
+                putch(digits[ch]);
+    } while (cnt > 0);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/setup.c linux/arch/mips/galileo-boards/ev96100/setup.c
--- linux.orig/arch/mips/galileo-boards/ev96100/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/setup.c	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,213 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Galileo EV96100 setup.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/atlas/atlas_setup.c.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mc146818rtc.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/pci.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/irq.h>
+#include <asm/delay.h>
+#include <asm/gt64120.h>
+#include <asm/galileo-boards/ev96100.h>
+#include <asm/galileo-boards/ev96100int.h>
+
+
+void (*__wbflush) (void);
+
+#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
+extern void console_setup(char *, int *);
+char serial_console[20];
+#endif
+
+extern char * __init prom_getcmdline(void);
+
+extern void mips_reboot_setup(void);
+extern struct rtc_ops no_rtc_ops;
+extern struct resource ioport_resource;
+
+static void rm7000_wbflush(void)
+{
+	 __asm__ __volatile__ ("sync");
+}
+
+unsigned char mac_0_1[12];
+
+
+void __init ev96100_setup(void)
+{
+	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
+	unsigned long status = read_32bit_cp0_register(CP0_STATUS);
+	unsigned long info = read_32bit_cp0_register(CP0_INFO);
+	u32 tmp;
+
+	char *argptr;
+
+	clear_cp0_status(ST0_FR);
+        __wbflush = rm7000_wbflush;
+
+        if (config & 0x8) {
+            printk("Secondary cache is enabled\n");
+        }
+        else {
+            printk("Secondary cache is disabled\n");
+        }
+
+        if (status & (1<<27)) {
+            printk("User-mode cache ops enabled\n");
+        }
+        else {
+            printk("User-mode cache ops disabled\n");
+        }
+
+        printk("CP0 info reg: %x\n", (unsigned)info);
+        if (info & (1<<28)) {
+            printk("burst mode Scache RAMS\n");
+        }
+        else {
+            printk("pipelined Scache RAMS\n");
+        }
+
+        if ((info & (0x3<<26)) >> 26 == 0) {
+            printk("67 percent drive strength\n");
+        }
+        else if ((info & (0x3<<26)) >> 26 == 1) {
+            printk("50 percent drive strength\n");
+        }
+        else if ((info & (0x3<<26)) >> 26 == 2) {
+            printk("100 percent drive strength\n");
+        }
+        else if ((info & (0x3<<26)) >> 26 == 3) {
+            printk("83 percent drive strength\n");
+        }
+
+
+        if ((info & (0x3<<23)) >> 23 == 0) {
+            printk("Write Protocol: R4000 compatible\n");
+        }
+        else if ((info & (0x3<<23)) >> 23 == 1) {
+            printk("Write Protocol: Reserved\n");
+        }
+        else if ((info & (0x3<<23)) >> 23 == 2) {
+            printk("Write Protocol: Pipelined\n");
+        }
+        else if ((info & (0x3<<23)) >> 23 == 3) {
+            printk("Write Protocol: Write re-issue\n");
+        }
+
+        if (info & 0x1) {
+            printk("Atomic Enable is set\n");
+        }
+
+	argptr = prom_getcmdline();
+#ifdef CONFIG_SERIAL_CONSOLE
+	if (strstr(argptr, "console=") == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " console=ttyS0,115200");
+	}
+#endif	  
+
+	rtc_ops = &no_rtc_ops;
+	mips_reboot_setup();
+	set_io_port_base(KSEG1);
+	ioport_resource.start = GT_PCI_IO_BASE;
+	ioport_resource.end   = GT_PCI_IO_BASE + 0x01ffffff;
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
+#endif
+
+
+	/* 
+	 * setup gt controller master bit so we can do config cycles 
+	 */
+
+	/* Clear cause register bits */
+	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 
+	                             GT_INTRCAUSE_TARABORT0_BIT));
+	/* Setup address */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+	udelay(2);
+	tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS));
+
+	tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 
+		PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+	udelay(2);
+	*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS) = cpu_to_le32(tmp);
+
+	/* Setup address */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+	udelay(2);
+	tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS));
+}
+
+unsigned short get_gt_devid() 
+{
+	u32 gt_devid;
+
+	/* Figure out if this is a gt96100 or gt96100A */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+	udelay(4);
+	gt_devid = le32_to_cpu(*(volatile u32 *)
+			(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS));
+	return (unsigned short)(gt_devid>>16);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/ev96100/time.c linux/arch/mips/galileo-boards/ev96100/time.c
--- linux.orig/arch/mips/galileo-boards/ev96100/time.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/ev96100/time.c	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,269 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Galileo EV96100 rtc routines.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/atlas/atlas_rtc.c.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/timex.h>
+
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+
+
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+
+extern volatile unsigned long wall_jiffies;
+unsigned long missed_heart_beats = 0;
+
+static unsigned long r4k_offset; /* Amount to increment compare reg each time */
+static unsigned long r4k_cur;    /* What counter should be at next timer irq */
+extern rwlock_t xtime_lock;
+
+static inline void ack_r4ktimer(unsigned long newval)
+{
+	write_32bit_cp0_register(CP0_COMPARE, newval);
+}
+
+static int set_rtc_mmss(unsigned long nowtime)
+{
+    /* EV96100 does not have a real time clock */
+    int retval = 0;
+
+    return retval;
+}
+
+
+
+/* 
+ * Figure out the r4k offset, the amount to increment the compare
+ * register for each time tick. 
+ * Use the RTC to calculate offset.
+ */
+static unsigned long __init cal_r4koff(void)
+{
+	unsigned long count;
+        count = 300000000/2;
+	return (count / HZ);
+}
+
+
+static unsigned long __init get_mips_time(void)
+{
+	unsigned int year, mon, day, hour, min, sec;
+
+        year = 2000;
+        mon = 10;
+        day = 31;
+        hour = 0;
+        min = 0;
+        sec = 0;
+	return mktime(year, mon, day, hour, min, sec);
+}
+
+
+/*
+ * called from start_kernel()
+ */
+void __init time_init(void)
+{
+
+        unsigned int est_freq;
+
+	r4k_offset = cal_r4koff();
+
+	est_freq = 2*r4k_offset*HZ;	
+	est_freq += 5000;    /* round */
+	est_freq -= est_freq%10000;
+	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
+	       (est_freq%1000000)*100/1000000);
+	r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
+
+	write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
+
+        /* FIX ME */
+	change_cp0_status(ST0_IM, IE_IRQ5);
+}
+
+/* This is for machines which generate the exact clock. */
+#define USECS_PER_JIFFY (1000000/HZ)
+
+/* Cycle counter value at the previous timer interrupt.. */
+
+static unsigned int timerhi = 0, timerlo = 0;
+
+/*
+ * FIXME: Does playing with the RP bit in c0_status interfere with this code?
+ */
+static unsigned long do_fast_gettimeoffset(void)
+{
+	u32 count;
+	unsigned long res, tmp;
+
+	/* Last jiffy when do_fast_gettimeoffset() was called. */
+	static unsigned long last_jiffies=0;
+	unsigned long quotient;
+
+	/*
+	 * Cached "1/(clocks per usec)*2^32" value.
+	 * It has to be recalculated once each jiffy.
+	 */
+	static unsigned long cached_quotient=0;
+
+	tmp = jiffies;
+
+	quotient = cached_quotient;
+
+	if (tmp && last_jiffies != tmp) {
+		last_jiffies = tmp;
+		__asm__(".set\tnoreorder\n\t"
+			".set\tnoat\n\t"
+			".set\tmips3\n\t"
+			"lwu\t%0,%2\n\t"
+			"dsll32\t$1,%1,0\n\t"
+			"or\t$1,$1,%0\n\t"
+			"ddivu\t$0,$1,%3\n\t"
+			"mflo\t$1\n\t"
+			"dsll32\t%0,%4,0\n\t"
+			"nop\n\t"
+			"ddivu\t$0,%0,$1\n\t"
+			"mflo\t%0\n\t"
+			".set\tmips0\n\t"
+			".set\tat\n\t"
+			".set\treorder"
+			:"=&r" (quotient)
+			:"r" (timerhi),
+			 "m" (timerlo),
+			 "r" (tmp),
+			 "r" (USECS_PER_JIFFY));
+		cached_quotient = quotient;
+	}
+
+	/* Get last timer tick in absolute kernel time */
+	count = read_32bit_cp0_register(CP0_COUNT);
+
+	/* .. relative to previous jiffy (32 bits is enough) */
+	count -= timerlo;
+
+	__asm__("multu\t%1,%2\n\t"
+		"mfhi\t%0"
+		:"=r" (res)
+		:"r" (count),
+		 "r" (quotient));
+
+	/*
+ 	 * Due to possible jiffies inconsistencies, we need to check 
+	 * the result so that we'll get a timer that is monotonic.
+	 */
+	if (res >= USECS_PER_JIFFY)
+		res = USECS_PER_JIFFY-1;
+
+	return res;
+}
+
+void do_gettimeofday(struct timeval *tv)
+{
+	unsigned int flags;
+
+	read_lock_irqsave (&xtime_lock, flags);
+	*tv = xtime;
+	tv->tv_usec += do_fast_gettimeoffset();
+
+	/*
+	 * xtime is atomically updated in timer_bh. jiffies - wall_jiffies
+	 * is nonzero if the timer bottom half hasnt executed yet.
+	 */
+	if (jiffies - wall_jiffies)
+		tv->tv_usec += USECS_PER_JIFFY;
+
+	read_unlock_irqrestore (&xtime_lock, flags);
+
+	if (tv->tv_usec >= 1000000) {
+		tv->tv_usec -= 1000000;
+		tv->tv_sec++;
+	}
+}
+
+void do_settimeofday(struct timeval *tv)
+{
+	write_lock_irq (&xtime_lock);
+
+	/* This is revolting. We need to set the xtime.tv_usec correctly.
+	 * However, the value in this location is is value at the last tick.
+	 * Discover what correction gettimeofday would have done, and then
+	 * undo it!
+	 */
+	tv->tv_usec -= do_fast_gettimeoffset();
+
+	if (tv->tv_usec < 0) {
+		tv->tv_usec += 1000000;
+		tv->tv_sec--;
+	}
+
+	xtime = *tv;
+	time_adjust = 0;		/* stop active adjtime() */
+	time_status |= STA_UNSYNC;
+	time_maxerror = NTP_PHASE_LIMIT;
+	time_esterror = NTP_PHASE_LIMIT;
+
+	write_unlock_irq (&xtime_lock);
+}
+
+/*
+ * There are a lot of conceptually broken versions of the MIPS timer interrupt
+ * handler floating around.  This one is rather different, but the algorithm
+ * is probably more robust.
+ */
+void mips_timer_interrupt(struct pt_regs *regs)
+{
+        int irq = 7; /* FIX ME */
+
+	if (r4k_offset == 0) {
+            goto null;
+        }
+
+	do {
+		kstat.irqs[0][irq]++;
+		do_timer(regs);
+		r4k_cur += r4k_offset;
+		ack_r4ktimer(r4k_cur);
+
+	} while (((unsigned long)read_32bit_cp0_register(CP0_COUNT) 
+                    - r4k_cur) < 0x7fffffff);
+	return;
+
+null:
+	ack_r4ktimer(0);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/generic/Makefile linux/arch/mips/galileo-boards/generic/Makefile
--- linux.orig/arch/mips/galileo-boards/generic/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/generic/Makefile	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,36 @@
+#
+# Carsten Langgaard, carstenl@mips.com
+# Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+#
+# ########################################################################
+#
+# This program is free software; you can distribute it and/or modify it
+# under the terms of the GNU General Public License (Version 2) as
+# published by the Free Software Foundation.
+# 
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+# 
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+#
+# #######################################################################
+#
+# Makefile for the MIPS boards generic routines under Linux.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+# Note 2! The CFLAGS definitions are now in the main makefile...
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET:= galboards.o
+
+obj-y := reset.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/galileo-boards/generic/reset.c linux/arch/mips/galileo-boards/generic/reset.c
--- linux.orig/arch/mips/galileo-boards/generic/reset.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/galileo-boards/generic/reset.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,72 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Galileo EV96100 reset routines.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/generic/reset.c
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+
+#include <asm/reboot.h>
+#include <asm/galileo-boards/ev96100.h>
+
+static void mips_machine_restart(char *command);
+static void mips_machine_halt(void);
+
+static void mips_machine_restart(char *command)
+{
+	set_cp0_status(ST0_BEV | ST0_ERL);
+	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_32bit_cp0_register(CP0_WIRED, 0);
+	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+	while (1);
+}
+
+static void mips_machine_halt(void)
+{
+	printk(KERN_NOTICE "You can safely turn off the power\n");
+	while (1)
+		__asm__(".set\tmips3\n\t"
+	                "wait\n\t"
+			".set\tmips0");
+}
+
+void mips_reboot_setup(void)
+{
+	_machine_restart = mips_machine_restart;
+	_machine_halt = mips_machine_halt;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/gt64120/momenco_ocelot/dbg_io.c linux/arch/mips/gt64120/momenco_ocelot/dbg_io.c
--- linux.orig/arch/mips/gt64120/momenco_ocelot/dbg_io.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/gt64120/momenco_ocelot/dbg_io.c	2002-08-01 06:42:43.000000000 +0000
@@ -2,6 +2,8 @@
 
 #if defined(CONFIG_REMOTE_DEBUG)
 
+#include <asm/serial.h> /* For the serial port location and base baud */
+
 /* --- CONFIG --- */
 
 typedef unsigned char uint8;
@@ -36,8 +38,8 @@
 /* === CONFIG === */
 
 /* [jsun] we use the second serial port for kdb */
-#define         BASE                    0xbd000020
-#define         MAX_BAUD                115200
+#define         BASE                    OCELOT_SERIAL1_BASE
+#define         MAX_BAUD                OCELOT_BASE_BAUD
 
 /* === END OF CONFIG === */
 
@@ -111,7 +113,7 @@
 {
 	if (!remoteDebugInitialized) {
 		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_9600,
+		debugInit(UART16550_BAUD_38400,
 			  UART16550_DATA_8BIT,
 			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
 	}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/gt64120/momenco_ocelot/irq.c linux/arch/mips/gt64120/momenco_ocelot/irq.c
--- linux.orig/arch/mips/gt64120/momenco_ocelot/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/gt64120/momenco_ocelot/irq.c	2002-08-01 06:42:28.000000000 +0000
@@ -40,7 +40,6 @@
 #include <linux/timex.h>
 #include <linux/slab.h>
 #include <linux/random.h>
-#include <linux/irq.h>
 #include <asm/bitops.h>
 #include <asm/bootinfo.h>
 #include <asm/io.h>
@@ -144,9 +143,8 @@
 
 	/*
 	 * Clear all of the interrupts while we change the able around a bit.
-	 * int-handler is not on bootstrap
 	 */
-	clear_cp0_status(ST0_IM | ST0_BEV);
+	clear_cp0_status(ST0_IM);
 	__cli();
 
 	/* Sets the first-level interrupt dispatcher. */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h linux/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
--- linux.orig/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h	2002-08-01 06:42:47.000000000 +0000
@@ -1,14 +1,10 @@
 /*
- * $Id$
- *
  * Ocelot Board Register Definitions
  *
  * (C) 2001 Red Hat, Inc.
  *
  * GPL'd
- *
  */
-
 #ifndef __MOMENCO_OCELOT_PLD_H__
 #define __MOMENCO_OCELOT_PLD_H__
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/gt64120/momenco_ocelot/prom.c linux/arch/mips/gt64120/momenco_ocelot/prom.c
--- linux.orig/arch/mips/gt64120/momenco_ocelot/prom.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/gt64120/momenco_ocelot/prom.c	2002-08-01 06:42:29.000000000 +0000
@@ -32,7 +32,12 @@
 
 #define PLD_REG(x)	((uint8_t*)(PLD_BASE+(x)))
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
+
+const char *get_system_type(void)
+{
+	return "Momentum Ocelot";
+}
 
 /* [jsun@junsun.net] PMON passes arguments in C main() style */
 void __init prom_init(int argc, const char **arg)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/gt64120/momenco_ocelot/reset.c linux/arch/mips/gt64120/momenco_ocelot/reset.c
--- linux.orig/arch/mips/gt64120/momenco_ocelot/reset.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/gt64120/momenco_ocelot/reset.c	2002-08-01 06:42:33.000000000 +0000
@@ -15,22 +15,21 @@
 #include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/system.h>
+#include <linux/delay.h>
 
 void momenco_ocelot_restart(char *command)
 {
-	*(volatile char *) 0xbc000000 = 0x0f;
+	void *nvram = ioremap_nocache(0x2c807000, 0x1000);
 
-	/*
-	 * Ouch, we're still alive ... This time we take the silver bullet ...
-	 * ... and find that we leave the hardware in a state in which the
-	 * kernel in the flush locks up somewhen during of after the PCI
-	 * detection stuff.
-	 */
-	clear_cp0_status(ST0_BEV | ST0_ERL);
-	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-	flush_cache_all();
-	write_32bit_cp0_register(CP0_WIRED, 0);
-	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+	if (!nvram) {
+		printk(KERN_NOTICE "ioremap of reset register failed\n");
+		return;
+	}
+	writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
+					assert reset in 1/16 second */
+	mdelay(10+(1000/16));
+	iounmap(nvram);
+	printk(KERN_NOTICE "Watchdog reset failed\n");
 }
 
 void momenco_ocelot_halt(void)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/gt64120/momenco_ocelot/setup.c linux/arch/mips/gt64120/momenco_ocelot/setup.c
--- linux.orig/arch/mips/gt64120/momenco_ocelot/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/gt64120/momenco_ocelot/setup.c	2002-08-01 06:42:45.000000000 +0000
@@ -2,11 +2,12 @@
  * setup.c
  *
  * BRIEF MODULE DESCRIPTION
- * Galileo Evaluation Boards - board dependent boot routines
+ * Momentum Computer Ocelot (CP7000) - board dependent boot routines
  *
  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
  * Copyright (C) 2000 RidgeRun, Inc.
  * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2002 Momentum Computer
  *
  * Author: RidgeRun, Inc.
  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
@@ -116,8 +117,7 @@
 
 	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
 	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
-	   appears to be one of the variants of ST M48T35 - see 
-	   http://www.st.com/stonline/bin/sftab.exe?table=172&filter0=M48T35
+	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
 
 		Ocelot PLD (CS0)	0x2c000000	0xe0020000
 		NVRAM			0x2c800000	0xe0030000
@@ -155,6 +155,7 @@
 	GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
 	GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
 
+	/* For the initial programming, we assume 512MB configuration */
 	/* Relocate the CPU's view of the RAM... */
 	GT_WRITE(GT_SCS10LD_OFS, 0);
 	GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
@@ -207,17 +208,66 @@
 	switch(tmpword &3) {
 	case 3:
 		/* 512MiB */
-		add_memory_region(256<<20, 256<<20, BOOT_MEM_RAM);
+		/* Decoders are allready set -- just add the
+		 * appropriate region */
+		add_memory_region( 0x40<<20,  0xC0<<20, BOOT_MEM_RAM);
+		add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
+		break;
 	case 2:
-		/* 256MiB */
-		/* FIXME: Is it actually here, or at 0x10000000? */
-		add_memory_region(128<<20, 128<<20, BOOT_MEM_RAM);
+		/* 256MiB -- two banks of 128MiB */
+		GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
+		GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
+		GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
+
+		GT_WRITE(GT_SCS0HD_OFS, 0x7f);
+		GT_WRITE(GT_SCS2LD_OFS, 0x80);
+		GT_WRITE(GT_SCS2HD_OFS, 0xff);
+
+		/* reconfigure the PCI0 interface view of memory */
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
+		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
+		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
+
+		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
+		add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
+		break;
 	case 1:
-		/* 128MiB */
-		add_memory_region(64<<20, 64<<20, BOOT_MEM_RAM);
+		/* 128MiB -- 64MiB per bank */
+		GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
+		GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
+		GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
+
+		GT_WRITE(GT_SCS0HD_OFS, 0x3f);
+		GT_WRITE(GT_SCS2LD_OFS, 0x40);
+		GT_WRITE(GT_SCS2HD_OFS, 0x7f);
+
+		/* reconfigure the PCI0 interface view of memory */
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
+		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
+		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
+
+		/* add the appropriate region */
+		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
+		break;
 	case 0:
 		/* 64MiB */
-		;
+		GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
+		GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
+		GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
+
+		GT_WRITE(GT_SCS0HD_OFS, 0x1f);
+		GT_WRITE(GT_SCS2LD_OFS, 0x20);
+		GT_WRITE(GT_SCS2HD_OFS, 0x3f);
+
+		/* reconfigure the PCI0 interface view of memory */
+		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
+		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
+		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
+
+		break;
 	}
 
 	/* Fix up the DiskOnChip mapping */
@@ -272,11 +322,13 @@
 static int io_base_ioremap(void)
 {
 	void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
+
 	if (!io_remap_range) {
-		panic("Could not ioremap I/O port range\n");
+		panic("Could not ioremap I/O port range");
 	}
-	mips_io_port_base = io_remap_range - GT_PCI_IO_BASE;
+	set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
+
 	return 0;
 }
-module_init(io_base_ioremap);
 
+module_init(io_base_ioremap);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/Makefile linux/arch/mips/hp-lj/Makefile
--- linux.orig/arch/mips/hp-lj/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/Makefile	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,42 @@
+#
+# Makefile for the HP specific kernel interface routines
+# under Linux.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+USE_STANDARD_AS_RULE := true
+
+all: hp-lj.o
+
+O_TARGET := hp-lj.o
+
+export-objs := utils.o
+
+obj-y   := init.o setup.o irq.o int-handler.o pci.o utils.o asic.o
+
+obj-$(CONFIG_REMOTE_DEBUG) += gdb_hook.o
+obj-$(CONFIG_DIRECT_PRINTK) += gdb_hook.o
+
+obj-$(CONFIG_BLK_DEV_INITRD) += initrd.o
+
+clean:
+	rm *.o
+
+forceit:
+
+# package filesystem from rootfs directory into binary package
+romfs.bin: forceit ./rootfs
+	@genromfs -d ./rootfs -f $@
+
+# transform rootfs.bin into object file format for linking
+initrd.o: romfs.bin
+	@echo "" | $(CROSS_COMPILE)as -o $@
+	@$(CROSS_COMPILE)objcopy --add-section .initrd=$< $@
+
+
+include $(TOPDIR)/Rules.make
+
+.PHONY: forceit
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/asic.c linux/arch/mips/hp-lj/asic.c
--- linux.orig/arch/mips/hp-lj/asic.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/asic.c	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,28 @@
+
+
+#include "asm/hp-lj/asic.h"
+
+AsicId GetAsicId(void)
+{
+   static int asic = IllegalAsic;
+
+   if (asic == IllegalAsic) {
+      if (*(unsigned int *)0xbff70000 == 0x1114103c)
+         asic = HarmonyAsic;
+      else if (*(unsigned int *)0xbff80000 == 0x110d103c)
+         asic = AndrosAsic;
+      else
+	 asic = UnknownAsic;
+   }
+   return asic;
+}
+
+
+const char* const GetAsicName(void)
+{
+   static const char* const Names[] = 
+        { "Illegal", "Unknown", "Andros", "Harmony" };
+
+   return Names[(int)GetAsicId()];
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/gdb_hook.c linux/arch/mips/hp-lj/gdb_hook.c
--- linux.orig/arch/mips/hp-lj/gdb_hook.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/gdb_hook.c	2002-08-01 06:42:31.000000000 +0000
@@ -0,0 +1,100 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * This is the interface to the remote debugger stub.
+ *
+ */
+#include <linux/serialP.h>
+#include <linux/serial_reg.h>
+
+#include <asm/serial.h>
+#include <asm/io.h>
+#include <asm/hp-lj/asic.h>
+
+
+int putDebugChar(char c);
+char getDebugChar(void);
+
+
+///////////////////////  andros values ///////////////////////////////////////////////////////
+#define SERIAL_REG(offset) (*((volatile unsigned int*)(HPSR_BASE_ADDR|offset)))
+
+// Register set base address
+#define HPSR_BASE_ADDR   0xbfe00000UL
+
+// Transmit / Receive Data
+#define HPSR_DATA_OFFSET    0x00020010UL
+// Transmit control / status
+#define HPSR_TX_STAT_OFFSET 0x0002000CUL
+// Receive status
+#define HPSR_RX_STAT_OFFSET 0x00020008UL
+
+#define HPSR_TX_STAT_READY  0x8UL
+#define HPSR_RX_DATA_AVAIL  0x4UL
+
+
+///////////////////////  harmony values ///////////////////////////////////////////////////////
+// Transmit / Receive Data
+#define H_HPSR_DATA_TX       *((volatile unsigned int*)0xbff65014)
+// Transmit / Receive Data
+#define H_HPSR_DATA_RX       *((volatile unsigned int*)0xbff65018)
+// Status
+#define H_HPSR_STAT          *((volatile unsigned int*)0xbff65004)
+
+// harmony serial status bits
+#define H_SER_STAT_TX_EMPTY       0x04
+#define H_SER_STAT_RX_EMPTY       0x10
+
+
+
+
+int putDebugChar(char c)
+{
+	if (GetAsicId() == HarmonyAsic) {
+		while (!( ( (H_HPSR_STAT) & H_SER_STAT_TX_EMPTY) != 0));
+
+		H_HPSR_DATA_TX = (unsigned int) c;
+
+	} else if (GetAsicId() == AndrosAsic) {
+        	while (((SERIAL_REG(HPSR_TX_STAT_OFFSET) & HPSR_TX_STAT_READY) == 0))
+             		;
+        	SERIAL_REG(HPSR_DATA_OFFSET) = (unsigned int) c;
+        } 
+	return 1;
+}
+
+char getDebugChar(void)
+{
+	if (GetAsicId() == HarmonyAsic) {
+		while (!(((H_HPSR_STAT) & H_SER_STAT_RX_EMPTY) == 0));
+
+	        return H_HPSR_DATA_RX;
+        
+	} else if (GetAsicId() == AndrosAsic) {
+        	while ((SERIAL_REG(HPSR_RX_STAT_OFFSET) & HPSR_RX_DATA_AVAIL) == 0)
+              		;
+
+        	return (SERIAL_REG(HPSR_DATA_OFFSET));
+
+	}
+}
+
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/init.c linux/arch/mips/hp-lj/init.c
--- linux.orig/arch/mips/hp-lj/init.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/init.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,53 @@
+/*
+ * init.c: PROM library initialisation code.
+ *
+ * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov 
+ */
+
+#include <linux/mm.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/hp-lj/asic.h>
+#include <linux/bootmem.h>
+
+#include "utils.h"
+
+
+#define Delimiter "CMDLINE="
+const char CommandLine[] = Delimiter
+  "root=/dev/hda3                                                                                                                                                                                                                                            ";
+
+char arcs_cmdline[CL_SIZE];
+
+int __init prom_init(int argc, char ** argv, char **envp)
+{
+	ulong mem_size = get_mem_avail();
+        int reserve_size = 0;
+
+	printk("Total Memory: %ld bytes\n", mem_size);
+
+	reserve_buffer(CommandLine, mem_size);
+
+	reserve_size = get_reserved_buffer_size();
+	mem_size -= reserve_size;
+
+	add_memory_region(0x0,mem_size, BOOT_MEM_RAM);
+        add_memory_region(mem_size,reserve_size, BOOT_MEM_RESERVED);
+
+	printk("Main Memory: %ld bytes\n", mem_size);
+	printk("Reserved Memory: %ld bytes at 0x%08x\n", 
+		get_reserved_buffer_size(), (ulong)get_reserved_buffer());
+
+	printk("Detected %s ASIC\n", GetAsicName());
+	mips_machgroup  = MACH_GROUP_HP_LJ;
+	mips_machtype   = MACH_UNKNOWN;
+
+	strcpy(arcs_cmdline, CommandLine+strlen(Delimiter));
+
+	return 0;
+}
+
+
+void prom_free_prom_memory (void)
+{
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/int-handler.S linux/arch/mips/hp-lj/int-handler.S
--- linux.orig/arch/mips/hp-lj/int-handler.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/int-handler.S	2002-08-01 06:42:40.000000000 +0000
@@ -0,0 +1,70 @@
+#include <asm/asm.h>
+
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+	.text
+	.set    mips1
+	.set    reorder
+	.set    macro
+	.set    noat
+	.align	5
+
+# MIPS has 16 exception vectors numbered 0 to 15
+# vector number 0 is for interrupts and the others are for various exceptions
+# The following code is installed as the handler for exception 0
+# There are 8 possible interrupts that can cause this exception.
+# The cause register indicates which are pending
+# The status register indicates which are enabled
+# This code segment basically will decipher which interrup occurred (7 downto 0)
+# and pass an integer indicating which was the highest priority pending interrupt
+# to the do_IRQ routine.
+
+NESTED(hpIRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI				# Important: mark KERNEL mode !
+	/*
+	 * Get pending interrupts
+	 */
+
+	mfc0	t0,CP0_CAUSE		# get pending interrupts
+	mfc0	t1,CP0_STATUS		# get enabled interrupts
+	and	t0,t1			# isolate allowed ones
+	andi	t0,0xff00		# isolate pending bits
+	sll	t0,16			# shift the pending bits down
+	beqz	t0,3f			# no pending intrs, then spurious
+	nop				# delay slot
+
+	/*
+	 * Find irq with highest priority
+	 * FIXME: This is slow - use binary search
+	 */
+
+	la	a0,7
+1:	bltz	t0,2f			# found pending irq
+	subu	a0,1
+	sll	t0,1
+	b	1b
+	nop				# delay slot
+
+
+call_do_IRQ:
+2:	move	a1,sp
+	jal	do_IRQ
+	nop				# delay slot
+	j       ret_from_irq
+	nop
+
+/*
+	mfc0	t0,CP0_STATUS		# disable interrupts
+	ori	t0,1
+	xori	t0,1
+	mtc0	t0,CP0_STATUS
+
+	la      a1, ret_from_irq
+	jr	a1
+*/	
+3:	j	spurious_interrupt
+END(hpIRQ)
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/irq.c linux/arch/mips/hp-lj/irq.c
--- linux.orig/arch/mips/hp-lj/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/irq.c	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Code to handle x86 style IRQs plus some generic interrupt stuff.
+ *
+ * Copyright (C) 1992 Linus Torvalds
+ * Copyright (C) 1994 - 2000 Ralf Baechle
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/gdb-stub.h>
+
+
+/* install the handler for exception 0 */
+void __init init_IRQ(void)
+{
+    extern void hpIRQ(void);
+    extern void mips_cpu_irq_init(u32 base);
+    mips_cpu_irq_init(0);
+    set_except_vector(0, hpIRQ);
+
+#ifdef CONFIG_REMOTE_DEBUG
+    { 
+       extern void breakpoint(void);
+       extern int remote_debug;
+
+       if (remote_debug) {
+          set_debug_traps();
+          breakpoint();
+       }
+    }
+#endif
+        
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/pci-dma.c linux/arch/mips/hp-lj/pci-dma.c
--- linux.orig/arch/mips/hp-lj/pci-dma.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/pci-dma.c	2002-08-01 06:42:29.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2000   Ani Joshi <ajoshi@unixbox.com>
+ *
+ *
+ * Dynamic DMA mapping support.
+ *
+ * swiped from i386, and cloned for MIPS by Geert.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
+			   dma_addr_t *dma_handle)
+{
+	void *ret;
+	int gfp = GFP_ATOMIC;
+
+	if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
+		gfp |= GFP_DMA;
+	ret = (void *)__get_free_pages(gfp, get_order(size));
+	if (ret != NULL) {
+		memset(ret, 0, size);
+		*dma_handle = virt_to_bus(ret);
+
+
+                // REVISIT  this needs reviewal as mentioned in bug report
+                // currently we bump kseg0 allocates to kseg1 uncacheable space
+
+                if ((((unsigned int) ret) & 0xe0000000) == 0x80000000) {
+	           //flush the cache to eliminate coherency problems
+	           // and assure dirty lines won't later get written over any dma, etc.
+                   flush_cache_all();
+		   ret = (void*)((unsigned int)ret | 0x20000000); 
+                }
+
+                
+	}
+	return ret;
+}
+
+
+void pci_free_consistent(struct pci_dev *hwdev, size_t size,
+			 void *vaddr, dma_addr_t dma_handle)
+{
+	free_pages((unsigned long)vaddr, get_order(size));
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/pci.c linux/arch/mips/hp-lj/pci.c
--- linux.orig/arch/mips/hp-lj/pci.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/pci.c	2002-08-01 06:42:45.000000000 +0000
@@ -0,0 +1,230 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SNI specific PCI support for RM200/RM300.
+ *
+ * Copyright (C) 1997 - 2000 Ralf Baechle
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/pci_channel.h>
+#include <asm/hp-lj/asic.h>
+
+#ifdef CONFIG_PCI
+
+volatile u32* pci_config_address_reg = (volatile u32*)0xfdead000;
+volatile u32* pci_config_data_reg = (volatile u32*)0xfdead000;
+
+
+
+#define cfgaddr(dev, where) (((dev->bus->number & 0xff) << 0x10) |  \
+                             ((dev->devfn & 0xff) << 0x08) |        \
+                             (where & 0xfc))
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int pcimt_read_config_byte (struct pci_dev *dev,
+                                   int where, unsigned char *val)
+{
+        *pci_config_address_reg = cfgaddr(dev, where);
+	*val = (le32_to_cpu(*pci_config_data_reg) >> ((where&3)<<3)) & 0xff;
+	//printk("pci_read_byte 0x%x == 0x%x\n", where, *val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcimt_read_config_word (struct pci_dev *dev,
+                                   int where, unsigned short *val)
+{
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	*pci_config_address_reg = cfgaddr(dev, where);
+	*val = (le32_to_cpu(*pci_config_data_reg) >> ((where&3)<<3)) & 0xffff;
+	//printk("pci_read_word 0x%x == 0x%x\n", where, *val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcimt_read_config_dword (struct pci_dev *dev,
+                                    int where, unsigned int *val)
+{
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	*pci_config_address_reg = cfgaddr(dev, where);
+	*val = le32_to_cpu(*pci_config_data_reg);
+	//printk("pci_read_dword 0x%x == 0x%x\n", where, *val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcimt_write_config_byte (struct pci_dev *dev,
+                                    int where, unsigned char val)
+{
+	*pci_config_address_reg = cfgaddr(dev, where);
+	*(volatile u8 *)(((int)pci_config_data_reg) + (where & 3)) = val;
+	//printk("pci_write_byte 0x%x = 0x%x\n", where, val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcimt_write_config_word (struct pci_dev *dev,
+                                    int where, unsigned short val)
+{
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	*pci_config_address_reg = cfgaddr(dev, where);
+	*(volatile u16 *)(((int)pci_config_data_reg) + (where & 2)) = 
+                  le16_to_cpu(val);
+	//printk("pci_write_word 0x%x = 0x%x\n", where, val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcimt_write_config_dword (struct pci_dev *dev,
+                                     int where, unsigned int val)
+{
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	*pci_config_address_reg = cfgaddr(dev, where);
+	*pci_config_data_reg = le32_to_cpu(val);
+	//printk("pci_write_dword 0x%x = 0x%x\n", where, val);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+
+struct pci_ops hp_pci_ops = {
+	pcimt_read_config_byte,
+	pcimt_read_config_word,
+	pcimt_read_config_dword,
+	pcimt_write_config_byte,
+	pcimt_write_config_word,
+	pcimt_write_config_dword
+};
+
+
+struct pci_channel mips_pci_channels[] = {
+	{ &hp_pci_ops, &ioport_resource, &iomem_resource },
+	{ NULL, NULL, NULL }
+};
+
+unsigned __init int pcibios_assign_all_busses(void)
+{
+        return 1;
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
+
+void __init pcibios_fixup_irqs(void)
+{
+   struct pci_dev *dev;
+   int slot_num;
+
+
+   pci_for_each_dev(dev) {
+      slot_num = PCI_SLOT(dev->devfn);
+      switch(slot_num) {
+         case 2: dev->irq = 3;  break;
+         case 3: dev->irq = 4;  break;
+         case 4: dev->irq = 5;  break;
+         default: break;
+      }
+   }
+}
+
+#define IO_MEM_LOGICAL_START   0x3e000000
+#define IO_MEM_LOGICAL_END     0x3fefffff
+
+#define IO_PORT_LOGICAL_START  0x3ff00000
+#define IO_PORT_LOGICAL_END    0x3fffffff
+
+
+#define IO_MEM_VIRTUAL_OFFSET  0xb0000000
+#define IO_PORT_VIRTUAL_OFFSET 0xb0000000
+
+#define ONE_MEG   (1024 * 1024)
+
+void __init pci_setup(void)
+{
+   u32 pci_regs_base_offset = 0xfdead000;
+
+   switch(GetAsicId()) {
+      case AndrosAsic:   pci_regs_base_offset = 0xbff80000;   break;
+      case HarmonyAsic:  pci_regs_base_offset = 0xbff70000;   break;
+      default:
+         printk("ERROR: PCI does not support %s Asic\n", GetAsicName()); 
+	 while(1);
+         break; 
+   }
+
+   // set bus stat/command reg
+   // REVIST this setting may need vary depending on the hardware
+   *((volatile unsigned int*)(pci_regs_base_offset | 0x0004)) =  0x38000007;
+
+
+   iomem_resource.start =  IO_MEM_LOGICAL_START + IO_MEM_VIRTUAL_OFFSET;
+   iomem_resource.end =    IO_MEM_LOGICAL_END + IO_MEM_VIRTUAL_OFFSET;
+
+   ioport_resource.start = IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET;
+   ioport_resource.end =   IO_PORT_LOGICAL_END + IO_PORT_VIRTUAL_OFFSET;
+
+   // KLUDGE (mips_io_port_base is screwed up, we've got to work around it here)
+   // by letting both low (illegal) and high (legal) addresses appear in pci io space
+   ioport_resource.start = 0x0; 
+
+   set_io_port_base(IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET);
+
+   // map the PCI address space
+   // global map - all levels & processes can access
+   // except that the range is outside user space
+   // parameters: lo0, lo1, hi, pagemask
+   // lo indicates physical page, hi indicates virtual address
+   add_wired_entry((IO_MEM_LOGICAL_START >> 6) | 0x17, 
+                   ((IO_MEM_LOGICAL_START + (16 * ONE_MEG)) >> 6) | 0x17,
+                   0xee000000, PM_16M);
+
+
+   // These are used in pci r/w routines so need to preceed bus scan
+   pci_config_data_reg = (u32*) (((u32)mips_io_port_base) | 0xcfc);
+   pci_config_address_reg = (u32*) (((u32)pci_regs_base_offset) | 0xcf8);
+
+}
+
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+    int pos;
+    int bases;
+
+    printk("adjusting pci device: %s\n", dev->name);
+ 
+    switch (dev->hdr_type) {
+       case PCI_HEADER_TYPE_NORMAL: bases = 6; break;
+       case PCI_HEADER_TYPE_BRIDGE: bases = 2; break;
+       case PCI_HEADER_TYPE_CARDBUS: bases = 1; break;
+       default: bases = 0; break;
+    }
+    for (pos=0; pos < bases; pos++) {
+       struct resource* res = &dev->resource[pos];
+       if (res->start >= IO_MEM_LOGICAL_START && 
+           res->end <= IO_MEM_LOGICAL_END) {
+              res->start += IO_MEM_VIRTUAL_OFFSET;
+              res->end += IO_MEM_VIRTUAL_OFFSET;
+       }
+       if (res->start >= IO_PORT_LOGICAL_START && 
+           res->end <= IO_PORT_LOGICAL_END) {
+              res->start += IO_PORT_VIRTUAL_OFFSET;
+              res->end += IO_PORT_VIRTUAL_OFFSET;
+       }
+    }
+
+}
+
+
+#endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/setup.c linux/arch/mips/hp-lj/setup.c
--- linux.orig/arch/mips/hp-lj/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/setup.c	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,161 @@
+/*
+ * Setup pointers to hardware-dependent routines.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
+ */
+#include <linux/config.h>
+#include <linux/hdreg.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/ide.h>
+#include <linux/bootmem.h>
+#include <asm/mc146818rtc.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/hp-lj/asic.h>
+#include "utils.h"
+
+#ifdef CONFIG_REMOTE_DEBUG
+int remote_debug = 0;
+#endif
+
+const char *get_system_type(void)
+{
+	return "HP LaserJet";		/* But which exactly?  */
+}
+
+static void (*timer_interrupt_service)(int irq, void *dev_id, struct pt_regs * regs) = NULL;
+
+
+static void andros_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+   if (!(*((volatile unsigned int*)0xbfea0010) & 0x20))  // mask = pend & en
+      return;
+
+   /* clear timer interrupt */
+   {
+      unsigned int tmr = *((volatile unsigned int*)0xbfe90040);   // ctl bits
+      *((volatile unsigned int*)0xbfe90040) = tmr;     // write to ack
+      *((volatile unsigned int*)0xbfea000c) = 0x20;    // sys int ack
+   }
+
+   /* service interrupt */
+   timer_interrupt_service(irq, dev_id, regs);
+}
+
+static void harmony_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+   if (!(*((volatile unsigned int*)0xbff63000) & 0x01))
+      return;  // big sys     int reg, 01-timer  did it
+   if (!(*((volatile unsigned int*)0xbff610a4) & 0x01))
+      return;  // local small int reg, 01-timer0 did it
+
+   *((volatile unsigned int*)0xbff610a4) = 1;   // ack local timer0 bit
+   *((volatile unsigned int*)0xbff63000) = 1;   // ack global timer bit
+
+   /* service interrupt */
+   timer_interrupt_service(irq, dev_id, regs);
+}
+
+
+#define ASIC_IRQ_NUMBER  2
+
+
+static void __init hp_time_init(struct irqaction *irq)
+{
+    timer_interrupt_service = irq->handler;
+
+    if (GetAsicId() == AndrosAsic) {
+       //*((volatile unsigned int*)0xbfe90000) = 0x2f;  // set by bootloader to 0x20              // prescaler
+       *((volatile unsigned int*)0xbfe90040) = 0x21;    // 20-res of 1kHz,1-int ack                // control
+       *((volatile unsigned int*)0xbfe90048) = 0x09;    // 09-reload val                          // reload
+       *((volatile unsigned int*)0xbfe90044) = 0x09;    // 09-count val                           // count
+       *((volatile unsigned int*)0xbfe90040) = 0x2f;    // 8-int enable,4-reload en,2-count down en,1-int-ack
+
+       irq->handler = andros_timer_interrupt;
+       irq->flags |= SA_INTERRUPT | SA_SHIRQ;
+       printk("setting up timer in hp_time_init\n");
+       setup_irq(ASIC_IRQ_NUMBER, irq); 
+    
+       // enable timer interrupt
+       *((volatile unsigned int*)0xbfea0000) = 0x20;
+
+    } else if (GetAsicId() == HarmonyAsic) {
+
+        *((volatile unsigned int*)0xbff61000) = 99;  // prescaler, 100Mz sys clk
+        *((volatile unsigned int*)0xbff61028) = 0x09;  // reload reg
+        *((volatile unsigned int*)0xbff61024) = 0x09;  // count reg
+        *((volatile unsigned int*)0xbff61020) = 0x0b;  // 80-1khz res on timer, 2 reload en, 1 - count down en
+
+        irq->handler = harmony_timer_interrupt;
+        irq->flags |= SA_INTERRUPT | SA_SHIRQ;
+        setup_irq(ASIC_IRQ_NUMBER, irq);
+
+        *((volatile unsigned int*)0xbff610a0) |= 1;    // turn on timer0
+
+    } else if (GetAsicId() == UnknownAsic) 
+        printk("Unknown asic in hp_time_init()\n");
+    else
+        printk("Unsupported asic in hp_time_init()\n");
+}
+
+
+static void hplj_restart(void)
+{
+   if (GetAsicId() == AndrosAsic) 
+       *((volatile unsigned int *) 0xbfe900c0) = 0;
+
+
+    if (GetAsicId() == HarmonyAsic)
+        *((volatile unsigned int *) 0xbff62030) = 0;
+
+   printk("Restart Failed ... halting instead\n");
+   while(1);
+}
+
+static void hplj_halt(void)
+{
+   while(1);
+}
+
+
+void __init hp_setup(void)
+{
+#ifdef CONFIG_PCI
+   extern void pci_setup(void);
+   pci_setup();
+#endif
+
+#ifdef CONFIG_IDE
+   {
+      extern struct ide_ops std_ide_ops;
+      ide_ops = &std_ide_ops;
+   }
+#endif
+
+   _machine_restart =(void (*)(char *)) hplj_restart;
+   _machine_halt = hplj_halt;
+   _machine_power_off = hplj_halt;
+
+   board_timer_setup = hp_time_init;
+
+#ifdef CONFIG_REMOTE_DEBUG
+   {
+      extern char CommandLine[];
+      remote_debug = (strstr(CommandLine, "kgdb") != NULL);
+   }
+#endif
+
+   printk("HP SETUP\n");
+}
+
+int __init page_is_ram(unsigned long pagenr)
+{
+	return 1;
+}
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/utils.c linux/arch/mips/hp-lj/utils.c
--- linux.orig/arch/mips/hp-lj/utils.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/utils.c	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,69 @@
+/*
+ *
+ *
+ *
+ *
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include "utils.h"
+
+
+#define  miu_chan_cfg(x)      ((volatile unsigned long  *)(0xbff40000+x*4))       /* for andros */
+
+int mbsize[8] = {1,2,4,8,16,32,64,128};
+
+unsigned long get_mem_avail(void) {
+
+    unsigned long  cfg[10],i,total_mem=0;
+
+	for(i=0;i<10;i++)  
+		cfg[i] = *miu_chan_cfg(i); 
+
+	for(i=0;i<10;i++){
+		if(cfg[i]==0x1fc160c2) continue;                           // skip empties 
+		if(   ( (cfg[i]>>12) & 0xf )   <=  0xb ) continue;         // skip roms
+        total_mem += mbsize[(cfg[i]>>16)&0x7] *1024*1024;
+	}
+    return total_mem;
+}
+
+
+
+
+static ulong* buffer_ptr = NULL;
+static ulong buffer_size = 0;
+
+ulong* get_reserved_buffer(void) {return KSEG0ADDR(buffer_ptr);}
+ulong* get_reserved_buffer_virtual(void) {return (ulong*)ReservedMemVirtualAddr;}
+ulong get_reserved_buffer_size(void) {return buffer_size;}
+
+#define MIN_GEN_MEM (4 << 20)
+
+	
+void  reserve_buffer(const char* cl, ulong base_mem) 
+{
+	char* pos = strstr(cl, "reserved_buffer=");
+ 	if (pos) {
+		buffer_size = simple_strtol(pos+strlen("reserved_buffer="), 
+					    0, 10);
+		buffer_size <<= 20;
+		if (buffer_size + MIN_GEN_MEM > base_mem)
+			buffer_size = base_mem - MIN_GEN_MEM;
+		if (buffer_size > 0) 
+			buffer_ptr = (ulong*)(base_mem - buffer_size);
+		else 
+			buffer_size = 0;
+	}
+}
+
+
+
+EXPORT_SYMBOL(get_reserved_buffer);
+EXPORT_SYMBOL(get_reserved_buffer_virtual);
+EXPORT_SYMBOL(get_reserved_buffer_size);
+
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/hp-lj/utils.h linux/arch/mips/hp-lj/utils.h
--- linux.orig/arch/mips/hp-lj/utils.h	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/hp-lj/utils.h	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,19 @@
+/*
+ *
+ *
+ *
+ */
+
+#include <linux/types.h>
+
+#define ReservedMemVirtualAddr  0x50000000
+
+unsigned long get_mem_avail(void);
+
+ulong* get_reserved_buffer(void);
+ulong* get_reserved_buffer_virtual(void);
+ulong get_reserved_buffer_size(void);
+
+void  reserve_buffer(const char* cl, ulong base_mem);
+
+
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/Makefile linux/arch/mips/ite-boards/generic/Makefile
--- linux.orig/arch/mips/ite-boards/generic/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/Makefile	2002-08-01 06:42:34.000000000 +0000
@@ -21,16 +21,8 @@
 
 obj-y := it8172_rtc.o it8172_setup.o irq.o int-handler.o pmon_prom.o time.o lpc.o puts.o reset.o
 
-ifdef CONFIG_PCI
-obj-y += it8172_pci.o
-endif
-
-ifdef CONFIG_IT8172_CIR
-obj-y += it8172_cir.o 
-endif
-
-ifdef CONFIG_REMOTE_DEBUG
- obj-y += dbg_io.o             
-endif
+obj-$(CONFIG_PCI) += it8172_pci.o
+obj-$(CONFIG_IT8172_CIR) += it8172_cir.o 
+obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o             
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/int-handler.S linux/arch/mips/ite-boards/generic/int-handler.S
--- linux.orig/arch/mips/ite-boards/generic/int-handler.S	2001-04-14 03:26:07.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/int-handler.S	2002-08-01 06:42:35.000000000 +0000
@@ -27,7 +27,7 @@
         andi    a0, t0, CAUSEF_IP7
         beq     a0, zero, 1f
         move    a0, sp
-        jal     mips_timer_interrupt
+        jal     local_timer_interrupt
 	j	ret_from_irq
         nop
         
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/irq.c linux/arch/mips/ite-boards/generic/irq.c
--- linux.orig/arch/mips/ite-boards/generic/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/irq.c	2002-08-01 06:42:45.000000000 +0000
@@ -72,17 +72,17 @@
 #define EXT_IRQ0_TO_IP 2 /* IP 2 */
 #define EXT_IRQ5_TO_IP 7 /* IP 7 */
 
-extern void set_debug_traps(void);
-extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
-extern asmlinkage void it8172_IRQ(void);
+#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
+
 unsigned int local_bh_count[NR_CPUS];
 unsigned int local_irq_count[NR_CPUS];
-unsigned long spurious_count = 0;
-irq_desc_t irq_desc[NR_IRQS];
-irq_desc_t *irq_desc_base=&irq_desc[0];
 void disable_it8172_irq(unsigned int irq_nr);
 void enable_it8172_irq(unsigned int irq_nr);
 
+extern void set_debug_traps(void);
+extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
+extern asmlinkage void it8172_IRQ(void);
+
 struct it8172_intc_regs volatile *it8172_hw0_icregs
 	= (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
 
@@ -105,7 +105,7 @@
         modify_cp0_intmask(0, irq_nr);
 }
 
-void disable_irq(unsigned int irq_nr)
+void local_disable_irq(unsigned int irq_nr)
 {
         unsigned long flags;
 
@@ -114,7 +114,7 @@
         restore_flags(flags);
 }
 
-void enable_irq(unsigned int irq_nr)
+void local_enable_irq(unsigned int irq_nr)
 {
 	unsigned long flags;
 
@@ -130,63 +130,70 @@
 
 	if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
 		/* LPC interrupt */
-		DPRINTK("disable, before lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
-		it8172_hw0_icregs->lpc_mask |= (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
-		DPRINTK("disable, after lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
+		DPRINTK("DB lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
+		it8172_hw0_icregs->lpc_mask |= 
+			(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
+		DPRINTK("DA lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
 	}
 	else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
 		/* Local Bus interrupt */
-		DPRINTK("before lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
-		it8172_hw0_icregs->lb_mask |= (1 << (irq_nr - IT8172_LB_IRQ_BASE));
-		DPRINTK("after lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
+		DPRINTK("DB lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
+		it8172_hw0_icregs->lb_mask |= 
+			(1 << (irq_nr - IT8172_LB_IRQ_BASE));
+		DPRINTK("DA lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
 	}
 	else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
 		/* PCI and other interrupts */
-		DPRINTK("before pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
-		it8172_hw0_icregs->pci_mask |= (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
-		DPRINTK("after pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
+		DPRINTK("DB pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
+		it8172_hw0_icregs->pci_mask |= 
+			(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
+		DPRINTK("DA pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
 	}
 	else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
 		/* NMI interrupts */
-		DPRINTK("before nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
-		it8172_hw0_icregs->nmi_mask |= (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
-		DPRINTK("after nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
+		DPRINTK("DB nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
+		it8172_hw0_icregs->nmi_mask |= 
+			(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
+		DPRINTK("DA nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
 	}
 	else {
-		panic("disable_it8172_irq: bad irq %d\n", irq_nr);
+		panic("disable_it8172_irq: bad irq %d", irq_nr);
 	}
 }
 
-
 void enable_it8172_irq(unsigned int irq_nr)
 {
 	DPRINTK("enable_it8172_irq %d\n", irq_nr);
 	if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
 		/* LPC interrupt */
-		DPRINTK("enable, before lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
-		it8172_hw0_icregs->lpc_mask &= ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
-		DPRINTK("enable, after lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
+		DPRINTK("EB before lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
+		it8172_hw0_icregs->lpc_mask &= 
+			~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
+		DPRINTK("EA after lpc_mask  %x\n", it8172_hw0_icregs->lpc_mask);
 	}
 	else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
 		/* Local Bus interrupt */
-		DPRINTK("before lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
-		it8172_hw0_icregs->lb_mask &= ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
-		DPRINTK("after lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
+		DPRINTK("EB lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
+		it8172_hw0_icregs->lb_mask &= 
+			~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
+		DPRINTK("EA lb_mask  %x\n", it8172_hw0_icregs->lb_mask);
 	}
 	else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
 		/* PCI and other interrupts */
-		DPRINTK("before pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
-		it8172_hw0_icregs->pci_mask &= ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
-		DPRINTK("after pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
+		DPRINTK("EB pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
+		it8172_hw0_icregs->pci_mask &= 
+			~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
+		DPRINTK("EA pci_mask  %x\n", it8172_hw0_icregs->pci_mask);
 	}
 	else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
 		/* NMI interrupts */
-		DPRINTK("before nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
-		it8172_hw0_icregs->nmi_mask &= ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
-		DPRINTK("after nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
+		DPRINTK("EB nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
+		it8172_hw0_icregs->nmi_mask &= 
+			~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
+		DPRINTK("EA nmi_mask  %x\n", it8172_hw0_icregs->nmi_mask);
 	}
 	else {
-		panic("enable_it8172_irq: bad irq %d\n", irq_nr);
+		panic("enable_it8172_irq: bad irq %d", irq_nr);
 	}
 }
 
@@ -217,160 +224,25 @@
 };
 
 
-int get_irq_list(char *buf)
-{
-        int i, len = 0, j;
-        struct irqaction * action;
-
-        len += sprintf(buf+len, "           ");
-        for (j=0; j<smp_num_cpus; j++)
-                len += sprintf(buf+len, "CPU%d       ",j);
-        *(char *)(buf+len++) = '\n';
-
-        for (i = 0 ; i < NR_IRQS ; i++) {
-                action = irq_desc[i].action;
-                if ( !action || !action->handler )
-                        continue;
-                len += sprintf(buf+len, "%3d: ", i);		
-                len += sprintf(buf+len, "%10u ", kstat_irqs(i));
-                if ( irq_desc[i].handler )		
-                        len += sprintf(buf+len, " %s ", irq_desc[i].handler->typename );
-                else
-                        len += sprintf(buf+len, "  None      ");
-                len += sprintf(buf+len, "    %s",action->name);
-                for (action=action->next; action; action = action->next) {
-                        len += sprintf(buf+len, ", %s", action->name);
-                }
-                len += sprintf(buf+len, "\n");
-        }
-        len += sprintf(buf+len, "BAD: %10lu\n", spurious_count);
-        return len;
-}
-
-asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
-{
-	struct irqaction *action;
-	int cpu;
-
-	cpu = smp_processor_id();
-	irq_enter(cpu, irq);
-
-	kstat.irqs[cpu][irq]++;
-#if 0
-	if (irq_desc[irq].handler && irq_desc[irq].handler->ack) {
-	//	printk("invoking ack handler\n");
-		irq_desc[irq].handler->ack(irq);
-	}
-#endif
-
-	action = irq_desc[irq].action;
-
-	if (action && action->handler)
-	{
-		//mask_irq(1<<irq);
-		//printk("action->handler %x\n", action->handler);
-		disable_it8172_irq(irq);
-		//if (!(action->flags & SA_INTERRUPT)) __sti(); /* reenable ints */
-		do { 
-			action->handler(irq, action->dev_id, regs);
-			action = action->next;
-		} while ( action );
-		//__cli(); /* disable ints */
-		if (irq_desc[irq].handler)
-		{
-		}
-		//unmask_irq(1<<irq);
-		enable_it8172_irq(irq);
-	}
-	else
-	{
-		spurious_count++;
-		printk("Unhandled interrupt %d, cause %x, disabled\n", 
-				(unsigned)irq, (unsigned)regs->cp0_cause);
-		disable_it8172_irq(irq);
-	}
-	irq_exit(cpu, irq);
-}
-
-int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *),
-	unsigned long irqflags, const char * devname, void *dev_id)
-{
-        struct irqaction *old, **p, *action;
-        unsigned long flags;
+static void enable_none(unsigned int irq) { }
+static unsigned int startup_none(unsigned int irq) { return 0; }
+static void disable_none(unsigned int irq) { }
+static void ack_none(unsigned int irq) { }
+
+/* startup is the same as "enable", shutdown is same as "disable" */
+#define shutdown_none	disable_none
+#define end_none	enable_none
+
+static struct hw_interrupt_type cp0_irq_type = {
+	"CP0 Count",
+	startup_none,
+	shutdown_none,
+	enable_none,
+	disable_none,
+	ack_none,
+	end_none
+};
 
-        /*
-         * IP0 and IP1 are software interrupts. IP7 is typically the timer interrupt.
-	 *
-	 * The ITE QED-4N-S01B board has one single interrupt line going from
-	 * the system controller to the CPU. It's connected to the CPU external
-	 * irq pin 1, which is IP2.  The interrupt numbers are listed in it8172_int.h;
-	 * the ISA interrupts are numbered from 0 to 15, and the rest go from
-	 * there.  
-         */
-
-	//printk("request_irq: %d handler %x\n", irq, handler);
-        if (irq >= NR_IRQS) 
-                return -EINVAL;
-
-        if (!handler)
-        {
-                /* Free */
-                for (p = &irq_desc[irq].action; (action = *p) != NULL; p = &action->next)
-                {
-                        /* Found it - now free it */
-                        save_flags(flags);
-                        cli();
-                        *p = action->next;
-			disable_it8172_irq(irq);
-                        restore_flags(flags);
-                        kfree(action);
-                        return 0;
-                }
-                return -ENOENT;
-        }
-        
-        action = (struct irqaction *)
-                kmalloc(sizeof(struct irqaction), GFP_KERNEL);
-        if (!action)
-                return -ENOMEM;
-        memset(action, 0, sizeof(struct irqaction));
-        
-        save_flags(flags);
-        cli();
-        
-        action->handler = handler;
-        action->flags = irqflags;					
-        action->mask = 0;
-        action->name = devname;
-        action->dev_id = dev_id;
-        action->next = NULL;
-
-        p = &irq_desc[irq].action;
-        
-        if ((old = *p) != NULL) {
-                /* Can't share interrupts unless both agree to */
-                if (!(old->flags & action->flags & SA_SHIRQ))
-                        return -EBUSY;
-                /* add new interrupt at end of irq queue */
-                do {
-                        p = &old->next;
-                        old = *p;
-                } while (old);
-        }
-        *p = action;
-	enable_it8172_irq(irq);
-        restore_flags(flags);	
-#if 0
-	printk("request_irq: status %x cause %x\n", 
-			read_32bit_cp0_register(CP0_STATUS), read_32bit_cp0_register(CP0_CAUSE));
-#endif
-        return 0;
-}
-		
-void free_irq(unsigned int irq, void *dev_id)
-{
-        request_irq(irq, NULL, 0, NULL, dev_id);
-}
 
 void enable_cpu_timer(void)
 {
@@ -381,26 +253,17 @@
         restore_flags(flags);
 }
 
-unsigned long probe_irq_on (void)
-{
-        return 0;
-}
-
-int probe_irq_off (unsigned long irqs)
-{
-        return 0;
-}
-
 
 void __init init_IRQ(void)
 {
 	int i;
         unsigned long flags;
 
-
         memset(irq_desc, 0, sizeof(irq_desc));
         set_except_vector(0, it8172_IRQ);
 
+	init_generic_irq();
+
 	/* mask all interrupts */
 	it8172_hw0_icregs->lb_mask  = 0xffff;
 	it8172_hw0_icregs->lpc_mask = 0xffff;
@@ -431,20 +294,11 @@
 		~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
 #endif
 
-	for (i = 0; i <= IT8172_INT_END; i++) {
-		irq_desc[i].status	= IRQ_DISABLED;
-		irq_desc[i].action	= 0;
-		irq_desc[i].depth	= 1;
-		irq_desc[i].handler	= &it8172_irq_type;
+	for (i = 0; i <= IT8172_LAST_IRQ; i++) {
+		irq_desc[i].handler = &it8172_irq_type;
 	}
-
-	/*
-	 * Enable external int line 2
-	 * All ITE interrupts are masked for now.
-	 */
-        save_and_cli(flags);
-	unmask_irq(1<<EXT_IRQ0_TO_IP);
-        restore_flags(flags);
+	irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
+	set_cp0_status(ALLINTS_NOTIMER);
 
 #ifdef CONFIG_REMOTE_DEBUG
 	/* If local serial I/O used for debug port, enter kgdb at once */
@@ -473,16 +327,16 @@
 void it8172_hw0_irqdispatch(struct pt_regs *regs)
 {
 	int irq;
-	unsigned short intstatus, status;
+	unsigned short intstatus = 0, status = 0;
 
 	intstatus = it8172_hw0_icregs->intstatus;
 	if (intstatus & 0x8) {
-		panic("Got NMI interrupt\n");
+		panic("Got NMI interrupt");
 	}
 	else if (intstatus & 0x4) {
 		/* PCI interrupt */
 		irq = 0;
-		status = it8172_hw0_icregs->pci_req;
+		status |= it8172_hw0_icregs->pci_req;
 		while (!(status & 0x1)) {
 			irq++;
 			status >>= 1;
@@ -493,7 +347,7 @@
 	else if (intstatus & 0x1) {
 		/* Local Bus interrupt */
 		irq = 0;
-		status = it8172_hw0_icregs->lb_req;
+		status |= it8172_hw0_icregs->lb_req;
 		while (!(status & 0x1)) {
 			irq++;
 			status >>= 1;
@@ -507,7 +361,7 @@
 		 * we could lose an interrupt this way because
 		 * we acknowledge all ints at onces. Revisit.
 		 */
-		status = it8172_hw0_icregs->lpc_req;
+		status |= it8172_hw0_icregs->lpc_req;
 		it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
 		irq = 0;
 		while (!(status & 0x1)) {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/it8172_pci.c linux/arch/mips/ite-boards/generic/it8172_pci.c
--- linux.orig/arch/mips/ite-boards/generic/it8172_pci.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/it8172_pci.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,4 +1,5 @@
 /*
+ *
  * BRIEF MODULE DESCRIPTION
  *	IT8172 system controller specific pci support.
  *
@@ -35,6 +36,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include <asm/pci_channel.h>
 #include <asm/it8172/it8172.h>
 #include <asm/it8172/it8172_pci.h>
 
@@ -42,7 +44,47 @@
 #define PCI_ACCESS_WRITE 1
 
 #undef DEBUG
-#undef DEBUG_CONFIG_CYCLES
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+static struct resource pci_mem_resource_1;
+
+static struct resource pci_io_resource = {
+	"io pci IO space", 
+	0x14000000,
+	0x17FFFFFF,
+	IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource_0 = {
+	"ext pci memory space 0/1", 
+	0x0C000000,
+	0x13FFFFFF,
+	IORESOURCE_MEM,
+	&pci_mem_resource_0,
+	NULL,
+	&pci_mem_resource_1
+};
+
+static struct resource pci_mem_resource_1 = {
+	"ext pci memory space 2/3", 
+	0x1A000000,
+	0x1FBFFFFF,
+	IORESOURCE_MEM,
+	&pci_mem_resource_0,
+	NULL,
+	NULL
+};
+
+extern struct pci_ops it8172_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+	{ &it8172_pci_ops, &pci_io_resource, &pci_mem_resource_0, 0, 0xff },
+	{ NULL, NULL, NULL, NULL, NULL}
+};
 
 static int
 it8172_pcibios_config_access(unsigned char access_type, struct pci_dev *dev,
@@ -54,12 +96,9 @@
 	unsigned char bus = dev->bus->number;
 	unsigned char dev_fn = dev->devfn;
 
-#ifdef DEBUG_CONFIG_CYCLES
-	printk("it config: type %d dev %x bus %d dev_fn %x data %x\n",
+	DBG("it config: type %d dev %x bus %d dev_fn %x data %x\n",
 			access_type, dev, bus, dev_fn, *data);
 
-#endif
-
 	/* Setup address */
 	IT_WRITE(IT_CONFADDR, (bus << IT_BUSNUM_SHF) | 
 			(dev_fn << IT_FUNCNUM_SHF) | (where & ~0x3));
@@ -86,7 +125,7 @@
  * read/write a 32bit word and mask/modify the data we actually want.
  */
 static int
-it8172_pcibios_read_config_byte (struct pci_dev *dev, int where, u8 *val)
+read_config_byte (struct pci_dev *dev, int where, u8 *val)
 {
 	u32 data = 0;
 
@@ -94,17 +133,15 @@
 		return -1;
 
 	*val = (data >> ((where & 3) << 3)) & 0xff;
-#ifdef DEBUG
-        printk("cfg read byte: bus %d dev_fn %x where %x: val %x\n", 
+        DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n", 
                 dev->bus->number, dev->devfn, where, *val);
-#endif
 
 	return PCIBIOS_SUCCESSFUL;
 }
 
 
 static int
-it8172_pcibios_read_config_word (struct pci_dev *dev, int where, u16 *val)
+read_config_word (struct pci_dev *dev, int where, u16 *val)
 {
 	u32 data = 0;
 
@@ -115,16 +152,14 @@
 	       return -1;
 
 	*val = (data >> ((where & 3) << 3)) & 0xffff;
-#ifdef DEBUG
-        printk("cfg read word: bus %d dev_fn %x where %x: val %x\n", 
+        DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", 
                 dev->bus->number, dev->devfn, where, *val);
-#endif
 
 	return PCIBIOS_SUCCESSFUL;
 }
 
 static int
-it8172_pcibios_read_config_dword (struct pci_dev *dev, int where, u32 *val)
+read_config_dword (struct pci_dev *dev, int where, u32 *val)
 {
 	u32 data = 0;
 
@@ -135,17 +170,15 @@
 		return -1;
 
 	*val = data;
-#ifdef DEBUG
-        printk("cfg read dword: bus %d dev_fn %x where %x: val %x\n", 
+        DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n", 
                 dev->bus->number, dev->devfn, where, *val);
-#endif
 
 	return PCIBIOS_SUCCESSFUL;
 }
 
 
 static int
-it8172_pcibios_write_config_byte (struct pci_dev *dev, int where, u8 val)
+write_config_byte (struct pci_dev *dev, int where, u8 val)
 {
 	u32 data = 0;
        
@@ -162,7 +195,7 @@
 }
 
 static int
-it8172_pcibios_write_config_word (struct pci_dev *dev, int where, u16 val)
+write_config_word (struct pci_dev *dev, int where, u16 val)
 {
         u32 data = 0;
 
@@ -183,7 +216,7 @@
 }
 
 static int
-it8172_pcibios_write_config_dword(struct pci_dev *dev, int where, u32 val)
+write_config_dword(struct pci_dev *dev, int where, u32 val)
 {
 	if (where & 3)
 		return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -195,87 +228,16 @@
 }
 
 struct pci_ops it8172_pci_ops = {
-	it8172_pcibios_read_config_byte,
-        it8172_pcibios_read_config_word,
-	it8172_pcibios_read_config_dword,
-	it8172_pcibios_write_config_byte,
-	it8172_pcibios_write_config_word,
-	it8172_pcibios_write_config_dword
+	read_config_byte,
+        read_config_word,
+	read_config_dword,
+	write_config_byte,
+	write_config_word,
+	write_config_dword
 };
 
-void __init pcibios_init(void)
-{
-
-	printk("PCI: Probing PCI hardware on host bus 0.\n");
-	pci_scan_bus(0, &it8172_pci_ops, NULL);
-}
-
-int __init
-pcibios_enable_device(struct pci_dev *dev)
-{
-	u16 cmd, old_cmd;
-	int idx;
-	struct resource *r;
-
-	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-	old_cmd = cmd;
-	for(idx=0; idx<6; idx++) {
-		r = &dev->resource[idx];
-		if (!r->start && r->end) {
-			printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
-			return -EINVAL;
-		}
-		if (r->flags & IORESOURCE_IO)
-			cmd |= PCI_COMMAND_IO;
-		if (r->flags & IORESOURCE_MEM)
-			cmd |= PCI_COMMAND_MEMORY;
-	}
-	if (dev->resource[PCI_ROM_RESOURCE].start)
-		cmd |= PCI_COMMAND_MEMORY;
-	if (cmd != old_cmd) {
-		printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
-		pci_write_config_word(dev, PCI_COMMAND, cmd);
-	}
-	return 0;
-}
-
-
-void __init
-pcibios_align_resource(void *data, struct resource *res, unsigned long size)
-{
-    printk("pcibios_align_resource\n");
-}
-
-char * __init
-pcibios_setup(char *str)
-{
-	/* Nothing to do for now.  */
-
-	return str;
-}
-
-void __init
-pcibios_update_resource(struct pci_dev *dev, struct resource *root,
-                        struct resource *res, int resource)
-{
-	unsigned long where, size;
-	u32 reg;
-
-	where = PCI_BASE_ADDRESS_0 + (resource * 4);
-	size = res->end - res->start;
-	pci_read_config_dword(dev, where, &reg);
-	reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
-	pci_write_config_dword(dev, where, reg);
-}
-
-void __init pcibios_fixup_bus(struct pci_bus *b)
-{
-	//printk("pcibios_fixup_bus\n");
-}
-
 unsigned __init int pcibios_assign_all_busses(void)
 {
-	return 1;
+       return 1;
 }
-
 #endif /* CONFIG_PCI */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/it8172_setup.c linux/arch/mips/ite-boards/generic/it8172_setup.c
--- linux.orig/arch/mips/ite-boards/generic/it8172_setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/it8172_setup.c	2002-08-01 06:42:41.000000000 +0000
@@ -53,7 +53,6 @@
 
 extern struct rtc_ops it8172_rtc_ops;
 extern struct resource ioport_resource;
-extern unsigned long mips_io_port_base;
 #ifdef CONFIG_BLK_DEV_IDE
 extern struct ide_ops std_ide_ops;
 extern struct ide_ops *ide_ops;
@@ -70,6 +69,14 @@
 extern void it8172_halt(void);
 extern void it8172_power_off(void);
 
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern unsigned long (*rtc_get_time)(void);
+extern int (*rtc_set_time)(unsigned long);
+extern void it8172_time_init(void);
+extern void it8172_timer_setup(struct irqaction *irq);
+extern unsigned long it8172_rtc_get_time(void);
+
 #ifdef CONFIG_IT8172_REVC
 struct {
     struct resource ram;
@@ -116,6 +123,7 @@
 {
 	unsigned short dsr;
 	char *argptr;
+	u32 it_ver;
 
 	argptr = prom_getcmdline();
 #ifdef CONFIG_SERIAL_CONSOLE
@@ -128,6 +136,11 @@
 	clear_cp0_status(ST0_FR);
 	rtc_ops = &it8172_rtc_ops;
 
+	board_time_init = it8172_time_init;
+	board_timer_setup = it8172_timer_setup;
+	rtc_get_time = it8172_rtc_get_time;
+	//rtc_set_time = it8172_rtc_set_time;
+
 	_machine_restart = it8172_restart;
 	_machine_halt = it8172_halt;
 	_machine_power_off = it8172_power_off;
@@ -137,7 +150,7 @@
 	*
 	* revisit this area.
 	*/
-	mips_io_port_base = KSEG1;
+	set_io_port_base(KSEG1);
 	ioport_resource.start = it8172_resources.pci_io.start;
 	ioport_resource.end = it8172_resources.pci_io.end;
 #ifdef CONFIG_IT8172_REVC
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/pmon_prom.c linux/arch/mips/ite-boards/generic/pmon_prom.c
--- linux.orig/arch/mips/ite-boards/generic/pmon_prom.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/pmon_prom.c	2002-08-01 06:42:27.000000000 +0000
@@ -44,7 +44,7 @@
 
 /* #define DEBUG_CMDLINE */
 
-char arcs_cmdline[COMMAND_LINE_SIZE];
+char arcs_cmdline[CL_SIZE];
 extern int prom_argc;
 extern char **prom_argv, **prom_envp;
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/generic/time.c linux/arch/mips/ite-boards/generic/time.c
--- linux.orig/arch/mips/ite-boards/generic/time.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/generic/time.c	2002-08-01 06:42:41.000000000 +0000
@@ -28,135 +28,18 @@
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
 #include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/timex.h>
 
 #include <asm/mipsregs.h>
 #include <asm/ptrace.h>
 #include <asm/it8172/it8172_int.h>
+#include <asm/debug.h>
 
-#include <linux/mc146818rtc.h>
-#include <linux/timex.h>
-
-extern void enable_cpu_timer(void);
-extern volatile unsigned long wall_jiffies;
-extern rwlock_t xtime_lock;
-
-unsigned long missed_heart_beats = 0;
-static long last_rtc_update = 0;
 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
 static unsigned long r4k_cur;    /* What counter should be at next timer irq */
-static unsigned int timer_tick_count=0;
-
-static inline void ack_r4ktimer(unsigned long newval)
-{
-	write_32bit_cp0_register(CP0_COMPARE, newval);
-}
-
-
-/*
- * In order to set the CMOS clock precisely, set_rtc_mmss has to be
- * called 500 ms after the second nowtime has started, because when
- * nowtime is written into the registers of the CMOS clock, it will
- * jump to the next second precisely 500 ms later. Check the Motorola
- * MC146818A or Dallas DS12887 data sheet for details.
- *
- * BUG: This routine does not handle hour overflow properly; it just
- *      sets the minutes. Usually you won't notice until after reboot!
- */
-static int set_rtc_mmss(unsigned long nowtime)
-{
-	int retval = 0;
-	int real_seconds, real_minutes, cmos_minutes;
-	unsigned char save_control, save_freq_select;
-
-	save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
-	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
-
-	save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
-	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
-
-	cmos_minutes = CMOS_READ(RTC_MINUTES);
-
-	/*
-	 * since we're only adjusting minutes and seconds,
-	 * don't interfere with hour overflow. This avoids
-	 * messing with unknown time zones but requires your
-	 * RTC not to be off by more than 15 minutes
-	 */
-	real_seconds = nowtime % 60;
-	real_minutes = nowtime / 60;
-	if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
-		real_minutes += 30;		/* correct for half hour time zone */
-	real_minutes %= 60;
-
-	if (abs(real_minutes - cmos_minutes) < 30) {
-		CMOS_WRITE(real_seconds,RTC_SECONDS);
-		CMOS_WRITE(real_minutes,RTC_MINUTES);
-	} else {
-		printk(KERN_WARNING
-		       "set_rtc_mmss: can't update from %d to %d\n",
-		       cmos_minutes, real_minutes);
- 		retval = -1;
-	}
-
-	/* The following flags have to be released exactly in this order,
-	 * otherwise the DS12887 (popular MC146818A clone with integrated
-	 * battery and quartz) will not reset the oscillator and will not
-	 * update precisely 500 ms later. You won't find this mentioned in
-	 * the Dallas Semiconductor data sheets, but who believes data
-	 * sheets anyway ...                           -- Markus Kuhn
-	 */
-	CMOS_WRITE(save_control, RTC_CONTROL);
-	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
-
-	return retval;
-}
-
-
-/*
- * There are a lot of conceptually broken versions of the MIPS timer interrupt
- * handler floating around.  This one is rather different, but the algorithm
- * is provably more robust.
- */
-void mips_timer_interrupt(struct pt_regs *regs)
-{
-	if (r4k_offset == 0)
-		goto null;
-
-	do {
-		kstat.irqs[0][MIPS_CPU_TIMER_IRQ]++;
-		do_timer(regs);
-
-		/* Historical comment/code:
- 		 * RTC time of day s updated approx. every 11 
- 		 * minutes.  Because of how the numbers work out 
- 		 * we need to make absolutely sure we do this update
- 		 * within 500ms before the * next second starts, 
- 		 * thus the following code.
- 		 */
-		read_lock(&xtime_lock);
-		if ((time_status & STA_UNSYNC) == 0 
-		    && xtime.tv_sec > last_rtc_update + 660 
-		    && xtime.tv_usec >= 500000 - (tick >> 1) 
-		    && xtime.tv_usec <= 500000 + (tick >> 1))
-			if (set_rtc_mmss(xtime.tv_sec) == 0)
-				last_rtc_update = xtime.tv_sec;
-			else {
-				/* do it again in 60 s */
-	    			last_rtc_update = xtime.tv_sec - 600; 
-			}
-		read_unlock(&xtime_lock);
-
-		r4k_cur += r4k_offset;
-		ack_r4ktimer(r4k_cur);
-
-	} while (((unsigned long)read_32bit_cp0_register(CP0_COUNT)
-	         - r4k_cur) < 0x7fffffff);
-
-	return;
-
-null:
-	ack_r4ktimer(0);
-}
+extern unsigned int mips_counter_frequency;
+extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
 
 /* 
  * Figure out the r4k offset, the amount to increment the compare
@@ -165,7 +48,6 @@
  */
 static unsigned long __init cal_r4koff(void)
 {
-	unsigned long count;
 	unsigned int flags;
 
 	__save_and_cli(flags);
@@ -181,15 +63,15 @@
 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 
-	count = read_32bit_cp0_register(CP0_COUNT);
+	mips_counter_frequency = read_32bit_cp0_register(CP0_COUNT);
 
 	/* restore interrupts */
 	__restore_flags(flags);
 		
-	return (count / HZ);
+	return (mips_counter_frequency / HZ);
 }
 
-static unsigned long __init get_mips_time(void)
+unsigned long it8172_rtc_get_time(void)
 {
 	unsigned int year, mon, day, hour, min, sec;
 	unsigned char save_control;
@@ -224,10 +106,11 @@
 	return mktime(year, mon, day, hour, min, sec);
 }
 
-void __init time_init(void)
+void __init it8172_time_init(void)
 {
         unsigned int est_freq, flags;
 
+	__save_and_cli(flags);
         /* Set Data mode - binary. */ 
         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 
@@ -240,140 +123,25 @@
 	est_freq -= est_freq%10000;
 	printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 
 	       (est_freq%1000000)*100/1000000);
-	r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
-
-	write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
-
-	enable_cpu_timer();
-
-	/* Read time from the RTC chipset. */
-	write_lock_irqsave (&xtime_lock, flags);
-	xtime.tv_sec = get_mips_time();
-	xtime.tv_usec = 0;
-	write_unlock_irqrestore(&xtime_lock, flags);
-}
-
-/* This is for machines which generate the exact clock. */
-#define USECS_PER_JIFFY (1000000/HZ)
-
-/* Cycle counter value at the previous timer interrupt.. */
-
-static unsigned int timerhi = 0, timerlo = 0;
-
-/*
- * FIXME: Does playing with the RP bit in c0_status interfere with this code?
- */
-static unsigned long do_fast_gettimeoffset(void)
-{
-	u32 count;
-	unsigned long res, tmp;
-
-	/* Last jiffy when do_fast_gettimeoffset() was called. */
-	static unsigned long last_jiffies=0;
-	unsigned long quotient;
-
-	/*
-	 * Cached "1/(clocks per usec)*2^32" value.
-	 * It has to be recalculated once each jiffy.
-	 */
-	static unsigned long cached_quotient=0;
-
-	tmp = jiffies;
-
-	quotient = cached_quotient;
-
-	if (tmp && last_jiffies != tmp) {
-		last_jiffies = tmp;
-		__asm__(".set\tnoreorder\n\t"
-			".set\tnoat\n\t"
-			".set\tmips3\n\t"
-			"lwu\t%0,%2\n\t"
-			"dsll32\t$1,%1,0\n\t"
-			"or\t$1,$1,%0\n\t"
-			"ddivu\t$0,$1,%3\n\t"
-			"mflo\t$1\n\t"
-			"dsll32\t%0,%4,0\n\t"
-			"nop\n\t"
-			"ddivu\t$0,%0,$1\n\t"
-			"mflo\t%0\n\t"
-			".set\tmips0\n\t"
-			".set\tat\n\t"
-			".set\treorder"
-			:"=&r" (quotient)
-			:"r" (timerhi),
-			 "m" (timerlo),
-			 "r" (tmp),
-			 "r" (USECS_PER_JIFFY)
-			:"$1");
-		cached_quotient = quotient;
-	}
-
-	/* Get last timer tick in absolute kernel time */
-	count = read_32bit_cp0_register(CP0_COUNT);
-
-	/* .. relative to previous jiffy (32 bits is enough) */
-	count -= timerlo;
-
-	__asm__("multu\t%1,%2\n\t"
-		"mfhi\t%0"
-		:"=r" (res)
-		:"r" (count),
-		 "r" (quotient));
-
-	/*
- 	 * Due to possible jiffies inconsistencies, we need to check 
-	 * the result so that we'll get a timer that is monotonic.
-	 */
-	if (res >= USECS_PER_JIFFY)
-		res = USECS_PER_JIFFY-1;
-
-	return res;
+	__restore_flags(flags);
 }
 
-void do_gettimeofday(struct timeval *tv)
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+void __init it8172_timer_setup(struct irqaction *irq)
 {
-	unsigned int flags;
+	puts("timer_setup\n");
+	put32(NR_IRQS);
+	puts("");
+        /* we are using the cpu counter for timer interrupts */
+	setup_irq(MIPS_CPU_TIMER_IRQ, irq);
 
-	read_lock_irqsave (&xtime_lock, flags);
-	*tv = xtime;
-	tv->tv_usec += do_fast_gettimeoffset();
-
-	/*
-	 * xtime is atomically updated in timer_bh. jiffies - wall_jiffies
-	 * is nonzero if the timer bottom half hasnt executed yet.
-	 */
-	if (jiffies - wall_jiffies)
-		tv->tv_usec += USECS_PER_JIFFY;
-
-	read_unlock_irqrestore (&xtime_lock, flags);
-
-	if (tv->tv_usec >= 1000000) {
-		tv->tv_usec -= 1000000;
-		tv->tv_sec++;
-	}
+        /* to generate the first timer interrupt */
+	r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
+	write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
+	set_cp0_status(ALLINTS);
 }
 
-void do_settimeofday(struct timeval *tv)
+void local_timer_interrupt(struct pt_regs *regs)
 {
-	write_lock_irq (&xtime_lock);
-
-	/* This is revolting. We need to set the xtime.tv_usec correctly.
-	 * However, the value in this location is is value at the last tick.
-	 * Discover what correction gettimeofday would have done, and then
-	 * undo it!
-	 */
-	tv->tv_usec -= do_fast_gettimeoffset();
-
-	if (tv->tv_usec < 0) {
-		tv->tv_usec += 1000000;
-		tv->tv_sec--;
-	}
-
-	xtime = *tv;
-	time_adjust = 0;		/* stop active adjtime() */
-	time_status |= STA_UNSYNC;
-	time_maxerror = NTP_PHASE_LIMIT;
-	time_esterror = NTP_PHASE_LIMIT;
-
-	write_unlock_irq (&xtime_lock);
+	do_IRQ(MIPS_CPU_TIMER_IRQ, regs);
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/ivr/Makefile linux/arch/mips/ite-boards/ivr/Makefile
--- linux.orig/arch/mips/ite-boards/ivr/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/ivr/Makefile	2002-08-01 06:42:43.000000000 +0000
@@ -22,7 +22,6 @@
 
 obj-y := init.o 
 
-obj-CONFIG_PCI += pci_fixup.o
-obj-CONFIG_BLK_DEV_INITRD += le_ramdisk.o
+obj-$(CONFIG_PCI) += pci_fixup.o 
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/ivr/init.c linux/arch/mips/ite-boards/ivr/init.c
--- linux.orig/arch/mips/ite-boards/ivr/init.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/ivr/init.c	2002-08-01 06:42:42.000000000 +0000
@@ -52,6 +52,10 @@
 #define PFN_UP(x)	(((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
 #define PFN_ALIGN(x)	(((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
 
+const char *get_system_type(void)
+{
+	return "Globespan IVR";
+}
 
 int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/ivr/pci_fixup.c linux/arch/mips/ite-boards/ivr/pci_fixup.c
--- linux.orig/arch/mips/ite-boards/ivr/pci_fixup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/ivr/pci_fixup.c	2002-08-01 06:42:37.000000000 +0000
@@ -40,10 +40,19 @@
 #include <asm/it8172/it8172_pci.h>
 #include <asm/it8172/it8172_int.h>
 
-void __init board_int_line_fixup(struct pci_dev *dev)     
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
+void __init pcibios_fixup_irqs(void)
 {
 	unsigned int slot, func;
 	unsigned char pin;
+	struct pci_dev *dev;
         const int internal_func_irqs[7] = {
             IT8172_AC97_IRQ,
             IT8172_DMA_IRQ,
@@ -54,57 +63,51 @@
             IT8172_MC68K_IRQ
         };
 
-#ifdef DEBUG
-	printk("board_int_line_fixup bus %d\n", dev->bus->number);
-#endif
-	if (dev->bus->number != 0)
-		return;
-
-	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
-
-#ifdef DEBUG
-	pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
-#endif
-
-	slot = PCI_SLOT(dev->devfn);
-        func = PCI_FUNC(dev->devfn);
+	pci_for_each_dev(dev) {
+		if (dev->bus->number != 0)
+			return;
 
-	switch (slot) {
-                case 0x01:
-                    /*
-                     * Internal device 1 is actually 7 different internal
-                     * devices on the IT8172G (a multi-function device).
-                     */
-                    if (func < 7)
-                        dev->irq = internal_func_irqs[func];
-                    break;
-		case 0x11:
-			switch (pin) {
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+		slot = PCI_SLOT(dev->devfn);
+		func = PCI_FUNC(dev->devfn);
+
+		switch (slot) {
+			case 0x01:
+			    /*
+			     * Internal device 1 is actually 7 different 
+			     * internal devices on the IT8172G (multi-function 
+			     * device).
+			     */
+			    if (func < 7)
+				dev->irq = internal_func_irqs[func];
+			    break;
+			case 0x11:   // Realtek RTL-8139
+				switch (pin) {
+					case 0: /* pin A, hardware bug */
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			case 0x12:   // ivr slot
+				switch (pin) {
 				case 0: /* pin A, hardware bug */
 				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTC_IRQ;
-					break;
-				case 2: /* pin B */
-					dev->irq = IT8172_PCI_INTD_IRQ;
-					break;
-				case 3: /* pin C */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
-				case 4: /* pin D */
 					dev->irq = IT8172_PCI_INTB_IRQ;
 					break;
-				default:
-					dev->irq = 0xff; 
-					break;
-
-			}
-			break;
-		case 0x13:
-			switch (pin) {
-				case 0: /* pin A, hardware bug */
-				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
 				case 2: /* pin B */
 					dev->irq = IT8172_PCI_INTB_IRQ;
 					break;
@@ -118,22 +121,37 @@
 					dev->irq = 0xff; 
 					break;
 
-			}
-			break;
-		default:
-			return;
-	}
-
+				}
+				break;
+			case 0x13:   // expansion slot
+				switch (pin) {
+					case 0: /* pin A, hardware bug */
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			default:
+				break;
+		}
 #ifdef DEBUG
-	printk("irq fixup: slot %d, vendor %x, int line %d, int number %d\n",
-			slot, vendor, pin, dev->irq);
+		printk("irq fixup: slot %d, int line %d, int number %d\n",
+			slot, pin, dev->irq);
 #endif
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+	}
 }
-
-struct pci_fixup pcibios_fixups[] = {
-	{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, board_int_line_fixup },
-	{ 0 }
-};
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/qed-4n-s01b/Makefile linux/arch/mips/ite-boards/qed-4n-s01b/Makefile
--- linux.orig/arch/mips/ite-boards/qed-4n-s01b/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/qed-4n-s01b/Makefile	2002-08-01 06:42:34.000000000 +0000
@@ -16,22 +16,11 @@
 .S.o:
 	$(CC) $(CFLAGS) -c $< -o $*.o
 
-all: ite.o
-
 O_TARGET := ite.o
 
 obj-y := init.o 
 
-ifdef CONFIG_PCI
-obj-y += pci_fixup.o
-endif
-
-ifdef CONFIG_BLK_DEV_INITRD
-obj-y += le_ramdisk.o
-endif
-
-
-dep:
-	$(CPP) -M *.c > .depend
+obj-$(CONFIG_PCI) += pci_fixup.o
+obj-$(CONFIG_BLK_DEV_INITRD) += le_ramdisk.o
 
 include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/qed-4n-s01b/init.c linux/arch/mips/ite-boards/qed-4n-s01b/init.c
--- linux.orig/arch/mips/ite-boards/qed-4n-s01b/init.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/qed-4n-s01b/init.c	2002-08-01 06:42:48.000000000 +0000
@@ -52,6 +52,10 @@
 #define PFN_UP(x)	(((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
 #define PFN_ALIGN(x)	(((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
 
+const char *get_system_type(void)
+{
+	return "ITE QED-4N-S01B";
+}
 
 int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
 {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/ite-boards/qed-4n-s01b/pci_fixup.c linux/arch/mips/ite-boards/qed-4n-s01b/pci_fixup.c
--- linux.orig/arch/mips/ite-boards/qed-4n-s01b/pci_fixup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/ite-boards/qed-4n-s01b/pci_fixup.c	2002-08-01 06:42:36.000000000 +0000
@@ -40,10 +40,19 @@
 #include <asm/it8172/it8172_pci.h>
 #include <asm/it8172/it8172_int.h>
 
-void __init board_int_line_fixup(struct pci_dev *dev)     
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
+void __init pcibios_fixup_irqs(void)
 {
 	unsigned int slot, func;
 	unsigned char pin;
+	struct pci_dev *dev;
         const int internal_func_irqs[7] = {
             IT8172_AC97_IRQ,
             IT8172_DMA_IRQ,
@@ -54,144 +63,133 @@
             IT8172_MC68K_IRQ
         };
 
-#ifdef DEBUG
-	printk("board_int_line_fixup bus %d\n", dev->bus->number);
-#endif
-	if (dev->bus->number != 0)
-		return;
-
-	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
-
-#ifdef DEBUG
-	pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
-#endif
-
-	slot = PCI_SLOT(dev->devfn);
-        func = PCI_FUNC(dev->devfn);
-
-	switch (slot) {
-                case 0x01:
-                    /*
-                     * Internal device 1 is actually 7 different internal
-                     * devices on the IT8172G (a multi-function device).
-                     */
-                    if (func < 7)
-                        dev->irq = internal_func_irqs[func];
-                    break;
-		case 0x10:
-			switch (pin) {
-				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
-				case 2: /* pin B */
-					dev->irq = IT8172_PCI_INTB_IRQ;
-					break;
-				case 3: /* pin C */
-					dev->irq = IT8172_PCI_INTC_IRQ;
-					break;
-				case 4: /* pin D */
-					dev->irq = IT8172_PCI_INTD_IRQ;
-					break;
-				default:
-					dev->irq = 0xff; 
-					break;
-
-			}
-			break;
-		case 0x11:
-			switch (pin) {
-				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
-				case 2: /* pin B */
-					dev->irq = IT8172_PCI_INTB_IRQ;
-					break;
-				case 3: /* pin C */
-					dev->irq = IT8172_PCI_INTC_IRQ;
-					break;
-				case 4: /* pin D */
-					dev->irq = IT8172_PCI_INTD_IRQ;
-					break;
-				default:
-					dev->irq = 0xff; 
-					break;
-
-			}
-			break;
-		case 0x12:
-			switch (pin) {
-				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTB_IRQ;
-					break;
-				case 2: /* pin B */
-					dev->irq = IT8172_PCI_INTC_IRQ;
-					break;
-				case 3: /* pin C */
-					dev->irq = IT8172_PCI_INTD_IRQ;
-					break;
-				case 4: /* pin D */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
-				default:
-					dev->irq = 0xff; 
-					break;
-
-			}
-			break;
-		case 0x13:
-			switch (pin) {
-				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTC_IRQ;
-					break;
-				case 2: /* pin B */
-					dev->irq = IT8172_PCI_INTD_IRQ;
-					break;
-				case 3: /* pin C */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
-				case 4: /* pin D */
-					dev->irq = IT8172_PCI_INTB_IRQ;
-					break;
-				default:
-					dev->irq = 0xff; 
-					break;
-
-			}
-			break;
-		case 0x14:
-			switch (pin) {
-				case 1: /* pin A */
-					dev->irq = IT8172_PCI_INTD_IRQ;
-					break;
-				case 2: /* pin B */
-					dev->irq = IT8172_PCI_INTA_IRQ;
-					break;
-				case 3: /* pin C */
-					dev->irq = IT8172_PCI_INTB_IRQ;
-					break;
-				case 4: /* pin D */
-					dev->irq = IT8172_PCI_INTC_IRQ;
-					break;
-				default:
-					dev->irq = 0xff; 
-					break;
-
-			}
-			break;
-		default:
+	pci_for_each_dev(dev) {
+		if (dev->bus->number != 0) {
 			return;
-	}
+		}
 
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+		slot = PCI_SLOT(dev->devfn);
+		func = PCI_FUNC(dev->devfn);
+
+		switch (slot) {
+			case 0x01:
+			    /*
+			     * Internal device 1 is actually 7 different 
+			     * internal devices on the IT8172G (a multi-
+			     * function device).
+			     */
+			    if (func < 7)
+				dev->irq = internal_func_irqs[func];
+			    break;
+			case 0x10:
+				switch (pin) {
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			case 0x11:
+				switch (pin) {
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			case 0x12:
+				switch (pin) {
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			case 0x13:
+				switch (pin) {
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			case 0x14:
+				switch (pin) {
+					case 1: /* pin A */
+						dev->irq = IT8172_PCI_INTD_IRQ;
+						break;
+					case 2: /* pin B */
+						dev->irq = IT8172_PCI_INTA_IRQ;
+						break;
+					case 3: /* pin C */
+						dev->irq = IT8172_PCI_INTB_IRQ;
+						break;
+					case 4: /* pin D */
+						dev->irq = IT8172_PCI_INTC_IRQ;
+						break;
+					default:
+						dev->irq = 0xff; 
+						break;
+
+				}
+				break;
+			default:
+				continue; /* do nothing */
+		}
 #ifdef DEBUG
-	printk("irq fixup: slot %d, vendor %x, int line %d, int number %d\n",
-			slot, vendor, pin, dev->irq);
+		printk("irq fixup: slot %d, int line %d, int number %d\n",
+			slot, pin, dev->irq);
 #endif
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+	}
 }
-
-struct pci_fixup pcibios_fixups[] = {
-	{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, board_int_line_fixup },
-	{ 0 }
-};
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/common/Makefile linux/arch/mips/jmr3927/common/Makefile
--- linux.orig/arch/mips/jmr3927/common/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/common/Makefile	2002-08-01 06:42:39.000000000 +0000
@@ -0,0 +1,18 @@
+#
+# Makefile for the common code of TOSHIBA JMR-TX3927 board
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+O_TARGET:= tx3927.o
+
+obj-y	 += prom.o puts.o rtc_ds1742.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/common/prom.c linux/arch/mips/jmr3927/common/prom.c
--- linux.orig/arch/mips/jmr3927/common/prom.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/common/prom.c	2002-08-01 06:42:47.000000000 +0000
@@ -0,0 +1,91 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *    PROM library initialisation code, assuming a version of
+ *    pmon is the boot code.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * Based on arch/mips/au1000/common/prom.c
+ *
+ * This file was derived from Carsten Langgaard's 
+ * arch/mips/mips-boards/xx files.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+/* #define DEBUG_CMDLINE */
+
+char arcs_cmdline[CL_SIZE];
+extern int prom_argc;
+extern char **prom_argv, **prom_envp;
+
+typedef struct
+{
+    char *name;
+/*    char *val; */
+}t_env_var;
+
+
+char * __init prom_getcmdline(void)
+{
+	return &(arcs_cmdline[0]);
+}
+
+void  __init prom_init_cmdline(void)
+{
+	char *cp;
+	int actr;
+
+	actr = 1; /* Always ignore argv[0] */
+
+	cp = &(arcs_cmdline[0]);
+	while(actr < prom_argc) {
+	        strcpy(cp, prom_argv[actr]);
+		cp += strlen(prom_argv[actr]);
+		*cp++ = ' ';
+		actr++;
+	}
+	if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+		--cp;
+	*cp = '\0';
+}
+
+int __init page_is_ram(unsigned long pagenr)
+{
+    return 1;
+}
+
+void prom_free_prom_memory (void)
+{
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/common/puts.c linux/arch/mips/jmr3927/common/puts.c
--- linux.orig/arch/mips/jmr3927/common/puts.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/common/puts.c	2002-08-01 06:42:27.000000000 +0000
@@ -0,0 +1,168 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Low level uart routines to directly access a TX[34]927 SIO.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ahennessy@mvista.com or source@mvista.com
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation 
+ *
+ * Based on arch/mips/au1000/common/puts.c
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <asm/jmr3927/txx927.h>
+#include <asm/jmr3927/tx3927.h>
+#include <asm/jmr3927/jmr3927.h>
+
+#define TIMEOUT       0xffffff
+#define SLOW_DOWN
+
+static const char digits[16] = "0123456789abcdef";
+
+#ifdef SLOW_DOWN
+#define slow_down() { int k; for (k=0; k<10000; k++); }
+#else
+#define slow_down()
+#endif
+
+void
+putch(const unsigned char c)
+{
+        int i = 0;
+	
+        do {
+            slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
+	tx3927_sioptr(1)->tfifo = c;
+	return;
+}
+
+unsigned char getch(void)
+{
+        int i = 0;
+	int dicr;
+	char c;
+	
+	/* diable RX int. */
+	dicr = tx3927_sioptr(1)->dicr;
+	tx3927_sioptr(1)->dicr = 0;
+
+        do {
+            slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID)
+		;
+	c = tx3927_sioptr(1)->rfifo;
+
+	/* clear RX int. status */
+	tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS;
+	/* enable RX int. */
+	tx3927_sioptr(1)->dicr = dicr;
+
+	return c;
+}
+void
+do_jmr3927_led_set(char n)
+{
+    /* and with current leds */
+    jmr3927_led_and_set(n);
+}
+
+void
+puts(unsigned char *cp)
+{
+    int i = 0;
+
+    while (*cp) {
+        do {
+            slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
+	tx3927_sioptr(1)->tfifo = *cp++;
+    }
+    putch('\r');
+    putch('\n');
+}
+
+void
+fputs(unsigned char *cp)
+{
+    int i = 0;
+
+    while (*cp) {
+        do {
+             slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
+	tx3927_sioptr(1)->tfifo = *cp++;
+    }
+}
+
+
+void
+put64(uint64_t ul)
+{
+    int cnt;
+    unsigned ch;
+
+    cnt = 16;            /* 16 nibbles in a 64 bit long */
+    putch('0');
+    putch('x');
+    do {
+        cnt--;
+        ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
+                putch(digits[ch]);
+    } while (cnt > 0);
+}
+
+void
+put32(unsigned u)
+{
+    int cnt;
+    unsigned ch;
+
+    cnt = 8;            /* 8 nibbles in a 32 bit long */
+    putch('0');
+    putch('x');
+    do {
+        cnt--;
+        ch = (unsigned char)(u >> cnt * 4) & 0x0F;
+                putch(digits[ch]);
+    } while (cnt > 0);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/common/rtc_ds1742.c linux/arch/mips/jmr3927/common/rtc_ds1742.c
--- linux.orig/arch/mips/jmr3927/common/rtc_ds1742.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/common/rtc_ds1742.c	2002-08-01 06:42:41.000000000 +0000
@@ -0,0 +1,173 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * arch/mips/jmr3927/common/rtc_ds1742.c
+ * Based on arch/mips/ddb5xxx/common/rtc_ds1386.c
+ *     low-level RTC hookups for s for Dallas 1742 chip.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation 
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ ***********************************************************************
+ */
+
+
+/*
+ * This file exports a function, rtc_ds1386_init(), which expects an
+ * uncached base address as the argument.  It will set the two function
+ * pointers expected by the MIPS generic timer code.
+ */
+
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/rtc.h>
+
+#include <asm/time.h>
+#include <asm/addrspace.h>
+
+#include <asm/jmr3927/ds1742rtc.h>
+#include <asm/debug.h>
+
+#define	EPOCH		2000
+
+#undef BCD_TO_BIN
+#define BCD_TO_BIN(val) (((val)&15) + ((val)>>4)*10)
+
+#undef BIN_TO_BCD
+#define BIN_TO_BCD(val) ((((val)/10)<<4) + (val)%10)
+
+static unsigned long rtc_base;
+
+static unsigned long
+rtc_ds1742_get_time(void)
+{
+	unsigned int year, month, day, hour, minute, second;
+	unsigned int century;
+
+	CMOS_WRITE(RTC_READ, RTC_CONTROL);
+	second = BCD_TO_BIN(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
+	minute = BCD_TO_BIN(CMOS_READ(RTC_MINUTES));
+	hour = BCD_TO_BIN(CMOS_READ(RTC_HOURS));
+	day = BCD_TO_BIN(CMOS_READ(RTC_DATE));
+	month = BCD_TO_BIN(CMOS_READ(RTC_MONTH));
+	year = BCD_TO_BIN(CMOS_READ(RTC_YEAR));
+	century = BCD_TO_BIN(CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK);
+	CMOS_WRITE(0, RTC_CONTROL);
+
+	year += century * 100;
+
+	return mktime(year, month, day, hour, minute, second);
+}
+extern void to_tm(unsigned long tim, struct rtc_time * tm);
+
+static int 
+rtc_ds1742_set_time(unsigned long t)
+{
+	struct rtc_time tm;
+	u8 year, month, day, hour, minute, second;
+	u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second;
+	int cmos_century;
+
+	CMOS_WRITE(RTC_READ, RTC_CONTROL);
+	cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
+	cmos_minute = (u8)CMOS_READ(RTC_MINUTES);
+	cmos_hour = (u8)CMOS_READ(RTC_HOURS);
+	cmos_day = (u8)CMOS_READ(RTC_DATE);
+	cmos_month = (u8)CMOS_READ(RTC_MONTH);
+	cmos_year = (u8)CMOS_READ(RTC_YEAR);
+	cmos_century = CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK;
+
+	CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
+
+	/* convert */
+	to_tm(t, &tm);
+
+	/* check each field one by one */
+	year = BIN_TO_BCD(tm.tm_year - EPOCH);
+	if (year != cmos_year) {
+		CMOS_WRITE(year,RTC_YEAR);
+	}
+
+	month = BIN_TO_BCD(tm.tm_mon);
+	if (month != (cmos_month & 0x1f)) {
+		CMOS_WRITE((month & 0x1f) | (cmos_month & ~0x1f),RTC_MONTH);
+	}
+
+	day = BIN_TO_BCD(tm.tm_mday);
+	if (day != cmos_day) {
+	
+		CMOS_WRITE(day, RTC_DATE);
+	}
+
+	if (cmos_hour & 0x40) {
+		/* 12 hour format */
+		hour = 0x40;
+		if (tm.tm_hour > 12) {
+			hour |= 0x20 | (BIN_TO_BCD(hour-12) & 0x1f);
+		} else {
+			hour |= BIN_TO_BCD(tm.tm_hour);
+		}
+	} else {
+		/* 24 hour format */
+		hour = BIN_TO_BCD(tm.tm_hour) & 0x3f;
+	}
+	if (hour != cmos_hour) CMOS_WRITE(hour, RTC_HOURS);
+
+	minute = BIN_TO_BCD(tm.tm_min);
+	if (minute !=  cmos_minute) {
+		CMOS_WRITE(minute, RTC_MINUTES);
+	}
+
+	second = BIN_TO_BCD(tm.tm_sec);
+	if (second !=  cmos_second) {
+		CMOS_WRITE(second & RTC_SECONDS_MASK,RTC_SECONDS);
+	}
+	
+	/* RTC_CENTURY and RTC_CONTROL share same address... */
+	CMOS_WRITE(cmos_century, RTC_CONTROL);
+
+	return 0;
+}
+
+void
+rtc_ds1742_init(unsigned long base)
+{
+	u8  cmos_second;
+
+	/* remember the base */
+	rtc_base = base;
+	db_assert((rtc_base & 0xe0000000) == KSEG1);
+
+	/* set the function pointers */
+	rtc_get_time = rtc_ds1742_get_time;
+	rtc_set_time = rtc_ds1742_set_time;
+
+	/* clear oscillator stop bit */
+	CMOS_WRITE(RTC_READ, RTC_CONTROL);
+	cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
+	CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
+	CMOS_WRITE(cmos_second, RTC_SECONDS); /* clear msb */
+	CMOS_WRITE(0, RTC_CONTROL);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/Makefile linux/arch/mips/jmr3927/rbhma3100/Makefile
--- linux.orig/arch/mips/jmr3927/rbhma3100/Makefile	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/Makefile	2002-08-01 06:42:33.000000000 +0000
@@ -0,0 +1,21 @@
+#
+# Makefile for TOSHIBA JMR-TX3927 board
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+.S.s:
+	$(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+	$(CC) $(CFLAGS) -c $< -o $*.o
+
+O_TARGET:= jmr3927.o
+
+obj-y	 += init.o int-handler.o irq.o setup.o rtc.o pci_fixup.o pci_ops.o
+
+obj-$(CONFIG_LL_DEBUG) 		+= debug.o
+obj-$(CONFIG_REMOTE_DEBUG)	+= kgdb_io.o
+
+include $(TOPDIR)/Rules.make
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/init.c linux/arch/mips/jmr3927/rbhma3100/init.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/init.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/init.c	2002-08-01 06:42:44.000000000 +0000
@@ -0,0 +1,80 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * arch/mips/jmr3927/common/init.c
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation 
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ ***********************************************************************
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/jmr3927/jmr3927.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+unsigned long mips_nofpu = 0;
+
+const char *get_system_type(void)
+{
+	return "Toshiba"
+#ifdef CONFIG_TOSHIBA_JMR3927
+	       " JMR_TX3927"
+#endif
+	;
+}
+
+extern void puts(unsigned char *cp);
+int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
+{
+#ifdef CONFIG_TOSHIBA_JMR3927
+	/* CCFG */
+	if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
+		puts("Warning: TX3927 TLB off\n");
+#endif
+	prom_argc = argc;
+	prom_argv = argv;
+	prom_envp = envp;     
+
+	mips_machgroup = MACH_GROUP_TOSHIBA;
+
+#ifdef CONFIG_TOSHIBA_JMR3927
+	mips_machtype = MACH_TOSHIBA_JMR3927;
+#endif
+
+	prom_init_cmdline();
+	add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
+	return 0;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/int-handler.S linux/arch/mips/jmr3927/rbhma3100/int-handler.S
--- linux.orig/arch/mips/jmr3927/rbhma3100/int-handler.S	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/int-handler.S	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * Based on arch/mips/tsdb/kernel/int-handler.S
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+#include <asm/jmr3927/jmr3927.h>
+
+	/* A lot of complication here is taken away because:
+	 *
+	 * 1) We handle one interrupt and return, sitting in a loop
+	 *    and moving across all the pending IRQ bits in the cause
+	 *    register is _NOT_ the answer, the common case is one
+	 *    pending IRQ so optimize in that direction.
+	 *
+	 * 2) We need not check against bits in the status register
+	 *    IRQ mask, that would make this routine slow as hell.
+	 *
+	 * 3) Linux only thinks in terms of all IRQs on or all IRQs
+	 *    off, nothing in between like BSD spl() brain-damage.
+	 *
+	 */
+
+/* Flush write buffer (needed?)
+ * NOTE: TX39xx performs "non-blocking load", so explicitly use the target
+ * register of LBU to flush immediately.
+ */
+#define FLUSH_WB(tmp)	\
+	la	tmp, JMR3927_IOC_REV_ADDR; \
+	lbu	tmp, (tmp); \
+	move	tmp, zero;
+
+	.text
+	.set	noreorder
+	.set	noat
+	.align	5
+	NESTED(jmr3927_IRQ, PT_SIZE, sp)
+	SAVE_ALL
+	CLI
+	.set	at
+	jal	jmr3927_irc_irqdispatch
+	 move	a0, sp
+	FLUSH_WB(t0)
+	j	ret_from_irq
+	 nop
+	END(jmr3927_IRQ)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/irq.c linux/arch/mips/jmr3927/rbhma3100/irq.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/irq.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/irq.c	2002-08-01 06:42:48.000000000 +0000
@@ -0,0 +1,515 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <linux/errno.h>
+#include <linux/kernel_stat.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/jmr3927/irq.h>
+#include <asm/debug.h>
+#include <asm/jmr3927/jmr3927.h>
+
+#if JMR3927_IRQ_END > NR_IRQS
+#error JMR3927_IRQ_END > NR_IRQS
+#endif
+
+struct tb_irq_space* tb_irq_spaces;
+
+unsigned int local_bh_count[NR_CPUS];
+unsigned int local_irq_count[NR_CPUS];
+
+static int jmr3927_irq_base=-1;
+
+#ifdef CONFIG_PCI
+static int jmr3927_gen_iack(void)
+{
+	/* generate ACK cycle */
+#ifdef __BIG_ENDIAN
+	return (tx3927_pcicptr->iiadp >> 24) & 0xff;
+#else
+	return tx3927_pcicptr->iiadp & 0xff;
+#endif
+}
+#endif
+
+extern asmlinkage void jmr3927_IRQ(void);
+
+#define irc_dlevel	0
+#define irc_elevel	1
+static unsigned char irc_level[TX3927_NUM_IR] = {
+	5, 5, 5, 5, 5, 5,	/* INT[5:0] */
+	7, 7,			/* SIO */
+	5, 5, 5, 0, 0,		/* DMA, PIO, PCI */
+	6, 6, 6			/* TMR */
+};
+
+static inline void mask_irq(unsigned int irq_nr)
+{
+	struct tb_irq_space* sp;
+	for (sp = tb_irq_spaces; sp; sp = sp->next) {
+		if (sp->start_irqno <= irq_nr &&
+		    irq_nr < sp->start_irqno + sp->nr_irqs) {
+			if (sp->mask_func)
+				sp->mask_func(irq_nr - sp->start_irqno,
+					      sp->space_id);
+			break;
+		}
+	}
+}
+
+static inline void unmask_irq(unsigned int irq_nr)
+{
+	struct tb_irq_space* sp;
+	for (sp = tb_irq_spaces; sp; sp = sp->next) {
+		if (sp->start_irqno <= irq_nr &&
+		    irq_nr < sp->start_irqno + sp->nr_irqs) {
+			if (sp->unmask_func)
+				sp->unmask_func(irq_nr - sp->start_irqno,
+						sp->space_id);
+			break;
+		}
+	}
+}
+
+static void jmr3927_irq_disable(unsigned int irq_nr);
+static void jmr3927_irq_enable(unsigned int irq_nr);
+
+static unsigned int jmr3927_irq_startup(unsigned int irq)
+{
+	jmr3927_irq_enable(irq);
+	return 0;
+}
+
+#define	jmr3927_irq_shutdown	jmr3927_irq_disable
+
+static void jmr3927_irq_ack(unsigned int irq)
+{
+	db_assert(jmr3927_irq_base != -1);
+	db_assert(irq >= jmr3927_irq_base);
+	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
+
+	if (irq == JMR3927_IRQ_IRC_TMR0) {
+		jmr3927_tmrptr->tisr = 0;       /* ack interrupt */  
+	}
+
+	jmr3927_irq_disable(irq);
+}
+
+static void jmr3927_irq_end(unsigned int irq)
+{
+	db_assert(jmr3927_irq_base != -1);
+	db_assert(irq >= jmr3927_irq_base);
+	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
+
+	jmr3927_irq_enable(irq);
+}
+
+static void jmr3927_irq_disable(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	db_assert(jmr3927_irq_base != -1);
+	db_assert(irq >= jmr3927_irq_base);
+	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
+
+	save_and_cli(flags);
+	mask_irq(irq_nr);
+	restore_flags(flags);
+}
+
+static void jmr3927_irq_enable(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	db_assert(jmr3927_irq_base != -1);
+	db_assert(irq >= jmr3927_irq_base);
+	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
+
+	save_and_cli(flags);
+	unmask_irq(irq_nr);
+	restore_flags(flags);
+}
+
+/*
+ * CP0_STATUS is a thread's resource (saved/restored on context switch).
+ * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
+ */
+static void mask_irq_isac(int irq_nr, int space_id)
+{
+	/* 0: mask */
+	unsigned char imask =
+		jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
+	unsigned int bit  = 1 << irq_nr;
+	jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
+	/* flush write buffer */
+	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
+}
+static void unmask_irq_isac(int irq_nr, int space_id)
+{
+	/* 0: mask */
+	unsigned char imask =
+		jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
+	unsigned int bit  = 1 << irq_nr;
+	jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
+	/* flush write buffer */
+	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
+}
+
+static void mask_irq_ioc(int irq_nr, int space_id)
+{
+	/* 0: mask */
+	unsigned char imask =
+		jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
+	unsigned int bit = 1 << irq_nr;
+	jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
+	/* flush write buffer */
+	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
+}
+static void unmask_irq_ioc(int irq_nr, int space_id)
+{
+	/* 0: mask */
+	unsigned char imask =
+		jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
+	unsigned int bit = 1 << irq_nr;
+	jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
+	/* flush write buffer */
+	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
+}
+
+static void mask_irq_irc(int irq_nr, int space_id)
+{
+	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
+	if (irq_nr & 1)
+		*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
+	else
+		*ilrp = (*ilrp & 0xff00) | irc_dlevel;
+	/* update IRCSR */
+	tx3927_ircptr->imr = 0;
+	tx3927_ircptr->imr = irc_elevel;
+}
+static void unmask_irq_irc(int irq_nr, int space_id)
+{
+	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
+	if (irq_nr & 1)
+		*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
+	else
+		*ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
+	/* update IRCSR */
+	tx3927_ircptr->imr = 0;
+	tx3927_ircptr->imr = irc_elevel;
+}
+
+struct tb_irq_space jmr3927_isac_irqspace = {
+	next: NULL,
+	start_irqno: JMR3927_IRQ_ISAC,
+	nr_irqs : JMR3927_NR_IRQ_ISAC,
+	mask_func: mask_irq_isac,
+	unmask_func: unmask_irq_isac,
+	name: "ISAC",
+	space_id: 0,
+	can_share : 0
+};
+struct tb_irq_space jmr3927_ioc_irqspace = {
+	next: NULL,
+	start_irqno: JMR3927_IRQ_IOC,
+	nr_irqs : JMR3927_NR_IRQ_IOC,
+	mask_func: mask_irq_ioc,
+	unmask_func: unmask_irq_ioc,
+	name: "IOC",
+	space_id: 0,
+	can_share : 1
+};
+struct tb_irq_space jmr3927_irc_irqspace = {
+	next: NULL,
+	start_irqno: JMR3927_IRQ_IRC,
+	nr_irqs : JMR3927_NR_IRQ_IRC,
+	mask_func: mask_irq_irc,
+	unmask_func: unmask_irq_irc,
+	name: "on-chip",
+	space_id: 0,
+	can_share : 0
+};
+
+void jmr3927_spurious(struct pt_regs *regs)
+{
+#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
+	tx_branch_likely_bug_fixup(regs);
+#endif
+	printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
+	       regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
+}
+
+extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
+void jmr3927_irc_irqdispatch(struct pt_regs *regs)
+{
+	int irq;
+	
+#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
+	tx_branch_likely_bug_fixup(regs);
+#endif
+	if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
+#if 0
+		jmr3927_spurious(regs);
+#endif
+		return;
+	}
+	irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
+
+	do_IRQ(irq + JMR3927_IRQ_IRC, regs);
+}
+
+static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
+	int i;
+
+	for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
+		if (istat & (1 << i)) {
+			irq = JMR3927_IRQ_IOC + i;
+			do_IRQ(irq, regs);
+		}
+	}
+}
+
+static struct irqaction ioc_action = {
+	jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL,
+};
+
+static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
+	int i;
+
+	for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
+		if (istat & (1 << i)) {
+			irq = JMR3927_IRQ_ISAC + i;
+			do_IRQ(irq, regs);
+		}
+	}
+}
+
+static struct irqaction isac_action = {
+	jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL,
+};
+
+
+static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
+{
+	printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
+}
+static struct irqaction isaerr_action = {
+	jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL,
+};
+
+static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
+{
+	printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
+	printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
+	       tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
+}
+static struct irqaction pcierr_action = {
+	jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL,
+};
+
+int jmr3927_ether1_irq = 0;
+
+void jmr3927_irq_init(u32 irq_base);
+void jmr3927_irq_setup(void)
+{
+	/* look for io board's presence */
+	int have_isac = jmr3927_have_isac();
+
+	/* Now, interrupt control disabled, */
+	/* all IRC interrupts are masked, */
+	/* all IRC interrupt mode are Low Active. */
+
+	if (have_isac) {
+
+		/* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
+		/* temporary enable interrupt control */
+		tx3927_ircptr->cer = 1;
+		/* ETHER1 Int. Is High-Active. */
+		if (tx3927_ircptr->ssr & (1 << 0))
+			jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
+#if 0	/* INT3 may be asserted by ether0 (even after reboot...) */
+		else if (tx3927_ircptr->ssr & (1 << 3))
+			jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
+#endif
+		/* disable interrupt control */
+		tx3927_ircptr->cer = 0;
+
+		/* Ether1: High Active */
+		if (jmr3927_ether1_irq) {
+			int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
+			tx3927_ircptr->cr[ether1_irc / 8] |=
+				TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
+		}
+	}
+
+	/* mask all IOC interrupts */
+	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
+	/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
+	jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
+
+	if (have_isac) {
+		/* mask all ISAC interrupts */
+		jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
+		/* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
+		jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
+	}
+
+	/* clear PCI Soft interrupts */
+	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
+	/* clear PCI Reset interrupts */
+	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
+
+	/* enable interrupt control */
+	tx3927_ircptr->cer = TX3927_IRCER_ICE;
+	tx3927_ircptr->imr = irc_elevel;
+
+	jmr3927_irq_init(NR_ISA_IRQS);
+
+	set_except_vector(0, jmr3927_IRQ);
+
+	/* setup irq space */
+	add_tb_irq_space(&jmr3927_isac_irqspace);
+	add_tb_irq_space(&jmr3927_ioc_irqspace);
+	add_tb_irq_space(&jmr3927_irc_irqspace);
+
+	/* setup IOC interrupt 1 (PCI, MODEM) */
+	setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
+
+	if (have_isac) {
+		setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
+		setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
+	}
+
+#ifdef CONFIG_PCI
+	setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
+#endif
+
+	/* enable all CPU interrupt bits. */
+	set_cp0_status(ST0_IM);	/* IE bit is still 0. */
+}
+
+void (*irq_setup)(void);
+void __init init_IRQ(void)
+{
+
+#ifdef CONFIG_REMOTE_DEBUG
+        extern void breakpoint(void);
+        extern void set_debug_traps(void);
+
+        puts("Wait for gdb client connection ...\n");
+        set_debug_traps();
+        breakpoint();
+#endif
+
+        /* invoke board-specific irq setup */
+        irq_setup();
+}
+
+hw_irq_controller jmr3927_irq_controller = {
+	"jmr3927_irq",
+	jmr3927_irq_startup,
+	jmr3927_irq_shutdown,
+	jmr3927_irq_enable,
+	jmr3927_irq_disable,
+	jmr3927_irq_ack,
+	jmr3927_irq_end,
+	NULL			/* no affinity stuff for UP */
+};
+
+void 
+jmr3927_irq_init(u32 irq_base)
+{
+	extern irq_desc_t irq_desc[];
+	u32 i;
+
+	for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &jmr3927_irq_controller;
+	}
+	
+	jmr3927_irq_base = irq_base;
+}
+
+#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
+static int tx_branch_likely_bug_count = 0;
+static int have_tx_branch_likely_bug = 0;
+void tx_branch_likely_bug_fixup(struct pt_regs *regs)
+{
+	/* TX39/49-BUG: Under this condition, the insn in delay slot
+           of the branch likely insn is executed (not nullified) even
+           the branch condition is false. */
+	if (!have_tx_branch_likely_bug)
+		return;
+	if ((regs->cp0_epc & 0xfff) == 0xffc &&
+	    KSEGX(regs->cp0_epc) != KSEG0 &&
+	    KSEGX(regs->cp0_epc) != KSEG1) {
+		unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
+		/* beql,bnel,blezl,bgtzl */
+		/* bltzl,bgezl,blezall,bgezall */
+		/* bczfl, bcztl */
+		if ((insn & 0xf0000000) == 0x50000000 ||
+		    (insn & 0xfc0e0000) == 0x04020000 ||
+		    (insn & 0xf3fe0000) == 0x41020000) {
+			regs->cp0_epc -= 4;
+			tx_branch_likely_bug_count++;
+			printk(KERN_INFO
+			       "fix branch-likery bug in %s (insn %08x)\n",
+			       current->comm, insn);
+		}
+	}
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/kgdb_io.c linux/arch/mips/jmr3927/rbhma3100/kgdb_io.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/kgdb_io.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/kgdb_io.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,155 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *	Low level uart routines to directly access a TX[34]927 SIO.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ahennessy@mvista.com or source@mvista.com
+ *
+ * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation 
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <asm/jmr3927/txx927.h>
+#include <asm/jmr3927/tx3927.h>
+#include <asm/jmr3927/jmr3927.h>
+
+#define TIMEOUT       0xffffff
+#define SLOW_DOWN
+
+static const char digits[16] = "0123456789abcdef";
+
+#ifdef SLOW_DOWN
+#define slow_down() { int k; for (k=0; k<10000; k++); }
+#else
+#define slow_down()
+#endif
+
+static int remoteDebugInitialized = 0;
+
+int putDebugChar(unsigned char c)
+{
+        int i = 0;
+	
+	if (!remoteDebugInitialized) {
+		remoteDebugInitialized = 1;
+		debugInit(38400);
+	}
+
+        do {
+            slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
+	tx3927_sioptr(0)->tfifo = c;
+
+	return 1;
+}
+
+unsigned char getDebugChar(void)
+{
+        int i = 0;
+	int dicr;
+	char c;
+	
+	if (!remoteDebugInitialized) {
+		remoteDebugInitialized = 1;
+		debugInit(38400);
+	}
+
+	/* diable RX int. */
+	dicr = tx3927_sioptr(0)->dicr;
+	tx3927_sioptr(0)->dicr = 0;
+
+        do {
+            slow_down();
+            i++;
+            if (i>TIMEOUT) {
+                break;
+            }
+        } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
+		;
+	c = tx3927_sioptr(0)->rfifo;
+
+	/* clear RX int. status */
+	tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
+	/* enable RX int. */
+	tx3927_sioptr(0)->dicr = dicr;
+
+	return c;
+}
+
+void debugInit(int baud)
+{
+	/*
+	volatile unsigned long lcr;
+	volatile unsigned long dicr;
+	volatile unsigned long disr;
+	volatile unsigned long cisr;
+	volatile unsigned long fcr;
+	volatile unsigned long flcr;
+	volatile unsigned long bgr;
+	volatile unsigned long tfifo;
+	volatile unsigned long rfifo;
+	*/
+
+	tx3927_sioptr(0)->lcr = 0x020;
+	tx3927_sioptr(0)->dicr = 0;
+	tx3927_sioptr(0)->disr = 0x4100;
+	tx3927_sioptr(0)->cisr = 0x014;
+	tx3927_sioptr(0)->fcr = 0;
+	tx3927_sioptr(0)->flcr = 0x02;
+	tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
+		TXx927_SIBGR_BCLK_T0;
+#if 0
+	/*
+	 * Reset the UART.
+	 */
+	tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
+	while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
+		;
+
+	/*
+	 * and set the speed of the serial port
+	 * (currently hardwired to 9600 8N1
+	 */
+
+	tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
+		TXx927_SILCR_USBL_1BIT |
+		TXx927_SILCR_SCS_IMCLK_BG;
+	tx3927_sioptr(0)->bgr =
+		((JMR3927_BASE_BAUD + baud / 2) / baud) |
+		TXx927_SIBGR_BCLK_T0;
+
+	/* HW RTS/CTS control */
+	if (ser->flags & ASYNC_HAVE_CTS_LINE)
+		tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
+			TXx927_SIFLCR_RTSTL_MAX /* 15 */;
+	/* Enable RX/TX */
+	tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
+#endif
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/pci_fixup.c linux/arch/mips/jmr3927/rbhma3100/pci_fixup.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/pci_fixup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/pci_fixup.c	2002-08-01 06:42:43.000000000 +0000
@@ -0,0 +1,140 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Board specific pci fixups.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_PCI
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/jmr3927/jmr3927.h>
+
+#undef	DEBUG
+#ifdef 	DEBUG
+#define	DBG(x...)	printk(x)
+#else
+#define	DBG(x...)	
+#endif
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+	/* will need to fixup IO resources */
+}
+
+void __init pcibios_fixup(void)
+{
+	/* nothing to do here */
+}
+
+int pci_get_irq(struct pci_dev *dev, int pin)
+{
+	unsigned char irq = pin;
+
+	/* IRQ rotation (PICMG) */
+	irq--;	/* 0-3 */
+	if (dev->bus->parent == NULL &&
+	    PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
+		/* PCI CardSlot (IDSEL=A23, DevNu=12) */
+		/* PCIA => PCIC (IDSEL=A23) */
+		/* NOTE: JMR3927 JP1 must be set to OPEN */
+		irq = (irq + 2) % 4;
+	} else if (dev->bus->parent == NULL &&
+		   PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
+		/* PCI CardSlot (IDSEL=A22, DevNu=11) */
+		/* PCIA => PCIA (IDSEL=A22) */
+		/* NOTE: JMR3927 JP1 must be set to OPEN */
+		irq = (irq + 0) % 4;
+	} else {
+		/* PCI Backplane */
+		irq = (irq + 3 + PCI_SLOT(dev->devfn)) % 4;
+#if 0	/* ??? */
+		for (bus = dev->bus; bus->parent != NULL; bus = bus->parent) {
+			irq = (irq + 3 + PCI_SLOT(bus->self->devfn)) % 4;
+		}
+#endif
+	}
+	irq++;	/* 1-4 */
+
+	switch (irq) {
+	case 1:
+		irq = JMR3927_IRQ_IOC_PCIA;
+		break;
+	case 2:
+		// wrong for backplane irq = JMR3927_IRQ_IOC_PCIB;
+		irq = JMR3927_IRQ_IOC_PCID;
+		break;
+	case 3:
+		irq = JMR3927_IRQ_IOC_PCIC;
+		break;
+	case 4:
+		// wrong for backplane irq = JMR3927_IRQ_IOC_PCID;
+		irq = JMR3927_IRQ_IOC_PCIB;
+		break;
+	}
+
+	/* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
+	if (dev->bus->parent == NULL &&
+	    PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(24)) {
+		extern int jmr3927_ether1_irq;
+		/* check this irq line was reserved for ether1 */
+		if (jmr3927_ether1_irq != JMR3927_IRQ_ETHER0)
+			irq = JMR3927_IRQ_ETHER0;
+		else
+			irq = 0;	/* disable */
+	}
+	return irq;
+}
+
+void __init pcibios_fixup_irqs(void)
+{
+	unsigned char irq;
+        struct pci_dev *dev;
+
+	pci_for_each_dev(dev) {
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
+		if (irq == 0)
+			return;
+
+		/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
+		if (!(dev->vendor == PCI_VENDOR_ID_EFAR &&
+		      dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)) {
+			irq = pci_get_irq(dev, irq);
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
+		}
+
+		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
+		printk(KERN_INFO "PCI: %02x:%02x IRQ %02x\n",
+		       dev->bus->number, dev->devfn, irq);
+		dev->irq = irq;
+	}
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/pci_ops.c linux/arch/mips/jmr3927/rbhma3100/pci_ops.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/pci_ops.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/pci_ops.c	2002-08-01 06:42:36.000000000 +0000
@@ -0,0 +1,471 @@
+/***********************************************************************
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation 
+ *
+ * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
+ *
+ *     Define the pci_ops for JMR3927.
+ *
+ * Much of the code is derived from the original DDB5074 port by 
+ * Geert Uytterhoeven <geert@sonycom.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ ***********************************************************************
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/config.h>
+
+#include <asm/addrspace.h>
+#include <asm/pci_channel.h>
+#include <asm/jmr3927/jmr3927.h>
+#include <asm/debug.h>
+
+struct resource pci_io_resource = {
+	"pci IO space", 
+	0x1000,  /* reserve regacy I/O space */
+	0x1000 + JMR3927_PCIIO_SIZE -1,
+	IORESOURCE_IO};
+
+struct resource pci_mem_resource = {
+	"pci memory space", 
+	JMR3927_PCIMEM,
+	JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE -1,
+	IORESOURCE_MEM};
+
+extern struct pci_ops jmr3927_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+	{ &jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff },
+	{ NULL, NULL, NULL, NULL, NULL}
+};
+
+unsigned int pcibios_assign_all_busses(void)
+{
+	return 1;
+}                           
+
+static int
+mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, int *flagsp)
+{
+	if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
+		return -1;
+
+	tx3927_pcicptr->ica = ((bus    & 0xff) << 0x10) |
+	                      ((dev_fn & 0xff) << 0x08) |
+	                      (where  & 0xfc);
+	/* clear M_ABORT and Disable M_ABORT Int. */
+	tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
+	tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
+	return 0;
+}
+
+static int
+check_abort(int flags)
+{
+	int code = PCIBIOS_SUCCESSFUL;
+	if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
+		tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
+		tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
+		code =PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	return code;
+}
+
+/*
+ * We can't address 8 and 16 bit words directly.  Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int jmr3927_pcibios_read_config_byte (struct pci_dev *dev,
+					     int where,
+					     unsigned char *val)
+{
+	int flags;
+	unsigned char bus, func_num;
+
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));  
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}                               
+
+	func_num = PCI_FUNC(dev->devfn);
+	if (mkaddr(bus, dev->devfn, where, &flags))
+		return -1;
+	*val = *(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3));
+	return check_abort(flags);
+}
+
+static int jmr3927_pcibios_read_config_word (struct pci_dev *dev,
+					     int where,
+					     unsigned short *val)
+{
+	int flags;
+	unsigned char bus, func_num;
+
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));  
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}                               
+
+	func_num = PCI_FUNC(dev->devfn);
+	if (mkaddr(bus, dev->devfn, where, &flags))
+		return -1;
+	*val = le16_to_cpu(*(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)));
+	return check_abort(flags);
+}
+
+static int jmr3927_pcibios_read_config_dword (struct pci_dev *dev,
+					      int where,
+					      unsigned int *val)
+{
+	int flags;
+	unsigned char bus, func_num;
+
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));  
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}                               
+
+	func_num = PCI_FUNC(dev->devfn);
+	if (mkaddr(bus, dev->devfn, where, &flags))
+		return -1;
+	*val = le32_to_cpu(tx3927_pcicptr->icd);
+	return check_abort(flags);
+}
+
+static int jmr3927_pcibios_write_config_byte (struct pci_dev *dev,
+					      int where,
+					      unsigned char val)
+{
+	int flags;
+	unsigned char bus, func_num;
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}                               
+
+	func_num = PCI_FUNC(dev->devfn);
+	if (mkaddr(bus, dev->devfn, where, &flags))
+		return -1;
+	*(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = val;
+	return check_abort(flags);
+}
+
+static int jmr3927_pcibios_write_config_word (struct pci_dev *dev,
+					      int where,
+					      unsigned short val)
+{
+	int flags;
+	unsigned char bus, func_num;
+
+	if (where & 1)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}                               
+
+	func_num = PCI_FUNC(dev->devfn);
+	if (mkaddr(bus, dev->devfn, where, &flags))
+		return -1;
+	*(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = cpu_to_le16(val);
+	return check_abort(flags);
+}
+
+static int jmr3927_pcibios_write_config_dword (struct pci_dev *dev,
+					       int where,
+					       unsigned int val)
+{
+	int flags;
+	unsigned char bus, func_num;
+
+	if (where & 3)
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	/* check if the bus is top-level */
+	if (dev->bus->parent != NULL) {
+		bus = dev->bus->number;
+		db_assert(bus != 0);
+	} else {
+		bus = 0;
+	}                               
+
+	func_num = PCI_FUNC(dev->devfn);
+	if (mkaddr(bus, dev->devfn, where, &flags))
+		return -1;
+	tx3927_pcicptr->icd = cpu_to_le32(val);
+	return check_abort(flags);
+}
+struct pci_ops jmr3927_pci_ops = {
+	jmr3927_pcibios_read_config_byte,
+	jmr3927_pcibios_read_config_word,
+	jmr3927_pcibios_read_config_dword,
+	jmr3927_pcibios_write_config_byte,
+	jmr3927_pcibios_write_config_word,
+	jmr3927_pcibios_write_config_dword
+};
+
+#ifndef JMR3927_INIT_INDIRECT_PCI
+inline unsigned long tc_readl(volatile __u32 *addr)
+{
+	return readl(addr);
+}
+inline void tc_writel(unsigned long data, volatile __u32 *addr)
+{
+	writel(data, addr);
+}
+#else
+unsigned long tc_readl(volatile __u32 *addr)
+{
+	unsigned long val;
+
+	addr = PHYSADDR(addr);
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)addr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+	return val;
+}
+void tc_writel(unsigned long data, volatile __u32 *addr)
+{
+	addr = PHYSADDR(addr);
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data);
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)addr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT)  | PCI_IPCIBE_IBE_LONG;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+}
+unsigned char tx_ioinb(unsigned char *addr)
+{
+	unsigned long val;
+	__u32 ioaddr;
+	int offset;
+	int byte;
+
+	ioaddr = (unsigned long)addr;
+        offset = ioaddr & 0x3;
+	if (offset == 0)
+		byte = 0x7;
+	else if (offset == 1)
+		byte = 0xb;
+	else if (offset == 2)
+		byte = 0xd;
+	else if (offset == 3)
+		byte = 0xe;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
+	val = val & 0xff;
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+	return val;
+}
+void tx_iooutb(unsigned long data, unsigned char *addr)
+{
+	__u32 ioaddr;
+	int offset;
+	int byte;
+
+	data = data | (data << 8) | (data << 16) | (data << 24);
+	ioaddr = (unsigned long)addr;
+        offset = ioaddr & 0x3;
+	if (offset == 0)
+		byte = 0x7;
+	else if (offset == 1)
+		byte = 0xb;
+	else if (offset == 2)
+		byte = 0xd;
+	else if (offset == 3)
+		byte = 0xe;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT)  | byte;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+}
+unsigned short tx_ioinw(unsigned short *addr)
+{
+	unsigned long val;
+	__u32 ioaddr;
+	int offset;
+	int byte;
+
+	ioaddr = (unsigned long)addr;
+        offset = ioaddr & 0x3;
+	if (offset == 0)
+		byte = 0x3;
+	else if (offset == 2)
+		byte = 0xc;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
+	val = val & 0xffff;
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+	return val;
+
+}
+void tx_iooutw(unsigned long data, unsigned short *addr)
+{
+	__u32 ioaddr;
+	int offset;
+	int byte;
+
+	data = data | (data << 16);
+	ioaddr = (unsigned long)addr;
+        offset = ioaddr & 0x3;
+	if (offset == 0)
+		byte = 0x3;
+	else if (offset == 2)
+		byte = 0xc;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT)  | byte;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+}
+unsigned long tx_ioinl(unsigned int *addr)
+{
+	unsigned long val;
+	__u32 ioaddr;
+
+	ioaddr = (unsigned long)addr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+	return val;
+}
+void tx_iooutl(unsigned long data, unsigned int *addr)
+{
+	__u32 ioaddr;
+
+	ioaddr = (unsigned long)addr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data);
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
+	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
+	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT)  | PCI_IPCIBE_IBE_LONG;
+	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
+	/* clear by setting */
+	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
+}
+void tx_insbyte(unsigned char *addr,void *buffer,unsigned int count)
+{
+	unsigned char *ptr = (unsigned char *) buffer;
+
+	while (count--) {
+		*ptr++ = tx_ioinb(addr);
+	}
+}
+void tx_insword(unsigned short *addr,void *buffer,unsigned int count)
+{
+	unsigned short *ptr = (unsigned short *) buffer;
+
+	while (count--) {
+		*ptr++ = tx_ioinw(addr);
+	}
+}
+void tx_inslong(unsigned int *addr,void *buffer,unsigned int count)
+{
+	unsigned long *ptr = (unsigned long *) buffer;
+
+	while (count--) {
+		*ptr++ = tx_ioinl(addr);
+	}
+}
+void tx_outsbyte(unsigned char *addr,void *buffer,unsigned int count)
+{
+	unsigned char *ptr = (unsigned char *) buffer;
+
+	while (count--) {
+		tx_iooutb(*ptr++,addr);
+	}
+}
+void tx_outsword(unsigned short *addr,void *buffer,unsigned int count)
+{
+	unsigned short *ptr = (unsigned short *) buffer;
+
+	while (count--) {
+		tx_iooutw(*ptr++,addr);
+	}
+}
+void tx_outslong(unsigned int *addr,void *buffer,unsigned int count)
+{
+	unsigned long *ptr = (unsigned long *) buffer;
+
+	while (count--) {
+		tx_iooutl(*ptr++,addr);
+	}
+}
+#endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/rtc.c linux/arch/mips/jmr3927/rbhma3100/rtc.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/rtc.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/rtc.c	2002-08-01 06:42:42.000000000 +0000
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * RTC routines for Dallas chip.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 200-2001 Toshiba Corporation
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <asm/mc146818rtc.h>	/* bad name... */
+#include <asm/jmr3927/jmr3927.h>
+
+static unsigned char jmr3927_rtc_read_data(unsigned long addr)
+{
+	return jmr3927_nvram_in(addr);
+}
+
+static void jmr3927_rtc_write_data(unsigned char data, unsigned long addr)
+{
+	jmr3927_nvram_out(data, addr);
+}
+
+static int jmr3927_rtc_bcd_mode(void)
+{
+	return 1;
+}
+
+struct rtc_ops jmr3927_rtc_ops = {
+	&jmr3927_rtc_read_data,
+	&jmr3927_rtc_write_data,
+	&jmr3927_rtc_bcd_mode
+};
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/jmr3927/rbhma3100/setup.c linux/arch/mips/jmr3927/rbhma3100/setup.c
--- linux.orig/arch/mips/jmr3927/rbhma3100/setup.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/jmr3927/rbhma3100/setup.c	2002-08-01 06:42:30.000000000 +0000
@@ -0,0 +1,525 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ahennessy@mvista.com       
+ *
+ * Based on arch/mips/ddb5xxx/ddb5477/setup.c
+ *
+ *     Setup file for JMR3927.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation 
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ ***********************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/console.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/ide.h>
+#include <linux/fs.h>		/* for ROOT_DEV */
+#include <linux/ioport.h>
+#include <linux/param.h>	/* for HZ */
+#include <linux/delay.h>
+
+#include <asm/addrspace.h>
+#include <asm/time.h>
+#include <asm/bcache.h>
+#include <asm/irq.h>
+#include <asm/reboot.h>
+#include <asm/gdb-stub.h>
+#include <asm/jmr3927/jmr3927.h>
+#include <asm/mipsregs.h>
+
+/* Tick Timer divider */
+#define JMR3927_TIMER_CCD	0	/* 1/2 */
+#define JMR3927_TIMER_CLK	(JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
+
+unsigned char led_state = 0xf;
+
+struct {
+    struct resource ram0;
+    struct resource ram1;
+    struct resource pcimem;
+    struct resource iob;
+    struct resource ioc;
+    struct resource pciio;
+    struct resource jmy1394;
+    struct resource rom1;
+    struct resource rom0;
+    struct resource sio0;
+    struct resource sio1;
+} jmr3927_resources = {
+    { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
+    { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
+    { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
+    { "IOB",           0x10000000, 0x13FFFFFF                  },
+    { "IOC",           0x14000000, 0x14FFFFFF                  },
+    { "PCIIO",         0x15000000, 0x15FFFFFF                  },
+    { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
+    { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
+    { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
+    { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
+    { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
+};
+
+/* don't enable - see errata */
+int jmr3927_ccfg_toeon = 0;
+
+static inline void do_reset(void)
+{
+#ifdef CONFIG_TC35815
+	extern void tc35815_killall(void);
+	tc35815_killall();
+#endif
+#if 1	/* Resetting PCI bus */
+	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
+	jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
+	(void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);	/* flush WB */
+	mdelay(1);
+	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
+#endif
+	jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
+}
+
+static void jmr3927_machine_restart(char *command)
+{
+	cli();
+	puts("Rebooting...");
+	do_reset();
+}
+
+static void jmr3927_machine_halt(void)
+{
+	puts("JMR-TX3927 halted.\n");
+	while (1);
+}
+
+static void jmr3927_machine_power_off(void)
+{
+	puts("JMR-TX3927 halted. Please turn off the power.\n");
+	while (1);
+}
+
+#define USE_RTC_DS1742
+#ifdef USE_RTC_DS1742
+extern void rtc_ds1742_init(unsigned long base);
+#endif
+static void __init jmr3927_time_init(void)
+{
+#ifdef USE_RTC_DS1742
+	if (jmr3927_have_nvram()) {
+	        rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
+	}
+#endif
+}
+
+unsigned long jmr3927_do_gettimeoffset(void);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+static void __init jmr3927_timer_setup(struct irqaction *irq)
+{
+	do_gettimeoffset = jmr3927_do_gettimeoffset;
+
+	jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
+	jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
+	jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
+	jmr3927_tmrptr->tcr =
+		TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
+
+	setup_irq(JMR3927_IRQ_TICK, irq);
+}
+
+#define USECS_PER_JIFFY (1000000/HZ)
+unsigned long jmr3927_do_gettimeoffset(void)
+{
+       unsigned long count;
+       unsigned long res = 0;
+
+       /* MUST read TRR before TISR. */
+       count = jmr3927_tmrptr->trr;
+
+       if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
+               /* timer interrupt is pending.  use Max value. */
+               res = USECS_PER_JIFFY - 1;
+       } else {
+               /* convert to usec */
+               /* res = count / (JMR3927_TIMER_CLK / 1000000); */
+               res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
+
+               /*
+                * Due to possible jiffies inconsistencies, we need to check
+                * the result so that we'll get a timer that is monotonic.
+                */
+               if (res >= USECS_PER_JIFFY)
+                       res = USECS_PER_JIFFY-1;
+       }
+
+       return res;
+}                                         
+
+#if defined(CONFIG_BLK_DEV_INITRD)
+extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
+#endif 
+
+//#undef DO_WRITE_THROUGH
+#define DO_WRITE_THROUGH
+#define DO_ENABLE_CACHE
+
+extern char * __init prom_getcmdline(void);
+static void jmr3927_board_init(void);
+extern void jmr3927_irq_setup(void);
+extern struct resource pci_io_resource;
+extern struct resource pci_mem_resource;
+void __init jmr3927_setup(void)
+{
+	extern int panic_timeout;
+	char *argptr;
+
+	irq_setup = jmr3927_irq_setup;
+	mips_io_port_base = JMR3927_PORT_BASE + JMR3927_PCIIO;
+
+	board_time_init = jmr3927_time_init;
+	board_timer_setup = jmr3927_timer_setup;
+
+	_machine_restart = jmr3927_machine_restart;
+	_machine_halt = jmr3927_machine_halt;
+	_machine_power_off = jmr3927_machine_power_off;
+
+	/*
+	 * IO/MEM resources. 
+	 */
+	ioport_resource.start = pci_io_resource.start;
+	ioport_resource.end = pci_io_resource.end;
+	iomem_resource.start = pci_mem_resource.start;
+	iomem_resource.end = pci_mem_resource.end;
+	
+	/* Reboot on panic */
+	panic_timeout = 180;
+
+	{
+		unsigned int conf;
+		conf = read_32bit_cp0_register(CP0_CONF);
+	}
+
+#if 1
+	/* cache setup */
+	{
+		unsigned int conf;
+#ifdef DO_ENABLE_CACHE
+		int mips_ic_disable = 0, mips_dc_disable = 0;
+#else
+		int mips_ic_disable = 1, mips_dc_disable = 1;
+#endif
+#ifdef DO_WRITE_THROUGH
+		int mips_config_cwfon = 0;
+		int mips_config_wbon = 0;
+#else
+		int mips_config_cwfon = 1;
+		int mips_config_wbon = 1;
+#endif
+
+		conf = read_32bit_cp0_register(CP0_CONF);
+		conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
+		conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
+		conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
+		conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
+		conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
+
+		write_32bit_cp0_register(CP0_CONF, conf);
+		write_32bit_cp0_register(CP0_TX39_CACHE, 0);
+	}
+#endif
+
+	/* initialize board */
+	jmr3927_board_init();
+
+	argptr = prom_getcmdline();
+
+	if ((argptr = strstr(argptr, "toeon")) != NULL) {
+			jmr3927_ccfg_toeon = 1;
+	}
+	argptr = prom_getcmdline();
+	if ((argptr = strstr(argptr, "ip=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " ip=bootp");
+	}
+
+#ifdef CONFIG_TXX927_SERIAL_CONSOLE
+	argptr = prom_getcmdline();
+	if ((argptr = strstr(argptr, "console=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " console=ttyS1,115200");
+	}
+#endif                                             
+}
+ 
+
+static void tx3927_setup(void);
+
+#ifdef CONFIG_PCI
+unsigned long mips_pci_io_base;
+unsigned long mips_pci_io_size;
+unsigned long mips_pci_mem_base;
+unsigned long mips_pci_mem_size;
+/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
+unsigned long mips_pci_io_pciaddr = 0;
+#endif
+extern struct rtc_ops *rtc_ops;
+extern struct rtc_ops jmr3927_rtc_ops;
+static void jmr3927_board_init()
+{
+	char *argptr;
+
+#ifdef CONFIG_PCI
+	mips_pci_io_base = JMR3927_PCIIO;
+	mips_pci_io_size = JMR3927_PCIIO_SIZE;
+	mips_pci_mem_base = JMR3927_PCIMEM;
+	mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
+#endif
+
+	tx3927_setup();
+
+#ifdef CONFIG_VT
+	conswitchp = &dummy_con;
+#endif
+
+	if (jmr3927_have_isac()) {
+
+#ifdef CONFIG_FB_E1355
+		argptr = prom_getcmdline();
+		if ((argptr = strstr(argptr, "video=")) == NULL) {
+			argptr = prom_getcmdline();
+			strcat(argptr, " video=e1355fb:crt16h");
+		}
+#endif
+
+#ifdef CONFIG_BLK_DEV_IDE
+		/* overrides PCI-IDE */
+#endif
+
+#ifdef CONFIG_PC_KEYB
+		//not yet kbd_ops = &jmr3927_kbd_ops;
+#endif
+	}
+#ifdef USE_RTC_DS1742
+	if (jmr3927_have_nvram()) {
+		rtc_ops = &jmr3927_rtc_ops;
+	}
+#endif
+
+	/* SIO0 DTR on */
+	jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
+
+	jmr3927_led_set(0);
+
+
+	if (jmr3927_have_isac()) 
+		jmr3927_io_led_set(0);
+	printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
+	       jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
+	       jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
+	       jmr3927_dipsw1(), jmr3927_dipsw2(),
+	       jmr3927_dipsw3(), jmr3927_dipsw4());
+	if (jmr3927_have_isac())
+		printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
+		       jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
+		       jmr3927_io_dipsw());
+}
+static void tx3927_setup(void)
+{
+	int i;
+
+	/* SDRAMC are configured by PROM */
+
+	/* ROMC */
+	tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
+	tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
+	tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
+	tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
+
+	/* CCFG */
+	/* enable Timeout BusError */
+	if (jmr3927_ccfg_toeon)
+		tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
+
+	/* clear BusErrorOnWrite flag */
+	tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
+	/* Disable PCI snoop */
+	tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
+
+#ifdef DO_WRITE_THROUGH
+	/* Enable PCI SNOOP - with write through only */
+	tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
+#endif
+
+	/* Pin selection */
+	tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
+	tx3927_ccfgptr->pcfg |=
+		TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
+		(TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
+
+	printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
+	       tx3927_ccfgptr->crir,
+	       tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
+
+	/* IRC */
+	/* disable interrupt control */
+	tx3927_ircptr->cer = 0;
+	/* mask all IRC interrupts */
+	tx3927_ircptr->imr = 0;
+	for (i = 0; i < TX3927_NUM_IR / 2; i++) {
+		tx3927_ircptr->ilr[i] = 0;
+	}
+	/* setup IRC interrupt mode (Low Active) */
+	for (i = 0; i < TX3927_NUM_IR / 8; i++) {
+		tx3927_ircptr->cr[i] = 0;
+	}
+
+	/* TMR */
+	/* disable all timers */
+	for (i = 0; i < TX3927_NR_TMR; i++) {
+		tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
+		tx3927_tmrptr(i)->tisr = 0;
+		tx3927_tmrptr(i)->cpra = 0xffffffff;
+		tx3927_tmrptr(i)->itmr = 0;
+		tx3927_tmrptr(i)->ccdr = 0;
+		tx3927_tmrptr(i)->pgmr = 0;
+	}
+
+	/* DMA */
+	tx3927_dmaptr->mcr = 0;
+	for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
+		/* reset channel */
+		tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
+		tx3927_dmaptr->ch[i].ccr = 0;
+	}
+	/* enable DMA */
+#ifdef __BIG_ENDIAN
+	tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
+#else
+	tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
+#endif
+
+#ifdef CONFIG_PCI
+	/* PCIC */
+	printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
+	       tx3927_pcicptr->did, tx3927_pcicptr->vid,
+	       tx3927_pcicptr->rid);
+	if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
+		printk("External\n");
+		/* XXX */
+	} else {
+		printk("Internal\n");
+
+		/* Reset PCI Bus */
+		jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
+		udelay(100);
+		jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
+				    JMR3927_IOC_RESET_ADDR);
+		udelay(100);
+		jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
+
+
+		/* Disable External PCI Config. Access */
+		tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
+#ifdef __BIG_ENDIAN
+		tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
+			TX3927_PCIC_LBC_TIBSE |
+			TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
+#endif
+		/* LB->PCI mappings */
+		tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
+		tx3927_pcicptr->ilbioma = mips_pci_io_base;
+		tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
+		tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
+		tx3927_pcicptr->ilbmma = mips_pci_mem_base;
+		tx3927_pcicptr->ipbmma = mips_pci_mem_base;
+		/* PCI->LB mappings */
+		tx3927_pcicptr->iobas = 0xffffffff;
+		tx3927_pcicptr->ioba = 0;
+		tx3927_pcicptr->tlbioma = 0;
+		tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
+		tx3927_pcicptr->mba = 0;
+		tx3927_pcicptr->tlbmma = 0;
+#ifndef JMR3927_INIT_INDIRECT_PCI
+		/* Enable Direct mapping Address Space Decoder */
+		tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
+#endif
+
+		/* Clear All Local Bus Status */
+		tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
+		/* Enable All Local Bus Interrupts */
+		tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
+		/* Clear All PCI Status Error */
+		tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
+		/* Enable All PCI Status Error Interrupts */
+		tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
+
+		/* PCIC Int => IRC IRQ10 */
+		tx3927_pcicptr->il = TX3927_IR_PCI;
+#if 1
+		/* Target Control (per errata) */
+		tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
+#endif
+
+		/* Enable Bus Arbiter */
+#if 0
+		tx3927_pcicptr->req_trace = 0x73737373;
+#endif
+		tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
+
+		tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
+			PCI_COMMAND_MEMORY |
+#if 1
+			PCI_COMMAND_IO |
+#endif
+			PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+	}
+#endif /* CONFIG_PCI */
+
+	/* PIO */
+	/* PIO[15:12] connected to LEDs */
+	tx3927_pioptr->dir = 0x0000f000;
+	tx3927_pioptr->maskcpu = 0;
+	tx3927_pioptr->maskext = 0;
+	{
+		unsigned int conf;
+
+	conf = read_32bit_cp0_register(CP0_CONF);
+               if (!(conf & TX39_CONF_ICE))
+                       printk("TX3927 I-Cache disabled.\n");
+               if (!(conf & TX39_CONF_DCE))
+                       printk("TX3927 D-Cache disabled.\n");
+               else if (!(conf & TX39_CONF_WBON))
+                       printk("TX3927 D-Cache WriteThrough.\n");
+               else if (!(conf & TX39_CONF_CWFON))
+                       printk("TX3927 D-Cache WriteBack.\n");
+               else
+                       printk("TX3927 D-Cache WriteBack (CWF) .\n");
+	}
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/Makefile linux/arch/mips/kernel/Makefile
--- linux.orig/arch/mips/kernel/Makefile	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/Makefile	2002-08-01 06:42:42.000000000 +0000
@@ -6,41 +6,45 @@
 # unless it's something special (ie not a .c file).
 #
 
-.S.s:
-	$(CPP) $(AFLAGS) $< -o $@
-.S.o:
-	$(CC) $(AFLAGS) -c $< -o $@
-
-EXTRA_AFLAGS = -mips3 -mcpu=r4000
+USE_STANDARD_AS_RULE := true
 
 all:	kernel.o head.o init_task.o
 
 O_TARGET := kernel.o
 
+export-objs			= irq.o pci-dma.o setup.o smp.o mips_ksyms.o \
+				  old-irq.o
+
 obj-y				+= branch.o process.o signal.o entry.o \
 				   traps.o ptrace.o vm86.o ioport.o reset.o \
 				   semaphore.o setup.o syscall.o sysmips.o \
 				   ipc.o scall_o32.o unaligned.o
 obj-$(CONFIG_MODULES)		+= mips_ksyms.o
 
-ifdef CONFIG_CPU_R3000
-obj-y	+= r2300_misc.o r2300_fpu.o r2300_switch.o
-else
-obj-y	+= r4k_misc.o r4k_switch.o 
-ifdef CONFIG_CPU_R6000
-obj-y	+= r6000_fpu.o
-else
-obj-y	+= r4k_fpu.o
-endif
-endif
+obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o r2300_switch.o
+obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o r2300_switch.o
+obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R4000)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_VR41XX)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R4300)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R4X00)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R5000)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R5432)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_RM7000)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_NEVADA)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R10000)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_SB1)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_MIPS32)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_MIPS64)	+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R6000)		+= r6000_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)		+= smp.o
 
 # Old style irq support, going to die in 2.5.
-export-objs			+= old-irq.o
 obj-$(CONFIG_NEW_IRQ)		+= irq.o
 obj-$(CONFIG_ROTTEN_IRQ)	+= old-irq.o
 obj-$(CONFIG_I8259)		+= i8259.o
+obj-$(CONFIG_IRQ_CPU)		+= irq_cpu.o
 
 # transition from old time.c to new time.c
 # some boards uses old-time.c, some use time.c, and some use their own ones
@@ -51,13 +55,13 @@
 obj-$(CONFIG_BINFMT_IRIX)	+= irixelf.o irixioctl.o irixsig.o sysirix.o \
 				   irixinv.o
 obj-$(CONFIG_REMOTE_DEBUG)	+= gdb-low.o gdb-stub.o 
-obj-$(CONFIG_PCI)		+= pci-dma.o
 obj-$(CONFIG_PROC_FS)		+= proc.o
 
-ifdef CONFIG_PCI
-obj-$(CONFIG_NEW_PCI)          += pci.o
-obj-$(CONFIG_PCI_AUTO)         += pci_auto.o
+obj-$(CONFIG_NEW_PCI)		+= pci.o
+ifndef CONFIG_MAPPED_PCI_IO
+obj-y				+= pci-dma.o
 endif
+obj-$(CONFIG_PCI_AUTO)		+= pci_auto.o
 
 entry.o: entry.S
 head.o: head.S
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/branch.c linux/arch/mips/kernel/branch.c
--- linux.orig/arch/mips/kernel/branch.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/branch.c	2002-08-01 06:42:44.000000000 +0000
@@ -16,7 +16,6 @@
 #include <asm/inst.h>
 #include <asm/ptrace.h>
 #include <asm/uaccess.h>
-#include <asm/bootinfo.h>
 #include <asm/processor.h>
 
 /*
@@ -164,10 +163,10 @@
 	 * And now the FPA/cp1 branch instructions.
 	 */
 	case cop1_op:
-		if(!(mips_cpu.options & MIPS_CPU_FPU))
+		if (!(mips_cpu.options & MIPS_CPU_FPU))
 			fcr31 = current->thread.fpu.soft.sr;
 		else
-			asm ("cfc1\t%0,$31":"=r" (fcr31));
+			asm("cfc1\t%0,$31":"=r" (fcr31));
 		bit = (insn.i_format.rt >> 2);
 		bit += (bit != 0);
 		bit += 23;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/entry.S linux/arch/mips/kernel/entry.S
--- linux.orig/arch/mips/kernel/entry.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/entry.S	2002-08-01 06:42:34.000000000 +0000
@@ -1,5 +1,4 @@
 /*
-/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -9,15 +8,17 @@
  * Copyright (C) 2001 MIPS Technologies, Inc.
  */
 #include <linux/config.h>
+#include <linux/init.h>
 #include <linux/sys.h>
 
 #include <asm/addrspace.h>
 #include <asm/asm.h>
+#include <asm/cacheops.h>
 #include <asm/current.h>
 #include <asm/errno.h>
 #include <asm/mipsregs.h>
 #include <asm/page.h>
-#include <asm/pgtable.h>
+#include <asm/pgtable-bits.h>
 #include <asm/stackframe.h>
 #include <asm/processor.h>
 #include <asm/regdef.h>
@@ -66,6 +67,7 @@
 		lw	v1, TASK_SIGPENDING($28)
 		bnez	v0, reschedule
 		bnez	v1, signal_return
+		FEXPORT(restore_all)
 restore_all:	.set	noat
 		RESTORE_ALL_AND_RET
 		.set	at
@@ -93,15 +95,89 @@
 		 * Someone tried to fool us by sending an interrupt but we
 		 * couldn't find a cause for it.
 		 */
-		lui     t1,%hi(spurious_count)
-		.set	reorder
-		lw      t0,%lo(spurious_count)(t1)
-		.set	noreorder
+		lui     t1,%hi(irq_err_count)
+		lw      t0,%lo(irq_err_count)(t1)
 		addiu   t0,1
-		sw      t0,%lo(spurious_count)(t1)
+		sw      t0,%lo(irq_err_count)(t1)
 		j	ret_from_irq
 		END(spurious_interrupt)
 
+		__INIT
+
+		.set	reorder
+
+		NESTED(except_vec1_generic, 0, sp)
+		PANIC("Exception vector 1 called")
+		END(except_vec1_generic)
+
+		/*
+		 * General exception vector.  Used for all CPUs except R4000
+		 * and R4400 SC and MC versions.
+		 */
+		NESTED(except_vec3_generic, 0, sp)
+		mfc0	k1, CP0_CAUSE
+		la	k0, exception_handlers
+		andi	k1, k1, 0x7c
+		addu	k0, k0, k1
+		lw	k0, (k0)
+		jr	k0
+		END(except_vec3_generic)
+		.set	at
+
+		/* General exception vector R4000 version. */
+		NESTED(except_vec3_r4000, 0, sp)
+		.set	push
+		.set    mips3
+		.set	noat
+		mfc0	k1, CP0_CAUSE
+		li	k0, 31<<2
+		andi	k1, k1, 0x7c
+		.set	noreorder
+		beq	k1, k0, handle_vced
+		 li	k0, 14<<2
+		beq	k1, k0, handle_vcei
+		 la	k0, exception_handlers
+		.set	reorder
+		addu	k0, k0, k1
+		lw	k0, (k0)
+		jr	k0
+
+		/*
+		 * Big shit, we now may have two dirty primary cache lines for
+		 * the same physical address.  We can savely invalidate the
+		 * line pointed to by c0_badvaddr because after return from
+		 * this exception handler the load / store will be re-executed.
+		 */
+handle_vced:
+		mfc0	k0, CP0_BADVADDR
+		li	k1, -4
+		and	k0, k1
+		mtc0	zero, CP0_TAGLO
+		cache	Index_Store_Tag_D,(k0)
+		cache	Hit_Writeback_Inv_SD,(k0)
+#ifdef CONFIG_PROC_FS
+		lui	k0, %hi(vced_count)
+		lw	k1, %lo(vced_count)(k0)
+		addiu	k1, 1
+		sw	k1, %lo(vced_count)(k0)
+#endif
+		eret
+
+handle_vcei:
+		mfc0	k0, CP0_BADVADDR
+		cache	Hit_Writeback_Inv_SD, (k0)	# also cleans pi
+#ifdef CONFIG_PROC_FS
+		lui	k0, %hi(vcei_count)
+		lw	k1, %lo(vcei_count)(k0)
+		addiu	k1, 1
+		sw	k1, %lo(vcei_count)(k0)
+#endif
+		eret
+		.set    pop
+		END(except_vec3_r4000)
+
+		__FINIT
+
 /*
  * Build a default exception handler for the exceptions that don't need
  * special handlers.  If you didn't know yet - I *like* playing games with
@@ -148,6 +224,7 @@
 		NESTED(handle_##exception, PT_SIZE, sp);                \
 		.set	noat;                                           \
 		SAVE_ALL;                                               \
+		FEXPORT(handle_##exception##_int);			\
 		__BUILD_clear_##clear(exception);                       \
 		.set	at;                                             \
 		__BUILD_##verbose(exception);                           \
@@ -159,16 +236,17 @@
 
 		BUILD_HANDLER(adel,ade,ade,silent)		/* #4  */
 		BUILD_HANDLER(ades,ade,ade,silent)		/* #5  */
-		BUILD_HANDLER(ibe,ibe,cli,verbose)		/* #6  */
-		BUILD_HANDLER(dbe,dbe,cli,silent)		/* #7  */
+		BUILD_HANDLER(ibe,be,cli,silent)		/* #6  */
+		BUILD_HANDLER(dbe,be,cli,silent)		/* #7  */
 		BUILD_HANDLER(bp,bp,sti,silent)			/* #9  */
 		BUILD_HANDLER(ri,ri,sti,silent)			/* #10 */
 		BUILD_HANDLER(cpu,cpu,sti,silent)		/* #11 */
 		BUILD_HANDLER(ov,ov,sti,silent)			/* #12 */
 		BUILD_HANDLER(tr,tr,sti,silent)			/* #13 */
 		BUILD_HANDLER(fpe,fpe,fpe,silent)		/* #15 */
-		BUILD_HANDLER(watch,watch,sti,verbose)		/* #23 */
-		BUILD_HANDLER(reserved,reserved,sti,verbose)	/* others */
+		BUILD_HANDLER(watch,watch,sti,silent)		/* #23 */
+		BUILD_HANDLER(mcheck,mcheck,cli,silent)		/* #24 */
+		BUILD_HANDLER(reserved,reserved,sti,silent)	/* others */
 
 		.set	pop
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/gdb-low.S linux/arch/mips/kernel/gdb-low.S
--- linux.orig/arch/mips/kernel/gdb-low.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/gdb-low.S	2002-08-01 06:42:35.000000000 +0000
@@ -145,9 +145,9 @@
  * FPU control registers
  */
 
-		mfc1	v0,CP1_STATUS
+		cfc1	v0,CP1_STATUS
 		sw	v0,GDB_FR_FSR(sp)
-		mfc1	v0,CP1_REVISION
+		cfc1	v0,CP1_REVISION
 		sw	v0,GDB_FR_FIR(sp)
 
 /*
@@ -304,7 +304,7 @@
 		lw	v1,GDB_FR_REG3(sp)
 		lw	v0,GDB_FR_REG2(sp)
 		lw	$1,GDB_FR_REG1(sp)
-#ifdef CONFIG_CPU_R3000
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 		lw	k0, GDB_FR_EPC(sp)
 		lw	sp, GDB_FR_REG29(sp)		/* Deallocate stack */
 		jr	k0
@@ -321,11 +321,7 @@
 		END(trap_low)
 
 LEAF(kgdb_read_byte)
-		.set push
-		.set noreorder
-		.set nomacro
 4:		lb	t0, (a0)
-		.set pop
 		sb	t0, (a1)
 		li	v0, 0
 		jr	ra
@@ -335,11 +331,7 @@
 		END(kgdb_read_byte)
 
 LEAF(kgdb_write_byte)
-		.set push
-		.set noreorder
-		.set nomacro
 5:		sb	a0, (a1)
-		.set pop
 		li	v0, 0
 		jr	ra
 		.section __ex_table,"a"
@@ -349,6 +341,7 @@
 
 		.type	kgdbfault@function
 		.ent	kgdbfault
+
 kgdbfault:	li	v0, -EFAULT
 		jr	ra
 		.end	kgdbfault
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/gdb-stub.c linux/arch/mips/kernel/gdb-stub.c
--- linux.orig/arch/mips/kernel/gdb-stub.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/gdb-stub.c	2002-08-01 06:42:48.000000000 +0000
@@ -11,8 +11,6 @@
  *  Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
  *
  *  Copyright (C) 1995 Andreas Busse
- *
- * $Id: gdb-stub.c,v 1.6 1999/05/01 22:40:35 ralf Exp $
  */
 
 /*
@@ -121,6 +119,7 @@
  *
  */
 
+#include <linux/config.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
 #include <linux/signal.h>
@@ -578,7 +577,7 @@
 	async_bp.addr = epc;
 	async_bp.val  = *(unsigned *)epc;
 	*(unsigned *)epc = BP;
-	flush_cache_all();
+	__flush_cache_all();
 }
 
 
@@ -805,7 +804,7 @@
 			 * NB: We flush both caches, just to be sure...
 			 */
 
-			flush_cache_all();
+			__flush_cache_all();
 			return;
 			/* NOTREACHED */
 			break;
@@ -834,7 +833,7 @@
 			 * use breakpoints and continue, instead.
 			 */
 			single_step(regs);
-			flush_cache_all();
+			__flush_cache_all();
 			return;
 			/* NOTREACHED */
 
@@ -925,9 +924,8 @@
 
 #ifdef CONFIG_GDB_CONSOLE
 
-void gdb_puts(const char *str)
+void gdb_putsn(const char *str, int l)
 {
-	int l = strlen(str);
 	char outbuf[18];
 
 	outbuf[0]='O';
@@ -949,7 +947,7 @@
 
 static void gdb_console_write(struct console *con, const char *s, unsigned n)
 {
-	gdb_puts(s);
+	gdb_putsn(s, n);
 }
 
 static struct console gdb_console = {
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/head.S linux/arch/mips/kernel/head.S
--- linux.orig/arch/mips/kernel/head.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/head.S	2002-08-01 06:42:32.000000000 +0000
@@ -1,6 +1,4 @@
 /*
- * arch/mips/kernel/head.S
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -13,550 +11,214 @@
  * Further modifications by David S. Miller and Harald Koerfgen
  * Copyright (C) 1999 Silicon Graphics, Inc.
  *
- * Head.S contains the MIPS exception handler and startup code.
- *
- **************************************************************************
- *  9 Nov, 2000.
- *  Added Cache Error exception handler and SBDDP EJTAG debug exception.
- *
- *  Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- **************************************************************************
+ * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  */
 #include <linux/config.h>
+#include <linux/init.h>
 #include <linux/threads.h>
 
 #include <asm/asm.h>
-#include <asm/cacheops.h>
 #include <asm/current.h>
 #include <asm/offset.h>
+#include <asm/pgtable-bits.h>
 #include <asm/processor.h>
 #include <asm/regdef.h>
 #include <asm/cachectl.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
-#include <asm/bootinfo.h>
-
-	.text
-	/*
-	 * Reserved space for exception handlers.
-	 * Necessary for machines which link their kernels at KSEG0.
-	 * FIXME: Use the initcode feature to get rid of unused handler
-	 * variants.
-	 */
-	.fill	0x280
-/*	
- * This is space for the interrupt handlers.
- * After trap_init() they are located at virtual address KSEG0.
- *
- * These handlers much be written in a relocatable manner
- * because based upon the cpu type an arbitrary one of the
- * following pieces of code will be copied to the KSEG0
- * vector location.
- */
-	/* TLB refill, EXL == 0, R4xx0, non-R4600 version */
-	.set	noreorder
-	.set	noat
-	LEAF(except_vec0_r4000)
-	.set	mips3
-#ifdef CONFIG_SMP
-	mfc0	k1, CP0_CONTEXT
-	la	k0, current_pgd
-	srl	k1, 23
-	sll	k1, 2
-	addu	k1, k0, k1
-	lw	k1, (k1)
-#else 
-	lw	k1, current_pgd			# get pgd pointer
-#endif	
-	mfc0	k0, CP0_BADVADDR		# Get faulting address
-	srl	k0, k0, 22			# get pgd only bits
-
-	sll	k0, k0, 2
-	addu	k1, k1, k0			# add in pgd offset
-	mfc0	k0, CP0_CONTEXT			# get context reg
-	lw	k1, (k1)
-#if defined(CONFIG_CPU_VR41XX)
-	srl	k0, k0, 3			# get pte offset
-#else
-	srl	k0, k0, 1			# get pte offset
-#endif
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0			# add in offset
-	lw	k0, 0(k1)			# get even pte
-	lw	k1, 4(k1)			# get odd pte
-	srl	k0, k0, 6			# convert to entrylo0
-	mtc0	k0, CP0_ENTRYLO0		# load it
-	srl	k1, k1, 6			# convert to entrylo1
-	mtc0	k1, CP0_ENTRYLO1		# load it
-	b	1f
-	tlbwr					# write random tlb entry
-1:
-	nop
-	eret					# return from trap
-	END(except_vec0_r4000)
-
-	/* TLB refill, EXL == 0, R4600 version */
-	LEAF(except_vec0_r4600)
-	.set	mips3
-	mfc0	k0, CP0_BADVADDR
-	srl	k0, k0, 22
-	lw	k1, current_pgd			# get pgd pointer
-	sll	k0, k0, 2
-	addu	k1, k1, k0
-	mfc0	k0, CP0_CONTEXT
-	lw	k1, (k1)
-	srl	k0, k0, 1
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0
-	lw	k0, 0(k1)
-	lw	k1, 4(k1)
-	srl	k0, k0, 6
-	mtc0	k0, CP0_ENTRYLO0
-	srl	k1, k1, 6
-	mtc0	k1, CP0_ENTRYLO1
-	nop
-	tlbwr
-	nop
-	eret
-	END(except_vec0_r4600)
-
-	/* TLB refill, EXL == 0, R52x0 "Nevada" version */
-        /*
-         * This version has a bug workaround for the Nevada.  It seems
-         * as if under certain circumstances the move from cp0_context
-         * might produce a bogus result when the mfc0 instruction and
-         * it's consumer are in a different cacheline or a load instruction,
-         * probably any memory reference, is between them.  This is
-         * potencially slower than the R4000 version, so we use this
-         * special version.
-         */
-	.set	noreorder
-	.set	noat
-	LEAF(except_vec0_nevada)
-	.set	mips3
-	mfc0	k0, CP0_BADVADDR		# Get faulting address
-	srl	k0, k0, 22			# get pgd only bits
-	lw	k1, current_pgd			# get pgd pointer
-	sll	k0, k0, 2
-	addu	k1, k1, k0			# add in pgd offset
-	lw	k1, (k1)
-	mfc0	k0, CP0_CONTEXT			# get context reg
-	srl	k0, k0, 1			# get pte offset
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0			# add in offset
-	lw	k0, 0(k1)			# get even pte
-	lw	k1, 4(k1)			# get odd pte
-	srl	k0, k0, 6			# convert to entrylo0
-	mtc0	k0, CP0_ENTRYLO0		# load it
-	srl	k1, k1, 6			# convert to entrylo1
-	mtc0	k1, CP0_ENTRYLO1		# load it
-	nop					# QED specified nops
-	nop
-	tlbwr					# write random tlb entry
-	nop					# traditional nop
-	eret					# return from trap
-	END(except_vec0_nevada)
-
-	/* TLB refill, EXL == 0, R4[40]00/R5000 badvaddr hwbug version */
-	LEAF(except_vec0_r45k_bvahwbug)
-	.set	mips3
-	mfc0	k0, CP0_BADVADDR
-	srl	k0, k0, 22
-	lw	k1, current_pgd			# get pgd pointer
-	sll	k0, k0, 2
-	addu	k1, k1, k0
-	mfc0	k0, CP0_CONTEXT
-	lw	k1, (k1)
-	srl	k0, k0, 1
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0
-	lw	k0, 0(k1)
-	lw	k1, 4(k1)
-	nop				/* XXX */
-	tlbp
-	srl	k0, k0, 6
-	mtc0	k0, CP0_ENTRYLO0
-	srl	k1, k1, 6
-	mfc0	k0, CP0_INDEX
-	mtc0	k1, CP0_ENTRYLO1
-	bltzl	k0, 1f
-	tlbwr
-1:
-	nop
-	eret
-	END(except_vec0_r45k_bvahwbug)
-
-#ifdef CONFIG_SMP
-	/* TLB refill, EXL == 0, R4000 MP badvaddr hwbug version */
-	LEAF(except_vec0_r4k_mphwbug)
-	.set	mips3
-	mfc0	k0, CP0_BADVADDR
-	srl	k0, k0, 22
-	lw	k1, current_pgd			# get pgd pointer
-	sll	k0, k0, 2
-	addu	k1, k1, k0
-	mfc0	k0, CP0_CONTEXT
-	lw	k1, (k1)
-	srl	k0, k0, 1
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0
-	lw	k0, 0(k1)
-	lw	k1, 4(k1)
-	nop				/* XXX */
-	tlbp
-	srl	k0, k0, 6
-	mtc0	k0, CP0_ENTRYLO0
-	srl	k1, k1, 6
-	mfc0	k0, CP0_INDEX
-	mtc0	k1, CP0_ENTRYLO1
-	bltzl	k0, 1f
-	tlbwr
-1:
-	nop
-	eret
-	END(except_vec0_r4k_mphwbug)
-#endif
-
-	/* TLB refill, EXL == 0, R4000 UP 250MHZ entrylo[01] hwbug version */
-	LEAF(except_vec0_r4k_250MHZhwbug)
-	.set	mips3
-	mfc0	k0, CP0_BADVADDR
-	srl	k0, k0, 22
-	lw	k1, current_pgd			# get pgd pointer
-	sll	k0, k0, 2
-	addu	k1, k1, k0
-	mfc0	k0, CP0_CONTEXT
-	lw	k1, (k1)
-	srl	k0, k0, 1
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0
-	lw	k0, 0(k1)
-	lw	k1, 4(k1)
-	srl	k0, k0, 6
-	mtc0	zero, CP0_ENTRYLO0
-	mtc0	k0, CP0_ENTRYLO0
-	srl	k1, k1, 6
-	mtc0	zero, CP0_ENTRYLO1
-	mtc0	k1, CP0_ENTRYLO1
-	b	1f
-	tlbwr
-1:
-	nop
-	eret
-	END(except_vec0_r4k_250MHZhwbug)
-
-#ifdef CONFIG_SMP
-	/* TLB refill, EXL == 0, R4000 MP 250MHZ entrylo[01]+badvaddr bug version */
-	LEAF(except_vec0_r4k_MP250MHZhwbug)
-	.set	mips3
-	mfc0	k0, CP0_BADVADDR
-	srl	k0, k0, 22
-	lw	k1, current_pgd			# get pgd pointer
-	sll	k0, k0, 2
-	addu	k1, k1, k0
-	mfc0	k0, CP0_CONTEXT
-	lw	k1, (k1)
-	srl	k0, k0, 1
-	and	k0, k0, 0xff8
-	addu	k1, k1, k0
-	lw	k0, 0(k1)
-	lw	k1, 4(k1)
-	nop				/* XXX */
-	tlbp
-	srl	k0, k0, 6
-	mtc0	zero, CP0_ENTRYLO0
-	mtc0	k0, CP0_ENTRYLO0
-	mfc0	k0, CP0_INDEX
-	srl	k1, k1, 6
-	mtc0	zero, CP0_ENTRYLO1
-	mtc0	k1, CP0_ENTRYLO1
-	bltzl	k0, 1f
-	tlbwr
-1:
-	nop
-	eret
-	END(except_vec0_r4k_MP250MHZhwbug)
-#endif
-
-	/* TLB refill, R[23]00 version */
-	LEAF(except_vec0_r2300)
-	.set	noat
-	.set	mips1
-	mfc0	k0, CP0_BADVADDR
-	lw	k1, current_pgd			# get pgd pointer
-	srl	k0, k0, 22
-	sll	k0, k0, 2
-	addu	k1, k1, k0
-	mfc0	k0, CP0_CONTEXT
-	lw	k1, (k1)
-	and	k0, k0, 0xffc
-	addu	k1, k1, k0
-	lw	k0, (k1)
-	nop
-	mtc0	k0, CP0_ENTRYLO0
-	mfc0	k1, CP0_EPC
-	tlbwr
-	jr	k1
-	rfe
-	END(except_vec0_r2300)
-
-
-	/* XTLB refill, EXL == 0, R4xx0 cpus only use this... */
-	NESTED(except_vec1_generic, 0, sp)
-	.set	noat
-	.set	mips3
-	/* Register saving is delayed as long as we don't know
-	 * which registers really need to be saved.
-	 */
-	mfc0	k1, CP0_CONTEXT
-	dsra	k1, 1
-	lwu	k0,  (k1)		# May cause another exception
-	lwu	k1, 4(k1)
-	dsrl	k0, 6			# Convert to EntryLo format
-	dsrl	k1, 6			# Convert to EntryLo format
-	dmtc0	k0, CP0_ENTRYLO0
-	dmtc0	k1, CP0_ENTRYLO1
-	nop				# Needed for R4[04]00 pipeline
-	tlbwr
-	nop				# Needed for R4[04]00 pipeline
-	nop
-	nop
-	eret
-	nop				/* Workaround for R4000 bug. */
-	eret
-	END(except_vec1_generic)
-
-	/* Cache Error */
-	LEAF(except_vec2_generic)
-	.set	noat
-	.set    mips0
-	/*
-	 * This is a very bad place to be.  Our cache error
-	 * detection has triggered.  If we have write-back data
-	 * in the cache, we may not be able to recover.  As a
-	 * first-order desperate measure, turn off KSEG0 cacheing.
-	 */
-	mfc0	k0,CP0_CONFIG
-	li	k1,~CONF_CM_CMASK
-	and	k0,k0,k1
-	ori	k0,k0,CONF_CM_UNCACHED
-	mtc0	k0,CP0_CONFIG
-	/* Give it a few cycles to sink in... */
-	nop
-	nop
-	nop
-
-	j	cache_parity_error
-	nop
-	END(except_vec2_generic)
-
-	/* General exception vector R4000 version. */
-	NESTED(except_vec3_r4000, 0, sp)
-	.set	noat
-	mfc0	k1, CP0_CAUSE
-	andi	k1, k1, 0x7c
-	li	k0, 31<<2
-	beq	k1, k0, handle_vced
-	 li	k0, 14<<2
-	beq	k1, k0, handle_vcei
-	 la	k0, exception_handlers
-	addu	k0, k0, k1
-	lw	k0, (k0)
-	nop
-	jr	k0
-	 nop
-
-/*
- * Big shit, we now may have two dirty primary cache lines for the same
- * physical address.  We can savely invalidate the line pointed to by
- * c0_badvaddr because after return from this exception handler the load /
- * store will be re-executed.
- */
-	.set    mips3
-handle_vced:
-	mfc0	k0, CP0_BADVADDR
- li k1, -4
- and k0, k1
-	mtc0	zero, CP0_TAGLO
-	cache	Index_Store_Tag_D,(k0)
-	cache	Hit_Writeback_Inv_SD,(k0)
-#ifdef CONFIG_PROC_FS
-	lui	k0, %hi(vced_count)
-	lw	k1, %lo(vced_count)(k0)
-	addiu	k1, 1
-	sw	k1, %lo(vced_count)(k0)
-#endif
-	eret
-
-handle_vcei:
-	mfc0	k0, CP0_BADVADDR
-	cache	Hit_Writeback_Inv_SD,(k0)		# also cleans pi
-#ifdef CONFIG_PROC_FS
-	lui	k0, %hi(vcei_count)
-	lw	k1, %lo(vcei_count)(k0)
-	addiu	k1, 1
-	sw	k1, %lo(vcei_count)(k0)
-#endif
-	eret
-
-	END(except_vec3_r4000)
-	.set	at
-
-	/* General exception vector. */
-	NESTED(except_vec3_generic, 0, sp)
-	.set	noat
-	.set	mips0
-	mfc0	k1, CP0_CAUSE
-	la	k0, exception_handlers
-	andi	k1, k1, 0x7c
-	addu	k0, k0, k1
-	lw	k0, (k0)
-	nop
-	jr	k0
-	 nop
-	END(except_vec3_generic)
-	.set	at
-
-	/*
-	 * Special interrupt vector for embedded MIPS.  This is a
-	 * dedicated interrupt vector which reduces interrupt processing
-	 * overhead.  The jump instruction will be inserted here at
-	 * initialization time.  This handler may only be 8 bytes in size!
-	 */
-	NESTED(except_vec4, 0, sp)
-1:	j	1b			/* Dummy, will be replaced */
-	 nop
-	END(except_vec4)
-
-	/*
-	 * SBDDP EJTAG debug exception handler.
-	 * The EJTAG debug exception entry point is 0xbfc00480, which
-	 * normally is in the boot PROM, so the boot PROM must do a
-	 * unconditional jump to this vector.
-	 */	
-	NESTED(except_vec_ejtag_debug, 0, sp)
-	j	ejtag_debug_handler
-	 nop
-	END(except_vec_ejtag_debug)
-
-	/*
-	 * EJTAG debug exception handler.
-	 */
-	NESTED(ejtag_debug_handler, PT_SIZE, sp)
-	.set	noat
-	.set	noreorder
-	SAVE_ALL
-	PRINT("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
-	mfc0	k0, $23         # Get EJTAG Debug register.
-	mfc0    k1, $24         # Get DEPC register.
-	bgez	k0, 1f
-	 addiu	k1, k1, 4	# SBDDP inst. in delay slot.
-	addiu	k1, k1, 4
-1:	mtc0	k1, $24
-	RESTORE_ALL
-	.word	0x4200001f      # deret, return EJTAG debug exception.
-	 nop
-	.set	at
-	END(ejtag_debug_handler)
 
-		
-/*
- * Kernel entry point
- */
-NESTED(kernel_entry, 16, sp)
-	.set	noreorder
-	/* The following two symbols are used for kernel profiling. */
-	EXPORT(stext)
-	EXPORT(_stext)
-
-	/*
-	 * Stack for kernel and init, current variable
-	 */
-	la	$28, init_task_union
-	addiu	t0, $28, KERNEL_STACK_SIZE-32
-	subu	sp, t0, 4*SZREG
-
-	sw	t0, kernelsp
-	/* The firmware/bootloader passes argc/argp/envp
-	 * to us as arguments.  But clear bss first because
-	 * the romvec and other important info is stored there
-	 * by prom_init().
-	 */
-	la	t0, _edata
-	sw	zero, (t0)
-	la	t1, (_end - 4)
-1:
-	addiu	t0, 4
-	bne	t0, t1, 1b
-	 sw	zero, (t0)
-
-	jal	init_arch
-	 nop
-	END(kernel_entry)
+		.text
+		/*
+		 * Reserved space for exception handlers.
+		 * Necessary for machines which link their kernels at KSEG0.
+		 */
+		.fill	0x400
+
+		__INIT
+
+		/* Cache Error */
+		LEAF(except_vec2_generic)
+		.set	noreorder
+		.set	noat
+		.set    mips0
+		/*
+		 * This is a very bad place to be.  Our cache error
+		 * detection has triggered.  If we have write-back data
+		 * in the cache, we may not be able to recover.  As a
+		 * first-order desperate measure, turn off KSEG0 cacheing.
+		 */
+		mfc0	k0,CP0_CONFIG
+		li	k1,~CONF_CM_CMASK
+		and	k0,k0,k1
+		ori	k0,k0,CONF_CM_UNCACHED
+		mtc0	k0,CP0_CONFIG
+		/* Give it a few cycles to sink in... */
+		nop
+		nop
+		nop
+
+		j	cache_parity_error
+		nop
+		END(except_vec2_generic)
+
+		.set	at
+
+		/*
+		 * Special interrupt vector for embedded MIPS.  This is a
+		 * dedicated interrupt vector which reduces interrupt processing
+		 * overhead.  The jump instruction will be inserted here at
+		 * initialization time.  This handler may only be 8 bytes in
+		 * size!
+		 */
+		NESTED(except_vec4, 0, sp)
+1:		j	1b			/* Dummy, will be replaced */
+		 nop
+		END(except_vec4)
+
+		/*
+		 * EJTAG debug exception handler.
+		 * The EJTAG debug exception entry point is 0xbfc00480, which
+		 * normally is in the boot PROM, so the boot PROM must do a
+		 * unconditional jump to this vector.
+		 */	
+		NESTED(except_vec_ejtag_debug, 0, sp)
+		j	ejtag_debug_handler
+		 nop
+		END(except_vec_ejtag_debug)
+
+		/*
+		 * EJTAG debug exception handler.
+		 */
+		NESTED(ejtag_debug_handler, PT_SIZE, sp)
+		.set	noat
+		.set	noreorder
+		mtc0	k0, CP0_DESAVE
+		mfc0	k0, CP0_DEBUG	
+
+		sll	k0, k0, 30	# Check for SDBBP.
+		bgez	k0, ejtag_return
+
+		la	k0, ejtag_debug_buffer
+		sw	k1, 0(k0)
+		SAVE_ALL
+		jal	ejtag_exception_handler
+		 move	a0, sp
+		RESTORE_ALL
+		la	k0, ejtag_debug_buffer
+		lw	k1, 0(k0)	
+
+ejtag_return:
+		mfc0	k0, CP0_DESAVE	
+		.word	0x4200001f     # DERET, return from EJTAG debug exception.
+		 nop
+		.set	at
+		END(ejtag_debug_handler)
+	
+		/*
+		* NMI debug exception handler for MIPS reference boards.
+		* The NMI debug exception entry point is 0xbfc00000, which
+		* normally is in the boot PROM, so the boot PROM must do a
+		* unconditional jump to this vector.
+		*/
+		NESTED(except_vec_nmi, 0, sp)
+		j       nmi_handler
+		 nop
+		END(except_vec_nmi)
+
+		NESTED(nmi_handler, PT_SIZE, sp)
+		.set    noat
+		.set    noreorder
+		.set    mips3
+		SAVE_ALL
+		jal     nmi_exception_handler
+		 move   a0, sp
+		RESTORE_ALL
+		eret
+		.set    at
+		.set    mips0
+		END(nmi_handler)	
+
+		/*
+		 * Kernel entry point
+		 */
+		NESTED(kernel_entry, 16, sp)
+		.set	noreorder
+		/* The following two symbols are used for kernel profiling. */
+		EXPORT(stext)
+		EXPORT(_stext)
+
+		/*
+		 * Stack for kernel and init, current variable
+		 */
+		la	$28, init_task_union
+		addiu	t0, $28, KERNEL_STACK_SIZE-32
+		subu	sp, t0, 4*SZREG
+
+		sw	t0, kernelsp
+		/* The firmware/bootloader passes argc/argp/envp
+		 * to us as arguments.  But clear bss first because
+		 * the romvec and other important info is stored there
+		 * by prom_init().
+		 */
+		la	t0, _edata
+		sw	zero, (t0)
+		la	t1, (_end - 4)
+1:
+		addiu	t0, 4
+		bne	t0, t1, 1b
+		 sw	zero, (t0)
+
+		jal	init_arch
+		 nop
+		END(kernel_entry)
 
 
 #ifdef CONFIG_SMP
 
 /*
- * SMP slave cpus entry point.  Board specific code
- * for bootstrap calls this function after setting up
- * the stack and gp registers. 
- */
-	LEAF(smp_bootstrap)
-	.set push
-	.set noreorder
-	mtc0	zero, CP0_WIRED
-	CLI
-	mfc0	t0, CP0_STATUS
-	li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV); 
-	and	t0, t1
-	or	t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR);
-	addiu	a0, zero, 0
-	jal	start_secondary
-         mtc0	t0, CP0_STATUS
-	.set pop
-	END(smp_bootstrap)
-#endif
-	
-/*
- * This buffer is reserved for the use of the cache error handler.
+ * SMP slave cpus entry point.  Board specific code for bootstrap calls this
+ * function after setting up the stack and gp registers. 
  */
+		LEAF(smp_bootstrap)
+		.set push
+		.set noreorder
+		mtc0	zero, CP0_WIRED
+		CLI
+		mfc0	t0, CP0_STATUS
+		li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX)
+		and	t0, t1
+		or	t0, (ST0_CU0);
+		jal	start_secondary
+		mtc0	t0, CP0_STATUS
+		.set pop
+		END(smp_bootstrap)
+#endif
+
+		__FINIT
+
+		/*
+		 * This buffer is reserved for the use of the EJTAG debug 
+		 * handler.
+		 */
 		.data
-		EXPORT(cache_error_buffer)
-		.fill	32*4,1,0
-
-#ifndef CONFIG_SMP
-EXPORT(kernelsp)
-		PTR	0
-EXPORT(current_pgd)
-		PTR     0
-#else
-		/* There's almost certainly a better way to do this with the macros...*/
-		.globl kernelsp
-		.comm  kernelsp,     NR_CPUS * 8, 8
-		.globl current_pgd
-		.comm	current_pgd, NR_CPUS * 8, 8
-#endif
-		.text
-		.org	0x1000
-EXPORT(swapper_pg_dir)
-
-		.org	0x2000
-EXPORT(empty_bad_page)
-
-		.org	0x3000
-EXPORT(empty_bad_page_table)
+		EXPORT(ejtag_debug_buffer)
+		.fill	4
+	
+		.comm	kernelsp,    NR_CPUS * 8, 8
+		.comm	pgd_current, NR_CPUS * 8, 8
 
-		.org	0x4000
-EXPORT(invalid_pte_table)
-
-		.org	0x5000
-/* XXX This label is required to keep GAS trying to be too clever ...
-   Bug?  */
-dummy:
-/*
- * Align to 8kb boundary for init_task_union which follows in the
- * .text segment.
- */
-		.align	13
+	.macro	page name, order=0
+	.globl	\name
+\name:	.size	\name, (_PAGE_SIZE << \order)
+	.org	. + (_PAGE_SIZE << \order)
+	.type	\name, @object
+	.endm
+
+	.data
+	.align	12
+
+	page	swapper_pg_dir, _PGD_ORDER
+	page	empty_bad_page, 0
+	page	empty_bad_page_table, 0
+	page	invalid_pte_table, 0
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/i8259.c linux/arch/mips/kernel/i8259.c
--- linux.orig/arch/mips/kernel/i8259.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/i8259.c	2002-08-01 06:42:33.000000000 +0000
@@ -11,7 +11,6 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
@@ -30,7 +29,7 @@
  * moves to arch independent land
  */
 
-spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
+static spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
 
 static void end_8259A_irq (unsigned int irq)
 {
@@ -69,9 +68,8 @@
  */
 static unsigned int cached_irq_mask = 0xffff;
 
-#define __byte(x,y) 	(((unsigned char *)&(y))[x])
-#define cached_21	(__byte(0,cached_irq_mask))
-#define cached_A1	(__byte(1,cached_irq_mask))
+#define cached_21	(cached_irq_mask)
+#define cached_A1	(cached_irq_mask >> 8)
 
 void disable_8259A_irq(unsigned int irq)
 {
@@ -211,7 +209,7 @@
 			printk("spurious 8259A interrupt: IRQ%d.\n", irq);
 			spurious_irq_mask |= irqmask;
 		}
-		irq_err_count++;
+		atomic_inc(&irq_err_count);
 		/*
 		 * Theoretically we do not have to handle this IRQ,
 		 * but in Linux this does not cause problems and is
@@ -234,7 +232,7 @@
 	 * outb_p - this has to work on a wide range of PC hardware.
 	 */
 	outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
-	outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
+	outb_p(0x00, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */
 	outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
 	if (auto_eoi)
 		outb_p(0x03, 0x21);	/* master does Auto EOI */
@@ -242,7 +240,7 @@
 		outb_p(0x01, 0x21);	/* master expects normal EOI */
 
 	outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
-	outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
+	outb_p(0x08, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */
 	outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
 	outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
 				    is to be investigated) */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/init_task.c linux/arch/mips/kernel/init_task.c
--- linux.orig/arch/mips/kernel/init_task.c	2001-09-17 22:29:09.000000000 +0000
+++ linux/arch/mips/kernel/init_task.c	2002-08-01 06:42:36.000000000 +0000
@@ -20,5 +20,5 @@
  * The things we do for performance..
  */
 union task_union init_task_union
-	__attribute__((__section__(".text"))) =
+	__attribute__((__section__(".data.init_task"))) =
 		{ INIT_TASK(init_task_union.task) };
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/irix5sys.h linux/arch/mips/kernel/irix5sys.h
--- linux.orig/arch/mips/kernel/irix5sys.h	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/kernel/irix5sys.h	2002-08-01 06:42:29.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: irix5sys.h,v 1.2 1998/08/17 10:16:25 ralf Exp $
- *
+/*
  * irix5sys.h: 32-bit IRIX5 ABI system call table.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/irixelf.c linux/arch/mips/kernel/irixelf.c
--- linux.orig/arch/mips/kernel/irixelf.c	2001-03-19 20:35:09.000000000 +0000
+++ linux/arch/mips/kernel/irixelf.c	2002-08-01 06:42:45.000000000 +0000
@@ -23,7 +23,6 @@
 #include <linux/string.h>
 #include <linux/file.h>
 #include <linux/fcntl.h>
-#include <linux/ptrace.h>
 #include <linux/slab.h>
 #include <linux/shm.h>
 #include <linux/personality.h>
@@ -32,6 +31,7 @@
 
 #include <asm/uaccess.h>
 #include <asm/pgalloc.h>
+#include <asm/ptrace.h>
 #include <asm/mipsregs.h>
 #include <asm/prctl.h>
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/irixinv.c linux/arch/mips/kernel/irixinv.c
--- linux.orig/arch/mips/kernel/irixinv.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/kernel/irixinv.c	2002-08-01 06:42:31.000000000 +0000
@@ -4,8 +4,6 @@
  * use the linked lists for the inventory yet. 
  *
  * Miguel de Icaza, 1997.
- *
- * $Id: irixinv.c,v 1.3 1998/04/05 11:23:51 ralf Exp $
  */
 #include <linux/mm.h>
 #include <linux/init.h>
@@ -79,3 +77,5 @@
 	add_to_inventory (2, 2, 0, 1, 0);
 	add_to_inventory (7, 14, 0, 0, 6);
 }
+
+module_init(init_inventory);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/irq.c linux/arch/mips/kernel/irq.c
--- linux.orig/arch/mips/kernel/irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/irq.c	2002-08-01 06:42:33.000000000 +0000
@@ -8,17 +8,22 @@
  * Copyright (C) 1992 Linus Torvalds
  * Copyright (C) 1994 - 2000 Ralf Baechle
  */
+#include <linux/config.h>
 #include <linux/kernel.h>
-#include <linux/irq.h>
+#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/proc_fs.h>
 #include <linux/slab.h>
 #include <linux/mm.h>
 #include <linux/random.h>
 #include <linux/sched.h>
 
+#include <asm/atomic.h>
 #include <asm/system.h>
+#include <asm/uaccess.h>
 
 /*
  * Controller mappings for all interrupt sources:
@@ -63,7 +68,7 @@
 	end_none
 };
 
-volatile unsigned long irq_err_count, spurious_count;
+atomic_t irq_err_count;
 
 /*
  * Generic, controller-independent functions:
@@ -71,13 +76,13 @@
 
 int get_irq_list(char *buf)
 {
+	int i, j;
 	struct irqaction * action;
 	char *p = buf;
-	int i;
 
 	p += sprintf(p, "           ");
-	for (i=0; i < 1 /*smp_num_cpus*/; i++)
-		p += sprintf(p, "CPU%d       ", i);
+	for (j=0; j<smp_num_cpus; j++)
+		p += sprintf(p, "CPU%d       ",j);
 	*p++ = '\n';
 
 	for (i = 0 ; i < NR_IRQS ; i++) {
@@ -85,7 +90,13 @@
 		if (!action) 
 			continue;
 		p += sprintf(p, "%3d: ",i);
+#ifndef CONFIG_SMP
 		p += sprintf(p, "%10u ", kstat_irqs(i));
+#else
+		for (j = 0; j < smp_num_cpus; j++)
+			p += sprintf(p, "%10u ",
+				kstat.irqs[cpu_logical_map(j)][i]);
+#endif
 		p += sprintf(p, " %14s", irq_desc[i].handler->typename);
 		p += sprintf(p, "  %s", action->name);
 
@@ -93,10 +104,182 @@
 			p += sprintf(p, ", %s", action->name);
 		*p++ = '\n';
 	}
-	p += sprintf(p, "ERR: %10lu\n", irq_err_count);
+	p += sprintf(p, "\n");
+	p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
 	return p - buf;
 }
 
+#ifdef CONFIG_SMP
+int global_irq_holder = NO_PROC_ID;
+spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED;
+
+/*
+ * Most of this code is take from the mips64 tree (ip27-irq.c).  It's virtually
+ * identical to the i386 implentation in arh/i386/irq.c, with translations for
+ * the interrupt enable bit
+ */
+
+#define MAXCOUNT 		100000000
+#define SYNC_OTHER_CORES(x)	udelay(x+1)
+
+static inline void wait_on_irq(int cpu)
+{
+	int count = MAXCOUNT;
+
+	for (;;) {
+
+		/*
+		 * Wait until all interrupts are gone. Wait
+		 * for bottom half handlers unless we're
+		 * already executing in one..
+		 */
+		if (!irqs_running())
+			if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock))
+				break;
+
+		/* Duh, we have to loop. Release the lock to avoid deadlocks */
+		spin_unlock(&global_irq_lock);
+
+		for (;;) {
+			if (!--count) {
+				printk("Count spun out.  Huh?\n");
+				count = ~0;
+			}
+			__sti();
+			SYNC_OTHER_CORES(cpu);
+			__cli();
+			if (irqs_running())
+				continue;
+			if (spin_is_locked(&global_irq_lock))
+				continue;
+			if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock))
+				continue;
+			if (spin_trylock(&global_irq_lock))
+				break;
+		}
+	}
+}
+
+/*
+ * This is called when we want to synchronize with
+ * interrupts. We may for example tell a device to
+ * stop sending interrupts: but to make sure there
+ * are no interrupts that are executing on another
+ * CPU we need to call this function.
+ */
+void synchronize_irq(void)
+{
+	if (irqs_running()) {
+		/* Stupid approach */
+		cli();
+		sti();
+	}
+}
+
+static inline void get_irqlock(int cpu)
+{
+	if (!spin_trylock(&global_irq_lock)) {
+		/* do we already hold the lock? */
+		if ((unsigned char) cpu == global_irq_holder)
+			return;
+		/* Uhhuh.. Somebody else got it. Wait.. */
+		spin_lock(&global_irq_lock);
+	}
+	/*
+	 * We also to make sure that nobody else is running
+	 * in an interrupt context.
+	 */
+	wait_on_irq(cpu);
+
+	/*
+	 * Ok, finally..
+	 */
+	global_irq_holder = cpu;
+}
+
+/*
+ * A global "cli()" while in an interrupt context turns into just a local 
+ * cli(). Interrupts should use spinlocks for the (very unlikely) case that 
+ * they ever want to protect against each other.
+ * 
+ * If we already have local interrupts disabled, this will not turn a local 
+ * disable into a global one (problems with spinlocks: this makes 
+ * save_flags+cli+sti usable inside a spinlock).
+ */
+
+void __global_cli(void)
+{
+	unsigned int flags;
+
+	__save_flags(flags);
+	if (flags & ST0_IE) {
+		int cpu = smp_processor_id();
+		__cli();
+		if (!local_irq_count(cpu))
+			get_irqlock(cpu);
+	}
+}
+
+void __global_sti(void)
+{
+	int cpu = smp_processor_id();
+
+	if (!local_irq_count(cpu))
+		release_irqlock(cpu);
+	__sti();
+}
+
+/*
+ * SMP flags value to restore to:
+ * 0 - global cli
+ * 1 - global sti
+ * 2 - local cli
+ * 3 - local sti
+ */
+unsigned long __global_save_flags(void)
+{
+	int retval;
+	int local_enabled;
+	unsigned long flags;
+	int cpu = smp_processor_id();
+
+	__save_flags(flags);
+	local_enabled = (flags & ST0_IE);
+	/* default to local */
+	retval = 2 + local_enabled;
+
+	/* check for global flags if we're not in an interrupt */
+	if (!local_irq_count(cpu)) {
+		if (local_enabled)
+			retval = 1;
+		if (global_irq_holder == cpu)
+			retval = 0;
+	}
+
+	return retval;
+}
+
+void __global_restore_flags(unsigned long flags)
+{
+	switch (flags) {
+		case 0:
+			__global_cli();
+			break;
+		case 1:
+			__global_sti();
+			break;
+		case 2:
+			__cli();
+			break;
+		case 3:
+			__sti();
+			break;
+		default:
+			printk("global_restore_flags: %08lx\n", flags);
+	}
+}
+#endif /* CONFIG_SMP */
+
 /*
  * This should really return information about whether
  * we should do bottom half handling etc. Right now we
@@ -690,7 +873,7 @@
 	}
 	spin_unlock_irqrestore(&desc->lock,flags);
 
-	/* register_irq_proc(irq); */
+	register_irq_proc(irq);
 	return 0;
 }
 
@@ -705,3 +888,176 @@
 		irq_desc[i].handler = &no_irq_type;
 	}
 }
+
+EXPORT_SYMBOL(disable_irq_nosync);
+EXPORT_SYMBOL(disable_irq);
+EXPORT_SYMBOL(enable_irq);
+EXPORT_SYMBOL(probe_irq_mask);
+
+static struct proc_dir_entry * root_irq_dir;
+static struct proc_dir_entry * irq_dir [NR_IRQS];
+
+#define HEX_DIGITS 8
+
+static unsigned int parse_hex_value (const char *buffer,
+		unsigned long count, unsigned long *ret)
+{
+	unsigned char hexnum [HEX_DIGITS];
+	unsigned long value;
+	int i;
+
+	if (!count)
+		return -EINVAL;
+	if (count > HEX_DIGITS)
+		count = HEX_DIGITS;
+	if (copy_from_user(hexnum, buffer, count))
+		return -EFAULT;
+
+	/*
+	 * Parse the first 8 characters as a hex string, any non-hex char
+	 * is end-of-string. '00e1', 'e1', '00E1', 'E1' are all the same.
+	 */
+	value = 0;
+
+	for (i = 0; i < count; i++) {
+		unsigned int c = hexnum[i];
+
+		switch (c) {
+			case '0' ... '9': c -= '0'; break;
+			case 'a' ... 'f': c -= 'a'-10; break;
+			case 'A' ... 'F': c -= 'A'-10; break;
+		default:
+			goto out;
+		}
+		value = (value << 4) | c;
+	}
+out:
+	*ret = value;
+	return 0;
+}
+
+#if CONFIG_SMP
+
+static struct proc_dir_entry * smp_affinity_entry [NR_IRQS];
+
+static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL };
+static int irq_affinity_read_proc (char *page, char **start, off_t off,
+			int count, int *eof, void *data)
+{
+	if (count < HEX_DIGITS+1)
+		return -EINVAL;
+	return sprintf (page, "%08lx\n", irq_affinity[(long)data]);
+}
+
+static int irq_affinity_write_proc (struct file *file, const char *buffer,
+					unsigned long count, void *data)
+{
+	int irq = (long) data, full_count = count, err;
+	unsigned long new_value;
+
+	if (!irq_desc[irq].handler->set_affinity)
+		return -EIO;
+
+	err = parse_hex_value(buffer, count, &new_value);
+
+	/*
+	 * Do not allow disabling IRQs completely - it's a too easy
+	 * way to make the system unusable accidentally :-) At least
+	 * one online CPU still has to be targeted.
+	 */
+	if (!(new_value & cpu_online_map))
+		return -EINVAL;
+
+	irq_affinity[irq] = new_value;
+	irq_desc[irq].handler->set_affinity(irq, new_value);
+
+	return full_count;
+}
+
+#endif
+
+static int prof_cpu_mask_read_proc (char *page, char **start, off_t off,
+			int count, int *eof, void *data)
+{
+	unsigned long *mask = (unsigned long *) data;
+	if (count < HEX_DIGITS+1)
+		return -EINVAL;
+	return sprintf (page, "%08lx\n", *mask);
+}
+
+static int prof_cpu_mask_write_proc (struct file *file, const char *buffer,
+					unsigned long count, void *data)
+{
+	unsigned long *mask = (unsigned long *) data, full_count = count, err;
+	unsigned long new_value;
+
+	err = parse_hex_value(buffer, count, &new_value);
+	if (err)
+		return err;
+
+	*mask = new_value;
+	return full_count;
+}
+
+#define MAX_NAMELEN 10
+
+static void register_irq_proc (unsigned int irq)
+{
+	char name [MAX_NAMELEN];
+
+	if (!root_irq_dir || (irq_desc[irq].handler == &no_irq_type) ||
+			irq_dir[irq])
+		return;
+
+	memset(name, 0, MAX_NAMELEN);
+	sprintf(name, "%d", irq);
+
+	/* create /proc/irq/1234 */
+	irq_dir[irq] = proc_mkdir(name, root_irq_dir);
+
+#if CONFIG_SMP
+	{
+		struct proc_dir_entry *entry;
+
+		/* create /proc/irq/1234/smp_affinity */
+		entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
+
+		if (entry) {
+			entry->nlink = 1;
+			entry->data = (void *)(long)irq;
+			entry->read_proc = irq_affinity_read_proc;
+			entry->write_proc = irq_affinity_write_proc;
+		}
+
+		smp_affinity_entry[irq] = entry;
+	}
+#endif
+}
+
+unsigned long prof_cpu_mask = -1;
+
+void init_irq_proc (void)
+{
+	struct proc_dir_entry *entry;
+	int i;
+
+	/* create /proc/irq */
+	root_irq_dir = proc_mkdir("irq", 0);
+
+	/* create /proc/irq/prof_cpu_mask */
+	entry = create_proc_entry("prof_cpu_mask", 0600, root_irq_dir);
+
+	if (!entry)
+	    return;
+
+	entry->nlink = 1;
+	entry->data = (void *)&prof_cpu_mask;
+	entry->read_proc = prof_cpu_mask_read_proc;
+	entry->write_proc = prof_cpu_mask_write_proc;
+
+	/*
+	 * Create entries for all existing IRQs.
+	 */
+	for (i = 0; i < NR_IRQS; i++)
+		register_irq_proc(i);
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/irq_cpu.c linux/arch/mips/kernel/irq_cpu.c
--- linux.orig/arch/mips/kernel/irq_cpu.c	1970-01-01 00:00:00.000000000 +0000
+++ linux/arch/mips/kernel/irq_cpu.c	2002-08-01 06:42:37.000000000 +0000
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This file define the irq handler for MIPS CPU interrupts.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
+ * level triggered (i.e., cannot be cleared from CPU; must be cleared from
+ * device).  The first two are software interrupts.  The last one is 
+ * usually the CPU timer interrupt if counter register is present or, for
+ * CPUs with an external FPU, by convention it's the FPU exception interrupt.
+ *
+ * This file exports one global function:
+ *	void mips_cpu_irq_init(int irq_base);
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+
+static int mips_cpu_irq_base = -1;
+
+static void mips_cpu_irq_enable(unsigned int irq)
+{
+	clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
+	set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
+}
+
+static void mips_cpu_irq_disable(unsigned int irq)
+{
+	clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
+}
+
+static unsigned int mips_cpu_irq_startup(unsigned int irq)
+{
+	mips_cpu_irq_enable(irq);
+
+	return 0;
+}
+
+#define	mips_cpu_irq_shutdown	mips_cpu_irq_disable
+
+static void mips_cpu_irq_ack(unsigned int irq)
+{
+	/* although we attemp to clear the IP bit in cause reigster, I think
+	 * usually it is cleared by device (irq source)
+	 */
+	clear_cp0_cause(1 << (irq - mips_cpu_irq_base + 8));
+
+	/* disable this interrupt - so that we safe proceed to the handler */
+	mips_cpu_irq_disable(irq);
+}
+
+static void mips_cpu_irq_end(unsigned int irq)
+{
+	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		mips_cpu_irq_enable(irq);
+}
+
+static hw_irq_controller mips_cpu_irq_controller = {
+	"MIPS",
+	mips_cpu_irq_startup,
+	mips_cpu_irq_shutdown,
+	mips_cpu_irq_enable,
+	mips_cpu_irq_disable,
+	mips_cpu_irq_ack,
+	mips_cpu_irq_end,
+	NULL			/* no affinity stuff for UP */
+};
+
+
+void __init mips_cpu_irq_init(int irq_base)
+{
+	int i;
+
+	for (i = irq_base; i < irq_base + 8; i++) {
+		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 1;
+		irq_desc[i].handler = &mips_cpu_irq_controller;
+	}
+
+	mips_cpu_irq_base = irq_base;
+}
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/mips_ksyms.c linux/arch/mips/kernel/mips_ksyms.c
--- linux.orig/arch/mips/kernel/mips_ksyms.c	2002-02-25 19:37:53.000000000 +0000
+++ linux/arch/mips/kernel/mips_ksyms.c	2002-08-01 06:42:35.000000000 +0000
@@ -25,6 +25,7 @@
 #include <asm/pgalloc.h>
 #include <asm/semaphore.h>
 #include <asm/sgi/sgihpc.h>
+#include <asm/sgi/sgimc.h>
 #include <asm/softirq.h>
 #include <asm/uaccess.h>
 #ifdef CONFIG_BLK_DEV_FD
@@ -62,8 +63,6 @@
 EXPORT_SYMBOL_NOVERS(strtok);
 
 EXPORT_SYMBOL(_clear_page);
-EXPORT_SYMBOL(enable_irq);
-EXPORT_SYMBOL(disable_irq);
 EXPORT_SYMBOL(kernel_thread);
 
 /*
@@ -87,8 +86,6 @@
  */
 EXPORT_SYMBOL(_flush_page_to_ram);
 EXPORT_SYMBOL(_flush_cache_all);
-EXPORT_SYMBOL(_dma_cache_wback_inv);
-EXPORT_SYMBOL(_dma_cache_inv);
 
 EXPORT_SYMBOL(invalid_pte_table);
 
@@ -101,11 +98,6 @@
 EXPORT_SYMBOL(__up);
 
 /*
- * Base address of ports for Intel style I/O.
- */
-EXPORT_SYMBOL(mips_io_port_base);
-
-/*
  * Architecture specific stuff.
  */
 #ifdef CONFIG_MIPS_JAZZ
@@ -116,6 +108,8 @@
 
 #ifdef CONFIG_SGI_IP22
 EXPORT_SYMBOL(hpc3c0);
+EXPORT_SYMBOL(hpc3c1);
+EXPORT_SYMBOL(mcmisc_regs);
 #endif
 
 /*
@@ -124,9 +118,6 @@
 #include <asm/branch.h>
 #include <linux/sched.h>
 
-int register_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31));
-int unregister_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31));
-
 #ifdef CONFIG_VT
 EXPORT_SYMBOL(screen_info);
 #endif
@@ -136,4 +127,3 @@
 #endif
 
 EXPORT_SYMBOL(get_wchan);
-EXPORT_SYMBOL(flush_tlb_page);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/old-irq.c linux/arch/mips/kernel/old-irq.c
--- linux.orig/arch/mips/kernel/old-irq.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/old-irq.c	2002-08-01 06:42:45.000000000 +0000
@@ -69,7 +69,7 @@
 #define cached_21       (__byte(0,cached_irq_mask))
 #define cached_A1       (__byte(1,cached_irq_mask))
 
-unsigned long spurious_count = 0;
+volatile unsigned long irq_err_count;
 
 /*
  * (un)mask_irq, disable_irq() and enable_irq() only handle (E)ISA and
@@ -403,3 +403,6 @@
 	/* i8259_init(); */
 	irq_setup();
 }
+
+EXPORT_SYMBOL(free_irq);
+EXPORT_SYMBOL(request_irq);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/old-time.c linux/arch/mips/kernel/old-time.c
--- linux.orig/arch/mips/kernel/old-time.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/old-time.c	2002-08-01 06:42:34.000000000 +0000
@@ -89,8 +89,7 @@
 			:"r" (timerhi),
 			 "m" (timerlo),
 			 "r" (tmp),
-			 "r" (USECS_PER_JIFFY)
-			:"$1");
+			 "r" (USECS_PER_JIFFY));
 		cached_quotient = quotient;
 	}
 
@@ -389,15 +388,19 @@
 	    xtime.tv_sec > last_rtc_update + 660 &&
 	    xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 &&
 	    xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) {
-	  if (set_rtc_mmss(xtime.tv_sec) == 0)
-	    last_rtc_update = xtime.tv_sec;
-	  else
-	    last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
+		if (set_rtc_mmss(xtime.tv_sec) == 0)
+			last_rtc_update = xtime.tv_sec;
+		else
+			/* do it again in 60 s */
+			last_rtc_update = xtime.tv_sec - 600;
 	}
-	/* As we return to user mode fire off the other CPU schedulers.. this is 
-	   basically because we don't yet share IRQ's around. This message is
-	   rigged to be safe on the 386 - basically it's a hack, so don't look
-	   closely for now.. */
+
+	/*
+	 * As we return to user mode fire off the other CPU schedulers.. this
+	 * is basically because we don't yet share IRQ's around. This message
+	 * is rigged to be safe on the 386 - basically it's a hack, so don't
+	 * look closely for now..
+	 */
 	/*smp_message_pass(MSG_ALL_BUT_SELF, MSG_RESCHEDULE, 0L, 0); */
 	read_unlock (&xtime_lock); 
 }
@@ -442,10 +445,12 @@
 
 void indy_r4k_timer_interrupt (struct pt_regs *regs)
 {
-	static const int INDY_R4K_TIMER_IRQ = 7;
 	int cpu = smp_processor_id();
+	int irq = 7;
 
-	r4k_timer_interrupt (INDY_R4K_TIMER_IRQ, NULL, regs);
+	irq_enter(cpu, irq);
+	r4k_timer_interrupt(irq, NULL, regs);
+	irq_exit(cpu, irq);
 
 	if (softirq_pending(cpu))
 		do_softirq();
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/pci-dma.c linux/arch/mips/kernel/pci-dma.c
--- linux.orig/arch/mips/kernel/pci-dma.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/pci-dma.c	2002-08-01 06:42:31.000000000 +0000
@@ -10,6 +10,7 @@
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 #include <linux/string.h>
 #include <linux/pci.h>
 
@@ -27,7 +28,7 @@
 
 	if (ret != NULL) {
 		memset(ret, 0, size);
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
 		dma_cache_wback_inv((unsigned long) ret, size);
 		ret = KSEG1ADDR(ret);
 #endif
@@ -42,8 +43,11 @@
 {
 	unsigned long addr = (unsigned long) vaddr;
 
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
 	addr = KSEG0ADDR(addr);
 #endif
 	free_pages(addr, get_order(size));
 }
+
+EXPORT_SYMBOL(pci_alloc_consistent);
+EXPORT_SYMBOL(pci_free_consistent);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/pci.c linux/arch/mips/kernel/pci.c
--- linux.orig/arch/mips/kernel/pci.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/pci.c	2002-08-01 06:42:33.000000000 +0000
@@ -55,6 +55,7 @@
  *		Dave Rusling david.rusling@reo.mts.dec.com
  *		David Mosberger davidm@cs.arizona.edu
  */
+#include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/types.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/pci_auto.c linux/arch/mips/kernel/pci_auto.c
--- linux.orig/arch/mips/kernel/pci_auto.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/pci_auto.c	2002-08-01 06:42:48.000000000 +0000
@@ -4,6 +4,7 @@
  * Author: Matt Porter <mporter@mvista.com>
  *
  * Copyright 2000, 2001 MontaVista Software Inc.
+ * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -19,6 +20,15 @@
  * . change most int to u32.
  *
  * Further modified to include it as mips generic code, ppopov@mvista.com.
+ *
+ * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
+ * - Add a top_bus argument to the "early config" functions so that
+ *   they can set a fake parent bus pointer to convince the underlying
+ *   pci ops to use type 1 configuration for sub busses.
+ * - Set bridge base and limit registers correctly.
+ * - Align io and memory base properly before and after bridge setup.
+ * - Don't fall through to pci_setup_bars for bridge.
+ * - Reformat the debug output to look more like lspci's output.
  */
 
 #include <linux/kernel.h>
@@ -35,13 +45,49 @@
 #define	DBG(x...)	
 #endif
 
-/* These are used for config access before all the PCI probing has been done. */
-int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
-int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
-int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val);
-int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val);
-int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val);
-int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val);
+/*
+ * These functions are used early on before PCI scanning is done
+ * and all of the pci_dev and pci_bus structures have been created.
+ */
+static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
+	int top_bus, int busnr, int devfn)
+{
+	static struct pci_dev dev;
+	static struct pci_bus bus;
+
+	dev.bus = &bus;
+	dev.sysdata = hose;
+	dev.devfn = devfn;
+	bus.number = busnr;
+	bus.ops = hose->pci_ops;
+
+	if(busnr != top_bus)
+		/* Fake a parent bus structure. */
+		bus.parent = &bus;
+	else
+		bus.parent = NULL;
+
+	return &dev;
+}
+
+#define EARLY_PCI_OP(rw, size, type)					\
+int early_##rw##_config_##size(struct pci_channel *hose,		\
+	int top_bus, int bus, int devfn, int offset, type value)	\
+{									\
+	return pci_##rw##_config_##size(				\
+		fake_pci_dev(hose, top_bus, bus, devfn),		\
+		offset, value);						\
+}
+
+EARLY_PCI_OP(read, byte, u8 *)
+EARLY_PCI_OP(read, word, u16 *)
+EARLY_PCI_OP(read, dword, u32 *)
+EARLY_PCI_OP(write, byte, u8)
+EARLY_PCI_OP(write, word, u16)
+EARLY_PCI_OP(write, dword, u32)
+
+static struct resource *io_resource_inuse;
+static struct resource *mem_resource_inuse;
 
 static u32 pciauto_lower_iospc;
 static u32 pciauto_upper_iospc;
@@ -51,6 +97,7 @@
 
 void __init 
 pciauto_setup_bars(struct pci_channel *hose,
+		   int top_bus,
 		   int current_bus,
 		   int pci_devfn)
 {
@@ -60,17 +107,14 @@
 	u32 * lower_limit;
 	int found_mem64 = 0;
 
-	DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
-	    current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
-
 	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) {
 		/* Tickle the BAR and get the response */
-		early_write_config_dword(hose,
+		early_write_config_dword(hose, top_bus,
 					 current_bus,
 					 pci_devfn,
 					 bar,
 					 0xffffffff);
-		early_read_config_dword(hose,
+		early_read_config_dword(hose, top_bus,
 					current_bus,
 					pci_devfn,
 					bar,
@@ -80,12 +124,21 @@
 		if (!bar_response)
 			continue;
 
+		/*
+		 * Workaround for a BAR that doesn't use its upper word,
+		 * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
+		 * bdl <brad@ltc.com>
+		 */
+		if (!(bar_response & 0xffff0000))
+			bar_response |= 0xffff0000;
+
+retry:
 		/* Check the BAR type and set our address mask */
 		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 			addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 			upper_limit = &pciauto_upper_iospc;
 			lower_limit = &pciauto_lower_iospc;
-			DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
+			DBG("        I/O");
 		} else {
 			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 			    PCI_BASE_ADDRESS_MEM_TYPE_64)
@@ -94,17 +147,45 @@
 			addr_mask = PCI_BASE_ADDRESS_MEM_MASK;		
 			upper_limit = &pciauto_upper_memspc;
 			lower_limit = &pciauto_lower_memspc;
-			DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
+			DBG("        Mem");
 		}
 
+
 		/* Calculate requested size */
 		bar_size = ~(bar_response & addr_mask) + 1;
 
 		/* Allocate a base address */
 		bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 
+		if ((bar_value + bar_size) > *upper_limit) {
+			if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+				if (io_resource_inuse->child) {
+					io_resource_inuse = 
+						io_resource_inuse->child;
+					pciauto_lower_iospc = 
+						io_resource_inuse->start;
+					pciauto_upper_iospc = 
+						io_resource_inuse->end + 1;
+					goto retry;
+				}
+
+			} else {
+				if (mem_resource_inuse->child) {
+					mem_resource_inuse = 
+						mem_resource_inuse->child;
+					pciauto_lower_memspc = 
+						mem_resource_inuse->start;
+					pciauto_upper_memspc = 
+						mem_resource_inuse->end + 1;
+					goto retry;
+				}
+			}
+			DBG(" unavailable -- skipping\n");
+			continue;
+		}
+
 		/* Write it out and update our limit */
-		early_write_config_dword(hose, current_bus, pci_devfn,
+		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 					 bar, bar_value);
 
 		*lower_limit = bar_value + bar_size;
@@ -116,97 +197,99 @@
 		 */ 
 		if (found_mem64) {
 			bar += 4;
-			early_write_config_dword(hose,
+			early_write_config_dword(hose, top_bus,
 						 current_bus,
 						 pci_devfn,
 						 bar,
 						 0x00000000);
 		}
 
-		bar_nr++;
+		DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 
-		DBG("size=0x%x, address=0x%x\n",
-		    bar_size, bar_value);
+		bar_nr++;
 	}
 
 }
 
 void __init
 pciauto_prescan_setup_bridge(struct pci_channel *hose,
+			     int top_bus,
 			     int current_bus,
 			     int pci_devfn,
 			     int sub_bus)
 {
-	int cmdstat;
-
 	/* Configure bus number registers */
-	early_write_config_byte(hose, current_bus, pci_devfn,
+	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 	                        PCI_PRIMARY_BUS, current_bus);
-	early_write_config_byte(hose, current_bus, pci_devfn,
+	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 				PCI_SECONDARY_BUS, sub_bus + 1);
-	early_write_config_byte(hose, current_bus, pci_devfn,
+	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 				PCI_SUBORDINATE_BUS, 0xff);
 
-	/* Round memory allocator to 1MB boundary */
-	pciauto_upper_memspc &= ~(0x100000 - 1);
+	/* Align memory and I/O to 1MB and 4KB boundaries. */
+	pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
+		& ~(0x100000 - 1);
+	pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
+		& ~(0x1000 - 1);
+
+	/* Set base (lower limit) of address range behind bridge. */
+	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+		PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
+	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
+		PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
+	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+		PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 
-	/* Round I/O allocator to 4KB boundary */
-	pciauto_upper_iospc &= ~(0x1000 - 1);
-
-	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
-	early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_LIMIT,
-				((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
-	early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_LIMIT,
-				((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
-	early_write_config_word(hose, current_bus, pci_devfn,
-				PCI_IO_LIMIT_UPPER16,
-				((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
-			
 	/* We don't support prefetchable memory for now, so disable */
-	early_write_config_word(hose, current_bus, pci_devfn,
-				PCI_PREF_MEMORY_BASE, 0x1000);
-	early_write_config_word(hose, current_bus, pci_devfn,
-				PCI_PREF_MEMORY_LIMIT, 0x1000);
-
-	/* Enable memory and I/O accesses, enable bus master */
-	early_read_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND,
-				&cmdstat);
-	early_write_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND,
-				 cmdstat | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-				 PCI_COMMAND_MASTER);
+	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+				PCI_PREF_MEMORY_BASE, 0);
+	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+				PCI_PREF_MEMORY_LIMIT, 0);
 }
 
 void __init
 pciauto_postscan_setup_bridge(struct pci_channel *hose,
+			      int top_bus,
 			      int current_bus,
 			      int pci_devfn,
 			      int sub_bus)
 {
+	u32 temp;
+
 	/* Configure bus number registers */
-	early_write_config_byte(hose, current_bus, pci_devfn,
+	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 				PCI_SUBORDINATE_BUS, sub_bus);
 
-	/* Round memory allocator to 1MB boundary */
-	pciauto_upper_memspc &= ~(0x100000 - 1);
-	early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_BASE,
-				pciauto_upper_memspc >> 16);
-
-	/* Round I/O allocator to 4KB boundary */
-	pciauto_upper_iospc &= ~(0x1000 - 1);
-	early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_BASE,
-				(pciauto_upper_iospc & 0x0000f000) >> 8);
-	early_write_config_word(hose, current_bus, pci_devfn,
-				PCI_IO_BASE_UPPER16, pciauto_upper_iospc >> 16);
+	/* Set upper limit of address range behind bridge. */
+	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+		PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
+	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
+		PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
+	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+		PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
+
+	/* Align memory and I/O to 1MB and 4KB boundaries. */
+	pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
+		& ~(0x100000 - 1);
+	pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
+		& ~(0x1000 - 1);
+
+	/* Enable memory and I/O accesses, enable bus master */
+	early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
+		PCI_COMMAND, &temp);
+	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
+		PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
+		| PCI_COMMAND_MASTER);
 }
 
 #define      PCIAUTO_IDE_MODE_MASK           0x05
 
 int __init
-pciauto_bus_scan(struct pci_channel *hose, int current_bus)
+pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 {
 	int sub_bus;
 	u32 pci_devfn, pci_class, cmdstat, found_multi=0;
-	unsigned short vid;
+	unsigned short vid, did;
 	unsigned char header_type;
 	int devfn_start = 0;
 	int devfn_stop = 0xff;
@@ -223,54 +306,70 @@
 		if (PCI_FUNC(pci_devfn) && !found_multi)
 			continue;
 
-		early_read_config_byte(hose, current_bus, pci_devfn,
+		early_read_config_word(hose, top_bus, current_bus, pci_devfn,
+				       PCI_VENDOR_ID, &vid);
+
+		if (vid == 0xffff) continue;
+
+		early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 				       PCI_HEADER_TYPE, &header_type);
 
 		if (!PCI_FUNC(pci_devfn))
 			found_multi = header_type & 0x80;
 
-		early_read_config_word(hose, current_bus, pci_devfn,
-				       PCI_VENDOR_ID, &vid);
-
-		if (vid == 0xffff) continue;
+		early_read_config_word(hose, top_bus, current_bus, pci_devfn,
+				       PCI_DEVICE_ID, &did);
 
-		early_read_config_dword(hose, current_bus, pci_devfn,
+		early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 					PCI_CLASS_REVISION, &pci_class);
+
+		DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
+			current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
+			pci_class >> 16, vid, did);
+		if (pci_class & 0xff)
+			DBG(" (rev %.2x)", pci_class & 0xff);
+		DBG("\n");
+
 		if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
-			DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
-			pciauto_prescan_setup_bridge(hose, current_bus,
+			DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
+				current_bus, sub_bus + 1);
+			pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 						     pci_devfn, sub_bus);
-			sub_bus = pciauto_bus_scan(hose, sub_bus+1);
-			pciauto_postscan_setup_bridge(hose, current_bus,
+			DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
+				sub_bus + 1,
+				pciauto_lower_iospc, pciauto_lower_memspc);
+			sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
+			DBG("Back to bus %.2x\n", current_bus);
+			pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 						      pci_devfn, sub_bus);
-
+			continue;
 		} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 
 			unsigned char prg_iface;
 
-			early_read_config_byte(hose, current_bus, pci_devfn,
-					       PCI_CLASS_PROG, &prg_iface);
+			early_read_config_byte(hose, top_bus, current_bus,
+				pci_devfn, PCI_CLASS_PROG, &prg_iface);
 			if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
-				DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
+				DBG("Skipping legacy mode IDE controller\n");
 				continue;
 			}
 		}
 
-		/*
+ 		/*
 		 * Found a peripheral, enable some standard
 		 * settings
 		 */
-		early_read_config_dword(hose, current_bus, pci_devfn,
+		early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 					PCI_COMMAND, &cmdstat);
-		early_write_config_dword(hose, current_bus, pci_devfn,
+		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 					 PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 					 PCI_COMMAND_MEMORY |
 					 PCI_COMMAND_MASTER);
-		early_write_config_byte(hose, current_bus, pci_devfn,
+		early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 					PCI_LATENCY_TIMER, 0x80);
 
 		/* Allocate PCI I/O and/or memory space */
-		pciauto_setup_bars(hose, current_bus, pci_devfn);
+		pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn);
 	}
 	return sub_bus;
 }
@@ -279,45 +378,17 @@
 pciauto_assign_resources(int busno, struct pci_channel *hose)
 {
 	/* setup resource limits */
-	pciauto_lower_iospc = hose->io_resource->start;
-	pciauto_upper_iospc = hose->io_resource->end + 1;
-	pciauto_lower_memspc = hose->mem_resource->start;
-	pciauto_upper_memspc = hose->mem_resource->end + 1;
-
-	return pciauto_bus_scan(hose, busno);
-}
-
-
-/*
- * These functions are used early on before PCI scanning is done
- * and all of the pci_dev and pci_bus structures have been created.
- */
-static struct pci_dev *fake_pci_dev(struct pci_channel *hose, int busnr,
-                                    int devfn)
-{
-	static struct pci_dev dev;
-	static struct pci_bus bus;
-
-	dev.bus = &bus;
-	dev.sysdata = hose;
-	dev.devfn = devfn;
-	bus.number = busnr;
-	bus.ops = hose->pci_ops;
+	io_resource_inuse = hose->io_resource;
+	mem_resource_inuse = hose->mem_resource;
 
-	return &dev;
-}
+	pciauto_lower_iospc = io_resource_inuse->start;
+	pciauto_upper_iospc = io_resource_inuse->end + 1;
+	pciauto_lower_memspc = mem_resource_inuse->start;
+	pciauto_upper_memspc = mem_resource_inuse->end + 1;
+	DBG("Autoconfig PCI channel 0x%p\n", hose);
+	DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
+		busno, pciauto_lower_iospc, pciauto_upper_iospc, 
+		pciauto_lower_memspc, pciauto_upper_memspc);
 
-#define EARLY_PCI_OP(rw, size, type)					\
-int early_##rw##_config_##size(struct pci_channel *hose, int bus,	\
-                               int devfn, int offset, type value)	\
-{									\
-	return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn),	\
-	                                offset, value);			\
+	return pciauto_bus_scan(hose, busno, busno);
 }
-
-EARLY_PCI_OP(read, byte, u8 *)
-EARLY_PCI_OP(read, word, u16 *)
-EARLY_PCI_OP(read, dword, u32 *)
-EARLY_PCI_OP(write, byte, u8)
-EARLY_PCI_OP(write, word, u16)
-EARLY_PCI_OP(write, dword, u32)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/proc.c linux/arch/mips/kernel/proc.c
--- linux.orig/arch/mips/kernel/proc.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/proc.c	2002-08-01 06:42:36.000000000 +0000
@@ -8,102 +8,139 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/seq_file.h>
 #include <asm/bootinfo.h>
 #include <asm/cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/processor.h>
 #include <asm/watch.h>
 
-extern unsigned long unaligned_instructions;
 unsigned int vced_count, vcei_count;
+
 #ifndef CONFIG_CPU_HAS_LLSC
 unsigned long ll_ops, sc_ops;
 #endif
 
-/*
- * BUFFER is PAGE_SIZE bytes long.
- *
- * Currently /proc/cpuinfo is being abused to print data about the
- * number of date/instruction cacheflushes.
- */
-int get_cpuinfo(char *buffer)
+static const char *cpu_name[] = {
+	[CPU_UNKNOWN]	"unknown",
+	[CPU_R2000]	"R2000",
+	[CPU_R3000]	"R3000",
+	[CPU_R3000A]	"R3000A",
+	[CPU_R3041]	"R3041",
+	[CPU_R3051]	"R3051",
+	[CPU_R3052]	"R3052",
+	[CPU_R3081]	"R3081",
+	[CPU_R3081E]	"R3081E",
+	[CPU_R4000PC]	"R4000PC",
+	[CPU_R4000SC]	"R4000SC",
+	[CPU_R4000MC]	"R4000MC",
+        [CPU_R4200]	"R4200",
+	[CPU_R4400PC]	"R4400PC",
+	[CPU_R4400SC]	"R4400SC",
+	[CPU_R4400MC]	"R4400MC",
+	[CPU_R4600]	"R4600",
+	[CPU_R6000]	"R6000",
+        [CPU_R6000A]	"R6000A",
+	[CPU_R8000]	"R8000",
+	[CPU_R10000]	"R10000",
+	[CPU_R4300]	"R4300",
+	[CPU_R4650]	"R4650",
+	[CPU_R4700]	"R4700",
+	[CPU_R5000]	"R5000",
+        [CPU_R5000A]	"R5000A",
+	[CPU_R4640]	"R4640",
+	[CPU_NEVADA]	"Nevada",
+	[CPU_RM7000]	"RM7000",
+	[CPU_R5432]	"R5432",
+	[CPU_4KC]	"MIPS 4Kc",
+        [CPU_5KC]	"MIPS 5Kc",
+	[CPU_R4310]	"R4310",
+	[CPU_SB1]	"SiByte SB1",
+	[CPU_TX3912]	"TX3912",
+	[CPU_TX3922]	"TX3922",
+	[CPU_TX3927]	"TX3927",
+	[CPU_AU1000]	"Au1000",
+	[CPU_AU1500]	"Au1500",
+	[CPU_4KEC]	"MIPS 4KEc",
+	[CPU_4KSC]	"MIPS 4KSc",
+	[CPU_VR41XX]	"NEC Vr41xx",
+	[CPU_R5500]	"R5500",
+	[CPU_TX49XX]	"TX49xx",
+	[CPU_TX39XX]	"TX39xx",
+	[CPU_20KC]	"MIPS 20Kc"
+};
+
+
+static int show_cpuinfo(struct seq_file *m, void *v)
 {
+	unsigned int version = mips_cpu.processor_id;
+	unsigned int fp_vers = mips_cpu.fpu_id;
+	unsigned long n = (unsigned long) v - 1;
 	char fmt [64];
-	const char *cpu_name[] = CPU_NAMES;
-	const char *mach_group_names[] = GROUP_NAMES;
-	const char *mach_unknown_names[] = GROUP_UNKNOWN_NAMES;
-	const char *mach_jazz_names[] = GROUP_JAZZ_NAMES;
-	const char *mach_dec_names[] = GROUP_DEC_NAMES;
-	const char *mach_arc_names[] = GROUP_ARC_NAMES;
-	const char *mach_sni_rm_names[] = GROUP_SNI_RM_NAMES;
-	const char *mach_acn_names[] = GROUP_ACN_NAMES;
-	const char *mach_sgi_names[] = GROUP_SGI_NAMES;
-	const char *mach_cobalt_names[] = GROUP_COBALT_NAMES;
-	const char *mach_nec_ddb_names[] = GROUP_NEC_DDB_NAMES;
-	const char *mach_baget_names[] = GROUP_BAGET_NAMES;
-	const char *mach_cosine_names[] = GROUP_COSINE_NAMES;
-	const char *mach_galileo_names[] = GROUP_GALILEO_NAMES;
-	const char *mach_momenco_names[] = GROUP_MOMENCO_NAMES;
- 	const char *mach_ite_names[] = GROUP_ITE_NAMES;
-	const char *mach_philips_names[] = GROUP_PHILIPS_NAMES;
- 	const char *mach_globespan_names[] = GROUP_GLOBESPAN_NAMES;
-	const char *mach_sibyte_names[] = GROUP_SIBYTE_NAMES;
-	const char *mach_toshiba_names[] = GROUP_TOSHIBA_NAMES;
-	const char *mach_alchemy_names[] = GROUP_ALCHEMY_NAMES;
-	const char **mach_group_to_name[] = { mach_unknown_names,
-		mach_jazz_names, mach_dec_names, mach_arc_names,
-		mach_sni_rm_names, mach_acn_names, mach_sgi_names,
-		mach_cobalt_names, mach_nec_ddb_names, mach_baget_names,
-		mach_cosine_names, mach_galileo_names, mach_momenco_names, 
-		mach_ite_names, mach_philips_names, mach_globespan_names,
-		mach_sibyte_names, mach_toshiba_names, mach_alchemy_names};
-	unsigned int version = read_32bit_cp0_register(CP0_PRID);
-	int len;
-
-	len = sprintf(buffer, "cpu\t\t\t: MIPS\n");
-	len += sprintf(buffer + len, "cpu model\t\t: %s V%d.%d\n",
-	               cpu_name[mips_cpu.cputype <= CPU_LAST ?
-	                        mips_cpu.cputype : CPU_UNKNOWN],
-	               (version >> 4) & 0x0f, version & 0x0f);
-	len += sprintf(buffer + len, "system type\t\t: %s %s\n",
-		       mach_group_names[mips_machgroup],
-		       mach_group_to_name[mips_machgroup][mips_machtype]);
-	len += sprintf(buffer + len, "BogoMIPS\t\t: %lu.%02lu\n",
-		       loops_per_jiffy/(500000/HZ),
-		       (loops_per_jiffy/(5000/HZ)) % 100);
 
-#if defined (__MIPSEB__)
-	len += sprintf(buffer + len, "byteorder\t\t: big endian\n");
-#endif
-#if defined (__MIPSEL__)
-	len += sprintf(buffer + len, "byteorder\t\t: little endian\n");
+#ifdef CONFIG_SMP
+	if (!CPUMASK_TSTB(cpu_online_map, n))
+		return 0;
 #endif
-	len += sprintf(buffer + len, "unaligned accesses\t: %lu\n",
-		       unaligned_instructions);
-	len += sprintf(buffer + len, "wait instruction\t: %s\n",
-	               cpu_wait ? "yes" : "no");
-	len += sprintf(buffer + len, "microsecond timers\t: %s\n",
-	               (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no");
-	len += sprintf(buffer + len, "extra interrupt vector\t: %s\n",
-	               (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no");
-	len += sprintf(buffer + len, "hardware watchpoint\t: %s\n",
-	               watch_available ? "yes" : "no");
+
+	/*
+	 * For the first processor also print the system type
+	 */
+	if (n == 0)
+		seq_printf(m, "system type\t\t: %s\n", get_system_type());
+
+	seq_printf(m, "processor\t\t: %ld\n", n);
+	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
+	        (mips_cpu.options & MIPS_CPU_FPU) ? "  FPU V%d.%d" : "");
+	seq_printf(m, fmt, cpu_name[mips_cpu.cputype <= CPU_LAST ?
+	                            mips_cpu.cputype : CPU_UNKNOWN],
+	                           (version >> 4) & 0x0f, version & 0x0f,
+	                           (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
+	seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
+	              loops_per_jiffy / (500000/HZ),
+	              (loops_per_jiffy / (5000/HZ)) % 100);
+	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
+	seq_printf(m, "microsecond timers\t: %s\n",
+	              (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no");
+	seq_printf(m, "tlb_entries\t\t: %d\n", mips_cpu.tlbsize);
+	seq_printf(m, "extra interrupt vector\t: %s\n",
+	              (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no");
+	seq_printf(m, "hardware watchpoint\t: %s\n",
+	              watch_available ? "yes" : "no");
 
 	sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
 	        (mips_cpu.options & MIPS_CPU_VCE) ? "%d" : "not available");
-	len += sprintf(buffer + len, fmt, 'D', vced_count);
-	len += sprintf(buffer + len, fmt, 'I', vcei_count);
+	seq_printf(m, fmt, 'D', vced_count);
+	seq_printf(m, fmt, 'I', vcei_count);
 
 #ifndef CONFIG_CPU_HAS_LLSC
-	len += sprintf(buffer + len, "ll emulations\t\t: %lu\n",
-		       ll_ops);
-	len += sprintf(buffer + len, "sc emulations\t\t: %lu\n",
-		       sc_ops);
+	seq_printf(m, "ll emulations\t\t: %lu\n", ll_ops);
+	seq_printf(m, "sc emulations\t\t: %lu\n", sc_ops);
 #endif
-	return len;
+
+	return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+	unsigned long i = *pos;
+
+	return i < NR_CPUS ? (void *) (i + 1) : NULL;
 }
 
-void init_irq_proc(void)
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 {
-	/* Nothing, for now.  */
+	++*pos;
+	return c_start(m, pos);
 }
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+struct seq_operations cpuinfo_op = {
+	start:	c_start,
+	next:	c_next,
+	stop:	c_stop,
+	show:	show_cpuinfo,
+};
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/process.c linux/arch/mips/kernel/process.c
--- linux.orig/arch/mips/kernel/process.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/process.c	2002-08-01 06:42:41.000000000 +0000
@@ -6,14 +6,13 @@
  * Copyright (C) 1994 - 2000 by Ralf Baechle and others.
  * Copyright (C) 1999 Silicon Graphics, Inc.
  */
-#include <linux/config.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/stddef.h>
 #include <linux/unistd.h>
-#include <linux/ptrace.h>
+#include <linux/personality.h>
 #include <linux/slab.h>
 #include <linux/mman.h>
 #include <linux/sys.h>
@@ -26,13 +25,13 @@
 #include <asm/system.h>
 #include <asm/mipsregs.h>
 #include <asm/processor.h>
-#include <asm/stackframe.h>
+#include <asm/ptrace.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/elf.h>
 #include <asm/isadep.h>
 
-void cpu_idle(void)
+ATTRIB_NORET void cpu_idle(void)
 {
 	/* endless idle loop with no priority at all */
 	current->nice = 20;
@@ -55,8 +54,8 @@
 void exit_thread(void)
 {
 	/* Forget lazy fpu state */
-	if (last_task_used_math == current) {
-		set_cp0_status(ST0_CU1);
+	if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
+		__enable_fpu();
 		__asm__ __volatile__("cfc1\t$0,$31");
 		last_task_used_math = NULL;
 	}
@@ -65,8 +64,8 @@
 void flush_thread(void)
 {
 	/* Forget lazy fpu state */
-	if (last_task_used_math == current) {
-		set_cp0_status(ST0_CU1);
+	if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
+		__enable_fpu();
 		__asm__ __volatile__("cfc1\t$0,$31");
 		last_task_used_math = NULL;
 	}
@@ -84,7 +83,7 @@
 
 	if (last_task_used_math == current)
 		if (mips_cpu.options & MIPS_CPU_FPU) {
-			set_cp0_status(ST0_CU1);
+			__enable_fpu();
 			save_fp(p);
 		}
 	/* set up new TSS. */
@@ -174,16 +173,15 @@
 		"1:  addiu   $sp,32           \n"
 		"    move    %0,$2            \n"
 		".set reorder"
-		:"=r" (retval)
-		:"i" (__NR_clone), "i" (__NR_exit),
-		 "r" (arg), "r" (fn),
-		 "r" (flags | CLONE_VM)
+		: "=r" (retval)
+		: "i" (__NR_clone), "i" (__NR_exit), "r" (arg), "r" (fn),
+		  "r" (flags | CLONE_VM)
 		 /*
 		  * The called subroutine might have destroyed any of the
 		  * at, result, argument or temporary registers ...
 		  */
-		:"$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
-		 "$9","$10","$11","$12","$13","$14","$15","$24","$25");
+		: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		  "$9","$10","$11","$12","$13","$14","$15","$24","$25");
 
 	return retval;
 }
@@ -196,7 +194,7 @@
 #define first_sched	((unsigned long) scheduling_functions_start_here)
 #define last_sched	((unsigned long) scheduling_functions_end_here)
 
-/* get_wchan - a maintenance nightmare ...  */
+/* get_wchan - a maintenance nightmare^W^Wpain in the ass ...  */
 unsigned long get_wchan(struct task_struct *p)
 {
 	unsigned long frame, pc;
@@ -217,26 +215,29 @@
 		goto schedule_timeout_caller;
 	if (pc >= (unsigned long)interruptible_sleep_on)
 		goto schedule_caller;
-	goto schedule_timeout_caller;
+	/* Fall through */
 
 schedule_caller:
-	frame = ((unsigned long *)p->thread.reg30)[9];
-	pc    = ((unsigned long *)frame)[11];
+	pc = ((unsigned long *)p->thread.reg30)[13];
+
 	return pc;
 
 schedule_timeout_caller:
-	/* Must be schedule_timeout ...  */
-	pc    = ((unsigned long *)p->thread.reg30)[10];
-	frame = ((unsigned long *)p->thread.reg30)[9];
-
-	/* The schedule_timeout frame ...  */
-	pc    = ((unsigned long *)frame)[14];
-	frame = ((unsigned long *)frame)[13];
+	/*
+	 * The schedule_timeout frame
+	 */
+	frame = ((unsigned long *)p->thread.reg30)[13];
+
+	/*
+	 * frame now points to sleep_on_timeout's frame
+	 */
+	frame = ((unsigned long *)frame)[9];
+	pc    = ((unsigned long *)frame)[10];
 
 	if (pc >= first_sched && pc < last_sched) {
 		/* schedule_timeout called by interruptible_sleep_on_timeout */
-		pc    = ((unsigned long *)frame)[11];
-		frame = ((unsigned long *)frame)[10];
+		frame = ((unsigned long *)frame)[9];
+		pc    = ((unsigned long *)frame)[10];
 	}
 
 	return pc;
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/ptrace.c linux/arch/mips/kernel/ptrace.c
--- linux.orig/arch/mips/kernel/ptrace.c	2001-09-18 23:56:19.000000000 +0000
+++ linux/arch/mips/kernel/ptrace.c	2002-08-01 06:42:44.000000000 +0000
@@ -20,7 +20,6 @@
 #include <linux/smp_lock.h>
 #include <linux/user.h>
 
-#include <asm/fp.h>
 #include <asm/mipsregs.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -42,7 +41,7 @@
 asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
 {
 	struct task_struct *child;
-	int res;
+	int ret;
 	extern void save_fp(struct task_struct *);
 
 	lock_kernel();
@@ -54,15 +53,15 @@
 	if (request == PTRACE_TRACEME) {
 		/* are we already being traced? */
 		if (current->ptrace & PT_PTRACED) {
-			res = -EPERM;
+			ret = -EPERM;
 			goto out;
 		}
 		/* set the ptrace bit in the process flags. */
 		current->ptrace |= PT_PTRACED;
-		res = 0;
+		ret = 0;
 		goto out;
 	}
-	res = -ESRCH;
+	ret = -ESRCH;
 	read_lock(&tasklist_lock);
 	child = find_task_by_pid(pid);
 	if (child)
@@ -71,23 +70,19 @@
 	if (!child)
 		goto out;
 
-	res = -EPERM;
+	ret = -EPERM;
 	if (pid == 1)		/* you may not mess with init */
 		goto out;
 
 	if (request == PTRACE_ATTACH) {
-		res = ptrace_attach(child);
+		ret = ptrace_attach(child);
 		goto out_tsk;
 	}
-	res = -ESRCH;
-	if (!(child->ptrace & PT_PTRACED))
-		goto out_tsk;
-	if (child->state != TASK_STOPPED) {
-		if (request != PTRACE_KILL)
-			goto out_tsk;
-	}
-	if (child->p_pptr != current)
+
+	ret = ptrace_check_attach(child, request == PTRACE_KILL);
+	if (ret < 0)
 		goto out_tsk;
+
 	switch (request) {
 	case PTRACE_PEEKTEXT: /* read word at location addr. */ 
 	case PTRACE_PEEKDATA: {
@@ -95,10 +90,10 @@
 		int copied;
 
 		copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
-		res = -EIO;
+		ret = -EIO;
 		if (copied != sizeof(tmp))
 			break;
-		res = put_user(tmp,(unsigned long *) data);
+		ret = put_user(tmp,(unsigned long *) data);
 
 		goto out;
 		}
@@ -126,9 +121,9 @@
 						child->thread.fpu.soft.regs;
 				} else 
 					if (last_task_used_math == child) {
-						enable_cp1();
+						__enable_fpu();
 						save_fp(child);
-						disable_cp1();
+						__disable_fpu();
 						last_task_used_math = NULL;
 						regs->cp0_status &= ~ST0_CU1;
 					}
@@ -174,33 +169,37 @@
 		case FPC_EIR: {	/* implementation / version register */
 			unsigned int flags;
 
+			if (!(mips_cpu.options & MIPS_CPU_FPU)) {
+				break;
+			}
+
 			__save_flags(flags);
-			enable_cp1();
+			__enable_fpu();
 			__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 			__restore_flags(flags);
 			break;
 		}
 		default:
 			tmp = 0;
-			res = -EIO;
+			ret = -EIO;
 			goto out;
 		}
-		res = put_user(tmp, (unsigned long *) data);
+		ret = put_user(tmp, (unsigned long *) data);
 		goto out;
 		}
 
 	case PTRACE_POKETEXT: /* write the word at location addr. */
 	case PTRACE_POKEDATA:
-		res = 0;
+		ret = 0;
 		if (access_process_vm(child, addr, &data, sizeof(data), 1)
 		    == sizeof(data))
 			break;
-		res = -EIO;
+		ret = -EIO;
 		goto out;
 
 	case PTRACE_POKEUSR: {
 		struct pt_regs *regs;
-		res = 0;
+		ret = 0;
 		regs = (struct pt_regs *) ((unsigned long) child +
 		       KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs));
 
@@ -217,9 +216,9 @@
 						fregs = (unsigned long long *)
 						child->thread.fpu.soft.regs;
 					} else {
-						enable_cp1();
+						__enable_fpu();
 						save_fp(child);
-						disable_cp1();
+						__disable_fpu();
 						last_task_used_math = NULL;
 						regs->cp0_status &= ~ST0_CU1;
 					}
@@ -266,7 +265,7 @@
 			break;
 		default:
 			/* The rest are not allowed. */
-			res = -EIO;
+			ret = -EIO;
 			break;
 		}
 		break;
@@ -274,7 +273,7 @@
 
 	case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
 	case PTRACE_CONT: { /* restart after signal. */
-		res = -EIO;
+		ret = -EIO;
 		if ((unsigned long) data > _NSIG)
 			break;
 		if (request == PTRACE_SYSCALL)
@@ -283,7 +282,7 @@
 			child->ptrace &= ~PT_TRACESYS;
 		child->exit_code = data;
 		wake_up_process(child);
-		res = 0;
+		ret = 0;
 		break;
 		}
 
@@ -293,7 +292,7 @@
 	 * exit.
 	 */
 	case PTRACE_KILL:
-		res = 0;
+		ret = 0;
 		if (child->state == TASK_ZOMBIE)	/* already dead */
 			break;
 		child->exit_code = SIGKILL;
@@ -301,7 +300,7 @@
 		break;
 
 	case PTRACE_DETACH: /* detach a process that was attached. */
-		res = ptrace_detach(child, data);
+		ret = ptrace_detach(child, data);
 		break;
 
 	case PTRACE_SETOPTIONS:
@@ -309,18 +308,18 @@
 			child->ptrace |= PT_TRACESYSGOOD;
 		else
 			child->ptrace &= ~PT_TRACESYSGOOD;
-		res = 0;
+		ret = 0;
 		break;
 
 	default:
-		res = -EIO;
+		ret = -EIO;
 		goto out;
 	}
 out_tsk:
 	free_task_struct(child);
 out:
 	unlock_kernel();
-	return res;
+	return ret;
 }
 
 asmlinkage void syscall_trace(void)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/r2300_misc.S linux/arch/mips/kernel/r2300_misc.S
--- linux.orig/arch/mips/kernel/r2300_misc.S	2000-02-28 15:18:20.000000000 +0000
+++ linux/arch/mips/kernel/r2300_misc.S	1970-01-01 00:00:00.000000000 +0000
@@ -1,199 +0,0 @@
-/* $Id: r2300_misc.S,v 1.8 1999/12/08 22:05:10 harald Exp $
- * misc.S: Misc. exception handling code for R3000/R2000.
- *
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
- *
- * Multi-CPU abstraction reworking:
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- * Further modifications to make this work:
- * Copyright (c) 1998 Harald Koerfgen
- * Copyright (c) 1998, 1999 Gleb Raiko & Vladimir Roganov
- */
-#include <asm/asm.h>
-#include <asm/current.h>
-#include <asm/bootinfo.h>
-#include <asm/cachectl.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/regdef.h>
-#include <asm/segment.h>
-#include <asm/stackframe.h>
-
-	.text
-	.set	mips1
-	.set	noreorder
-
-#undef NOTLB_OPTIMIZE /* If you are paranoid, define this. */
-
-	/* ABUSE of CPP macros 101. */
-
-	/* After this macro runs, the pte faulted on is
-	 * in register PTE, a ptr into the table in which
-	 * the pte belongs is in PTR.
-	 */
-#define LOAD_PTE(pte, ptr) \
-	mfc0	pte, CP0_BADVADDR; \
-	lw	ptr, current_pgd; \
-	srl	pte, pte, 22; \
-	sll	pte, pte, 2; \
-	addu	ptr, ptr, pte; \
-	mfc0	pte, CP0_CONTEXT; \
-	lw	ptr, (ptr); \
-	andi	pte, pte, 0xffc; \
-	addu	ptr, ptr, pte; \
-	lw	pte, (ptr); \
-	nop;
-
-	/* This places the even/odd pte pair in the page
-	 * table at PTR into ENTRYLO0 and ENTRYLO1 using
-	 * TMP as a scratch register.
-	 */
-#define PTE_RELOAD(ptr) \
-	lw	ptr, (ptr)	; \
-	nop			; \
-	mtc0	ptr, CP0_ENTRYLO0; \
-	nop;
-
-#define DO_FAULT(write) \
-	.set	noat; \
-	.set	macro; \
-	SAVE_ALL; \
-	mfc0	a2, CP0_BADVADDR; \
-	STI; \
-	.set	at; \
-	move	a0, sp; \
-	jal	do_page_fault; \
-	 li	a1, write; \
-	j	ret_from_sys_call; \
-	 nop; \
-	.set	noat; \
-	.set	nomacro;
-
-	/* Check is PTE is present, if not then jump to LABEL.
-	 * PTR points to the page table where this PTE is located,
-	 * when the macro is done executing PTE will be restored
-	 * with it's original value.
-	 */
-#define PTE_PRESENT(pte, ptr, label) \
-	andi	pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
-	xori	pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
-	bnez	pte, label; \
-	.set	push;       \
-	.set	reorder;    \
-	 lw	pte, (ptr); \
-	.set	pop; 
-
-	/* Make PTE valid, store result in PTR. */
-#define PTE_MAKEVALID(pte, ptr) \
-	ori	pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \
-	sw	pte, (ptr);
-
-	/* Check if PTE can be written to, if not branch to LABEL.
-	 * Regardless restore PTE with value from PTR when done.
-	 */
-#define PTE_WRITABLE(pte, ptr, label) \
-	andi	pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
-	xori	pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
-	bnez	pte, label; \
-	.set    push;       \
-	.set    reorder;    \
-	lw      pte, (ptr); \
-	.set    pop;
- 
-
-	/* Make PTE writable, update software status bits as well,
-	 * then store at PTR.
-	 */
-#define PTE_MAKEWRITE(pte, ptr) \
-	ori	pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \
-			   _PAGE_VALID | _PAGE_DIRTY); \
-	sw	pte, (ptr);
-
-/*
- * The index register may have the probe fail bit set,
- * because we would trap on access kseg2, i.e. without refill.
- */
-#define TLB_WRITE(reg) \
-	mfc0	reg, CP0_INDEX; \
-	nop; \
-	bltz    reg, 1f; \
-	 nop; \
-	tlbwi; \
-	j	2f; \
-	 nop; \
-1:	tlbwr; \
-2:
-
-#define RET(reg) \
-	mfc0	reg, CP0_EPC; \
-	nop; \
-	jr	reg; \
-	 rfe
-			
-	.set	noreorder
-
-	.align	5
-NESTED(handle_tlbl, PT_SIZE, sp)
-	.set	noat
-
-#ifndef NOTLB_OPTIMIZE
-	/* Test present bit in entry. */
-	LOAD_PTE(k0, k1)
-        tlbp
-        PTE_PRESENT(k0, k1, nopage_tlbl)
-        PTE_MAKEVALID(k0, k1)
-        PTE_RELOAD(k1)
-	TLB_WRITE(k0)
-	RET(k0)
-nopage_tlbl:
-#endif
-
-	DO_FAULT(0)
-END(handle_tlbl)
-
-NESTED(handle_tlbs, PT_SIZE, sp)
-	.set	noat
-
-#ifndef NOTLB_OPTIMIZE
-	LOAD_PTE(k0, k1)
-	tlbp                            # find faulting entry
-	PTE_WRITABLE(k0, k1, nopage_tlbs)
-	PTE_MAKEWRITE(k0, k1)
-	PTE_RELOAD(k1)
-	TLB_WRITE(k0)
-	RET(k0)
-nopage_tlbs:
-#endif
-
-	DO_FAULT(1)
-END(handle_tlbs)
-
-	.align	5
-NESTED(handle_mod, PT_SIZE, sp)
-	.set	noat
-#ifndef NOTLB_OPTIMIZE
-	LOAD_PTE(k0, k1)
-	tlbp					# find faulting entry
-	andi	k0, k0, _PAGE_WRITE
-	beqz	k0, nowrite_mod
-	.set	push
-	.set    reorder
-	lw	k0, (k1)
-	.set    pop
-
-	/* Present and writable bits set, set accessed and dirty bits. */
-	PTE_MAKEWRITE(k0, k1)
-
-	/* Now reload the entry into the tlb. */
-	PTE_RELOAD(k1)
-	tlbwi
-	RET(k0)
-#endif
-
-nowrite_mod:
-	DO_FAULT(1)
-END(handle_mod)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/r2300_switch.S linux/arch/mips/kernel/r2300_switch.S
--- linux.orig/arch/mips/kernel/r2300_switch.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/r2300_switch.S	2002-08-01 06:42:37.000000000 +0000
@@ -10,15 +10,15 @@
  * Further modifications to make this work:
  * Copyright (c) 1998-2000 Harald Koerfgen
  */
+#include <linux/config.h>
 #include <asm/asm.h>
-#include <asm/bootinfo.h>
 #include <asm/cachectl.h>
 #include <asm/current.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/offset.h>
 #include <asm/page.h>
-#include <asm/pgtable.h>
+#include <asm/pgtable-bits.h>
 #include <asm/processor.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
@@ -72,7 +72,7 @@
 
 LEAF(lazy_fpu_switch)
 	mfc0	t0, CP0_STATUS			# enable cp1
-	li	t3, 0x20000000
+	li	t3, ST0_CU1
 	or	t0, t3
 	mtc0	t0, CP0_STATUS
 
@@ -118,7 +118,7 @@
 
 LEAF(init_fpu)
 	mfc0	t0, CP0_STATUS
-	li	t1, 0x20000000
+	li	t1, ST0_CU1
 	or	t0, t1
 	mtc0	t0, CP0_STATUS
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/r4k_misc.S linux/arch/mips/kernel/r4k_misc.S
--- linux.orig/arch/mips/kernel/r4k_misc.S	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/kernel/r4k_misc.S	1970-01-01 00:00:00.000000000 +0000
@@ -1,236 +0,0 @@
-/* $Id: r4k_misc.S,v 1.8 1999/10/09 00:00:58 ralf Exp $
- *
- * r4k_misc.S: Misc. exception handling code for r4k.
- *
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
- *
- * Multi-cpu abstraction and reworking:
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- */
-/**************************************************************************
- *  14 Nov, 2000.
- *  Made support for MIPS32 CPUs.
- *
- *  Carsten Langgaard, carstenl@mips.com
- *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *************************************************************************/
-#include <asm/asm.h>
-#include <asm/current.h>
-#include <asm/offset.h>
-#include <asm/bootinfo.h>
-#include <asm/cachectl.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-
-#undef NOTLB_OPTIMIZE /* If you are paranoid, define this. */
-
-	/* ABUSE of CPP macros 101. */
-
-	/* After this macro runs, the pte faulted on is
-	 * in register PTE, a ptr into the table in which
-	 * the pte belongs is in PTR.
-	 */
-
-#ifdef CONFIG_SMP
-#define GET_PGD(scratch, ptr)        \
-	mfc0    ptr, CP0_CONTEXT;    \
-	la      scratch, current_pgd;\
-	srl     ptr, 23;             \
-	sll     ptr, 2;              \
-	addu    ptr, scratch, ptr;   \
-	lw      ptr, (ptr);          
-#else
-#define GET_PGD(scratch, ptr)    \
-	lw	ptr, current_pgd;
-#endif
-	
-	
-#define LOAD_PTE(pte, ptr) \
-	GET_PGD(pte, ptr)          \
-	mfc0	pte, CP0_BADVADDR; \
-	srl	pte, pte, 22; \
-	sll	pte, pte, 2; \
-	addu	ptr, ptr, pte; \
-	mfc0	pte, CP0_BADVADDR; \
-	lw	ptr, (ptr); \
-	srl	pte, pte, 10; \
-	and	pte, pte, 0xffc; \
-	addu	ptr, ptr, pte; \
-	lw	pte, (ptr);
-
-	/* This places the even/odd pte pair in the page
-	 * table at PTR into ENTRYLO0 and ENTRYLO1 using
-	 * TMP as a scratch register.
-	 */
-#define PTE_RELOAD(ptr, tmp) \
-	ori	ptr, ptr, 0x4; \
-	xori	ptr, ptr, 0x4; \
-	lw	tmp, 4(ptr); \
-	lw	ptr, 0(ptr); \
-	srl	tmp, tmp, 6; \
-	mtc0	tmp, CP0_ENTRYLO1; \
-	srl	ptr, ptr, 6; \
-	mtc0	ptr, CP0_ENTRYLO0;
-
-#define DO_FAULT(write) \
-	.set	noat; \
-	SAVE_ALL; \
-	mfc0	a2, CP0_BADVADDR; \
-	STI; \
-	.set	at; \
-	move	a0, sp; \
-	jal	do_page_fault; \
-	 li	a1, write; \
-	j	ret_from_sys_call; \
-	 nop; \
-	.set	noat;
-
-	/* Check is PTE is present, if not then jump to LABEL.
-	 * PTR points to the page table where this PTE is located,
-	 * when the macro is done executing PTE will be restored
-	 * with it's original value.
-	 */
-#define PTE_PRESENT(pte, ptr, label) \
-	andi	pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
-	xori	pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
-	bnez	pte, label; \
-	 lw	pte, (ptr);
-
-	/* Make PTE valid, store result in PTR. */
-#define PTE_MAKEVALID(pte, ptr) \
-	ori	pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \
-	sw	pte, (ptr);
-
-	/* Check if PTE can be written to, if not branch to LABEL.
-	 * Regardless restore PTE with value from PTR when done.
-	 */
-#define PTE_WRITABLE(pte, ptr, label) \
-	andi	pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
-	xori	pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
-	bnez	pte, label; \
-	 lw	pte, (ptr);
-
-	/* Make PTE writable, update software status bits as well,
-	 * then store at PTR.
-	 */
-#define PTE_MAKEWRITE(pte, ptr) \
-	ori	pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \
-			   _PAGE_VALID | _PAGE_DIRTY); \
-	sw	pte, (ptr);
-
-	.set	noreorder
-
-/*
- * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
- * 2. A timing hazard exists for the TLBP instruction.
- *
- *      stalling_instruction
- *      TLBP
- *
- * The JTLB is being read for the TLBP throughout the stall generated by the
- * previous instruction. This is not really correct as the stalling instruction
- * can modify the address used to access the JTLB.  The failure symptom is that
- * the TLBP instruction will use an address created for the stalling instruction
- * and not the address held in C0_ENHI and thus report the wrong results.
- *
- * The software work-around is to not allow the instruction preceding the TLBP
- * to stall - make it an NOP or some other instruction guaranteed not to stall.
- *
- * Errata 2 will not be fixed.  This errata is also on the R5000.
- *
- * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
- */
-#define R5K_HAZARD nop
-
-	/*
-	 * Note for many R4k variants tlb probes cannot be executed out
-	 * of the instruction cache else you get bogus results.
-	 */
-	.align	5
-	NESTED(handle_tlbl, PT_SIZE, sp)
-	.set	noat
-invalid_tlbl:
-#ifndef NOTLB_OPTIMIZE
-	/* Test present bit in entry. */
-	LOAD_PTE(k0, k1)
-	R5K_HAZARD
-	tlbp
-	PTE_PRESENT(k0, k1, nopage_tlbl)
-	PTE_MAKEVALID(k0, k1)
-	PTE_RELOAD(k1, k0)
-	nop
-	b	1f
-	 tlbwi
-1:
-	nop
-	.set	mips3	
-	eret
-	.set	mips0
-#endif
-
-nopage_tlbl:
-	DO_FAULT(0)
-	END(handle_tlbl)
-
-	.align	5
-	NESTED(handle_tlbs, PT_SIZE, sp)
-	.set	noat
-#ifndef NOTLB_OPTIMIZE
-	LOAD_PTE(k0, k1)
-	R5K_HAZARD
-	tlbp				# find faulting entry
-	PTE_WRITABLE(k0, k1, nopage_tlbs)
-	PTE_MAKEWRITE(k0, k1)
-	PTE_RELOAD(k1, k0)
-	nop
-	b	1f
-	 tlbwi
-1:
-	nop
-	.set	mips3	
-	eret
-	.set	mips0
-#endif
-
-nopage_tlbs:
-	DO_FAULT(1)
-	END(handle_tlbs)
-
-	.align	5
-	NESTED(handle_mod, PT_SIZE, sp)
-	.set	noat
-#ifndef NOTLB_OPTIMIZE
-	LOAD_PTE(k0, k1)
-	R5K_HAZARD
-	tlbp					# find faulting entry
-	andi	k0, k0, _PAGE_WRITE
-	beqz	k0, nowrite_mod
-	 lw	k0, (k1)
-
-	/* Present and writable bits set, set accessed and dirty bits. */
-	PTE_MAKEWRITE(k0, k1)
-#if 0
-	ori	k0, k0, (_PAGE_ACCESSED | _PAGE_DIRTY)
-	sw	k0, (k1)
-#endif
-
-	/* Now reload the entry into the tlb. */
-	PTE_RELOAD(k1, k0)
-	nop
-	b	1f
-	 tlbwi
-1:
-	nop
-	.set	mips3
-	eret
-	.set	mips0
-#endif
-
-nowrite_mod:
-	DO_FAULT(1)
-	END(handle_mod)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/r4k_switch.S linux/arch/mips/kernel/r4k_switch.S
--- linux.orig/arch/mips/kernel/r4k_switch.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/r4k_switch.S	2002-08-01 06:42:47.000000000 +0000
@@ -12,14 +12,13 @@
  */
 #include <linux/config.h>
 #include <asm/asm.h>
-#include <asm/bootinfo.h>
 #include <asm/cachectl.h>
 #include <asm/current.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/offset.h>
 #include <asm/page.h>
-#include <asm/pgtable.h>
+#include <asm/pgtable-bits.h>
 #include <asm/processor.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
@@ -78,7 +77,7 @@
 
 LEAF(lazy_fpu_switch)
 	mfc0	t0, CP0_STATUS			# enable cp1
-	li	t3, 0x20000000
+	li	t3, ST0_CU1
 	or	t0, t3
 	mtc0	t0, CP0_STATUS
 
@@ -127,7 +126,7 @@
 LEAF(init_fpu)
 	.set	mips3
 	mfc0	t0, CP0_STATUS
-	li	t1, 0x20000000
+	li	t1, ST0_CU1
 	or	t0, t1
 	mtc0	t0, CP0_STATUS
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/scall_o32.S linux/arch/mips/kernel/scall_o32.S
--- linux.orig/arch/mips/kernel/scall_o32.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/scall_o32.S	2002-08-01 06:42:47.000000000 +0000
@@ -3,23 +3,20 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1997, 1998, 1999, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
  */
-#include <asm/asm.h>
+#include <linux/config.h>
 #include <linux/errno.h>
+#include <asm/asm.h>
 #include <asm/current.h>
 #include <asm/mipsregs.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 #include <asm/isadep.h>
+#include <asm/sysmips.h>
 #include <asm/unistd.h>
 
-/* This duplicates the definition from <linux/sched.h> */
-#define PT_TRACESYS	0x00000002	/* tracing system calls */
-
-/* This duplicates the definition from <asm/signal.h> */
-#define SIGILL		4		/* Illegal instruction (ANSI).  */
-
 /* Highest syscall used of any syscall flavour */
 #define MAX_SYSCALL_NO	__NR_Linux + __NR_Linux_syscalls
 
@@ -86,13 +83,13 @@
 	ori	t0, t0, 1
 	mtc0	t0, CP0_STATUS
 
+	SAVE_STATIC
 	move	a0, zero
 	move	a1, sp
 	jal	do_signal
 	b	restore_all
 
 o32_reschedule:
-	SAVE_STATIC
 	jal	schedule
 	b	o32_ret_from_sys_call
 
@@ -192,3 +189,146 @@
 	sw	t0, PT_R7(sp)
 	j	ret_from_sys_call
 	END(handle_sys)
+
+	LEAF(mips_atomic_set)
+	andi	v0, a1, 3			# must be word aligned
+	bnez	v0, bad_alignment
+
+	lw	v1, THREAD_CURDS($28)		# in legal address range?
+	addiu	a0, a1, 4
+	or	a0, a0, a1
+	and	a0, a0, v1
+	bltz	a0, bad_address
+
+#ifdef CONFIG_CPU_HAS_LLSC
+	/* Ok, this is the ll/sc case.  World is sane :-)  */
+1:	ll	v0, (a1)
+	move	a0, a2
+2:	sc	a0, (a1)
+	beqz	a0, 1b
+
+	.section __ex_table,"a"
+	PTR	1b, bad_stack
+	PTR	2b, bad_stack
+	.previous
+#else
+	sw	a1, 16(sp)
+	sw	a2, 20(sp)
+
+	move	a0, sp
+	move	a2, a1
+	li	a1, 1
+	jal	do_page_fault
+
+	lw	a1, 16(sp)
+	lw	a2, 20(sp)
+
+	/*
+	 * At this point the page should be readable and writable unless
+	 * there was no more memory available.
+	 */
+1:	lw	v0, (a1)
+2:	sw	a2, (a1)
+
+	.section __ex_table,"a"
+	PTR	1b, no_mem
+	PTR	2b, no_mem
+	.previous
+#endif
+
+	sw	v0, PT_R2(sp)		# result
+1:
+
+	/* Success, so skip usual error handling garbage.  */
+	lw	t0, TASK_PTRACE($28)	# syscall tracing enabled?
+	andi	t0, PT_TRACESYS
+	bnez	t0, 1f
+	b	o32_ret_from_sys_call
+
+1:	SAVE_STATIC
+	jal	syscall_trace
+	li	a3, 0			# success
+	j	ret_from_sys_call
+
+no_mem:	li	v0, -ENOMEM
+	jr	ra
+
+bad_address:
+	li	v0, -EFAULT
+	jr	ra
+
+bad_alignment:
+	li	v0, -EINVAL
+	jr	ra
+	END(mips_atomic_set)	
+
+	LEAF(sys_sysmips)
+	beq	a0, MIPS_ATOMIC_SET, mips_atomic_set
+	j	_sys_sysmips
+	END(sys_sysmips)
+
+	LEAF(sys_syscall)
+	lw	t0, PT_R29(sp)			# user sp
+
+	sltu	v0, a0, __NR_Linux + __NR_Linux_syscalls + 1
+	beqz	v0, enosys
+
+	sll	v0, t1, 2
+	la	v1, sys_syscall
+	lw	t2, sys_call_table(v0)		# function pointer
+	lbu	t4, sys_narg_table(t1)		# number of arguments
+
+	li	v0, -EINVAL
+	beq	t2, v1, out			# do not recurse
+
+	beqz	t2, enosys			# null function pointer?
+
+	andi	v0, t0, 0x3			# unaligned stack pointer?
+	bnez	v0, sigsegv
+
+	addu	v0, t0, 16			# v0 = usp + 16
+	addu	t1, v0, 12			# 3 32-bit arguments
+	lw	v1, THREAD_CURDS($28)
+	or	v0, v0, t1
+	and	v1, v1, v0
+	bltz	v1, efault
+
+	move	a0, a1				# shit argument registers
+	move	a1, a2
+	move	a2, a3
+
+1:	lw	a3, 16(t0)
+2:	lw	t3, 20(t0)
+3:	lw	t4, 24(t0)
+
+	.section	__ex_table, "a"
+	.word	1b, efault
+	.word	2b, efault
+	.word	3b, efault
+	.previous
+
+	sw	t3, 16(sp)			# put into new stackframe
+	sw	t4, 20(sp)
+
+	bnez	t4, 1f				# zero arguments?
+	addu	a0, sp, 32			# then pass sp in a0
+1:
+
+	sw	t3, 16(sp)
+	sw	v1, 20(sp)
+	jr	t2
+	/* Unreached */
+
+enosys:	li	v0, -ENOSYS
+	b	out
+
+sigsegv:
+	li	a0, _SIGSEGV
+	move	a1, $28
+	jal	force_sig
+	/* Fall through */
+
+efault:	li	v0, -EFAULT
+
+out:	jr	ra
+	END(sys_syscall)
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/setup.c linux/arch/mips/kernel/setup.c
--- linux.orig/arch/mips/kernel/setup.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/setup.c	2002-08-01 06:42:34.000000000 +0000
@@ -4,9 +4,10 @@
  * for more details.
  *
  * Copyright (C) 1995  Linus Torvalds
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000  Ralf Baechle
+ * Copyright (C) 1995  Waldorf Electronics
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001  Ralf Baechle
  * Copyright (C) 1996  Stoned Elipot
- * Copyright (C) 2000  Maciej W. Rozycki
+ * Copyright (C) 2000, 2001  Maciej W. Rozycki
  */
 #include <linux/config.h>
 #include <linux/errno.h>
@@ -16,10 +17,10 @@
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 #include <linux/stddef.h>
 #include <linux/string.h>
 #include <linux/unistd.h>
-#include <linux/ptrace.h>
 #include <linux/slab.h>
 #include <linux/user.h>
 #include <linux/utsname.h>
@@ -35,14 +36,12 @@
 #include <asm/cachectl.h>
 #include <asm/cpu.h>
 #include <asm/io.h>
-#include <asm/stackframe.h>
+#include <asm/ptrace.h>
 #include <asm/system.h>
-#ifdef CONFIG_SGI_IP22
-#include <asm/sgialib.h>
-#endif
 
-
-struct mips_cpuinfo boot_cpu_data = { 0, NULL, NULL, 0 };
+#ifndef CONFIG_SMP
+struct cpuinfo_mips cpu_data[1];
+#endif
 
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -95,21 +94,24 @@
 unsigned char aux_device_present;
 extern char _ftext, _etext, _fdata, _edata, _end;
 
-static char command_line[COMMAND_LINE_SIZE];
-       char saved_command_line[COMMAND_LINE_SIZE];
-extern char arcs_cmdline[COMMAND_LINE_SIZE];
+static char command_line[CL_SIZE];
+       char saved_command_line[CL_SIZE];
+extern char arcs_cmdline[CL_SIZE];
 
 /*
  * mips_io_port_base is the begin of the address space to which x86 style
  * I/O ports are mapped.
  */
-unsigned long mips_io_port_base;
+const unsigned long mips_io_port_base = -1;
+EXPORT_SYMBOL(mips_io_port_base);
+
 
 /*
  * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
  * for the processor.
  */
 unsigned long isa_slot_offset;
+EXPORT_SYMBOL(isa_slot_offset);
 
 extern void sgi_sysinit(void);
 extern void SetUpBootInfo(void);
@@ -120,6 +122,49 @@
 static struct resource code_resource = { "Kernel code" };
 static struct resource data_resource = { "Kernel data" };
 
+static inline void check_wait(void)
+{
+	printk("Checking for 'wait' instruction... ");
+	switch(mips_cpu.cputype) {
+	case CPU_R3081:
+	case CPU_R3081E:
+		cpu_wait = r3081_wait;
+		printk(" available.\n");
+		break;
+	case CPU_TX3927:
+	case CPU_TX39XX:
+		cpu_wait = r39xx_wait;
+		printk(" available.\n");
+		break;
+	case CPU_R4200: 
+/*	case CPU_R4300: */
+	case CPU_R4600: 
+	case CPU_R4640: 
+	case CPU_R4650: 
+	case CPU_R4700: 
+	case CPU_R5000: 
+	case CPU_NEVADA:
+	case CPU_RM7000:
+	case CPU_TX49XX:
+	case CPU_4KC:
+	case CPU_4KEC:
+	case CPU_4KSC:
+	case CPU_5KC:
+/*	case CPU_20KC:*/
+		cpu_wait = r4k_wait;
+		printk(" available.\n");
+		break;
+	default:
+		printk(" unavailable.\n");
+		break;
+	}
+}
+
+void __init check_bugs(void)
+{
+	check_wait();
+}
+
 /*
  * Probe whether cpu has config register by trying to play with
  * alternate cache bit and see whether it matters.
@@ -142,9 +187,34 @@
 #endif
 }
 
+/*
+ * Get the FPU Implementation/Revision.
+ */
+static inline unsigned long cpu_get_fpu_id(void)
+{
+	unsigned long tmp, fpu_id;
+
+	tmp = read_32bit_cp0_register(CP0_STATUS);
+	__enable_fpu();
+	fpu_id = read_32bit_cp1_register(CP1_REVISION);
+	write_32bit_cp0_register(CP0_STATUS, tmp);
+	return fpu_id;
+}
+
+/*
+ * Check the CPU has an FPU the official way.
+ */
+static inline int cpu_has_fpu(void)
+{
+	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
+}
+
 /* declaration of the global struct */
-struct mips_cpu mips_cpu = {PRID_IMP_UNKNOWN, CPU_UNKNOWN, 0, 0, 0,
-			    {0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0}};
+struct mips_cpu mips_cpu = {
+    processor_id:	PRID_IMP_UNKNOWN,
+    fpu_id:		FPIR_IMP_NONE,
+    cputype:		CPU_UNKNOWN
+};
 
 /* Shortcut for assembler access to mips_cpu.options */
 int *cpuoptions = &mips_cpu.options;
@@ -154,11 +224,27 @@
 
 static inline void cpu_probe(void)
 {
-
 #ifdef CONFIG_CPU_MIPS32
+	unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
 	unsigned long config1;
-#endif
 
+        if (config0 & (1 << 31)) {
+		/* MIPS32 compliant CPU. Read Config 1 register. */
+		mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+		mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
+			MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
+		config1 = read_mips32_cp0_config1();
+		if (config1 & (1 << 3))
+			mips_cpu.options |= MIPS_CPU_WATCH;
+		if (config1 & (1 << 2))
+			mips_cpu.options |= MIPS_CPU_MIPS16;
+		if (config1 & (1 << 1))
+			mips_cpu.options |= MIPS_CPU_EJTAG;
+		if (config1 & 1)
+			mips_cpu.options |= MIPS_CPU_FPU;
+		mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+	}
+#endif
 	mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
 	switch (mips_cpu.processor_id & 0xff0000) {
 	case PRID_COMP_LEGACY:
@@ -166,7 +252,9 @@
 		case PRID_IMP_R2000:
 			mips_cpu.cputype = CPU_R2000;
 			mips_cpu.isa_level = MIPS_CPU_ISA_I;
-			mips_cpu.options = MIPS_CPU_TLB;
+			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
+			if (cpu_has_fpu())
+				mips_cpu.options |= MIPS_CPU_FPU;
 			mips_cpu.tlbsize = 64;
 			break;
 		case PRID_IMP_R3000:
@@ -178,7 +266,9 @@
 			else
 				mips_cpu.cputype = CPU_R3000;
 			mips_cpu.isa_level = MIPS_CPU_ISA_I;
-			mips_cpu.options = MIPS_CPU_TLB;
+			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
+			if (cpu_has_fpu())
+				mips_cpu.options |= MIPS_CPU_FPU;
 			mips_cpu.tlbsize = 64;
 			break;
 		case PRID_IMP_R4000:
@@ -187,8 +277,9 @@
 			else
 				mips_cpu.cputype = CPU_R4000SC;
 			mips_cpu.isa_level = MIPS_CPU_ISA_III;
-			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
-				           MIPS_CPU_WATCH | MIPS_CPU_VCE;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR | MIPS_CPU_WATCH |
+			                   MIPS_CPU_VCE;
 			mips_cpu.tlbsize = 48;
 			break;
                 case PRID_IMP_VR41XX:
@@ -197,67 +288,101 @@
                         mips_cpu.options = R4K_OPTS;
                         mips_cpu.tlbsize = 32;
                         break;
+		case PRID_IMP_R4300:
+			mips_cpu.cputype = CPU_R4300;
+			mips_cpu.isa_level = MIPS_CPU_ISA_III;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+					   MIPS_CPU_32FPR;
+			mips_cpu.tlbsize = 32;
+			break;
 		case PRID_IMP_R4600:
 			mips_cpu.cputype = CPU_R4600;
 			mips_cpu.isa_level = MIPS_CPU_ISA_III;
 			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
 			mips_cpu.tlbsize = 48;
 			break;
-/*
- * This processor doesn't have an MMU, so it's not "real easy" to
- * run Linux on it. It is left purely for documentation.
- *		case PRID_IMP_R4650:
+		#if 0
+ 		case PRID_IMP_R4650:
+			/*
+			 * This processor doesn't have an MMU, so it's not
+			 * "real easy" to run Linux on it. It is left purely
+			 * for documentation.  Commented out because it shares
+			 * it's c0_prid id number with the TX3900.
+			 */
 	 		mips_cpu.cputype = CPU_R4650;
 		 	mips_cpu.isa_level = MIPS_CPU_ISA_III;
 			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
 		        mips_cpu.tlbsize = 48;
 			break;
-*/
+		#endif
 		case PRID_IMP_TX39:
 			mips_cpu.isa_level = MIPS_CPU_ISA_I;
 			mips_cpu.options = MIPS_CPU_TLB;
 
-			switch (mips_cpu.processor_id & 0xff) {
-			case PRID_REV_TX3912:
-				mips_cpu.cputype = CPU_TX3912;
-				mips_cpu.tlbsize = 32;
-				break;
-			case PRID_REV_TX3922:
-				mips_cpu.cputype = CPU_TX3922;
-				mips_cpu.tlbsize = 64;
-				break;
-			case PRID_REV_TX3927:
+			if ((mips_cpu.processor_id & 0xf0) ==
+			    (PRID_REV_TX3927 & 0xf0)) {
 				mips_cpu.cputype = CPU_TX3927;
 				mips_cpu.tlbsize = 64;
-				break;
-			default:
-				mips_cpu.cputype = CPU_UNKNOWN;
-				break;
+				mips_cpu.icache.ways = 2;
+				mips_cpu.dcache.ways = 2;
+			} else {
+				switch (mips_cpu.processor_id & 0xff) {
+				case PRID_REV_TX3912:
+					mips_cpu.cputype = CPU_TX3912;
+					mips_cpu.tlbsize = 32;
+					break;
+				case PRID_REV_TX3922:
+					mips_cpu.cputype = CPU_TX3922;
+					mips_cpu.tlbsize = 64;
+					break;
+				default:
+					mips_cpu.cputype = CPU_UNKNOWN;
+					break;
+				}
 			}
 			break;
 		case PRID_IMP_R4700:
 			mips_cpu.cputype = CPU_R4700;
 			mips_cpu.isa_level = MIPS_CPU_ISA_III;
-			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR;
 			mips_cpu.tlbsize = 48;
 			break;
+		case PRID_IMP_TX49:
+			mips_cpu.cputype = CPU_TX49XX;
+			mips_cpu.isa_level = MIPS_CPU_ISA_III;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR;
+			mips_cpu.tlbsize = 48;
+			mips_cpu.icache.ways = 4;
+			mips_cpu.dcache.ways = 4;
+			break;
 		case PRID_IMP_R5000:
 			mips_cpu.cputype = CPU_R5000;
 			mips_cpu.isa_level = MIPS_CPU_ISA_IV; 
-			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR;
 			mips_cpu.tlbsize = 48;
 			break;
 		case PRID_IMP_R5432:
 			mips_cpu.cputype = CPU_R5432;
 			mips_cpu.isa_level = MIPS_CPU_ISA_IV; 
-			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR | MIPS_CPU_WATCH;
+			mips_cpu.tlbsize = 48;
+			break;
+		case PRID_IMP_R5500:
+			mips_cpu.cputype = CPU_R5500;
+			mips_cpu.isa_level = MIPS_CPU_ISA_IV; 
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR | MIPS_CPU_WATCH;
 			mips_cpu.tlbsize = 48;
 			break;
 		case PRID_IMP_NEVADA:
 			mips_cpu.cputype = CPU_NEVADA;
 			mips_cpu.isa_level = MIPS_CPU_ISA_IV; 
-			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 
-				           MIPS_CPU_DIVEC;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
 			mips_cpu.tlbsize = 48;
 			mips_cpu.icache.ways = 2;
 			mips_cpu.dcache.ways = 2;
@@ -277,7 +402,17 @@
 		case PRID_IMP_RM7000:
 			mips_cpu.cputype = CPU_RM7000;
 			mips_cpu.isa_level = MIPS_CPU_ISA_IV;
-			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+			mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+			                   MIPS_CPU_32FPR;
+			/*
+			 * Undocumented RM7000:  Bit 29 in the info register of
+			 * the RM7000 v2.0 indicates if the TLB has 48 or 64
+			 * entries.
+			 *
+			 * 29      1 =>    64 entry JTLB
+			 *         0 =>    48 entry JTLB
+			 */
+			mips_cpu.tlbsize = (get_info() & (1 << 29)) ? 64 : 48;
 			break;
 		case PRID_IMP_R8000:
 			mips_cpu.cputype = CPU_R8000;
@@ -294,6 +429,14 @@
 				           MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
 			mips_cpu.tlbsize = 64;
 			break;
+		case PRID_IMP_R12000:
+			mips_cpu.cputype = CPU_R12000;
+			mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
+				           MIPS_CPU_FPU | MIPS_CPU_32FPR | 
+				           MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
+			mips_cpu.tlbsize = 64;
+			break;
 		default:
 			mips_cpu.cputype = CPU_UNKNOWN;
 			break;
@@ -304,80 +447,53 @@
 		switch (mips_cpu.processor_id & 0xff00) {
 		case PRID_IMP_4KC:
 			mips_cpu.cputype = CPU_4KC;
-			goto cpu_4kc;
+			break;
 		case PRID_IMP_4KEC:
 			mips_cpu.cputype = CPU_4KEC;
-			goto cpu_4kc;
+			break;
 		case PRID_IMP_4KSC:
 			mips_cpu.cputype = CPU_4KSC;
-cpu_4kc:
-			/* Why do we set all these options by default, THEN query them?? */
-			mips_cpu.cputype = MIPS_CPU_ISA_M32;
-			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
-				           MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | 
-				           MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
-			config1 = read_mips32_cp0_config1();
-			if (config1 & (1 << 3))
-				mips_cpu.options |= MIPS_CPU_WATCH;
-			if (config1 & (1 << 2))
-				mips_cpu.options |= MIPS_CPU_MIPS16;
-			if (config1 & 1)
-				mips_cpu.options |= MIPS_CPU_FPU;
-			mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
 			break;
 		case PRID_IMP_5KC:
 			mips_cpu.cputype = CPU_5KC;
-			mips_cpu.cputype = MIPS_CPU_ISA_M64;
-			/* See comment above about querying options */
-			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
-				           MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | 
-				           MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
-			config1 = read_mips32_cp0_config1();
-			if (config1 & (1 << 3))
-				mips_cpu.options |= MIPS_CPU_WATCH;
-			if (config1 & (1 << 2))
-				mips_cpu.options |= MIPS_CPU_MIPS16;
-			if (config1 & 1)
-				mips_cpu.options |= MIPS_CPU_FPU;
+			mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+			break;
+		case PRID_IMP_20KC:
+			mips_cpu.cputype = CPU_20KC;
+			mips_cpu.isa_level = MIPS_CPU_ISA_M64;
 			break;
-			mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
 		default:
 			mips_cpu.cputype = CPU_UNKNOWN;
 			break;
 		}		
 		break;
-#endif
 	case PRID_COMP_ALCHEMY:
 		switch (mips_cpu.processor_id & 0xff00) {
-#ifdef CONFIG_CPU_MIPS32
-		case PRID_IMP_AU1000:
-			mips_cpu.cputype = CPU_AU1000;
-			mips_cpu.isa_level = MIPS_CPU_ISA_M32;
-			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
-					   MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | 
-					   MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
-			config1 = read_mips32_cp0_config1();
-			if (config1 & (1 << 3))
-				mips_cpu.options |= MIPS_CPU_WATCH;
-			if (config1 & (1 << 2))
-				mips_cpu.options |= MIPS_CPU_MIPS16;
-			if (config1 & 1)
-				mips_cpu.options |= MIPS_CPU_FPU;
-			mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+		case PRID_IMP_AU1_REV1:
+		case PRID_IMP_AU1_REV2:
+			if (mips_cpu.processor_id & 0xff000000)
+				mips_cpu.cputype = CPU_AU1500;
+			else
+				mips_cpu.cputype = CPU_AU1000;
 			break;
-#endif
 		default:
 			mips_cpu.cputype = CPU_UNKNOWN;
 			break;
 		}
 		break;
+#endif /* CONFIG_CPU_MIPS32 */
 	case PRID_COMP_SIBYTE:
 		switch (mips_cpu.processor_id & 0xff00) {
 		case PRID_IMP_SB1:
 			mips_cpu.cputype = CPU_SB1;
-			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
-				           MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_FPU |
-		      	           MIPS_CPU_VCE;
+			mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+			mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+			                   MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+			                   MIPS_CPU_MCHECK;
+#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
+			/* FPU in pass1 is known to have issues. */
+			mips_cpu.options |= MIPS_CPU_FPU;
+#endif
 			break;
 		default:
 			mips_cpu.cputype = CPU_UNKNOWN;
@@ -387,6 +503,15 @@
 	default:
 		mips_cpu.cputype = CPU_UNKNOWN;
 	}
+	if (mips_cpu.options & MIPS_CPU_FPU)
+		mips_cpu.fpu_id = cpu_get_fpu_id();
+}
+
+static inline void cpu_report(void)
+{
+	printk("CPU revision is: %08x\n", mips_cpu.processor_id);
+	if (mips_cpu.options & MIPS_CPU_FPU)
+		printk("FPU revision is: %08x\n", mips_cpu.fpu_id);
 }
 
 asmlinkage void __init
@@ -403,6 +528,8 @@
 	sgi_sysinit();
 #endif
 
+	cpu_report();
+
 	/*
 	 * Determine the mmu/cache attached to this machine,
 	 * then flush the tlb and caches.  On the r4xx0
@@ -410,16 +537,14 @@
 	 */
 	loadmmu();
 
-	/* Disable coprocessors and set FPU for 16 FPRs */
-	s = read_32bit_cp0_register(CP0_STATUS);
-	s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
-	s |= ST0_CU0;
-	write_32bit_cp0_register(CP0_STATUS, s);
+	/* Disable coprocessors and set FPU for 16/32 FPR register model */
+	clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
+	set_cp0_status(ST0_CU0);
 
 	start_kernel();
 }
 
-void __init add_memory_region(unsigned long start, unsigned long size,
+void __init add_memory_region(phys_t start, phys_t size,
 			      long type)
 {
 	int x = boot_mem_map.nr_map;
@@ -440,8 +565,10 @@
 	int i;
 
 	for (i = 0; i < boot_mem_map.nr_map; i++) {
-		printk(" memory: %08lx @ %08lx ",
-			boot_mem_map.map[i].size, boot_mem_map.map[i].addr);
+		printk(" memory: %08Lx @ %08Lx ",
+			(u64) boot_mem_map.map[i].size,
+		        (u64) boot_mem_map.map[i].addr);
+
 		switch (boot_mem_map.map[i].type) {
 		case BOOT_MEM_RAM:
 			printk("(usable)\n");
@@ -498,7 +625,7 @@
 		c = *(from++);
 		if (!c)
 			break;
-		if (COMMAND_LINE_SIZE <= ++len)
+		if (CL_SIZE <= ++len)
 			break;
 		*(to++) = c;
 	}
@@ -514,19 +641,30 @@
 {
 	void atlas_setup(void);
 	void baget_setup(void);
+	void cobalt_setup(void);
 	void ddb_setup(void);
 	void decstation_setup(void);
 	void deskstation_setup(void);
 	void jazz_setup(void);
 	void sni_rm200_pci_setup(void);
-	void sgi_setup(void);
+	void ip22_setup(void);
         void ev96100_setup(void);
 	void malta_setup(void);
+	void ikos_setup(void);
 	void momenco_ocelot_setup(void);
 	void nino_setup(void);
+	void nec_osprey_setup(void);
+	void jmr3927_setup(void);
+ 	void it8172_setup(void);
+	void swarm_setup(void);
+	void hp_setup(void);
 
 	unsigned long bootmap_size;
-	unsigned long start_pfn, max_pfn, first_usable_pfn;
+	unsigned long start_pfn, max_pfn, max_low_pfn, first_usable_pfn;
+#ifdef CONFIG_BLK_DEV_INITRD
+	unsigned long tmp;
+	unsigned long* initrd_header;
+#endif
 
 	int i;
 
@@ -551,6 +689,11 @@
 		baget_setup();
 		break;
 #endif
+#ifdef CONFIG_MIPS_COBALT
+        case MACH_GROUP_COBALT:
+                cobalt_setup();
+                break;
+#endif
 #ifdef CONFIG_DECSTATION
 	case MACH_GROUP_DEC:
 		decstation_setup();
@@ -579,7 +722,7 @@
 #ifdef CONFIG_SGI_IP22
 	/* As of now this is only IP22.  */
 	case MACH_GROUP_SGI:
-		sgi_setup();
+		ip22_setup();
 		break;
 #endif
 #ifdef CONFIG_SNI_RM200_PCI
@@ -602,6 +745,11 @@
                ddb_setup();
                break;
 #endif
+#ifdef CONFIG_NEC_OSPREY
+	case MACH_GROUP_NEC_VR41XX:
+		nec_osprey_setup();
+		break;
+#endif
 #ifdef CONFIG_MIPS_EV96100
 	case MACH_GROUP_GALILEO:
 		ev96100_setup();
@@ -628,6 +776,26 @@
 		au1000_setup();
 		break;
 #endif
+#ifdef CONFIG_MIPS_PB1500
+	case MACH_GROUP_ALCHEMY:
+		au1500_setup();
+		break;
+#endif
+#ifdef CONFIG_TOSHIBA_JMR3927
+	case MACH_GROUP_TOSHIBA:
+		jmr3927_setup();
+		break;
+#endif
+#ifdef CONFIG_SIBYTE_SWARM
+	case MACH_GROUP_SIBYTE:
+		swarm_setup();
+		break;
+#endif
+#ifdef CONFIG_HP_LASERJET
+        case MACH_GROUP_HP_LJ:
+                hp_setup();
+                break;
+#endif
 	default:
 		panic("Unsupported architecture");
 	}
@@ -643,11 +811,26 @@
 #define PFN_DOWN(x)	((x) >> PAGE_SHIFT)
 #define PFN_PHYS(x)	((x) << PAGE_SHIFT)
 
+#define MAXMEM		HIGHMEM_START
+#define MAXMEM_PFN	PFN_DOWN(MAXMEM)
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8; 
+	if (tmp < (unsigned long)&_end) 
+		tmp += PAGE_SIZE;
+	initrd_header = (unsigned long *)tmp;
+	if (initrd_header[0] == 0x494E5244) {
+		initrd_start = (unsigned long)&initrd_header[2];
+		initrd_end = initrd_start + initrd_header[1];
+	}
+	start_pfn = PFN_UP(__pa((&_end)+(initrd_end - initrd_start) + PAGE_SIZE));
+#else
 	/*
 	 * Partially used pages are not usable - thus
 	 * we are rounding upwards.
 	 */
 	start_pfn = PFN_UP(__pa(&_end));
+#endif	/* CONFIG_BLK_DEV_INITRD */
 
 	/* Find the highest page frame number we have available.  */
 	max_pfn = 0;
@@ -674,9 +857,36 @@
 			}
 		}
 	}
-	
-	/* Initialize the boot-time allocator.  */
-	bootmap_size = init_bootmem(first_usable_pfn, max_pfn);
+
+	/*
+	 * Determine low and high memory ranges
+	 */
+	max_low_pfn = max_pfn;
+	if (max_low_pfn > MAXMEM_PFN) {
+		max_low_pfn = MAXMEM_PFN;
+#ifndef CONFIG_HIGHMEM
+		/* Maximum memory usable is what is directly addressable */
+		printk(KERN_WARNING "Warning only %ldMB will be used.\n",
+		       MAXMEM>>20);
+		printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
+#endif
+	}
+
+#ifdef CONFIG_HIGHMEM
+	/*
+	 * Crude, we really should make a better attempt at detecting
+	 * highstart_pfn
+	 */
+	highstart_pfn = highend_pfn = max_pfn;
+	if (max_pfn > MAXMEM_PFN) {
+		highstart_pfn = MAXMEM_PFN;
+		printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
+		       (highend_pfn - highstart_pfn) >> (20 - PAGE_SHIFT));
+	}
+#endif
+
+	/* Initialize the boot-time allocator with low memory only.  */
+	bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
 
 	/*
 	 * Register fully available low RAM pages with the bootmem allocator.
@@ -694,7 +904,7 @@
 		 * We are rounding up the start address of usable memory:
 		 */
 		curr_pfn = PFN_UP(boot_mem_map.map[i].addr);
-		if (curr_pfn >= max_pfn)
+		if (curr_pfn >= max_low_pfn)
 			continue;
 		if (curr_pfn < start_pfn)
 			curr_pfn = start_pfn;
@@ -705,8 +915,19 @@
 		last_pfn = PFN_DOWN(boot_mem_map.map[i].addr
 				    + boot_mem_map.map[i].size);
 
-		if (last_pfn > max_pfn)
-			last_pfn = max_pfn;
+		if (last_pfn > max_low_pfn)
+			last_pfn = max_low_pfn;
+
+		/*
+		 * Only register lowmem part of lowmem segment with bootmem.
+		 */
+		size = last_pfn - curr_pfn;
+		if (curr_pfn > PFN_DOWN(HIGHMEM_START))
+			continue;
+		if (curr_pfn + size - 1 > PFN_DOWN(HIGHMEM_START))
+			size = PFN_DOWN(HIGHMEM_START) - curr_pfn;
+		if (!size)
+			continue;
 
 		/*
 		 * ... finally, did all the rounding and playing
@@ -715,7 +936,7 @@
 		if (last_pfn <= curr_pfn)
 			continue;
 
-		size = last_pfn - curr_pfn;
+		/* Register lowmem ranges */
 		free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
 	}
 
@@ -725,7 +946,7 @@
 #ifdef CONFIG_BLK_DEV_INITRD
 	/* Board specific code should have set up initrd_start and initrd_end */
 	ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
-	if( __rd_start != __rd_end ) {
+	if (&__rd_start != &__rd_end) {
 		initrd_start = (unsigned long)&__rd_start;
 		initrd_end = (unsigned long)&__rd_end;
 	}
@@ -757,6 +978,7 @@
 	 */
 	for (i = 0; i < boot_mem_map.nr_map; i++) {
 		struct resource *res;
+		unsigned long addr_pfn, end_pfn;
 
 		res = alloc_bootmem(sizeof(struct resource));
 		switch (boot_mem_map.map[i].type) {
@@ -768,8 +990,16 @@
 		default:
 			res->name = "reserved";
 		}
+		addr_pfn = PFN_UP(boot_mem_map.map[i].addr);
+		end_pfn = PFN_UP(boot_mem_map.map[i].addr+boot_mem_map.map[i].size);
+		if (addr_pfn > max_low_pfn)
+			continue;
 		res->start = boot_mem_map.map[i].addr;
-		res->end = res->start + boot_mem_map.map[i].size - 1;
+		if (end_pfn < max_low_pfn) {
+			res->end = res->start + boot_mem_map.map[i].size - 1;
+		} else {
+			res->end = max_low_pfn - 1;
+		}
 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 		request_resource(&iomem_resource, res);
 
@@ -789,9 +1019,22 @@
 	write_32bit_cp0_register(CP0_CONF, cfg|CONF_HALT);
 }
 
+void r39xx_wait(void)
+{
+	unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
+	write_32bit_cp0_register(CP0_CONF, cfg|TX39_CONF_HALT);
+}
+
 void r4k_wait(void)
 {
 	__asm__(".set\tmips3\n\t"
 		"wait\n\t"
 		".set\tmips0");
 }
+
+static int __init fpu_disable(char *s)
+{
+	mips_cpu.options &= ~MIPS_CPU_FPU;
+	return 1;
+}
+__setup("nofpu", fpu_disable);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/signal.c linux/arch/mips/kernel/signal.c
--- linux.orig/arch/mips/kernel/signal.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/signal.c	2002-08-01 06:42:47.000000000 +0000
@@ -13,6 +13,7 @@
 #include <linux/smp.h>
 #include <linux/smp_lock.h>
 #include <linux/kernel.h>
+#include <linux/personality.h>
 #include <linux/signal.h>
 #include <linux/errno.h>
 #include <linux/wait.h>
@@ -21,6 +22,7 @@
 
 #include <asm/asm.h>
 #include <asm/bitops.h>
+#include <asm/cpu.h>
 #include <asm/pgalloc.h>
 #include <asm/stackframe.h>
 #include <asm/uaccess.h>
@@ -76,8 +78,7 @@
  * Atomically swap in the new signal mask, and wait for a signal.
  */
 save_static_function(sys_sigsuspend);
-static_unused int
-_sys_sigsuspend(struct pt_regs regs)
+static_unused int _sys_sigsuspend(struct pt_regs regs)
 {
 	sigset_t *uset, saveset, newset;
 
@@ -102,10 +103,8 @@
 	}
 }
 
-
 save_static_function(sys_rt_sigsuspend);
-static_unused int
-_sys_rt_sigsuspend(struct pt_regs regs)
+static_unused int _sys_rt_sigsuspend(struct pt_regs regs)
 {
 	sigset_t *unewset, saveset, newset;
         size_t sigsetsize;
@@ -136,8 +135,8 @@
 	}
 }
 
-asmlinkage int 
-sys_sigaction(int sig, const struct sigaction *act, struct sigaction *oact)
+asmlinkage int sys_sigaction(int sig, const struct sigaction *act,
+	struct sigaction *oact)
 {
 	struct k_sigaction new_ka, old_ka;
 	int ret;
@@ -177,8 +176,7 @@
 	return ret;
 }
 
-asmlinkage int
-sys_sigaltstack(struct pt_regs regs)
+asmlinkage int sys_sigaltstack(struct pt_regs regs)
 {
 	const stack_t *uss = (const stack_t *) regs.regs[4];
 	stack_t *uoss = (stack_t *) regs.regs[5];
@@ -187,8 +185,57 @@
 	return do_sigaltstack(uss, uoss, usp);
 }
 
-asmlinkage int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
+static inline int restore_thread_fp_context(struct sigcontext *sc)
+{
+	u64 *pfreg = &current->thread.fpu.soft.regs[0];
+	int err = 0;
+
+	/* 
+	 * Copy all 32 64-bit values, for two reasons.  First, the R3000 and
+	 * R4000/MIPS32 kernels use the thread FP register storage differently,
+	 * such that a full copy is essentially necessary to support both.
+	 */
+
+#define restore_fpr(i) 						\
+	do { err |= __get_user(pfreg[i], &sc->sc_fpregs[i]); } while(0)
+
+	restore_fpr( 0); restore_fpr( 1); restore_fpr( 2); restore_fpr( 3);
+	restore_fpr( 4); restore_fpr( 5); restore_fpr( 6); restore_fpr( 7);
+	restore_fpr( 8); restore_fpr( 9); restore_fpr(10); restore_fpr(11);
+	restore_fpr(12); restore_fpr(13); restore_fpr(14); restore_fpr(15);
+	restore_fpr(16); restore_fpr(17); restore_fpr(18); restore_fpr(19);
+	restore_fpr(20); restore_fpr(21); restore_fpr(22); restore_fpr(23);
+	restore_fpr(24); restore_fpr(25); restore_fpr(26); restore_fpr(27);
+	restore_fpr(28); restore_fpr(29); restore_fpr(30); restore_fpr(31);
+
+	err |= __get_user(current->thread.fpu.soft.sr, &sc->sc_fpc_csr);
+
+	return err;
+}
+
+static inline int save_thread_fp_context(struct sigcontext *sc)
+{
+	u64 *pfreg = &current->thread.fpu.soft.regs[0];
+	int err = 0;
+
+#define save_fpr(i) 							\
+	do { err |= __put_user(pfreg[i], &sc->sc_fpregs[i]); } while(0)
+
+	save_fpr( 0); save_fpr( 1); save_fpr( 2); save_fpr( 3);
+	save_fpr( 4); save_fpr( 5); save_fpr( 6); save_fpr( 7);
+	save_fpr( 8); save_fpr( 9); save_fpr(10); save_fpr(11);
+	save_fpr(12); save_fpr(13); save_fpr(14); save_fpr(15);
+	save_fpr(16); save_fpr(17); save_fpr(18); save_fpr(19);
+	save_fpr(20); save_fpr(21); save_fpr(22); save_fpr(23);
+	save_fpr(24); save_fpr(25); save_fpr(26); save_fpr(27);
+	save_fpr(28); save_fpr(29); save_fpr(30); save_fpr(31);
+
+	err |= __put_user(current->thread.fpu.soft.sr, &sc->sc_fpc_csr);
+
+	return err;
+}
+
+static int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
 {
 	int owned_fp;
 	int err = 0;
@@ -204,7 +251,7 @@
 #define restore_gp_reg(i) do {						\
 	err |= __get_user(reg, &sc->sc_regs[i]);			\
 	regs->regs[i] = reg;						\
-} while(0);
+} while(0)
 	restore_gp_reg( 1); restore_gp_reg( 2); restore_gp_reg( 3);
 	restore_gp_reg( 4); restore_gp_reg( 5); restore_gp_reg( 6);
 	restore_gp_reg( 7); restore_gp_reg( 8); restore_gp_reg( 9);
@@ -219,11 +266,24 @@
 #undef restore_gp_reg
 
 	err |= __get_user(owned_fp, &sc->sc_ownedfp);
+	err |= __get_user(current->used_math, &sc->sc_used_math);
+
 	if (owned_fp) {
 		err |= restore_fp_context(sc);
-		last_task_used_math = current;
+		goto out;
 	}
 
+	if (current == last_task_used_math) {
+		/* Signal handler acquired FPU - give it back */
+		last_task_used_math = NULL;
+		regs->cp0_status &= ~ST0_CU1;
+	}
+	if (current->used_math) {
+		/* Undo possible contamination of thread state */
+		err |= restore_thread_fp_context(sc);
+	}
+
+out:
 	return err;
 }
 
@@ -241,8 +301,7 @@
 	struct ucontext rs_uc;
 };
 
-asmlinkage void
-sys_sigreturn(struct pt_regs regs)
+asmlinkage void sys_sigreturn(struct pt_regs regs)
 {
 	struct sigframe *frame;
 	sigset_t blocked;
@@ -278,8 +337,7 @@
 	force_sig(SIGSEGV, current);
 }
 
-asmlinkage void
-sys_rt_sigreturn(struct pt_regs regs)
+asmlinkage void sys_rt_sigreturn(struct pt_regs regs)
 {
 	struct rt_sigframe *frame;
 	sigset_t set;
@@ -320,21 +378,21 @@
 	force_sig(SIGSEGV, current);
 }
 
-static int inline
-setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
+static int inline setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
 {
 	int owned_fp;
 	int err = 0;
 	u64 reg;
 
-	err |= __put_user(regs->cp0_epc, &sc->sc_pc);
+	reg = regs->cp0_epc; err |= __put_user(reg, &sc->sc_pc);
 	err |= __put_user(regs->cp0_status, &sc->sc_status);
 
 #define save_gp_reg(i) {						\
 	reg = regs->regs[i];						\
 	err |= __put_user(reg, &sc->sc_regs[i]);			\
 } while(0)
-	__put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2);
+	reg = 0; err |= __put_user(reg, &sc->sc_regs[0]);
+	save_gp_reg(1); save_gp_reg(2);
 	save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6);
 	save_gp_reg(7); save_gp_reg(8); save_gp_reg(9); save_gp_reg(10);
 	save_gp_reg(11); save_gp_reg(12); save_gp_reg(13); save_gp_reg(14);
@@ -345,36 +403,53 @@
 	save_gp_reg(31);
 #undef save_gp_reg
 
-	err |= __put_user(regs->hi, &sc->sc_mdhi);
-	err |= __put_user(regs->lo, &sc->sc_mdlo);
+	reg = regs->hi; err |= __put_user(reg, &sc->sc_mdhi);
+	reg = regs->lo; err |= __put_user(reg, &sc->sc_mdlo);
 	err |= __put_user(regs->cp0_cause, &sc->sc_cause);
 	err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr);
 
 	owned_fp = (current == last_task_used_math);
 	err |= __put_user(owned_fp, &sc->sc_ownedfp);
+	err |= __put_user(current->used_math, &sc->sc_used_math);
 
-	if (current->used_math) {	/* fp is active.  */
-		set_cp0_status(ST0_CU1);
+	if (!current->used_math)
+		goto out;
+
+	/* There exists FP thread state that may be trashed by signal */
+	if (owned_fp) {	
+		/* fp is active.  Save context from FPU */
 		err |= save_fp_context(sc);
-		last_task_used_math = NULL;
-		regs->cp0_status &= ~ST0_CU1;
-		current->used_math = 0;
+		goto out;
 	}
 
+	/* 
+	 * Someone else has FPU. 
+	 * Copy Thread context into signal context 
+	 */
+	err |= save_thread_fp_context(sc);
+
+out:
 	return err;
 }
 
 /*
  * Determine which stack to use..
  */
-static inline void *
-get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
+static inline void * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
+	size_t frame_size)
 {
 	unsigned long sp;
 
 	/* Default to using normal stack */
 	sp = regs->regs[29];
 
+	/* 
+ 	 * FPU emulator may have it's own trampoline active just
+ 	 * above the user stack, 16-bytes before the next lowest
+ 	 * 16 byte boundary.  Try to avoid trashing it.
+ 	 */
+ 	sp -= 32;
+
 	/* This is the X/Open sanctioned signal stack switching.  */
 	if ((ka->sa.sa_flags & SA_ONSTACK) && ! on_sig_stack(sp))
                 sp = current->sas_ss_sp + current->sas_ss_size;
@@ -382,9 +457,8 @@
 	return (void *)((sp - frame_size) & ALMASK);
 }
 
-static void inline
-setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
-            int signr, sigset_t *set)
+static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
+	int signr, sigset_t *set)
 {
 	struct sigframe *frame;
 	int err = 0;
@@ -445,9 +519,8 @@
 	force_sig(SIGSEGV, current);
 }
 
-static void inline
-setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
-               int signr, sigset_t *set, siginfo_t *info)
+static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
+	int signr, sigset_t *set, siginfo_t *info)
 {
 	struct rt_sigframe *frame;
 	int err = 0;
@@ -521,8 +594,7 @@
 	force_sig(SIGSEGV, current);
 }
 
-static inline void
-handle_signal(unsigned long sig, struct k_sigaction *ka,
+static inline void handle_signal(unsigned long sig, struct k_sigaction *ka,
 	siginfo_t *info, sigset_t *oldset, struct pt_regs * regs)
 {
 	if (ka->sa.sa_flags & SA_SIGINFO)
@@ -541,8 +613,7 @@
 	}
 }
 
-static inline void
-syscall_restart(struct pt_regs *regs, struct k_sigaction *ka)
+static inline void syscall_restart(struct pt_regs *regs, struct k_sigaction *ka)
 {
 	switch(regs->regs[0]) {
 	case ERESTARTNOHAND:
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/smp.c linux/arch/mips/kernel/smp.c
--- linux.orig/arch/mips/kernel/smp.c	2001-12-21 17:41:53.000000000 +0000
+++ linux/arch/mips/kernel/smp.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,11 +1,4 @@
 /*
- *
- *  arch/mips/kernel/smp.c
- *
- *  Copyright (C) 2000 Sibyte
- * 
- *  Written by Justin Carlson (carlson@sibyte.com)
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -20,20 +13,24 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  *
+ * Copyright (C) 2000, 2001 Kanoj Sarcar
+ * Copyright (C) 2000, 2001 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2000, 2001 Broadcom Corporation
  */ 
-
-
-#include <linux/config.h>
+#include <linux/cache.h>
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/threads.h>
 #include <linux/time.h>
+#include <linux/module.h>
 #include <linux/timex.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
-#include <linux/cache.h>
+#include <linux/mm.h>
 
 #include <asm/atomic.h>
+#include <asm/cpu.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/hardirq.h>
@@ -42,38 +39,29 @@
 #include <asm/delay.h>
 #include <asm/smp.h>
 
-/*
- * This was written with the BRCM12500 MP SOC in mind, but tries to
- * be generic.  It's modelled on the mips64 smp.c code, which is
- * derived from Sparc, I'm guessing, which is derived from...
- * 
- * It's probably horribly designed for very large ccNUMA systems
- * as it doesn't take any node clustering into account.  
-*/
-
-
 /* Ze Big Kernel Lock! */
 spinlock_t kernel_flag __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
-int smp_threads_ready;  /* Not used */
-int smp_num_cpus;    
-int global_irq_holder = NO_PROC_ID;
-spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED;
-struct mips_cpuinfo cpu_data[NR_CPUS];
-
-struct smp_fn_call_struct smp_fn_call = 
-{ SPIN_LOCK_UNLOCKED, ATOMIC_INIT(0), NULL, NULL};
+int smp_threads_ready;
+atomic_t smp_commenced = ATOMIC_INIT(0);
+int smp_num_cpus = 1;			/* Number that came online.  */
+cpumask_t cpu_online_map;		/* Bitmask of currently online CPUs */
+int __cpu_number_map[NR_CPUS];
+int __cpu_logical_map[NR_CPUS];
+struct cpuinfo_mips cpu_data[NR_CPUS];
+void (*volatile smp_cpu0_finalize)(void);
 
-static atomic_t cpus_booted = ATOMIC_INIT(0);
+// static atomic_t cpus_booted = ATOMIC_INIT(0);
+atomic_t cpus_booted = ATOMIC_INIT(0);
 
 
 /* These are defined by the board-specific code. */
 
-/* Cause the function described by smp_fn_call 
-   to be executed on the passed cpu.  When the function
-   has finished, increment the finished field of
-   smp_fn_call. */
-
-void core_call_function(int cpu);
+/*
+ * Cause the function described by call_data to be executed on the passed
+ * cpu.  When the function has finished, increment the finished field of
+ * call_data.
+ */
+void core_send_ipi(int cpu, unsigned int action);
 
 /*
  * Clear all undefined state in the cpu, set up sp and gp to the passed
@@ -85,108 +73,54 @@
  *  After we've done initial boot, this function is called to allow the
  *  board code to clean up state, if needed 
  */
-
 void prom_init_secondary(void);
 
-
-void cpu_idle(void);
-
-/* Do whatever setup needs to be done for SMP at the board level.  Return
-   the number of cpus in the system, including this one */
+/*
+ * Do whatever setup needs to be done for SMP at the board level.  Return
+ * the number of cpus in the system, including this one
+ */
 int prom_setup_smp(void);
 
-int start_secondary(void *unused)
+/*
+ * Hook for doing final board-specific setup after the generic smp setup
+ * is done
+ */
+asmlinkage void start_secondary(void)
 {
+	unsigned int cpu = smp_processor_id();
+
 	prom_init_secondary();
-	write_32bit_cp0_register(CP0_CONTEXT, smp_processor_id()<<23);
-	current_pgd[smp_processor_id()] = init_mm.pgd;
+	per_cpu_trap_init();
+
+	/*
+	 * XXX parity protection should be folded in here when it's converted
+	 * to an option instead of something based on .cputype
+	 */
+
+	pgd_current[cpu] = init_mm.pgd;
+	cpu_data[cpu].udelay_val = loops_per_jiffy;
+	prom_smp_finish();
 	printk("Slave cpu booted successfully\n");
+	CPUMASK_SETB(cpu_online_map, cpu);
 	atomic_inc(&cpus_booted);
+	while (!atomic_read(&smp_commenced));
 	cpu_idle();
-	return 0;
-}
-
-void __init smp_boot_cpus(void)
-{
-	int i;
-
-	smp_num_cpus = prom_setup_smp();
-	init_new_context(current, &init_mm);
-	current->processor = 0;
-	atomic_set(&cpus_booted, 1);  /* Master CPU is already booted... */
-	init_idle();
-	for (i = 1; i < smp_num_cpus; i++) {
-		struct task_struct *p;
-		struct pt_regs regs;
-		printk("Starting CPU %d... ", i);
-
-		/* Spawn a new process normally.  Grab a pointer to
-		   its task struct so we can mess with it */
-		do_fork(CLONE_VM|CLONE_PID, 0, &regs, 0);
-		p = init_task.prev_task;
-
-		/* Schedule the first task manually */
-		p->processor = i;
-		p->cpus_runnable = 1 << i; /* we schedule the first task manually */
-
-		/* Attach to the address space of init_task. */
-		atomic_inc(&init_mm.mm_count);
-		p->active_mm = &init_mm;
-		init_tasks[i] = p;
-
-		del_from_runqueue(p);
-		unhash_process(p);
-
-		prom_boot_secondary(i,
-				    (unsigned long)p + KERNEL_STACK_SIZE - 32,
-				    (unsigned long)p);
-
-#if 0
-
-		/* This is copied from the ip-27 code in the mips64 tree */
-
-		struct task_struct *p;
-
-		/*
-		 * The following code is purely to make sure
-		 * Linux can schedule processes on this slave.
-		 */
-		kernel_thread(0, NULL, CLONE_PID);
-		p = init_task.prev_task;
-		sprintf(p->comm, "%s%d", "Idle", i);
-		init_tasks[i] = p;
-		p->processor = i;
-		p->cpus_runnable = 1 << i; /* we schedule the first task manually *
-		del_from_runqueue(p);
-		unhash_process(p);
-		/* Attach to the address space of init_task. */
-		atomic_inc(&init_mm.mm_count);
-		p->active_mm = &init_mm;
-		prom_boot_secondary(i, 
-				    (unsigned long)p + KERNEL_STACK_SIZE - 32,
-				    (unsigned long)p);
-#endif
-	}
-
-	/* Wait for everyone to come up */
-	while (atomic_read(&cpus_booted) != smp_num_cpus);
 }
 
 void __init smp_commence(void)
 {
-	/* Not sure what to do here yet */
+	wmb();
+	atomic_set(&smp_commenced, 1);
 }
 
-static void reschedule_this_cpu(void *dummy)
+void smp_send_reschedule(int cpu)
 {
-	current->need_resched = 1;
+	core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF);
 }
 
-void FASTCALL(smp_send_reschedule(int cpu))
-{
-	smp_call_function(reschedule_this_cpu, NULL, 0, 0);
-}
+static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
 
+struct call_data_struct *call_data;
 
 /*
  * The caller of this wants the passed function to run on every cpu.  If wait
@@ -196,43 +130,76 @@
 int smp_call_function (void (*func) (void *info), void *info, int retry, 
 								int wait)
 {
-	int cpus = smp_num_cpus - 1;
-	int i;
+	struct call_data_struct data;
+	int i, cpus = smp_num_cpus - 1;
+	int cpu = smp_processor_id();
 
-	if (smp_num_cpus < 2) {
+	if (!cpus)
 		return 0;
-	}
 
-	spin_lock_bh(&smp_fn_call.lock);
+	data.func = func;
+	data.info = info;
+	atomic_set(&data.started, 0);
+	data.wait = wait;
+	if (wait)
+		atomic_set(&data.finished, 0);
+
+	spin_lock(&call_lock);
+	call_data = &data;
+
+	/* Send a message to all other CPUs and wait for them to respond */
+	for (i = 0; i < smp_num_cpus; i++)
+		if (i != cpu)
+			core_send_ipi(i, SMP_CALL_FUNCTION);
+
+	/* Wait for response */
+	/* FIXME: lock-up detection, backtrace on lock-up */
+	while (atomic_read(&data.started) != cpus)
+		barrier();
+
+	if (wait)
+		while (atomic_read(&data.finished) != cpus)
+			barrier();
+	spin_unlock(&call_lock);
 
-	atomic_set(&smp_fn_call.finished, 0);
-	smp_fn_call.fn = func;
-	smp_fn_call.data = info;
-
-	for (i = 0; i < smp_num_cpus; i++) {
-		if (i != smp_processor_id()) {
-			/* Call the board specific routine */
-			core_call_function(i);
-		}
-	}
-
-	if (wait) {
-		while(atomic_read(&smp_fn_call.finished) != cpus) {}
-	}
-
-	spin_unlock_bh(&smp_fn_call.lock);
 	return 0;
 }
 
-void synchronize_irq(void)
+void smp_call_function_interrupt(void)
 {
-	panic("synchronize_irq");
+	void (*func) (void *info) = call_data->func;
+	void *info = call_data->info;
+	int wait = call_data->wait;
+	int cpu = smp_processor_id();
+
+	irq_enter(cpu, 0);	/* XXX choose an irq number? */
+	/*
+	 * Notify initiating CPU that I've grabbed the data
+	 * and am about to execute the function
+	 */
+	mb();
+	atomic_inc(&call_data->started);
+
+	/*
+	 * At this point the info structure may be out of scope unless wait==1
+	 */
+	(*func)(info);
+	if (wait) {
+		mb();
+		atomic_inc(&call_data->finished);
+	}
+	irq_exit(cpu, 0);	/* XXX choose an irq number? */
 }
 
 static void stop_this_cpu(void *dummy)
 {
-	printk("Cpu stopping\n");
-	for (;;);
+	int cpu = smp_processor_id();
+	if (cpu)
+		for (;;);		/* XXX Use halt like i386 */
+
+	/* XXXKW this isn't quite there yet */
+	while (!smp_cpu0_finalize) ;
+	smp_cpu0_finalize();
 }
 
 void smp_send_stop(void)
@@ -247,157 +214,110 @@
 	return 0;
 }
 
+static void flush_tlb_all_ipi(void *info)
+{
+	local_flush_tlb_all();
+}
 
-/*
- * Most of this code is take from the mips64 tree (ip27-irq.c).  It's virtually
- * identical to the i386 implentation in arh/i386/irq.c, with translations for
- * the interrupt enable bit
- */
-
-#define MAXCOUNT 		100000000
-#define SYNC_OTHER_CORES(x)	udelay(x+1)
+void flush_tlb_all(void)
+{
+	smp_call_function(flush_tlb_all_ipi, 0, 1, 1);
+	local_flush_tlb_all();
+}
 
-static inline void wait_on_irq(int cpu)
+static void flush_tlb_mm_ipi(void *mm)
 {
-	int count = MAXCOUNT;
+	local_flush_tlb_mm((struct mm_struct *)mm);
+}
 
-	for (;;) {
+/*
+ * The following tlb flush calls are invoked when old translations are 
+ * being torn down, or pte attributes are changing. For single threaded
+ * address spaces, a new context is obtained on the current cpu, and tlb
+ * context on other cpus are invalidated to force a new context allocation
+ * at switch_mm time, should the mm ever be used on other cpus. For 
+ * multithreaded address spaces, intercpu interrupts have to be sent.
+ * Another case where intercpu interrupts are required is when the target
+ * mm might be active on another cpu (eg debuggers doing the flushes on
+ * behalf of debugees, kswapd stealing pages from another process etc).
+ * Kanoj 07/00.
+ */
 
-		/*
-		 * Wait until all interrupts are gone. Wait
-		 * for bottom half handlers unless we're
-		 * already executing in one..
-		 */
-		if (!irqs_running())
-			if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock))
-				break;
-
-		/* Duh, we have to loop. Release the lock to avoid deadlocks */
-		spin_unlock(&global_irq_lock);
-
-		for (;;) {
-			if (!--count) {
-				printk("Count spun out.  Huh?\n");
-				count = ~0;
-			}
-			__sti();
-			SYNC_OTHER_CORES(cpu);
-			__cli();
-			if (irqs_running())
-				continue;
-			if (spin_is_locked(&global_irq_lock))
-				continue;
-			if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock))
-				continue;
-			if (spin_trylock(&global_irq_lock))
-				break;
-		}
+void flush_tlb_mm(struct mm_struct *mm)
+{
+	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
+		smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1);
+	} else {
+		int i;
+		for (i = 0; i < smp_num_cpus; i++)
+			if (smp_processor_id() != i)
+				CPU_CONTEXT(i, mm) = 0;
 	}
+	local_flush_tlb_mm(mm);
 }
 
+struct flush_tlb_data {
+	struct mm_struct *mm;
+	struct vm_area_struct *vma;
+	unsigned long addr1;
+	unsigned long addr2;
+};
 
-static inline void get_irqlock(int cpu)
+static void flush_tlb_range_ipi(void *info)
 {
-	if (!spin_trylock(&global_irq_lock)) {
-		/* do we already hold the lock? */
-		if ((unsigned char) cpu == global_irq_holder)
-			return;
-		/* Uhhuh.. Somebody else got it. Wait.. */
-		spin_lock(&global_irq_lock);
-	}
-	/*
-	 * We also to make sure that nobody else is running
-	 * in an interrupt context.
-	 */
-	wait_on_irq(cpu);
+	struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
 
-	/*
-	 * Ok, finally..
-	 */
-	global_irq_holder = cpu;
+	local_flush_tlb_range(fd->mm, fd->addr1, fd->addr2);
 }
 
-
-/*
- * A global "cli()" while in an interrupt context
- * turns into just a local cli(). Interrupts
- * should use spinlocks for the (very unlikely)
- * case that they ever want to protect against
- * each other.
- *
- * If we already have local interrupts disabled,
- * this will not turn a local disable into a
- * global one (problems with spinlocks: this makes
- * save_flags+cli+sti usable inside a spinlock).
- */
-void __global_cli(void)
+void flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end)
 {
-	unsigned int flags;
+	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
+		struct flush_tlb_data fd;
 
-	__save_flags(flags);
-	if (flags & ST0_IE) {
-		int cpu = smp_processor_id();
-		__cli();
-		if (!local_irq_count(cpu))
-			get_irqlock(cpu);
+		fd.mm = mm;
+		fd.addr1 = start;
+		fd.addr2 = end;
+		smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1);
+	} else {
+		int i;
+		for (i = 0; i < smp_num_cpus; i++)
+			if (smp_processor_id() != i)
+				CPU_CONTEXT(i, mm) = 0;
 	}
+	local_flush_tlb_range(mm, start, end);
 }
 
-void __global_sti(void)
+static void flush_tlb_page_ipi(void *info)
 {
-	int cpu = smp_processor_id();
+	struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
 
-	if (!local_irq_count(cpu))
-		release_irqlock(cpu);
-	__sti();
+	local_flush_tlb_page(fd->vma, fd->addr1);
 }
 
-/*
- * SMP flags value to restore to:
- * 0 - global cli
- * 1 - global sti
- * 2 - local cli
- * 3 - local sti
- */
-unsigned long __global_save_flags(void)
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
-	int retval;
-	int local_enabled;
-	unsigned long flags;
-	int cpu = smp_processor_id();
+	if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
+		struct flush_tlb_data fd;
 
-	__save_flags(flags);
-	local_enabled = (flags & ST0_IE);
-	/* default to local */
-	retval = 2 + local_enabled;
-
-	/* check for global flags if we're not in an interrupt */
-	if (!local_irq_count(cpu)) {
-		if (local_enabled)
-			retval = 1;
-		if (global_irq_holder == cpu)
-			retval = 0;
+		fd.vma = vma;
+		fd.addr1 = page;
+		smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1);
+	} else {
+		int i;
+		for (i = 0; i < smp_num_cpus; i++)
+			if (smp_processor_id() != i)
+				CPU_CONTEXT(i, vma->vm_mm) = 0;
 	}
-
-	return retval;
+	local_flush_tlb_page(vma, page);
 }
 
-void __global_restore_flags(unsigned long flags)
-{
-	switch (flags) {
-		case 0:
-			__global_cli();
-			break;
-		case 1:
-			__global_sti();
-			break;
-		case 2:
-			__cli();
-			break;
-		case 3:
-			__sti();
-			break;
-		default:
-			printk("global_restore_flags: %08lx\n", flags);
-	}
-}
+EXPORT_SYMBOL(smp_num_cpus);
+EXPORT_SYMBOL(flush_tlb_page);
+EXPORT_SYMBOL(cpu_data);
+EXPORT_SYMBOL(synchronize_irq);
+EXPORT_SYMBOL(kernel_flag);
+EXPORT_SYMBOL(__global_sti);
+EXPORT_SYMBOL(__global_cli);
+EXPORT_SYMBOL(__global_save_flags);
+EXPORT_SYMBOL(__global_restore_flags);
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/syscall.c linux/arch/mips/kernel/syscall.c
--- linux.orig/arch/mips/kernel/syscall.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/kernel/syscall.c	2002-08-01 06:42:36.000000000 +0000
@@ -14,6 +14,7 @@
 #undef CONF_DEBUG_IRIX
 
 #include <linux/config.h>
+#include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
@@ -28,7 +29,7 @@
 #include <asm/offset.h>
 #include <asm/ptrace.h>
 #include <asm/signal.h>
-#include <asm/stackframe.h>
+#include <asm/shmparam.h>
 #include <asm/uaccess.h>
 
 extern asmlinkage void syscall_trace(void);
@@ -54,6 +55,59 @@
 	return res;
 }
 
+#define COLOUR_ALIGN(addr,pgoff)		\
+	((((addr)+SHMLBA-1)&~(SHMLBA-1)) +	\
+	 (((pgoff)<<PAGE_SHIFT) & (SHMLBA-1)))
+
+unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
+	unsigned long len, unsigned long pgoff, unsigned long flags)
+{
+	struct vm_area_struct * vmm;
+	int do_color_align;
+
+	if (flags & MAP_FIXED) {
+		/*
+		 * We do not accept a shared mapping if it would violate
+		 * cache aliasing constraints.
+		 */
+		if ((flags & MAP_SHARED) && (addr & (SHMLBA - 1)))
+			return -EINVAL;
+		return addr;
+	}
+
+	if (len > TASK_SIZE)
+		return -ENOMEM;
+	do_color_align = 0;
+	if (filp || (flags & MAP_SHARED))
+		do_color_align = 1;
+	if (addr) {
+		if (do_color_align)
+			addr = COLOUR_ALIGN(addr, pgoff);
+		else
+			addr = PAGE_ALIGN(addr);
+		vmm = find_vma(current->mm, addr);
+		if (TASK_SIZE - len >= addr &&
+		    (!vmm || addr + len <= vmm->vm_start))
+			return addr;
+	}
+	addr = TASK_UNMAPPED_BASE;
+	if (do_color_align)
+		addr = COLOUR_ALIGN(addr, pgoff);
+	else
+		addr = PAGE_ALIGN(addr);
+
+	for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
+		/* At this point:  (!vmm || addr < vmm->vm_end). */
+		if (TASK_SIZE - len < addr)
+			return -ENOMEM;
+		if (!vmm || addr + len <= vmm->vm_start)
+			return addr;
+		addr = vmm->vm_end;
+		if (do_color_align)
+			addr = COLOUR_ALIGN(addr, pgoff);
+	}
+}
+
 /* common code for old and new mmaps */
 static inline long
 do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
@@ -82,7 +136,16 @@
 asmlinkage unsigned long old_mmap(unsigned long addr, size_t len, int prot,
                                   int flags, int fd, off_t offset)
 {
-	return do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+	int result;
+
+	result = -EINVAL;
+	if (offset & ~PAGE_MASK)
+		goto out;
+
+	result = do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+
+out:
+	return result;
 }
 
 asmlinkage long
@@ -175,76 +238,6 @@
 }
 
 /*
- * Do the indirect syscall syscall.
- * Don't care about kernel locking; the actual syscall will do it.
- *
- * XXX This is borken.
- */
-asmlinkage int sys_syscall(struct pt_regs regs)
-{
-	syscall_t syscall;
-	unsigned long syscallnr = regs.regs[4];
-	unsigned long a0, a1, a2, a3, a4, a5, a6;
-	int nargs, errno;
-
-	if (syscallnr > __NR_Linux + __NR_Linux_syscalls)
-		return -ENOSYS;
-
-	syscall = sys_call_table[syscallnr];
-	nargs = sys_narg_table[syscallnr];
-	/*
-	 * Prevent stack overflow by recursive
-	 * syscall(__NR_syscall, __NR_syscall,...);
-	 */
-	if (syscall == (syscall_t) sys_syscall) {
-		return -EINVAL;
-	}
-
-	if (syscall == NULL) {
-		return -ENOSYS;
-	}
-
-	if(nargs > 3) {
-		unsigned long usp = regs.regs[29];
-		unsigned long *sp = (unsigned long *) usp;
-		if(usp & 3) {
-			printk("unaligned usp -EFAULT\n");
-			force_sig(SIGSEGV, current);
-			return -EFAULT;
-		}
-		errno = verify_area(VERIFY_READ, (void *) (usp + 16),
-		                    (nargs - 3) * sizeof(unsigned long));
-		if(errno) {
-			return -EFAULT;
-		}
-		switch(nargs) {
-		case 7:
-			a3 = sp[4]; a4 = sp[5]; a5 = sp[6]; a6 = sp[7];
-			break;
-		case 6:
-			a3 = sp[4]; a4 = sp[5]; a5 = sp[6]; a6 = 0;
-			break;
-		case 5:
-			a3 = sp[4]; a4 = sp[5]; a5 = a6 = 0;
-			break;
-		case 4:
-			a3 = sp[4]; a4 = a5 = a6 = 0;
-			break;
-
-		default:
-			a3 = a4 = a5 = a6 = 0;
-			break;
-		}
-	} else {
-		a3 = a4 = a5 = a6 = 0;
-	}
-	a0 = regs.regs[5]; a1 = regs.regs[6]; a2 = regs.regs[7];
-	if(nargs == 0)
-		a0 = (unsigned long) &regs;
-	return syscall((void *)a0, a1, a2, a3, a4, a5, a6);
-}
-
-/*
  * If we ever come here the user sp is bad.  Zap the process right away.
  * Due to the bad stack signaling wouldn't work.
  * XXX kernel locking???
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/syscalls.h linux/arch/mips/kernel/syscalls.h
--- linux.orig/arch/mips/kernel/syscalls.h	2001-10-08 17:39:18.000000000 +0000
+++ linux/arch/mips/kernel/syscalls.h	2002-08-01 06:42:30.000000000 +0000
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001, 2002 by Ralf Baechle
  */
 
 /*
@@ -20,7 +20,7 @@
 SYS(sys_read, 3)
 SYS(sys_write, 3)
 SYS(sys_open, 3)				/* 4005 */
-SYS(sys_close, 3)
+SYS(sys_close, 1)
 SYS(sys_waitpid, 3)
 SYS(sys_creat, 2)
 SYS(sys_link, 2)
@@ -235,3 +235,23 @@
 SYS(sys_madvise, 3)
 SYS(sys_getdents64, 3)
 SYS(sys_fcntl64, 3)				/* 4220 */
+SYS(sys_ni_syscall, 0)
+SYS(sys_gettid, 0)
+SYS(sys_readahead, 5)
+SYS(sys_ni_syscall, 0)				/* reserved for setxattr */
+SYS(sys_ni_syscall, 0)				/* 4225 res. for lsetxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for fsetxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for getxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for lgetxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for fgetxattr */
+SYS(sys_ni_syscall, 0)				/* 4230 res. for listxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for llistxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for flistxattr */
+SYS(sys_ni_syscall, 0)				/* reserved for removexattr */
+SYS(sys_ni_syscall, 0)				/* reserved for lremovexattr */
+SYS(sys_ni_syscall, 0)				/* 4235 res. for fremovexattr */
+SYS(sys_tkill, 2)
+SYS(sys_ni_syscall, 0)				/* res. for sendfile64 */
+SYS(sys_ni_syscall, 0)				/* res. for futex */
+SYS(sys_ni_syscall, 0)				/* res. for sched_setaffinity */
+SYS(sys_ni_syscall, 0)				/* 4240 res. for sched_getaffinity */
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/sysirix.c linux/arch/mips/kernel/sysirix.c
--- linux.orig/arch/mips/kernel/sysirix.c	2001-08-12 22:05:26.000000000 +0000
+++ linux/arch/mips/kernel/sysirix.c	2002-08-01 06:42:40.000000000 +0000
@@ -1876,7 +1876,8 @@
 	return 0;
 }
 
-asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, unsigned int count, int *eob)
+asmlinkage int irix_ngetdents(unsigned int fd, void * dirent,
+	unsigned int count, int *eob)
 {
 	struct file *file;
 	struct irix_dirent32 *lastdirent;
@@ -1900,6 +1901,7 @@
 	error = vfs_readdir(file, irix_filldir32, &buf);
 	if (error < 0)
 		goto out_putf;
+
 	error = buf.error;
 	lastdirent = buf.previous;
 	if (lastdirent) {
@@ -1908,11 +1910,10 @@
 	}
 
 	if (put_user(0, eob) < 0) {
-		error = EFAULT;
+		error = -EFAULT;
 		goto out_putf;
 	}
 
-
 #ifdef DEBUG_GETDENTS
 	printk("eob=%d returning %d\n", *eob, count - buf.count);
 #endif
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/sysmips.c linux/arch/mips/kernel/sysmips.c
--- linux.orig/arch/mips/kernel/sysmips.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/kernel/sysmips.c	2002-08-01 06:42:36.000000000 +0000
@@ -1,13 +1,11 @@
 /*
- * MIPS specific syscalls
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995, 1996, 1997, 2000 by Ralf Baechle
+ * Copyright (C) 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
  */
-#include <linux/config.h>
 #include <linux/errno.h>
 #include <linux/linkage.h>
 #include <linux/mm.h>
@@ -48,11 +46,10 @@
 }
 
 asmlinkage int
-sys_sysmips(int cmd, int arg1, int arg2, int arg3)
+_sys_sysmips(int cmd, int arg1, int arg2, int arg3)
 {
-	int	*p;
 	char	*name;
-	int	tmp, len, retval, errno;
+	int	tmp, len, retval;
 
 	switch(cmd) {
 	case SETNAME: {
@@ -74,55 +71,10 @@
 		return 0;
 	}
 
-	case MIPS_ATOMIC_SET: {
-#ifdef CONFIG_CPU_HAS_LLSC
-		unsigned int tmp;
-
-		p = (int *) arg1;
-		errno = verify_area(VERIFY_WRITE, p, sizeof(*p));
-		if (errno)
-			return errno;
-		errno = 0;
-
-		__asm__(".set\tpush\t\t\t# sysmips(MIPS_ATOMIC, ...)\n\t"
-			".set\tmips2\n\t"
-			".set\tnoat\n\t"
-			"1:\tll\t%0, %4\n\t"
-			"move\t$1, %3\n\t"
-			"2:\tsc\t$1, %1\n\t"
-			"beqz\t$1, 1b\n\t"
-			".set\tpop\n\t"
-			".section\t.fixup,\"ax\"\n"
-			"3:\tli\t%2, 1\t\t\t# error\n\t"
-			".previous\n\t"
-			".section\t__ex_table,\"a\"\n\t"
-			".word\t1b, 3b\n\t"
-			".word\t2b, 3b\n\t"
-			".previous\n\t"
-			: "=&r" (tmp), "=o" (* (u32 *) p), "=r" (errno)
-			: "r" (arg2), "o" (* (u32 *) p), "2" (errno)
-			: "$1");
-
-		if (errno)
-			return -EFAULT;
-
-		/* We're skipping error handling etc.  */
-		if (current->ptrace & PT_TRACESYS)
-			syscall_trace();
-
-		((struct pt_regs *)&cmd)->regs[2] = tmp;
-		((struct pt_regs *)&cmd)->regs[7] = 0;
-
-		__asm__ __volatile__(
-			"move\t$29, %0\n\t"
-			"j\to32_ret_from_sys_call"
-			: /* No outputs */
-			: "r" (&cmd));
-		/* Unreached */
-#else
-	printk("sys_sysmips(MIPS_ATOMIC_SET, ...) not ready for !CONFIG_CPU_HAS_LLSC\n");
-#endif
-	}
+	case MIPS_ATOMIC_SET:
+		printk(KERN_CRIT "How did I get here?\n");
+		retval = -EINVAL;
+		goto out;
 
 	case MIPS_FIXADE:
 		tmp = current->thread.mflags & ~3;
@@ -131,7 +83,7 @@
 		goto out;
 
 	case FLUSH_CACHE:
-		flush_cache_all();
+		__flush_cache_all();
 		retval = 0;
 		goto out;
 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/time.c linux/arch/mips/kernel/time.c
--- linux.orig/arch/mips/kernel/time.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/time.c	2002-08-01 06:42:42.000000000 +0000
@@ -30,7 +30,7 @@
 
 /* This is for machines which generate the exact clock. */
 #define USECS_PER_JIFFY (1000000/HZ)
-#define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff)
+#define USECS_PER_JIFFY_FRAC ((u32)((1000000ULL << 32) / HZ))
 
 /*
  * forward reference
@@ -39,6 +39,11 @@
 extern volatile unsigned long wall_jiffies;
 
 /*
+ * whether we emulate local_timer_interrupts for SMP machines.
+ */
+int emulate_local_timer_interrupt;
+
+/*
  * By default we provide the null RTC ops
  */
 static unsigned long null_rtc_get_time(void)
@@ -255,8 +260,7 @@
 	        :"r" (timerhi),
 	         "m" (timerlo),
 	         "r" (tmp),
-	         "r" (USECS_PER_JIFFY)
-	        :"$1");
+	         "r" (USECS_PER_JIFFY));
 	        cached_quotient = quotient;
 	}
 
@@ -284,6 +288,42 @@
 
 
 /*
+ * local_timer_interrupt() does profiling and process accounting
+ * on a per-CPU basis.  
+ *
+ * In UP mode, it is invoked from the (global) timer_interrupt.  
+ *
+ * In SMP mode, it might invoked by per-CPU timer interrupt, or
+ * a broadcasted inter-processor interrupt which itself is triggered
+ * by the global timer interrupt.
+ */
+void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	if (!user_mode(regs)) {
+		if (prof_buffer && current->pid) {
+			extern int _stext;
+			unsigned long pc = regs->cp0_epc;
+
+			pc -= (unsigned long) &_stext;
+			pc >>= prof_shift;
+			/*
+			 * Dont ignore out-of-bounds pc values silently,
+			 * put them into the last histogram slot, so if
+			 * present, they will show up as a sharp peak.
+			 */
+			if (pc > prof_len-1)
+			pc = prof_len-1;
+			atomic_inc((atomic_t *)&prof_buffer[pc]);
+		}
+	}
+
+#ifdef CONFIG_SMP
+	/* in UP mode, update_process_times() is invoked by do_timer() */
+	update_process_times(user_mode(regs));
+#endif
+}
+
+/*
  * high-level timer interrupt service routines.  This function
  * is set as irqaction->handler and is invoked through do_IRQ.
  */
@@ -310,24 +350,6 @@
 
 	}
 
-	if(!user_mode(regs)) {
-		if (prof_buffer && current->pid) {
-			extern int _stext;
-			unsigned long pc = regs->cp0_epc;
-
-			pc -= (unsigned long) &_stext;
-			pc >>= prof_shift;
-			/*
-			 * Dont ignore out-of-bounds pc values silently,
-			 * put them into the last histogram slot, so if
-			 * present, they will show up as a sharp peak.
-			 */
-			if (pc > prof_len-1)
-			pc = prof_len-1;
-			atomic_inc((atomic_t *)&prof_buffer[pc]);
-		}
-	}
-
 	/*
 	 * call the generic timer interrupt handling
 	 */
@@ -360,6 +382,31 @@
 	if (!jiffies) {
 		timerhi = timerlo = 0;
 	}
+
+#if !defined(CONFIG_SMP)
+	/* 
+	 * In UP mode, we call local_timer_interrupt() to do profiling
+	 * and process accouting.  
+	 *
+	 * In SMP mode, local_timer_interrupt() is invoked by appropriate
+	 * low-level local timer interrupt handler.
+	 */
+	local_timer_interrupt(0, NULL, regs);
+
+#else	/* CONFIG_SMP */
+
+	if (emulate_local_timer_interrupt) {
+		/* 
+		 * this is the place where we send out inter-process
+		 * interrupts and let each CPU do its own profiling
+		 * and process accouting.
+		 *
+		 * Obviously we need to call local_timer_interrupt() for
+		 * the current CPU too.
+		 */
+		panic("Not implemented yet!!!");
+	}
+#endif	/* CONFIG_SMP */
 }
 
 asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
@@ -378,6 +425,21 @@
 		do_softirq();
 }
 
+asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs)
+{
+	int cpu = smp_processor_id();
+
+	irq_enter(cpu, irq);
+	kstat.irqs[cpu][irq]++;
+
+	/* we keep interrupt disabled all the time */
+	local_timer_interrupt(irq, NULL, regs);
+	
+	irq_exit(cpu, irq);
+
+	if (softirq_pending(cpu))
+		do_softirq();
+}
 
 /*
  * time_init() - it does the following things.
@@ -407,7 +469,8 @@
 	0,
 	"timer",
 	NULL,
-	NULL};
+	NULL
+};
 
 void __init time_init(void)
 {
@@ -475,10 +538,10 @@
 
 void to_tm(unsigned long tim, struct rtc_time * tm)
 {
-	long hms, day;
+	long hms, day, gday;
 	int i;
 
-	day = tim / SECDAY;
+	gday = day = tim / SECDAY;
 	hms = tim % SECDAY;
 
 	/* Hours, minutes, seconds are easy */
@@ -497,7 +560,7 @@
 	for (i = 1; day >= days_in_month(i); i++)
 	day -= days_in_month(i);
 	days_in_month(FEBRUARY) = 28;
-	tm->tm_mon = i;
+	tm->tm_mon = i-1;	/* tm_mon starts from 0 to 11 */
 
 	/* Days are what is left over (+1) from all that. */
 	tm->tm_mday = day + 1;
@@ -505,5 +568,5 @@
 	/*
 	 * Determine the day of week
 	 */
-	tm->tm_wday = (day + 3) % 7;
+	tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/traps.c linux/arch/mips/kernel/traps.c
--- linux.orig/arch/mips/kernel/traps.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/traps.c	2002-08-01 06:42:42.000000000 +0000
@@ -10,6 +10,7 @@
  *
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
  */
 #include <linux/config.h>
 #include <linux/init.h>
@@ -32,6 +33,7 @@
 #include <asm/siginfo.h>
 #include <asm/watch.h>
 #include <asm/system.h>
+#include <asm/traps.h>
 #include <asm/uaccess.h>
 #include <asm/mmu_context.h>
 
@@ -66,8 +68,7 @@
 
 char watch_available = 0;
 
-void (*ibe_board_handler)(struct pt_regs *regs);
-void (*dbe_board_handler)(struct pt_regs *regs);
+int (*be_board_handler)(struct pt_regs *regs, int is_fixup);
 
 int kstack_depth_to_print = 24;
 
@@ -77,12 +78,9 @@
  */
 #define MODULE_RANGE (8*1024*1024)
 
-#ifndef CONFIG_CPU_HAS_LLSC
 /*
  * This stuff is needed for the userland ll-sc emulation for R2300
  */
-void simulate_ll(struct pt_regs *regs, unsigned int opcode);
-void simulate_sc(struct pt_regs *regs, unsigned int opcode);
 
 #define OPCODE 0xfc000000
 #define BASE   0x03e00000
@@ -90,8 +88,97 @@
 #define OFFSET 0x0000ffff
 #define LL     0xc0000000
 #define SC     0xe0000000
+
+/*
+ * The ll_bit is cleared by r*_switch.S
+ */
+
+unsigned long ll_bit;
+#ifdef CONFIG_PROC_FS
+extern unsigned long ll_ops;
+extern unsigned long sc_ops;
+#endif
+
+static struct task_struct *ll_task = NULL;
+
+static inline void simulate_ll(struct pt_regs *regp, unsigned int opcode)
+{
+	unsigned long value, *vaddr;
+	long offset;
+	int signal = 0;
+
+	/*
+	 * analyse the ll instruction that just caused a ri exception
+	 * and put the referenced address to addr.
+	 */
+
+	/* sign extend offset */
+	offset = opcode & OFFSET;
+	offset <<= 16;
+	offset >>= 16;
+
+	vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
+
+#ifdef CONFIG_PROC_FS
+	ll_ops++;
+#endif
+
+	if ((unsigned long)vaddr & 3)
+		signal = SIGBUS;
+	else if (get_user(value, vaddr))
+		signal = SIGSEGV;
+	else {
+		if (ll_task == NULL || ll_task == current) {
+			ll_bit = 1;
+		} else {
+			ll_bit = 0;
+		}
+		ll_task = current;
+		regp->regs[(opcode & RT) >> 16] = value;
+	}
+	if (compute_return_epc(regp))
+		return;
+	if (signal)
+		send_sig(signal, current, 1);
+}
+
+static inline void simulate_sc(struct pt_regs *regp, unsigned int opcode)
+{
+	unsigned long *vaddr, reg;
+	long offset;
+	int signal = 0;
+
+	/*
+	 * analyse the sc instruction that just caused a ri exception
+	 * and put the referenced address to addr.
+	 */
+
+	/* sign extend offset */
+	offset = opcode & OFFSET;
+	offset <<= 16;
+	offset >>= 16;
+
+	vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
+	reg = (opcode & RT) >> 16;
+
+#ifdef CONFIG_PROC_FS
+	sc_ops++;
 #endif
 
+	if ((unsigned long)vaddr & 3)
+		signal = SIGBUS;
+	else if (ll_bit == 0 || ll_task != current)
+		regp->regs[reg] = 0;
+	else if (put_user(regp->regs[reg], vaddr))
+		signal = SIGSEGV;
+	else
+		regp->regs[reg] = 1;
+	if (compute_return_epc(regp))
+		return;
+	if (signal)
+		send_sig(signal, current, 1);
+}
+
 /*
  * This routine abuses get_user()/put_user() to reference pointers
  * with at least a bit of error checking ...
@@ -101,7 +188,7 @@
 	int i;
 	unsigned int *stack;
 
-	stack = sp;
+	stack = sp ? sp : (unsigned int *)&sp;
 	i = 0;
 
 	printk("Stack:");
@@ -128,12 +215,13 @@
 void show_trace(unsigned int *sp)
 {
 	int i;
+	int column = 0;
 	unsigned int *stack;
 	unsigned long kernel_start, kernel_end;
 	unsigned long module_start, module_end;
 	extern char _stext, _etext;
 
-	stack = sp;
+	stack = sp ? sp : (unsigned int *) &sp;
 	i = 0;
 
 	kernel_start = (unsigned long) &_stext;
@@ -164,12 +252,23 @@
 		    (addr >= module_start && addr < module_end)) { 
 
 			printk(" [<%08lx>]", addr);
+			if (column++ == 5) {
+				printk("\n");
+				column = 0;
+			}
 			if (++i > 40) {
 				printk(" ...");
 				break;
 			}
 		}
 	}
+	if (column != 0)
+		printk("\n");
+}
+
+void show_trace_task(struct task_struct *tsk)
+{
+	show_trace((unsigned int *)tsk->thread.reg29);
 }
 
 void show_code(unsigned int *pc)
@@ -188,17 +287,36 @@
 	}
 }
 
-spinlock_t die_lock;
+void show_regs(struct pt_regs * regs)
+{
+	/*
+	 * Saved main processor registers
+	 */
+	printk("$0 : %08x %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+	       0,             regs->regs[1], regs->regs[2], regs->regs[3],
+	       regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
+	printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+	       regs->regs[8],  regs->regs[9],  regs->regs[10], regs->regs[11],
+               regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
+	printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+	       regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19],
+               regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
+	printk("$24: %08lx %08lx                   %08lx %08lx %08lx %08lx\n",
+	       regs->regs[24], regs->regs[25],
+	       regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
+	printk("Hi : %08lx\n", regs->hi);
+	printk("Lo : %08lx\n", regs->lo);
 
-extern void __die(const char * str, struct pt_regs * regs, const char *where,
-                  unsigned long line)
+	/*
+	 * Saved cp0 registers
+	 */
+	printk("epc  : %08lx    %s\nStatus: %08lx\nCause : %08lx\n",
+	       regs->cp0_epc, print_tainted(), regs->cp0_status,
+	       regs->cp0_cause);
+}
+
+void show_registers(struct pt_regs *regs)
 {
-	console_verbose();
-	spin_lock_irq(&die_lock);
-	printk("%s", str);
-	if (where)
-		printk(" in %s, line %ld", where, line);
-	printk(":\n");
 	show_regs(regs);
 	printk("Process %s (pid: %d, stackpage=%08lx)\n",
 		current->comm, current->pid, (unsigned long) current);
@@ -206,6 +324,20 @@
 	show_trace((unsigned int *) regs->regs[29]);
 	show_code((unsigned int *) regs->cp0_epc);
 	printk("\n");
+}
+
+static spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
+
+void __die(const char * str, struct pt_regs * regs, const char *where,
+           unsigned long line)
+{
+	console_verbose();
+	spin_lock_irq(&die_lock);
+	printk("%s", str);
+	if (where)
+		printk(" in %s, line %ld", where, line);
+	printk(":\n");
+	show_registers(regs);
 	spin_unlock_irq(&die_lock);
 	do_exit(SIGSEGV);
 }
@@ -286,20 +418,35 @@
 #endif
 }
 
-static void default_be_board_handler(struct pt_regs *regs)
+asmlinkage void do_be(struct pt_regs *regs)
 {
 	unsigned long new_epc;
-	unsigned long fixup;
+	unsigned long fixup = 0;
 	int data = regs->cp0_cause & 4;
+	int action = MIPS_BE_FATAL;
 
-	if (data && !user_mode(regs)) {
+	if (data && !user_mode(regs))
 		fixup = search_dbe_table(regs->cp0_epc);
+
+	if (fixup)
+		action = MIPS_BE_FIXUP;
+
+	if (be_board_handler)
+		action = be_board_handler(regs, fixup != 0);
+
+	switch (action) {
+	case MIPS_BE_DISCARD:
+		return;
+	case MIPS_BE_FIXUP:
 		if (fixup) {
 			new_epc = fixup_exception(dpf_reg, fixup,
 						  regs->cp0_epc);
 			regs->cp0_epc = new_epc;
 			return;
 		}
+		break;
+	default:
+		break;
 	}
 
 	/*
@@ -312,16 +459,6 @@
 	force_sig(SIGBUS, current);
 }
 
-asmlinkage void do_ibe(struct pt_regs *regs)
-{
-	ibe_board_handler(regs);
-}
-
-asmlinkage void do_dbe(struct pt_regs *regs)
-{
-	dbe_board_handler(regs);
-}
-
 asmlinkage void do_ov(struct pt_regs *regs)
 {
 	if (compute_return_epc(regs))
@@ -356,26 +493,31 @@
 		sig = fpu_emulator_cop1Handler(regs);
 
 		/* 
-		 * We can't allow the emulated instruction to leave the
-		 * Unimplemented Operation bit set in $fcr31.
+		 * We can't allow the emulated instruction to leave any of 
+		 * the cause bit set in $fcr31.
 		 */
-		current->thread.fpu.soft.sr &= ~FPU_CSR_UNI_X;
+		current->thread.fpu.soft.sr &= ~FPU_CSR_ALL_X;
 
 		/* Restore the hardware register state */
 		restore_fp(current);
 
 		/* If something went wrong, signal */
 		if (sig)
+		{
+			/* 
+			 * Return EPC is not calculated in the FPU emulator, 
+			 * if a signal is being send. So we calculate it here.
+			 */
+			compute_return_epc(regs);
 			force_sig(sig, current);
+		}
 
 		return;
 	}
 
 	if (compute_return_epc(regs))
 		return;
-
 	force_sig(SIGFPE, current);
-	printk(KERN_DEBUG "Sent send SIGFPE to %s\n", current->comm);
 }
 
 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
@@ -424,7 +566,7 @@
 			info.si_code = FPE_INTOVF;
 		info.si_signo = SIGFPE;
 		info.si_errno = 0;
-		info.si_addr = (void *)compute_return_epc(regs);
+		info.si_addr = (void *)regs->cp0_epc;
 		force_sig_info(SIGFPE, &info, current);
 		break;
 	default:
@@ -464,7 +606,7 @@
 			info.si_code = FPE_INTOVF;
 		info.si_signo = SIGFPE;
 		info.si_errno = 0;
-		info.si_addr = (void *)compute_return_epc(regs);
+		info.si_addr = (void *)regs->cp0_epc;
 		force_sig_info(SIGFPE, &info, current);
 		break;
 	default:
@@ -476,12 +618,6 @@
 	force_sig(SIGSEGV, current);
 }
 
-#ifndef CONFIG_CPU_HAS_LLSC
-
-#ifdef CONFIG_SMP
-#error "ll/sc emulation is not SMP safe"
-#endif
-
 /*
  * userland emulation for R2300 CPUs
  * needed for the multithreading part of glibc
@@ -491,11 +627,18 @@
  */
 asmlinkage void do_ri(struct pt_regs *regs)
 {
-	unsigned int opcode;
-
 	if (!user_mode(regs))
 		BUG();
 
+#ifndef CONFIG_CPU_HAS_LLSC
+
+#ifdef CONFIG_SMP
+#error "ll/sc emulation is not SMP safe"
+#endif
+
+	{
+	unsigned int opcode;
+
 	if (!get_insn_opcode(regs, &opcode)) {
 		if ((opcode & OPCODE) == LL) {
 			simulate_ll(regs, opcode);
@@ -506,121 +649,19 @@
 			return;
 		}
 	}
-
-	if (compute_return_epc(regs))
-		return;
-	force_sig(SIGILL, current);
-}
-
-/*
- * The ll_bit is cleared by r*_switch.S
- */
-
-unsigned long ll_bit;
-#ifdef CONFIG_PROC_FS
-extern unsigned long ll_ops;
-extern unsigned long sc_ops;
-#endif
-
-static struct task_struct *ll_task = NULL;
-
-void simulate_ll(struct pt_regs *regp, unsigned int opcode)
-{
-	unsigned long value, *vaddr;
-	long offset;
-	int signal = 0;
-
-	/*
-	 * analyse the ll instruction that just caused a ri exception
-	 * and put the referenced address to addr.
-	 */
-
-	/* sign extend offset */
-	offset = opcode & OFFSET;
-	offset <<= 16;
-	offset >>= 16;
-
-	vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
-
-#ifdef CONFIG_PROC_FS
-	ll_ops++;
-#endif
-
-	if ((unsigned long)vaddr & 3)
-		signal = SIGBUS;
-	else if (get_user(value, vaddr))
-		signal = SIGSEGV;
-	else {
-		if (ll_task == NULL || ll_task == current) {
-			ll_bit = 1;
-		} else {
-			ll_bit = 0;
-		}
-		ll_task = current;
-		regp->regs[(opcode & RT) >> 16] = value;
 	}
-	if (compute_return_epc(regp))
-		return;
-	if (signal)
-		send_sig(signal, current, 1);
-}
-
-void simulate_sc(struct pt_regs *regp, unsigned int opcode)
-{
-	unsigned long *vaddr, reg;
-	long offset;
-	int signal = 0;
-
-	/*
-	 * analyse the sc instruction that just caused a ri exception
-	 * and put the referenced address to addr.
-	 */
+#endif /* CONFIG_CPU_HAS_LLSC */
 
-	/* sign extend offset */
-	offset = opcode & OFFSET;
-	offset <<= 16;
-	offset >>= 16;
-
-	vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
-	reg = (opcode & RT) >> 16;
-
-#ifdef CONFIG_PROC_FS
-	sc_ops++;
-#endif
-
-	if ((unsigned long)vaddr & 3)
-		signal = SIGBUS;
-	else if (ll_bit == 0 || ll_task != current)
-		regp->regs[reg] = 0;
-	else if (put_user(regp->regs[reg], vaddr))
-		signal = SIGSEGV;
-	else
-		regp->regs[reg] = 1;
-	if (compute_return_epc(regp))
-		return;
-	if (signal)
-		send_sig(signal, current, 1);
-}
-
-#else /* MIPS 2 or higher */
-
-asmlinkage void do_ri(struct pt_regs *regs)
-{
-	unsigned int opcode;
-
-	get_insn_opcode(regs, &opcode);
 	if (compute_return_epc(regs))
 		return;
-
 	force_sig(SIGILL, current);
 }
 
-#endif
-
 asmlinkage void do_cpu(struct pt_regs *regs)
 {
 	unsigned int cpid;
 	extern void lazy_fpu_switch(void *);
+	extern void save_fp(struct task_struct *);
 	extern void init_fpu(void);
 	void fpu_emulator_init_fpu(void);
 	int sig;
@@ -639,10 +680,13 @@
 	if (current->used_math) {		/* Using the FPU again.  */
 		lazy_fpu_switch(last_task_used_math);
 	} else {				/* First time FPU user.  */
+		if (last_task_used_math != NULL)
+			save_fp(last_task_used_math);
 		init_fpu();
 		current->used_math = 1;
 	}
 	last_task_used_math = current;
+
 	return;
 
 fp_emul:
@@ -655,19 +699,38 @@
 	sig = fpu_emulator_cop1Handler(regs);
 	last_task_used_math = current;
 	if (sig)
+	{
+		/* 
+		 * Return EPC is not calculated in the FPU emulator, if 
+		 * a signal is being send. So we calculate it here.
+		 */
+		compute_return_epc(regs);
 		force_sig(sig, current);
+	}
 	return;
 
 bad_cid:
+#ifndef CONFIG_CPU_HAS_LLSC
+	switch (mips_cpu.cputype) {
+	case CPU_TX3927:
+	case CPU_TX39XX:
+		do_ri(regs);
+		return;
+	}
+#endif
+	compute_return_epc(regs);
 	force_sig(SIGILL, current);
 }
 
 asmlinkage void do_watch(struct pt_regs *regs)
 {
+	extern void dump_tlb_all(void);
+
 	/*
 	 * We use the watch exception where available to detect stack
 	 * overflows.
 	 */
+	dump_tlb_all();
 	show_regs(regs);
 	panic("Caught WATCH exception - probably caused by stack overflow.");
 }
@@ -753,6 +816,50 @@
 	panic("Can't handle the cache error!");
 }
 
+/*
+ * SDBBP EJTAG debug exception handler.
+ * We skip the instruction and return to the next instruction.
+ */
+void ejtag_exception_handler(struct pt_regs *regs)
+{
+        unsigned int depc, old_epc, debug;
+
+        printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
+        depc = read_32bit_cp0_register(CP0_DEPC);
+        debug = read_32bit_cp0_register(CP0_DEBUG);
+        printk("DEPC = %08x, DEBUG = %08x\n", depc, debug); 
+        if (debug & 0x80000000) {
+                /* 
+                 * In branch delay slot.
+                 * We cheat a little bit here and use EPC to calculate the
+                 * debug return address (DEPC). EPC is restored after the
+                 * calculation.
+                 */
+                old_epc = regs->cp0_epc;
+                regs->cp0_epc = depc;
+                __compute_return_epc(regs);
+                depc = regs->cp0_epc;
+                regs->cp0_epc = old_epc;
+        } else
+                depc += 4;
+        write_32bit_cp0_register(CP0_DEPC, depc);
+
+#if 0
+	printk("\n\n----- Enable EJTAG single stepping ----\n\n");
+	write_32bit_cp0_register(CP0_DEBUG, debug | 0x100);
+#endif
+}
+
+/*
+ * NMI exception handler.
+ */
+void nmi_exception_handler(struct pt_regs *regs)
+{
+        printk("NMI taken!!!!\n");
+        die("NMI", regs);
+        while(1) ;  /* We die here. */
+}
+
 unsigned long exception_handlers[32];
 
 /*
@@ -782,24 +889,39 @@
 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
 
+void __init per_cpu_trap_init(void)
+{
+	unsigned int cpu = smp_processor_id();
+
+	/* Some firmware leaves the BEV flag set, clear it.  */
+	clear_cp0_status(ST0_BEV);
+
+	/*
+	 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+	 * interrupt processing overhead.  Use it where available.
+	 */
+	if (mips_cpu.options & MIPS_CPU_DIVEC)
+		set_cp0_cause(CAUSEF_IV);
+
+	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
+	set_context(cpu << 23);
+}
+
 void __init trap_init(void)
 {
-	extern char except_vec0_nevada, except_vec0_r4000;
-	extern char except_vec0_r4600, except_vec0_r2300;
 	extern char except_vec1_generic, except_vec2_generic;
 	extern char except_vec3_generic, except_vec3_r4000;
 	extern char except_vec4;
 	extern char except_vec_ejtag_debug;
 	unsigned long i;
 
-	/* Some firmware leaves the BEV flag set, clear it.  */
-	clear_cp0_status(ST0_BEV);
+	per_cpu_trap_init();
 
 	/* Copy the generic exception handler code to it's final destination. */
 	memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
 	memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
 	memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
-	flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
+
 	/*
 	 * Setup default vectors
 	 */
@@ -810,7 +932,8 @@
 	 * Copy the EJTAG debug exception vector handler code to it's final 
 	 * destination.
 	 */
-	memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
+	if (mips_cpu.options & MIPS_CPU_EJTAG)
+		memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
 
 	/*
 	 * Only some CPUs have the watch exceptions or a dedicated
@@ -833,21 +956,21 @@
 	 */
 	parity_protection_init();
 
+	/*
+	 * The Data Bus Errors / Instruction Bus Errors are signaled
+	 * by external hardware.  Therefore these two exceptions
+	 * may have board specific handlers.
+	 */
+	bus_error_init();
+
 	set_except_vector(1, handle_mod);
 	set_except_vector(2, handle_tlbl);
 	set_except_vector(3, handle_tlbs);
 	set_except_vector(4, handle_adel);
 	set_except_vector(5, handle_ades);
 
-	/*
-	 * The Data Bus Error/ Instruction Bus Errors are signaled
-	 * by external hardware.  Therefore these two expection have
-	 * board specific handlers.
-	 */
 	set_except_vector(6, handle_ibe);
 	set_except_vector(7, handle_dbe);
-	ibe_board_handler = default_be_board_handler;
-	dbe_board_handler = default_be_board_handler;
 
 	set_except_vector(8, handle_sys);
 	set_except_vector(9, handle_bp);
@@ -856,37 +979,22 @@
 	set_except_vector(12, handle_ov);
 	set_except_vector(13, handle_tr);
 
-	if (mips_cpu.options & MIPS_CPU_FPU)
+	if ((mips_cpu.options & MIPS_CPU_FPU) &&
+	    !(mips_cpu.options & MIPS_CPU_NOFPUEX))
 		set_except_vector(15, handle_fpe);
+	if (mips_cpu.options & MIPS_CPU_MCHECK)
+		set_except_vector(24, handle_mcheck);
 
 	/*
 	 * Handling the following exceptions depends mostly of the cpu type
 	 */
 	if ((mips_cpu.options & MIPS_CPU_4KEX)
 	    && (mips_cpu.options & MIPS_CPU_4KTLB)) {
-		if (mips_cpu.cputype == CPU_NEVADA) {
-			memcpy((void *)KSEG0, &except_vec0_nevada, 0x80);
-		} else if (mips_cpu.cputype == CPU_R4600)
-			memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
-		else
-			memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
-
 		/* Cache error vector already set above.  */
 
 		if (mips_cpu.options & MIPS_CPU_VCE) {
 			memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000,
 			       0x80);
-		} else {
-			memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic,
-			       0x80);
-		}
-
-		if (mips_cpu.options & MIPS_CPU_FPU) {
-		        save_fp_context = _save_fp_context;
-			restore_fp_context = _restore_fp_context;
-		} else {
-		        save_fp_context = fpu_emulator_save_context;
-			restore_fp_context = fpu_emulator_restore_context;
 		}
 	} else switch (mips_cpu.cputype) {
 	case CPU_SB1:
@@ -894,10 +1002,15 @@
 		 * XXX - This should be folded in to the "cleaner" handling,
 		 * above
 		 */
-		memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
 		memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
-		save_fp_context = _save_fp_context;
-		restore_fp_context = _restore_fp_context;
+#ifdef CONFIG_SB1_CACHE_ERROR
+		{
+		/* Special cache error handler for SB1 */
+		extern char except_vec2_sb1;
+		memcpy((void *)(KSEG0 + 0x100), &except_vec2_sb1, 0x80);
+		memcpy((void *)(KSEG1 + 0x100), &except_vec2_sb1, 0x80);
+		}
+#endif
 
 		/* Enable timer interrupt and scd mapped interrupt */
 		clear_cp0_status(0xf000);
@@ -905,9 +1018,6 @@
 		break;
 	case CPU_R6000:
 	case CPU_R6000A:
-	        save_fp_context = _save_fp_context;
-		restore_fp_context = _restore_fp_context;
-		
 		/*
 		 * The R6000 is the only R-series CPU that features a machine
 		 * check exception (similar to the R4000 cache error) and
@@ -929,9 +1039,7 @@
 	case CPU_TX3912:
 	case CPU_TX3922:
 	case CPU_TX3927:
-	        save_fp_context = _save_fp_context;
-		restore_fp_context = _restore_fp_context;
-		memcpy((void *)KSEG0, &except_vec0_r2300, 0x80);
+	case CPU_TX39XX:
 		memcpy((void *)(KSEG0 + 0x80), &except_vec3_generic, 0x80);
 		break;
 
@@ -939,13 +1047,24 @@
 	default:
 		panic("Unknown CPU type");
 	}
-	flush_icache_range(KSEG0, KSEG0 + 0x200);
+
+	flush_icache_range(KSEG0, KSEG0 + 0x400);
+
+	if (mips_cpu.options & MIPS_CPU_FPU) {
+	        save_fp_context = _save_fp_context;
+		restore_fp_context = _restore_fp_context;
+	} else {
+		save_fp_context = fpu_emulator_save_context;
+		restore_fp_context = fpu_emulator_restore_context;
+	}
 
 	if (mips_cpu.isa_level == MIPS_CPU_ISA_IV)
 		set_cp0_status(ST0_XX);
 
 	atomic_inc(&init_mm.mm_count);	/* XXX  UP?  */
 	current->active_mm = &init_mm;
-	write_32bit_cp0_register(CP0_CONTEXT, smp_processor_id()<<23);
-	current_pgd[0] = init_mm.pgd;
+
+	/* XXX Must be done for all CPUs  */
+	current_cpu_data.asid_cache = ASID_FIRST_VERSION;
+	TLBMISS_HANDLER_SETUP();
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/kernel/unaligned.c linux/arch/mips/kernel/unaligned.c
--- linux.orig/arch/mips/kernel/unaligned.c	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/kernel/unaligned.c	2002-08-01 06:42:29.000000000 +0000
@@ -5,7 +5,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996, 1998 by Ralf Baechle
+ * Copyright (C) 1996, 1998, 2002 by Ralf Baechle
  * Copyright (C) 1999 Silicon Graphics, Inc.
  *
  * This file contains exception handler for address error exception with the
@@ -96,13 +96,12 @@
 	if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0)	\
 		goto sigbus;
 
-static inline void
-emulate_load_store_insn(struct pt_regs *regs,
-                        unsigned long addr,
-                        unsigned long pc)
+static inline int emulate_load_store_insn(struct pt_regs *regs,
+	unsigned long addr, unsigned long pc)
 {
 	union mips_instruction insn;
 	unsigned long value, fixup;
+	unsigned int res;
 
 	regs->regs[0] = 0;
 	/*
@@ -145,116 +144,96 @@
 	 */
 	case lh_op:
 		check_axs(pc, addr, 2);
-		__asm__(
-			".set\tnoat\n"
+		__asm__(".set\tnoat\n"
 #ifdef __BIG_ENDIAN
-			"1:\tlb\t%0,0(%1)\n"
-			"2:\tlbu\t$1,1(%1)\n\t"
+			"1:\tlb\t%0, 0(%2)\n"
+			"2:\tlbu\t$1, 1(%2)\n\t"
 #endif
 #ifdef __LITTLE_ENDIAN
-			"1:\tlb\t%0,1(%1)\n"
-			"2:\tlbu\t$1,0(%1)\n\t"
+			"1:\tlb\t%0, 1(%2)\n"
+			"2:\tlbu\t$1, 0(%2)\n\t"
 #endif
-			"sll\t%0,0x8\n\t"
-			"or\t%0,$1\n\t"
-			".set\tat\n\t"
+			"sll\t%0, 0x8\n\t"
+			"or\t%0, $1\n\t"
+			"li\t%1, 0\n"
+			"3:\t.set\tat\n\t"
+			".section\t.fixup,\"ax\"\n\t"
+			"4:\tli\t%1, %3\n\t"
+			"j\t3b\n\t"
+			".previous\n\t"
 			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
+			STR(PTR)"\t1b, 4b\n\t"
+			STR(PTR)"\t2b, 4b\n\t"
 			".previous"
-			:"=&r" (value)
-			:"r" (addr), "i" (&&fault)
-			:"$1");
+			: "=&r" (value), "=r" (res)
+			: "r" (addr), "i" (-EFAULT));
+		if (res)
+			goto fault;
 		regs->regs[insn.i_format.rt] = value;
-		return;
+		return 0;
 
 	case lw_op:
 		check_axs(pc, addr, 4);
 		__asm__(
 #ifdef __BIG_ENDIAN
-			"1:\tlwl\t%0,(%1)\n"
-			"2:\tlwr\t%0,3(%1)\n\t"
+			"1:\tlwl\t%0, (%2)\n"
+			"2:\tlwr\t%0, 3(%2)\n\t"
 #endif
 #ifdef __LITTLE_ENDIAN
-			"1:\tlwl\t%0,3(%1)\n"
-			"2:\tlwr\t%0,(%1)\n\t"
+			"1:\tlwl\t%0, 3(%2)\n"
+			"2:\tlwr\t%0, (%2)\n\t"
 #endif
+			"li\t%1, 0\n"
+			"3:\t.section\t.fixup,\"ax\"\n\t"
+			"4:\tli\t%1, %3\n\t"
+			"j\t3b\n\t"
+			".previous\n\t"
 			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
+			STR(PTR)"\t1b, 4b\n\t"
+			STR(PTR)"\t2b, 4b\n\t"
 			".previous"
-			:"=&r" (value)
-			:"r" (addr), "i" (&&fault));
-			regs->regs[insn.i_format.rt] = value;
-			return;
+			: "=&r" (value), "=r" (res)
+			: "r" (addr), "i" (-EFAULT));
+		if (res)
+			goto fault;
+		regs->regs[insn.i_format.rt] = value;
+		return 0;
 
 	case lhu_op:
 		check_axs(pc, addr, 2);
 		__asm__(
 			".set\tnoat\n"
 #ifdef __BIG_ENDIAN
-			"1:\tlbu\t%0,0(%1)\n"
-			"2:\tlbu\t$1,1(%1)\n\t"
+			"1:\tlbu\t%0, 0(%2)\n"
+			"2:\tlbu\t$1, 1(%2)\n\t"
 #endif
 #ifdef __LITTLE_ENDIAN
-			"1:\tlbu\t%0,1(%1)\n"
-			"2:\tlbu\t$1,0(%1)\n\t"
+			"1:\tlbu\t%0, 1(%2)\n"
+			"2:\tlbu\t$1, 0(%2)\n\t"
 #endif
-			"sll\t%0,0x8\n\t"
-			"or\t%0,$1\n\t"
-			".set\tat\n\t"
+			"sll\t%0, 0x8\n\t"
+			"or\t%0, $1\n\t"
+			"li\t%1, 0\n"
+			"3:\t.set\tat\n\t"
+			".section\t.fixup,\"ax\"\n\t"
+			"4:\tli\t%1, %3\n\t"
+			"j\t3b\n\t"
+			".previous\n\t"
 			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
+			STR(PTR)"\t1b, 4b\n\t"
+			STR(PTR)"\t2b, 4b\n\t"
 			".previous"
-			:"=&r" (value)
-			:"r" (addr), "i" (&&fault)
-			:"$1");
+			: "=&r" (value), "=r" (res)
+			: "r" (addr), "i" (-EFAULT));
+		if (res)
+			goto fault;
 		regs->regs[insn.i_format.rt] = value;
-		return;
+		return 0;
 
 	case lwu_op:
-		check_axs(pc, addr, 4);
-		__asm__(
-#ifdef __BIG_ENDIAN
-			"1:\tlwl\t%0,(%1)\n"
-			"2:\tlwr\t%0,3(%1)\n\t"
-#endif
-#ifdef __LITTLE_ENDIAN
-			"1:\tlwl\t%0,3(%1)\n"
-			"2:\tlwr\t%0,(%1)\n\t"
-#endif
-			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
-			".previous"
-			:"=&r" (value)
-			:"r" (addr), "i" (&&fault));
-		value &= 0xffffffff;
-		regs->regs[insn.i_format.rt] = value;
-		return;
-
 	case ld_op:
-		check_axs(pc, addr, 8);
-		__asm__(
-			".set\tmips3\n"
-#ifdef __BIG_ENDIAN
-			"1:\tldl\t%0,(%1)\n"
-			"2:\tldr\t%0,7(%1)\n\t"
-#endif
-#ifdef __LITTLE_ENDIAN
-			"1:\tldl\t%0,7(%1)\n"
-			"2:\tldr\t%0,(%1)\n\t"
-#endif
-			".set\tmips0\n\t"
-			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
-			".previous"
-			:"=&r" (value)
-			:"r" (addr), "i" (&&fault));
-		regs->regs[insn.i_format.rt] = value;
-		return;
+		/* Cannot handle 64-bit instructions in 32-bit kernel */
+		goto sigill;
 
 	case sh_op:
 		check_axs(pc, addr, 2);
@@ -262,68 +241,65 @@
 		__asm__(
 #ifdef __BIG_ENDIAN
 			".set\tnoat\n"
-			"1:\tsb\t%0,1(%1)\n\t"
-			"srl\t$1,%0,0x8\n"
-			"2:\tsb\t$1,0(%1)\n\t"
+			"1:\tsb\t%1, 1(%2)\n\t"
+			"srl\t$1, %1, 0x8\n"
+			"2:\tsb\t$1, 0(%2)\n\t"
 			".set\tat\n\t"
 #endif
 #ifdef __LITTLE_ENDIAN
 			".set\tnoat\n"
-			"1:\tsb\t%0,0(%1)\n\t"
-			"srl\t$1,%0,0x8\n"
-			"2:\tsb\t$1,1(%1)\n\t"
+			"1:\tsb\t%1, 0(%2)\n\t"
+			"srl\t$1,%1, 0x8\n"
+			"2:\tsb\t$1, 1(%2)\n\t"
 			".set\tat\n\t"
 #endif
+			"li\t%0, 0\n"
+			"3:\n\t"
+			".section\t.fixup,\"ax\"\n\t"
+			"4:\tli\t%0, %3\n\t"
+			"j\t3b\n\t"
+			".previous\n\t"
 			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
+			STR(PTR)"\t1b, 4b\n\t"
+			STR(PTR)"\t2b, 4b\n\t"
 			".previous"
-			: /* no outputs */
-			:"r" (value), "r" (addr), "i" (&&fault)
-			:"$1");
-		return;
+			: "=r" (res)
+			: "r" (value), "r" (addr), "i" (-EFAULT));
+		if (res)
+			goto fault;
+		return 0;
 
 	case sw_op:
 		check_axs(pc, addr, 4);
 		value = regs->regs[insn.i_format.rt];
 		__asm__(
 #ifdef __BIG_ENDIAN
-			"1:\tswl\t%0,(%1)\n"
-			"2:\tswr\t%0,3(%1)\n\t"
+			"1:\tswl\t%1,(%2)\n"
+			"2:\tswr\t%1, 3(%2)\n\t"
 #endif
 #ifdef __LITTLE_ENDIAN
-			"1:\tswl\t%0,3(%1)\n"
-			"2:\tswr\t%0,(%1)\n\t"
+			"1:\tswl\t%1, 3(%2)\n"
+			"2:\tswr\t%1, (%2)\n\t"
 #endif
+			"li\t%0, 0\n"
+			"3:\n\t"
+			".section\t.fixup,\"ax\"\n\t"
+			"4:\tli\t%0, %3\n\t"
+			"j\t3b\n\t"
+			".previous\n\t"
 			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
+			STR(PTR)"\t1b, 4b\n\t"
+			STR(PTR)"\t2b, 4b\n\t"
 			".previous"
-			: /* no outputs */
-			:"r" (value), "r" (addr), "i" (&&fault));
-		return;
+		: "=r" (res)
+		: "r" (value), "r" (addr), "i" (-EFAULT));
+		if (res)
+			goto fault;
+		return 0;
 
 	case sd_op:
-		check_axs(pc, addr, 8);
-		value = regs->regs[insn.i_format.rt];
-		__asm__(
-			".set\tmips3\n"
-#ifdef __BIG_ENDIAN
-			"1:\tsdl\t%0,(%1)\n"
-			"2:\tsdr\t%0,7(%1)\n\t"
-#endif
-#ifdef __LITTLE_ENDIAN
-			"1:\tsdl\t%0,7(%1)\n"
-			"2:\tsdr\t%0,(%1)\n\t"
-#endif
-			".set\tmips0\n\t"
-			".section\t__ex_table,\"a\"\n\t"
-			STR(PTR)"\t1b,%2\n\t"
-			STR(PTR)"\t2b,%2\n\t"
-			".previous"
-			: /* no outputs */
-			:"r" (value), "r" (addr), "i" (&&fault));
-		return;
+		/* Cannot handle 64-bit instructions in 32-bit kernel */
+		goto sigill;
 
 	case lwc1_op:
 	case ldc1_op:
@@ -352,31 +328,35 @@
 		 */
 		goto sigill;
 	}
-	return;
+	return 0;
 
 fault:
 	/* Did we have an exception handler installed? */
-	fixup = search_exception_table(regs->cp0_epc);
+	fixup = search_exception_table(exception_epc(regs));
 	if (fixup) {
 		long new_epc;
 		new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
 		printk(KERN_DEBUG "%s: Forwarding exception at [<%lx>] (%lx)\n",
 		       current->comm, regs->cp0_epc, new_epc);
 		regs->cp0_epc = new_epc;
-		return;
+		return 1;
 	}
 
 	die_if_kernel ("Unhandled kernel unaligned access", regs);
 	send_sig(SIGSEGV, current, 1);
-	return;
+
+	return 0;
+
 sigbus:
-	die_if_kernel ("Unhandled kernel unaligned access", regs);
+	die_if_kernel("Unhandled kernel unaligned access", regs);
 	send_sig(SIGBUS, current, 1);
-	return;
+
+	return 0;
+
 sigill:
-	die_if_kernel ("Unhandled kernel unaligned access or invalid instruction", regs);
+	die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
 	send_sig(SIGILL, current, 1);
-	return;
+	return 0;
 }
 
 #ifdef CONFIG_PROC_FS
@@ -394,11 +374,11 @@
 	 * of the CPU after executing the instruction
 	 * in the delay slot of an emulated branch.
 	 */
-
-	if ((unsigned long)regs->cp0_epc == current->thread.dsemul_aerpc) {
-		do_dsemulret(regs);
+	/* Terminate if exception was recognized as a delay slot return */
+	if (do_dsemulret(regs))
 		return;
-	}
+
+	/* Otherwise handle as normal */
 
 	/*
 	 * Did we catch a fault trying to load an instruction?
@@ -409,12 +389,16 @@
 		goto sigbus;
 
 	pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0);
-	if (compute_return_epc(regs))
-		return;
 	if ((current->thread.mflags & MF_FIXADE) == 0)
 		goto sigbus;
 
-	emulate_load_store_insn(regs, regs->cp0_badvaddr, pc);
+	/*
+	 * Do branch emulation only if we didn't forward the exception.
+	 * This is all so but ugly ...
+	 */
+	if (!emulate_load_store_insn(regs, regs->cp0_badvaddr, pc))
+		compute_return_epc(regs);
+
 #ifdef CONFIG_PROC_FS
 	unaligned_instructions++;
 #endif
@@ -422,8 +406,12 @@
 	return;
 
 sigbus:
-	die_if_kernel ("Kernel unaligned instruction access", regs);
+	die_if_kernel("Kernel unaligned instruction access", regs);
 	force_sig(SIGBUS, current);
 
+	/*
+	 * XXX On return from the signal handler we should advance the epc
+	 */
+
 	return;
 }
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/Makefile linux/arch/mips/lib/Makefile
--- linux.orig/arch/mips/lib/Makefile	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/lib/Makefile	2002-08-01 06:42:31.000000000 +0000
@@ -2,10 +2,7 @@
 # Makefile for MIPS-specific library files..
 #
 
-.S.s:
-	$(CPP) $(CFLAGS) $< -o $*.s
-.S.o:
-	$(CC) $(CFLAGS) -c $< -o $*.o
+USE_STANDARD_AS_RULE := true
 
 L_TARGET = lib.a
 
@@ -14,7 +11,7 @@
 				   watch.o strlen_user.o strncpy_user.o \
 				   strnlen_user.o
 
-ifdef CONFIG_CPU_R3000
+ifeq ($(CONFIG_CPU_R3000)$(CONFIG_CPU_TX39XX),y)
   obj-y	+= r3k_dump_tlb.o 
 else
   obj-y	+= dump_tlb.o 
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/csum_partial.S linux/arch/mips/lib/csum_partial.S
--- linux.orig/arch/mips/lib/csum_partial.S	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/lib/csum_partial.S	2002-08-01 06:42:41.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: csum_partial.S,v 1.1 1998/05/04 09:12:52 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/csum_partial_copy.c linux/arch/mips/lib/csum_partial_copy.c
--- linux.orig/arch/mips/lib/csum_partial_copy.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/lib/csum_partial_copy.c	2002-08-01 06:42:44.000000000 +0000
@@ -13,8 +13,6 @@
  *		modify it under the terms of the GNU General Public License
  *		as published by the Free Software Foundation; either version
  *		2 of the License, or (at your option) any later version.
- *
- * $Id: csum_partial_copy.c,v 1.2 1998/09/19 19:16:17 ralf Exp $
  */
 #include <net/checksum.h>
 #include <linux/types.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/dump_tlb.c linux/arch/mips/lib/dump_tlb.c
--- linux.orig/arch/mips/lib/dump_tlb.c	2000-02-25 06:52:30.000000000 +0000
+++ linux/arch/mips/lib/dump_tlb.c	2002-08-01 06:42:27.000000000 +0000
@@ -4,30 +4,47 @@
  * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
  * Copyright (C) 1999 by Silicon Graphics, Inc.
  */
+#include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/string.h>
 
 #include <asm/bootinfo.h>
+#include <asm/cpu.h>
 #include <asm/cachectl.h>
 #include <asm/mipsregs.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 
-#define mips_tlb_entries 48
+static inline const char *msg2str(unsigned int mask)
+{
+	switch (mask) {
+	case PM_4K:	return "4kb";
+	case PM_16K:	return "16kb";
+	case PM_64K:	return "64kb";
+	case PM_256K:	return "256kb";
+#ifndef CONFIG_CPU_VR41XX
+	case PM_1M:	return "1Mb";
+	case PM_4M:	return "4Mb";
+	case PM_16M:	return "16Mb";
+	case PM_64M:	return "64Mb";
+	case PM_256M:	return "256Mb";
+#endif
+	}
+}
 
-void
-dump_tlb(int first, int last)
+void dump_tlb(int first, int last)
 {
 	int	i;
 	unsigned int pagemask, c0, c1, asid;
-	unsigned long entryhi, entrylo0, entrylo1;
+	unsigned long long entrylo0, entrylo1;
+	unsigned long entryhi;
 
 	asid = get_entryhi() & 0xff;
 
-	for(i=first;i<=last;i++)
-	{
+	printk("\n");
+	for(i=first;i<=last;i++) {
 		write_32bit_cp0_register(CP0_INDEX, i);
 		__asm__ __volatile__(
 			".set\tmips3\n\t"
@@ -39,49 +56,45 @@
 			".set\tmips0\n\t");
 		pagemask = read_32bit_cp0_register(CP0_PAGEMASK);
 		entryhi  = read_32bit_cp0_register(CP0_ENTRYHI);
-		entrylo0 = read_32bit_cp0_register(CP0_ENTRYLO0);
-		entrylo1 = read_32bit_cp0_register(CP0_ENTRYLO1);
+		entrylo0 = get_entrylo0();
+		entrylo1 = get_entrylo1();
 
-		/* Unused entries have a virtual address of KSEG0.  */
-		if ((entryhi & 0xffffe000) != 0x80000000
+		/* Unused entries have a virtual address in KSEG0.  */
+		if ((entryhi & 0xf0000000) != 0x80000000
 		    && (entryhi & 0xff) == asid) {
 			/*
 			 * Only print entries in use
 			 */
-			printk("Index: %2d pgmask=%08x ", i, pagemask);
+			printk("Index: %2d pgmask=%s ", i, msg2str(pagemask));
 
 			c0 = (entrylo0 >> 3) & 7;
 			c1 = (entrylo1 >> 3) & 7;
 
-			printk("va=%08lx asid=%08lx"
-			       "  [pa=%06lx c=%d d=%d v=%d g=%ld]"
-			       "  [pa=%06lx c=%d d=%d v=%d g=%ld]",
-			       (entryhi & 0xffffe000),
-			       entryhi & 0xff,
-			       entrylo0 & PAGE_MASK, c0,
+			printk("va=%08lx asid=%02lx\n",
+			       (entryhi & 0xffffe000), (entryhi & 0xff));
+			printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
+			       (entrylo0 << 6) & PAGE_MASK, c0,
 			       (entrylo0 & 4) ? 1 : 0,
 			       (entrylo0 & 2) ? 1 : 0,
-			       (entrylo0 & 1),
-			       entrylo1 & PAGE_MASK, c1,
+			       (entrylo0 & 1));
+			printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
+			       (entrylo1 << 6) & PAGE_MASK, c1,
 			       (entrylo1 & 4) ? 1 : 0,
 			       (entrylo1 & 2) ? 1 : 0,
 			       (entrylo1 & 1));
-			       
+			printk("\n");
 		}
 	}
-	printk("\n");
 
 	set_entryhi(asid);
 }
 
-void
-dump_tlb_all(void)
+void dump_tlb_all(void)
 {
-	dump_tlb(0, mips_tlb_entries - 1);
+	dump_tlb(0, mips_cpu.tlbsize - 1);
 }
 
-void
-dump_tlb_wired(void)
+void dump_tlb_wired(void)
 {
 	int	wired;
 
@@ -125,7 +138,7 @@
 void
 dump_tlb_nonwired(void)
 {
-	dump_tlb(read_32bit_cp0_register(CP0_WIRED), mips_tlb_entries - 1);
+	dump_tlb(read_32bit_cp0_register(CP0_WIRED), mips_cpu.tlbsize - 1);
 }
 
 void
@@ -140,12 +153,20 @@
 	addr = (unsigned int) address;
 
 	printk("Addr                 == %08x\n", addr);
-	printk("tasks->mm.pgd        == %08x\n", (unsigned int) t->mm->pgd);
-
-	page_dir = pgd_offset(t->mm, 0);
+	printk("task                 == %08p\n", t);
+	printk("task->mm             == %08p\n", t->mm);
+	//printk("tasks->mm.pgd        == %08x\n", (unsigned int) t->mm->pgd);
+
+	if (addr > KSEG0)
+		page_dir = pgd_offset_k(0);
+	else
+		page_dir = pgd_offset(t->mm, 0);
 	printk("page_dir == %08x\n", (unsigned int) page_dir);
 
-	pgd = pgd_offset(t->mm, addr);
+	if (addr > KSEG0)
+		pgd = pgd_offset_k(addr);
+	else
+		pgd = pgd_offset(t->mm, addr);
 	printk("pgd == %08x, ", (unsigned int) pgd);
 
 	pmd = pmd_offset(pgd, addr);
@@ -155,7 +176,11 @@
 	printk("pte == %08x, ", (unsigned int) pte);
 
 	page = *pte;
-	printk("page == %08x\n", (unsigned int) pte_val(page));
+#ifdef CONFIG_64BIT_PHYS_ADDR
+	printk("page == %08Lx\n", (unsigned long long) pte_val(page));
+#else
+	printk("page == %08lx\n", (unsigned int) pte_val(page));
+#endif
 
 	val = pte_val(page);
 	if (val & _PAGE_PRESENT) printk("present ");
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/floppy-no.c linux/arch/mips/lib/floppy-no.c
--- linux.orig/arch/mips/lib/floppy-no.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/lib/floppy-no.c	2002-08-01 06:42:39.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: floppy-no.c,v 1.1 1998/05/07 18:38:32 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/floppy-std.c linux/arch/mips/lib/floppy-std.c
--- linux.orig/arch/mips/lib/floppy-std.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/lib/floppy-std.c	2002-08-01 06:42:34.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: floppy-std.c,v 1.2 1999/01/04 16:03:51 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/ide-no.c linux/arch/mips/lib/ide-no.c
--- linux.orig/arch/mips/lib/ide-no.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/lib/ide-no.c	2002-08-01 06:42:39.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: ide-no.c,v 1.2 1998/06/30 00:21:54 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/kbd-no.c linux/arch/mips/lib/kbd-no.c
--- linux.orig/arch/mips/lib/kbd-no.c	2000-05-13 15:29:14.000000000 +0000
+++ linux/arch/mips/lib/kbd-no.c	2002-08-01 06:42:39.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: kbd-no.c,v 1.1 1998/10/28 12:38:14 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/kbd-std.c linux/arch/mips/lib/kbd-std.c
--- linux.orig/arch/mips/lib/kbd-std.c	2001-07-02 20:56:40.000000000 +0000
+++ linux/arch/mips/lib/kbd-std.c	2002-08-01 06:42:27.000000000 +0000
@@ -1,5 +1,4 @@
-/* $Id: kbd-std.c,v 1.2 1999/06/11 14:29:45 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -8,6 +7,7 @@
  *
  * Copyright (C) 1998, 1999 by Ralf Baechle
  */
+#include <linux/config.h>
 #include <linux/ioport.h>
 #include <linux/sched.h>
 #include <linux/pc_keyb.h>
diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/arch/mips/lib/memcpy.S linux/arch/mips/lib/memcpy.S
--- linux.orig/arch/mips/lib/memcpy.S	2001-09-09 17:43:01.000000000 +0000
+++ linux/arch/mips/lib/memcpy.S	2002-08-01 06:42:30.000000000 +0000
@@ -4,407 +4,445 @@
  * for more details.
  *
  * Unified implementation of memcpy, memmove and the __copy_user backend.
- * For __rmemcpy and memmove an exception is always a kernel bug, therefore
- * they're not protected.  In order to keep the exception fixup routine
- * simple all memory accesses in __copy_user to src rsp. dst are stricly
- * incremental.  The fixup routine depends on $at not being changed.
+ *
+ * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Broadcom, Inc.
+ *   memcpy/copy_user author: Mark Vandevoorde
+ *
+ * Mnemonic names for arguments to memcpy/__copy_user
  */
+#include <linux/config.h>
 #include <asm/asm.h>
 #include <asm/offset.h>
 #include <asm/regdef.h>
 
+#define dst a0
+#define src a1
+#define len a2
+
 /*
- * The fixup routine for copy_to_user depends on copying strictly in
- * increasing order.  Gas expands the ulw/usw macros in the wrong order for
- * little endian machines, so we cannot depend on them.
+ * Spec
+ *
+ * memcpy copies len bytes from src to dst and sets v0 to dst.
+ * It assumes that
+ *   - src and dst don't overlap
+ *   - src is readable
+ *   - dst is writable
+ * memcpy uses the standard calling convention
+ *
+ * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
+ * the number of uncopied bytes due to an exception caused by a read or write.
+ * __copy_user assumes that src and dst don't overlap, and that the call is
+ * implementing one of the following:
+ *   copy_to_user
+ *     - src is readable  (no exceptions when reading src)
+ *   copy_from_user
+ *     - dst is writable  (no exceptions when writing dst)
+ * __copy_user uses a non-standard calling convention; see
+ * include/asm-mips/uaccess.h
+ *
+ * When an exception happens on a load, the handler must
+ # ensure that all of the destination buffer is overwritten to prevent
+ * leaking information to user mode programs.
  */
-#ifdef __MIPSEB__
-#define uswL	swl
-#define uswU	swr
-#define ulwL	lwl
-#define ulwU	lwr
-#endif
-#ifdef __MIPSEL__
-#define uswL	swr
-#define uswU	swl
-#define ulwL	lwr
-#define ulwU	lwl
-#endif
 
-#define EX(insn,reg,addr,handler)			\
-9:	insn	reg, addr;				\
-	.section __ex_table,"a"; 			\
-	PTR	9b, handler; 				\
-	.previous
+/*
+ * Implementation
+ */
 
-#define UEX(insn,reg,addr,handler)			\
-9:	insn ## L reg, addr;				\
-10:	insn ## U reg, 3 + addr;			\
-	.section __ex_table,"a"; 			\
-	PTR	9b, handler; 				\
-	PTR	10b, handler; 				\
+/*
+ * The exception handler for loads requires that:
+ *  1- AT contain the address of the byte just past the end of the source
+ *     of the copy,
+ *  2- src_entry <= src < AT, and
+ *  3- (dst - src) == (dst_entry - src_entry),
+ * The _entry suffix denotes values when __copy_user was called.
+ *
+ * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
+ * (2) is met by incrementing src by the number of bytes copied
+ * (3) is met by not doing loads between a pair of increments of dst and src
+ *
+ * The exception handlers for stores adjust len (if necessary) and return.
+ * These handlers do not need to overwrite any data.
+ *
+ * For __rmemcpy and memmove an exception is always a kernel bug, therefore
+ * they're not protected.
+ */
+
+#define EXC(inst_reg,addr,handler)		\
+9:	inst_reg, addr;				\
+	.section __ex_table,"a";		\
+	PTR	9b, handler;			\
 	.previous
 
-/* ascending order, destination aligned  */
-#define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \
-	EX(lw, t0, (offset + 0x00)(src), l_fixup); \
-	EX(lw, t1, (offset + 0x04)(src), l_fixup); \
-	EX(lw, t2, (offset + 0x08)(src), l_fixup); \
-	EX(lw, t3, (offset + 0x0c)(src), l_fixup); \
-	EX(sw, t0, (offset + 0x00)(dst), s_fixup); \
-	EX(sw, t1, (offset + 0x04)(dst), s_fixup); \
-	EX(sw, t2, (offset + 0x08)(dst), s_fixup); \
-	EX(sw, t3, (offset + 0x0c)(dst), s_fixup); \
-	EX(lw, t0, (offset + 0x10)(src), l_fixup); \
-	EX(lw, t1, (offset + 0x14)(src), l_fixup); \
-	EX(lw, t2, (offset + 0x18)(src), l_fixup); \
-	EX(lw, t3, (offset + 0x1c)(src), l_fixup); \
-	EX(sw, t0, (offset + 0x10)(dst), s_fixup); \
-	EX(sw, t1, (offset + 0x14)(dst), s_fixup); \
-	EX(sw, t2, (offset + 0x18)(dst), s_fixup); \
-	EX(sw, t3, (offset + 0x1c)(dst), s_fixup)
-
-/* ascending order, destination unaligned  */
-#define UMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \
-	EX(lw, t0, (offset + 0x00)(src), l_fixup); \
-	EX(lw, t1, (offset + 0x04)(src), l_fixup); \
-	EX(lw, t2, (offset + 0x08)(src), l_fixup); \
-	EX(lw, t3, (offset + 0x0c)(src), l_fixup); \
-	UEX(usw, t0, (offset + 0x00)(dst), s_fixup); \
-	UEX(usw, t1, (offset + 0x04)(dst), s_fixup); \
-	UEX(usw, t2, (offset + 0x08)(dst), s_fixup); \
-	UEX(usw, t3, (offset + 0x0c)(dst), s_fixup); \
-	EX(lw, t0, (offset + 0x10)(src), l_fixup); \
-	EX(lw, t1, (offset + 0x14)(src), l_fixup); \
-	EX(lw, t2, (offset + 0x18)(src), l_fixup); \
-	EX(lw, t3, (offset + 0x1c)(src), l_fixup); \
-	UEX(usw, t0, (offset + 0x10)(dst), s_fixup); \
-	UEX(usw, t1, (offset + 0x14)(dst), s_fixup); \
-	UEX(usw, t2, (offset + 0x18)(dst), s_fixup); \
-	UEX(usw, t3, (offset + 0x1c)(dst), s_fixup)
+/*
+ * In the mips (not mips64) tree, so we can't use doubles
+ */
+#undef USE_DOUBLE
+
+#if defined(USE_DOUBLE)
+
+#define LOAD   ld
+#define LOADL  ldl
+#define LOADR  ldr
+#define STOREL sdl
+#define STORER sdr
+#define STORE  sd
+#define ADD    daddu
+#define SUB    dsubu
+#define SRL    dsrl
+#define SRA    dsra
+#define SLL    dsll
+#define SLLV   dsllv
+#define SRLV   dsrlv
+#define NBYTES 8
+#define LOG_NBYTES 3
+
+#else
+
+#define LOAD   lw
+#define LOADL  lwl
+#define LOADR  lwr
+#define STOREL swl
+#define STORER swr
+#define STORE  sw
+#define ADD    addu
+#define SUB    subu
+#define SRL    srl
+#define SLL    sll
+#define SRA    sra
+#define SLLV   sllv
+#define SRLV   srlv
+#define NBYTES 4
+#define LOG_NBYTES 2
+
+#endif /* USE_DOUBLE */
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define LDFIRST LOADR
+#define LDREST  LOADL
+#define STFIRST STORER
+#define STREST  STOREL
+#define SHIFT_DISCARD SLLV
+#else
+#define LDFIRST LOADL
+#define LDREST  LOADR
+#define STFIRST STOREL
+#define STREST  STORER
+#define SHIFT_DISCARD SRLV
+#endif
+
+#define FIRST(unit) ((unit)*NBYTES)
+#define REST(unit)  (FIRST(unit)+NBYTES-1)
+#define UNIT(unit)  FIRST(unit)
+
+#define ADDRMASK (NBYTES-1)
 
 	.text
 	.set	noreorder
 	.set	noat
 
+/*
+ * A combined memcpy/__copy_user
+ * __copy_user sets len to 0 for success; else to an upper bound of
+ * the number of uncopied bytes.
+ * memcpy sets v0 to dst.
+ */
 	.align	5
 LEAF(memcpy)					/* a0=dst a1=src a2=len */
-	move	v0, a0				/* return value */
+	move	v0, dst				/* return value */
 __memcpy:
-EXPORT(__copy_user)
-	xor	t0, a0, a1
-	andi	t0, t0, 0x3
-	move	t7, a0
-	beqz	t0, can_align
-	 sltiu	t8, a2, 0x8
-
-	b	memcpy_u_src			# bad alignment
-	 move	t2, a2
-
-can_align:
-	bnez	t8, small_memcpy		# < 8 bytes to copy
-	 move	t2, a2
-
-	beqz	a2, out
-	 andi	t8, a1, 0x1
-
-hword_align:
-	beqz	t8, word_align
-	 andi	t8, a1, 0x2
-
-	EX(lb, t0, (a1), l_fixup)
-	subu	a2, a2, 0x1
-	EX(sb, t0, (a0), s_fixup)
-	addu	a1, a1, 0x1
-	addu	a0, a0, 0x1
-	andi	t8, a1, 0x2
-
-word_align:
-	beqz	t8, dword_align
-	 sltiu	t8, a2, 56
-	
-	EX(lh, t0, (a1), l_fixup)
-	subu	a2, a2, 0x2
-	EX(sh, t0, (a0), s_fixup)
-	sltiu	t8, a2, 56
-	addu	a0, a0, 0x2
-	addu	a1, a1, 0x2
-
-dword_align:
-	bnez	t8, do_end_words
-	 move	t8, a2
-
-	andi	t8, a1, 0x4
-	beqz	t8, qword_align
-	 andi	t8, a1, 0x8
-
-	EX(lw, t0, 0x00(a1), l_fixup)
-	subu	a2, a2, 0x4
-	EX(sw, t0, 0x00(a0), s_fixup)
-	addu	a1, a1, 0x4
-	addu	a0, a0, 0x4
-	andi	t8, a1, 0x8
-
-qword_align:
-	beqz	t8, oword_align
-	 andi	t8, a1, 0x10
-
-	EX(lw, t0, 0x00(a1), l_fixup)
-	EX(lw, t1, 0x04(a1), l_fixup)
-	subu	a2, a2, 0x8
-	EX(sw, t0, 0x00(a0), s_fixup)
-	EX(sw, t1, 0x04(a0), s_fixup)
-	addu	a1, a1, 0x8
-	andi	t8, a1, 0x10
-	addu	a0, a0, 0x8
-
-oword_align:
-	beqz	t8, begin_movement
-	 srl	t8, a2, 0x7
-
-	EX(lw, t3, 0x00(a1), l_fixup)
-	EX(lw, t4, 0x04(a1), l_fixup)
-	EX(lw, t0, 0x08(a1), l_fixup)
-	EX(lw, t1, 0x0c(a1), l_fixup)
-	EX(sw, t3, 0x00(a0), s_fixup)
-	EX(sw, t4, 0x04(a0), s_fixup)
-	EX(sw, t0, 0x08(a0), s_fixup)
-	EX(sw, t1, 0x0c(a0), s_fixup)
-	subu	a2, a2, 0x10
-	addu	a1, a1, 0x10
-	srl	t8, a2, 0x7
-	addu	a0, a0, 0x10
-
-begin_movement:
-	beqz	t8, 0f
-	 andi	t2, a2, 0x40
-
-move_128bytes:
-	MOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4)
-	MOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4)
-	MOVE_BIGCHUNK(a1, a0, 0x40, t0, t1, t3, t4)
-	MOVE_BIGCHUNK(a1, a0, 0x60, t0, t1, t3, t4)
-	subu	t8, t8, 0x01
-	addu	a1, a1, 0x80
-	bnez	t8, move_128bytes
-	 addu	a0, a0, 0x80
-
-0:
-	beqz	t2, 1f
-	 andi	t2, a2, 0x20
-
-move_64bytes:
-	MOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4)
-	MOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4)
-	addu	a1, a1, 0x40
-	addu	a0, a0, 0x40
-
+FEXPORT(__copy_user)
+	/*
+	 * Note: dst & src may be unaligned, len may be 0
+	 * Temps
+	 */
+#define rem t8
+
+	/*
+	 * The "issue break"s below are very approximate.
+	 * Issue delays for dcache fills will perturb the schedule, as will
+	 * load queue full replay traps, etc.
+	 *
+	 * If len < NBYTES use byte operations.
+	 */
+	PREF(	0, 0(src) )
+	PREF(	1, 0(dst) )
+	sltu	t2, len, NBYTES
+	and	t1, dst, ADDRMASK
+	PREF(	0, 1*32(src) )
+	PREF(	1, 1*32(dst) )
+	bnez	t2, copy_bytes_checklen
+	 and	t0, src, ADDRMASK
+	PREF(	0, 2*32(src) )
+	PREF(	1, 2*32(dst) )
+	bnez	t1, dst_unaligned
+	 nop
+	bnez	t0, src_unaligned_dst_aligned
+	/*
+	 * use delay slot for fall-through
+	 * src and dst are aligned; need to compute rem
+	 */
+both_aligned:
+	 SRL	t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
+	beqz	t0, cleanup_both_aligned # len < 8*NBYTES
+	 and	rem, len, (8*NBYTES-1)	 # rem = len % (8*NBYTES)
+	PREF(	0, 3*32(src) )
+	PREF(	1, 3*32(dst) )
+	.align	4
 1:
-	beqz	t2, do_end_words
-	 andi	t8, a2, 0x1c
-
-move_32bytes:
-	MOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4)
-	andi	t8, a2, 0x1c
-	addu	a1, a1, 0x20
-	addu	a0, a0, 0x20
-
-do_end_words:
-	beqz	t8, maybe_end_cruft
-	 srl	t8, t8, 0x2
-
-end_words:
-	EX(lw, t0, (a1), l_fixup)
-	subu	t8, t8, 0x1
-	EX(sw, t0, (a0), s_fixup)
-	addu	a1, a1, 0x4
-	bnez	t8, end_words
-	 addu	a0, a0, 0x4
-
-maybe_end_cruft:
-	andi	t2, a2, 0x3
-
-small_memcpy:
-	beqz	t2, out
-	 move	a2, t2
-
-end_bytes:
-	EX(lb, t0, (a1), l_fixup)
-	subu	a2, a2, 0x1
-	EX(sb, t0, (a0), s_fixup)
-	addu	a1, a1, 0x1
-	bnez	a2, end_bytes
-	 addu	a0, a0, 0x1
-
-out:	jr	ra
-	 move	a2, zero
-
-/* ------------------------------------------------------------------------- */
+EXC(	LOAD	t0, UNIT(0)(src),	l_exc)
+EXC(	LOAD	t1, UNIT(1)(src),	l_exc_copy)
+EXC(	LOAD	t2, UNIT(2)(src),	l_exc_copy)
+EXC(	LOAD	t3, UNIT(3)(src),	l_exc_copy)
+	SUB	len, len, 8*NBYTES
+EXC(	LOAD	t4, UNIT(4)(src),	l_exc_copy)
+EXC(	LOAD	t7, UNIT(5)(src),	l_exc_copy)
+EXC(	STORE	t0, UNIT(0)(dst),	s_exc_p8u)
+EXC(	STORE	t1, UNIT(1)(dst),	s_exc_p7u)
+EXC(	LOAD	t0, UNIT(6)(src),	l_exc_copy)
+EXC(	LOAD	t1, UNIT(7)(src),	l_exc_copy)
+	ADD	src, src, 8*NBYTES
+	ADD	dst, dst, 8*NBYTES
+EXC(	STORE	t2, UNIT(-6)(dst),	s_exc_p6u)
+EXC(	STORE	t3, UNIT(-5)(dst),	s_exc_p5u)
+EXC(	STORE	t4, UNIT(-4)(dst),	s_exc_p4u)
00000(src),	l_ex	t0,000000000(src	l_exc_copy)
+EX------D	t1, UNIT(7)_intr_handler, 0,endif
-2E	t3, UNIT(-5)(dsOAD	t1 -UNIT(7)(sndlea2, 0x12OAD	t
+		 nop
+		ENO(kernel_entry)
 
 
 #iffinition from <as , UNIT(7)_intr_handler, 0,endif
-2E	t3, URIT(-5)(C(	STORE	t3&
-
-move_LOAD	t0, UND	t0,#+EXu might also (	STORE	t4, UNIT(-4)(dst),	s_exc_p4llllllllD	t0,#+E_NOFPUEX))
 	e_LO4)(racheIT(6t8, a1, 0x2	-
-	EX(lb, t0, (a1), l_fixup)
-	subu	a2, a2, 0x1
-	EX(sb, t0,  a2B, s_fixuourthA als*/
+STORE	t7,(	1,A_DEBU, 0x12)(ra_XC(	Lt0,  a2B, 
 
 #ia2B, s_(7)_intr_handler, 0,endif
-2E	t3, UNIT(-5)(dsOAD	t1 -UNIT(7)(sndlea2, 0x l_fix     0x1
-	EX(sb, if
-2E	t3,
 
 #ia2B, so)(dsOAD	t1 -UNIT(2)
-	 sltiuIGCHUNK( if we0, (a0), s_LO4)(rachA_DEBU, 0x12)(r2	-
), l_ou§up/
-	subu	a2,,a2, 0x1src)hany)
+EXC(	LN). */
-	3, URIT(-5)(C(	STORE	t3&
-
-move_LOAD	t0, UND	t0<4+EXu migst also (	STORE	t1, UNIT(-4)(dst),	s_exc_p4lll
-	EX(13XC(	Lt0,  a2B, 0x12OAD	t
+	t nop
+		ENO(kernel_entry)
 
 
 #iffinitnsmtc¨ð2E	t3_(7)_intrdhandler, 0,endif
-2E	t3a2B, so)(dsOAD	rc)hany)
+EXC(	LNwe0, (a0), s (a0), s  a0)(	LNwe0, ou§up/
-	susrst;iE	t1, UNIc, 8*NBYTES
a1, 0x40
-	md	3, UR,endif
-2E	OFF_STATE (SASTATE (SASy)
+EXC(	LNwe0, (a0), s (a0), s  a0)(	LNob0, ou§up/
-	susrst;iE	t18 UNIc* Copy all non-order, non-type flags */
-
	t nop
+		 PRIDFOll pertebndif
-2E	enum fixed_addS
+EXC(	LB+	   +(unsigned int) (bootDeviceBase + b),	sBN
+		 PRIDy)
+DLer(from->si_pid, &to->si, 0,en	 PR-2E	t3n2Jinstr(SASTATE (SAmamap_nbndif
-NIT(7)_intr_han& src may;' + b)& srcPR-2bndis
-	t0<4+EXurc ms0)(	LNob0, ouMD stor(	L iAD	t
+el, pemfmon is DBU, 0 (a0)rc 11&`	 PR	t0<4+EXu0, UND	t0 dst),	s_exc_i| PC_CNTRL_EN0 NTRL_CN RL_EN0,access", regsxed_addS
+EXC(	t0<4+t<5initioe from <a,enda0)rc 11&`	 PR	t0el, pemfmon is se byte operadions.
+	 */
+	PSEF(	0, 0(src) )
+	PREF(	1,s0 <as , UNIT s */
-
+:5&
-   # deret,+EXurc ms0)(	LNobug ouMD stor(	L iAD	t
+el, pemfmon 